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-------------------------------------------------------------------------------
--
-- Title : inv
-- Design : lab2
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : inv.vhd
-- Generated : Fri Oct 3 17:29:58 2014
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {inv} architecture {inv}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity inv is
port(
A : in STD_LOGIC;
Z : out STD_LOGIC
);
end inv;
--}} End of automatically maintained section
architecture inv of inv is
begin
Z <= not A;
end inv;
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS DARTMOUTH
-- Engineer: CHRISTOPHER PARKS ([email protected])
--
-- Create Date: 14:45:47 03/31/2016
-- Design Name:
-- Module Name: word_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity word_unit is
Port ( DATAIN : in STD_LOGIC_VECTOR (15 downto 0);
IMMAddr : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR(3 downto 0); -- Pass OP(2) to this (OP=0=Load, OP=1=Write)
RESULT : out STD_LOGIC_VECTOR (15 downto 0);
DST_ADR : out STD_LOGIC_VECTOR (7 downto 0);
STORE_DATA : out STD_LOGIC_VECTOR (15 downto 0));
end word_unit;
architecture Combinational of word_unit is
signal WREN : STD_LOGIC_VECTOR(0 downto 0) := "0";
begin
DST_ADR <= IMMAddr;
STORE_DATA <= DATAIN;
WREN <= "0" when OP = x"9" else -- x"9" is load word
"1" when OP = x"A"; -- x"A" is store word
DATAMEMORY : entity work.DATAMEM port map(ADDRA => IMMAddr,
DINA => DATAIN,
WEA => WREN, -- Write enable
CLKA => CLK,
DOUTA => RESULT);
-- When OP = 1 then WRITE is enabled, IMMAddr gives us the address to write to, DATAIN gives us the data to write. RESULT will soon show data written if untouched
-- When OP = 0 then WRITE is disabled, DATAIN is ignored, IMMAddr gives us the address to read from, and RESULT is set to the RESULT.
end Combinational;
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS DARTMOUTH
-- Engineer: CHRISTOPHER PARKS ([email protected])
--
-- Create Date: 14:45:47 03/31/2016
-- Design Name:
-- Module Name: word_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity word_unit is
Port ( DATAIN : in STD_LOGIC_VECTOR (15 downto 0);
IMMAddr : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR(3 downto 0); -- Pass OP(2) to this (OP=0=Load, OP=1=Write)
RESULT : out STD_LOGIC_VECTOR (15 downto 0);
DST_ADR : out STD_LOGIC_VECTOR (7 downto 0);
STORE_DATA : out STD_LOGIC_VECTOR (15 downto 0));
end word_unit;
architecture Combinational of word_unit is
signal WREN : STD_LOGIC_VECTOR(0 downto 0) := "0";
begin
DST_ADR <= IMMAddr;
STORE_DATA <= DATAIN;
WREN <= "0" when OP = x"9" else -- x"9" is load word
"1" when OP = x"A"; -- x"A" is store word
DATAMEMORY : entity work.DATAMEM port map(ADDRA => IMMAddr,
DINA => DATAIN,
WEA => WREN, -- Write enable
CLKA => CLK,
DOUTA => RESULT);
-- When OP = 1 then WRITE is enabled, IMMAddr gives us the address to write to, DATAIN gives us the data to write. RESULT will soon show data written if untouched
-- When OP = 0 then WRITE is disabled, DATAIN is ignored, IMMAddr gives us the address to read from, and RESULT is set to the RESULT.
end Combinational;
|
--!
--! \file osif_core.vhd
--!
--! OSIF logic and interface to IPIF
--!
--! The osif_core contains processes for OS request handling. Also, it
--! instantiates the DCR slave module, which manages communication
--! between the CPU and the OSIF.
--!
--! There are two sets of registers, one for each direction (logic to bus
--! and bus to logic). Each set has the a register for command, data,
--! and extended data; the bus to logic set has another handshake register
--! indicating an incoming request from the DCR bus.
--!
--! Communication with the user task goes through the osif_task2os and
--! osif_os2task data structures, which are converted to std_logic_vectors
--! at the module interface, because XPS cannot handle VHDL records. An
--! incoming request from a task to perform an operating system call
--! is signalled by the request line of the task2os record. Requests can be
--! divided into two categories:
--!
--! - those that are handled in hardware without microprocessor
--! involvement (like shared memory accesses), and
--! - those that have to be handled in the microprocessor
--!
--! The first are handled directly within osif_core (and its submodules),
--! whereas the latter cause an interrupt to the microprocessor, preempt
--! any running processes there and wake up a software thread, which then
--! acts on behalf of the hardware thread.
--!
--!
--!
--!
--!
--! Memory bus interface fifo_manager
--! Memory (master/slave)
--! Bus <----------------------------+ ^
--! (e.g. PLB) | |
--! | +----------------+
--! _______|____|____
--! | |
--! clk, reset ------------------>| command_decoder |
--! |_________________|
--! | |
--! | +----------------+
--! Hardware | _____|__________
--! Thread <-----------------------------+ | |
--! Hardware Thread Control Interface | dcr_slave_regs |
--! |________________|
--! ^
--! |
--! V
--! D C R
--! \author Enno Luebbers <[email protected]>
--! \date 08.12.2008
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major changes
-- 01.08.2006 Enno Luebbers File created (from opb_reconos_slot_v1_00_c)
-- 03.08.2006 Enno Luebbers Added PLB bus master (moved to v1.01.a),
-- removed BRAM interface
-- 04.08.2006 Enno Luebbers moved user_logic to toplevel
-- 07.08.2006 Enno Luebbers moved logic to separate modules
-- (bus_master, bus_slave_regs)
-- xx.10.2007 Enno Luebbers added local FIFO manager
-- 23.11.2007 Enno Luebbers moved slave registers to DCR
-- 08.12.2008 Enno Luebbers modularized (moved memory bus controller
-- to separate module)
-- 10.12.2008 Enno Luebbers moved and renamed from user_logic to osif_core
--
--*************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library proc_common_v1_00_b;
--use proc_common_v1_00_b.proc_common_pkg.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
library osif_core_v2_03_a;
use osif_core_v2_03_a.all;
entity osif_core is
generic
(
-- Bus protocol parameters
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
C_NUM_CE : integer := 2;
C_BURST_AWIDTH : integer := 13; -- 1024 x 64 Bit = 8192 Bytes = 2^13 Bytes
C_THREAD_RESET_CYCLES : natural := 10; -- number of cycles the thread reset is held
C_FIFO_DWIDTH : integer := 32;
C_BURSTLEN_WIDTH : integer := 5; -- max 16x64 bit bursts
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_TLB_TAG_WIDTH : integer := 20;
C_TLB_DATA_WIDTH : integer := 21;
C_ENABLE_MMU : boolean := true;
C_MMU_STAT_REGS : boolean := false;
C_DCR_ILA : integer := 0 -- 0: no debug ILA, 1: include debug chipscope ILA for DCR debugging
);
port
(
sys_clk : in std_logic;
sys_reset : in std_logic;
interrupt : out std_logic;
busy : out std_logic;
blocking : out std_logic;
-- task interface
task_clk : out std_logic;
task_reset : out std_logic;
osif_os2task_vec : out std_logic_vector(0 to C_OSIF_OS2TASK_REC_WIDTH-1);
osif_task2os_vec : in std_logic_vector(0 to C_OSIF_TASK2OS_REC_WIDTH-1);
-- FIFO manager access signals
-- left (read) FIFO
o_fifomgr_read_remove : out std_logic;
i_fifomgr_read_data : in std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifomgr_read_wait : in std_logic;
-- right (write) FIFO
o_fifomgr_write_add : out std_logic;
o_fifomgr_write_data : out std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifomgr_write_wait : in std_logic;
-- memory access signals
o_mem_singleData : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
i_mem_singleData : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
o_mem_localAddr : out std_logic_vector(0 to C_AWIDTH-1);
o_mem_targetAddr : out std_logic_vector(0 to C_AWIDTH-1);
o_mem_singleRdReq : out std_logic;
o_mem_singleWrReq : out std_logic;
o_mem_burstRdReq : out std_logic;
o_mem_burstWrReq : out std_logic;
o_mem_burstLen : out std_logic_vector(0 to C_BURSTLEN_WIDTH-1);
i_mem_busy : in std_logic;
i_mem_rdDone : in std_logic;
i_mem_wrDone : in std_logic;
-- bus macro control
o_bm_enable : out std_logic;
-- tlb interface
i_tlb_rdata : in std_logic_vector(C_TLB_DATA_WIDTH - 1 downto 0);
o_tlb_wdata : out std_logic_vector(C_TLB_DATA_WIDTH - 1 downto 0);
o_tlb_tag : out std_logic_vector(C_TLB_TAG_WIDTH - 1 downto 0);
i_tlb_match : in std_logic;
o_tlb_we : out std_logic;
i_tlb_busy : in std_logic;
o_tlb_request : out std_logic;
-- dcr bus protocol ports
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
i_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic;
i_dcrICON : in std_logic_vector(35 downto 0)
);
end entity osif_core;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of osif_core is
--#################################################################################################################
-------
-- OS signals
-------
-- between os and task
signal osif_os2task : osif_os2task_t;
signal osif_task2os : osif_task2os_t;
-- FIXME: is there a better way than a handshake register?
signal os2task_newcmd : std_logic := '0';
signal request_blocking : std_logic := '0';
signal request_unblocking : std_logic := '0';
-- signal os2task_reset : std_logic := '0';
signal task2os_error : std_logic := '0'; -- FIXME: this is being ignored
-- dirty flag signals indicating unread data in read registers
signal slv_busy : std_logic;
signal post_sw_request : std_logic;
--
signal cdec_post : std_logic;
signal mmu_post : std_logic;
signal mmu_exception : std_logic;
signal cdec_command : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := (others => '0'); -- task2os command
signal cdec_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0'); -- task2os data
signal cdec_datax : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0'); -- task2os data
---------
-- slave register signals (put on DCR)
---------
signal slv_bus2osif_command : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1);
signal slv_bus2osif_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal slv_bus2osif_done : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal slv_osif2bus_command : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := (others => '0'); -- task2os command
signal slv_osif2bus_flags : std_logic_vector(0 to C_OSIF_FLAGS_WIDTH-1);
signal slv_osif2bus_saved_state_enc : std_logic_vector(0 to C_OSIF_STATE_ENC_WIDTH-1);
signal slv_osif2bus_saved_step_enc : std_logic_vector(0 to C_OSIF_STEP_ENC_WIDTH-1);
signal slv_osif2bus_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0'); -- task2os data
signal slv_osif2bus_datax : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0'); -- task2os data
signal slv_osif2bus_signature : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0'); -- hwthread signature
---------
-- status registers
---------
signal thread_init_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1); -- thread data (passed at initialization)
---------
-- local FIFO handles (used for FIFO message routing)
---------
signal fifo_read_handle : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal fifo_write_handle : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
---------
-- thread reset counter
---------
signal reset_counter : natural range 0 to C_THREAD_RESET_CYCLES-1 := C_THREAD_RESET_CYCLES-1;
signal request_reset : std_logic;
signal thread_reset_i : std_logic;
---------
-- signals for cooperative multithreading
---------
signal thread_is_resuming : std_logic;
signal yield_request : std_logic; -- request from OS to yield
signal yield_flag : std_logic; -- if '!', thread can yield
signal saved_state_enc : reconos_state_enc_t;
signal saved_step_enc : reconos_step_enc_t;
signal resume_state_enc : reconos_state_enc_t;
signal resume_step_enc : reconos_step_enc_t;
-- mmu diagnosis
signal mmu_tlb_miss_count : std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
signal mmu_tlb_hit_count : std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
signal mmu_page_fault_count : std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
signal mmu_state_fault : std_logic;
signal mmu_state_access_violation : std_logic;
-- mmu configuration and state
signal mmu_setpgd : std_logic;
signal mmu_repeat : std_logic;
signal mmu_config_data : std_logic_vector(0 to 31);
signal cdec_srrq : std_logic;
signal cdec_swrq : std_logic;
signal cdec_brrq : std_logic;
signal cdec_bwrq : std_logic;
signal cdec_laddr : std_logic_vector(31 downto 0);
signal cdec_raddr : std_logic_vector(31 downto 0);
signal mmu_data : std_logic_vector(31 downto 0);
signal mmu_busy : std_logic;
signal mmu_wrDone : std_logic;
signal mmu_rdDone : std_logic;
begin
enable_mmu : if C_ENABLE_MMU generate
handle_mmu_exception : process(sys_clk, sys_reset, mmu_exception)
variable step : integer range 0 to 1;
begin
if sys_reset = '1' then
mmu_post <= '0';
step := 0;
elsif rising_edge(sys_clk) then
case step is
when 0 =>
if mmu_exception = '1' then
mmu_post <= '1';
step := 1;
end if;
when 1 =>
mmu_post <= '0';
if mmu_exception = '0' then
step := 0;
end if;
end case;
end if;
end process;
post_mux : process(mmu_state_fault, mmu_exception,cdec_command, cdec_data, cdec_datax, mmu_data, cdec_post, mmu_post)
begin
if mmu_exception = '0' then
slv_osif2bus_command <= cdec_command;
slv_osif2bus_data <= cdec_data;
slv_osif2bus_datax <= cdec_datax;
post_sw_request <= cdec_post;
else
if mmu_state_fault = '1' then
slv_osif2bus_command <= OSIF_CMD_MMU_FAULT;
else
slv_osif2bus_command <= OSIF_CMD_MMU_ACCESS_VIOLATION;
end if;
slv_osif2bus_data <= mmu_data;
slv_osif2bus_datax <= X"22221111";
post_sw_request <= mmu_post;
end if;
end process;
mmu_exception <= mmu_state_fault or mmu_state_access_violation;
--post_sw_request <= cdec_post or mmu_post;
interrupt <= post_sw_request or cdec_post;
i_mmu : entity osif_core_v2_03_a.mmu
generic map
(
--C_BASEADDR => C_BASEADDR,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_MMU_STAT_REGS => C_MMU_STAT_REGS
)
port map
(
clk => sys_clk,
rst => sys_reset,
-- incoming memory interface
i_swrq => cdec_swrq, --
i_srrq => cdec_srrq, --
i_bwrq => cdec_bwrq, --
i_brrq => cdec_brrq, --
i_addr => cdec_raddr,--
i_laddr => cdec_laddr,--
o_data => mmu_data, --
o_busy => mmu_busy,--
o_rdone => mmu_rdDone,--
o_wdone => mmu_wrDone,--
-- outgoing memory interface
o_swrq => o_mem_singleWrReq,
o_srrq => o_mem_singleRdReq,
o_bwrq => o_mem_burstWrReq,
o_brrq => o_mem_burstRdReq,
o_addr => o_mem_targetAddr,
o_laddr => o_mem_localAddr,
i_data => i_mem_singleData,
i_busy => i_mem_busy,
i_rdone => i_mem_rdDone,
i_wdone => i_mem_wrDone,
-- configuration interface
i_cfg => mmu_config_data,
i_setpgd => mmu_setpgd,
i_repeat => mmu_repeat,
-- interrupts
o_state_fault => mmu_state_fault,
o_state_access_violation => mmu_state_access_violation,
-- tlb interface
i_tlb_match => i_tlb_match,
i_tlb_busy => i_tlb_busy,
--i_tlb_wdone => i_tlb_wdone,
o_tlb_we => o_tlb_we,
i_tlb_data => i_tlb_rdata,
o_tlb_data => o_tlb_wdata,
o_tlb_tag => o_tlb_tag,
o_tlb_request => o_tlb_request,
-- diagnosis
o_tlb_miss_count => mmu_tlb_miss_count,
o_tlb_hit_count => mmu_tlb_hit_count,
o_page_fault_count => mmu_page_fault_count
);
end generate;
disable_mmu : if not C_ENABLE_MMU generate
interrupt <= cdec_post;
o_mem_singleWrReq <= cdec_swrq;
o_mem_singleRdReq <= cdec_srrq;
o_mem_burstWrReq <= cdec_bwrq;
o_mem_burstRdReq <= cdec_brrq;
o_mem_targetAddr <= cdec_raddr;
o_mem_localAddr <= cdec_laddr;
mmu_data <= i_mem_singleData;
mmu_busy <= i_mem_busy;
mmu_rdDone <= i_mem_rdDone;
mmu_wrDone <= i_mem_wrDone;
mmu_config_data <= (others => '0');
mmu_setpgd <= '0';
mmu_repeat <= '0';
mmu_state_fault <= '0';
mmu_state_access_violation <= '0';
mmu_tlb_miss_count <= (others => '0');
mmu_tlb_hit_count <= (others => '0');
mmu_page_fault_count <= (others => '0');
o_tlb_we <= '0';
o_tlb_wdata <= (others => '0');
o_tlb_tag <= (others => '0');
o_tlb_request <= '0';
end generate;
-- ################### MODULE INSTANTIATIONS ####################
-----------------------------------------------------------------------
-- dcr_slave_regs_inst: DCR bus slave instatiation
--
-- Handles access to the various registers.
-- NOTE: While slv_bus2osif_* signals are latched by bus_slave_regs,
-- the slv_osif2bus_* signals MUST BE STABLE until the transaction
-- is complete (busy goes low for s/w OS requests or the shm bus
-- bus master transaction completes).
-----------------------------------------------------------------------
dcr_slave_regs_inst : entity osif_core_v2_03_a.dcr_slave_regs
generic map (
C_DCR_BASEADDR => C_DCR_BASEADDR,
C_DCR_HIGHADDR => C_DCR_HIGHADDR,
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH,
C_NUM_REGS => 4,
C_ENABLE_MMU => C_ENABLE_MMU,
C_INCLUDE_ILA => C_DCR_ILA
)
port map (
clk => sys_clk,
reset => thread_reset_i, --sys_reset,
o_dcrAck => o_dcrAck,
o_dcrDBus => o_dcrDBus,
i_dcrABus => i_dcrABus,
i_dcrDBus => i_dcrDBus,
i_dcrRead => i_dcrRead,
i_dcrWrite => i_dcrWrite,
i_dcrICON => i_dcrICON,
-- user registers
i_osif2bus_command => slv_osif2bus_command,
i_osif2bus_flags => slv_osif2bus_flags,
i_osif2bus_saved_state_enc => slv_osif2bus_saved_state_enc,
i_osif2bus_saved_step_enc => slv_osif2bus_saved_step_enc,
i_osif2bus_data => slv_osif2bus_data,
i_osif2bus_datax => slv_osif2bus_datax,
i_osif2bus_signature => slv_osif2bus_signature,
o_bus2osif_command => slv_bus2osif_command,
o_bus2osif_data => slv_bus2osif_data,
o_bus2osif_done => slv_bus2osif_done,
i_tlb_miss_count => mmu_tlb_miss_count,
i_tlb_hit_count => mmu_tlb_hit_count,
i_page_fault_count => mmu_page_fault_count,
-- additional user interface
o_newcmd => os2task_newcmd,
i_post => post_sw_request,
o_busy => slv_busy
--o_interrupt => interrupt
);
-----------------------------------------------------------------------
-- command_decoder_inst: command decoder instatiation
--
-- Handles decoding the commands from the HW thread.
-- NOTE: the command decoder is completely asynchronous. It also
-- handles the setting and releasing of the osif_os2task.busy
-- and .blocking signals.
-----------------------------------------------------------------------
command_decoder_inst : entity osif_core_v2_03_a.command_decoder
generic map (
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
C_BURST_AWIDTH => C_BURST_AWIDTH,
C_FIFO_DWIDTH => C_FIFO_DWIDTH,
C_BURSTLEN_WIDTH => C_BURSTLEN_WIDTH
)
port map (
i_clk => sys_clk,
i_reset => thread_reset_i, -- Bus2IP_Reset,
i_osif => osif_task2os,
o_osif => osif_os2task,
o_sw_request => cdec_post,
i_request_blocking => request_blocking,
i_release_blocking => request_unblocking,
i_init_data => thread_init_data,
o_bm_my_addr => cdec_laddr,
o_bm_target_addr => cdec_raddr,
o_bm_read_req => cdec_srrq,
o_bm_write_req => cdec_swrq,
o_bm_burst_read_req => cdec_brrq,
o_bm_burst_write_req => cdec_bwrq,
o_bm_burst_length => o_mem_burstLen,
i_bm_busy => mmu_busy,
i_bm_read_done => mmu_rdDone,
i_bm_write_done => mmu_wrDone,
i_slv_busy => slv_busy,
i_slv_bus2osif_command => slv_bus2osif_command,
i_slv_bus2osif_data => slv_bus2osif_data,
i_slv_bus2osif_shm => mmu_data,
o_slv_osif2bus_command => cdec_command,
o_slv_osif2bus_data => cdec_data,
o_slv_osif2bus_datax => cdec_datax,
o_slv_osif2bus_shm => o_mem_singleData,
o_hwthread_signature => slv_osif2bus_signature,
o_fifo_read_remove => o_fifomgr_read_remove,
i_fifo_read_data => i_fifomgr_read_data,
i_fifo_read_wait => i_fifomgr_read_wait,
o_fifo_write_add => o_fifomgr_write_add,
o_fifo_write_data => o_fifomgr_write_data,
i_fifo_write_wait => i_fifomgr_write_wait,
i_fifo_read_handle => fifo_read_handle,
i_fifo_write_handle => fifo_write_handle,
i_resume => thread_is_resuming,
i_yield => yield_request,
o_yield => yield_flag,
o_saved_state_enc => saved_state_enc,
o_saved_step_enc => saved_step_enc,
i_resume_state_enc => resume_state_enc,
i_resume_step_enc => resume_step_enc
);
-- ################### CONCURRENT ASSIGNMENTS ####################
-----------------------------------------------------------------------
-- User task signal routing
--
-- The user task is supplied with a dedicated clock and reset signal,
-- just in case we want to use them later.
-----------------------------------------------------------------------
task_clk <= sys_clk; --Bus2IP_Clk;
thread_reset_i <= '1' when reset_counter > 0 else '0';
task_reset <= thread_reset_i;
-- OSIF record to vector conversion (because EDK cannot handle records)
osif_os2task_vec <= to_std_logic_vector(osif_os2task);
osif_task2os <= to_osif_task2os_t(osif_task2os_vec);
-- FIXME: ignoring task error
task2os_error <= osif_task2os.error;
-- flags and yield control
slv_osif2bus_flags <= yield_flag & "0000000";
slv_osif2bus_saved_state_enc <= saved_state_enc;
slv_osif2bus_saved_step_enc <= saved_step_enc;
-- drive debug signals
busy <= osif_os2task.busy;
blocking <= osif_os2task.blocking;
-- ################### PROCESSES ####################
-----------------------------------------------------------------------
-- handle_os2task_response: Handles incoming OS commands
--
-- Especially the OSIF_CMD_UNBLOCK command, which signals that a
-- blocking OS call has returned.
-----------------------------------------------------------------------
-- FIXME: does this have to be synchronous?
handle_os2task_response : process(sys_clk, sys_reset)
begin
if sys_reset = '1' then
request_blocking <= '0';
request_unblocking <= '0';
request_reset <= '0';
o_bm_enable <= '0'; -- bus macros are disabled by default!
thread_init_data <= (others => '0');
thread_is_resuming <= '0'; -- per default, the thread is not resumed, but created/started
resume_state_enc <= (others => '0');
resume_step_enc <= (others => '0');
yield_request <= '0';
elsif rising_edge(sys_clk) then
-- also reset everything on a synchronous thread_reset!
if thread_reset_i = '1' then
request_blocking <= '0';
request_unblocking <= '0';
request_reset <= '0';
-- o_bm_enable <= '0'; -- do not disable bus macros on a thread reset (would break signature read)
thread_init_data <= (others => '0');
thread_is_resuming <= '0'; -- per default, the thread is not resumed, but created/started
resume_state_enc <= (others => '0');
resume_step_enc <= (others => '0');
-- yield_request <= '0'; -- yield_request is persistent across resets!
end if;
request_blocking <= '0';
request_unblocking <= '0';
request_reset <= '0';
mmu_setpgd <= '0';
mmu_repeat <= '0';
if os2task_newcmd = '1' then
case slv_bus2osif_command(0 to C_OSIF_CMD_WIDTH-1) is
when OSIF_CMD_UNBLOCK =>
request_unblocking <= '1';
when OSIF_CMD_SET_INIT_DATA =>
thread_init_data <= slv_bus2osif_data;
when OSIF_CMD_RESET =>
request_blocking <= '1';
request_reset <= '1';
when OSIF_CMD_BUSMACRO =>
if slv_bus2osif_data = OSIF_DATA_BUSMACRO_DISABLE then -- disable
o_bm_enable <= '0';
else
o_bm_enable <= '1'; -- enable
end if;
when OSIF_CMD_SET_FIFO_READ_HANDLE =>
fifo_read_handle <= slv_bus2osif_data;
when OSIF_CMD_SET_FIFO_WRITE_HANDLE =>
fifo_write_handle <= slv_bus2osif_data;
when OSIF_CMD_SET_RESUME_STATE =>
resume_state_enc <= slv_bus2osif_data(0 to C_OSIF_STATE_ENC_WIDTH-1);
resume_step_enc <= slv_bus2osif_data(C_OSIF_STATE_ENC_WIDTH to C_OSIF_STATE_ENC_WIDTH+C_OSIF_STEP_ENC_WIDTH-1);
thread_is_resuming <= '1';
-- FIXME: do we need this?
when OSIF_CMD_CLEAR_RESUME_STATE =>
resume_state_enc <= (others => '0');
resume_step_enc <= (others => '0');
thread_is_resuming <= '0';
when OSIF_CMD_REQUEST_YIELD =>
yield_request <= '1';
when OSIF_CMD_CLEAR_YIELD =>
yield_request <= '0';
when OSIF_CMD_MMU_SETPGD =>
mmu_setpgd <= '1';
mmu_config_data <= slv_bus2osif_data;
when OSIF_CMD_MMU_REPEAT =>
mmu_repeat <= '1';
when others =>
end case;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- reset_proc: handles reset of software thread
-----------------------------------------------------------------------
reset_proc: process(sys_clk, sys_reset)
begin
if sys_reset = '1' then
reset_counter <= C_THREAD_RESET_CYCLES-1;
elsif rising_edge(sys_clk) then
if request_reset = '1' then
reset_counter <= C_THREAD_RESET_CYCLES-1;
elsif reset_counter > 0 then
reset_counter <= reset_counter - 1;
end if;
end if;
end process;
end IMP;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLMULT_SDNF1_3_block.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLMULT_SDNF1_3_block
-- Source Path: hdl_ofdm_tx/ifft/TWDLMULT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TWDLMULT_SDNF1_3_block IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_2_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_4_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_4_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_2_vld : IN std_logic;
twdl_3_3_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_3_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_4_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_4_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_4_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_3_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_3_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_4_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_4_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_3_vld : OUT std_logic
);
END TWDLMULT_SDNF1_3_block;
ARCHITECTURE rtl OF TWDLMULT_SDNF1_3_block IS
-- Component Declarations
COMPONENT Complex3Multiply_block
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din1_re_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
din1_im_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
din1_vld_dly3 : IN std_logic;
twdl_3_3_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_3_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_3_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_3_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin1_vld : OUT std_logic
);
END COMPONENT;
COMPONENT Complex3Multiply_block1
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din2_re_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
din2_im_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
di2_vld_dly3 : IN std_logic;
twdl_3_4_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_4_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_4_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_4_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin2_vld : OUT std_logic
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : Complex3Multiply_block
USE ENTITY work.Complex3Multiply_block(rtl);
FOR ALL : Complex3Multiply_block1
USE ENTITY work.Complex3Multiply_block1(rtl);
-- Signals
SIGNAL dout_2_re_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_re : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_2_im_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_im : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_vld_dly1 : std_logic;
SIGNAL din1_vld_dly2 : std_logic;
SIGNAL din1_vld_dly3 : std_logic;
SIGNAL twdlXdin_3_re_tmp : std_logic_vector(18 DOWNTO 0); -- ufix19
SIGNAL twdlXdin_3_im_tmp : std_logic_vector(18 DOWNTO 0); -- ufix19
SIGNAL twdlXdin1_vld : std_logic;
SIGNAL dout_4_re_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_re_1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_4_im_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_im_1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL di2_vld_dly1 : std_logic;
SIGNAL di2_vld_dly2 : std_logic;
SIGNAL di2_vld_dly3 : std_logic;
SIGNAL twdlXdin_4_re_tmp : std_logic_vector(18 DOWNTO 0); -- ufix19
SIGNAL twdlXdin_4_im_tmp : std_logic_vector(18 DOWNTO 0); -- ufix19
BEGIN
u_MUL3_1 : Complex3Multiply_block
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
din1_re_dly3 => std_logic_vector(din1_re_dly3), -- sfix19_En13
din1_im_dly3 => std_logic_vector(din1_im_dly3), -- sfix19_En13
din1_vld_dly3 => din1_vld_dly3,
twdl_3_3_re => twdl_3_3_re, -- sfix16_En14
twdl_3_3_im => twdl_3_3_im, -- sfix16_En14
softReset => softReset,
twdlXdin_3_re => twdlXdin_3_re_tmp, -- sfix19_En13
twdlXdin_3_im => twdlXdin_3_im_tmp, -- sfix19_En13
twdlXdin1_vld => twdlXdin1_vld
);
u_MUL3_2 : Complex3Multiply_block1
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
din2_re_dly3 => std_logic_vector(din2_re_dly3), -- sfix19_En13
din2_im_dly3 => std_logic_vector(din2_im_dly3), -- sfix19_En13
di2_vld_dly3 => di2_vld_dly3,
twdl_3_4_re => twdl_3_4_re, -- sfix16_En14
twdl_3_4_im => twdl_3_4_im, -- sfix16_En14
softReset => softReset,
twdlXdin_4_re => twdlXdin_4_re_tmp, -- sfix19_En13
twdlXdin_4_im => twdlXdin_4_im_tmp, -- sfix19_En13
twdlXdin2_vld => twdlXdin_3_vld
);
dout_2_re_signed <= signed(dout_2_re);
din_re <= resize(dout_2_re_signed, 19);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly1 <= din_re;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly2 <= din1_re_dly1;
END IF;
END IF;
END PROCESS intdelay_1_process;
dout_2_im_signed <= signed(dout_2_im);
din_im <= resize(dout_2_im_signed, 19);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly1 <= din_im;
END IF;
END IF;
END PROCESS intdelay_2_process;
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly2 <= din1_im_dly1;
END IF;
END IF;
END PROCESS intdelay_3_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly3 <= din1_re_dly2;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly3 <= din1_im_dly2;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_vld_dly2 <= din1_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_7_process;
intdelay_8_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_vld_dly3 <= din1_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_8_process;
dout_4_re_signed <= signed(dout_4_re);
din_re_1 <= resize(dout_4_re_signed, 19);
intdelay_9_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly1 <= din_re_1;
END IF;
END IF;
END PROCESS intdelay_9_process;
intdelay_10_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly2 <= din2_re_dly1;
END IF;
END IF;
END PROCESS intdelay_10_process;
dout_4_im_signed <= signed(dout_4_im);
din_im_1 <= resize(dout_4_im_signed, 19);
intdelay_11_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly1 <= din_im_1;
END IF;
END IF;
END PROCESS intdelay_11_process;
intdelay_12_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly2 <= din2_im_dly1;
END IF;
END IF;
END PROCESS intdelay_12_process;
intdelay_13_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly3 <= din2_re_dly2;
END IF;
END IF;
END PROCESS intdelay_13_process;
intdelay_14_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly3 <= din2_im_dly2;
END IF;
END IF;
END PROCESS intdelay_14_process;
intdelay_15_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_15_process;
intdelay_16_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly2 <= di2_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_16_process;
intdelay_17_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly3 <= di2_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_17_process;
twdlXdin_3_re <= twdlXdin_3_re_tmp;
twdlXdin_3_im <= twdlXdin_3_im_tmp;
twdlXdin_4_re <= twdlXdin_4_re_tmp;
twdlXdin_4_im <= twdlXdin_4_im_tmp;
END rtl;
|
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:27:17 10/31/2011
-- Design Name:
-- Module Name: /home/cvargasc/Documentos/Uniandes/201120/Fundamentos de Sistemas Digitales/Laboratorios/practica7/practica7/testPreEscalador.vhd
-- Project Name: practica7
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: preEscalador
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testPreEscalador IS
END testPreEscalador;
ARCHITECTURE behavior OF testPreEscalador IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT preEscalador
PORT(
clk : IN std_logic;
reset : IN std_logic;
caidaBolitaOut : OUT std_logic;
multiplexorOut : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal caidaBolitaOut : std_logic;
signal multiplexorOut : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: preEscalador PORT MAP (
clk => clk,
reset => reset,
caidaBolitaOut => caidaBolitaOut,
multiplexorOut => multiplexorOut
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait;
end process;
END;
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 35776)
`protect data_block
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`protect end_protected
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net6,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net1,
G => net5,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net6,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net1,
G => vbias2,
S => net3
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net4,
G => net1,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net4
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
|
--autor: igor macedo silva
--description: generic multiplexer for a generic number of inputs and generic bus size.
library ieee;
use ieee.std_logic_1164.all;
--creation of specifc package for array input
package barramento is
--constant insize: integer := 4;
--constant bussize: integer := 4;
--type int_matrix is array (integer range <>) of std_logic_vector(integer range <>);
type logic_matrix is array (natural range <>, natural range <>) of std_logic;
end package;
library ieee;
use ieee.std_logic_1164.all;
use work.barramento.all;
entity muxt is
generic(
insize: integer := 2;
bussize: integer := 4
);
port(
--i0, i1, i2, i3 : in bit;4
--type int_array is array ((insize-1) to 0) of bit_vector((bussize-1) downto 0);
bar : in logic_matrix(0 to (insize-1),0 to (bussize-1));
s : out std_logic_vector(0 to (bussize-1));
c : in integer range 0 to insize-1
);
end entity;
architecture estrutura of muxt is
begin
process(c)
begin
for i in 0 to (bussize-1) loop
s(i) <= bar(c,i);
end loop;
end process;
end architecture;
--=========================================================================
--autor: igor macedo silva
--description: generic multiplexer for a generic number of inputs and generic bus size.
--creation of specifc package for array input
-- package barramento is
-- constant insize: integer := 4;
-- constant bussize: integer := 4;
-- type int_array is array (integer range <>) of bit_vector(integer range <>);
-- end package;
--
-- use work.barramento.all;
--
-- entity muxt is
-- --generic(insize: integer := 4);
-- --generic(bussize: integer := 4);
-- port(
-- --i0, i1, i2, i3 : in bit;
-- --type int_array is array ((insize-1) to 0) of bit_vector((bussize-1) downto 0);
-- bar : in int_array;
-- s : out bit_vector((bussize-1) downto 0);
-- c : in integer range insize-1 downto 0
-- );
-- end entity;
--
-- architecture estrutura of muxt is
-- begin
-- s <= bar(c);
-- end architecture;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY CART_ROM IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END CART_ROM;
ARCHITECTURE CART_ROM_arch OF CART_ROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF CART_ROM_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF CART_ROM_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF CART_ROM_arch : ARCHITECTURE IS "CART_ROM,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF CART_ROM_arch: ARCHITECTURE IS "CART_ROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=CART_ROM.mif,C_INIT_FILE=CART_ROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=32768,C_READ_DEPTH_A=32768,C_ADDRA_WIDTH=15,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=32768,C_READ_DEPTH_B=32768,C_ADDRB_WIDTH=15,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=8,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.326399 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "CART_ROM.mif",
C_INIT_FILE => "CART_ROM.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 32768,
C_READ_DEPTH_A => 32768,
C_ADDRA_WIDTH => 15,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 32768,
C_READ_DEPTH_B => 32768,
C_ADDRB_WIDTH => 15,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "8",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.326399 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 15)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END CART_ROM_arch;
|
--------------------------------------------
-- Author: Mike Field <[email protected]>
--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity epp_interface is
port (
clk : in std_logic;
fifo_rd : out STD_LOGIC := '0';
fifo_data : in STD_LOGIC_VECTOR(7 downto 0);
fifo_empty : in STD_LOGIC;
epp_astb : in STD_LOGIC;
epp_dstb : in STD_LOGIC;
epp_wait : out STD_LOGIC := '0';
epp_wr : in STD_LOGIC;
epp_data : inout STD_LOGIC_VECTOR (7 downto 0));
end epp_interface;
architecture Behavioral of epp_interface is
type t_state is (s_idle, s_astb_read, s_astb_write, s_dstb_read, s_dstb_write);
signal state : t_state := s_idle;
signal sync_astb : std_logic_vector(1 downto 0) := "00";
signal sync_dstb : std_logic_vector(1 downto 0) := "00";
begin
with state select epp_data <= fifo_data when s_dstb_read,
x"AA" when s_astb_read,
(others => 'Z') when others;
process(clk)
begin
if rising_edge(clk) then
fifo_rd <= '0';
case state is
when s_idle =>
if sync_astb(0) = '0' then
--------------
-- address strobe
--------------
if epp_wr = '0' then
state <= s_astb_write;
else
state <= s_astb_read;
end if;
epp_wait <= '1';
elsif sync_dstb(0) = '0' then
--------------
-- data strobe
--------------
if epp_wr = '0' then
state <= s_dstb_write;
epp_wait <= '1';
else
if fifo_empty = '0' then
state <= s_dstb_read;
epp_wait <= '1';
end if;
end if;
end if;
when s_astb_read =>
if sync_astb(0) = '1' then
epp_wait <= '0';
state <= s_idle;
end if;
when s_astb_write =>
if sync_astb(0) = '1' then
epp_wait <= '0';
state <= s_idle;
end if;
when s_dstb_read =>
if sync_dstb(0) = '1' then
epp_wait <= '0';
state <= s_idle;
fifo_rd <= '1';
end if;
when s_dstb_write =>
if sync_dstb(0) = '1' then
epp_wait <= '0';
state <= s_idle;
end if;
when others =>
state <= s_idle;
end case;
---------------------------
-- Sync the strobe signals
---------------------------
sync_astb <= epp_astb & sync_astb(sync_astb'high downto 1);
sync_dstb <= epp_dstb & sync_dstb(sync_dstb'high downto 1);
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gigatron_tb is
end entity;
architecture rtl of gigatron_tb is
signal clk : std_logic := '0';
signal stop : std_logic := '0';
signal reset : std_logic := '1';
signal spi_req : std_logic;
signal red : unsigned(4 downto 0);
signal grn : unsigned(4 downto 0);
signal blu : unsigned(4 downto 0);
signal hsync : std_logic;
signal vsync : std_logic;
signal ram_data : unsigned(15 downto 0);
signal ram_addr : unsigned(12 downto 0);
signal ram_ba : unsigned(1 downto 0);
signal ram_we : std_logic;
signal ram_ras : std_logic;
signal ram_cas : std_logic;
signal ram_ldqm : std_logic;
signal ram_udqm : std_logic;
signal rom_a : unsigned(15 downto 0);
signal rom_q : unsigned(15 downto 0);
begin
clk <= (not stop) and (not clk) after 5 ns;
gigatron_inst : entity work.gigatron_top
generic map (
clk_ticks_per_usec => 100,
romload_size => 32
)
port map (
clk => clk,
reset => reset,
flashslot => "11000",
joystick => (others => '1'),
-- SPI interface
spi_cs_n => open,
spi_req => spi_req,
spi_ack => spi_req,
spi_d => open,
spi_q => X"00",
-- SDRAM interface
ram_data => ram_data,
ram_addr => ram_addr,
ram_ba => ram_ba,
ram_we => ram_we,
ram_ras => ram_ras,
ram_cas => ram_cas,
ram_ldqm => ram_ldqm,
ram_udqm => ram_udqm,
-- Video
red => red,
grn => grn,
blu => blu,
hsync => hsync,
vsync => vsync
);
rom_inst : entity work.gigatron_tb_rom
port map (
a => rom_a,
q => rom_q
);
sdram_emu_blk : block
signal oe_reg : std_logic := '0';
signal a_reg : unsigned(15 downto 0) := (others => '0');
begin
rom_a <= a_reg;
ram_data <= rom_q when oe_reg = '1' else (others => '0');
process(clk)
begin
if rising_edge(clk) then
if ram_ras = '0' then
a_reg(15 downto 9) <= ram_addr(6 downto 0);
oe_reg <= '0';
end if;
if (ram_cas = '0') and (ram_we = '1') then
a_reg(8 downto 0) <= ram_addr(8 downto 0);
oe_reg <= '1';
end if;
end if;
end process;
end block;
process
begin
reset <= '1';
wait for 1 us;
reset <= '0';
wait for 1000000 us;
stop <= '1';
wait;
end process;
end architecture;
|
library verilog;
use verilog.vl_types.all;
entity altfp_mult is
generic(
width_exp : integer := 8;
width_man : integer := 23;
dedicated_multiplier_circuitry: string := "AUTO";
reduced_functionality: string := "NO";
pipeline : integer := 5;
denormal_support: string := "YES";
exception_handling: string := "YES";
lpm_hint : string := "UNUSED";
lpm_type : string := "altfp_mult";
LATENCY : vl_notype;
WIDTH_MAN_EXP : vl_notype
);
port(
clock : in vl_logic;
clk_en : in vl_logic;
aclr : in vl_logic;
dataa : in vl_logic_vector;
datab : in vl_logic_vector;
result : out vl_logic_vector;
overflow : out vl_logic;
underflow : out vl_logic;
zero : out vl_logic;
denormal : out vl_logic;
indefinite : out vl_logic;
nan : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_exp : constant is 1;
attribute mti_svvh_generic_type of width_man : constant is 1;
attribute mti_svvh_generic_type of dedicated_multiplier_circuitry : constant is 1;
attribute mti_svvh_generic_type of reduced_functionality : constant is 1;
attribute mti_svvh_generic_type of pipeline : constant is 1;
attribute mti_svvh_generic_type of denormal_support : constant is 1;
attribute mti_svvh_generic_type of exception_handling : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of LATENCY : constant is 3;
attribute mti_svvh_generic_type of WIDTH_MAN_EXP : constant is 3;
end altfp_mult;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 10:12:12 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-e.vhd,v 1.2 2005/07/15 16:20:06 wig Exp $
-- $Date: 2005/07/15 16:20:06 $
-- $Log: inst_t_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:20:06 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_t_e
--
entity inst_t_e is
-- Generics:
-- No Generated Generics for Entity inst_t_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_t_e
end inst_t_e;
--
-- End of Generated Entity inst_t_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
use work.cpu_types_pkg.all;
use work.cpu_btb_cache_pkg.all;
use work.cpu_btb_cache_config_pkg.all;
use work.cpu_btb_cache_replace_pkg.all;
library util;
use util.types_pkg.all;
use util.logic_pkg.all;
use util.numeric_pkg.all;
library mem;
library tech;
architecture rtl of cpu_btb_cache is
constant state_way_lsb : natural := cpu_btb_cache_assoc + cpu_btb_cache_replace_state_bits;
constant state_replace_way_lsb : natural := cpu_btb_cache_replace_state_bits;
constant state_replace_state_lsb : natural := 0;
type way_tags_type is array (cpu_btb_cache_assoc-1 downto 0) of std_ulogic_vector(cpu_ivaddr_bits-1 downto cpu_btb_cache_index_bits);
type comb_type is record
wstate_way : std_ulogic_vector(cpu_btb_cache_assoc-1 downto 0);
wstate_replace_way : std_ulogic_vector(cpu_btb_cache_assoc-1 downto 0);
wstate_replace_state : cpu_btb_cache_replace_state_type;
rway_tags : way_tags_type;
rway_unpri : std_ulogic_vector(cpu_btb_cache_assoc downto 0);
rway_pri : std_ulogic_vector(cpu_btb_cache_assoc downto 0);
rway : std_ulogic_vector(cpu_btb_cache_assoc-1 downto 0);
rhit : std_ulogic;
rtarget : cpu_ivaddr_type;
whit : std_ulogic;
cache_we : std_ulogic;
cache_wway : std_ulogic_vector(cpu_btb_cache_assoc-1 downto 0);
cache_wtagen : std_ulogic;
cache_wdataen : std_ulogic;
cache_windex : std_ulogic_vector(cpu_btb_cache_index_bits-1 downto 0);
cache_wtag : std_ulogic_vector(cpu_ivaddr_bits-1 downto cpu_btb_cache_index_bits);
cache_wdata : std_ulogic_vector(cpu_ivaddr_bits-1 downto 0);
cache_re : std_ulogic;
cache_rway : std_ulogic_vector(cpu_btb_cache_assoc-1 downto 0);
cache_rtagen : std_ulogic;
cache_rdataen : std_ulogic;
cache_rindex : std_ulogic_vector(cpu_btb_cache_index_bits-1 downto 0);
cache_rtag : std_ulogic_vector2(cpu_btb_cache_assoc-1 downto 0, cpu_ivaddr_bits-1 downto cpu_btb_cache_index_bits);
cache_rdata : std_ulogic_vector2(cpu_btb_cache_assoc-1 downto 0, cpu_ivaddr_bits-1 downto 0);
replace_re : std_ulogic;
replace_rindex : std_ulogic_vector(cpu_btb_cache_index_bits-1 downto 0);
replace_rway : std_ulogic_vector(cpu_btb_cache_assoc-1 downto 0);
replace_rstate : cpu_btb_cache_replace_state_type;
replace_we : std_ulogic;
replace_windex : std_ulogic_vector(cpu_btb_cache_index_bits-1 downto 0);
replace_wway : std_ulogic_vector(cpu_btb_cache_assoc-1 downto 0);
replace_wstate : cpu_btb_cache_replace_state_type;
rtag_write : std_ulogic;
cpu_btb_cache_replace_ctrl_in : cpu_btb_cache_replace_ctrl_in_type;
cpu_btb_cache_replace_dp_in : cpu_btb_cache_replace_dp_in_type;
cpu_btb_cache_replace_dp_out : cpu_btb_cache_replace_dp_out_type;
end record;
type reg_type is record
rrequested : std_ulogic;
rtag : std_ulogic_vector(cpu_ivaddr_bits-1 downto cpu_btb_cache_index_bits);
end record;
constant reg_init : reg_type := (
rrequested => '0',
rtag => (others => 'X')
);
constant reg_x : reg_type := (
rrequested => 'X',
rtag => (others => 'X')
);
signal c : comb_type;
signal r, r_next : reg_type;
begin
c.wstate_way <= cpu_btb_cache_dp_in.wstate(state_way_lsb+cpu_btb_cache_assoc-1 downto
state_way_lsb);
c.wstate_replace_way <= cpu_btb_cache_dp_in.wstate(state_replace_way_lsb+cpu_btb_cache_assoc-1 downto
state_replace_way_lsb);
c.wstate_replace_state <= cpu_btb_cache_dp_in.wstate(state_replace_state_lsb+cpu_btb_cache_replace_state_bits-1 downto
state_replace_state_lsb);
c.whit <= reduce_or(c.wstate_way);
c.cache_we <= cpu_btb_cache_ctrl_in.wen and not c.whit;
c.cache_wway <= c.wstate_replace_way;
c.cache_wtagen <= cpu_btb_cache_ctrl_in.wen;
c.cache_wdataen <= cpu_btb_cache_ctrl_in.wen;
c.cache_windex <= cpu_btb_cache_dp_in.waddr(cpu_btb_cache_index_bits-1 downto 0);
c.cache_wtag <= cpu_btb_cache_dp_in.waddr(cpu_ivaddr_bits-1 downto cpu_btb_cache_index_bits);
c.cache_wdata <= cpu_btb_cache_dp_in.wtarget;
c.replace_we <= cpu_btb_cache_ctrl_in.wen;
c.replace_windex <= cpu_btb_cache_dp_in.waddr(cpu_btb_cache_index_bits-1 downto 0);
with c.whit select
c.replace_wway <= c.wstate_replace_way when '0',
c.wstate_way when '1',
(others => 'X') when others;
c.replace_wstate <= c.wstate_replace_state;
c.cache_re <= cpu_btb_cache_ctrl_in.ren;
c.cache_rway <= (others => '1');
c.cache_rtagen <= cpu_btb_cache_ctrl_in.ren;
c.cache_rdataen <= cpu_btb_cache_ctrl_in.ren;
c.cache_rindex <= cpu_btb_cache_dp_in.raddr(cpu_btb_cache_index_bits-1 downto 0);
c.replace_re <= cpu_btb_cache_ctrl_in.ren;
c.replace_rindex <= cpu_btb_cache_dp_in.raddr(cpu_btb_cache_index_bits-1 downto 0);
r_next.rrequested <= c.cache_re;
c.rtag_write <= c.cache_re;
with c.rtag_write select
r_next.rtag <= cpu_btb_cache_dp_in.raddr(cpu_ivaddr_bits-1 downto cpu_btb_cache_index_bits) when '1',
r.rtag when '0',
(others => 'X') when others;
seq : process (clk) is
begin
if rising_edge(clk) then
case rstn is
when '1' =>
r <= r_next;
when '0' =>
r <= reg_init;
when others =>
r <= reg_x;
end case;
end if;
end process;
way_loop : for n in cpu_btb_cache_assoc-1 downto 0 generate
ivaddr_bit_loop : for m in cpu_ivaddr_bits-1 downto cpu_btb_cache_index_bits generate
c.rway_tags(n)(m) <= c.cache_rtag(n, m);
end generate;
c.rway_unpri(n) <= logic_eq(c.rway_tags(n), r.rtag);
end generate;
-- need to prioritize because we might get multiple hits, since we don't keep valid bits
c.rway_unpri(cpu_btb_cache_assoc) <= '1';
c.rway_pri <= prioritize_least(c.rway_unpri);
c.rway <= c.rway_pri(cpu_btb_cache_assoc-1 downto 0);
c.rhit <= any_ones(c.rway);
c.replace_rway <= c.cpu_btb_cache_replace_dp_out.rway;
c.replace_rstate <= c.cpu_btb_cache_replace_dp_out.rstate;
c.cpu_btb_cache_replace_ctrl_in <= (
re => c.replace_re,
we => c.replace_we
);
c.cpu_btb_cache_replace_dp_in <= (
rindex => c.replace_rindex,
windex => c.replace_windex,
wway => c.replace_wway,
wstate => c.replace_wstate
);
cpu_btb_cache_ctrl_out <= (
rvalid => c.rhit
);
cpu_btb_cache_dp_out.rstate <= (
c.rway &
c.replace_rway &
c.replace_rstate
);
rtarget_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_ivaddr_bits,
sel_bits => cpu_btb_cache_assoc
)
port map (
din => c.cache_rdata,
sel => c.rway,
dout => cpu_btb_cache_dp_out.rtarget
);
replace : entity work.cpu_btb_cache_replace(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_btb_cache_replace_ctrl_in => c.cpu_btb_cache_replace_ctrl_in,
cpu_btb_cache_replace_dp_in => c.cpu_btb_cache_replace_dp_in,
cpu_btb_cache_replace_dp_out => c.cpu_btb_cache_replace_dp_out
);
cache : entity mem.cache_core_1r1w(rtl)
generic map (
log2_assoc => cpu_btb_cache_log2_assoc,
word_bits => cpu_ivaddr_bits,
index_bits => cpu_btb_cache_index_bits,
offset_bits => 0,
tag_bits => cpu_ivaddr_bits - cpu_btb_cache_index_bits,
write_first => true
)
port map (
clk => clk,
rstn => rstn,
we => c.cache_we,
wway => c.cache_wway,
wtagen => c.cache_wtagen,
wdataen => c.cache_wdataen,
windex => c.cache_windex,
woffset => "",
wtag => c.cache_wtag,
wdata => c.cache_wdata,
re => c.cache_re,
rway => c.cache_rway,
rtagen => c.cache_rtagen,
rdataen => c.cache_rdataen,
rindex => c.cache_rindex,
roffset => "",
rtag => c.cache_rtag,
rdata => c.cache_rdata
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
-- Routines to help output text at a higher level of abstraction.
package tbu_text_out_pkg is
--type integer_vector is array (natural range <>) of integer;
procedure put(text: string);
procedure put(value: boolean);
procedure put(value: real);
procedure put(value: integer);
procedure putv(vector: integer_vector);
procedure putv(value: std_logic_vector);
procedure putv(value: bit_vector);
procedure putv(value: unsigned);
procedure print(text: string; newline: boolean := true);
end;
package body tbu_text_out_pkg is
procedure put(text: string) is
variable s: line;
begin
write(s, text);
writeline(output,s);
end;
-- Declare a shared line to allow incremental text output to the same line
shared variable current_line: line;
-- Incrementally output text to the same line. To force a line break, call
-- with newline = true.
procedure print(text: string; newline: boolean := true) is
begin
write(current_line, text);
if (newline) then
writeline(output, current_line);
end if;
end;
procedure put(value: boolean) is begin
-- synthesis translate_off
put(to_string(value));
-- synthesis translate_on
end;
procedure put(value: real) is begin
-- synthesis translate_off
put(to_string(value));
-- synthesis translate_on
end;
procedure put(value: integer) is begin
-- synthesis translate_off
put(to_string(value));
-- synthesis translate_on
end;
procedure putv(vector: integer_vector) is begin
-- synthesis translate_off
for i in vector'range loop
print(to_string(vector(i)) & " ", newline => false);
end loop;
print("");
-- synthesis translate_on
end;
procedure putv(value: std_logic_vector) is begin
-- synthesis translate_off
put(to_string(value));
-- synthesis translate_on
end;
procedure putv(value: bit_vector) is begin
-- synthesis translate_off
put(to_string(value));
-- synthesis translate_on
end;
procedure putv(value: unsigned) is begin
-- synthesis translate_off
put(to_string(value));
-- synthesis translate_on
end;
end;
|
architecture RTL of FIFO is
begin
process
begin
sig1 <= sig2;
sig2 <= sig3;
end process;
-- Violations below
process
begin
sig1 <= sig2; sig2 <= sig3; -- Comment 1
siga <= sigb; sigb <= sigc; sigc <= sigd;
end process;
end architecture RTL;
|
------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 23:40:00 02/26/2015
-- Design Name:
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 16.0
-- Description: This AES3/EBU and SPDIF receiver is compliant with
-- IEC61937, IEC60958-3 and IEC60958-4
-- The input is sampled in by either
-- 49.152 MHz for 48kHz, 96kHz and 192kHz samplerates
-- 45.1584 MHz for 44.1kHz, 88.2kHz or 176.4 kHz
--
-- Dependencies:
--
-- Revision:
-- Revision 0.1 - File created
-- Revision 0.2 - Changed indentation
-- - rewrite of the state machine
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spdif_pkg.all;
entity aes3rx is
port (
-- Synchronous reset
reset : in std_ulogic;
-- Master clock
clk : in std_ulogic;
aes_in : in t_aes_in;
aes_out : out t_aes_out
);
end aes3rx;
architecture rtl of aes3rx is
type t_reg_type is record
slv_aes3 : std_logic_vector(3 downto 0);
sl_aes3_clk : std_logic;
sl_change : std_logic; -- detects
slv_sync_count : std_logic_vector(5 downto 0);
slv_clk_counter : std_logic_vector(7 downto 0);
slv_decoder_shift : std_logic_vector(7 downto 0);
sl_x_detected : std_logic; -- Asserted when x preamble has been detected
sl_y_detected : std_logic; -- Asserted when y preamble has been detected
sl_z_detected : std_logic; -- Asserted when z preamble has been detected
sl_preamble_detected : std_logic; -- Asserted when all preambles
sl_lock : std_logic;
state : t_aes3_state;
end record;
signal r, r_next : t_reg_type;
begin
-- _ _ _ _ _ _ _
-- / \_/ \_/ \_/ \_/ \_/ \_/ \_/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\
-- __
-- __/
input_shift_proc: process(aes_in, reset, r)
variable v : t_reg_type;
begin
v := r;
-- getting asynchronous input
v.slv_aes3 := aes_in.data & r.slv_aes3(3 downto 1);
-- detecting signal change
v.sl_change := r.slv_aes3(2) xor r.slv_aes3(1);
-- counts number of aes_clk pulses since last detected preamble
if r.sl_preamble_detected = '1' then
v.slv_sync_count := (others => '0');
else
v.slv_sync_count := std_logic_vector(unsigned(r.slv_sync_count) + 1);
end if;
-- counting
if r.slv_clk_counter = b"0000_0000" then
if r.sl_change = '1' then
v.slv_clk_counter := (others => '1');
else
v.slv_clk_counter := std_logic_vector(unsigned(r.slv_clk_counter) - 1);
end if;
end if;
-- decoder shift register
v.slv_decoder_shift := r.slv_aes3(0) & r.slv_decoder_shift(7 downto 1);
-- Generates a clock pulse when clk_counter counts to zero
if r.slv_clk_counter = x"00" then
v.sl_aes3_clk := '1';
else
v.sl_aes3_clk := '0';
end if;
-- preamble detection
v.sl_x_detected := preamble_detection(r.slv_decoder_shift, X_PREAMBLE);
v.sl_y_detected := preamble_detection(r.slv_decoder_shift, Y_PREAMBLE);
v.sl_z_detected := preamble_detection(r.slv_decoder_shift, Z_PREAMBLE);
v.sl_preamble_detected := v.sl_x_detected or v.sl_y_detected or v.sl_z_detected;
-- preamble detection
if r.sl_preamble_detected = '1' then
end if;
-- Locking state machine for AES3/EBU data stream.
-- The locking for 192kHz, 96kHz and 48kHz will be done in parallel.
-- The clock will be set to 122 MHz
case r.state is
when UNLOCKED =>
if r.sl_preamble_detected = '1' then
v.state := CONFIRMING;
v.sl_lock := '0';
end if;
when CONFIRMING =>
if r.sl_preamble_detected = '1' then
v.state := LOCKED;
end if;
when LOCKED =>
if r.sl_preamble_detected = '0' then
v.state := UNLOCKED;
v.sl_lock := '1';
end if;
end case;
if (reset = '0') then
v.state := UNLOCKED;
end if;
r_next <= v;
aes_out.lock <= r.sl_lock;
end process input_shift_proc;
proc : process (clk)
begin
if rising_edge(clk) then
r <= r_next;
end if;
end process proc;
end rtl;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:27:52 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_ref_1_0/system_vga_sync_ref_1_0_sim_netlist.vhdl
-- Design : system_vga_sync_ref_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_ref_1_0_vga_sync_ref is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
start : out STD_LOGIC;
active : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
vsync : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_ref_1_0_vga_sync_ref : entity is "vga_sync_ref";
end system_vga_sync_ref_1_0_vga_sync_ref;
architecture STRUCTURE of system_vga_sync_ref_1_0_vga_sync_ref is
signal \^active\ : STD_LOGIC;
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal counter : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \counter[12]_i_3_n_0\ : STD_LOGIC;
signal \counter[12]_i_4_n_0\ : STD_LOGIC;
signal \counter[12]_i_5_n_0\ : STD_LOGIC;
signal \counter[12]_i_6_n_0\ : STD_LOGIC;
signal \counter[16]_i_3_n_0\ : STD_LOGIC;
signal \counter[16]_i_4_n_0\ : STD_LOGIC;
signal \counter[16]_i_5_n_0\ : STD_LOGIC;
signal \counter[16]_i_6_n_0\ : STD_LOGIC;
signal \counter[20]_i_3_n_0\ : STD_LOGIC;
signal \counter[20]_i_4_n_0\ : STD_LOGIC;
signal \counter[20]_i_5_n_0\ : STD_LOGIC;
signal \counter[20]_i_6_n_0\ : STD_LOGIC;
signal \counter[24]_i_3_n_0\ : STD_LOGIC;
signal \counter[24]_i_4_n_0\ : STD_LOGIC;
signal \counter[24]_i_5_n_0\ : STD_LOGIC;
signal \counter[24]_i_6_n_0\ : STD_LOGIC;
signal \counter[28]_i_3_n_0\ : STD_LOGIC;
signal \counter[28]_i_4_n_0\ : STD_LOGIC;
signal \counter[28]_i_5_n_0\ : STD_LOGIC;
signal \counter[28]_i_6_n_0\ : STD_LOGIC;
signal \counter[31]_i_10_n_0\ : STD_LOGIC;
signal \counter[31]_i_11_n_0\ : STD_LOGIC;
signal \counter[31]_i_12_n_0\ : STD_LOGIC;
signal \counter[31]_i_13_n_0\ : STD_LOGIC;
signal \counter[31]_i_14_n_0\ : STD_LOGIC;
signal \counter[31]_i_15_n_0\ : STD_LOGIC;
signal \counter[31]_i_16_n_0\ : STD_LOGIC;
signal \counter[31]_i_17_n_0\ : STD_LOGIC;
signal \counter[31]_i_18_n_0\ : STD_LOGIC;
signal \counter[31]_i_19_n_0\ : STD_LOGIC;
signal \counter[31]_i_1_n_0\ : STD_LOGIC;
signal \counter[31]_i_2_n_0\ : STD_LOGIC;
signal \counter[31]_i_4_n_0\ : STD_LOGIC;
signal \counter[31]_i_6_n_0\ : STD_LOGIC;
signal \counter[31]_i_7_n_0\ : STD_LOGIC;
signal \counter[31]_i_8_n_0\ : STD_LOGIC;
signal \counter[31]_i_9_n_0\ : STD_LOGIC;
signal \counter[4]_i_3_n_0\ : STD_LOGIC;
signal \counter[4]_i_4_n_0\ : STD_LOGIC;
signal \counter[4]_i_5_n_0\ : STD_LOGIC;
signal \counter[4]_i_6_n_0\ : STD_LOGIC;
signal \counter[8]_i_3_n_0\ : STD_LOGIC;
signal \counter[8]_i_4_n_0\ : STD_LOGIC;
signal \counter[8]_i_5_n_0\ : STD_LOGIC;
signal \counter[8]_i_6_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_2\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_3\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_5\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_6\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_7\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_7\ : STD_LOGIC;
signal \h_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_7_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_8_n_0\ : STD_LOGIC;
signal \h_count_reg_reg__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_in : STD_LOGIC_VECTOR ( 31 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^start\ : STD_LOGIC;
signal start_i_1_n_0 : STD_LOGIC;
signal start_i_2_n_0 : STD_LOGIC;
signal start_i_3_n_0 : STD_LOGIC;
signal start_i_4_n_0 : STD_LOGIC;
signal start_i_5_n_0 : STD_LOGIC;
signal start_i_6_n_0 : STD_LOGIC;
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_10_n_0\ : STD_LOGIC;
signal \state[1]_i_11_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
signal \state[1]_i_4_n_0\ : STD_LOGIC;
signal \state[1]_i_5_n_0\ : STD_LOGIC;
signal \state[1]_i_6_n_0\ : STD_LOGIC;
signal \state[1]_i_7_n_0\ : STD_LOGIC;
signal \state[1]_i_8_n_0\ : STD_LOGIC;
signal \state[1]_i_9_n_0\ : STD_LOGIC;
signal \state_reg_n_0_[0]\ : STD_LOGIC;
signal \state_reg_n_0_[1]\ : STD_LOGIC;
signal \v_count_reg[9]_i_10_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_7_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_8_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_9_n_0\ : STD_LOGIC;
signal \v_count_reg_reg__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_counter_reg[31]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_counter_reg[31]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \counter[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \counter[31]_i_15\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \counter[31]_i_18\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \h_count_reg[0]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[8]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_7\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_8\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of start_i_3 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of start_i_4 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of start_i_6 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \state[1]_i_10\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \v_count_reg[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \v_count_reg[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_6\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_7\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_8\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_9\ : label is "soft_lutpair8";
begin
active <= \^active\;
start <= \^start\;
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000002FFFE"
)
port map (
I0 => \^active\,
I1 => active_i_2_n_0,
I2 => \v_count_reg[9]_i_1_n_0\,
I3 => start_i_2_n_0,
I4 => \state_reg_n_0_[0]\,
I5 => \counter[31]_i_1_n_0\,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => counter(25),
I2 => counter(26),
I3 => counter(24),
I4 => \v_count_reg[9]_i_5_n_0\,
I5 => \counter[31]_i_7_n_0\,
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => active_i_1_n_0,
Q => \^active\,
R => '0'
);
\counter[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => counter(0),
O => p_2_in(0)
);
\counter[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(10)
);
\counter[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(11)
);
\counter[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(12)
);
\counter[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(12),
O => \counter[12]_i_3_n_0\
);
\counter[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(11),
O => \counter[12]_i_4_n_0\
);
\counter[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(10),
O => \counter[12]_i_5_n_0\
);
\counter[12]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(9),
O => \counter[12]_i_6_n_0\
);
\counter[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(13)
);
\counter[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(14)
);
\counter[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(15)
);
\counter[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(16)
);
\counter[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(16),
O => \counter[16]_i_3_n_0\
);
\counter[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(15),
O => \counter[16]_i_4_n_0\
);
\counter[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(14),
O => \counter[16]_i_5_n_0\
);
\counter[16]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(13),
O => \counter[16]_i_6_n_0\
);
\counter[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(17)
);
\counter[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(18)
);
\counter[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(19)
);
\counter[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(1)
);
\counter[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(20)
);
\counter[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(20),
O => \counter[20]_i_3_n_0\
);
\counter[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(19),
O => \counter[20]_i_4_n_0\
);
\counter[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(18),
O => \counter[20]_i_5_n_0\
);
\counter[20]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(17),
O => \counter[20]_i_6_n_0\
);
\counter[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(21)
);
\counter[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(22)
);
\counter[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(23)
);
\counter[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(24)
);
\counter[24]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(24),
O => \counter[24]_i_3_n_0\
);
\counter[24]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(23),
O => \counter[24]_i_4_n_0\
);
\counter[24]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(22),
O => \counter[24]_i_5_n_0\
);
\counter[24]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(21),
O => \counter[24]_i_6_n_0\
);
\counter[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(25)
);
\counter[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(26)
);
\counter[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(27)
);
\counter[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(28)
);
\counter[28]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(28),
O => \counter[28]_i_3_n_0\
);
\counter[28]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(27),
O => \counter[28]_i_4_n_0\
);
\counter[28]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(26),
O => \counter[28]_i_5_n_0\
);
\counter[28]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(25),
O => \counter[28]_i_6_n_0\
);
\counter[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[31]_i_5_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(29)
);
\counter[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(2)
);
\counter[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[31]_i_5_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(30)
);
\counter[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => vsync,
I1 => rst,
O => \counter[31]_i_1_n_0\
);
\counter[31]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => counter(24),
I1 => counter(26),
I2 => counter(25),
O => \counter[31]_i_10_n_0\
);
\counter[31]_i_11\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(31),
O => \counter[31]_i_11_n_0\
);
\counter[31]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(30),
O => \counter[31]_i_12_n_0\
);
\counter[31]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(29),
O => \counter[31]_i_13_n_0\
);
\counter[31]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(17),
I1 => counter(16),
I2 => counter(19),
I3 => counter(18),
I4 => \v_count_reg[9]_i_10_n_0\,
I5 => \counter[31]_i_10_n_0\,
O => \counter[31]_i_14_n_0\
);
\counter[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => counter(31),
I1 => counter(30),
I2 => counter(29),
O => \counter[31]_i_15_n_0\
);
\counter[31]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF7FFFFFFFFFFF"
)
port map (
I0 => counter(2),
I1 => counter(1),
I2 => counter(0),
I3 => counter(3),
I4 => \state_reg_n_0_[1]\,
I5 => \state_reg_n_0_[0]\,
O => \counter[31]_i_16_n_0\
);
\counter[31]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => counter(4),
I1 => counter(8),
I2 => counter(6),
I3 => counter(5),
O => \counter[31]_i_17_n_0\
);
\counter[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(10),
I1 => counter(11),
O => \counter[31]_i_18_n_0\
);
\counter[31]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(15),
I1 => counter(14),
I2 => counter(13),
I3 => counter(12),
O => \counter[31]_i_19_n_0\
);
\counter[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state_reg_n_0_[1]\,
O => \counter[31]_i_2_n_0\
);
\counter[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"4440404044404440"
)
port map (
I0 => \counter[31]_i_4_n_0\,
I1 => \counter_reg[31]_i_5_n_5\,
I2 => \counter[31]_i_6_n_0\,
I3 => \counter[31]_i_7_n_0\,
I4 => \counter[31]_i_8_n_0\,
I5 => \counter[31]_i_9_n_0\,
O => p_2_in(31)
);
\counter[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => start_i_5_n_0,
I2 => start_i_4_n_0,
I3 => \v_count_reg[9]_i_5_n_0\,
I4 => start_i_3_n_0,
I5 => \counter[31]_i_10_n_0\,
O => \counter[31]_i_4_n_0\
);
\counter[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEFEFEFF"
)
port map (
I0 => \counter[31]_i_14_n_0\,
I1 => counter(28),
I2 => counter(27),
I3 => \state_reg_n_0_[1]\,
I4 => \state_reg_n_0_[0]\,
I5 => \counter[31]_i_15_n_0\,
O => \counter[31]_i_6_n_0\
);
\counter[31]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFEFF"
)
port map (
I0 => \counter[31]_i_16_n_0\,
I1 => \counter[31]_i_17_n_0\,
I2 => counter(7),
I3 => counter(9),
I4 => \counter[31]_i_18_n_0\,
I5 => \counter[31]_i_19_n_0\,
O => \counter[31]_i_7_n_0\
);
\counter[31]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFBFFF"
)
port map (
I0 => \h_count_reg[9]_i_5_n_0\,
I1 => counter(3),
I2 => counter(0),
I3 => counter(7),
I4 => counter(6),
I5 => \h_count_reg[9]_i_2_n_0\,
O => \counter[31]_i_8_n_0\
);
\counter[31]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \counter[31]_i_19_n_0\,
I1 => counter(10),
I2 => counter(11),
I3 => counter(8),
I4 => counter(9),
O => \counter[31]_i_9_n_0\
);
\counter[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(3)
);
\counter[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(4)
);
\counter[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(4),
O => \counter[4]_i_3_n_0\
);
\counter[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(3),
O => \counter[4]_i_4_n_0\
);
\counter[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(2),
O => \counter[4]_i_5_n_0\
);
\counter[4]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(1),
O => \counter[4]_i_6_n_0\
);
\counter[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(5)
);
\counter[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(6)
);
\counter[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(7)
);
\counter[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(8)
);
\counter[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(8),
O => \counter[8]_i_3_n_0\
);
\counter[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(7),
O => \counter[8]_i_4_n_0\
);
\counter[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(6),
O => \counter[8]_i_5_n_0\
);
\counter[8]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(5),
O => \counter[8]_i_6_n_0\
);
\counter[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(9)
);
\counter_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(0),
Q => counter(0),
R => \counter[31]_i_1_n_0\
);
\counter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(10),
Q => counter(10),
R => \counter[31]_i_1_n_0\
);
\counter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(11),
Q => counter(11),
R => \counter[31]_i_1_n_0\
);
\counter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(12),
Q => counter(12),
R => \counter[31]_i_1_n_0\
);
\counter_reg[12]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[8]_i_2_n_0\,
CO(3) => \counter_reg[12]_i_2_n_0\,
CO(2) => \counter_reg[12]_i_2_n_1\,
CO(1) => \counter_reg[12]_i_2_n_2\,
CO(0) => \counter_reg[12]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[12]_i_2_n_4\,
O(2) => \counter_reg[12]_i_2_n_5\,
O(1) => \counter_reg[12]_i_2_n_6\,
O(0) => \counter_reg[12]_i_2_n_7\,
S(3) => \counter[12]_i_3_n_0\,
S(2) => \counter[12]_i_4_n_0\,
S(1) => \counter[12]_i_5_n_0\,
S(0) => \counter[12]_i_6_n_0\
);
\counter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(13),
Q => counter(13),
R => \counter[31]_i_1_n_0\
);
\counter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(14),
Q => counter(14),
R => \counter[31]_i_1_n_0\
);
\counter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(15),
Q => counter(15),
R => \counter[31]_i_1_n_0\
);
\counter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(16),
Q => counter(16),
R => \counter[31]_i_1_n_0\
);
\counter_reg[16]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[12]_i_2_n_0\,
CO(3) => \counter_reg[16]_i_2_n_0\,
CO(2) => \counter_reg[16]_i_2_n_1\,
CO(1) => \counter_reg[16]_i_2_n_2\,
CO(0) => \counter_reg[16]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[16]_i_2_n_4\,
O(2) => \counter_reg[16]_i_2_n_5\,
O(1) => \counter_reg[16]_i_2_n_6\,
O(0) => \counter_reg[16]_i_2_n_7\,
S(3) => \counter[16]_i_3_n_0\,
S(2) => \counter[16]_i_4_n_0\,
S(1) => \counter[16]_i_5_n_0\,
S(0) => \counter[16]_i_6_n_0\
);
\counter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(17),
Q => counter(17),
R => \counter[31]_i_1_n_0\
);
\counter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(18),
Q => counter(18),
R => \counter[31]_i_1_n_0\
);
\counter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(19),
Q => counter(19),
R => \counter[31]_i_1_n_0\
);
\counter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(1),
Q => counter(1),
R => \counter[31]_i_1_n_0\
);
\counter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(20),
Q => counter(20),
R => \counter[31]_i_1_n_0\
);
\counter_reg[20]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[16]_i_2_n_0\,
CO(3) => \counter_reg[20]_i_2_n_0\,
CO(2) => \counter_reg[20]_i_2_n_1\,
CO(1) => \counter_reg[20]_i_2_n_2\,
CO(0) => \counter_reg[20]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[20]_i_2_n_4\,
O(2) => \counter_reg[20]_i_2_n_5\,
O(1) => \counter_reg[20]_i_2_n_6\,
O(0) => \counter_reg[20]_i_2_n_7\,
S(3) => \counter[20]_i_3_n_0\,
S(2) => \counter[20]_i_4_n_0\,
S(1) => \counter[20]_i_5_n_0\,
S(0) => \counter[20]_i_6_n_0\
);
\counter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(21),
Q => counter(21),
R => \counter[31]_i_1_n_0\
);
\counter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(22),
Q => counter(22),
R => \counter[31]_i_1_n_0\
);
\counter_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(23),
Q => counter(23),
R => \counter[31]_i_1_n_0\
);
\counter_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(24),
Q => counter(24),
R => \counter[31]_i_1_n_0\
);
\counter_reg[24]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[20]_i_2_n_0\,
CO(3) => \counter_reg[24]_i_2_n_0\,
CO(2) => \counter_reg[24]_i_2_n_1\,
CO(1) => \counter_reg[24]_i_2_n_2\,
CO(0) => \counter_reg[24]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[24]_i_2_n_4\,
O(2) => \counter_reg[24]_i_2_n_5\,
O(1) => \counter_reg[24]_i_2_n_6\,
O(0) => \counter_reg[24]_i_2_n_7\,
S(3) => \counter[24]_i_3_n_0\,
S(2) => \counter[24]_i_4_n_0\,
S(1) => \counter[24]_i_5_n_0\,
S(0) => \counter[24]_i_6_n_0\
);
\counter_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(25),
Q => counter(25),
R => \counter[31]_i_1_n_0\
);
\counter_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(26),
Q => counter(26),
R => \counter[31]_i_1_n_0\
);
\counter_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(27),
Q => counter(27),
R => \counter[31]_i_1_n_0\
);
\counter_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(28),
Q => counter(28),
R => \counter[31]_i_1_n_0\
);
\counter_reg[28]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[24]_i_2_n_0\,
CO(3) => \counter_reg[28]_i_2_n_0\,
CO(2) => \counter_reg[28]_i_2_n_1\,
CO(1) => \counter_reg[28]_i_2_n_2\,
CO(0) => \counter_reg[28]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[28]_i_2_n_4\,
O(2) => \counter_reg[28]_i_2_n_5\,
O(1) => \counter_reg[28]_i_2_n_6\,
O(0) => \counter_reg[28]_i_2_n_7\,
S(3) => \counter[28]_i_3_n_0\,
S(2) => \counter[28]_i_4_n_0\,
S(1) => \counter[28]_i_5_n_0\,
S(0) => \counter[28]_i_6_n_0\
);
\counter_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(29),
Q => counter(29),
R => \counter[31]_i_1_n_0\
);
\counter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(2),
Q => counter(2),
R => \counter[31]_i_1_n_0\
);
\counter_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(30),
Q => counter(30),
R => \counter[31]_i_1_n_0\
);
\counter_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(31),
Q => counter(31),
R => \counter[31]_i_1_n_0\
);
\counter_reg[31]_i_5\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[28]_i_2_n_0\,
CO(3 downto 2) => \NLW_counter_reg[31]_i_5_CO_UNCONNECTED\(3 downto 2),
CO(1) => \counter_reg[31]_i_5_n_2\,
CO(0) => \counter_reg[31]_i_5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_counter_reg[31]_i_5_O_UNCONNECTED\(3),
O(2) => \counter_reg[31]_i_5_n_5\,
O(1) => \counter_reg[31]_i_5_n_6\,
O(0) => \counter_reg[31]_i_5_n_7\,
S(3) => '0',
S(2) => \counter[31]_i_11_n_0\,
S(1) => \counter[31]_i_12_n_0\,
S(0) => \counter[31]_i_13_n_0\
);
\counter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(3),
Q => counter(3),
R => \counter[31]_i_1_n_0\
);
\counter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(4),
Q => counter(4),
R => \counter[31]_i_1_n_0\
);
\counter_reg[4]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \counter_reg[4]_i_2_n_0\,
CO(2) => \counter_reg[4]_i_2_n_1\,
CO(1) => \counter_reg[4]_i_2_n_2\,
CO(0) => \counter_reg[4]_i_2_n_3\,
CYINIT => counter(0),
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[4]_i_2_n_4\,
O(2) => \counter_reg[4]_i_2_n_5\,
O(1) => \counter_reg[4]_i_2_n_6\,
O(0) => \counter_reg[4]_i_2_n_7\,
S(3) => \counter[4]_i_3_n_0\,
S(2) => \counter[4]_i_4_n_0\,
S(1) => \counter[4]_i_5_n_0\,
S(0) => \counter[4]_i_6_n_0\
);
\counter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(5),
Q => counter(5),
R => \counter[31]_i_1_n_0\
);
\counter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(6),
Q => counter(6),
R => \counter[31]_i_1_n_0\
);
\counter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(7),
Q => counter(7),
R => \counter[31]_i_1_n_0\
);
\counter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(8),
Q => counter(8),
R => \counter[31]_i_1_n_0\
);
\counter_reg[8]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[4]_i_2_n_0\,
CO(3) => \counter_reg[8]_i_2_n_0\,
CO(2) => \counter_reg[8]_i_2_n_1\,
CO(1) => \counter_reg[8]_i_2_n_2\,
CO(0) => \counter_reg[8]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[8]_i_2_n_4\,
O(2) => \counter_reg[8]_i_2_n_5\,
O(1) => \counter_reg[8]_i_2_n_6\,
O(0) => \counter_reg[8]_i_2_n_7\,
S(3) => \counter[8]_i_3_n_0\,
S(2) => \counter[8]_i_4_n_0\,
S(1) => \counter[8]_i_5_n_0\,
S(0) => \counter[8]_i_6_n_0\
);
\counter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(9),
Q => counter(9),
R => \counter[31]_i_1_n_0\
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \h_count_reg_reg__0\(0),
O => \plusOp__0\(0)
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \h_count_reg_reg__0\(0),
I1 => \h_count_reg_reg__0\(1),
O => \plusOp__0\(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \h_count_reg_reg__0\(2),
I1 => \h_count_reg_reg__0\(0),
I2 => \h_count_reg_reg__0\(1),
O => \plusOp__0\(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \h_count_reg_reg__0\(3),
I1 => \h_count_reg_reg__0\(1),
I2 => \h_count_reg_reg__0\(0),
I3 => \h_count_reg_reg__0\(2),
O => \plusOp__0\(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \h_count_reg_reg__0\(2),
I1 => \h_count_reg_reg__0\(0),
I2 => \h_count_reg_reg__0\(1),
I3 => \h_count_reg_reg__0\(3),
I4 => \h_count_reg_reg__0\(4),
O => \plusOp__0\(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(5),
I1 => \h_count_reg_reg__0\(2),
I2 => \h_count_reg_reg__0\(0),
I3 => \h_count_reg_reg__0\(1),
I4 => \h_count_reg_reg__0\(3),
I5 => \h_count_reg_reg__0\(4),
O => \plusOp__0\(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \h_count_reg_reg__0\(6),
I1 => \h_count_reg[9]_i_7_n_0\,
I2 => \h_count_reg_reg__0\(5),
O => \plusOp__0\(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \h_count_reg_reg__0\(7),
I1 => \h_count_reg_reg__0\(5),
I2 => \h_count_reg[9]_i_7_n_0\,
I3 => \h_count_reg_reg__0\(6),
O => \plusOp__0\(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(8),
I1 => \h_count_reg_reg__0\(6),
I2 => \h_count_reg[9]_i_7_n_0\,
I3 => \h_count_reg_reg__0\(5),
I4 => \h_count_reg_reg__0\(7),
O => \plusOp__0\(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDFDDDDDDDDD"
)
port map (
I0 => rst,
I1 => vsync,
I2 => \counter[31]_i_9_n_0\,
I3 => \h_count_reg[9]_i_4_n_0\,
I4 => \h_count_reg[9]_i_5_n_0\,
I5 => \h_count_reg[9]_i_6_n_0\,
O => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state_reg_n_0_[1]\,
O => \h_count_reg[9]_i_2_n_0\
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(9),
I1 => \h_count_reg_reg__0\(7),
I2 => \h_count_reg_reg__0\(5),
I3 => \h_count_reg[9]_i_7_n_0\,
I4 => \h_count_reg_reg__0\(6),
I5 => \h_count_reg_reg__0\(8),
O => \plusOp__0\(9)
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFFFFFFFFFFFFFF"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => \state_reg_n_0_[0]\,
I2 => counter(6),
I3 => counter(7),
I4 => counter(0),
I5 => counter(3),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg[9]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => counter(1),
I1 => counter(2),
I2 => counter(4),
I3 => counter(5),
O => \h_count_reg[9]_i_5_n_0\
);
\h_count_reg[9]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_5_n_0\,
I1 => counter(24),
I2 => counter(26),
I3 => counter(25),
I4 => \v_count_reg[9]_i_10_n_0\,
I5 => \h_count_reg[9]_i_8_n_0\,
O => \h_count_reg[9]_i_6_n_0\
);
\h_count_reg[9]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \h_count_reg_reg__0\(4),
I1 => \h_count_reg_reg__0\(3),
I2 => \h_count_reg_reg__0\(1),
I3 => \h_count_reg_reg__0\(0),
I4 => \h_count_reg_reg__0\(2),
O => \h_count_reg[9]_i_7_n_0\
);
\h_count_reg[9]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(17),
I1 => counter(16),
I2 => counter(19),
I3 => counter(18),
O => \h_count_reg[9]_i_8_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(0),
Q => \h_count_reg_reg__0\(0),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(1),
Q => \h_count_reg_reg__0\(1),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(2),
Q => \h_count_reg_reg__0\(2),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(3),
Q => \h_count_reg_reg__0\(3),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(4),
Q => \h_count_reg_reg__0\(4),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(5),
Q => \h_count_reg_reg__0\(5),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(6),
Q => \h_count_reg_reg__0\(6),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(7),
Q => \h_count_reg_reg__0\(7),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(8),
Q => \h_count_reg_reg__0\(8),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(9),
Q => \h_count_reg_reg__0\(9),
R => \h_count_reg[9]_i_1_n_0\
);
start_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000220E0000"
)
port map (
I0 => \^start\,
I1 => start_i_2_n_0,
I2 => \state_reg_n_0_[0]\,
I3 => \state_reg_n_0_[1]\,
I4 => rst,
I5 => vsync,
O => start_i_1_n_0
);
start_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \h_count_reg[9]_i_6_n_0\,
I1 => start_i_3_n_0,
I2 => start_i_4_n_0,
I3 => start_i_5_n_0,
O => start_i_2_n_0
);
start_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(15),
I1 => counter(14),
I2 => counter(4),
I3 => counter(6),
O => start_i_3_n_0
);
start_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => counter(3),
I1 => counter(1),
I2 => counter(2),
I3 => counter(11),
I4 => start_i_6_n_0,
O => start_i_4_n_0
);
start_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => counter(5),
I1 => counter(13),
I2 => counter(8),
I3 => counter(9),
I4 => \state_reg_n_0_[1]\,
I5 => \state_reg_n_0_[0]\,
O => start_i_5_n_0
);
start_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => counter(7),
I1 => counter(0),
I2 => counter(10),
I3 => counter(12),
O => start_i_6_n_0
);
start_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => start_i_1_n_0,
Q => \^start\,
R => '0'
);
\state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FE560000"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state[1]_i_2_n_0\,
I2 => start_i_2_n_0,
I3 => \state_reg_n_0_[1]\,
I4 => rst,
I5 => vsync,
O => \state[0]_i_1_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E6E2"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => \state[1]_i_2_n_0\,
I2 => \state[1]_i_3_n_0\,
I3 => \state_reg_n_0_[0]\,
I4 => \state[1]_i_4_n_0\,
O => \state[1]_i_1_n_0\
);
\state[1]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => counter(2),
I1 => counter(1),
O => \state[1]_i_10_n_0\
);
\state[1]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(27),
I1 => counter(28),
O => \state[1]_i_11_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444F44444444"
)
port map (
I0 => \counter[31]_i_7_n_0\,
I1 => \h_count_reg[9]_i_6_n_0\,
I2 => \state[1]_i_5_n_0\,
I3 => \state[1]_i_6_n_0\,
I4 => \v_count_reg[9]_i_4_n_0\,
I5 => \state[1]_i_7_n_0\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => \v_count_reg[9]_i_7_n_0\,
I1 => \v_count_reg_reg__0\(9),
I2 => \v_count_reg_reg__0\(6),
I3 => \v_count_reg_reg__0\(5),
I4 => \v_count_reg_reg__0\(7),
I5 => \v_count_reg_reg__0\(8),
O => \state[1]_i_3_n_0\
);
\state[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAABAAAAAAAA"
)
port map (
I0 => \counter[31]_i_1_n_0\,
I1 => \state[1]_i_8_n_0\,
I2 => \state[1]_i_9_n_0\,
I3 => \state[1]_i_6_n_0\,
I4 => start_i_4_n_0,
I5 => \state[1]_i_7_n_0\,
O => \state[1]_i_4_n_0\
);
\state[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \state[1]_i_10_n_0\,
I1 => counter(7),
I2 => counter(5),
I3 => \h_count_reg[9]_i_2_n_0\,
I4 => \state[1]_i_9_n_0\,
I5 => \v_count_reg[9]_i_9_n_0\,
O => \state[1]_i_5_n_0\
);
\state[1]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(25),
I1 => counter(26),
I2 => \state[1]_i_11_n_0\,
I3 => counter(16),
I4 => counter(31),
I5 => \v_count_reg[9]_i_8_n_0\,
O => \state[1]_i_6_n_0\
);
\state[1]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => counter(18),
I1 => counter(17),
I2 => counter(19),
I3 => \v_count_reg[9]_i_10_n_0\,
I4 => counter(24),
O => \state[1]_i_7_n_0\
);
\state[1]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => counter(13),
I1 => counter(5),
I2 => \state_reg_n_0_[0]\,
I3 => \state_reg_n_0_[1]\,
I4 => counter(9),
I5 => counter(14),
O => \state[1]_i_8_n_0\
);
\state[1]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(30),
I1 => counter(29),
I2 => counter(4),
I3 => counter(8),
O => \state[1]_i_9_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => \state_reg_n_0_[0]\,
R => '0'
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => \state_reg_n_0_[1]\,
R => '0'
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \v_count_reg_reg__0\(0),
O => plusOp(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \v_count_reg_reg__0\(0),
I1 => \v_count_reg_reg__0\(1),
O => plusOp(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \v_count_reg_reg__0\(2),
I1 => \v_count_reg_reg__0\(0),
I2 => \v_count_reg_reg__0\(1),
O => plusOp(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \v_count_reg_reg__0\(3),
I1 => \v_count_reg_reg__0\(1),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(2),
O => plusOp(3)
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(4),
I1 => \v_count_reg_reg__0\(2),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(1),
I4 => \v_count_reg_reg__0\(3),
O => plusOp(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(5),
I1 => \v_count_reg_reg__0\(3),
I2 => \v_count_reg_reg__0\(1),
I3 => \v_count_reg_reg__0\(0),
I4 => \v_count_reg_reg__0\(2),
I5 => \v_count_reg_reg__0\(4),
O => plusOp(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \v_count_reg_reg__0\(6),
I1 => \v_count_reg[9]_i_7_n_0\,
I2 => \v_count_reg_reg__0\(5),
O => plusOp(6)
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \v_count_reg_reg__0\(7),
I1 => \v_count_reg_reg__0\(5),
I2 => \v_count_reg[9]_i_7_n_0\,
I3 => \v_count_reg_reg__0\(6),
O => plusOp(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(8),
I1 => \v_count_reg_reg__0\(6),
I2 => \v_count_reg[9]_i_7_n_0\,
I3 => \v_count_reg_reg__0\(5),
I4 => \v_count_reg_reg__0\(7),
O => plusOp(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \v_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \v_count_reg[9]_i_5_n_0\,
I3 => \v_count_reg[9]_i_6_n_0\,
I4 => \state[1]_i_3_n_0\,
O => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg[9]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(21),
I1 => counter(20),
I2 => counter(23),
I3 => counter(22),
O => \v_count_reg[9]_i_10_n_0\
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(9),
I1 => \v_count_reg_reg__0\(7),
I2 => \v_count_reg_reg__0\(8),
I3 => \v_count_reg_reg__0\(6),
I4 => \v_count_reg[9]_i_7_n_0\,
I5 => \v_count_reg_reg__0\(5),
O => plusOp(9)
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \v_count_reg[9]_i_8_n_0\,
I1 => counter(7),
I2 => counter(8),
I3 => \h_count_reg[9]_i_5_n_0\,
I4 => \v_count_reg[9]_i_9_n_0\,
I5 => \counter[31]_i_10_n_0\,
O => \v_count_reg[9]_i_3_n_0\
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(11),
I1 => counter(10),
I2 => counter(9),
I3 => counter(14),
I4 => counter(12),
I5 => counter(13),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => counter(28),
I1 => counter(27),
I2 => counter(29),
I3 => counter(30),
I4 => counter(31),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \v_count_reg[9]_i_10_n_0\,
I1 => counter(18),
I2 => counter(19),
I3 => counter(16),
I4 => counter(17),
O => \v_count_reg[9]_i_6_n_0\
);
\v_count_reg[9]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \v_count_reg_reg__0\(3),
I1 => \v_count_reg_reg__0\(1),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(2),
I4 => \v_count_reg_reg__0\(4),
O => \v_count_reg[9]_i_7_n_0\
);
\v_count_reg[9]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(6),
I1 => counter(15),
O => \v_count_reg[9]_i_8_n_0\
);
\v_count_reg[9]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF7F"
)
port map (
I0 => counter(3),
I1 => counter(0),
I2 => \state_reg_n_0_[1]\,
I3 => \state_reg_n_0_[0]\,
O => \v_count_reg[9]_i_9_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(0),
Q => \v_count_reg_reg__0\(0),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(1),
Q => \v_count_reg_reg__0\(1),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(2),
Q => \v_count_reg_reg__0\(2),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(3),
Q => \v_count_reg_reg__0\(3),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(4),
Q => \v_count_reg_reg__0\(4),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(5),
Q => \v_count_reg_reg__0\(5),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(6),
Q => \v_count_reg_reg__0\(6),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(7),
Q => \v_count_reg_reg__0\(7),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(8),
Q => \v_count_reg_reg__0\(8),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(9),
Q => \v_count_reg_reg__0\(9),
R => \counter[31]_i_1_n_0\
);
\xaddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(0),
Q => xaddr(0),
R => '0'
);
\xaddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(1),
Q => xaddr(1),
R => '0'
);
\xaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(2),
Q => xaddr(2),
R => '0'
);
\xaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(3),
Q => xaddr(3),
R => '0'
);
\xaddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(4),
Q => xaddr(4),
R => '0'
);
\xaddr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(5),
Q => xaddr(5),
R => '0'
);
\xaddr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(6),
Q => xaddr(6),
R => '0'
);
\xaddr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(7),
Q => xaddr(7),
R => '0'
);
\xaddr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(8),
Q => xaddr(8),
R => '0'
);
\xaddr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(9),
Q => xaddr(9),
R => '0'
);
\yaddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(0),
Q => yaddr(0),
R => '0'
);
\yaddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(1),
Q => yaddr(1),
R => '0'
);
\yaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(2),
Q => yaddr(2),
R => '0'
);
\yaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(3),
Q => yaddr(3),
R => '0'
);
\yaddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(4),
Q => yaddr(4),
R => '0'
);
\yaddr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(5),
Q => yaddr(5),
R => '0'
);
\yaddr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(6),
Q => yaddr(6),
R => '0'
);
\yaddr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(7),
Q => yaddr(7),
R => '0'
);
\yaddr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(8),
Q => yaddr(8),
R => '0'
);
\yaddr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(9),
Q => yaddr(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_ref_1_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_ref_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_ref_1_0 : entity is "system_vga_sync_ref_1_0,vga_sync_ref,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_ref_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_ref_1_0 : entity is "vga_sync_ref,Vivado 2016.4";
end system_vga_sync_ref_1_0;
architecture STRUCTURE of system_vga_sync_ref_1_0 is
begin
U0: entity work.system_vga_sync_ref_1_0_vga_sync_ref
port map (
active => active,
clk => clk,
rst => rst,
start => start,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1294.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p06n01i01294ent IS
END c08s04b00x00p06n01i01294ent;
ARCHITECTURE c08s04b00x00p06n01i01294arch OF c08s04b00x00p06n01i01294ent IS
type BIT_VECTOR is array (integer range <>) of BIT;
signal DID : BIT_VECTOR(0 to 7);
BEGIN
TESTING: PROCESS
variable NUM1 : BIT_VECTOR(0 to 7) := B"01010101";
BEGIN
DID <= NUM1;
wait on DID;
assert NOT( DID = B"01010101" )
report "***PASSED TEST: c08s04b00x00p06n01i01294"
severity NOTE;
assert ( DID = B"01010101" )
report "***FAILED TEST: c08s04b00x00p06n01i01294 - Type of the right hand and left hand side of the signal assignment statement must be the same"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p06n01i01294arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1294.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p06n01i01294ent IS
END c08s04b00x00p06n01i01294ent;
ARCHITECTURE c08s04b00x00p06n01i01294arch OF c08s04b00x00p06n01i01294ent IS
type BIT_VECTOR is array (integer range <>) of BIT;
signal DID : BIT_VECTOR(0 to 7);
BEGIN
TESTING: PROCESS
variable NUM1 : BIT_VECTOR(0 to 7) := B"01010101";
BEGIN
DID <= NUM1;
wait on DID;
assert NOT( DID = B"01010101" )
report "***PASSED TEST: c08s04b00x00p06n01i01294"
severity NOTE;
assert ( DID = B"01010101" )
report "***FAILED TEST: c08s04b00x00p06n01i01294 - Type of the right hand and left hand side of the signal assignment statement must be the same"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p06n01i01294arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1294.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p06n01i01294ent IS
END c08s04b00x00p06n01i01294ent;
ARCHITECTURE c08s04b00x00p06n01i01294arch OF c08s04b00x00p06n01i01294ent IS
type BIT_VECTOR is array (integer range <>) of BIT;
signal DID : BIT_VECTOR(0 to 7);
BEGIN
TESTING: PROCESS
variable NUM1 : BIT_VECTOR(0 to 7) := B"01010101";
BEGIN
DID <= NUM1;
wait on DID;
assert NOT( DID = B"01010101" )
report "***PASSED TEST: c08s04b00x00p06n01i01294"
severity NOTE;
assert ( DID = B"01010101" )
report "***FAILED TEST: c08s04b00x00p06n01i01294 - Type of the right hand and left hand side of the signal assignment statement must be the same"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p06n01i01294arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1368.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01368ent IS
END c08s05b00x00p03n01i01368ent;
ARCHITECTURE c08s05b00x00p03n01i01368arch OF c08s05b00x00p03n01i01368ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr1 : st_arr1 := c_st_arr1_1 ;
--
BEGIN
v_st_arr1(st_arr1'Left) :=
c_st_arr1_2(st_arr1'Right) ;
assert NOT(v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01368"
severity NOTE;
assert (v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01368 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01368arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1368.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01368ent IS
END c08s05b00x00p03n01i01368ent;
ARCHITECTURE c08s05b00x00p03n01i01368arch OF c08s05b00x00p03n01i01368ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr1 : st_arr1 := c_st_arr1_1 ;
--
BEGIN
v_st_arr1(st_arr1'Left) :=
c_st_arr1_2(st_arr1'Right) ;
assert NOT(v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01368"
severity NOTE;
assert (v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01368 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01368arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1368.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01368ent IS
END c08s05b00x00p03n01i01368ent;
ARCHITECTURE c08s05b00x00p03n01i01368arch OF c08s05b00x00p03n01i01368ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr1 : st_arr1 := c_st_arr1_1 ;
--
BEGIN
v_st_arr1(st_arr1'Left) :=
c_st_arr1_2(st_arr1'Right) ;
assert NOT(v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01368"
severity NOTE;
assert (v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01368 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01368arch;
|
-- revision history:
-- 07.08.2015 Patrick Appenheimer created
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library WORK;
use WORK.cpu_pack.all;
entity tb_fsm is
end entity tb_fsm;
architecture behav_tb_fsm of tb_fsm is
-- -------- SIMULATION CONSTANTS -----
constant CLK_TIME : time := 2500 ps;
constant RST_TIME : time := 15 ns;
-- -------- FSM INTERFACE -----------------
signal clk : std_logic := '0';
signal rst : std_logic;
signal instr_in : std_logic_vector(31 downto 0);
signal fsm_busy: std_logic;
signal nextfsm_busy: std_logic;
signal nextfsm_state: std_logic_vector(4 downto 0);
signal output_buffer : std_logic_vector(29 downto 0);
signal instr : std_logic_vector(31 downto 0);
signal test_instr_stall : std_logic;
signal test_data_stall : std_logic;
-- ------ SIMULATION CONTROL ---------------
signal sim_finish : std_logic;
begin
-- GENERAL CONTROL SIGNALS
clk <= not clk after CLK_TIME;
rst <= '1', '0' after RST_TIME;
-- FSM
u1_fsm : entity work.fsm(behavioral)
port map(clk, rst, fsm_busy, nextfsm_busy, nextfsm_state, output_buffer, instr_in, test_instr_stall, test_data_stall);
-- TEST PROCESS
test_process:
process
begin
sim_finish <= '0';
wait for 1 ns;
sim_finish <= '1';
rst <= '1';
--usually the first instruction address should be dropping out at
-- instr_addr and it should be 00000000, so we return an instruction
-- and set the ID's muxes for correct decoding
-- To test:
-- instr_address: 00000004
-- if: Instruction 1: LUI $gp, 1
instr_in <= x"3c1c0001";
--id: Nothing
--id_regdest_mux <= "00";
--id_regshift_mux <= "00";
--in_mux_pc <= '0';
--ex: Nothing
--exc_mux1 <= "10";
--exc_mux2 <= "00";
--alu_op <= "000001";
-- mem: Nothing
--memstg_mux <= '1';
-- wb: Nothing
--id_enable_regs <= '0';
wait for clk_time;
-- To test:
-- shift_2 : 10;
-- imm_2: 00000001
-- regdest_2: 1C
-- instr_address: 00000004
-- ip_2 : 00000000
instr_in <= x"279c8070"; -- Instruction 2: ADDIU $gp, $gp, -32656
--id: Instruction 1 (LUI $gp, 1)
--id_regdest_mux <= "10";
--id_regshift_mux <= "01";
--in_mux_pc <= '0';
--ex: Nothing
--exc_mux1 <= "10";
--exc_mux2 <= "00";
--alu_op <= "000001";
-- mem: Nothing
--memstg_mux <= '1';
-- wb: Nothing
--id_enable_regs <= '0';
wait for clk_time;
-- To test:
-- regdest_2: 1C
-- reg_a_2: 00010000;
-- imm_2: 8070
-- instr_address: 00000008
-- ip_2 : 00000004
-- alu_result_3: 000010000
-- regdest_3: 1C
-- ip_3 : 00000000
instr_in <= x"08000004"; -- Instruction 3: J 0x10
--id: Instruction 2 (ADDIU $gp, $gp, -32656)
--id_regdest_mux <= "10";
--id_regshift_mux <= "00";
--in_mux_pc <= '0';
--ex: Instruction 1 (LUI $gp, 1)
--exc_mux1 <= "00";
--exc_mux2 <= "01";
--alu_op <= "000100";
-- mem: Nothing
--memstg_mux <= '1';
-- wb: Nothing
--id_enable_regs <= '0';
wait for clk_time;
wait;
end process;
end architecture behav_tb_fsm;
|
-------------------------------------------------------------------------------
-- Entity: gpio
-- Author: Waj
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- GPIO block for simple von-Neumann MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: ... tbd ...
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity gpio is
port(rst : in std_logic;
clk : in std_logic;
-- GPIO bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus;
-- GPIO pin signals
gpio_in : in std_logic_vector(DW-1 downto 0);
gpio_out : out std_logic_vector(DW-1 downto 0);
gpio_out_enb : out std_logic_vector(DW-1 downto 0);
-- Encoder pin signals
enc_a : in std_logic;
enc_b : in std_logic
);
end gpio;
architecture rtl of gpio is
-- address select signal
signal addr_sel : t_gpio_addr_sel;
-- peripheral registers - gpio
signal data_in_reg : std_logic_vector(DW-1 downto 0);
signal data_out_reg : std_logic_vector(DW-1 downto 0);
signal out_enb_reg : std_logic_vector(DW-1 downto 0);
-- gpio input synchronisation
signal sync_gpio_in : std_logic_vector(DW-1 downto 0);
-- peripheral registers - encoder
signal enc_capture : std_logic;
signal enc_capt_reg : std_logic;
signal enc_capt_prev: std_logic;
signal enc_buf_dist : std_logic_vector(DW-1 downto 0);
signal enc_buf_pos : std_logic_vector(DW-1 downto 0);
signal enc_buf_neg : std_logic_vector(DW-1 downto 0);
-- encoder counter registers
signal enc_cnt_dist : std_logic_vector(DW-1 downto 0);
signal enc_cnt_pos : std_logic_vector(DW-1 downto 0);
signal enc_cnt_neg : std_logic_vector(DW-1 downto 0);
-- encoder count enable
signal enc_cnt_enb_pos : std_logic;
signal enc_cnt_enb_neg : std_logic;
-- encoder fsm
type t_enc_state is (st_active, st_idle_pos, st_idle_neg);
signal c_st : t_enc_state;
signal n_st : t_enc_state;
begin
-- output ssignment
gpio_out <= data_out_reg;
gpio_out_enb <= out_enb_reg;
-----------------------------------------------------------------------------
-- Input register
-----------------------------------------------------------------------------
P_in: process(clk)
begin
if rst = '1' then
sync_gpio_in <= (others=>'0');
elsif rising_edge(clk) then
sync_gpio_in <= gpio_in;
data_in_reg <= sync_gpio_in;
end if;
end process;
-----------------------------------------------------------------------------
-- Encoder fsm
-----------------------------------------------------------------------------
-- Memorizing process
p_enc_fsm_seq: process(rst, clk)
begin
if rst = '1' then
c_st <= st_active;
elsif rising_edge(clk) then
c_st <= n_st;
end if;
end process;
-- Combinatoric process
p_enc_fsm_comb: process(enc_a, enc_b, c_st)
begin
-- default assignments
n_st <= c_st;
enc_cnt_enb_pos <= '0';
enc_cnt_enb_neg <= '0';
-- states
case c_st is
when st_active =>
if enc_a = '0' and enc_b = '0' then
n_st <= st_idle_pos;
end if;
when st_idle_pos =>
if enc_a = '1' and enc_b = '0' then
n_st <= st_idle_neg;
elsif enc_a = '1' and enc_b = '1' then
enc_cnt_enb_pos <= '1';
n_st <= st_active;
end if;
when st_idle_neg =>
if enc_a = '0' and enc_b = '1' then
n_st <= st_idle_pos;
elsif enc_a = '1' and enc_b = '1' then
enc_cnt_enb_neg <= '1';
n_st <= st_active;
end if;
when others =>
n_st <= st_active;
end case;
end process;
-----------------------------------------------------------------------------
-- Encoder counter
-----------------------------------------------------------------------------
p_enc_cnt: process(rst, clk)
begin
if rst = '1' then
-- clear counter registers
enc_cnt_dist <= (others => '0');
enc_cnt_pos <= (others => '0');
enc_cnt_neg <= (others => '0');
-- clear buffer registers
enc_buf_dist <= (others => '0');
enc_buf_pos <= (others => '0');
enc_buf_neg <= (others => '0');
elsif rising_edge(clk) then
if enc_capture = '1' then
-- capture occured -> copy counter to buffer and reset counter
if enc_cnt_enb_pos = '0' and enc_cnt_enb_neg = '0' then -- no count
-- counter registers
enc_cnt_dist <= (others => '0');
enc_cnt_pos <= (others => '0');
enc_cnt_neg <= (others => '0');
-- buffer registers
enc_buf_dist <= enc_cnt_dist;
enc_buf_pos <= enc_cnt_pos;
enc_buf_neg <= enc_cnt_neg;
elsif enc_cnt_enb_pos = '0' and enc_cnt_enb_neg = '1' then -- neg count
-- counter registers
enc_cnt_dist <= (others => '0');
enc_cnt_pos <= (others => '0');
enc_cnt_neg <= (others => '0');
-- buffer registers
enc_buf_dist <= std_logic_vector(unsigned(enc_cnt_dist) - 1);
enc_buf_pos <= enc_cnt_pos;
enc_buf_neg <= std_logic_vector(unsigned(enc_cnt_neg) + 1);
elsif enc_cnt_enb_pos = '1' and enc_cnt_enb_neg = '0' then -- pos count
-- counter registers
enc_cnt_dist <= (others => '0');
enc_cnt_pos <= (others => '0');
enc_cnt_neg <= (others => '0');
-- buffer registers
enc_buf_dist <= std_logic_vector(unsigned(enc_cnt_dist) + 1);
enc_buf_pos <= std_logic_vector(unsigned(enc_cnt_pos) + 1);
enc_buf_neg <= enc_cnt_neg;
else -- pos and neg count (currently impossible)
-- counter registers
enc_cnt_dist <= (others => '0');
enc_cnt_pos <= (others => '0');
enc_cnt_neg <= (others => '0');
-- buffer registers
enc_buf_dist <= enc_cnt_dist;
enc_buf_pos <= std_logic_vector(unsigned(enc_cnt_pos) + 1);
enc_buf_neg <= std_logic_vector(unsigned(enc_cnt_neg) + 1);
end if;
else -- no capture occured
if enc_cnt_enb_pos = '0' and enc_cnt_enb_neg = '0' then -- no count
-- counter registers
enc_cnt_dist <= enc_cnt_dist;
enc_cnt_pos <= enc_cnt_pos;
enc_cnt_neg <= enc_cnt_neg;
-- buffer registers
enc_buf_dist <= enc_buf_dist;
enc_buf_pos <= enc_buf_pos;
enc_buf_neg <= enc_buf_neg;
elsif enc_cnt_enb_pos = '0' and enc_cnt_enb_neg = '1' then -- neg count
-- counter registers
enc_cnt_dist <= std_logic_vector(unsigned(enc_cnt_dist) - 1);
enc_cnt_pos <= enc_cnt_pos;
enc_cnt_neg <= std_logic_vector(unsigned(enc_cnt_neg) + 1);
-- buffer registers
enc_buf_dist <= enc_buf_dist;
enc_buf_pos <= enc_buf_pos;
enc_buf_neg <= enc_buf_neg;
elsif enc_cnt_enb_pos = '1' and enc_cnt_enb_neg = '0' then -- pos count
-- counter registers
enc_cnt_dist <= std_logic_vector(unsigned(enc_cnt_dist) + 1);
enc_cnt_pos <= std_logic_vector(unsigned(enc_cnt_pos) + 1);
enc_cnt_neg <= enc_cnt_neg;
-- buffer registers
enc_buf_dist <= enc_buf_dist;
enc_buf_pos <= enc_buf_pos;
enc_buf_neg <= enc_buf_neg;
else -- pos and neg count (with current state machine impossible)
-- counter registers
enc_cnt_dist <= enc_cnt_dist;
enc_cnt_pos <= std_logic_vector(unsigned(enc_cnt_pos) + 1);
enc_cnt_neg <= std_logic_vector(unsigned(enc_cnt_neg) + 1);
-- buffer registers
enc_buf_dist <= enc_buf_dist;
enc_buf_pos <= enc_buf_pos;
enc_buf_neg <= enc_buf_neg;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Encoder - Capture signal
-----------------------------------------------------------------------------
p_enc_capture: process(clk, rst)
begin
if rst = '1' then
enc_capture <= '0';
enc_capt_prev <= '0';
else
if rising_edge(clk) then
if enc_capt_prev = '0' and enc_capt_reg = '1' then
-- rising edge on capture
enc_capture <= '1';
else
enc_capture <= '0';
end if;
enc_capt_prev <= enc_capt_reg;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Address Decoding (combinationally)
-----------------------------------------------------------------------------
process(bus_in.addr)
begin
case bus_in.addr is
-- Port 1 addresses -----------------------------------------------------
when c_addr_gpio_data_in => addr_sel <= gpio_data_in;
when c_addr_gpio_data_out => addr_sel <= gpio_data_out;
when c_addr_gpio_out_enb => addr_sel <= gpio_enb;
-- Encoder adresses -----------------------------------------------------
when c_addr_enc_ctrl => addr_sel <= enc_ctrl;
when c_addr_enc_dist => addr_sel <= enc_dist;
when c_addr_enc_pos => addr_sel <= enc_pos;
when c_addr_enc_neg => addr_sel <= enc_neg;
-- unused addresses -----------------------------------------------------
when others => addr_sel <= none;
end case;
end process;
-----------------------------------------------------------------------------
-- Read Access (R and R/W registers)
-----------------------------------------------------------------------------
P_read: process(clk)
begin
if rising_edge(clk) then
-- default assignment
bus_out.data <= (others => '0');
-- use address select signal
case addr_sel is
when gpio_data_in => bus_out.data <= data_in_reg;
when gpio_data_out => bus_out.data <= data_out_reg;
when gpio_enb => bus_out.data <= out_enb_reg;
when enc_ctrl => bus_out.data <= "101010100101010" & enc_capture;
when enc_dist => bus_out.data <= enc_buf_dist;
when enc_pos => bus_out.data <= enc_buf_pos;
when enc_neg => bus_out.data <= enc_buf_neg;
when others => null;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- Write Access (R/W registers only)
-----------------------------------------------------------------------------
P_write: process(clk, rst)
begin
if rst = '1' then
data_out_reg <= (others => '0');
out_enb_reg <= (others => '0'); -- output disabled per default
enc_capt_reg <= '0';
elsif rising_edge(clk) then
if bus_in.wr_enb = '1' then
-- use address select signal
case addr_sel is
when gpio_data_out => data_out_reg <= bus_in.data;
when gpio_enb => out_enb_reg <= bus_in.data;
when enc_ctrl => enc_capt_reg <= bus_in.data(0);
when others => null;
end case;
else
enc_capt_reg <= '0';
end if;
end if;
end process;
end rtl;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\hdlcodercpu_eml\output_enable.vhd
-- Created: 2014-08-26 11:41:14
--
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: output_enable
-- Source Path: hdlcodercpu_eml/CPU_Subsystem_8_bit/output_enable
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY output_enable IS
PORT( u : IN std_logic_vector(7 DOWNTO 0); -- int8
enable : IN std_logic;
y : OUT std_logic_vector(7 DOWNTO 0) -- int8
);
END output_enable;
ARCHITECTURE rtl OF output_enable IS
-- Signals
SIGNAL u_signed : signed(7 DOWNTO 0); -- int8
SIGNAL y_tmp : signed(7 DOWNTO 0); -- int8
BEGIN
u_signed <= signed(u);
output_enable_1_output : PROCESS (u_signed, enable)
BEGIN
--MATLAB Function 'CPU_Subsystem_8_bit/output_enable': '<S12>:1'
-- to the pin-out
-- HDL specific fimath
--'<S12>:1:12'
y_tmp <= to_signed(2#00000000#, 8);
IF enable = '1' THEN
--'<S12>:1:14'
--'<S12>:1:15'
y_tmp <= u_signed;
END IF;
END PROCESS output_enable_1_output;
y <= std_logic_vector(y_tmp);
END rtl;
|
-- Generation properties:
-- Format : hierarchical
-- Generic mappings : exclude
-- Leaf-level entities : direct binding
-- Regular libraries : use library name
-- View name : include
--
LIBRARY lab9_new_lib;
CONFIGURATION execute_struct_config OF execute IS
FOR struct
FOR ALL : mini_ALU
USE CONFIGURATION lab9_new_lib.mini_ALU_struct_config;
END FOR;
FOR ALL : mini_Shifter
USE ENTITY lab9_new_lib.mini_Shifter(Behavior);
END FOR;
END FOR;
END execute_struct_config;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net4,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net3,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias4,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net1,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net1,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:29:36 11/21/2013
-- Design Name:
-- Module Name: MUX_3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX_3 is
Port ( SRC_1 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_3 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SELEC : in STD_LOGIC_VECTOR (1 downto 0) := "00";
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO
);
end MUX_3;
architecture Behavioral of MUX_3 is
begin
process(SRC_1, SRC_2, SRC_3, SELEC)
begin
case SELEC is
when "00" =>
OUTPUT <= SRC_1;
when "01" =>
OUTPUT <= SRC_2;
when "10" =>
OUTPUT <= SRC_3;
when others =>
OUTPUT <= HIGH_RESIST;
end case;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:29:36 11/21/2013
-- Design Name:
-- Module Name: MUX_3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX_3 is
Port ( SRC_1 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_3 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SELEC : in STD_LOGIC_VECTOR (1 downto 0) := "00";
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO
);
end MUX_3;
architecture Behavioral of MUX_3 is
begin
process(SRC_1, SRC_2, SRC_3, SELEC)
begin
case SELEC is
when "00" =>
OUTPUT <= SRC_1;
when "01" =>
OUTPUT <= SRC_2;
when "10" =>
OUTPUT <= SRC_3;
when others =>
OUTPUT <= HIGH_RESIST;
end case;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Mihaita Nagy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 18:46:55 03/05/2013
-- Design Name:
-- Module Name: pwm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This module represents the 8-bit PWM component, used by the RgbLed module
-- to generate the sweeping colors
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity Pwm is
port(
clk_i : in std_logic; -- system clock = 100MHz
data_i : in std_logic_vector(7 downto 0); -- the number to be modulated
pwm_o : out std_logic
);
end Pwm;
architecture Behavioral of Pwm is
signal cnt : std_logic_vector(7 downto 0);
begin
COUNT: process(clk_i)
begin
if rising_edge(clk_i) then
cnt <= cnt + '1';
end if;
end process COUNT;
COMPARE: process(data_i, cnt)
begin
if unsigned(cnt) < unsigned(data_i) then
pwm_o <= '1';
else
pwm_o <= '0';
end if;
end process COMPARE;
end Behavioral;
|
package pkg is
end pkg;
|
package pkg is
end pkg;
|
package pkg is
end pkg;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.2
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fir_hw_smpl_V_ram is
generic(
mem_type : string := "block";
dwidth : integer := 18;
awidth : integer := 7;
mem_size : integer := 128
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of fir_hw_smpl_V_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity fir_hw_smpl_V is
generic (
DataWidth : INTEGER := 18;
AddressRange : INTEGER := 128;
AddressWidth : INTEGER := 7);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of fir_hw_smpl_V is
component fir_hw_smpl_V_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
fir_hw_smpl_V_ram_U : component fir_hw_smpl_V_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
|
--!
--! @file: pkg_adder.vhd
--! @brief: package that holds full adder
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
package pkg_adder is
component full_adder is
port (
a, b: std_logic;
cin: in std_logic;
s: out std_logic;
cout: out std_logic);
end component full_adder;
end package pkg_adder;
------------------------------
package body pkg_adder is
--functionsdefinitions, deferredconstants. they need to have the full subprogram header exactly as it appears in package
end package body pkg_adder;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Entity: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2017 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.io.all;
entity clknet_ClockNetwork_Atlys is
generic (
DEBUG : BOOLEAN := FALSE;
CLOCK_IN_FREQ : FREQ := 100 MHz
);
port (
ClockIn_100MHz : in STD_LOGIC;
ClockNetwork_Reset : in STD_LOGIC;
ClockNetwork_ResetDone : out STD_LOGIC;
Control_Clock_100MHz : out STD_LOGIC;
Clock_200MHz : out STD_LOGIC;
Clock_125MHz : out STD_LOGIC;
Clock_100MHz : out STD_LOGIC;
Clock_10MHz : out STD_LOGIC;
Clock_Stable_200MHz : out STD_LOGIC;
Clock_Stable_125MHz : out STD_LOGIC;
Clock_Stable_100MHz : out STD_LOGIC;
Clock_Stable_10MHz : out STD_LOGIC
);
end entity;
-- DCM - clock wizard report
--
-- Output Output Phase Duty Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)
-------------------------------------------------------------------------------
-- CLK_OUT0 100.000 0.000 50.0 200.000 150.000
-- CLK_OUT1 200.000 0.000 50.0 300.000 150.000
-- CLK_OUT2 125.000 0.000 50.0 360.000 150.000
-- CLK_OUT3 10.000 0.000 50.0 300.000 150.000
--
architecture rtl of clknet_ClockNetwork_Atlys is
attribute KEEP : BOOLEAN;
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
-- control clock: 100 MHz
-- slowest output clock: 10 MHz
-- worst case delay: (Control_Clock freq / slowest clock in MHz) * register stages + safety
-- => 24 (100 MHz / 10 MHz) * 2 register stages + 4
constant CMB_DELAY_CYCLES : POSITIVE := integer(real(CLOCK_IN_FREQ / 10 MHz) * 2.0 + 4.0);
signal ClkNet_Reset : STD_LOGIC;
signal DCM_Reset : STD_LOGIC;
signal DCM_Reset_clr : STD_LOGIC;
signal DCM_ResetState : STD_LOGIC := '0';
signal DCM_Reset_delayed : STD_LOGIC_VECTOR(CMB_DELAY_CYCLES - 1 DOWNTO 0);
signal DCM_Locked_async : STD_LOGIC;
signal DCM_Locked : STD_LOGIC;
signal DCM_Locked_d : STD_LOGIC := '0';
signal DCM_Locked_re : STD_LOGIC;
signal DCM_LockedState : STD_LOGIC := '0';
signal Locked : STD_LOGIC;
signal Reset : STD_LOGIC;
signal Control_Clock : STD_LOGIC;
signal Control_Clock_BUFG : STD_LOGIC;
signal DCM_Clock_10MHz : STD_LOGIC;
signal DCM_Clock_100MHz : STD_LOGIC;
signal DCM_Clock_125MHz : STD_LOGIC;
signal DCM_Clock_200MHz : STD_LOGIC;
signal DCM_Clock_10MHz_BUFG : STD_LOGIC;
signal DCM_Clock_100MHz_BUFG : STD_LOGIC;
signal DCM_Clock_125MHz_BUFG : STD_LOGIC;
signal DCM_Clock_200MHz_BUFG : STD_LOGIC;
attribute KEEP of DCM_Clock_10MHz_BUFG : signal is DEBUG;
attribute KEEP of DCM_Clock_100MHz_BUFG : signal is DEBUG;
attribute KEEP of DCM_Clock_125MHz_BUFG : signal is DEBUG;
attribute KEEP of DCM_Clock_200MHz_BUFG : signal is DEBUG;
begin
-- ==================================================================
-- ResetControl
-- ==================================================================
-- synchronize external (async) ClockNetwork_Reset and internal (but async) DCM_Locked signals to "Control_Clock" domain
syncControlClock: entity PoC.sync_Bits_Xilinx
generic map (
BITS => 2 -- number of BITS to synchronize
)
port map (
Clock => Control_Clock, -- Clock to be synchronized to
Input(0) => ClockNetwork_Reset, -- Data to be synchronized
Input(1) => DCM_Locked_async, --
Output(0) => ClkNet_Reset, -- synchronized data
Output(1) => DCM_Locked --
);
-- clear reset signals, if external Reset is low and CMB (clock modifying block) noticed reset -> locked = low
DCM_Reset_clr <= ClkNet_Reset nor DCM_Locked;
-- detect rising edge on CMB locked signals
DCM_Locked_d <= DCM_Locked when rising_edge(Control_Clock);
DCM_Locked_re <= not DCM_Locked_d and DCM_Locked;
-- RS-FF Q RST SET CLK
-- hold reset until external reset goes low and CMB noticed reset
DCM_ResetState <= ffrs(q => DCM_ResetState, rst => DCM_Reset_clr, set => ClkNet_Reset) when rising_edge(Control_Clock);
-- deassert *_LockedState, if CMBs are going to be reseted; assert it if *_Locked is high again
DCM_LockedState <= ffrs(q => DCM_LockedState, rst => DCM_Reset, set => DCM_Locked_re) when rising_edge(Control_Clock);
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
DCM_Reset_delayed <= sr_left(DCM_Reset_delayed, DCM_ResetState) when rising_edge(Control_Clock);
DCM_Reset <= DCM_Reset_delayed(DCM_Reset_delayed'high);
Locked <= DCM_LockedState and '1'; --PLL_LockedState;
ClockNetwork_ResetDone <= Locked;
-- ==================================================================
-- ClockBuffers
-- ==================================================================
-- Control_Clock
BUFR_Control_Clock : BUFG
port map (
I => ClockIn_100MHz,
O => Control_Clock_BUFG
);
Control_Clock <= Control_Clock_BUFG;
-- 10 MHz BUFG
BUFG_DCM_Clock_10MHz : BUFG
port map (
I => DCM_Clock_10MHz,
O => DCM_Clock_10MHz_BUFG
);
-- 100 MHz BUFG
BUFG_DCM_Clock_100MHz : BUFG
port map (
I => DCM_Clock_100MHz,
O => DCM_Clock_100MHz_BUFG
);
-- 125 MHz BUFG
BUFG_DCM_Clock_125MHz : BUFG
port map (
I => DCM_Clock_125MHz,
O => DCM_Clock_125MHz_BUFG
);
-- 200 MHz BUFG
BUFG_DCM_Clock_200MHz : BUFG
port map (
I => DCM_Clock_200MHz,
O => DCM_Clock_200MHz_BUFG
);
-- ==================================================================
-- Mixed-Mode Clock Manager (DCM)
-- ==================================================================
System_DCM : DCM_SP
generic map (
STARTUP_WAIT => false,
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS"
PHASE_SHIFT => 0,
CLKIN_PERIOD => to_real(to_time(CLOCK_IN_FREQ), 1.0 ns),
CLKIN_DIVIDE_BY_2 => FALSE,
CLK_FEEDBACK => "1X",
CLKOUT_PHASE_SHIFT => "NONE",
CLKDV_DIVIDE => 10.0,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5
)
port map (
RST => DCM_Reset,
CLKIN => ClockIn_100MHz,
CLKFB => DCM_Clock_100MHz_BUFG,
CLK0 => DCM_Clock_100MHz,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => DCM_Clock_200MHz,
CLK2X180 => open,
CLKFX => DCM_Clock_125MHz,
CLKFX180 => open,
CLKDV => DCM_Clock_10MHz,
-- DCM status
LOCKED => DCM_Locked_async,
STATUS => open,
-- Dynamic Phase Shift Port
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
DSSEN => '0'
);
Control_Clock_100MHz <= Control_Clock_BUFG;
Clock_200MHz <= DCM_Clock_200MHz_BUFG;
Clock_125MHz <= DCM_Clock_125MHz_BUFG;
Clock_100MHz <= DCM_Clock_100MHz_BUFG;
Clock_10MHz <= DCM_Clock_10MHz_BUFG;
-- synchronize internal Locked signal to output clock domains
syncLocked200MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_200MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_200MHz -- synchronized data
);
syncLocked125MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_125MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_125MHz -- synchronized data
);
syncLocked100MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_100MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_100MHz -- synchronized data
);
syncLocked10MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_10MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_10MHz -- synchronized data
);
end architecture;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_04a is
end entity inline_04a;
architecture test of inline_04a is
-- code from book
function vector_multiply ( p : real_vector; r : real ) return real_vector is
variable result : real_vector(p'range);
begin
for index in p'range loop
result(index) := p(index) * r;
end loop;
return result;
end function vector_multiply;
--
quantity scale_factor : real;
quantity source_position, scaled_position : real_vector(1 to 3);
-- end code from book
begin
-- code from book
scaled_position == vector_multiply ( source_position, scale_factor );
-- end code from book
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_04a is
end entity inline_04a;
architecture test of inline_04a is
-- code from book
function vector_multiply ( p : real_vector; r : real ) return real_vector is
variable result : real_vector(p'range);
begin
for index in p'range loop
result(index) := p(index) * r;
end loop;
return result;
end function vector_multiply;
--
quantity scale_factor : real;
quantity source_position, scaled_position : real_vector(1 to 3);
-- end code from book
begin
-- code from book
scaled_position == vector_multiply ( source_position, scale_factor );
-- end code from book
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_04a is
end entity inline_04a;
architecture test of inline_04a is
-- code from book
function vector_multiply ( p : real_vector; r : real ) return real_vector is
variable result : real_vector(p'range);
begin
for index in p'range loop
result(index) := p(index) * r;
end loop;
return result;
end function vector_multiply;
--
quantity scale_factor : real;
quantity source_position, scaled_position : real_vector(1 to 3);
-- end code from book
begin
-- code from book
scaled_position == vector_multiply ( source_position, scale_factor );
-- end code from book
end architecture test;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SubBytes_module is
Generic ( DATA_LENGTH : integer := 128 );
Port ( data_out : out STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
finish : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
start : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_LOGIC);
end SubBytes_module;
architecture RTL of SubBytes_module is
-----------------------------
--------- CONSTANTS ---------
-----------------------------
constant BYTES_COUNT : integer := 16;
constant BYTE_LENGTH : integer := 8;
-----------------------------
----------- TYPES -----------
-----------------------------
type REG_SBOX_VALUES is array (BYTES_COUNT-1 downto 0) of std_logic_vector (BYTE_LENGTH-1 downto 0);
-----------------------------
---------- SIGNALS ----------
-----------------------------
-- Memory to store 16 bytes
signal bytes_memory_in : REG_SBOX_VALUES;
signal bytes_memory_out : REG_SBOX_VALUES;
-- Managed signal
signal start_sbox_module : std_logic;
signal finish_sbox_module_0 : std_logic;
signal finish_sbox_module_1 : std_logic;
signal finish_sbox_module_2 : std_logic;
signal finish_sbox_module_3 : std_logic;
signal finish_sbox_module_4 : std_logic;
signal finish_sbox_module_5 : std_logic;
signal finish_sbox_module_6 : std_logic;
signal finish_sbox_module_7 : std_logic;
signal finish_sbox_module_8 : std_logic;
signal finish_sbox_module_9 : std_logic;
signal finish_sbox_module_10 : std_logic;
signal finish_sbox_module_11 : std_logic;
signal finish_sbox_module_12 : std_logic;
signal finish_sbox_module_13 : std_logic;
signal finish_sbox_module_14 : std_logic;
signal finish_sbox_module_15 : std_logic;
signal finish_all_sbox : std_logic;
-----------------------------
--------- COMPONENTS --------
-----------------------------
component SBox_module is
Generic ( BYTE_LENGTH : integer := 8 );
Port ( data_out : out STD_LOGIC_VECTOR (BYTE_LENGTH-1 downto 0);
finish : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (BYTE_LENGTH-1 downto 0);
start : in STD_LOGIC);
end component SBox_module;
begin
-- Initialize and Reset process
reset_n_init_process : process(reset)
begin
if(rising_edge(reset)) then
bytes_memory_in(BYTES_COUNT-1 downto 0) <= (others => X"0");
start_sbox_module <= '0';
finish_sbox_module_0 <= '0';
finish_sbox_module_1 <= '0';
finish_sbox_module_2 <= '0';
finish_sbox_module_3 <= '0';
finish_sbox_module_4 <= '0';
finish_sbox_module_5 <= '0';
finish_sbox_module_6 <= '0';
finish_sbox_module_7 <= '0';
finish_sbox_module_8 <= '0';
finish_sbox_module_9 <= '0';
finish_sbox_module_10 <= '0';
finish_sbox_module_11 <= '0';
finish_sbox_module_12 <= '0';
finish_sbox_module_13 <= '0';
finish_sbox_module_14 <= '0';
finish_sbox_module_15 <= '0';
end if;
end process reset_n_init_process;
-- Structure of signals transmission
bytes_memory_in(0) <= data_in(BYTE_LENGTH-1 downto BYTE_LENGTH-8) when rising_edge(start);
bytes_memory_in(1) <= data_in(BYTE_LENGTH*2-1 downto BYTE_LENGTH*2-8) when rising_edge(start);
bytes_memory_in(2) <= data_in(BYTE_LENGTH*3-1 downto BYTE_LENGTH*3-8) when rising_edge(start);
bytes_memory_in(3) <= data_in(BYTE_LENGTH*4-1 downto BYTE_LENGTH*4-8) when rising_edge(start);
bytes_memory_in(4) <= data_in(BYTE_LENGTH*5-1 downto BYTE_LENGTH*5-8) when rising_edge(start);
bytes_memory_in(5) <= data_in(BYTE_LENGTH*6-1 downto BYTE_LENGTH*6-8) when rising_edge(start);
bytes_memory_in(6) <= data_in(BYTE_LENGTH*7-1 downto BYTE_LENGTH*7-8) when rising_edge(start);
bytes_memory_in(7) <= data_in(BYTE_LENGTH*8-1 downto BYTE_LENGTH*8-8) when rising_edge(start);
bytes_memory_in(8) <= data_in(BYTE_LENGTH*9-1 downto BYTE_LENGTH*9-8) when rising_edge(start);
bytes_memory_in(9) <= data_in(BYTE_LENGTH*10-1 downto BYTE_LENGTH*10-8) when rising_edge(start);
bytes_memory_in(10) <= data_in(BYTE_LENGTH*11-1 downto BYTE_LENGTH*11-8) when rising_edge(start);
bytes_memory_in(11) <= data_in(BYTE_LENGTH*12-1 downto BYTE_LENGTH*12-8) when rising_edge(start);
bytes_memory_in(12) <= data_in(BYTE_LENGTH*13-1 downto BYTE_LENGTH*13-8) when rising_edge(start);
bytes_memory_in(13) <= data_in(BYTE_LENGTH*14-1 downto BYTE_LENGTH*14-8) when rising_edge(start);
bytes_memory_in(14) <= data_in(BYTE_LENGTH*15-1 downto BYTE_LENGTH*15-8) when rising_edge(start);
bytes_memory_in(15) <= data_in(BYTE_LENGTH*16-1 downto BYTE_LENGTH*16-8) when rising_edge(start);
start_sbox_module <= '1' when rising_edge(start);
data_out(BYTE_LENGTH-1 downto BYTE_LENGTH-8) <= bytes_memory_out(0) when clock = '1' and finish_sbox_module_0 = '1';
data_out(BYTE_LENGTH*2-1 downto BYTE_LENGTH*2-8) <= bytes_memory_out(1) when clock = '1' and finish_sbox_module_1 = '1';
data_out(BYTE_LENGTH*3-1 downto BYTE_LENGTH*3-8) <= bytes_memory_out(2) when clock = '1' and finish_sbox_module_2 = '1';
data_out(BYTE_LENGTH*4-1 downto BYTE_LENGTH*4-8) <= bytes_memory_out(3) when clock = '1' and finish_sbox_module_3 = '1';
data_out(BYTE_LENGTH*5-1 downto BYTE_LENGTH*5-8) <= bytes_memory_out(4) when clock = '1' and finish_sbox_module_4 = '1';
data_out(BYTE_LENGTH*6-1 downto BYTE_LENGTH*6-8) <= bytes_memory_out(5) when clock = '1' and finish_sbox_module_5 = '1';
data_out(BYTE_LENGTH*7-1 downto BYTE_LENGTH*7-8) <= bytes_memory_out(6) when clock = '1' and finish_sbox_module_6 = '1';
data_out(BYTE_LENGTH*8-1 downto BYTE_LENGTH*8-8) <= bytes_memory_out(7) when clock = '1' and finish_sbox_module_7 = '1';
data_out(BYTE_LENGTH*9-1 downto BYTE_LENGTH*9-8) <= bytes_memory_out(8) when clock = '1' and finish_sbox_module_8 = '1';
data_out(BYTE_LENGTH*10-1 downto BYTE_LENGTH*10-8) <= bytes_memory_out(9) when clock = '1' and finish_sbox_module_9 = '1';
data_out(BYTE_LENGTH*11-1 downto BYTE_LENGTH*11-8) <= bytes_memory_out(10) when clock = '1' and finish_sbox_module_10 = '1';
data_out(BYTE_LENGTH*12-1 downto BYTE_LENGTH*12-8) <= bytes_memory_out(11) when clock = '1' and finish_sbox_module_11 = '1';
data_out(BYTE_LENGTH*13-1 downto BYTE_LENGTH*13-8) <= bytes_memory_out(12) when clock = '1' and finish_sbox_module_12 = '1';
data_out(BYTE_LENGTH*14-1 downto BYTE_LENGTH*14-8) <= bytes_memory_out(13) when clock = '1' and finish_sbox_module_13 = '1';
data_out(BYTE_LENGTH*15-1 downto BYTE_LENGTH*15-8) <= bytes_memory_out(14) when clock = '1' and finish_sbox_module_14 = '1';
data_out(BYTE_LENGTH*16-1 downto BYTE_LENGTH*16-8) <= bytes_memory_out(15) when clock = '1' and finish_sbox_module_15 = '1';
SBox_module_0 : SBox_module
port map (bytes_memory_out(0), finish_sbox_module_0, bytes_memory_in(0), start_sbox_module);
SBox_module_1 : SBox_module
port map (bytes_memory_out(1), finish_sbox_module_1, bytes_memory_in(1), start_sbox_module);
SBox_module_2 : SBox_module
port map (bytes_memory_out(2), finish_sbox_module_2, bytes_memory_in(2), start_sbox_module);
SBox_module_3 : SBox_module
port map (bytes_memory_out(3), finish_sbox_module_3, bytes_memory_in(3), start_sbox_module);
SBox_module_4 : SBox_module
port map (bytes_memory_out(4), finish_sbox_module_4, bytes_memory_in(4), start_sbox_module);
SBox_module_5 : SBox_module
port map (bytes_memory_out(5), finish_sbox_module_5, bytes_memory_in(5), start_sbox_module);
SBox_module_6 : SBox_module
port map (bytes_memory_out(6), finish_sbox_module_6, bytes_memory_in(6), start_sbox_module);
SBox_module_7 : SBox_module
port map (bytes_memory_out(7), finish_sbox_module_7, bytes_memory_in(7), start_sbox_module);
SBox_module_8 : SBox_module
port map (bytes_memory_out(8), finish_sbox_module_8, bytes_memory_in(8), start_sbox_module);
SBox_module_9 : SBox_module
port map (bytes_memory_out(9), finish_sbox_module_9, bytes_memory_in(9), start_sbox_module);
SBox_module_10 : SBox_module
port map (bytes_memory_out(10), finish_sbox_module_10, bytes_memory_in(10), start_sbox_module);
SBox_module_11 : SBox_module
port map (bytes_memory_out(11), finish_sbox_module_11, bytes_memory_in(11), start_sbox_module);
SBox_module_12 : SBox_module
port map (bytes_memory_out(12), finish_sbox_module_12, bytes_memory_in(12), start_sbox_module);
SBox_module_13 : SBox_module
port map (bytes_memory_out(13), finish_sbox_module_13, bytes_memory_in(13), start_sbox_module);
SBox_module_14 : SBox_module
port map (bytes_memory_out(14), finish_sbox_module_14, bytes_memory_in(14), start_sbox_module);
SBox_module_15 : SBox_module
port map (bytes_memory_out(15), finish_sbox_module_15, bytes_memory_in(15), start_sbox_module);
finish_all_sbox <= finish_sbox_module_0 and finish_sbox_module_1 and finish_sbox_module_2 and
finish_sbox_module_3 and finish_sbox_module_4 and finish_sbox_module_5 and
finish_sbox_module_6 and finish_sbox_module_7 and finish_sbox_module_8 and
finish_sbox_module_9 and finish_sbox_module_10 and finish_sbox_module_11 and
finish_sbox_module_12 and finish_sbox_module_13 and finish_sbox_module_14 and
finish_sbox_module_15;
finish <= finish_all_sbox;
end RTL;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cmpy_v5_0_fc1d91881e8e8ae6.vhd when simulating
-- the core, cmpy_v5_0_fc1d91881e8e8ae6. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cmpy_v5_0_fc1d91881e8e8ae6 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
);
END cmpy_v5_0_fc1d91881e8e8ae6;
ARCHITECTURE cmpy_v5_0_fc1d91881e8e8ae6_a OF cmpy_v5_0_fc1d91881e8e8ae6 IS
-- synthesis translate_off
COMPONENT wrapped_cmpy_v5_0_fc1d91881e8e8ae6
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cmpy_v5_0_fc1d91881e8e8ae6 USE ENTITY XilinxCoreLib.cmpy_v5_0(behavioral)
GENERIC MAP (
c_a_width => 24,
c_b_width => 24,
c_has_aclken => 1,
c_has_aresetn => 0,
c_has_s_axis_a_tlast => 0,
c_has_s_axis_a_tuser => 0,
c_has_s_axis_b_tlast => 0,
c_has_s_axis_b_tuser => 1,
c_has_s_axis_ctrl_tlast => 0,
c_has_s_axis_ctrl_tuser => 0,
c_latency => 6,
c_m_axis_dout_tdata_width => 48,
c_m_axis_dout_tuser_width => 1,
c_mult_type => 1,
c_optimize_goal => 1,
c_out_width => 24,
c_s_axis_a_tdata_width => 48,
c_s_axis_a_tuser_width => 1,
c_s_axis_b_tdata_width => 48,
c_s_axis_b_tuser_width => 1,
c_s_axis_ctrl_tdata_width => 8,
c_s_axis_ctrl_tuser_width => 1,
c_throttle_scheme => 3,
c_tlast_resolution => 0,
c_verbosity => 0,
c_xdevice => "xc6vlx240t",
c_xdevicefamily => "virtex6",
has_negate => 0,
round => 0,
single_output => 0,
use_dsp_cascades => 1
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cmpy_v5_0_fc1d91881e8e8ae6
PORT MAP (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tuser => s_axis_b_tuser,
s_axis_b_tdata => s_axis_b_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tuser => m_axis_dout_tuser,
m_axis_dout_tdata => m_axis_dout_tdata
);
-- synthesis translate_on
END cmpy_v5_0_fc1d91881e8e8ae6_a;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity single_crl is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
player : in std_logic; -- '0' player 1 ;
-- '1' palyer 2
saida : out std_logic_vector(1 downto 0); -- '00' vazio;
-- '01' player 1;
-- '10' player 2;
-- '11' erro
handler : out std_logic_vector(1 downto 0)
);
end single_crl;
architecture estados of single_crl is
type tipo_estado is (INICIAL, PLAYER_ONE, PLAYER_TWO, ERRO_ONE, ERRO_TWO);
signal estado : tipo_estado;
begin
process (clock, reset, enable, player)
begin
if reset = '1' then
estado <= INICIAL;
elsif clock'event and clock = '1' then
case estado is
when INICIAL =>
if enable = '1' then
if player = '1' then
estado <= PLAYER_ONE;
else
estado <= PLAYER_TWO;
end if;
end if;
when PLAYER_ONE =>
if enable = '1' then
estado <= ERRO_ONE;
end if;
when PLAYER_TWO =>
if enable = '1' then
estado <= ERRO_TWO;
end if;
when ERRO_ONE =>
estado <= PLAYER_ONE;
when ERRO_TWO =>
estado <= PLAYER_TWO;
end case;
end if;
end process;
process (estado)
begin
case estado is
when INICIAL =>
saida <= "00";
handler <= "00";
when PLAYER_ONE =>
saida <= "01";
handler <= "01";
when PLAYER_TWO =>
saida <= "10";
handler <= "10";
when ERRO_ONE =>
saida <= "01";
handler <= "11";
when ERRO_TWO =>
saida <= "10";
handler <= "11";
end case;
end process;
end estados;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1268.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p07n01i01268ent IS
END c08s02b00x00p07n01i01268ent;
ARCHITECTURE c08s02b00x00p07n01i01268arch OF c08s02b00x00p07n01i01268ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c08s02b00x00p07n01i01268 - This test needs manual check."
severity NOTE;
wait;
END PROCESS TESTING;
END c08s02b00x00p07n01i01268arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1268.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p07n01i01268ent IS
END c08s02b00x00p07n01i01268ent;
ARCHITECTURE c08s02b00x00p07n01i01268arch OF c08s02b00x00p07n01i01268ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c08s02b00x00p07n01i01268 - This test needs manual check."
severity NOTE;
wait;
END PROCESS TESTING;
END c08s02b00x00p07n01i01268arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1268.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p07n01i01268ent IS
END c08s02b00x00p07n01i01268ent;
ARCHITECTURE c08s02b00x00p07n01i01268arch OF c08s02b00x00p07n01i01268ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c08s02b00x00p07n01i01268 - This test needs manual check."
severity NOTE;
wait;
END PROCESS TESTING;
END c08s02b00x00p07n01i01268arch;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 18:34:35 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_vga_sync_reset_0_0 -prefix
-- system_vga_sync_reset_0_0_ system_vga_sync_reset_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_reset_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_reset_0_0_vga_sync_reset is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
end system_vga_sync_reset_0_0_vga_sync_reset;
architecture STRUCTURE of system_vga_sync_reset_0_0_vga_sync_reset is
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal \h_count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal hsync_i_1_n_0 : STD_LOGIC;
signal hsync_i_2_n_0 : STD_LOGIC;
signal hsync_i_3_n_0 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \v_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal vsync_i_1_n_0 : STD_LOGIC;
signal vsync_i_2_n_0 : STD_LOGIC;
signal \^xaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^yaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of active_i_2 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[8]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of hsync_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of hsync_i_3 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \v_count_reg[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of vsync_i_2 : label is "soft_lutpair3";
begin
xaddr(9 downto 0) <= \^xaddr\(9 downto 0);
yaddr(9 downto 0) <= \^yaddr\(9 downto 0);
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000222A00000000"
)
port map (
I0 => active_i_2_n_0,
I1 => \^xaddr\(9),
I2 => \^xaddr\(7),
I3 => \^xaddr\(8),
I4 => \^yaddr\(9),
I5 => rst,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(5),
I2 => \^yaddr\(6),
I3 => \^yaddr\(8),
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => active_i_1_n_0,
Q => active,
R => '0'
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(0),
O => \h_count_reg[0]_i_1_n_0\
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^xaddr\(0),
I1 => \^xaddr\(1),
O => plusOp(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
I2 => \^xaddr\(2),
O => plusOp(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(0),
I2 => \^xaddr\(1),
I3 => \^xaddr\(3),
O => plusOp(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
I4 => \^xaddr\(4),
O => plusOp(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(3),
I5 => \^xaddr\(5),
O => plusOp(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^xaddr\(5),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(6),
O => plusOp(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF40"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \^xaddr\(5),
I2 => \^xaddr\(6),
I3 => \^xaddr\(7),
O => plusOp(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF7F0080"
)
port map (
I0 => \^xaddr\(7),
I1 => \^xaddr\(6),
I2 => \^xaddr\(5),
I3 => \h_count_reg[9]_i_3_n_0\,
I4 => \^xaddr\(8),
O => plusOp(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10000000FFFFFFFF"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \^xaddr\(7),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \h_count_reg[9]_i_4_n_0\,
I5 => rst,
O => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFFFFFFF20000000"
)
port map (
I0 => \^xaddr\(8),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(6),
I4 => \^xaddr\(7),
I5 => \^xaddr\(9),
O => plusOp(9)
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
I4 => \^xaddr\(4),
O => \h_count_reg[9]_i_3_n_0\
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(5),
I1 => \^xaddr\(6),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg[0]_i_1_n_0\,
Q => \^xaddr\(0),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(1),
Q => \^xaddr\(1),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(2),
Q => \^xaddr\(2),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(3),
Q => \^xaddr\(3),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(4),
Q => \^xaddr\(4),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(5),
Q => \^xaddr\(5),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(6),
Q => \^xaddr\(6),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(7),
Q => \^xaddr\(7),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(8),
Q => \^xaddr\(8),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(9),
Q => \^xaddr\(9),
R => \h_count_reg[9]_i_1_n_0\
);
hsync_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"ABEAFFFF"
)
port map (
I0 => hsync_i_2_n_0,
I1 => \^xaddr\(5),
I2 => \^xaddr\(6),
I3 => hsync_i_3_n_0,
I4 => rst,
O => hsync_i_1_n_0
);
hsync_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \^xaddr\(9),
I1 => \^xaddr\(8),
I2 => \^xaddr\(7),
O => hsync_i_2_n_0
);
hsync_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(3),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(4),
O => hsync_i_3_n_0
);
hsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => hsync_i_1_n_0,
Q => hsync,
R => '0'
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^yaddr\(0),
O => \plusOp__0\(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => \plusOp__0\(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(0),
I2 => \^yaddr\(2),
O => \plusOp__0\(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^yaddr\(2),
I1 => \^yaddr\(0),
I2 => \^yaddr\(1),
I3 => \^yaddr\(3),
O => \plusOp__0\(3)
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(2),
I4 => \^yaddr\(4),
O => \plusOp__0\(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(0),
I3 => \^yaddr\(1),
I4 => \^yaddr\(3),
I5 => \^yaddr\(5),
O => \plusOp__0\(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^yaddr\(5),
I1 => \v_count_reg[9]_i_6_n_0\,
I2 => \^yaddr\(6),
O => \plusOp__0\(6)
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F708"
)
port map (
I0 => \^yaddr\(5),
I1 => \^yaddr\(6),
I2 => \v_count_reg[9]_i_6_n_0\,
I3 => \^yaddr\(7),
O => \plusOp__0\(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFF4000"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \^yaddr\(8),
O => \plusOp__0\(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00400000FFFFFFFF"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \h_count_reg[9]_i_4_n_0\,
I3 => \^yaddr\(0),
I4 => \v_count_reg[9]_i_5_n_0\,
I5 => rst,
O => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => \^xaddr\(5),
I1 => \^xaddr\(6),
I2 => \^xaddr\(9),
I3 => \^xaddr\(8),
I4 => \^xaddr\(7),
I5 => \h_count_reg[9]_i_3_n_0\,
O => \v_count_reg[9]_i_2_n_0\
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFFFFF40000000"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => \^yaddr\(7),
I2 => \^yaddr\(5),
I3 => \^yaddr\(6),
I4 => \^yaddr\(8),
I5 => \^yaddr\(9),
O => \plusOp__0\(9)
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \^yaddr\(9),
I1 => \^xaddr\(7),
I2 => \^yaddr\(7),
I3 => \^yaddr\(8),
I4 => \^xaddr\(9),
I5 => \^xaddr\(8),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(4),
I2 => \^yaddr\(2),
I3 => \^yaddr\(1),
I4 => \^yaddr\(6),
I5 => \^yaddr\(5),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(2),
I4 => \^yaddr\(4),
O => \v_count_reg[9]_i_6_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(0),
Q => \^yaddr\(0),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(1),
Q => \^yaddr\(1),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(2),
Q => \^yaddr\(2),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(3),
Q => \^yaddr\(3),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(4),
Q => \^yaddr\(4),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(5),
Q => \^yaddr\(5),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(6),
Q => \^yaddr\(6),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(7),
Q => \^yaddr\(7),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(8),
Q => \^yaddr\(8),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(9),
Q => \^yaddr\(9),
R => \v_count_reg[9]_i_1_n_0\
);
vsync_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFBFFFFFFFF"
)
port map (
I0 => vsync_i_2_n_0,
I1 => \^yaddr\(1),
I2 => \^yaddr\(2),
I3 => \^yaddr\(9),
I4 => \^yaddr\(4),
I5 => rst,
O => vsync_i_1_n_0
);
vsync_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^yaddr\(8),
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \^yaddr\(3),
O => vsync_i_2_n_0
);
vsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => vsync_i_1_n_0,
Q => vsync,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_reset_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_reset_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_reset_0_0 : entity is "system_vga_sync_reset_0_0,vga_sync_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_reset_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_reset_0_0 : entity is "vga_sync_reset,Vivado 2016.4";
end system_vga_sync_reset_0_0;
architecture STRUCTURE of system_vga_sync_reset_0_0 is
begin
U0: entity work.system_vga_sync_reset_0_0_vga_sync_reset
port map (
active => active,
clk => clk,
hsync => hsync,
rst => rst,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.math_real.all;
use work.globals.all;
-- register on a register bus
entity reg is
generic (REG_BYTES : integer;
DEFAULT_VALUE : integer := 0;
REG_ADDR_BASE : reg_addr_t);
port (Clk : in std_logic;
Rst : in std_logic;
RegBusI : in reg_bus_t;
RegBusO : out reg_bus_t;
Value : out std_logic_vector(REG_BYTES*8 - 1 downto 0));
end reg;
-- Operation:
-- Hold the @Value. Access it when address on the bus matches @REG_ADDR_BASE.
-- Writes are atomic - @Value is changed only when address on the bus is out of
-- the range of addresses of this register.
-- Writes to register must be 'clock-in-clock' to ensure atomicity of the value.
architecture Behavioral of reg is
constant OFFSET_LEN : integer := integer(ceil(log2(real(REG_BYTES))));
constant REG_BITS : integer := REG_BYTES*8;
subtype OffsetRange is natural range OFFSET_LEN - 1 downto 0;
subtype AddrRange is natural range REG_ADDR_W - 1 downto OFFSET_LEN;
signal offset : integer;
signal bus_addr, reg_addr : std_logic_vector(AddrRange);
signal v_atomic, v_new : std_logic_vector(REG_BITS - 1 downto 0) := CONV_std_logic_vector(DEFAULT_VALUE, REG_BITS);
begin
offset <= CONV_integer(RegBusI.addr(OffsetRange));
bus_addr <= RegBusI.addr(AddrRange);
reg_addr <= REG_ADDR_BASE(AddrRange);
Value <= v_atomic;
update : process (Clk)
begin
if rising_edge(Clk) then
RegBusO <= RegBusI;
if bus_addr = reg_addr then
if RegBusI.wr = '1' then
v_new(7 + offset*8 downto offset*8) <= RegBusI.data;
else
RegBusO.data <= v_atomic(7 + offset*8 downto offset*8);
end if;
else
v_atomic <= v_new;
end if;
if Rst = '1' then
v_new <= CONV_std_logic_vector(DEFAULT_VALUE, REG_BITS);
RegBusO.addr <= reg_addr_invl;
end if;
end if;
end process;
end Behavioral;
|
---- UART code taken from http://www.bealto.com/fpga-uart.html
-- -- Eric Bainville
-- -- Mar 2013
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library work;
--use work.math_real.all;
--entity basic_uart is
-- generic (
-- DIVISOR: natural := 54 -- DIVISOR = 100,000,000 / (16 x BAUD_RATE)
-- -- 2400 -> 2604
-- -- 9600 -> 651
-- -- 115200 -> 54
-- -- 1562500 -> 4
-- -- 2083333 -> 3
-- );
-- port (
-- clk: in std_logic; -- clock
-- reset: in std_logic; -- reset
-- -- Client interface
-- rx_data: out std_logic_vector(7 downto 0); -- received byte
-- rx_enable: out std_logic; -- validates received byte (1 system clock spike)
-- tx_data: in std_logic_vector(7 downto 0); -- byte to send
-- tx_enable: in std_logic; -- validates byte to send if tx_ready is '1'
-- tx_ready: out std_logic; -- if '1', we can send a new byte, otherwise we won't take it
-- -- Physical interface
-- rx: in std_logic;
-- tx: out std_logic
-- );
--end basic_uart;
--architecture Behavioral of basic_uart is
-- constant COUNTER_BITS : natural := integer(ceil(log(2,real(DIVISOR))));
-- type fsm_state_t is (idle, active); -- common to both RX and TX FSM
-- type rx_state_t is
-- record
-- fsm_state: fsm_state_t; -- FSM state
-- counter: std_logic_vector(3 downto 0); -- tick count
-- bits: std_logic_vector(7 downto 0); -- received bits
-- nbits: std_logic_vector(3 downto 0); -- number of received bits (includes start bit)
-- enable: std_logic; -- signal we received a new byte
-- end record;
-- type tx_state_t is
-- record
-- fsm_state: fsm_state_t; -- FSM state
-- counter: std_logic_vector(3 downto 0); -- tick count
-- bits: std_logic_vector(8 downto 0); -- bits to emit, includes start bit
-- nbits: std_logic_vector(3 downto 0); -- number of bits left to send
-- ready: std_logic; -- signal we are accepting a new byte
-- end record;
-- signal rx_state,rx_state_next: rx_state_t;
-- signal tx_state,tx_state_next: tx_state_t;
-- signal sample: std_logic; -- 1 clk spike at 16x baud rate
-- signal sample_counter: std_logic_vector(COUNTER_BITS-1 downto 0); -- should fit values in 0..DIVISOR-1
--begin
-- -- sample signal at 16x baud rate, 1 CLK spikes
-- sample_process: process (clk,reset) is
-- begin
-- if reset = '1' then
-- sample_counter <= (others => '0');
-- sample <= '0';
-- elsif rising_edge(clk) then
-- if sample_counter = DIVISOR-1 then
-- sample <= '1';
-- sample_counter <= (others => '0');
-- else
-- sample <= '0';
-- sample_counter <= sample_counter + 1;
-- end if;
-- end if;
-- end process;
-- -- RX, TX state registers update at each CLK, and RESET
-- reg_process: process (clk,reset) is
-- begin
-- if reset = '1' then
-- rx_state.fsm_state <= idle;
-- rx_state.bits <= (others => '0');
-- rx_state.nbits <= (others => '0');
-- rx_state.enable <= '0';
-- tx_state.fsm_state <= idle;
-- tx_state.bits <= (others => '1');
-- tx_state.nbits <= (others => '0');
-- tx_state.ready <= '1';
-- elsif rising_edge(clk) then
-- rx_state <= rx_state_next;
-- tx_state <= tx_state_next;
-- end if;
-- end process;
-- -- RX FSM
-- rx_process: process (rx_state,sample,rx) is
-- begin
-- case rx_state.fsm_state is
-- when idle =>
-- rx_state_next.counter <= (others => '0');
-- rx_state_next.bits <= (others => '0');
-- rx_state_next.nbits <= (others => '0');
-- rx_state_next.enable <= '0';
-- if rx = '0' then
-- -- start a new byte
-- rx_state_next.fsm_state <= active;
-- else
-- -- keep idle
-- rx_state_next.fsm_state <= idle;
-- end if;
-- when active =>
-- rx_state_next <= rx_state;
-- if sample = '1' then
-- if rx_state.counter = 8 then
-- -- sample next RX bit (at the middle of the counter cycle)
-- if rx_state.nbits = 9 then
-- rx_state_next.fsm_state <= idle; -- back to idle state to wait for next start bit
-- rx_state_next.enable <= rx; -- OK if stop bit is '1'
-- else
-- rx_state_next.bits <= rx & rx_state.bits(7 downto 1);
-- rx_state_next.nbits <= rx_state.nbits + 1;
-- end if;
-- end if;
-- rx_state_next.counter <= rx_state.counter + 1;
-- end if;
-- end case;
-- end process;
-- -- RX output
-- rx_output: process (rx_state) is
-- begin
-- rx_enable <= rx_state.enable;
-- rx_data <= rx_state.bits;
-- end process;
-- -- TX FSM
-- tx_process: process (tx_state,sample,tx_enable,tx_data) is
-- begin
-- case tx_state.fsm_state is
-- when idle =>
-- if tx_enable = '1' then
-- -- start a new bit
-- tx_state_next.bits <= tx_data & '0'; -- data & start
-- tx_state_next.nbits <= "0000" + 10; -- send 10 bits (includes '1' stop bit)
-- tx_state_next.counter <= (others => '0');
-- tx_state_next.fsm_state <= active;
-- tx_state_next.ready <= '0';
-- else
-- -- keep idle
-- tx_state_next.bits <= (others => '1');
-- tx_state_next.nbits <= (others => '0');
-- tx_state_next.counter <= (others => '0');
-- tx_state_next.fsm_state <= idle;
-- tx_state_next.ready <= '1';
-- end if;
-- when active =>
-- tx_state_next <= tx_state;
-- if sample = '1' then
-- if tx_state.counter = 15 then
-- -- send next bit
-- if tx_state.nbits = 0 then
-- -- turn idle
-- tx_state_next.bits <= (others => '1');
-- tx_state_next.nbits <= (others => '0');
-- tx_state_next.counter <= (others => '0');
-- tx_state_next.fsm_state <= idle;
-- tx_state_next.ready <= '1';
-- else
-- tx_state_next.bits <= '1' & tx_state.bits(8 downto 1);
-- tx_state_next.nbits <= tx_state.nbits - 1;
-- end if;
-- end if;
-- tx_state_next.counter <= tx_state.counter + 1;
-- end if;
-- end case;
-- end process;
-- -- TX output
-- tx_output: process (tx_state) is
-- begin
-- tx_ready <= tx_state.ready;
-- tx <= tx_state.bits(0);
-- end process;
--end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity uart is
port (
reset :in std_logic;
txclk :in std_logic;
ld_tx_data :in std_logic;
tx_data :in std_logic_vector (7 downto 0);
tx_enable :in std_logic;
selCheck :in std_logic_vector(1 downto 0);
tx_out :out std_logic;
tx_empty :out std_logic;
rxclk :in std_logic;
uld_rx_data :in std_logic;
rx_data :out std_logic_vector (7 downto 0);
rx_enable :in std_logic;
rx_in :in std_logic;
rx_empty :out std_logic
);
end entity;
architecture rtl of uart is
-- Internal Variables
signal tx_reg :std_logic_vector (7 downto 0);
signal tx_over_run :std_logic;
signal tx_cnt :std_logic_vector (3 downto 0);
signal rx_reg :std_logic_vector (7 downto 0);
signal rx_sample_cnt :std_logic_vector (3 downto 0);
signal rx_cnt :std_logic_vector (3 downto 0);
signal rx_frame_err :std_logic;
signal rx_over_run :std_logic;
signal rx_d1 :std_logic;
signal rx_d2 :std_logic;
signal rx_busy :std_logic;
signal rx_is_empty :std_logic;
signal tx_is_empty :std_logic;
begin
-- UART RX Logic
process (rxclk, reset,selCheck) begin
if (reset = '1') then
rx_reg <= (others=>'0');
rx_data <= (others=>'0');
rx_sample_cnt <= (others=>'0');
rx_cnt <= (others=>'0');
rx_frame_err <= '0';
rx_over_run <= '0';
rx_is_empty <= '1';
rx_d1 <= '1';
rx_d2 <= '1';
rx_busy <= '0';
elsif (rising_edge(rxclk)) then
-- Synchronize the asynch signal
rx_d1 <= rx_in;
rx_d2 <= rx_d1;
-- Uload the rx data
if (uld_rx_data = '1') then
rx_data <= rx_reg;
rx_is_empty <= '1';
end if;
if uld_rx_data = '1' and selCheck /= "00" and rx_is_empty = '1' then
rx_data <= "00000000";
end if;
-- Receive data only when rx is enabled
if (rx_enable = '1') then
-- Check if just received start of frame
if (rx_busy = '0' and rx_d2 = '0') then
rx_busy <= '1';
rx_sample_cnt <= X"1";
rx_cnt <= X"0";
end if;
-- Start of frame detected, Proceed with rest of data
if (rx_busy = '1') then
rx_sample_cnt <= rx_sample_cnt + 1;
-- Logic to sample at middle of data
if (rx_sample_cnt = 7) then
if ((rx_d2 = '1') and (rx_cnt = 0)) then
rx_busy <= '0';
else
rx_cnt <= rx_cnt + 1;
-- Start storing the rx data
if (rx_cnt > 0 and rx_cnt < 9) then
rx_reg(conv_integer(rx_cnt) - 1) <= rx_d2;
end if;
if (rx_cnt = 9) then
rx_busy <= '0';
-- Check if End of frame received correctly
if (rx_d2 = '0') then
rx_frame_err <= '1';
else
rx_is_empty <= '0';
rx_frame_err <= '0';
-- Check if last rx data was not unloaded,
if (rx_is_empty = '1') then
rx_over_run <= '0';
else
rx_over_run <= '1';
end if;
end if;
end if;
end if;
end if;
end if;
end if;
if (rx_enable = '0') then
rx_busy <= '0';
end if;
end if;
end process;
rx_empty <= rx_is_empty;
-- UART TX Logic
process (txclk, reset) begin
if (reset = '1') then
tx_reg <= (others=>'0');
tx_is_empty <= '1';
tx_over_run <= '0';
tx_out <= '0';
tx_cnt <= (others=>'0');
elsif (rising_edge(txclk)) then
if (ld_tx_data = '1') then
if (tx_is_empty = '0') then
tx_over_run <= '0';
else
tx_reg <= tx_data;
tx_is_empty <= '0';
end if;
end if;
if (tx_enable = '1' and tx_is_empty = '0') then
tx_cnt <= tx_cnt + 1;
if (tx_cnt = 0) then
tx_out <= '0';
end if;
if (tx_cnt > 0 and tx_cnt < 9) then
tx_out <= tx_reg(conv_integer(tx_cnt) -1);
end if;
if (tx_cnt = 9) then
tx_out <= '1';
tx_cnt <= X"0";
tx_is_empty <= '1';
end if;
end if;
if (tx_enable = '0') then
tx_cnt <= X"0";
end if;
end if;
end process;
-- process(uld_rx_data)
-- begin
-- if uld_rx_data = '1' and selCheck /= "00" and rx_is_empty = '1' then
-- rx_data <= "00000000";
-- end if;
-- end process;
-- tx_empty <= tx_is_empty;
end architecture; |
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: dlx-rtl.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 19:54:44 $
--
--------------------------------------------------------------------------
--
-- Register transfer level architecture of DLX processor.
--
use std.textio.all,
work.images.image_hex,
work.bv_arithmetic.all,
work.dlx_instr.all,
work.alu_types.all;
architecture rtl of dlx is
component alu
port (s1 : in dlx_word;
s2 : in dlx_word;
result : out dlx_word;
latch_en : in bit;
func : in alu_func;
zero, negative, overflow : out bit);
end component;
component reg_file
port (a1 : in dlx_reg_addr; -- port1 address
q1 : out dlx_word; -- port1 read data
a2 : in dlx_reg_addr; -- port2 address
q2 : out dlx_word; -- port2 read data
a3 : in dlx_reg_addr; -- port3 address
d3 : in dlx_word; -- port3 write data
write_en : in bit); -- port3 write enable
end component;
component latch
port (d : in dlx_word;
q : out dlx_word;
latch_en : in bit);
end component;
component reg_1_out
port (d : in dlx_word;
q : out dlx_word_bus bus;
latch_en : in bit;
out_en : in bit);
end component;
component reg_2_out
port (d : in dlx_word;
q1, q2 : out dlx_word_bus bus;
latch_en : in bit;
out_en1, out_en2 : in bit);
end component;
component reg_3_out
port (d : in dlx_word;
q1, q2, q3 : out dlx_word_bus bus;
latch_en : in bit;
out_en1, out_en2, out_en3 : in bit);
end component;
component reg_2_1_out
port (d : in dlx_word;
q1, q2 : out dlx_word_bus bus;
q3 : out dlx_word;
latch_en : in bit;
out_en1, out_en2 : in bit);
end component;
component mux2
port (i0, i1 : in dlx_word;
y : out dlx_word;
sel : in bit);
end component;
component ir
port (d : in dlx_word; -- instruction input from memory
immed_q1, immed_q2 : out dlx_word_bus bus;
ir_out : out dlx_word; -- instruction output to control
latch_en : in bit;
immed_sel1, immed_sel2 : in immed_size; -- select 16-bit or 26-bit immed
immed_unsigned1, immed_unsigned2 : in bit; -- extend immed unsigned/signed
immed_en1, immed_en2 : in bit); -- enable immed const outputs
end component;
component controller
port (phi1, phi2 : in bit;
reset : in bit;
halt : out bit;
width : out mem_width;
write_enable : out bit;
mem_enable : out bit;
ifetch : out bit;
ready : in bit;
alu_latch_en : out bit;
alu_function : out alu_func;
alu_zero, alu_negative, alu_overflow : in bit;
reg_s1_addr, reg_s2_addr, reg_dest_addr : out dlx_reg_addr;
reg_write : out bit;
c_latch_en : out bit;
a_latch_en, a_out_en : out bit;
b_latch_en, b_out_en : out bit;
temp_latch_en, temp_out_en1, temp_out_en2 : out bit;
iar_latch_en, iar_out_en1, iar_out_en2 : out bit;
pc_latch_en, pc_out_en1, pc_out_en2 : out bit;
mar_latch_en, mar_out_en1, mar_out_en2 : out bit;
mem_addr_mux_sel : out bit;
mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out bit;
mdr_mux_sel : out bit;
ir_latch_en : out bit;
ir_immed_sel1, ir_immed_sel2 : out immed_size;
ir_immed_unsigned1, ir_immed_unsigned2 : out bit;
ir_immed_en1, ir_immed_en2 : out bit;
current_instruction : in dlx_word;
const1, const2 : out dlx_word_bus bus);
end component;
signal s1_bus, s2_bus : dlx_word_bus;
signal dest_bus : dlx_word;
signal alu_latch_en : bit;
signal alu_function : alu_func;
signal alu_zero, alu_negative, alu_overflow : bit;
signal reg_s1_addr, reg_s2_addr, reg_dest_addr : dlx_reg_addr;
signal reg_file_out1, reg_file_out2, reg_file_in : dlx_word;
signal reg_write : bit;
signal a_out_en, a_latch_en : bit;
signal b_out_en, b_latch_en : bit;
signal c_latch_en : bit;
signal temp_out_en1, temp_out_en2, temp_latch_en : bit;
signal iar_out_en1, iar_out_en2, iar_latch_en : bit;
signal pc_out_en1, pc_out_en2, pc_latch_en : bit;
signal pc_to_mem : dlx_word;
signal mar_out_en1, mar_out_en2, mar_latch_en : bit;
signal mar_to_mem : dlx_word;
signal mem_addr_mux_sel : bit;
signal mdr_out_en1, mdr_out_en2, mdr_out_en3, mdr_latch_en : bit;
signal mdr_in : dlx_word;
signal mdr_mux_sel : bit;
signal current_instruction : dlx_word;
signal ir_latch_en : bit;
signal ir_immed_sel1, ir_immed_sel2 : immed_size;
signal ir_immed_unsigned1, ir_immed_unsigned2 : bit;
signal ir_immed_en1, ir_immed_en2 : bit;
begin
the_alu : alu
port map (s1 => s1_bus, s2 => s2_bus, result => dest_bus,
latch_en => alu_latch_en, func => alu_function,
zero => alu_zero, negative => alu_negative, overflow => alu_overflow);
the_reg_file : reg_file
port map (a1 => reg_s1_addr, q1 => reg_file_out1,
a2 => reg_s2_addr, q2 => reg_file_out2,
a3 => reg_dest_addr, d3 => reg_file_in,
write_en => reg_write);
c_reg : latch
port map (d => dest_bus, q => reg_file_in, latch_en => c_latch_en);
a_reg : reg_1_out
port map (d => reg_file_out1, q => s1_bus,
latch_en => a_latch_en, out_en => a_out_en);
b_reg : reg_1_out
port map (d => reg_file_out2, q => s2_bus,
latch_en => b_latch_en, out_en => b_out_en);
temp_reg : reg_2_out
port map (d => dest_bus, q1 => s1_bus, q2 => s2_bus,
latch_en => temp_latch_en,
out_en1 => temp_out_en1, out_en2 => temp_out_en2);
iar_reg : reg_2_out
port map (d => dest_bus, q1 => s1_bus, q2 => s2_bus,
latch_en => iar_latch_en,
out_en1 => iar_out_en1, out_en2 => iar_out_en2);
pc_reg : reg_2_1_out
port map (d => dest_bus, q1 => s1_bus, q2 => s2_bus, q3 => pc_to_mem,
latch_en => pc_latch_en,
out_en1 => pc_out_en1, out_en2 => pc_out_en2);
mar_reg : reg_2_1_out
port map (d => dest_bus, q1 => s1_bus, q2 => s2_bus, q3 => mar_to_mem,
latch_en => mar_latch_en,
out_en1 => mar_out_en1, out_en2 => mar_out_en2);
mem_addr_mux : mux2
port map (i0 => pc_to_mem, i1 => mar_to_mem, y => a,
sel => mem_addr_mux_sel);
mdr_reg : reg_3_out
port map (d => mdr_in, q1 => s1_bus, q2 => s2_bus, q3 => d,
latch_en => mdr_latch_en,
out_en1 => mdr_out_en1, out_en2 => mdr_out_en2,
out_en3 => mdr_out_en3);
mdr_mux : mux2
port map (i0 => dest_bus, i1 => d, y => mdr_in,
sel => mdr_mux_sel);
instr_reg : ir
port map (d => d, immed_q1 => s1_bus, immed_q2 => s2_bus,
ir_out => current_instruction,
latch_en => ir_latch_en,
immed_sel1 => ir_immed_sel1, immed_sel2 => ir_immed_sel2,
immed_unsigned1 => ir_immed_unsigned1,
immed_unsigned2 => ir_immed_unsigned2,
immed_en1 => ir_immed_en1, immed_en2 => ir_immed_en2);
the_controller : controller
port map (phi1, phi2, reset, halt,
width, write_enable, mem_enable, ifetch, ready,
alu_latch_en, alu_function, alu_zero, alu_negative, alu_overflow,
reg_s1_addr, reg_s2_addr, reg_dest_addr, reg_write,
c_latch_en, a_latch_en, a_out_en, b_latch_en, b_out_en,
temp_latch_en, temp_out_en1, temp_out_en2,
iar_latch_en, iar_out_en1, iar_out_en2,
pc_latch_en, pc_out_en1, pc_out_en2,
mar_latch_en, mar_out_en1, mar_out_en2, mem_addr_mux_sel,
mdr_latch_en, mdr_out_en1, mdr_out_en2,
mdr_out_en3, mdr_mux_sel,
ir_latch_en, ir_immed_sel1, ir_immed_sel2,
ir_immed_unsigned1, ir_immed_unsigned2, ir_immed_en1, ir_immed_en2,
current_instruction, s1_bus, s2_bus);
debug_s1 : if debug generate
s1_monitor : process (s1_bus)
variable L : line;
begin
write(L, tag);
write(L, string'(" s1_monitor: "));
write(L, image_hex(s1_bus));
writeline(output, L);
end process s1_monitor;
end generate;
debug_s2 : if debug generate
s2_monitor : process (s2_bus)
variable L : line;
begin
write(L, tag);
write(L, string'(" s2_monitor: "));
write(L, image_hex(s2_bus));
writeline(output, L);
end process s2_monitor;
end generate;
debug_dest : if debug generate
dest_monitor : process (dest_bus)
variable L : line;
begin
write(L, tag);
write(L, string'(" dest_monitor: "));
write(L, image_hex(dest_bus));
writeline(output, L);
end process dest_monitor;
end generate;
end rtl;
|
-- $Id: fx2_2fifoctl_ic.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2012-2017 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: fx2_2fifoctl_ic - syn
-- Description: Cypress EZ-USB FX2 controller (2 fifo; int clk)
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_i_gen
-- vlib/xlib/iob_reg_o_gen
-- vlib/xlib/iob_reg_io_gen
-- memlib/fifo_2c_dram
--
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.34
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2017-04-30 888 14.7 131013 xc6slx16-2 145 147 32 75 s 5.5/5.1
-- 2013-01-04 469 13.3 O76x xc3s1200e-4 112 172 64 169 s 7.4/7.4
-- 2012-01-14 453 13.3 O76x xc3s1200e-4 101? 173 64 159 s 8.3/7.4
-- 2012-01-08 451 13.3 O76x xc3s1200e-4 110 166 64 163 s 7.5
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-04-30 888 1.3 BUGFIX: resolve rx fifo threshold deadlock
-- add fsm_* monitor lines
-- 2013-01-04 469 1.2 BUGFIX: redo rx logic, now properly pipelined
-- 2012-01-15 453 1.1 use aempty/afull logic; collapse tx and pe flows
-- 2012-01-09 451 1.0 Initial version
-- 2012-01-01 448 0.5 First draft
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.memlib.all;
use work.fx2lib.all;
entity fx2_2fifoctl_ic is -- EZ-USB FX2 controller(2 fifo; int clk)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1); -- threshold for tx afull flag
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit data busy
TXAFULL : out slbit; -- transmit almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end fx2_2fifoctl_ic;
architecture syn of fx2_2fifoctl_ic is
constant c_rxfifo : slv2 := c_fifo_ep4;
constant c_txfifo : slv2 := c_fifo_ep6;
constant c_flag_prog : integer := 0;
constant c_flag_tx_ff : integer := 1;
constant c_flag_rx_ef : integer := 2;
constant c_flag_tx2_ff : integer := 3;
type state_type is (
s_idle, -- s_idle: idle state
s_rxprep0, -- s_rxprep0: switch to rx-fifo
s_rxprep1, -- s_rxprep1: fifo addr setup
s_rxprep2, -- s_rxprep2: wait for flags
s_rxdisp, -- s_rxdisp: read, dispatch
s_rxpipe, -- s_rxpipe: read, pipe wait
s_txprep0, -- s_txprep0: switch to tx-fifo
s_txprep1, -- s_txprep1: fifo addr setup
s_txprep2, -- s_txprep2: wait for flags
s_txdisp -- s_txdisp: write, dispatch
);
type regs_type is record
state : state_type; -- state
petocnt : slv(PETOWIDTH-1 downto 0); -- pktend time out counter
pepend : slbit; -- pktend pending
rxpipe1 : slbit; -- read pipe 1: iob capture stage
rxpipe2 : slbit; -- read pipe 2: fifo write stage
ccnt : slv(CCWIDTH-1 downto 0); -- chunk counter
moni_ep4_sel : slbit; -- ep4 (rx) select
moni_ep6_sel : slbit; -- ep6 (tx) select
moni_ep4_pf : slbit; -- ep4 (rx) prog flag
moni_ep6_pf : slbit; -- ep6 (tx) prog flag
end record regs_type;
constant petocnt_init : slv(PETOWIDTH-1 downto 0) := (others=>'0');
constant ccnt_init : slv(CCWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
s_idle, -- state
petocnt_init, -- petocnt
'0', -- pepend
'0','0', -- rxpipe1, rxpipe2
ccnt_init, -- ccnt
'0','0', -- moni_ep(4|6)_sel
'0','0' -- moni_ep(4|6)_pf
);
constant rxfifo_thres : natural := 3; -- required free space in rx fifo to
-- start rx pipeline
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal FX2_FIFO : slv2 := (others=>'0');
signal FX2_FIFO_CE : slbit := '0';
signal FX2_FLAG_N : slv4 := (others=>'0');
signal FX2_SLRD_N : slbit := '1';
signal FX2_SLWR_N : slbit := '1';
signal FX2_SLOE_N : slbit := '1';
signal FX2_PKTEND_N : slbit := '1';
signal FX2_DATA_CEI : slbit := '0';
signal FX2_DATA_CEO : slbit := '0';
signal FX2_DATA_OE : slbit := '0';
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXSIZE_FX2 : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal RXSIZE_USR : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal TXSIZE_FX2 : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TXSIZE_USR : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TXBUSY_L : slbit := '0';
signal R_MONI_C : fx2ctl_moni_type := fx2ctl_moni_init;
signal R_MONI_S : fx2ctl_moni_type := fx2ctl_moni_init;
begin
assert RXAEMPTY_THRES<=2**RXFAWIDTH-1 and
TXAFULL_THRES<=2**TXFAWIDTH-1
report "assert((RXAEMPTY|TXAFULL)_THRES <= 2**(RX|TX)FAWIDTH)-1"
severity failure;
IOB_FX2_FIFO : iob_reg_o_gen
generic map (
DWIDTH => 2,
INIT => '0')
port map (
CLK => I_FX2_IFCLK,
CE => FX2_FIFO_CE,
DO => FX2_FIFO,
PAD => O_FX2_FIFO
);
IOB_FX2_FLAG : iob_reg_i_gen
generic map (
DWIDTH => 4,
INIT => '0')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DI => FX2_FLAG_N,
PAD => I_FX2_FLAG
);
IOB_FX2_SLRD : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLRD_N,
PAD => O_FX2_SLRD_N
);
IOB_FX2_SLWR : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLWR_N,
PAD => O_FX2_SLWR_N
);
IOB_FX2_SLOE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLOE_N,
PAD => O_FX2_SLOE_N
);
IOB_FX2_PKTEND : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_PKTEND_N,
PAD => O_FX2_PKTEND_N
);
IOB_FX2_DATA : iob_reg_io_gen
generic map (
DWIDTH => 8,
PULL => "KEEP")
port map (
CLK => I_FX2_IFCLK,
CEI => FX2_DATA_CEI,
CEO => FX2_DATA_CEO,
OE => FX2_DATA_OE,
DI => RXFIFO_DI, -- input data (read from pad)
DO => TXFIFO_DO, -- output data (write to pad)
PAD => IO_FX2_DATA
);
RXFIFO : fifo_2c_dram -- input fifo, 2 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => I_FX2_IFCLK,
CLKR => CLK,
RESETW => '0',
RESETR => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZEW => RXSIZE_FX2,
SIZER => RXSIZE_USR
);
TXFIFO : fifo_2c_dram -- output fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLK,
CLKR => I_FX2_IFCLK,
RESETW => RESET,
RESETR => '0',
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY_L,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZEW => TXSIZE_USR,
SIZER => TXSIZE_FX2
);
proc_regs: process (I_FX2_IFCLK)
begin
if rising_edge(I_FX2_IFCLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, FX2_FLAG_N, TXFIFO_VAL, RXSIZE_FX2, TXBUSY_L)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ififo_ce : slbit := '0';
variable ififo : slv2 := "00";
variable irxfifo_ena : slbit := '0';
variable itxfifo_hold : slbit := '0';
variable islrd : slbit := '0';
variable islwr : slbit := '0';
variable isloe : slbit := '0';
variable ipktend : slbit := '0';
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
variable idata_oe : slbit := '0';
variable slrxok : slbit := '0';
variable sltxok : slbit := '0';
variable pipeok : slbit := '0';
variable rxfifook : slbit := '0';
variable cc_clr : slbit := '0';
variable cc_cnt : slbit := '0';
variable cc_done : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ififo_ce := '0';
ififo := "00";
irxfifo_ena := '0';
itxfifo_hold := '1';
islrd := '0';
islwr := '0';
isloe := '0';
ipktend := '0';
idata_cei := '0';
idata_ceo := '0';
idata_oe := '0';
slrxok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low!
sltxok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low!
pipeok := FX2_FLAG_N(c_flag_prog); -- almost flag is act.low!
rxfifook := '0';
if unsigned(RXSIZE_FX2)>rxfifo_thres then -- enough space in rx fifo ?
rxfifook := '1';
end if;
cc_clr := '0';
cc_cnt := '0';
if unsigned(r.ccnt) = 0 then
cc_done := '1';
else
cc_done := '0';
end if;
n.rxpipe1 := '0';
case r.state is
when s_idle => -- s_idle:
if slrxok='1' and rxfifook='1' then -- rx data and space in fifo
ififo_ce := '1';
ififo := c_rxfifo;
n.state := s_rxprep1;
elsif sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1')then
ififo_ce := '1';
ififo := c_txfifo;
n.state := s_txprep1;
end if;
when s_rxprep0 => -- s_rxprep0: switch to rx-fifo
ififo_ce := '1';
ififo := c_rxfifo;
n.state := s_rxprep1;
when s_rxprep1 => -- s_rxprep1: fifo addr setup
cc_clr := '1';
n.state := s_rxprep2;
when s_rxprep2 => -- s_rxprep2: wait for flags
isloe := '1';
n.state := s_rxdisp;
when s_rxdisp => -- s_rxdisp: read, dispatch
isloe := '1';
-- if chunk done and tx or pe pending and possible
if cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1') then
if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ?
n.state := s_rxdisp; -- wait
else
n.state := s_txprep0; -- otherwise switch to tx flow
end if;
-- if more rx to do and possible
elsif slrxok='1' and rxfifook='1' then
islrd := '1';
cc_cnt := '1';
n.rxpipe1 := '1';
if pipeok='1' then
n.state := s_rxdisp; -- 1 cycle read
--n.state := s_rxprep2; -- 2 cycle read
else
n.state := s_rxpipe;
end if;
-- otherwise back to idle
else
if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ?
n.state := s_rxdisp; -- wait
else
n.state := s_idle; -- to idle
end if;
end if;
when s_rxpipe => -- s_rxpipe: read, pipe wait
isloe := '1';
n.state := s_rxprep2;
when s_txprep0 => -- s_txprep0: switch to tx-fifo
ififo_ce := '1';
ififo := c_txfifo;
n.state := s_txprep1;
when s_txprep1 => -- s_txprep1: fifo addr setup
cc_clr := '1';
n.state := s_txprep2;
when s_txprep2 => -- s_txprep2: wait for flags
n.state := s_txdisp;
when s_txdisp => -- s_txdisp: write, dispatch
-- if chunk done and rx pending and possible
if cc_done='1' and slrxok='1' and rxfifook='1' then
n.state := s_rxprep0;
-- if pktend to do and possible
elsif sltxok = '1' and r.pepend = '1' then
ipktend := '1';
n.pepend := '0';
n.state := s_idle;
-- if more tx to do and possible
elsif sltxok = '1' and TXFIFO_VAL = '1' then
cc_cnt := '1'; -- inc chunk count
n.pepend := '0'; -- cancel pe (avoid back-2-back tx+pe)
itxfifo_hold := '0';
idata_ceo := '1';
idata_oe := '1';
islwr := '1';
if pipeok = '1' then -- if not almost full
n.state := s_txdisp; -- stream
else
n.state := s_txprep1; -- wait for full flag
end if;
-- otherwise back to idle
else
n.state := s_idle;
end if;
when others => null;
end case;
-- rx pipe handling
idata_cei := r.rxpipe1;
n.rxpipe2 := r.rxpipe1;
irxfifo_ena := r.rxpipe2;
-- chunk counter handling
if cc_clr = '1' then
n.ccnt := (others=>'1');
elsif cc_cnt='1' and unsigned(r.ccnt) > 0 then
n.ccnt := slv(unsigned(r.ccnt) - 1);
end if;
-- pktend time-out handling:
-- if tx fifo is non-empty, set counter to max
-- if tx fifo is empty, count down every ifclk cycle
-- on 1->0 transition queue pktend request
if TXFIFO_VAL = '1' then
n.petocnt := (others=>'1');
else
if unsigned(r.petocnt) /= 0 then
n.petocnt := slv(unsigned(r.petocnt) - 1);
if unsigned(r.petocnt) = 1 then
n.pepend := '1';
end if;
end if;
end if;
n.moni_ep4_sel := '0';
n.moni_ep6_sel := '0';
if r.state = s_rxdisp or r.state = s_rxpipe then
n.moni_ep4_sel := '1';
n.moni_ep4_pf := not FX2_FLAG_N(c_flag_prog);
elsif r.state = s_txdisp then
n.moni_ep6_sel := '1';
n.moni_ep6_pf := not FX2_FLAG_N(c_flag_prog);
end if;
N_REGS <= n;
FX2_FIFO_CE <= ififo_ce;
FX2_FIFO <= ififo;
FX2_SLRD_N <= not islrd;
FX2_SLWR_N <= not islwr;
FX2_SLOE_N <= not isloe;
FX2_PKTEND_N <= not ipktend;
FX2_DATA_CEI <= idata_cei;
FX2_DATA_CEO <= idata_ceo;
FX2_DATA_OE <= idata_oe;
RXFIFO_ENA <= irxfifo_ena;
TXFIFO_HOLD <= itxfifo_hold;
end process proc_next;
proc_moni: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_MONI_C <= fx2ctl_moni_init;
R_MONI_S <= fx2ctl_moni_init;
else
R_MONI_C <= fx2ctl_moni_init;
R_MONI_C.fifo_ep4 <= R_REGS.moni_ep4_sel;
R_MONI_C.fifo_ep6 <= R_REGS.moni_ep6_sel;
R_MONI_C.flag_ep4_empty <= not FX2_FLAG_N(c_flag_rx_ef);
R_MONI_C.flag_ep4_almost <= R_REGS.moni_ep4_pf;
R_MONI_C.flag_ep6_full <= not FX2_FLAG_N(c_flag_tx_ff);
R_MONI_C.flag_ep6_almost <= R_REGS.moni_ep6_pf;
R_MONI_C.slrd <= not FX2_SLRD_N;
R_MONI_C.slwr <= not FX2_SLWR_N;
R_MONI_C.pktend <= not FX2_PKTEND_N;
case R_REGS.state is
when s_idle => R_MONI_C.fsm_idle <= '1';
when s_rxprep0 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_rx <= '1';
when s_rxprep1 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_rx <= '1';
when s_rxprep2 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_rx <= '1';
when s_rxdisp => R_MONI_C.fsm_disp <= '1'; R_MONI_C.fsm_rx <= '1';
when s_rxpipe => R_MONI_C.fsm_pipe <= '1'; R_MONI_C.fsm_rx <= '1';
when s_txprep0 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_tx <= '1';
when s_txprep1 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_tx <= '1';
when s_txprep2 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_tx <= '1';
when s_txdisp => R_MONI_C.fsm_disp <= '1'; R_MONI_C.fsm_tx <= '1';
when others => null;
end case;
R_MONI_S <= R_MONI_C;
end if;
end if;
end process proc_moni;
proc_almost: process (RXSIZE_USR, TXSIZE_USR)
begin
-- rxsize_usr is the number of bytes to read
-- txsize_usr is the number of bytes to write
if unsigned(RXSIZE_USR) <= RXAEMPTY_THRES then
RXAEMPTY <= '1';
else
RXAEMPTY <= '0';
end if;
if unsigned(TXSIZE_USR) <= TXAFULL_THRES then
TXAFULL <= '1';
else
TXAFULL <= '0';
end if;
end process proc_almost;
TXBUSY <= TXBUSY_L;
MONI <= R_MONI_S;
end syn;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Delayed bidirectional wire
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity delay_wire is
generic(
data_width : integer := 1;
delay_atob : real := 0.0;
delay_btoa : real := 0.0
);
port(
a : inout std_logic_vector(data_width-1 downto 0);
b : inout std_logic_vector(data_width-1 downto 0);
x : in std_logic_vector(data_width-1 downto 0) := (others => '0')
);
end delay_wire;
architecture rtl of delay_wire is
signal a_dly,b_dly : std_logic_vector(data_width-1 downto 0) := (others => 'Z');
constant zvector : std_logic_vector(data_width-1 downto 0) := (others => 'Z');
function errinj(a,b: std_logic_vector) return std_logic_vector is
variable r: std_logic_vector(a'length-1 downto 0);
begin
r := a;
for k in a'length-1 downto 0 loop
if (a(k)='0' or a(k)='1') and b(k)='1' then
r(k) := not a(k);
end if;
end loop;
return r;
end;
begin
process(a)
begin
if a'event then
if b_dly = zvector then
a_dly <= transport a after delay_atob*1 ns;
else
a_dly <= (others => 'Z');
end if;
end if;
end process;
process(b)
begin
if b'event then
if a_dly = zvector then
b_dly <= transport errinj(b,x) after delay_btoa*1 ns;
else
b_dly <= (others => 'Z');
end if;
end if;
end process;
a <= b_dly; b <= a_dly;
end;
|
library ieee;
use ieee.std_logic_1164.all;
--This is the initial implementation of a left shift function. There is also a ready function for left or right shift declared in ieee.numeric_std . But we found it out later so we kept our initial implementation.
entity left_shift_by_1 is
port( data_in: in std_logic_vector(0 to 27);
data_out: out std_logic_vector(0 to 27));
end left_shift_by_1;
architecture behavior of left_shift_by_1 is
begin
data_out(0)<=data_in(1);
data_out(1)<=data_in(2);
data_out(2)<=data_in(3);
data_out(3)<=data_in(4);
data_out(4)<=data_in(5);
data_out(5)<=data_in(6);
data_out(6)<=data_in(7);
data_out(7)<=data_in(8);
data_out(8)<=data_in(9);
data_out(9)<=data_in(10);
data_out(10)<=data_in(11);
data_out(11)<=data_in(12);
data_out(12)<=data_in(13);
data_out(13)<=data_in(14);
data_out(14)<=data_in(15);
data_out(15)<=data_in(16);
data_out(16)<=data_in(17);
data_out(17)<=data_in(18);
data_out(18)<=data_in(19);
data_out(19)<=data_in(20);
data_out(20)<=data_in(21);
data_out(21)<=data_in(22);
data_out(22)<=data_in(23);
data_out(23)<=data_in(24);
data_out(24)<=data_in(25);
data_out(25)<=data_in(26);
data_out(26)<=data_in(27);
data_out(27)<=data_in(0);
end behavior;
|
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--
-- Adds
-- U = usb/uvc
-- J = jpeg encoder
-- S = source selector
-- H = Hdmi
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity controller is
port
(
status : out std_logic_vector(4 downto 0);
usb_cmd : out std_logic_vector(2 downto 0); -- UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2)
jpeg_encoder_cmd : out std_logic_vector(1 downto 0); -- encodingQuality(1 downto 0)
selector_cmd : out std_logic_vector(12 downto 0); -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted) (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
HB_on : out std_logic;
uart_rd : out std_logic;
uart_rx_empty : in std_logic;
uart_din : in std_logic_vector(7 downto 0);
uart_clk : in std_logic;
usb_or_uart : in std_logic;
hdmi_cmd : out std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
hdmi_dvi : in std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
rdy_H : in std_logic_vector(1 downto 0);
btnu : in std_logic;
btnd : in std_logic;
btnl : in std_logic;
btnr : in std_logic;
uvc_rst : out std_logic;
cmd_byte : in std_logic_vector(7 downto 0);
cmd_en : in std_logic;
rst : in std_logic;
ifclk : in std_logic;
clk : in std_logic
);
end entity;
ARCHITECTURE rtl OF controller is
COMPONENT cmdfifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
signal usb_cmd_i : std_logic_vector(2 downto 0); -- UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2)
signal jpeg_encoder_cmd_i : std_logic_vector(1 downto 0); -- encodingQuality(1 downto 0)
signal selector_cmd_i : std_logic_vector(12 downto 0); -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted) (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
signal HB_on_i : std_logic;
signal hdmi_cmd_i : std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
signal hdmi_dvi_q : std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
signal counter : std_logic_vector(7 downto 0);
signal cmd : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal add : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal rd_en : STD_LOGIC;
signal dout : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal full : STD_LOGIC;
signal almost_full : STD_LOGIC;
signal empty : STD_LOGIC;
signal almost_empty : STD_LOGIC;
signal valid : STD_LOGIC;
signal uvc_rst_i : STD_LOGIC;
signal vsync_q : STD_LOGIC;
signal vsync_rising_edge : STD_LOGIC;
signal pressed : STD_LOGIC;
signal toggle : STD_LOGIC;
signal uart_rd_s : STD_LOGIC;
signal empty_s : STD_LOGIC;
signal fifo_din : STD_LOGIC_VECTOR(7 downto 0);
signal fifo_clk : STD_LOGIC;
signal fifo_wr : STD_LOGIC;
begin
-- comb logic
usb_cmd <= usb_cmd_i;
jpeg_encoder_cmd <= jpeg_encoder_cmd_i;
selector_cmd <= selector_cmd_i;
hdmi_cmd <= hdmi_cmd_i;
HB_on <= HB_on_i;
-- CMD Decoder
process(rst,clk)
begin
if rst = '1' then
usb_cmd_i <= "001"; -- uvc on/off(2) raw/jpeg(1) UVCpayloadheader(0)
jpeg_encoder_cmd_i <= "00"; -- encodingQuality(1 downto 0)
selector_cmd_i(3 downto 0) <= "0111"; -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted)
selector_cmd_i(12 downto 4) <= "111000000"; --(4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
HB_on_i <= '1';
hdmi_cmd_i <= "11"; -- if 1 then dvi else hdmi
uvc_rst_i <= '1';
pressed <= '0';
hdmi_dvi_q <= "00";
status <= (others => '0');
toggle <= '0';
counter <= (others => '0');
elsif rising_edge(clk) then
if uvc_rst_i = '1' then
uvc_rst <= '1';
counter <= (others => '0');
toggle <= '1';
else
counter <= counter+1;
end if;
if counter = (counter'range => '1') and toggle = '1' then
uvc_rst <= '0';
toggle <= '0';
end if;
uvc_rst_i <= '0';
status <= (others => '0');
rd_en <= '0';
hdmi_dvi_q <= hdmi_dvi;
if (hdmi_dvi_q(0) xor hdmi_dvi(0)) = '1' then
hdmi_cmd_i(0) <= hdmi_dvi(0);
end if;
if (hdmi_dvi_q(1) xor hdmi_dvi(1)) = '1' then
hdmi_cmd_i(1) <= hdmi_dvi(1);
end if;
if btnd = '1' and pressed = '0' then
uvc_rst_i <= '1';
selector_cmd_i(1 downto 0) <= "11";
pressed <= '1';
else
pressed <= '0';
end if;
if btnl = '1' and pressed = '0' and rdy_H(1) = '1' then
uvc_rst_i <= '1';
selector_cmd_i(1 downto 0) <= "01";
pressed <= '1';
else
pressed <= '0';
end if;
if btnu = '1' and pressed = '0' and rdy_H(0) = '1' then
uvc_rst_i <= '1';
selector_cmd_i(1 downto 0) <= "00";
pressed <= '1';
else
pressed <= '0';
end if;
if empty = '0' and rd_en = '0' then
rd_en <= '1';
case add is
when X"55" | X"75" => -- U UVC/USB / UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2)
case cmd is
when X"4a" | X"6a" => -- J j
usb_cmd_i(1) <= '1';
uvc_rst_i <= '1';
when X"52" | X"72" => -- Rr
usb_cmd_i(1) <= '0';
uvc_rst_i <= '1';
when X"4e" | X"6e" => -- N n (on)
usb_cmd_i(2) <= '1';
uvc_rst_i <= '1';
when X"46" | X"66" => -- Ff (off)
usb_cmd_i(2) <= '0';
uvc_rst_i <= '1';
when X"56" | X"76" => -- V v (video) header on
usb_cmd_i(0) <= '1';
uvc_rst_i <= '1';
when X"49" | X"69" => -- I i (image) header off
usb_cmd_i(0) <= '0';
uvc_rst_i <= '1';
when X"53" | X"73" => -- Status
status(0) <= '1';
when X"48" | X"68" => -- H
uvc_rst_i <= '1';
if (selector_cmd_i(1 downto 0) = "00") then -- hdmi 0
hdmi_cmd_i(0) <= '0'; -- HDMI
elsif (selector_cmd_i(1 downto 0) = "01") then -- hdmi 1
hdmi_cmd_i(1) <= '0'; -- HDMI
end if;
when X"44" | X"64" => -- D
uvc_rst_i <= '1';
if (selector_cmd_i(1 downto 0) = "00") then -- hdmi 0
hdmi_cmd_i(0) <= '1'; -- DVI
elsif (selector_cmd_i(1 downto 0) = "01") then -- hdmi 1
hdmi_cmd_i(1) <= '1'; -- DVI
end if;
when others =>
end case;
when X"4a" | X"6a" => -- J Jpeg
case cmd is
when X"53" | X"73" => -- Status
status(1) <= '1';
when X"30" => -- quality 100 %
jpeg_encoder_cmd_i(1 downto 0) <= "00";
when X"31" => -- quality 85%
jpeg_encoder_cmd_i(1 downto 0) <= "01";
when X"32" => -- quality 75%
jpeg_encoder_cmd_i(1 downto 0) <= "10";
when X"33" => -- quality 50%
jpeg_encoder_cmd_i(1 downto 0) <= "11";
when others =>
end case;
when X"48" | X"68" => -- H Hdmi
case cmd is
when X"53" | X"73" => -- Status
status(3) <= '1';
when X"30" => -- Force HDMI 0 to 720p
hdmi_cmd_i(0) <= '0';
uvc_rst_i <= '1';
when X"31" => -- Force HDMI 0 to 1024
hdmi_cmd_i(0) <= '1';
uvc_rst_i <= '1';
when X"32" => -- Force HDMI 1 to 720p
hdmi_cmd_i(1) <= '0';
uvc_rst_i <= '1';
when X"33" => -- Force HDMI 1 to 1024
hdmi_cmd_i(1) <= '1';
uvc_rst_i <= '1';
when others =>
end case;
when X"53" | X"73" => -- S Source Selector
case cmd is -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted) (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
when X"53" | X"73" => -- Status
status(2) <= '1';
when X"55" | X"75" => -- U button force source to HDMI0
if rdy_H(0) = '1' then
selector_cmd_i(1 downto 0) <= "00";
uvc_rst_i <= '1';
end if;
when X"4c" | X"6c" => -- L button force source to HDMI1
if rdy_H(1) = '1' then
selector_cmd_i(1 downto 0) <= "01";
uvc_rst_i <= '1';
end if;
when X"52" | X"72" => -- V button force source to VGA
-- selector_cmd_i(1 downto 0) <= "10";
when X"44" | X"64" => -- D button force source to test pattern
selector_cmd_i(1 downto 0) <= "11";
uvc_rst_i <= '1';
when X"47" | X"67" => -- Froce Gray
selector_cmd_i(2) <= '0';
when X"43" | X"63" => -- Froce Color
selector_cmd_i(2) <= '1';
when X"49" | X"69" => -- Invert Color
selector_cmd_i(3) <= not selector_cmd_i(3);
when X"48" | X"68" => -- Heart Beat On/Off
HB_on_i <= not HB_on_i;
when others =>
end case;
-- RGB (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
when X"52" | X"72" => -- Red
case cmd is
when X"4e" | X"6e" => -- N n (on)
selector_cmd_i(12) <= '1';
when X"46" | X"66" => -- Ff (off)
selector_cmd_i(12) <= '0';
when X"30" =>
selector_cmd_i(9 downto 8) <= "00";
when X"31" =>
selector_cmd_i(9 downto 8) <= "01";
when X"32" =>
selector_cmd_i(9 downto 8) <= "10";
when X"33" =>
selector_cmd_i(9 downto 8) <= "11";
when others =>
end case;
when X"47" | X"67" => -- Green (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
case cmd is
when X"4e" | X"6e" => -- N n (on)
selector_cmd_i(11) <= '1';
when X"46" | X"66" => -- Ff (off)
selector_cmd_i(11) <= '0';
when X"30" =>
selector_cmd_i(7 downto 6) <= "00";
when X"31" =>
selector_cmd_i(7 downto 6) <= "01";
when X"32" =>
selector_cmd_i(7 downto 6) <= "10";
when X"33" =>
selector_cmd_i(7 downto 6) <= "11";
when others =>
end case;
when X"42" | X"62" => -- Blue
case cmd is
when X"4e" | X"6e" => -- N n (on)
selector_cmd_i(10) <= '1';
when X"46" | X"66" => -- Ff (off)
selector_cmd_i(10) <= '0';
when X"30" =>
selector_cmd_i(5 downto 4) <= "00";
when X"31" =>
selector_cmd_i(5 downto 4) <= "01";
when X"32" =>
selector_cmd_i(5 downto 4) <= "10";
when X"33" =>
selector_cmd_i(5 downto 4) <= "11";
when others =>
end case;
when X"44" | X"64" => --Debug
case cmd is
when X"53" | X"73" => --Status
status(4) <= '1';
when others =>
end case;
when others =>
end case; -- case add
end if; -- cmd_en
end if; -- clk
end process;
uart_rd <= uart_rd_s;
uart_ctrl : process(uart_clk, uart_rx_empty, empty_s)
begin
if rst = '1' then
uart_rd_s <= '0';
elsif rising_edge(uart_clk) then
empty_s <= uart_rx_empty;
end if;
if empty_s = '1' and uart_rx_empty = '0' then
uart_rd_s <= '1';
end if;
if empty_s = uart_rx_empty then
uart_rd_s <= '0';
end if;
end process;
fifo_mux: process(usb_or_uart, uart_rd_s, cmd_en, uart_din, cmd_byte, uart_clk, ifclk)
begin
if usb_or_uart = '0' then
fifo_din <= cmd_byte;
fifo_wr <= cmd_en;
fifo_clk <= ifclk;
else
fifo_din <= uart_din;
fifo_wr <= uart_rd_s;
fifo_clk <= uart_clk;
end if;
end process;
cmd <= dout(7 downto 0);
add <= dout(15 downto 8);
cmdfifo_comp : cmdfifo
PORT MAP (
rst => rst,
wr_clk => fifo_clk,
rd_clk => clk,
din => fifo_din,
wr_en => fifo_wr,
rd_en => rd_en,
dout => dout,
full => full,
almost_full => almost_full,
empty => empty,
almost_empty => almost_empty,
valid => valid
);
END ARCHITECTURE;
|
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--
-- Adds
-- U = usb/uvc
-- J = jpeg encoder
-- S = source selector
-- H = Hdmi
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity controller is
port
(
status : out std_logic_vector(4 downto 0);
usb_cmd : out std_logic_vector(2 downto 0); -- UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2)
jpeg_encoder_cmd : out std_logic_vector(1 downto 0); -- encodingQuality(1 downto 0)
selector_cmd : out std_logic_vector(12 downto 0); -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted) (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
HB_on : out std_logic;
uart_rd : out std_logic;
uart_rx_empty : in std_logic;
uart_din : in std_logic_vector(7 downto 0);
uart_clk : in std_logic;
usb_or_uart : in std_logic;
hdmi_cmd : out std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
hdmi_dvi : in std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
rdy_H : in std_logic_vector(1 downto 0);
btnu : in std_logic;
btnd : in std_logic;
btnl : in std_logic;
btnr : in std_logic;
uvc_rst : out std_logic;
cmd_byte : in std_logic_vector(7 downto 0);
cmd_en : in std_logic;
rst : in std_logic;
ifclk : in std_logic;
clk : in std_logic
);
end entity;
ARCHITECTURE rtl OF controller is
COMPONENT cmdfifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
signal usb_cmd_i : std_logic_vector(2 downto 0); -- UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2)
signal jpeg_encoder_cmd_i : std_logic_vector(1 downto 0); -- encodingQuality(1 downto 0)
signal selector_cmd_i : std_logic_vector(12 downto 0); -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted) (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
signal HB_on_i : std_logic;
signal hdmi_cmd_i : std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
signal hdmi_dvi_q : std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
signal counter : std_logic_vector(7 downto 0);
signal cmd : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal add : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal rd_en : STD_LOGIC;
signal dout : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal full : STD_LOGIC;
signal almost_full : STD_LOGIC;
signal empty : STD_LOGIC;
signal almost_empty : STD_LOGIC;
signal valid : STD_LOGIC;
signal uvc_rst_i : STD_LOGIC;
signal vsync_q : STD_LOGIC;
signal vsync_rising_edge : STD_LOGIC;
signal pressed : STD_LOGIC;
signal toggle : STD_LOGIC;
signal uart_rd_s : STD_LOGIC;
signal empty_s : STD_LOGIC;
signal fifo_din : STD_LOGIC_VECTOR(7 downto 0);
signal fifo_clk : STD_LOGIC;
signal fifo_wr : STD_LOGIC;
begin
-- comb logic
usb_cmd <= usb_cmd_i;
jpeg_encoder_cmd <= jpeg_encoder_cmd_i;
selector_cmd <= selector_cmd_i;
hdmi_cmd <= hdmi_cmd_i;
HB_on <= HB_on_i;
-- CMD Decoder
process(rst,clk)
begin
if rst = '1' then
usb_cmd_i <= "001"; -- uvc on/off(2) raw/jpeg(1) UVCpayloadheader(0)
jpeg_encoder_cmd_i <= "00"; -- encodingQuality(1 downto 0)
selector_cmd_i(3 downto 0) <= "0111"; -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted)
selector_cmd_i(12 downto 4) <= "111000000"; --(4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
HB_on_i <= '1';
hdmi_cmd_i <= "11"; -- if 1 then dvi else hdmi
uvc_rst_i <= '1';
pressed <= '0';
hdmi_dvi_q <= "00";
status <= (others => '0');
toggle <= '0';
counter <= (others => '0');
elsif rising_edge(clk) then
if uvc_rst_i = '1' then
uvc_rst <= '1';
counter <= (others => '0');
toggle <= '1';
else
counter <= counter+1;
end if;
if counter = (counter'range => '1') and toggle = '1' then
uvc_rst <= '0';
toggle <= '0';
end if;
uvc_rst_i <= '0';
status <= (others => '0');
rd_en <= '0';
hdmi_dvi_q <= hdmi_dvi;
if (hdmi_dvi_q(0) xor hdmi_dvi(0)) = '1' then
hdmi_cmd_i(0) <= hdmi_dvi(0);
end if;
if (hdmi_dvi_q(1) xor hdmi_dvi(1)) = '1' then
hdmi_cmd_i(1) <= hdmi_dvi(1);
end if;
if btnd = '1' and pressed = '0' then
uvc_rst_i <= '1';
selector_cmd_i(1 downto 0) <= "11";
pressed <= '1';
else
pressed <= '0';
end if;
if btnl = '1' and pressed = '0' and rdy_H(1) = '1' then
uvc_rst_i <= '1';
selector_cmd_i(1 downto 0) <= "01";
pressed <= '1';
else
pressed <= '0';
end if;
if btnu = '1' and pressed = '0' and rdy_H(0) = '1' then
uvc_rst_i <= '1';
selector_cmd_i(1 downto 0) <= "00";
pressed <= '1';
else
pressed <= '0';
end if;
if empty = '0' and rd_en = '0' then
rd_en <= '1';
case add is
when X"55" | X"75" => -- U UVC/USB / UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2)
case cmd is
when X"4a" | X"6a" => -- J j
usb_cmd_i(1) <= '1';
uvc_rst_i <= '1';
when X"52" | X"72" => -- Rr
usb_cmd_i(1) <= '0';
uvc_rst_i <= '1';
when X"4e" | X"6e" => -- N n (on)
usb_cmd_i(2) <= '1';
uvc_rst_i <= '1';
when X"46" | X"66" => -- Ff (off)
usb_cmd_i(2) <= '0';
uvc_rst_i <= '1';
when X"56" | X"76" => -- V v (video) header on
usb_cmd_i(0) <= '1';
uvc_rst_i <= '1';
when X"49" | X"69" => -- I i (image) header off
usb_cmd_i(0) <= '0';
uvc_rst_i <= '1';
when X"53" | X"73" => -- Status
status(0) <= '1';
when X"48" | X"68" => -- H
uvc_rst_i <= '1';
if (selector_cmd_i(1 downto 0) = "00") then -- hdmi 0
hdmi_cmd_i(0) <= '0'; -- HDMI
elsif (selector_cmd_i(1 downto 0) = "01") then -- hdmi 1
hdmi_cmd_i(1) <= '0'; -- HDMI
end if;
when X"44" | X"64" => -- D
uvc_rst_i <= '1';
if (selector_cmd_i(1 downto 0) = "00") then -- hdmi 0
hdmi_cmd_i(0) <= '1'; -- DVI
elsif (selector_cmd_i(1 downto 0) = "01") then -- hdmi 1
hdmi_cmd_i(1) <= '1'; -- DVI
end if;
when others =>
end case;
when X"4a" | X"6a" => -- J Jpeg
case cmd is
when X"53" | X"73" => -- Status
status(1) <= '1';
when X"30" => -- quality 100 %
jpeg_encoder_cmd_i(1 downto 0) <= "00";
when X"31" => -- quality 85%
jpeg_encoder_cmd_i(1 downto 0) <= "01";
when X"32" => -- quality 75%
jpeg_encoder_cmd_i(1 downto 0) <= "10";
when X"33" => -- quality 50%
jpeg_encoder_cmd_i(1 downto 0) <= "11";
when others =>
end case;
when X"48" | X"68" => -- H Hdmi
case cmd is
when X"53" | X"73" => -- Status
status(3) <= '1';
when X"30" => -- Force HDMI 0 to 720p
hdmi_cmd_i(0) <= '0';
uvc_rst_i <= '1';
when X"31" => -- Force HDMI 0 to 1024
hdmi_cmd_i(0) <= '1';
uvc_rst_i <= '1';
when X"32" => -- Force HDMI 1 to 720p
hdmi_cmd_i(1) <= '0';
uvc_rst_i <= '1';
when X"33" => -- Force HDMI 1 to 1024
hdmi_cmd_i(1) <= '1';
uvc_rst_i <= '1';
when others =>
end case;
when X"53" | X"73" => -- S Source Selector
case cmd is -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted) (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
when X"53" | X"73" => -- Status
status(2) <= '1';
when X"55" | X"75" => -- U button force source to HDMI0
if rdy_H(0) = '1' then
selector_cmd_i(1 downto 0) <= "00";
uvc_rst_i <= '1';
end if;
when X"4c" | X"6c" => -- L button force source to HDMI1
if rdy_H(1) = '1' then
selector_cmd_i(1 downto 0) <= "01";
uvc_rst_i <= '1';
end if;
when X"52" | X"72" => -- V button force source to VGA
-- selector_cmd_i(1 downto 0) <= "10";
when X"44" | X"64" => -- D button force source to test pattern
selector_cmd_i(1 downto 0) <= "11";
uvc_rst_i <= '1';
when X"47" | X"67" => -- Froce Gray
selector_cmd_i(2) <= '0';
when X"43" | X"63" => -- Froce Color
selector_cmd_i(2) <= '1';
when X"49" | X"69" => -- Invert Color
selector_cmd_i(3) <= not selector_cmd_i(3);
when X"48" | X"68" => -- Heart Beat On/Off
HB_on_i <= not HB_on_i;
when others =>
end case;
-- RGB (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
when X"52" | X"72" => -- Red
case cmd is
when X"4e" | X"6e" => -- N n (on)
selector_cmd_i(12) <= '1';
when X"46" | X"66" => -- Ff (off)
selector_cmd_i(12) <= '0';
when X"30" =>
selector_cmd_i(9 downto 8) <= "00";
when X"31" =>
selector_cmd_i(9 downto 8) <= "01";
when X"32" =>
selector_cmd_i(9 downto 8) <= "10";
when X"33" =>
selector_cmd_i(9 downto 8) <= "11";
when others =>
end case;
when X"47" | X"67" => -- Green (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
case cmd is
when X"4e" | X"6e" => -- N n (on)
selector_cmd_i(11) <= '1';
when X"46" | X"66" => -- Ff (off)
selector_cmd_i(11) <= '0';
when X"30" =>
selector_cmd_i(7 downto 6) <= "00";
when X"31" =>
selector_cmd_i(7 downto 6) <= "01";
when X"32" =>
selector_cmd_i(7 downto 6) <= "10";
when X"33" =>
selector_cmd_i(7 downto 6) <= "11";
when others =>
end case;
when X"42" | X"62" => -- Blue
case cmd is
when X"4e" | X"6e" => -- N n (on)
selector_cmd_i(10) <= '1';
when X"46" | X"66" => -- Ff (off)
selector_cmd_i(10) <= '0';
when X"30" =>
selector_cmd_i(5 downto 4) <= "00";
when X"31" =>
selector_cmd_i(5 downto 4) <= "01";
when X"32" =>
selector_cmd_i(5 downto 4) <= "10";
when X"33" =>
selector_cmd_i(5 downto 4) <= "11";
when others =>
end case;
when X"44" | X"64" => --Debug
case cmd is
when X"53" | X"73" => --Status
status(4) <= '1';
when others =>
end case;
when others =>
end case; -- case add
end if; -- cmd_en
end if; -- clk
end process;
uart_rd <= uart_rd_s;
uart_ctrl : process(uart_clk, uart_rx_empty, empty_s)
begin
if rst = '1' then
uart_rd_s <= '0';
elsif rising_edge(uart_clk) then
empty_s <= uart_rx_empty;
end if;
if empty_s = '1' and uart_rx_empty = '0' then
uart_rd_s <= '1';
end if;
if empty_s = uart_rx_empty then
uart_rd_s <= '0';
end if;
end process;
fifo_mux: process(usb_or_uart, uart_rd_s, cmd_en, uart_din, cmd_byte, uart_clk, ifclk)
begin
if usb_or_uart = '0' then
fifo_din <= cmd_byte;
fifo_wr <= cmd_en;
fifo_clk <= ifclk;
else
fifo_din <= uart_din;
fifo_wr <= uart_rd_s;
fifo_clk <= uart_clk;
end if;
end process;
cmd <= dout(7 downto 0);
add <= dout(15 downto 8);
cmdfifo_comp : cmdfifo
PORT MAP (
rst => rst,
wr_clk => fifo_clk,
rd_clk => clk,
din => fifo_din,
wr_en => fifo_wr,
rd_en => rd_en,
dout => dout,
full => full,
almost_full => almost_full,
empty => empty,
almost_empty => almost_empty,
valid => valid
);
END ARCHITECTURE;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_PHASE_ACCUMS is
port(
PRESETN : in vl_logic;
HCLK : in vl_logic;
DAC0_IN : in vl_logic_vector(23 downto 0);
DAC1_IN : in vl_logic_vector(23 downto 0);
DAC2_IN : in vl_logic_vector(23 downto 0);
DAC0_CTRL : in vl_logic_vector(7 downto 0);
DAC1_CTRL : in vl_logic_vector(7 downto 0);
DAC2_CTRL : in vl_logic_vector(7 downto 0);
OBD_FPGA0_CLKOUT: in vl_logic;
OBD_FPGA1_CLKOUT: in vl_logic;
OBD_FPGA2_CLKOUT: in vl_logic;
OBD_FPGA0_DOUT : in vl_logic;
OBD_FPGA1_DOUT : in vl_logic;
OBD_FPGA2_DOUT : in vl_logic;
OBD_DOUT0 : out vl_logic;
OBD_DOUT1 : out vl_logic;
OBD_DOUT2 : out vl_logic;
OBD_CLKOUT0 : out vl_logic;
OBD_CLKOUT1 : out vl_logic;
OBD_CLKOUT2 : out vl_logic;
OBD_ENABLE0 : out vl_logic;
OBD_ENABLE1 : out vl_logic;
OBD_ENABLE2 : out vl_logic
);
end F2DSS_SSE_PHASE_ACCUMS;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_PHASE_ACCUMS is
port(
PRESETN : in vl_logic;
HCLK : in vl_logic;
DAC0_IN : in vl_logic_vector(23 downto 0);
DAC1_IN : in vl_logic_vector(23 downto 0);
DAC2_IN : in vl_logic_vector(23 downto 0);
DAC0_CTRL : in vl_logic_vector(7 downto 0);
DAC1_CTRL : in vl_logic_vector(7 downto 0);
DAC2_CTRL : in vl_logic_vector(7 downto 0);
OBD_FPGA0_CLKOUT: in vl_logic;
OBD_FPGA1_CLKOUT: in vl_logic;
OBD_FPGA2_CLKOUT: in vl_logic;
OBD_FPGA0_DOUT : in vl_logic;
OBD_FPGA1_DOUT : in vl_logic;
OBD_FPGA2_DOUT : in vl_logic;
OBD_DOUT0 : out vl_logic;
OBD_DOUT1 : out vl_logic;
OBD_DOUT2 : out vl_logic;
OBD_CLKOUT0 : out vl_logic;
OBD_CLKOUT1 : out vl_logic;
OBD_CLKOUT2 : out vl_logic;
OBD_ENABLE0 : out vl_logic;
OBD_ENABLE1 : out vl_logic;
OBD_ENABLE2 : out vl_logic
);
end F2DSS_SSE_PHASE_ACCUMS;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_PHASE_ACCUMS is
port(
PRESETN : in vl_logic;
HCLK : in vl_logic;
DAC0_IN : in vl_logic_vector(23 downto 0);
DAC1_IN : in vl_logic_vector(23 downto 0);
DAC2_IN : in vl_logic_vector(23 downto 0);
DAC0_CTRL : in vl_logic_vector(7 downto 0);
DAC1_CTRL : in vl_logic_vector(7 downto 0);
DAC2_CTRL : in vl_logic_vector(7 downto 0);
OBD_FPGA0_CLKOUT: in vl_logic;
OBD_FPGA1_CLKOUT: in vl_logic;
OBD_FPGA2_CLKOUT: in vl_logic;
OBD_FPGA0_DOUT : in vl_logic;
OBD_FPGA1_DOUT : in vl_logic;
OBD_FPGA2_DOUT : in vl_logic;
OBD_DOUT0 : out vl_logic;
OBD_DOUT1 : out vl_logic;
OBD_DOUT2 : out vl_logic;
OBD_CLKOUT0 : out vl_logic;
OBD_CLKOUT1 : out vl_logic;
OBD_CLKOUT2 : out vl_logic;
OBD_ENABLE0 : out vl_logic;
OBD_ENABLE1 : out vl_logic;
OBD_ENABLE2 : out vl_logic
);
end F2DSS_SSE_PHASE_ACCUMS;
|
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: addition/subtraction entity for the addition/subtraction unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: [email protected]
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use IEEE.std_logic_arith.all;
library work;
use work.fpupack.all;
entity addsub_28 is
port(
clk_i : in std_logic;
fpu_op_i : in std_logic;
fracta_i : in std_logic_vector(FRAC_WIDTH+4 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
fractb_i : in std_logic_vector(FRAC_WIDTH+4 downto 0);
signa_i : in std_logic;
signb_i : in std_logic;
fract_o : out std_logic_vector(FRAC_WIDTH+4 downto 0);
sign_o : out std_logic);
end addsub_28;
architecture rtl of addsub_28 is
signal s_fracta_i, s_fractb_i : std_logic_vector(FRAC_WIDTH+4 downto 0);
signal s_fract_o : std_logic_vector(FRAC_WIDTH+4 downto 0);
signal s_signa_i, s_signb_i, s_sign_o : std_logic;
signal s_fpu_op_i : std_logic;
signal fracta_lt_fractb : std_logic;
signal s_addop: std_logic;
begin
-- Input Register
--process(clk_i)
--begin
-- if rising_edge(clk_i) then
s_fracta_i <= fracta_i;
s_fractb_i <= fractb_i;
s_signa_i<= signa_i;
s_signb_i<= signb_i;
s_fpu_op_i <= fpu_op_i;
-- end if;
--end process;
-- Output Register
process(clk_i)
begin
if rising_edge(clk_i) then
fract_o <= s_fract_o;
sign_o <= s_sign_o;
end if;
end process;
fracta_lt_fractb <= '1' when s_fracta_i > s_fractb_i else '0';
-- check if its a subtraction or an addition operation
s_addop <= ((s_signa_i xor s_signb_i)and not (s_fpu_op_i)) or ((s_signa_i xnor s_signb_i)and (s_fpu_op_i));
-- sign of result
s_sign_o <= '0' when s_fract_o = conv_std_logic_vector(0,28) and (s_signa_i and s_signb_i)='0' else
((not s_signa_i) and ((not fracta_lt_fractb) and (fpu_op_i xor s_signb_i))) or
((s_signa_i) and (fracta_lt_fractb or (fpu_op_i xor s_signb_i)));
-- add/substract
process(s_fracta_i, s_fractb_i, s_addop, fracta_lt_fractb)
begin
if s_addop='0' then
s_fract_o <= s_fracta_i + s_fractb_i;
else
if fracta_lt_fractb = '1' then
s_fract_o <= s_fracta_i - s_fractb_i;
else
s_fract_o <= s_fractb_i - s_fracta_i;
end if;
end if;
end process;
end rtl;
|
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: addition/subtraction entity for the addition/subtraction unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: [email protected]
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use IEEE.std_logic_arith.all;
library work;
use work.fpupack.all;
entity addsub_28 is
port(
clk_i : in std_logic;
fpu_op_i : in std_logic;
fracta_i : in std_logic_vector(FRAC_WIDTH+4 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
fractb_i : in std_logic_vector(FRAC_WIDTH+4 downto 0);
signa_i : in std_logic;
signb_i : in std_logic;
fract_o : out std_logic_vector(FRAC_WIDTH+4 downto 0);
sign_o : out std_logic);
end addsub_28;
architecture rtl of addsub_28 is
signal s_fracta_i, s_fractb_i : std_logic_vector(FRAC_WIDTH+4 downto 0);
signal s_fract_o : std_logic_vector(FRAC_WIDTH+4 downto 0);
signal s_signa_i, s_signb_i, s_sign_o : std_logic;
signal s_fpu_op_i : std_logic;
signal fracta_lt_fractb : std_logic;
signal s_addop: std_logic;
begin
-- Input Register
--process(clk_i)
--begin
-- if rising_edge(clk_i) then
s_fracta_i <= fracta_i;
s_fractb_i <= fractb_i;
s_signa_i<= signa_i;
s_signb_i<= signb_i;
s_fpu_op_i <= fpu_op_i;
-- end if;
--end process;
-- Output Register
process(clk_i)
begin
if rising_edge(clk_i) then
fract_o <= s_fract_o;
sign_o <= s_sign_o;
end if;
end process;
fracta_lt_fractb <= '1' when s_fracta_i > s_fractb_i else '0';
-- check if its a subtraction or an addition operation
s_addop <= ((s_signa_i xor s_signb_i)and not (s_fpu_op_i)) or ((s_signa_i xnor s_signb_i)and (s_fpu_op_i));
-- sign of result
s_sign_o <= '0' when s_fract_o = conv_std_logic_vector(0,28) and (s_signa_i and s_signb_i)='0' else
((not s_signa_i) and ((not fracta_lt_fractb) and (fpu_op_i xor s_signb_i))) or
((s_signa_i) and (fracta_lt_fractb or (fpu_op_i xor s_signb_i)));
-- add/substract
process(s_fracta_i, s_fractb_i, s_addop, fracta_lt_fractb)
begin
if s_addop='0' then
s_fract_o <= s_fracta_i + s_fractb_i;
else
if fracta_lt_fractb = '1' then
s_fract_o <= s_fracta_i - s_fractb_i;
else
s_fract_o <= s_fractb_i - s_fracta_i;
end if;
end if;
end process;
end rtl;
|
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: addition/subtraction entity for the addition/subtraction unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: [email protected]
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use IEEE.std_logic_arith.all;
library work;
use work.fpupack.all;
entity addsub_28 is
port(
clk_i : in std_logic;
fpu_op_i : in std_logic;
fracta_i : in std_logic_vector(FRAC_WIDTH+4 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
fractb_i : in std_logic_vector(FRAC_WIDTH+4 downto 0);
signa_i : in std_logic;
signb_i : in std_logic;
fract_o : out std_logic_vector(FRAC_WIDTH+4 downto 0);
sign_o : out std_logic);
end addsub_28;
architecture rtl of addsub_28 is
signal s_fracta_i, s_fractb_i : std_logic_vector(FRAC_WIDTH+4 downto 0);
signal s_fract_o : std_logic_vector(FRAC_WIDTH+4 downto 0);
signal s_signa_i, s_signb_i, s_sign_o : std_logic;
signal s_fpu_op_i : std_logic;
signal fracta_lt_fractb : std_logic;
signal s_addop: std_logic;
begin
-- Input Register
--process(clk_i)
--begin
-- if rising_edge(clk_i) then
s_fracta_i <= fracta_i;
s_fractb_i <= fractb_i;
s_signa_i<= signa_i;
s_signb_i<= signb_i;
s_fpu_op_i <= fpu_op_i;
-- end if;
--end process;
-- Output Register
process(clk_i)
begin
if rising_edge(clk_i) then
fract_o <= s_fract_o;
sign_o <= s_sign_o;
end if;
end process;
fracta_lt_fractb <= '1' when s_fracta_i > s_fractb_i else '0';
-- check if its a subtraction or an addition operation
s_addop <= ((s_signa_i xor s_signb_i)and not (s_fpu_op_i)) or ((s_signa_i xnor s_signb_i)and (s_fpu_op_i));
-- sign of result
s_sign_o <= '0' when s_fract_o = conv_std_logic_vector(0,28) and (s_signa_i and s_signb_i)='0' else
((not s_signa_i) and ((not fracta_lt_fractb) and (fpu_op_i xor s_signb_i))) or
((s_signa_i) and (fracta_lt_fractb or (fpu_op_i xor s_signb_i)));
-- add/substract
process(s_fracta_i, s_fractb_i, s_addop, fracta_lt_fractb)
begin
if s_addop='0' then
s_fract_o <= s_fracta_i + s_fractb_i;
else
if fracta_lt_fractb = '1' then
s_fract_o <= s_fracta_i - s_fractb_i;
else
s_fract_o <= s_fractb_i - s_fracta_i;
end if;
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port(reset,rb,eq,d7,d711,d2312:in bit;
roll,win,lose,sp:out bit);
end control;
architecture con of control is
signal count:std_logic_vector(3 downto 0):="0000";
signal w,l:bit;
begin
process(reset,rb)
begin
if reset='0' then
sp<='1';
count<="0000";
elsif rb'event and rb='1' then
count<=count+1;
elsif rb'event and rb='0' and count="0001" then
sp<='0';
end if;
roll<=not rb;
end process;
process(count,eq,d7,d711,d2312)
begin
--if w='0' and l='0' then
if count="0000" then
w <='0';l <='0';
elsif count="0001" then
w <=d711;l <=d2312;
else
w <=eq;l <=d7;
end if;
--end if;
end process;
win<=w;
lose<=l;
end con; |
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.fixed_generic_pkg.all;
use work.fixed_float_types.all;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.complex_const_mult_pkg.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity complex_const_mult_s is
generic(
SPEED_opt : T_speed := t_exc;
ROUND_STYLE_opt : T_round_style := fixed_truncate;
ROUND_TO_BIT_opt : integer_exc := integer'low;
MAX_ERROR_PCT_opt : real_exc := real'low;
MIN_OUTPUT_BIT : integer := integer'low;
MULTIPLICAND_REAL : real;
MULTIPLICAND_IMAG : real
);
port(
clk : in std_ulogic;
input_real : in u_sfixed;
input_imag : in u_sfixed;
valid_input : in std_ulogic;
output_real : out u_sfixed;
output_imag : out u_sfixed;
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture complex_const_mult_s_1 of complex_const_mult_s is
/*================================================================================================*/
/*================================================================================================*/
begin
complex_const_mult_core_s_1:
entity work.complex_const_mult_core_s
generic map(
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
MULTIPLICAND_REAL => MULTIPLICAND_REAL,
MULTIPLICAND_IMAG => MULTIPLICAND_IMAG,
INPUT_HIGH => input_real'high,
INPUT_LOW => input_real'low
)
port map(
clk => clk,
input_real => input_real,
input_imag => input_imag,
valid_input => valid_input,
output_real => output_real,
output_imag => output_imag,
valid_output => valid_output
);
end architecture; |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_ire.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
use work.dlx_types.all;
entity ir_extender is
generic ( Tpd : delay_length );
port ( d : in dlx_word;
q : out dlx_word;
immed_size_26 : in std_logic;
immed_unsigned : in std_logic;
immed_en : in std_logic );
end entity ir_extender;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_ire.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
use work.dlx_types.all;
entity ir_extender is
generic ( Tpd : delay_length );
port ( d : in dlx_word;
q : out dlx_word;
immed_size_26 : in std_logic;
immed_unsigned : in std_logic;
immed_en : in std_logic );
end entity ir_extender;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_ire.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
use work.dlx_types.all;
entity ir_extender is
generic ( Tpd : delay_length );
port ( d : in dlx_word;
q : out dlx_word;
immed_size_26 : in std_logic;
immed_unsigned : in std_logic;
immed_en : in std_logic );
end entity ir_extender;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_v10:3.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_v10_v3_0_9;
USE lmb_v10_v3_0_9.lmb_v10;
ENTITY system_dlmb_v10_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
SYS_Rst : IN STD_LOGIC;
LMB_Rst : OUT STD_LOGIC;
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
M_ReadStrobe : IN STD_LOGIC;
M_WriteStrobe : IN STD_LOGIC;
M_AddrStrobe : IN STD_LOGIC;
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_ReadStrobe : OUT STD_LOGIC;
LMB_WriteStrobe : OUT STD_LOGIC;
LMB_AddrStrobe : OUT STD_LOGIC;
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Ready : OUT STD_LOGIC;
LMB_Wait : OUT STD_LOGIC;
LMB_UE : OUT STD_LOGIC;
LMB_CE : OUT STD_LOGIC;
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
);
END system_dlmb_v10_0;
ARCHITECTURE system_dlmb_v10_0_arch OF system_dlmb_v10_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_dlmb_v10_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_v10 IS
GENERIC (
C_LMB_NUM_SLAVES : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_LMB_AWIDTH : INTEGER;
C_EXT_RESET_HIGH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
SYS_Rst : IN STD_LOGIC;
LMB_Rst : OUT STD_LOGIC;
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
M_ReadStrobe : IN STD_LOGIC;
M_WriteStrobe : IN STD_LOGIC;
M_AddrStrobe : IN STD_LOGIC;
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_ReadStrobe : OUT STD_LOGIC;
LMB_WriteStrobe : OUT STD_LOGIC;
LMB_AddrStrobe : OUT STD_LOGIC;
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Ready : OUT STD_LOGIC;
LMB_Wait : OUT STD_LOGIC;
LMB_UE : OUT STD_LOGIC;
LMB_CE : OUT STD_LOGIC;
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
);
END COMPONENT lmb_v10;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_dlmb_v10_0_arch: ARCHITECTURE IS "lmb_v10,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_dlmb_v10_0_arch : ARCHITECTURE IS "system_dlmb_v10_0,lmb_v10,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_dlmb_v10_0_arch: ARCHITECTURE IS "system_dlmb_v10_0,lmb_v10,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_v10,x_ipVersion=3.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_LMB_NUM_SLAVES=1,C_LMB_DWIDTH=32,C_LMB_AWIDTH=32,C_EXT_RESET_HIGH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_M RST";
ATTRIBUTE X_INTERFACE_INFO OF M_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ABUS";
ATTRIBUTE X_INTERFACE_INFO OF M_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF M_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READY";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WAIT";
ATTRIBUTE X_INTERFACE_INFO OF LMB_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M UE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M CE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE";
BEGIN
U0 : lmb_v10
GENERIC MAP (
C_LMB_NUM_SLAVES => 1,
C_LMB_DWIDTH => 32,
C_LMB_AWIDTH => 32,
C_EXT_RESET_HIGH => 1
)
PORT MAP (
LMB_Clk => LMB_Clk,
SYS_Rst => SYS_Rst,
LMB_Rst => LMB_Rst,
M_ABus => M_ABus,
M_ReadStrobe => M_ReadStrobe,
M_WriteStrobe => M_WriteStrobe,
M_AddrStrobe => M_AddrStrobe,
M_DBus => M_DBus,
M_BE => M_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB_ABus => LMB_ABus,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadDBus => LMB_ReadDBus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_Ready => LMB_Ready,
LMB_Wait => LMB_Wait,
LMB_UE => LMB_UE,
LMB_CE => LMB_CE,
LMB_BE => LMB_BE
);
END system_dlmb_v10_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity simple01 is
port (a, b, c : in std_logic;
z : out std_logic);
end simple01;
architecture behav of simple01 is
begin
process(A, B, C)
variable temp : std_logic;
begin
case a is
when '1' =>
assert b = '0';
z <= '0';
when '0' =>
z <= '1';
when others =>
z <= 'X';
end case;
end process;
end behav;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
-- WARNING! This package will be deprecated and no longer receive updates or bug fixes!
-- The data_queue_pkg in uvvm_util/src/data_queue_pkg.vhd has replaced ti_data_queue_pkg
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
package ti_data_queue_pkg is
-- Declaration of storage
subtype t_data_buffer is std_logic_vector(C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1 downto 0);
shared variable shared_data_buffer : t_data_buffer;
type t_buffer_natural_array is array (C_NUMBER_OF_DATA_BUFFERS-1 downto 0) of natural;
type t_buffer_boolean_array is array (C_NUMBER_OF_DATA_BUFFERS-1 downto 0) of boolean;
type t_data_queue is protected
------------------------------------------
-- init_queue
------------------------------------------
-- This function allocates space in the buffer and returns an index that
-- must be used to access the queue.
--
-- - Parameters:
-- - queue_size_in_bits (natural) - The size of the queue
-- - scope - Log scope for all alerts/logs
--
-- - Returns: The index of the initiated queue (natural).
-- Returns 0 on error.
--
impure function init_queue(
queue_size_in_bits : natural;
scope : string := "data_queue"
) return natural;
------------------------------------------
-- init_queue
------------------------------------------
-- This procedure allocates space in the buffer at the given queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be initialized.
-- - queue_size_in_bits (natural) - The size of the queue
-- - scope - Log scope for all alerts/logs
--
procedure init_queue(
queue_idx : natural;
queue_size_in_bits : natural;
scope : string := "data_queue"
);
------------------------------------------
-- flush
------------------------------------------
-- This procedure empties the queue given
-- by queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be flushed.
--
procedure flush(
queue_idx : natural
);
------------------------------------------
-- push_back
------------------------------------------
-- This procedure pushes data to the end of a queue.
-- The size of the data is unconstrained, meaning that
-- it can be any size. Pushing data with a size that is
-- larger than the queue size results in wrapping, i.e.,
-- that when reaching the end the data remaining will over-
-- write the data that was written first.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be pushed to.
-- - data - The data that shall be pushed (slv)
--
procedure push_back(
queue_idx : natural;
data : std_logic_vector
);
------------------------------------------
-- peek_front
------------------------------------------
-- This function returns the data from the front
-- of the queue without popping it.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the front of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the queue size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function peek_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- peek_back
------------------------------------------
-- This function returns the data from the back
-- of the queue without popping it.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the back of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the queue size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function peek_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- pop_back
------------------------------------------
-- This function returns the data from the back
-- and removes the returned data from the queue.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the back of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to pop from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to pop a larger value than the queue size is allowed
-- but triggers a TB_WARNING.
--
--
impure function pop_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- pop_front
------------------------------------------
-- This function returns the data from the front
-- and removes the returned data from the queue.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the front of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to pop from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to pop a larger value than the queue size is allowed
-- but triggers a TB_WARNING.
--
--
impure function pop_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- get_count
------------------------------------------
-- This function returns a natural indicating the number of elements
-- currently occupying the buffer given by queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
--
-- - Returns: The number of elements occupying the queue (natural).
--
--
impure function get_count(
queue_idx : natural
) return natural;
------------------------------------------
-- get_queue_count_max
------------------------------------------
-- This function returns a natural indicating the maximum number
-- of elements that can occupy the buffer given by queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
--
-- - Returns: The maximum number of elements that can be placed
-- in the queue (natural).
--
--
impure function get_queue_count_max(
queue_idx : natural
) return natural;
------------------------------------------
-- get_queue_is_full
------------------------------------------
-- This function returns a boolean indicating if the
-- queue is full or not.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
--
-- - Returns: TRUE if queue is full, FALSE if not.
--
--
impure function get_queue_is_full(
queue_idx : natural
) return boolean;
------------------------------------------
-- deallocate_buffer
------------------------------------------
-- This procedure resets the entire std_logic_vector and all
-- variable arrays related to the buffer, effectively removing all queues.
--
-- - Parameters:
-- - dummy - VOID
--
--
procedure deallocate_buffer(
dummy : t_void
);
end protected;
end package ti_data_queue_pkg;
package body ti_data_queue_pkg is
type t_data_queue is protected body
-- Internal variables for the data queue
-- The buffer is one large std_logic_vector of size C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER.
-- There are several queues that can be instantiated in the slv.
-- There is one set of variables per queue.
variable v_queue_initialized : t_buffer_boolean_array := (others => false);
variable v_queue_size_in_bits : t_buffer_natural_array := (others => 0);
variable v_count : t_buffer_natural_array := (others => 0);
-- min_idx/max idx: These variables set the upper and lower limit of each queue in the buffer.
-- This is how the large slv buffer is divided into several smaller queues.
-- After a queue has been instantiated, all queue operations in the buffer
-- for a given idx will happen within the v_min_idx and v_max_idx boundary.
-- These variables will be set when a queue is instantiated, and will not
-- change afterwards.
variable v_min_idx : t_buffer_natural_array := (others => 0);
variable v_max_idx : t_buffer_natural_array := (others => 0);
variable v_next_available_idx : natural := 0; -- Where the v_min_idx of the next queue initialized shall be set.
-- first_idx/last_idx: These variables set the current indices within a queue, i.e., within
-- the min_idx/max_idx boundary. These variables will change every time
-- a given queue has data pushed or popped.
variable v_first_idx : t_buffer_natural_array := (others => 0);
variable v_last_idx : t_buffer_natural_array := (others => 0);
type t_string_pointer is access string;
variable v_scope : t_string_pointer := NULL;
------------------------------------------
-- init_queue
------------------------------------------
impure function init_queue(
queue_size_in_bits : natural;
scope : string := "data_queue"
) return natural is
variable vr_queue_idx : natural;
variable vr_queue_idx_found : boolean := false;
begin
if v_scope = NULL then
v_scope := new string'(scope);
end if;
if not check_value(v_next_available_idx < C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER, TB_ERROR,
"init_queue called, but no more space in buffer!", v_scope.all, ID_NEVER)
then
return 0;
end if;
-- Find first available queue
-- and tag as initialized
for i in t_buffer_boolean_array'range loop
if not v_queue_initialized(i) then
-- Save queue idx
vr_queue_idx := i;
vr_queue_idx_found := true;
-- Tag this queue as initialized
v_queue_initialized(vr_queue_idx) := true;
exit; -- exit loop
end if;
end loop;
-- Verify that an available queue idx was found, else trigger alert and return 0
if not check_value(vr_queue_idx_found, TB_ERROR,
"init_queue called, but all queues have already been initialized!", v_scope.all, ID_NEVER)
then
return 0;
end if;
-- Set buffer size for this buffer to queue_size_in_bits
if queue_size_in_bits <= (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - (v_next_available_idx - 1) then -- less than or equal to the remaining total buffer space available
v_queue_size_in_bits(vr_queue_idx) := queue_size_in_bits;
else
alert(TB_ERROR, "queue_size_in_bits larger than maximum allowed!", v_scope.all);
v_queue_size_in_bits(vr_queue_idx) := (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - v_next_available_idx; -- Set to remaining available bits
end if;
-- Set starting and ending indices for this queue_idx
v_min_idx(vr_queue_idx) := v_next_available_idx;
v_max_idx(vr_queue_idx) := v_min_idx(vr_queue_idx) + v_queue_size_in_bits(vr_queue_idx) - 1;
v_first_idx(vr_queue_idx) := v_min_idx(vr_queue_idx);
v_last_idx(vr_queue_idx) := v_min_idx(vr_queue_idx);
v_next_available_idx := v_max_idx(vr_queue_idx) + 1;
log(ID_UVVM_DATA_QUEUE, "Queue " & to_string(vr_queue_idx) & " initialized with buffer size " & to_string(v_queue_size_in_bits(vr_queue_idx)) & ".", v_scope.all);
-- Clear the buffer just to be sure
flush(vr_queue_idx);
-- Return the index of the buffer
return vr_queue_idx;
end function;
------------------------------------------
-- init_queue
------------------------------------------
procedure init_queue(
queue_idx : natural;
queue_size_in_bits : natural;
scope : string := "data_queue"
) is
begin
if v_scope = NULL then
v_scope := new string'(scope);
end if;
if not v_queue_initialized(queue_idx) then
-- Set buffer size for this buffer to queue_size_in_bits
if queue_size_in_bits <= (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - (v_next_available_idx - 1) then -- less than or equal to the remaining total buffer space available
v_queue_size_in_bits(queue_idx) := queue_size_in_bits;
else
alert(TB_ERROR, "queue_size_in_bits larger than maximum allowed!", v_scope.all);
v_queue_size_in_bits(queue_idx) := (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - v_next_available_idx; -- Set to remaining available bits
end if;
-- Set starting and ending indices for this queue_idx
v_min_idx(queue_idx) := v_next_available_idx;
v_max_idx(queue_idx) := v_min_idx(queue_idx) + v_queue_size_in_bits(queue_idx) - 1;
v_first_idx(queue_idx) := v_min_idx(queue_idx);
v_last_idx(queue_idx) := v_min_idx(queue_idx);
v_next_available_idx := v_max_idx(queue_idx) + 1;
-- Tag this buffer as initialized
v_queue_initialized(queue_idx) := true;
log(ID_UVVM_DATA_QUEUE, "Queue " & to_string(queue_idx) & " initialized with buffer size " & to_string(v_queue_size_in_bits(queue_idx)) & ".", v_scope.all);
-- Clear the buffer just to be sure
flush(queue_idx);
else
alert(TB_ERROR, "init_queue called, but the desired buffer index is already in use! No action taken.", v_scope.all);
return;
end if;
end procedure;
------------------------------------------
-- push_back
------------------------------------------
procedure push_back(
queue_idx : natural;
data : std_logic_vector
) is
alias a_data : std_logic_vector(data'length - 1 downto 0) is data;
begin
if check_value(v_queue_initialized(queue_idx), TB_ERROR,
"push_back called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER)
then
for i in a_data'right to a_data'left loop -- From right to left since LSB shall be first in the queue.
shared_data_buffer(v_last_idx(queue_idx)) := a_data(i);
if v_last_idx(queue_idx) /= v_max_idx(queue_idx) then
v_last_idx(queue_idx) := v_last_idx(queue_idx) + 1;
else
v_last_idx(queue_idx) := v_min_idx(queue_idx);
end if;
v_count(queue_idx) := v_count(queue_idx) + 1;
end loop;
log(ID_UVVM_DATA_QUEUE, "Data " & to_string(data, HEX) & " pushed to back of queue " & to_string(queue_idx) & " (index " & to_string(v_last_idx(queue_idx)) & "). Fill level is " & to_string(v_count(queue_idx)) & "/" & to_string(v_queue_size_in_bits(queue_idx)) & ".", v_scope.all);
end if;
end procedure;
------------------------------------------
-- flush
------------------------------------------
procedure flush(
queue_idx : natural
) is
begin
check_value(v_queue_initialized(queue_idx), TB_WARNING, "flush called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
shared_data_buffer(v_max_idx(queue_idx) downto v_min_idx(queue_idx)) := (others => '0');
v_first_idx(queue_idx) := v_min_idx(queue_idx);
v_last_idx(queue_idx) := v_min_idx(queue_idx);
v_count(queue_idx) := 0;
end procedure;
------------------------------------------
-- peek_front
------------------------------------------
impure function peek_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits - 1 downto 0) := (others => '0');
variable v_current_idx : natural;
begin
check_value(v_queue_initialized(queue_idx), TB_ERROR, "peek_front() called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
check_value(v_count(queue_idx) > 0, TB_WARNING, "peek_front() when queue " & to_string(queue_idx) & " is empty. Return value will be garbage.", v_scope.all, ID_NEVER);
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "peek_front called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
v_current_idx := v_first_idx(queue_idx);
-- Generate return value
for i in 0 to v_return_entry'length - 1 loop
v_return_entry(i) := shared_data_buffer(v_current_idx);
if v_current_idx < v_max_idx(queue_idx) then
v_current_idx := v_current_idx + 1;
else
v_current_idx := v_min_idx(queue_idx);
end if;
end loop;
return v_return_entry;
end function;
------------------------------------------
-- peek_back
------------------------------------------
impure function peek_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits - 1 downto 0) := (others => '0');
variable v_current_idx : natural;
begin
check_value(v_queue_initialized(queue_idx), TB_ERROR, "peek_back called, but queue not initialized.", v_scope.all, ID_NEVER);
check_value(v_count(queue_idx) > 0, TB_WARNING, "peek_back() when queue " & to_string(queue_idx) & " is empty. Return value will be garbage.", v_scope.all, ID_NEVER);
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "peek_back called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
if v_last_idx(queue_idx) > 0 then
v_current_idx := v_last_idx(queue_idx) - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
-- Generate return value
for i in v_return_entry'length - 1 downto 0 loop
v_return_entry(i) := shared_data_buffer(v_current_idx);
if v_current_idx > v_min_idx(queue_idx) then
v_current_idx := v_current_idx - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
end loop;
return v_return_entry;
end function;
------------------------------------------
-- pop_back
------------------------------------------
impure function pop_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits-1 downto 0);
variable v_current_idx : natural;
begin
check_value(v_queue_initialized(queue_idx), TB_ERROR, "pop_back called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "pop_back called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
if v_queue_initialized(queue_idx) then
v_return_entry := peek_back(queue_idx, entry_size_in_bits);
if v_count(queue_idx) > 0 then
if v_last_idx(queue_idx) > v_min_idx(queue_idx) then
v_current_idx := v_last_idx(queue_idx) - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
-- Clear fields that belong to the return value
for i in 0 to entry_size_in_bits - 1 loop
shared_data_buffer(v_current_idx) := '0';
if v_current_idx > v_min_idx(queue_idx) then
v_current_idx := v_current_idx - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
v_count(queue_idx) := v_count(queue_idx) - 1;
end loop;
-- Set last idx
if v_current_idx < v_max_idx(queue_idx) then
v_last_idx(queue_idx) := v_current_idx + 1;
else
v_last_idx(queue_idx) := v_min_idx(queue_idx);
end if;
end if;
end if;
return v_return_entry;
end function;
------------------------------------------
-- pop_front
------------------------------------------
impure function pop_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits-1 downto 0);
variable v_current_idx : natural := v_first_idx(queue_idx);
begin
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "pop_front called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
if check_value(v_queue_initialized(queue_idx), TB_ERROR,
"pop_front called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER)
then
v_return_entry := peek_front(queue_idx, entry_size_in_bits);
if v_count(queue_idx) > 0 then
-- v_first_idx points to the idx PREVIOUS to the first element in the buffer.
-- Therefore must correct if at max_idx.
v_current_idx := v_first_idx(queue_idx);
-- Clear fields that belong to the return value
for i in 0 to entry_size_in_bits - 1 loop
shared_data_buffer(v_current_idx) := '0';
if v_current_idx < v_max_idx(queue_idx) then
v_current_idx := v_current_idx + 1;
else
v_current_idx := v_min_idx(queue_idx);
end if;
v_count(queue_idx) := v_count(queue_idx) - 1;
end loop;
v_first_idx(queue_idx) := v_current_idx;
end if;
return v_return_entry;
end if;
v_return_entry := (others => '0');
return v_return_entry;
end function;
------------------------------------------
-- get_count
------------------------------------------
impure function get_count(
queue_idx : natural
) return natural is
begin
check_value(v_queue_initialized(queue_idx), TB_WARNING, "get_count called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
return v_count(queue_idx);
end function;
------------------------------------------
-- get_queue_count_max
------------------------------------------
impure function get_queue_count_max(
queue_idx : natural
) return natural is
begin
check_value(v_queue_initialized(queue_idx), TB_WARNING, "get_queue_count_max called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
return v_queue_size_in_bits(queue_idx);
end function;
------------------------------------------
-- get_queue_is_full
------------------------------------------
impure function get_queue_is_full(
queue_idx : natural
) return boolean is
begin
check_value(v_queue_initialized(queue_idx), TB_WARNING, "get_queue_is_full called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
if v_count(queue_idx) >= v_queue_size_in_bits(queue_idx) then
return true;
else
return false;
end if;
end function;
------------------------------------------
-- deallocate_buffer
------------------------------------------
procedure deallocate_buffer(
dummy : t_void
) is
begin
shared_data_buffer := (others => '0');
v_queue_initialized := (others => false);
v_queue_size_in_bits := (others => 0);
v_count := (others => 0);
v_min_idx := (others => 0);
v_max_idx := (others => 0);
v_first_idx := (others => 0);
v_last_idx := (others => 0);
v_next_available_idx := 0;
log(ID_UVVM_DATA_QUEUE, "Buffer has been deallocated, i.e., all queues removed.", v_scope.all);
end procedure;
end protected body;
end package body ti_data_queue_pkg;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
library IEEE; use IEEE.std_logic_1164.all;
entity tb_timer_w_stim is
end tb_timer_w_stim;
architecture TB_timer_w_stim of tb_timer_w_stim is
-- Component declarations
-- Signal declarations
terminal in_src, rc_ext : electrical;
signal trig, rst : std_ulogic;
signal tim_out : std_ulogic;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_constant(ideal)
generic map(
level => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
R1 : entity work.resistor(simple)
generic map(
resistance => 10.0e3
)
port map(
pos => in_src,
neg => rc_ext
);
C1 : entity work.capacitor(ideal)
generic map(
cap => 10.0e-6
)
port map(
p1 => rc_ext,
p2 => electrical_ref
);
timer1 : entity work.timer(behavioral)
generic map(
threshold => 2.0,
clamp_on_resistance => 1.0e-3,
clamp_off_resistance => 1.0e6
)
port map(
trigger_n => trig,
reset => rst,
q => tim_out,
rc_ext => rc_ext
);
-- rst
P_rst :
process
begin
wait for 0.000 ns; rst <= '1';
wait for 1.000 ms; rst <= '0';
wait for 100.000 ms; rst <= '1';
wait for 1.000 ms; rst <= '0';
wait;
end process;
-- trig
P_trig :
process
begin
wait for 0.0 ns; trig <= '0';
wait for 5.000 ms; trig <= '1';
wait for 1.0 ms; trig <= '0';
wait for 1.0 ms; trig <= '1';
wait for 40.0 ms; trig <= '1';
wait for 1.0 ms; trig <= '0';
wait for 1.0 ms; trig <= '1';
wait for 40.0 ms; trig <= '1';
wait for 1.0 ms; trig <= '0';
wait for 1.0 ms; trig <= '1';
wait;
end process;
end TB_timer_w_stim;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
library IEEE; use IEEE.std_logic_1164.all;
entity tb_timer_w_stim is
end tb_timer_w_stim;
architecture TB_timer_w_stim of tb_timer_w_stim is
-- Component declarations
-- Signal declarations
terminal in_src, rc_ext : electrical;
signal trig, rst : std_ulogic;
signal tim_out : std_ulogic;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_constant(ideal)
generic map(
level => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
R1 : entity work.resistor(simple)
generic map(
resistance => 10.0e3
)
port map(
pos => in_src,
neg => rc_ext
);
C1 : entity work.capacitor(ideal)
generic map(
cap => 10.0e-6
)
port map(
p1 => rc_ext,
p2 => electrical_ref
);
timer1 : entity work.timer(behavioral)
generic map(
threshold => 2.0,
clamp_on_resistance => 1.0e-3,
clamp_off_resistance => 1.0e6
)
port map(
trigger_n => trig,
reset => rst,
q => tim_out,
rc_ext => rc_ext
);
-- rst
P_rst :
process
begin
wait for 0.000 ns; rst <= '1';
wait for 1.000 ms; rst <= '0';
wait for 100.000 ms; rst <= '1';
wait for 1.000 ms; rst <= '0';
wait;
end process;
-- trig
P_trig :
process
begin
wait for 0.0 ns; trig <= '0';
wait for 5.000 ms; trig <= '1';
wait for 1.0 ms; trig <= '0';
wait for 1.0 ms; trig <= '1';
wait for 40.0 ms; trig <= '1';
wait for 1.0 ms; trig <= '0';
wait for 1.0 ms; trig <= '1';
wait for 40.0 ms; trig <= '1';
wait for 1.0 ms; trig <= '0';
wait for 1.0 ms; trig <= '1';
wait;
end process;
end TB_timer_w_stim;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
library IEEE; use IEEE.std_logic_1164.all;
entity tb_timer_w_stim is
end tb_timer_w_stim;
architecture TB_timer_w_stim of tb_timer_w_stim is
-- Component declarations
-- Signal declarations
terminal in_src, rc_ext : electrical;
signal trig, rst : std_ulogic;
signal tim_out : std_ulogic;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_constant(ideal)
generic map(
level => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
R1 : entity work.resistor(simple)
generic map(
resistance => 10.0e3
)
port map(
pos => in_src,
neg => rc_ext
);
C1 : entity work.capacitor(ideal)
generic map(
cap => 10.0e-6
)
port map(
p1 => rc_ext,
p2 => electrical_ref
);
timer1 : entity work.timer(behavioral)
generic map(
threshold => 2.0,
clamp_on_resistance => 1.0e-3,
clamp_off_resistance => 1.0e6
)
port map(
trigger_n => trig,
reset => rst,
q => tim_out,
rc_ext => rc_ext
);
-- rst
P_rst :
process
begin
wait for 0.000 ns; rst <= '1';
wait for 1.000 ms; rst <= '0';
wait for 100.000 ms; rst <= '1';
wait for 1.000 ms; rst <= '0';
wait;
end process;
-- trig
P_trig :
process
begin
wait for 0.0 ns; trig <= '0';
wait for 5.000 ms; trig <= '1';
wait for 1.0 ms; trig <= '0';
wait for 1.0 ms; trig <= '1';
wait for 40.0 ms; trig <= '1';
wait for 1.0 ms; trig <= '0';
wait for 1.0 ms; trig <= '1';
wait for 40.0 ms; trig <= '1';
wait for 1.0 ms; trig <= '0';
wait for 1.0 ms; trig <= '1';
wait;
end process;
end TB_timer_w_stim;
|
----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: sg_pp_md_top - Structural
-- Description:
-- A top module for string_generator, pre_processing and md5 modules
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity sg_pp_md_top is
port (
clk : in std_logic;
rstn : in std_logic;
i_start_sg : in std_logic;
i_halt_sg : in std_logic;
i_start_md5 : in std_logic;
o_hash : out unsigned(127 downto 0);
o_done_md5 : out std_logic
);
end sg_pp_md_top;
architecture Structural of sg_pp_md_top is
component string_generator
port (
clk : in std_logic;
rstn : in std_logic; -- active low reset ofc
i_start : in std_logic;
i_halt : in std_logic;
o_done : out std_logic;
o_length : out std_logic_vector(2 downto 0); -- max 6 chars
o_string : out std_logic_vector(47 downto 0) -- 6 char string
);
end component;
component pre_process
Port ( i_data : in STD_LOGIC_VECTOR (47 downto 0);
i_length : in STD_LOGIC_VECTOR (2 downto 0);
o_data_0 : out unsigned (31 downto 0);
o_data_1 : out unsigned (31 downto 0);
o_length : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component MD5
port (
clk : in std_logic;
rstn : in std_logic;
i_start : in std_logic;
--i_data : in unsigned(71 downto 0); -- 8 chars + 1 appended bit
i_data_0 : in unsigned(31 downto 0); -- first 4 chars
i_data_1 : in unsigned(31 downto 0); -- next 4 chars
i_length : in std_logic_vector(7 downto 0); -- nbr of chars
o_done : out std_logic;
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end component;
signal s_len_sg_pp : std_logic_vector(2 downto 0); -- length sg->pp
signal s_len_pp_md5 : std_logic_vector(7 downto 0); -- length pp->md5
signal s_string_sg_pp : std_logic_vector(47 downto 0);
signal s_string1_pp_md5 : unsigned(31 downto 0);
signal s_string2_pp_md5 : unsigned(31 downto 0);
begin
sg_inst: string_generator
port map (
clk => clk,
rstn => rstn,
i_start => i_start_sg,
i_halt => i_halt_sg,
o_done => open,
o_length => s_len_sg_pp,
o_string => s_string_sg_pp
);
pp_inst: pre_process
port map(
i_data => s_string_sg_pp,
i_length => s_len_sg_pp,
o_data_0 => s_string1_pp_md5,
o_data_1 => s_string2_pp_md5,
o_length => s_len_pp_md5
);
MD5_inst: MD5
port map (
clk => clk,
rstn => rstn,
i_start => i_start_md5,
i_data_0 => s_string1_pp_md5,
i_data_1 => s_string2_pp_md5,
i_length => s_len_pp_md5,
o_done => o_done_md5,
o_hash_0 => o_hash(31 downto 0),
o_hash_1 => o_hash(63 downto 32),
o_hash_2 => o_hash(95 downto 64),
o_hash_3 => o_hash(127 downto 96)
);
end Structural;
|
----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: sg_pp_md_top - Structural
-- Description:
-- A top module for string_generator, pre_processing and md5 modules
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity sg_pp_md_top is
port (
clk : in std_logic;
rstn : in std_logic;
i_start_sg : in std_logic;
i_halt_sg : in std_logic;
i_start_md5 : in std_logic;
o_hash : out unsigned(127 downto 0);
o_done_md5 : out std_logic
);
end sg_pp_md_top;
architecture Structural of sg_pp_md_top is
component string_generator
port (
clk : in std_logic;
rstn : in std_logic; -- active low reset ofc
i_start : in std_logic;
i_halt : in std_logic;
o_done : out std_logic;
o_length : out std_logic_vector(2 downto 0); -- max 6 chars
o_string : out std_logic_vector(47 downto 0) -- 6 char string
);
end component;
component pre_process
Port ( i_data : in STD_LOGIC_VECTOR (47 downto 0);
i_length : in STD_LOGIC_VECTOR (2 downto 0);
o_data_0 : out unsigned (31 downto 0);
o_data_1 : out unsigned (31 downto 0);
o_length : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component MD5
port (
clk : in std_logic;
rstn : in std_logic;
i_start : in std_logic;
--i_data : in unsigned(71 downto 0); -- 8 chars + 1 appended bit
i_data_0 : in unsigned(31 downto 0); -- first 4 chars
i_data_1 : in unsigned(31 downto 0); -- next 4 chars
i_length : in std_logic_vector(7 downto 0); -- nbr of chars
o_done : out std_logic;
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end component;
signal s_len_sg_pp : std_logic_vector(2 downto 0); -- length sg->pp
signal s_len_pp_md5 : std_logic_vector(7 downto 0); -- length pp->md5
signal s_string_sg_pp : std_logic_vector(47 downto 0);
signal s_string1_pp_md5 : unsigned(31 downto 0);
signal s_string2_pp_md5 : unsigned(31 downto 0);
begin
sg_inst: string_generator
port map (
clk => clk,
rstn => rstn,
i_start => i_start_sg,
i_halt => i_halt_sg,
o_done => open,
o_length => s_len_sg_pp,
o_string => s_string_sg_pp
);
pp_inst: pre_process
port map(
i_data => s_string_sg_pp,
i_length => s_len_sg_pp,
o_data_0 => s_string1_pp_md5,
o_data_1 => s_string2_pp_md5,
o_length => s_len_pp_md5
);
MD5_inst: MD5
port map (
clk => clk,
rstn => rstn,
i_start => i_start_md5,
i_data_0 => s_string1_pp_md5,
i_data_1 => s_string2_pp_md5,
i_length => s_len_pp_md5,
o_done => o_done_md5,
o_hash_0 => o_hash(31 downto 0),
o_hash_1 => o_hash(63 downto 32),
o_hash_2 => o_hash(95 downto 64),
o_hash_3 => o_hash(127 downto 96)
);
end Structural;
|
----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: sg_pp_md_top - Structural
-- Description:
-- A top module for string_generator, pre_processing and md5 modules
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity sg_pp_md_top is
port (
clk : in std_logic;
rstn : in std_logic;
i_start_sg : in std_logic;
i_halt_sg : in std_logic;
i_start_md5 : in std_logic;
o_hash : out unsigned(127 downto 0);
o_done_md5 : out std_logic
);
end sg_pp_md_top;
architecture Structural of sg_pp_md_top is
component string_generator
port (
clk : in std_logic;
rstn : in std_logic; -- active low reset ofc
i_start : in std_logic;
i_halt : in std_logic;
o_done : out std_logic;
o_length : out std_logic_vector(2 downto 0); -- max 6 chars
o_string : out std_logic_vector(47 downto 0) -- 6 char string
);
end component;
component pre_process
Port ( i_data : in STD_LOGIC_VECTOR (47 downto 0);
i_length : in STD_LOGIC_VECTOR (2 downto 0);
o_data_0 : out unsigned (31 downto 0);
o_data_1 : out unsigned (31 downto 0);
o_length : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component MD5
port (
clk : in std_logic;
rstn : in std_logic;
i_start : in std_logic;
--i_data : in unsigned(71 downto 0); -- 8 chars + 1 appended bit
i_data_0 : in unsigned(31 downto 0); -- first 4 chars
i_data_1 : in unsigned(31 downto 0); -- next 4 chars
i_length : in std_logic_vector(7 downto 0); -- nbr of chars
o_done : out std_logic;
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end component;
signal s_len_sg_pp : std_logic_vector(2 downto 0); -- length sg->pp
signal s_len_pp_md5 : std_logic_vector(7 downto 0); -- length pp->md5
signal s_string_sg_pp : std_logic_vector(47 downto 0);
signal s_string1_pp_md5 : unsigned(31 downto 0);
signal s_string2_pp_md5 : unsigned(31 downto 0);
begin
sg_inst: string_generator
port map (
clk => clk,
rstn => rstn,
i_start => i_start_sg,
i_halt => i_halt_sg,
o_done => open,
o_length => s_len_sg_pp,
o_string => s_string_sg_pp
);
pp_inst: pre_process
port map(
i_data => s_string_sg_pp,
i_length => s_len_sg_pp,
o_data_0 => s_string1_pp_md5,
o_data_1 => s_string2_pp_md5,
o_length => s_len_pp_md5
);
MD5_inst: MD5
port map (
clk => clk,
rstn => rstn,
i_start => i_start_md5,
i_data_0 => s_string1_pp_md5,
i_data_1 => s_string2_pp_md5,
i_length => s_len_pp_md5,
o_done => o_done_md5,
o_hash_0 => o_hash(31 downto 0),
o_hash_1 => o_hash(63 downto 32),
o_hash_2 => o_hash(95 downto 64),
o_hash_3 => o_hash(127 downto 96)
);
end Structural;
|
----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: sg_pp_md_top - Structural
-- Description:
-- A top module for string_generator, pre_processing and md5 modules
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity sg_pp_md_top is
port (
clk : in std_logic;
rstn : in std_logic;
i_start_sg : in std_logic;
i_halt_sg : in std_logic;
i_start_md5 : in std_logic;
o_hash : out unsigned(127 downto 0);
o_done_md5 : out std_logic
);
end sg_pp_md_top;
architecture Structural of sg_pp_md_top is
component string_generator
port (
clk : in std_logic;
rstn : in std_logic; -- active low reset ofc
i_start : in std_logic;
i_halt : in std_logic;
o_done : out std_logic;
o_length : out std_logic_vector(2 downto 0); -- max 6 chars
o_string : out std_logic_vector(47 downto 0) -- 6 char string
);
end component;
component pre_process
Port ( i_data : in STD_LOGIC_VECTOR (47 downto 0);
i_length : in STD_LOGIC_VECTOR (2 downto 0);
o_data_0 : out unsigned (31 downto 0);
o_data_1 : out unsigned (31 downto 0);
o_length : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component MD5
port (
clk : in std_logic;
rstn : in std_logic;
i_start : in std_logic;
--i_data : in unsigned(71 downto 0); -- 8 chars + 1 appended bit
i_data_0 : in unsigned(31 downto 0); -- first 4 chars
i_data_1 : in unsigned(31 downto 0); -- next 4 chars
i_length : in std_logic_vector(7 downto 0); -- nbr of chars
o_done : out std_logic;
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end component;
signal s_len_sg_pp : std_logic_vector(2 downto 0); -- length sg->pp
signal s_len_pp_md5 : std_logic_vector(7 downto 0); -- length pp->md5
signal s_string_sg_pp : std_logic_vector(47 downto 0);
signal s_string1_pp_md5 : unsigned(31 downto 0);
signal s_string2_pp_md5 : unsigned(31 downto 0);
begin
sg_inst: string_generator
port map (
clk => clk,
rstn => rstn,
i_start => i_start_sg,
i_halt => i_halt_sg,
o_done => open,
o_length => s_len_sg_pp,
o_string => s_string_sg_pp
);
pp_inst: pre_process
port map(
i_data => s_string_sg_pp,
i_length => s_len_sg_pp,
o_data_0 => s_string1_pp_md5,
o_data_1 => s_string2_pp_md5,
o_length => s_len_pp_md5
);
MD5_inst: MD5
port map (
clk => clk,
rstn => rstn,
i_start => i_start_md5,
i_data_0 => s_string1_pp_md5,
i_data_1 => s_string2_pp_md5,
i_length => s_len_pp_md5,
o_done => o_done_md5,
o_hash_0 => o_hash(31 downto 0),
o_hash_1 => o_hash(63 downto 32),
o_hash_2 => o_hash(95 downto 64),
o_hash_3 => o_hash(127 downto 96)
);
end Structural;
|
--
-- Authors: Francisco Paiva Knebel
-- Gabriel Alexandre Zillmer
--
-- Universidade Federal do Rio Grande do Sul
-- Instituto de Informática
-- Sistemas Digitais
-- Prof. Fernanda Lima Kastensmidt
--
-- Create Date: 08:58:01 05/03/2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity regNZ is
port (
N_in : in STD_LOGIC;
Z_in : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
loadN : in STD_LOGIC;
loadZ : in STD_LOGIC;
N_out : out STD_LOGIC;
Z_out : out STD_LOGIC
);
end regNZ;
architecture Behavioral of regNZ is
signal data_N: STD_LOGIC;
signal data_Z: STD_LOGIC;
begin
process (clk, rst)
begin
if (rst = '1') then
data_N <= '0';
data_Z <= '0';
elsif (clk = '1' and clk'EVENT) then
if (loadN = '1') then
data_N <= N_in;
end if;
if (loadZ = '1') then
data_Z <= Z_in;
end if;
end if;
end process;
N_out <= data_N;
Z_out <= data_Z;
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity biaser is
generic(
EXP_BITS: natural := 6
);
port (
operation : in std_logic; --Indicates whether to add or remove the bias
exp_in: in std_logic_vector(EXP_BITS - 1 downto 0);
exp_out: out std_logic_vector(EXP_BITS - 1 downto 0)
);
end;
architecture biaser_arq of biaser is
begin
process(operation, exp_in)
variable bias_vector : std_logic_vector(EXP_BITS - 2 downto 0) := (others => '1');
variable bias : integer := to_integer(unsigned(bias_vector));
variable tmp_exp : integer := 0;
begin
tmp_exp := to_integer(unsigned(exp_in));
if operation = '0' then
exp_out <= std_logic_vector(to_signed(tmp_exp + bias, EXP_BITS));
else
exp_out <= std_logic_vector(to_signed(tmp_exp - bias, EXP_BITS));
end if;
end process;
end architecture;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package resolved is
type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
function resolved ( s : std_ulogic_vector ) return std_ulogic;
end package resolved;
package body resolved is
-- code from book
type stdlogic_table is array (std_ulogic, std_ulogic) of std_ulogic;
constant resolution_table : stdlogic_table :=
-- ---------------------------------------------
-- 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'
-- ---------------------------------------------
( ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- 'U'
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- 'X'
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- '0'
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- '1'
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- 'Z'
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- 'W'
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- 'L'
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- 'H'
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- '-'
);
function resolved ( s : std_ulogic_vector ) return std_ulogic is
variable result : std_ulogic := 'Z'; -- weakest state default
begin
if s'length = 1 then
return s(s'low);
else
for i in s'range loop
result := resolution_table(result, s(i));
end loop;
end if;
return result;
end function resolved;
-- end code from book
end package body resolved;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package resolved is
type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
function resolved ( s : std_ulogic_vector ) return std_ulogic;
end package resolved;
package body resolved is
-- code from book
type stdlogic_table is array (std_ulogic, std_ulogic) of std_ulogic;
constant resolution_table : stdlogic_table :=
-- ---------------------------------------------
-- 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'
-- ---------------------------------------------
( ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- 'U'
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- 'X'
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- '0'
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- '1'
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- 'Z'
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- 'W'
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- 'L'
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- 'H'
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- '-'
);
function resolved ( s : std_ulogic_vector ) return std_ulogic is
variable result : std_ulogic := 'Z'; -- weakest state default
begin
if s'length = 1 then
return s(s'low);
else
for i in s'range loop
result := resolution_table(result, s(i));
end loop;
end if;
return result;
end function resolved;
-- end code from book
end package body resolved;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package resolved is
type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
function resolved ( s : std_ulogic_vector ) return std_ulogic;
end package resolved;
package body resolved is
-- code from book
type stdlogic_table is array (std_ulogic, std_ulogic) of std_ulogic;
constant resolution_table : stdlogic_table :=
-- ---------------------------------------------
-- 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'
-- ---------------------------------------------
( ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- 'U'
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- 'X'
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- '0'
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- '1'
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- 'Z'
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- 'W'
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- 'L'
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- 'H'
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- '-'
);
function resolved ( s : std_ulogic_vector ) return std_ulogic is
variable result : std_ulogic := 'Z'; -- weakest state default
begin
if s'length = 1 then
return s(s'low);
else
for i in s'range loop
result := resolution_table(result, s(i));
end loop;
end if;
return result;
end function resolved;
-- end code from book
end package body resolved;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.xil.all;
library L_Example;
entity PauloBlaze_Atlys is
port (
Atlys_SystemClock_100MHz : in STD_LOGIC;
Atlys_GPIO_Button_Reset_n : in STD_LOGIC;
Atlys_GPIO_Switches : in STD_LOGIC_VECTOR(7 downto 0);
Atlys_GPIO_LED : out STD_LOGIC_VECTOR(7 downto 0);
Atlys_USB_UART_TX : out STD_LOGIC; -- USB-UART Bridge is "slave"
Atlys_USB_UART_RX : in STD_LOGIC; -- USB-UART Bridge is "slave"
Atlys_JA_SerialClock : inout STD_LOGIC;
Atlys_JA_SerialData : inout STD_LOGIC
);
end;
--
--
-- LED configuration
-- =============================================================================================================================================================
-- LED 7 LED 6 LED 5 LED 4 LED 3 LED 2 LED 1 LED 0
-- <unused> <unused> <unused> <unused> <unused> <unused> <unused> <unused>
architecture top of PauloBlaze_Atlys is
attribute KEEP : BOOLEAN;
attribute ASYNC_REG : STRING;
attribute SHREG_EXTRACT : STRING;
-- ==========================================================================================================================================================
-- configurations
-- ==========================================================================================================================================================
-- common configuration
constant DEBUG : BOOLEAN := TRUE;
constant ENABLE_CHIPSCOPE : BOOLEAN := (VENDOR = VENDOR_XILINX);
constant ENABLE_DEBUGPORT : BOOLEAN := TRUE;
constant SYS_CLOCK_FREQ : FREQ := 100 MHz;
-- ClockNetwork configuration
-- ===========================================================================
constant SYSTEM_CLOCK_FREQ : FREQ := SYS_CLOCK_FREQ;
-- ==========================================================================================================================================================
-- signal declarations
-- ==========================================================================================================================================================
-- clock and reset signals
signal System_RefClock_100MHz : STD_LOGIC;
signal ClkNet_Reset : STD_LOGIC;
signal ClkNet_ResetDone : STD_LOGIC;
signal SystemClock_200MHz : STD_LOGIC;
signal SystemClock_125MHz : STD_LOGIC;
signal SystemClock_100MHz : STD_LOGIC;
signal SystemClock_10MHz : STD_LOGIC;
signal SystemClock_Stable_200MHz : STD_LOGIC;
signal SystemClock_Stable_125MHz : STD_LOGIC;
signal SystemClock_Stable_100MHz : STD_LOGIC;
signal SystemClock_Stable_10MHz : STD_LOGIC;
signal Control_Clock : STD_LOGIC;
signal System_Clock : STD_LOGIC;
signal System_ClockStable : STD_LOGIC;
signal System_Reset : STD_LOGIC;
attribute KEEP of System_Clock : signal is TRUE;
attribute KEEP of System_Reset : signal is TRUE;
-- active-low board signals
signal Atlys_GPIO_Button_Reset : STD_LOGIC;
-- signal Atlys_EthernetPHY_Reset : STD_LOGIC;
-- signal Atlys_EthernetPHY_Interrupt : STD_LOGIC;
-- cross-over signals
signal Atlys_UART_TX : STD_LOGIC;
signal Atlys_UART_RX : STD_LOGIC;
-- debounced button signals (debounce circuit works @10 MHz)
signal GPIO_Button_Reset : STD_LOGIC;
-- synchronized button signals
signal Button_Reset : STD_LOGIC;
-- edge-detections on GPIO_Button_*
-- PerformanceTest signals
signal ex_ClkNet_Reset : STD_LOGIC;
signal ex_ClkNet_ResetDone : STD_LOGIC;
signal UART_TX : STD_LOGIC;
signal UART_RX : STD_LOGIC;
signal Raw_IIC_mux : STD_LOGIC;
signal Raw_IIC_Clock_i : STD_LOGIC;
signal Raw_IIC_Clock_t : STD_LOGIC;
signal Raw_IIC_Data_i : STD_LOGIC;
signal Raw_IIC_Data_t : STD_LOGIC;
signal Raw_IIC_Switch_Reset : STD_LOGIC;
signal IIC_SerialClock_i : STD_LOGIC;
signal IIC_SerialClock_o : STD_LOGIC;
signal IIC_SerialClock_t : STD_LOGIC;
signal IIC_SerialData_i : STD_LOGIC;
signal IIC_SerialData_o : STD_LOGIC;
signal IIC_SerialData_t : STD_LOGIC;
signal IIC_Switch_Reset : STD_LOGIC;
begin
-- ==========================================================================================================================================================
-- assert statements
-- ==========================================================================================================================================================
assert FALSE report "SoFPGA configuration:" severity NOTE;
assert FALSE report " SYS_CLOCK_FREQ: " & to_string(SYS_CLOCK_FREQ, 3) severity NOTE;
-- ==========================================================================================================================================================
-- Input/output buffers
-- ==========================================================================================================================================================
IBUFGDS_SystemClock : IBUFG
port map (
I => Atlys_SystemClock_100MHz,
O => System_RefClock_100MHz
);
-- ==========================================================================================================================================================
-- active-low to active-high conversion
-- ==========================================================================================================================================================
-- input signals
Atlys_GPIO_Button_Reset <= not Atlys_GPIO_Button_Reset_n;
-- Atlys_EthernetPHY_Interrupt <= NOT Atlys_EthernetPHY_Interrupt_n;
-- output signals
-- Atlys_EthernetPHY_Reset_n <= not Atlys_EthernetPHY_Reset;
-- ==========================================================================================================================================================
-- cross-over signal renaming
-- ==========================================================================================================================================================
-- USB-UART is the slave, FPGA is the master
Atlys_USB_UART_TX <= Atlys_UART_TX;
Atlys_UART_RX <= Atlys_USB_UART_RX;
-- ==========================================================================================================================================================
-- ClockNetwork
-- ==========================================================================================================================================================
ClkNet_Reset <= GPIO_Button_Reset;
Ex_ClkNet_Reset <= GPIO_Button_Reset;
ClkNet : entity L_Example.ClockNetwork_Atlys
generic map (
CLOCK_IN_FREQ => SYS_CLOCK_FREQ
)
port map (
ClockIn_100MHz => System_RefClock_100MHz,
ClockNetwork_Reset => ClkNet_Reset,
ClockNetwork_ResetDone => ClkNet_ResetDone,
Control_Clock_100MHz => Control_Clock,
Clock_200MHz => SystemClock_200MHz,
Clock_125MHz => SystemClock_125MHz,
Clock_100MHz => SystemClock_100MHz,
Clock_10MHz => SystemClock_10MHz,
Clock_Stable_200MHz => SystemClock_Stable_200MHz,
Clock_Stable_125MHz => SystemClock_Stable_125MHz,
Clock_Stable_100MHz => SystemClock_Stable_100MHz,
Clock_Stable_10MHz => SystemClock_Stable_10MHz
);
-- system signals
System_Clock <= SystemClock_100MHz;
System_ClockStable <= SystemClock_Stable_100MHz;
System_Reset <= not SystemClock_Stable_100MHz;
-- ==========================================================================================================================================================
-- signal debouncing
-- ==========================================================================================================================================================
DebBtn : entity PoC.io_Debounce
generic map (
CLOCK_FREQ => SYSTEM_CLOCK_FREQ,
BOUNCE_TIME => 5 ms,
BITS => 1,
ADD_INPUT_SYNCHRONIZERS => TRUE
)
port map (
Clock => Control_Clock,
Reset => '0',
Input(0) => Atlys_GPIO_Button_Reset,
Output(0) => GPIO_Button_Reset
);
-- synchronize to System_Clock
sync1 : entity PoC.sync_Bits_Xilinx
port map (
Clock => System_Clock, -- Clock to be synchronized to
Input(0) => GPIO_Button_Reset, -- Data to be synchronized
Output(0) => Button_Reset -- synchronised data
);
-- ==========================================================================================================================================================
-- main design
-- ==========================================================================================================================================================
-- Button inputs, some are also driven by Chipscope
-- Switch inputs
-- unused <= Atlys_GPIO_Switches(0);
-- unused <= Atlys_GPIO_Switches(1);
-- unused <= Atlys_GPIO_Switches(2);
-- unused <= Atlys_GPIO_Switches(3);
-- unused <= Atlys_GPIO_Switches(4);
-- unused <= Atlys_GPIO_Switches(5);
-- unused <= Atlys_GPIO_Switches(6);
-- unused <= Atlys_GPIO_Switches(7);
-- LED outputs
blkLED : block
signal GPIO_LED : T_SLV_8;
signal GPIO_LED_iob : T_SLV_8 := (others => '0');
begin
GPIO_LED(0) <= System_ClockStable; --ClkNet_ResetDone;
GPIO_LED(1) <= Ex_ClkNet_ResetDone;
GPIO_LED(2) <= '0';
GPIO_LED(3) <= '0';
GPIO_LED(4) <= '0';
GPIO_LED(5) <= '0';
GPIO_LED(6) <= '0';
GPIO_LED(7) <= '0';
GPIO_LED_iob <= GPIO_LED when rising_edge(System_Clock);
Atlys_GPIO_LED <= GPIO_LED_iob;
end block;
Ex : entity L_Example.ex_ExampleDesign
generic map (
DEBUG => DEBUG,
ENABLE_CHIPSCOPE => ENABLE_CHIPSCOPE,
ENABLE_DEBUGPORT => ENABLE_DEBUGPORT,
SYSTEM_CLOCK_FREQ => SYS_CLOCK_FREQ
)
port map (
ClockNetwork_Reset => Ex_ClkNet_Reset,
ClockNetwork_ResetDone => Ex_ClkNet_ResetDone,
System_Clock => System_Clock,
System_ClockStable => System_ClockStable,
System_Reset => System_Reset,
UART_TX => UART_TX,
UART_RX => UART_RX,
Raw_IIC_mux => Raw_IIC_mux,
Raw_IIC_Clock_i => Raw_IIC_Clock_i,
Raw_IIC_Clock_t => Raw_IIC_Clock_t,
Raw_IIC_Data_i => Raw_IIC_Data_i,
Raw_IIC_Data_t => Raw_IIC_Data_t--,
-- IIC_SerialClock_i => IIC_SerialClock_i,
-- IIC_SerialClock_o => IIC_SerialClock_o,
-- IIC_SerialClock_t => IIC_SerialClock_t,
-- IIC_SerialData_i => IIC_SerialData_i,
-- IIC_SerialData_o => IIC_SerialData_o,
-- IIC_SerialData_t => IIC_SerialData_t,
-- IICSwitch_Reset => IIC_Switch_Reset
);
-- ==========================================================================================================================================================
-- I2C Bus
-- ==========================================================================================================================================================
blkIOBUF_IIC : block
signal SerialClock_o : STD_LOGIC;
signal SerialClock_t : STD_LOGIC;
signal SerialData_o : STD_LOGIC;
signal SerialData_t : STD_LOGIC;
signal SerialClock_o_iob : STD_LOGIC := '0';
signal SerialClock_t_iob : STD_LOGIC := '1';
signal SerialData_o_iob : STD_LOGIC := '0';
signal SerialData_t_iob : STD_LOGIC := '1';
signal SerialClock_async : STD_LOGIC;
signal SerialClock_i_meta : STD_LOGIC := '1';
signal SerialClock_i_sync : STD_LOGIC := '1';
signal SerialData_async : STD_LOGIC;
signal SerialData_i_meta : STD_LOGIC := '1';
signal SerialData_i_sync : STD_LOGIC := '1';
-- Mark register DataSync_meta's input as asynchronous
attribute ASYNC_REG of SerialClock_i_meta : signal is "TRUE";
attribute ASYNC_REG of SerialData_i_meta : signal is "TRUE";
-- Prevent XST from translating two FFs into SRL plus FF
attribute SHREG_EXTRACT of SerialClock_i_meta : signal is "NO";
attribute SHREG_EXTRACT of SerialClock_i_sync : signal is "NO";
attribute SHREG_EXTRACT of SerialData_i_meta : signal is "NO";
attribute SHREG_EXTRACT of SerialData_i_sync : signal is "NO";
BEGIN
SerialClock_o <= mux(Raw_IIC_mux, IIC_SerialClock_o, '0');
SerialClock_t <= mux(Raw_IIC_mux, IIC_SerialClock_t, Raw_IIC_Clock_t);
SerialData_o <= mux(Raw_IIC_mux, IIC_SerialData_o, '0');
SerialData_t <= mux(Raw_IIC_mux, IIC_SerialData_t, Raw_IIC_Data_t);
SerialClock_o_iob <= SerialClock_o when rising_edge(System_Clock);
SerialClock_t_iob <= SerialClock_t when rising_edge(System_Clock);
SerialData_o_iob <= SerialData_o when rising_edge(System_Clock);
SerialData_t_iob <= SerialData_t when rising_edge(System_Clock);
SerialClock_i_meta <= SerialClock_async when rising_edge(System_Clock);
SerialClock_i_sync <= SerialClock_i_meta when rising_edge(System_Clock);
SerialData_i_meta <= SerialData_async when rising_edge(System_Clock);
SerialData_i_sync <= SerialData_i_meta when rising_edge(System_Clock);
IIC_SerialClock_i <= SerialClock_i_sync or Raw_IIC_mux;
Raw_IIC_Clock_i <= SerialClock_i_sync or not Raw_IIC_mux;
IIC_SerialData_i <= SerialData_i_sync or Raw_IIC_mux;
Raw_IIC_Data_i <= SerialData_i_sync or not Raw_IIC_mux;
IOBUF_IIC_SerialClock : IOBUF
port map (
T => SerialClock_t_iob, -- 3-state enable input, high=input, low=output
I => SerialClock_o_iob, -- buffer input
O => SerialClock_async, -- buffer output
IO => Atlys_JA_SerialClock -- buffer inout port (connect directly to top-level port)
);
IOBUF_IIC_SerialData : IOBUF
port map (
T => SerialData_t_iob, -- 3-state enable input, high=input, low=output
I => SerialData_o_iob, -- buffer input
O => SerialData_async, -- buffer output
IO => Atlys_JA_SerialData -- buffer inout port (connect directly to top-level port)
);
end block;
blkIOBUF_UART : block
signal blkUART_TX_iob : STD_LOGIC := '1';
signal blkUART_RX_async : STD_LOGIC;
signal blkUART_RX_meta : STD_LOGIC := '1';
signal blkUART_RX_sync : STD_LOGIC := '1';
-- Mark register DataSync_meta's input as asynchronous
attribute ASYNC_REG of blkUART_RX_meta : signal is "TRUE";
-- Prevent XST from translating two FFs into SRL plus FF
attribute SHREG_EXTRACT of blkUART_RX_meta : signal is "NO";
attribute SHREG_EXTRACT of blkUART_RX_sync : signal is "NO";
begin
blkUART_TX_iob <= UART_TX when rising_edge(System_Clock);
OBUF_UART_TX : OBUF
port map (
I => blkUART_TX_iob,
O => Atlys_UART_TX
);
IBUF_UART_RX : IBUF
port map (
I => Atlys_UART_RX,
O => blkUART_RX_async
);
blkUART_RX_meta <= blkUART_RX_async when rising_edge(System_Clock);
blkUART_RX_sync <= blkUART_RX_meta when rising_edge(System_Clock);
UART_RX <= blkUART_RX_sync;
end block;
end;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.ALL;
ENTITY fsm_challenge IS
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
xdone, ydone, ldone : IN STD_LOGIC;
sw : IN STD_LOGIC_VECTOR(17 downto 0);
draw : IN STD_LOGIC;
initx, inity, loady, loadx, plot, initl, drawl : OUT STD_LOGIC;
colour : OUT STD_LOGIC_VECTOR(2 downto 0);
x : OUT STD_LOGIC_VECTOR(7 downto 0);
y : OUT STD_LOGIC_VECTOR(6 downto 0);
ledg : OUT STD_LOGIC_VECTOR(7 downto 0);
initLoad : OUT STD_LOGIC
);
END fsm_challenge;
ARCHITECTURE behavioural OF fsm_challenge IS
TYPE state_types is (START, LOAD_Y, LOAD_X, LOAD_DONE, INIT_LINE, DRAW_LINE, DONE_LINE);
SIGNAL curr_state, next_state : state_types := START;
SIGNAL loadCount : integer := 0;
BEGIN
PROCESS(clock, resetb)
--VARIABLE next_state : state_types;
BEGIN
IF (resetb = '0') THEN
curr_state <= START;
loadCount <= 0;
ELSIF rising_edge(clock) THEN
curr_state <= next_state;
IF(next_state = DONE_LINE) THEN
loadCount <= 1;
END IF;
END IF;
END PROCESS;
PROCESS(curr_state, next_state)
BEGIN
CASE curr_state IS
WHEN START =>
INITX <= '1';
INITY <= '1';
LOADY <= '1';
LOADX <= '1';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
initLoad <= '1';
colour <= "000";
ledg <= "00000000";
next_state <= LOAD_X;
WHEN LOAD_Y =>
INITX <= '1';
INITY <= '0';
LOADY <= '1';
LOADX <= '1';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
IF(loadCount > 0) THEN
initLoad <= '0';
ELSE
initLoad <= '1';
END IF;
ledg <= "00000001";
next_state <= LOAD_X;
WHEN LOAD_X =>
INITX <= '0';
INITY <= '0';
LOADY <= '0';
LOADX <= '1';
INITL <= '0';
DRAWL <= '0';
PLOT <= '1';
IF(loadCount > 0) THEN
initLoad <= '0';
ELSE
initLoad <= '1';
END IF;
ledg <= "00000010";
IF (XDONE = '0') THEN
next_state <= LOAD_X;
ELSIF (XDONE = '1' AND YDONE = '0') THEN
next_state <= LOAD_Y;
ELSE
next_state <= LOAD_DONE;
END IF;
when LOAD_DONE =>
INITX <= '0';
INITY <= '0';
LOADY <= '0';
LOADX <= '0';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
ledg <= "00000100";
IF (draw = '0') THEN
x <= sw(17 downto 10);
y <= sw(9 downto 3);
--Clip input to within bounds
IF (unsigned(sw(17 downto 10)) > 159) THEN
x <= "10011111";
END IF;
IF (unsigned(sw(9 downto 3)) > 119) THEN
y <= "1110111";
END IF;
next_state <= INIT_LINE;
ELSE
next_state <= LOAD_DONE;
END IF;
WHEN INIT_LINE =>
IF(loadCount > 0) THEN
initLoad <= '0';
ELSE
initLoad <= '1';
END IF;
INITX <= '0';
INITY <= '0';
LOADY <= '0';
LOADX <= '0';
INITL <= '1';
DRAWL <= '0';
PLOT <= '0';
ledg <= "00001000";
colour <= sw(2 downto 0);
next_state <= DRAW_LINE;
WHEN DRAW_LINE =>
INITX <= '0';
INITY <= '0';
LOADY <= '0';
LOADX <= '0';
INITL <= '0';
DRAWL <= '1';
PLOT <= '1';
ledg <= "00010000";
IF (LDONE = '1') THEN
ledg <= "11111111";
next_state <= DONE_LINE;
ELSE
next_state <= DRAW_LINE;
END IF;
WHEN DONE_LINE =>
ledg <= "00100000";
INITX <= '0';
INITY <= '0';
LOADY <= '0';
LOADX <= '0';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
next_state <= LOAD_DONE;
WHEN others =>
ledg <= "01000000";
INITX <= '0';
INITY <= '0';
LOADY <= '0';
LOADX <= '0';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
next_state <= DONE_LINE;
END CASE;
END PROCESS;
END behavioural;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: tx_Mem_Reader - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
--
-- Revision 1.00 - first release. 20.03.2008
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
entity tx_Mem_Reader is
port (
-- DDR Read Interface
DDR_rdc_sof : out std_logic;
DDR_rdc_eof : out std_logic;
DDR_rdc_v : out std_logic;
DDR_rdc_Shift : out std_logic;
DDR_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : in std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : out std_logic;
DDR_FIFO_Empty : in std_logic;
DDR_FIFO_RdQout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Wishbone Read interface
wb_rdc_sof : out std_logic;
wb_rdc_v : out std_logic;
wb_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_full : in std_logic;
-- Wisbbone Buffer read port
wb_FIFO_re : out std_logic;
wb_FIFO_empty : in std_logic;
wb_FIFO_qout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Register Read interface
Regs_RdAddr : out std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_RdQout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Read Command interface
RdNumber : in std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
RdNumber_eq_One : in std_logic;
RdNumber_eq_Two : in std_logic;
StartAddr : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Shift_1st_QWord : in std_logic;
is_CplD : in std_logic;
BAR_value : in std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
RdCmd_Req : in std_logic;
RdCmd_Ack : out std_logic;
-- Output port of the memory buffer
mbuf_Din : out std_logic_vector(C_DBUS_WIDTH*9/8-1 downto 0);
mbuf_WE : out std_logic;
mbuf_Full : in std_logic;
mbuf_aFull : in std_logic;
-- Common ports
Tx_TimeOut : out std_logic;
Tx_wb_TimeOut : out std_logic;
mReader_Rst_n : in std_logic;
user_clk : in std_logic
);
end tx_Mem_Reader;
architecture Behavioral of tx_Mem_Reader is
type mReaderStates is (St_mR_Idle, -- Memory reader Idle
St_mR_CmdLatch, -- Capture the read command
St_mR_Transfer, -- Acknowlege the command request
St_mR_wb_A, -- Wishbone access state A
St_mR_DDR_A, -- DDR access state A
St_mR_DDR_C, -- DDR access state C
St_mR_Last -- Last word is reached
);
-- State variables
signal TxMReader_State : mReaderStates;
-- DDR Read Interface
signal DDR_rdc_sof_i : std_logic;
signal DDR_rdc_eof_i : std_logic;
signal DDR_rdc_v_i : std_logic;
signal DDR_rdc_Shift_i : std_logic;
signal DDR_rdc_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Register read address
signal Regs_RdAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_RdEn : std_logic;
signal Regs_Hit : std_logic;
signal Regs_Write_mbuf_r1 : std_logic;
signal Regs_Write_mbuf_r2 : std_logic;
signal Regs_Write_mbuf_r3 : std_logic;
-- DDR FIFO read enable
signal DDR_FIFO_RdEn_i : std_logic;
signal DDR_FIFO_RdEn_Mask : std_logic;
signal DDR_FIFO_Hit : std_logic;
signal DDR_FIFO_Write_mbuf_r1 : std_logic;
signal DDR_FIFO_Write_mbuf_r2 : std_logic;
signal DDR_FIFO_Write_mbuf_r3 : std_logic;
signal DDR_FIFO_RdQout_swap : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Wishbone interface
signal wb_rdc_sof_i : std_logic;
signal wb_rdc_v_i : std_logic;
signal wb_rdc_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wb_rdc_full_i : std_logic;
signal wb_FIFO_Hit : std_logic;
signal wb_FIFO_Write_mbuf : std_logic;
signal wb_FIFO_Write_mbuf_r1 : std_logic;
signal wb_FIFO_Write_mbuf_r2 : std_logic;
signal wb_FIFO_re_i : std_logic;
signal wb_FIFO_RdEn_Mask_rise : std_logic;
signal wb_FIFO_RdEn_Mask_rise_r1 : std_logic;
signal wb_FIFO_RdEn_Mask_rise_r2 : std_logic;
signal wb_FIFO_RdEn_Mask_rise_r3 : std_logic;
signal wb_FIFO_RdEn_Mask : std_logic;
signal wb_FIFO_RdEn_Mask_r1 : std_logic;
signal wb_FIFO_RdEn_Mask_r2 : std_logic;
signal wb_FIFO_Rd_1Dw : std_logic;
signal wb_FIFO_qout_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wb_FIFO_qout_shift : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wb_FIFO_qout_swapped : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Memory data outputs
signal wb_FIFO_Dout_wire : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_Dout_wire : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Regs_RdQout_wire : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal mbuf_Din_wire_OR : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Output port of the memory buffer
signal mbuf_Din_i : std_logic_vector(C_DBUS_WIDTH*9/8-1 downto 0);
signal mbuf_WE_i : std_logic;
signal mbuf_Full_i : std_logic;
signal mbuf_aFull_i : std_logic;
signal mbuf_aFull_r1 : std_logic;
-- Read command request and acknowledge
signal RdCmd_Req_i : std_logic;
signal RdCmd_Ack_i : std_logic;
signal Shift_1st_QWord_k : std_logic;
signal is_CplD_k : std_logic;
signal may_be_MWr_k : std_logic;
signal TRem_n_last_QWord : std_logic;
signal regs_Rd_Counter : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
signal regs_Rd_Cntr_eq_One : std_logic;
signal regs_Rd_Cntr_eq_Two : std_logic;
signal DDR_Rd_Counter : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
signal DDR_Rd_Cntr_eq_One : std_logic;
signal wb_FIFO_Rd_Counter : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
signal wb_FIFO_Rd_Cntr_eq_Two : std_logic;
signal Address_var : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Address_step : std_logic_vector(4-1 downto 0);
signal TxTLP_eof_n : std_logic;
signal TxTLP_eof_n_r1 : std_logic;
-- signal TxTLP_eof_n_r2 : std_logic;
signal TimeOut_Counter : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal TO_Cnt_Rst : std_logic;
signal Tx_TimeOut_i : std_logic;
signal Tx_wb_TimeOut_i : std_logic := '0';
begin
-- read command REQ + ACK
RdCmd_Req_i <= RdCmd_Req;
RdCmd_Ack <= RdCmd_Ack_i;
-- Time out signal out
Tx_TimeOut <= Tx_TimeOut_i;
Tx_wb_TimeOut <= Tx_wb_TimeOut_i;
------------------------------------------------------------
--- Memory read control
------------------------------------------------------------
-- Wishbone Buffer read
wb_FIFO_re <= wb_FIFO_re_i;
wb_rdc_sof <= wb_rdc_sof_i;
wb_rdc_v <= wb_rdc_v_i;
wb_rdc_din <= wb_rdc_din_i;
wb_rdc_full_i <= wb_rdc_full;
-- DDR FIFO Read
DDR_rdc_sof <= DDR_rdc_sof_i;
DDR_rdc_eof <= DDR_rdc_eof_i;
DDR_rdc_v <= DDR_rdc_v_i;
DDR_rdc_Shift <= DDR_rdc_Shift_i;
DDR_rdc_din <= DDR_rdc_din_i;
DDR_FIFO_RdQout_swap <= (DDR_FIFO_RdQout(C_DBUS_WIDTH/2-1 downto 0) &
DDR_FIFO_RdQout(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2));
DDR_FIFO_RdEn <= DDR_FIFO_RdEn_i;
-- Register address for read
Regs_RdAddr <= Regs_RdAddr_i;
-- Memory buffer write port
--ported from TRN to AXI, swap DWORDs
mbuf_Din <= mbuf_Din_i(C_DBUS_WIDTH*9/8-1 downto C_DBUS_WIDTH)
& mbuf_Din_i(31 downto 0)
& mbuf_Din_i(63 downto 32);
mbuf_WE <= mbuf_WE_i;
mbuf_Full_i <= mbuf_Full;
mbuf_aFull_i <= mbuf_aFull;
--
Regs_RdAddr_i <= Address_var(C_EP_AWIDTH-1 downto 0);
-----------------------------------------------------
-- Synchronous Delay: mbuf_aFull
--
Synchron_Delay_mbuf_aFull :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
mbuf_aFull_r1 <= mbuf_aFull_i or mbuf_Full_i;
end if;
end process;
-- ---------------------------------------------------
-- State Machine: Tx Memory read control
--
mR_FSM_Control :
process (user_clk, mReader_Rst_n)
begin
if mReader_Rst_n = '0' then
DDR_rdc_sof_i <= '0';
DDR_rdc_eof_i <= '0';
DDR_rdc_v_i <= '0';
DDR_rdc_Shift_i <= '0';
DDR_rdc_din_i <= (others => '0');
wb_rdc_sof_i <= '0';
wb_rdc_v_i <= '0';
wb_rdc_din_i <= (others => '0');
wb_FIFO_Hit <= '0';
wb_FIFO_re_i <= '0';
wb_FIFO_RdEn_Mask <= '0';
DDR_FIFO_Hit <= '0';
DDR_FIFO_RdEn_i <= '0';
DDR_FIFO_RdEn_Mask <= '0';
Regs_Hit <= '0';
Regs_RdEn <= '0';
regs_Rd_Counter <= (others => '0');
DDR_Rd_Counter <= (others => '0');
DDR_Rd_Cntr_eq_One <= '0';
wb_FIFO_Rd_Counter <= (others => '0');
wb_FIFO_Rd_Cntr_eq_Two <= '0';
regs_Rd_Cntr_eq_One <= '0';
regs_Rd_Cntr_eq_Two <= '0';
Shift_1st_QWord_k <= '0';
is_CplD_k <= '0';
may_be_MWr_k <= '0';
TRem_n_last_QWord <= '0';
Address_var <= (others => '1');
TxTLP_eof_n <= '1';
TO_Cnt_Rst <= '1';
RdCmd_Ack_i <= '0';
TxMReader_State <= St_mR_Idle;
elsif user_clk'event and user_clk = '1' then
case TxMReader_State is
when St_mR_Idle =>
if RdCmd_Req_i = '0' then
TxMReader_State <= St_mR_Idle;
wb_FIFO_Hit <= '0';
Regs_Hit <= '0';
Regs_RdEn <= '0';
TxTLP_eof_n <= '1';
Address_var <= (others => '1');
RdCmd_Ack_i <= '0';
is_CplD_k <= '0';
may_be_MWr_k <= '0';
else
RdCmd_Ack_i <= '1';
Shift_1st_QWord_k <= Shift_1st_QWord;
TRem_n_last_QWord <= Shift_1st_QWord xor RdNumber(0);
is_CplD_k <= is_CplD;
may_be_MWr_k <= not is_CplD;
TxTLP_eof_n <= '1';
if BAR_value(C_ENCODE_BAR_NUMBER-1 downto 0)
= CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER)
then
wb_FIFO_Hit <= '0';
DDR_FIFO_Hit <= '1';
Regs_Hit <= '0';
Regs_RdEn <= '0';
Address_var <= Address_var;
TxMReader_State <= St_mR_DDR_A;
elsif BAR_value(C_ENCODE_BAR_NUMBER-1 downto 0)
= CONV_STD_LOGIC_VECTOR(CINT_REGS_SPACE_BAR, C_ENCODE_BAR_NUMBER)
then
wb_FIFO_Hit <= '0';
DDR_FIFO_Hit <= '0';
Regs_Hit <= '1';
Regs_RdEn <= '1';
if Shift_1st_QWord = '1' then
Address_var(C_EP_AWIDTH-1 downto 0) <= StartAddr(C_EP_AWIDTH-1 downto 0) - "100";
else
Address_var(C_EP_AWIDTH-1 downto 0) <= StartAddr(C_EP_AWIDTH-1 downto 0);
end if;
TxMReader_State <= St_mR_CmdLatch;
elsif BAR_value(C_ENCODE_BAR_NUMBER-1 downto 0)
= CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER)
then
wb_FIFO_Hit <= '1';
DDR_FIFO_Hit <= '0';
Regs_Hit <= '0';
Regs_RdEn <= '0';
Address_var <= Address_var;
TxMReader_State <= St_mR_wb_A;
else
wb_FIFO_Hit <= '0';
DDR_FIFO_Hit <= '0';
Regs_Hit <= '0';
Regs_RdEn <= '0';
Address_var <= Address_var;
TxMReader_State <= St_mR_CmdLatch;
end if;
end if;
when St_mR_DDR_A =>
DDR_rdc_sof_i <= '1';
DDR_rdc_eof_i <= '0';
DDR_rdc_v_i <= '1';
DDR_rdc_Shift_i <= Shift_1st_QWord_k;
DDR_rdc_din_i <= C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_TLP_FLD_WIDTH_OF_LENG+2+32)
& RdNumber & "00"
& StartAddr(C_DBUS_WIDTH-1-32 downto 0);
Regs_RdEn <= '0';
DDR_FIFO_RdEn_i <= '0';
TxTLP_eof_n <= '1';
RdCmd_Ack_i <= '1';
TxMReader_State <= St_mR_DDR_C; -- St_mR_DDR_B;
when St_mR_wb_A =>
wb_rdc_sof_i <= '1';
wb_rdc_v_i <= '1';
wb_rdc_din_i <= C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_TLP_FLD_WIDTH_OF_LENG+2+32)
& RdNumber & "00"
& StartAddr(C_DBUS_WIDTH-1-32 downto 0);
Regs_RdEn <= '0';
wb_FIFO_re_i <= '0';
TxTLP_eof_n <= '1';
RdCmd_Ack_i <= '1';
if wb_rdc_full_i = '0' then
TxMReader_State <= St_mR_DDR_C;
else
TxMReader_State <= St_mR_wb_A;
end if;
when St_mR_DDR_C =>
DDR_rdc_sof_i <= '0';
DDR_rdc_eof_i <= '0';
DDR_rdc_v_i <= '0';
DDR_rdc_din_i <= DDR_rdc_din_i;
wb_rdc_sof_i <= '0';
wb_rdc_v_i <= '0';
wb_rdc_din_i <= wb_rdc_din_i;
RdCmd_Ack_i <= '0';
TxTLP_eof_n <= '1';
if DDR_FIFO_Hit = '1' and DDR_FIFO_Empty = '1' and Tx_TimeOut_i = '0' then
TxMReader_State <= St_mR_DDR_C;
elsif wb_FIFO_Hit = '1' and wb_FIFO_empty = '1' and Tx_wb_TimeOut_i = '0' then
TxMReader_State <= St_mR_DDR_C;
else
TxMReader_State <= St_mR_CmdLatch;
end if;
when St_mR_CmdLatch =>
RdCmd_Ack_i <= '0';
if regs_Rd_Cntr_eq_One = '1' then
Regs_RdEn <= '0';
Address_var <= Address_var;
TxTLP_eof_n <= '0';
TxMReader_State <= St_mR_Last;
elsif regs_Rd_Cntr_eq_Two = '1' then
if Shift_1st_QWord_k = '1' then
TxMReader_State <= St_mR_Transfer;
Regs_RdEn <= Regs_RdEn; -- '1';
TxTLP_eof_n <= '1';
Address_var(C_EP_AWIDTH-1 downto 0) <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
else
TxMReader_State <= St_mR_Last;
Regs_RdEn <= '0';
TxTLP_eof_n <= '0';
Address_var(C_EP_AWIDTH-1 downto 0) <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
end if;
else
Regs_RdEn <= Regs_RdEn;
Address_var(C_EP_AWIDTH-1 downto 0) <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
TxTLP_eof_n <= '1';
TxMReader_State <= St_mR_Transfer;
end if;
when St_mR_Transfer =>
RdCmd_Ack_i <= '0';
if DDR_FIFO_Hit = '1' and DDR_FIFO_RdEn_Mask = '1' then
Address_var <= Address_var;
Regs_RdEn <= '0';
TxTLP_eof_n <= '0';
TxMReader_State <= St_mR_Last;
elsif wb_FIFO_Hit = '1' and wb_FIFO_RdEn_Mask = '1' then
Address_var <= Address_var;
Regs_RdEn <= '0';
TxTLP_eof_n <= '0';
TxMReader_State <= St_mR_Last;
elsif wb_FIFO_Hit = '0' and regs_Rd_Cntr_eq_One = '1' then
Address_var <= Address_var;
Regs_RdEn <= '0';
TxTLP_eof_n <= '0';
TxMReader_State <= St_mR_Last;
elsif wb_FIFO_Hit = '0' and regs_Rd_Cntr_eq_Two = '1' then
Address_var <= Address_var;
Regs_RdEn <= '0';
TxTLP_eof_n <= '0';
TxMReader_State <= St_mR_Last;
elsif mbuf_aFull_r1 = '1' then
Address_var <= Address_var;
Regs_RdEn <= '0';
TxTLP_eof_n <= TxTLP_eof_n;
TxMReader_State <= St_mR_Transfer;
else
Address_var(C_EP_AWIDTH-1 downto 0) <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
Regs_RdEn <= Regs_Hit;
TxTLP_eof_n <= TxTLP_eof_n;
TxMReader_State <= St_mR_Transfer;
end if;
when St_mR_Last =>
Regs_RdEn <= '0';
DDR_FIFO_RdEn_i <= '0';
TxTLP_eof_n <= (not DDR_FIFO_Hit) and (not wb_FIFO_Hit);
RdCmd_Ack_i <= '0';
TxMReader_State <= St_mR_Idle;
when others =>
Address_var <= Address_var;
wb_FIFO_Hit <= '0';
Regs_RdEn <= '0';
DDR_FIFO_RdEn_i <= '0';
TxTLP_eof_n <= '1';
RdCmd_Ack_i <= '0';
TxMReader_State <= St_mR_Idle;
end case;
case TxMReader_State is
when St_mR_Idle =>
TO_Cnt_Rst <= '1';
when others =>
TO_Cnt_Rst <= '0';
end case;
case TxMReader_State is
when St_mR_Idle =>
DDR_FIFO_RdEn_i <= '0';
DDR_FIFO_RdEn_Mask <= '0';
when others =>
if DDR_Rd_Cntr_eq_One = '1'
and (DDR_FIFO_Empty = '0' or Tx_TimeOut_i = '1')
and DDR_FIFO_RdEn_i = '1'
then
DDR_FIFO_RdEn_Mask <= '1';
DDR_FIFO_RdEn_i <= '0';
else
DDR_FIFO_RdEn_Mask <= DDR_FIFO_RdEn_Mask;
DDR_FIFO_RdEn_i <= DDR_FIFO_Hit
and not mbuf_aFull_r1
and not DDR_FIFO_RdEn_Mask;
end if;
end case;
case TxMReader_State is
when St_mR_Idle =>
wb_FIFO_re_i <= '0';
wb_FIFO_RdEn_Mask <= '0';
when others =>
if wb_FIFO_Rd_Cntr_eq_Two = '1'
and (wb_FIFO_empty = '0' or Tx_wb_TimeOut_i = '1')
and wb_FIFO_re_i = '1'
then
wb_FIFO_RdEn_Mask <= '1';
wb_FIFO_re_i <= '0';
else
wb_FIFO_RdEn_Mask <= wb_FIFO_RdEn_Mask;
wb_FIFO_re_i <= wb_FIFO_Hit
and not mbuf_aFull_r1
and not wb_FIFO_RdEn_Mask;
end if;
end case;
case TxMReader_State is
when St_mR_Idle =>
if RdCmd_Req_i = '1' and
BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
/= CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
then
regs_Rd_Counter <= RdNumber;
regs_Rd_Cntr_eq_One <= RdNumber_eq_One;
regs_Rd_Cntr_eq_Two <= RdNumber_eq_Two;
else
regs_Rd_Counter <= (others => '0');
regs_Rd_Cntr_eq_One <= '0';
regs_Rd_Cntr_eq_Two <= '0';
end if;
when St_mR_CmdLatch =>
if DDR_FIFO_Hit = '0' then
if Shift_1st_QWord_k = '1' then
regs_Rd_Counter <= regs_Rd_Counter - '1';
if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_One <= '1';
else
regs_Rd_Cntr_eq_One <= '0';
end if;
if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(3, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_Two <= '1';
else
regs_Rd_Cntr_eq_Two <= '0';
end if;
else
regs_Rd_Counter <= regs_Rd_Counter - "10"; -- '1';
if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(3, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_One <= '1';
else
regs_Rd_Cntr_eq_One <= '0';
end if;
if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_Two <= '1';
else
regs_Rd_Cntr_eq_Two <= '0';
end if;
end if;
else
regs_Rd_Counter <= regs_Rd_Counter;
regs_Rd_Cntr_eq_One <= regs_Rd_Cntr_eq_One;
regs_Rd_Cntr_eq_Two <= regs_Rd_Cntr_eq_Two;
end if;
when St_mR_Transfer =>
if DDR_FIFO_Hit = '0'
and mbuf_aFull_r1 = '0'
then
regs_Rd_Counter <= regs_Rd_Counter - "10"; -- '1';
if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_One <= '1';
elsif regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_One <= '1';
elsif regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(3, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_One <= '1';
else
regs_Rd_Cntr_eq_One <= '0';
end if;
if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_Two <= '1';
else
regs_Rd_Cntr_eq_Two <= '0';
end if;
else
regs_Rd_Counter <= regs_Rd_Counter;
regs_Rd_Cntr_eq_One <= regs_Rd_Cntr_eq_One;
regs_Rd_Cntr_eq_Two <= regs_Rd_Cntr_eq_Two;
end if;
when others =>
regs_Rd_Counter <= regs_Rd_Counter;
regs_Rd_Cntr_eq_One <= regs_Rd_Cntr_eq_One;
regs_Rd_Cntr_eq_Two <= regs_Rd_Cntr_eq_Two;
end case;
case TxMReader_State is
when St_mR_Idle =>
if RdCmd_Req_i = '1' and
BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
= CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
then
if RdNumber(0) = '1' then
DDR_Rd_Counter <= RdNumber + '1';
DDR_Rd_Cntr_eq_One <= RdNumber_eq_One;
elsif Shift_1st_QWord = '1' then
DDR_Rd_Counter <= RdNumber + "10";
DDR_Rd_Cntr_eq_One <= RdNumber_eq_One;
else
DDR_Rd_Counter <= RdNumber;
DDR_Rd_Cntr_eq_One <= RdNumber_eq_One or RdNumber_eq_Two;
end if;
else
DDR_Rd_Counter <= (others => '0');
DDR_Rd_Cntr_eq_One <= '0';
end if;
when others =>
if ((DDR_FIFO_Empty = '0' or Tx_TimeOut_i = '1') and DDR_FIFO_RdEn_i = '1')
then
DDR_Rd_Counter <= DDR_Rd_Counter - "10"; -- '1';
if DDR_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
DDR_Rd_Cntr_eq_One <= '1';
else
DDR_Rd_Cntr_eq_One <= '0';
end if;
else
DDR_Rd_Counter <= DDR_Rd_Counter;
DDR_Rd_Cntr_eq_One <= DDR_Rd_Cntr_eq_One;
end if;
end case;
case TxMReader_State is
when St_mR_Idle =>
if RdCmd_Req_i = '1' and
BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
= CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
then
if RdNumber_eq_One = '1' then
wb_FIFO_Rd_Counter <= RdNumber + '1';
wb_FIFO_Rd_Cntr_eq_Two <= '1';
wb_FIFO_Rd_1Dw <= '1';
else
wb_FIFO_Rd_Counter <= RdNumber;
wb_FIFO_Rd_Cntr_eq_Two <= RdNumber_eq_Two; -- or RdNumber_eq_One;
wb_FIFO_Rd_1Dw <= '0';
end if;
else
wb_FIFO_Rd_Counter <= (others => '0');
wb_FIFO_Rd_Cntr_eq_Two <= '0';
wb_FIFO_Rd_1Dw <= '0';
end if;
when others =>
wb_FIFO_Rd_1Dw <= wb_FIFO_Rd_1Dw;
if (wb_FIFO_empty = '0' or Tx_wb_TimeOut_i = '1') and wb_FIFO_re_i = '1'
then
wb_FIFO_Rd_Counter <= wb_FIFO_Rd_Counter - "10"; -- '1';
if wb_FIFO_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
wb_FIFO_Rd_Cntr_eq_Two <= '1';
else
wb_FIFO_Rd_Cntr_eq_Two <= '0';
end if;
else
wb_FIFO_Rd_Counter <= wb_FIFO_Rd_Counter;
wb_FIFO_Rd_Cntr_eq_Two <= wb_FIFO_Rd_Cntr_eq_Two;
end if;
end case;
end if;
end process;
-----------------------------------------------------
-- Synchronous Delay: mbuf_writes
--
Synchron_Delay_mbuf_writes :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
Regs_Write_mbuf_r1 <= Regs_RdEn;
Regs_Write_mbuf_r2 <= Regs_Write_mbuf_r1;
Regs_Write_mbuf_r3 <= Regs_Write_mbuf_r2;
DDR_FIFO_Write_mbuf_r1 <= DDR_FIFO_RdEn_i and (not DDR_FIFO_Empty or Tx_TimeOut_i);
DDR_FIFO_Write_mbuf_r2 <= DDR_FIFO_Write_mbuf_r1;
DDR_FIFO_Write_mbuf_r3 <= DDR_FIFO_Write_mbuf_r2;
wb_FIFO_Write_mbuf <= wb_FIFO_re_i and (not wb_FIFO_empty or Tx_wb_TimeOut_i);
wb_FIFO_Write_mbuf_r1 <= wb_FIFO_Write_mbuf;
wb_FIFO_Write_mbuf_r2 <= wb_FIFO_Write_mbuf_r1;
wb_FIFO_RdEn_Mask_r1 <= wb_FIFO_RdEn_Mask;
wb_FIFO_RdEn_Mask_r2 <= wb_FIFO_RdEn_Mask_r1;
end if;
end process;
--------------------------------------------------------------------------
-- Wires to be OR'ed to build mbuf_Din
--------------------------------------------------------------------------
wb_FIFO_Dout_wire <= wb_FIFO_qout_r1 when (wb_FIFO_Hit = '1' and Shift_1st_QWord_k = '0')
else wb_FIFO_qout_shift when (wb_FIFO_Hit = '1' and Shift_1st_QWord_k = '1')
else (others => '0');
DDR_Dout_wire <= DDR_FIFO_RdQout_swap when DDR_FIFO_Hit = '1' else (others => '0');
Regs_RdQout_wire <= Regs_RdQout --watch out!
when Regs_Hit = '1' else (others => '0');
mbuf_Din_wire_OR <= wb_FIFO_Dout_wire or DDR_Dout_wire or Regs_RdQout_wire;
-----------------------------------------------------
-- Synchronous Delay: mbuf_WE
--
Synchron_Delay_mbuf_WE :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
mbuf_WE_i <= DDR_FIFO_Write_mbuf_r1
or Regs_Write_mbuf_r2
or (wb_FIFO_Write_mbuf_r1 or (Shift_1st_QWord_k and wb_FIFO_RdEn_Mask_rise_r1));
end if;
end process;
-----------------------------------------------------
-- Synchronous Delay: TxTLP_eof_n
--
Synchron_Delay_TxTLP_eof_n :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
TxTLP_eof_n_r1 <= TxTLP_eof_n;
-- TxTLP_eof_n_r2 <= TxTLP_eof_n_r1;
end if;
end process;
wb_FIFO_qout_swapped <= wb_FIFO_qout(C_DBUS_WIDTH/2-1 downto 0) & wb_FIFO_qout(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2);
-----------------------------------------------------
-- Synchronous Delay: wb_FIFO_qout
--
Synchron_Delay_wb_FIFO_qout :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
wb_FIFO_RdEn_Mask_rise <= wb_FIFO_RdEn_Mask and not wb_FIFO_RdEn_Mask_r1;
wb_FIFO_RdEn_Mask_rise_r1 <= wb_FIFO_RdEn_Mask_rise;
wb_FIFO_RdEn_Mask_rise_r2 <= wb_FIFO_RdEn_Mask_rise_r1;
wb_FIFO_qout_r1 <= wb_FIFO_qout_swapped;
wb_FIFO_qout_shift <= wb_FIFO_qout_r1(C_DBUS_WIDTH/2-1 downto 0)
& wb_FIFO_qout_swapped(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2);
end if;
end process;
-----------------------------------------------------
-- Synchronous Delay: mbuf_Din
--
Synchron_Delay_mbuf_Din :
process (user_clk, mReader_Rst_n)
begin
if mReader_Rst_n = '0' then
mbuf_Din_i <= (C_DBUS_WIDTH => '1', others => '0');
elsif user_clk'event and user_clk = '1' then
if Tx_TimeOut_i = '1' and DDR_FIFO_Hit = '1' then
mbuf_Din_i(C_DBUS_WIDTH-1 downto 0) <= (others => '1');
elsif Tx_wb_TimeOut_i = '1' and wb_FIFO_Hit = '1' and is_CplD_k = '1' then
mbuf_Din_i(C_DBUS_WIDTH-1 downto 0) <= (others => '1');
elsif Tx_wb_TimeOut_i = '1' and wb_FIFO_Hit = '1' and may_be_MWr_k = '1' then
mbuf_Din_i(C_DBUS_WIDTH-1 downto 0) <= (others => '1');
else
mbuf_Din_i(C_DBUS_WIDTH-1 downto 0) <= Endian_Invert_64(mbuf_Din_wire_OR);
end if;
if DDR_FIFO_Hit = '1' then
mbuf_Din_i(C_DBUS_WIDTH) <= not DDR_FIFO_RdEn_Mask;
mbuf_Din_i(70) <= TRem_n_last_QWord;
elsif wb_FIFO_Hit = '1' then
if Shift_1st_QWord_k = '1' and wb_FIFO_Rd_1Dw = '0' then
mbuf_Din_i(C_DBUS_WIDTH) <= not wb_FIFO_RdEn_Mask_r2;
else
mbuf_Din_i(C_DBUS_WIDTH) <= not wb_FIFO_RdEn_Mask_r1;
end if;
mbuf_Din_i(70) <= TRem_n_last_QWord;
else
mbuf_Din_i(C_DBUS_WIDTH) <= TxTLP_eof_n_r1;
mbuf_Din_i(70) <= TRem_n_last_QWord;
end if;
end if;
end process;
-----------------------------------------------------
-- Synchronous: Time-out counter
--
Synchron_TimeOut_Counter :
process (user_clk, TO_Cnt_Rst)
begin
if TO_Cnt_Rst = '1' then
TimeOut_Counter <= (others => '0');
elsif user_clk'event and user_clk = '1' then
TimeOut_Counter(21 downto 0) <= TimeOut_Counter(21 downto 0) + '1';
end if;
end process;
-----------------------------------------------------
-- Synchronous: Tx_TimeOut
--
SynchOUT_Tx_TimeOut :
process (user_clk, mReader_Rst_n)
begin
if mReader_Rst_n = '0' then
Tx_TimeOut_i <= '0';
elsif user_clk'event and user_clk = '1' then
if TimeOut_Counter(21 downto 6) = X"FFFF" and DDR_FIFO_Hit = '1' then
Tx_TimeOut_i <= '1';
else
Tx_TimeOut_i <= Tx_TimeOut_i;
end if;
end if;
end process;
-----------------------------------------------------
-- Synchronous: Tx_wb_TimeOut
--
SynchOUT_Tx_wb_TimeOut :
process (user_clk, mReader_Rst_n)
begin
if mReader_Rst_n = '0' then
Tx_wb_TimeOut_i <= '0';
elsif user_clk'event and user_clk = '1' then
if TimeOut_Counter(21 downto 6) = X"FFFF" and wb_FIFO_Hit = '1' then
Tx_wb_TimeOut_i <= '1';
else
Tx_wb_TimeOut_i <= Tx_wb_TimeOut_i;
end if;
end if;
end process;
end architecture Behavioral;
|
-------------------------------------------------------------------------------
-- ua_narrow.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: ua_narrow.vhd
--
-- Description: Creates a narrow burst count load value when an operation
-- is an unaligned narrow WRAP or INCR burst type. Used by
-- I_NARROW_CNT module.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/4/2011 v1.03a
-- ~~~~~~
-- Edit for scalability and support of 512 and 1024-bit data widths.
-- ^^^^^^
-- JLJ 2/8/2011 v1.03a
-- ~~~~~~
-- Update bit vector usage of address LSB for calculating ua_narrow_load.
-- Add axi_bram_ctrl_funcs package inclusion.
-- ^^^^^^
-- JLJ 3/1/2011 v1.03a
-- ~~~~~~
-- Fix XST handling for DIV functions. Create seperate process when
-- divisor is not constant and a power of two.
-- ^^^^^^
-- JLJ 3/2/2011 v1.03a
-- ~~~~~~
-- Update range of integer signals.
-- ^^^^^^
-- JLJ 3/4/2011 v1.03a
-- ~~~~~~
-- Remove use of local function, Create_Size_Max.
-- ^^^^^^
-- JLJ 3/11/2011 v1.03a
-- ~~~~~~
-- Remove C_AXI_DATA_WIDTH generate statments.
-- ^^^^^^
-- JLJ 3/14/2011 v1.03a
-- ~~~~~~
-- Update ua_narrow_load signal assignment to pass simulations & XST.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Update multiply function on signal, ua_narrow_wrap_gt_width,
-- for timing path improvements. Replace with left shift operation.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity ua_narrow is
generic (
C_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 32;
-- Adjust BRAM address width based on C_AXI_DATA_WIDTH
C_NARROW_BURST_CNT_LEN : integer := 4
-- Size of narrow burst counter
);
port (
curr_wrap_burst : in std_logic;
curr_incr_burst : in std_logic;
bram_addr_ld_en : in std_logic;
curr_axlen : in std_logic_vector (7 downto 0) := (others => '0');
curr_axsize : in std_logic_vector (2 downto 0) := (others => '0');
curr_axaddr_lsb : in std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
curr_ua_narrow_wrap : out std_logic;
curr_ua_narrow_incr : out std_logic;
ua_narrow_load : out std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0)
:= (others => '0')
);
end entity ua_narrow;
-------------------------------------------------------------------------------
architecture implementation of ua_narrow is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- AXI Size Constants
-- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
-- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
-- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
-- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
-- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
-- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
-- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
-- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine max value of ARSIZE based on the AXI data width.
-- Use function in axi_bram_ctrl_funcs package.
constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH);
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
constant C_AXI_DATA_WIDTH_BYTES_LOG2 : integer := log2(C_AXI_DATA_WIDTH_BYTES);
-- Use constant to compare when LSB of ADDR is equal to zero.
constant axaddr_lsb_zero : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
-- 8d = size of AxLEN vector
constant C_MAX_LSHIFT_SIZE : integer := C_AXI_DATA_WIDTH_BYTES_LOG2 + 8;
-- Convert # of data bytes for AXI data bus into an unsigned vector (C_MAX_LSHIFT_SIZE:0).
constant C_AXI_DATA_WIDTH_BYTES_UNSIGNED : unsigned (C_MAX_LSHIFT_SIZE downto 0) :=
to_unsigned (C_AXI_DATA_WIDTH_BYTES, C_MAX_LSHIFT_SIZE+1);
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal ua_narrow_wrap_gt_width : std_logic := '0';
signal curr_axsize_unsigned : unsigned (2 downto 0) := (others => '0');
signal curr_axsize_int : integer := 0;
signal curr_axlen_unsigned : unsigned (7 downto 0) := (others => '0');
signal curr_axlen_unsigned_lshift : unsigned (C_MAX_LSHIFT_SIZE downto 0) := (others => '0'); -- Max = 32768d
signal bytes_per_addr : integer := 1; -- range 1 to 128 := 1;
signal size_plus_lsb : integer := 1; -- range 1 to 256 := 1;
signal narrow_addr_offset : integer := 1;
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
-- v1.03a
-- Added for narrow INCR bursts with UA addresses
-- Check if burst is a) INCR type,
-- b) a narrow burst (SIZE = full width of bus)
-- c) LSB of address is non zero
curr_ua_narrow_incr <= '1' when (curr_incr_burst = '1') and
(curr_axsize (2 downto 0) /= C_AXI_SIZE_MAX) and
(curr_axaddr_lsb /= axaddr_lsb_zero) and
(bram_addr_ld_en = '1')
else '0';
-- v1.03a
-- Detect narrow WRAP bursts
-- Detect if the operation is a) WRAP type,
-- b) a narrow burst (SIZE = full width of bus)
-- c) LSB of address is non zero
-- d) complete size of WRAP is larger than width of BRAM
curr_ua_narrow_wrap <= '1' when (curr_wrap_burst = '1') and
(curr_axsize (2 downto 0) /= C_AXI_SIZE_MAX) and
(curr_axaddr_lsb /= axaddr_lsb_zero) and
(bram_addr_ld_en = '1') and
(ua_narrow_wrap_gt_width = '1')
else '0';
---------------------------------------------------------------------------
-- v1.03a
-- Check condition if narrow burst wraps within the size of the BRAM width.
-- Check if size * length > BRAM width in bytes.
--
-- When asserted = '1', means that narrow burst counter is not preloaded early,
-- the BRAM burst will be contained within the BRAM data width.
curr_axsize_unsigned <= unsigned (curr_axsize);
curr_axsize_int <= to_integer (curr_axsize_unsigned);
curr_axlen_unsigned <= unsigned (curr_axlen);
-- Original logic with multiply function.
--
-- ua_narrow_wrap_gt_width <= '0' when (((2**(to_integer (curr_axsize_unsigned))) *
-- unsigned (curr_axlen (7 downto 0)))
-- < C_AXI_DATA_WIDTH_BYTES)
-- else '1';
-- Replace with left shift operation of AxLEN.
-- Replace multiply of AxLEN * AxSIZE with a left shift function.
LEN_LSHIFT: process (curr_axlen_unsigned, curr_axsize_int)
begin
for i in C_MAX_LSHIFT_SIZE downto 0 loop
if (i >= curr_axsize_int + 8) then
curr_axlen_unsigned_lshift (i) <= '0';
elsif (i >= curr_axsize_int) then
curr_axlen_unsigned_lshift (i) <= curr_axlen_unsigned (i - curr_axsize_int);
else
curr_axlen_unsigned_lshift (i) <= '0';
end if;
end loop;
end process LEN_LSHIFT;
-- Final result.
ua_narrow_wrap_gt_width <= '0' when (curr_axlen_unsigned_lshift < C_AXI_DATA_WIDTH_BYTES_UNSIGNED)
else '1';
---------------------------------------------------------------------------
-- v1.03a
-- For narrow burst transfer, provides the number of bytes per address
-- XST does not support divisors that are not constants AND powers of two.
-- Create process to create a fixed value for divisor.
-- Replace this statement:
-- bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / (2**(to_integer (curr_axsize_unsigned)));
-- With this new process:
-- Replace case statement with unsigned signal comparator.
DIV_AXSIZE: process (curr_axsize)
begin
case (curr_axsize) is
when "000" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 1;
when "001" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 2;
when "010" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 4;
when "011" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 8;
when "100" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 16;
when "101" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 32;
when "110" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 64;
when "111" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 128; -- Max SIZE for 1024-bit AXI bus
when others => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES;
end case;
end process DIV_AXSIZE;
-- Original statement.
-- XST does not support divisors that are not constants AND powers of two.
-- Insert process to perform (size_plus_lsb / size_bytes_int) function in generation of ua_narrow_load.
--
-- size_bytes_int <= (2**(to_integer (curr_axsize_unsigned)));
--
-- ua_narrow_load <= std_logic_vector (to_unsigned (bytes_per_addr -
-- (size_plus_lsb / size_bytes_int), C_NARROW_BURST_CNT_LEN));
-- AxSIZE + LSB of address
-- Use all LSB address bit lanes for the narrow transfer based on C_S_AXI_DATA_WIDTH
size_plus_lsb <= (2**(to_integer (curr_axsize_unsigned))) +
to_integer (unsigned (curr_axaddr_lsb (C_AXI_DATA_WIDTH_BYTES_LOG2-1 downto 0)));
-- Process to keep synthesis with divide by constants that are a power of 2.
DIV_SIZE_BYTES: process (size_plus_lsb,
curr_axsize)
begin
-- Use unsigned w/ curr_axsize signal
case (curr_axsize) is
when "000" => narrow_addr_offset <= size_plus_lsb / 1;
when "001" => narrow_addr_offset <= size_plus_lsb / 2;
when "010" => narrow_addr_offset <= size_plus_lsb / 4;
when "011" => narrow_addr_offset <= size_plus_lsb / 8;
when "100" => narrow_addr_offset <= size_plus_lsb / 16;
when "101" => narrow_addr_offset <= size_plus_lsb / 32;
when "110" => narrow_addr_offset <= size_plus_lsb / 64;
when "111" => narrow_addr_offset <= size_plus_lsb / 128; -- Max SIZE for 1024-bit AXI bus
when others => narrow_addr_offset <= size_plus_lsb;
end case;
end process DIV_SIZE_BYTES;
-- Final new statement.
-- Passing in simulation and XST.
ua_narrow_load <= std_logic_vector (to_unsigned (bytes_per_addr -
narrow_addr_offset, C_NARROW_BURST_CNT_LEN))
when (bytes_per_addr >= narrow_addr_offset)
else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN));
---------------------------------------------------------------------------
end architecture implementation;
|
-- Generic registers file.
--
-- Luz micro-controller implementation
-- Eli Bendersky (C) 2008-2010
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
-- 5-port (three reads, two writes on the same clock cycle)
-- The registers file is completely synchronous. Therefore, read
-- before write is possible on the same cycle into the same
-- register.
--
-- Read ports: A, B, C
-- sel_a/b/c selects which register to output to A/B/C
-- The contents of the selected register will appear on the data
-- lines of the port in the next clock cycle.
--
-- Write ports: Y and Z
-- sel_y/z selects which register to write
-- write_y/z is a strobe to activate writing
--
entity registers is
generic
(
-- Number of registers: 2**NREGS_LOG2
--
NREGS_LOG2: natural := 5
);
port
(
clk: in std_logic;
reset_n: in std_logic;
sel_a: in std_logic_vector(NREGS_LOG2 - 1 downto 0);
reg_a_out: out word;
sel_b: in std_logic_vector(NREGS_LOG2 - 1 downto 0);
reg_b_out: out word;
sel_c: in std_logic_vector(NREGS_LOG2 - 1 downto 0);
reg_c_out: out word;
sel_y: in std_logic_vector(NREGS_LOG2 - 1 downto 0);
write_y: in std_logic;
reg_y_in: in word;
sel_z: in std_logic_vector(NREGS_LOG2 - 1 downto 0);
write_z: in std_logic;
reg_z_in: in word
);
end registers;
architecture registers_arc of registers is
type register_file_type is array(natural range 0 to 2**NREGS_LOG2 - 1) of word;
signal register_file: register_file_type;
begin
proc_regs_out: process(clk, reset_n)
begin
if (reset_n = '0') then
reg_a_out <= (others => '0');
reg_b_out <= (others => '0');
reg_c_out <= (others => '0');
elsif (rising_edge(clk)) then
reg_a_out <= register_file(to_integer(unsigned(sel_a)));
reg_b_out <= register_file(to_integer(unsigned(sel_b)));
reg_c_out <= register_file(to_integer(unsigned(sel_c)));
end if;
end process;
proc_regs_in: process(clk, reset_n)
begin
if (reset_n = '0') then
for i in 0 to 2**NREGS_LOG2 - 1 loop
register_file(i) <= (others => '0');
end loop;
elsif (rising_edge(clk)) then
if (write_y = '1') then
register_file(to_integer(unsigned(sel_y))) <= reg_y_in;
end if;
if (write_z = '1') then
register_file(to_integer(unsigned(sel_z))) <= reg_z_in;
end if;
end if;
end process;
end;
|
-- Generic registers file.
--
-- Luz micro-controller implementation
-- Eli Bendersky (C) 2008-2010
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
-- 5-port (three reads, two writes on the same clock cycle)
-- The registers file is completely synchronous. Therefore, read
-- before write is possible on the same cycle into the same
-- register.
--
-- Read ports: A, B, C
-- sel_a/b/c selects which register to output to A/B/C
-- The contents of the selected register will appear on the data
-- lines of the port in the next clock cycle.
--
-- Write ports: Y and Z
-- sel_y/z selects which register to write
-- write_y/z is a strobe to activate writing
--
entity registers is
generic
(
-- Number of registers: 2**NREGS_LOG2
--
NREGS_LOG2: natural := 5
);
port
(
clk: in std_logic;
reset_n: in std_logic;
sel_a: in std_logic_vector(NREGS_LOG2 - 1 downto 0);
reg_a_out: out word;
sel_b: in std_logic_vector(NREGS_LOG2 - 1 downto 0);
reg_b_out: out word;
sel_c: in std_logic_vector(NREGS_LOG2 - 1 downto 0);
reg_c_out: out word;
sel_y: in std_logic_vector(NREGS_LOG2 - 1 downto 0);
write_y: in std_logic;
reg_y_in: in word;
sel_z: in std_logic_vector(NREGS_LOG2 - 1 downto 0);
write_z: in std_logic;
reg_z_in: in word
);
end registers;
architecture registers_arc of registers is
type register_file_type is array(natural range 0 to 2**NREGS_LOG2 - 1) of word;
signal register_file: register_file_type;
begin
proc_regs_out: process(clk, reset_n)
begin
if (reset_n = '0') then
reg_a_out <= (others => '0');
reg_b_out <= (others => '0');
reg_c_out <= (others => '0');
elsif (rising_edge(clk)) then
reg_a_out <= register_file(to_integer(unsigned(sel_a)));
reg_b_out <= register_file(to_integer(unsigned(sel_b)));
reg_c_out <= register_file(to_integer(unsigned(sel_c)));
end if;
end process;
proc_regs_in: process(clk, reset_n)
begin
if (reset_n = '0') then
for i in 0 to 2**NREGS_LOG2 - 1 loop
register_file(i) <= (others => '0');
end loop;
elsif (rising_edge(clk)) then
if (write_y = '1') then
register_file(to_integer(unsigned(sel_y))) <= reg_y_in;
end if;
if (write_z = '1') then
register_file(to_integer(unsigned(sel_z))) <= reg_z_in;
end if;
end if;
end process;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity instruction_memory is
port(address : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(11 downto 0);
immediate_addr : in std_logic_vector(5 downto 0);
immediate_out : out std_logic_vector(31 downto 0));
end instruction_memory;
architecture Behavioral of instruction_memory is
type instruction_data_type is array (4095 downto 0) of std_logic_vector(11 downto 0); --4 kB of data memory
signal instruction_data : instruction_data_type;
type immediate_data_type is array (63 downto 0) of std_logic_vector(31 downto 0);
signal immediate_data : immediate_data_type;
signal address_short : std_logic_vector(11 downto 0);
begin
address_short <= address(11 downto 0);
data_out <= instruction_data(conv_integer(unsigned(address_short)));
immediate_out <= immediate_data(conv_integer(unsigned(immediate_addr)));
immediate_data(0) <= x"00000000";
immediate_data(1) <= x"80000000";
immediate_data(2) <= x"06660000";
immediate_data(3) <= x"08cc0000";
immediate_data(4) <= x"00000001";
immediate_data(5) <= x"00000012";
immediate_data(6) <= x"20000000";
immediate_data(7) <= x"00000002";
immediate_data(8) <= x"00000003";
immediate_data(9) <= x"000000ff";
immediate_data(10) <= x"40000000";
immediate_data(11) <= x"00000049";
immediate_data(12) <= x"0000004c";
instruction_data(1) <= "010100000001";
instruction_data(2) <= "110011000000";
instruction_data(3) <= "010100000010";
instruction_data(4) <= "010100000000";
instruction_data(5) <= "110001000000";
instruction_data(6) <= "010100000011";
instruction_data(7) <= "010100000100";
instruction_data(8) <= "110001000000";
instruction_data(9) <= "010100000011";
instruction_data(10) <= "010101000000";
instruction_data(11) <= "001011000000";
instruction_data(12) <= "010100000010";
instruction_data(13) <= "010101000000";
instruction_data(14) <= "001011000000";
instruction_data(15) <= "010100000011";
instruction_data(16) <= "010100000011";
instruction_data(17) <= "010100000010";
instruction_data(18) <= "001011000000";
instruction_data(19) <= "010100000110";
instruction_data(20) <= "001011000000";
instruction_data(21) <= "000001000000";
instruction_data(22) <= "010010000000";
instruction_data(23) <= "010100000000";
instruction_data(24) <= "110000000000";
instruction_data(25) <= "010010000000";
instruction_data(26) <= "000010000000";
instruction_data(27) <= "000001000000";
instruction_data(28) <= "010001000000";
instruction_data(29) <= "010101000000";
instruction_data(30) <= "010101000000";
instruction_data(31) <= "001011000000";
instruction_data(32) <= "010101000000";
instruction_data(33) <= "010100000111";
instruction_data(34) <= "110001000000";
instruction_data(35) <= "010010000000";
instruction_data(36) <= "011010000000";
instruction_data(37) <= "010101000000";
instruction_data(38) <= "001011000000";
instruction_data(39) <= "010101000000";
instruction_data(40) <= "010100000111";
instruction_data(41) <= "110000000000";
instruction_data(42) <= "000001000000";
instruction_data(43) <= "010100000111";
instruction_data(44) <= "110001000000";
instruction_data(45) <= "010010000000";
instruction_data(46) <= "010001000000";
instruction_data(47) <= "010100000100";
instruction_data(48) <= "110000000000";
instruction_data(49) <= "010010000000";
instruction_data(50) <= "010100001000";
instruction_data(51) <= "110000000000";
instruction_data(52) <= "010100000100";
instruction_data(53) <= "000001000000";
instruction_data(54) <= "010100001001";
instruction_data(55) <= "000110000000";
instruction_data(56) <= "010000000000";
instruction_data(57) <= "010100001000";
instruction_data(58) <= "110001000000";
instruction_data(59) <= "010100000111";
instruction_data(60) <= "010100001011";
instruction_data(61) <= "100001000000";
instruction_data(62) <= "010100000111";
instruction_data(63) <= "110000000000";
instruction_data(64) <= "010100001010";
instruction_data(65) <= "000110000000";
instruction_data(66) <= "010000000000";
instruction_data(67) <= "010000000000";
instruction_data(68) <= "010100001000";
instruction_data(69) <= "010100001011";
instruction_data(70) <= "100001000000";
instruction_data(71) <= "010100000101";
instruction_data(72) <= "100000000000";
instruction_data(73) <= "010100001000";
instruction_data(74) <= "110000000000";
instruction_data(75) <= "110011000000";
instruction_data(76) <= "010100001100";
instruction_data(77) <= "100000000000";
end Behavioral; |
-------------------------------------------------------------------------------
-- Entity: mcu
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description:
-- Top-level description of a simple von-Neumann MCU.
-- All top-level component are instantiated here. Also, tri-state buffers for
-- bi-directional GPIO pins are described here.
-------------------------------------------------------------------------------
-- Total # of FFs: 0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity mcu is
port(rst : in std_logic;
clk : in std_logic;
-- General-Purpose I/O ports
GPIO_0 : inout std_logic_vector(DW-1 downto 0);
GPIO_1 : inout std_logic_vector(DW-1 downto 0);
GPIO_2 : inout std_logic_vector(DW-1 downto 0);
GPIO_3 : inout std_logic_vector(DW-1 downto 0);
-- Dedicated LCD port
LCD : out std_logic_vector(LCD_PW-1 downto 0)
);
end mcu;
architecture rtl of mcu is
-- CPU signals
signal cpu2bus : t_cpu2bus;
signal bus2cpu : t_bus2cpu;
-- ROM signals
signal bus2rom : t_bus2ros;
signal rom2bus : t_ros2bus;
-- ROM signals
signal bus2ram : t_bus2rws;
signal ram2bus : t_rws2bus;
-- GPIO signals
signal bus2gpio : t_bus2rws;
signal gpio2bus : t_rws2bus;
signal gpio_in : t_gpio_pin_in;
signal gpio_out : t_gpio_pin_out;
-- LCD signals
signal bus2lcd : t_bus2rws;
signal lcd2bus : t_rws2bus;
signal lcd_out : std_logic_vector(LCD_PW-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Tri-state buffers for GPIO pins
-----------------------------------------------------------------------------
gpio_in.in_0 <= GPIO_0;
gpio_in.in_1 <= GPIO_1;
gpio_in.in_2 <= GPIO_2;
gpio_in.in_3 <= GPIO_3;
gen_gpin: for k in 0 to DW-1 generate
GPIO_0(k) <= gpio_out.out_0(k) when gpio_out.enb_0(k) = '1' else 'Z';
GPIO_1(k) <= gpio_out.out_1(k) when gpio_out.enb_1(k) = '1' else 'Z';
GPIO_2(k) <= gpio_out.out_2(k) when gpio_out.enb_2(k) = '1' else 'Z';
GPIO_3(k) <= gpio_out.out_3(k) when gpio_out.enb_3(k) = '1' else 'Z';
end generate;
-----------------------------------------------------------------------------
-- LCD interface pins
-----------------------------------------------------------------------------
LCD <= lcd_out;
-----------------------------------------------------------------------------
-- Instantiation of top-level components (assumed to be in library work)
-----------------------------------------------------------------------------
-- CPU ----------------------------------------------------------------------
i_cpu: entity work.cpu
port map(
rst => rst,
clk => clk,
bus_in => bus2cpu,
bus_out => cpu2bus
);
-- BUS ----------------------------------------------------------------------
i_bus: entity work.buss
port map(
rst => rst,
clk => clk,
cpu_in => cpu2bus,
cpu_out => bus2cpu,
rom_in => rom2bus,
rom_out => bus2rom,
ram_in => ram2bus,
ram_out => bus2ram,
gpio_in => gpio2bus,
gpio_out => bus2gpio,
lcd_in => lcd2bus,
lcd_out => bus2lcd
);
-- ROM ----------------------------------------------------------------------
i_rom: entity work.rom
port map(
clk => clk,
bus_in => bus2rom,
bus_out => rom2bus
);
-- RAM ----------------------------------------------------------------------
i_ram: entity work.ram
port map(
clk => clk,
bus_in => bus2ram,
bus_out => ram2bus
);
-- GPIO ---------------------------------------------------------------------
i_gpio: entity work.gpio
port map(
rst => rst,
clk => clk,
bus_in => bus2gpio,
bus_out => gpio2bus,
pin_in => gpio_in,
pin_out => gpio_out
);
-- LCD ----------------------------------------------------------------------
i_lcd: entity work.lcd
port map(
rst => rst,
clk => clk,
bus_in => bus2lcd,
bus_out => lcd2bus,
lcd_out => lcd_out
);
end rtl;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.3e-06,
W => Wdiff_0,
Wdiff_0init => 5.5e-07,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.3e-06,
W => Wdiff_0,
Wdiff_0init => 5.5e-07,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.4e-06,
W => W_0,
W_0init => 4.7e-05
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.3e-06,
W => Wdiff_0,
Wdiff_0init => 5.5e-07,
scope => private
)
port map(
D => net6,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.3e-06,
W => Wdiff_0,
Wdiff_0init => 5.5e-07,
scope => private
)
port map(
D => net6,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.35e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 2.75e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.35e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 2.75e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.35e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 2.75e-06,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.35e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 2.75e-06,
scope => private
)
port map(
D => net3,
G => net6,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 5.35e-06,
W => Wsrc_2,
Wsrc_2init => 7.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => net4,
N => net2
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 5.35e-06,
W => Wsrc_2,
Wsrc_2init => 7.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net3
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 4.4e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 1.69e-05,
scope => Wprivate
)
port map(
D => net4,
G => vbias2,
S => net7
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.8e-06,
W => Wcm_1,
Wcm_1init => 1.015e-05,
scope => private
)
port map(
D => net7,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.8e-06,
W => Wcmout_1,
Wcmout_1init => 2.005e-05,
scope => private
)
port map(
D => net8,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 4.4e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 1.69e-05,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net8
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 4.4e-06,
W => (pfak)*(WBias),
WBiasinit => 1.895e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 4.4e-06,
W => (pfak)*(WBias),
WBiasinit => 1.895e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 4.4e-06,
W => WBias,
WBiasinit => 1.895e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.4e-06,
W => WBias,
WBiasinit => 1.895e-05
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.4e-06,
W => WBias,
WBiasinit => 1.895e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.4e-06,
W => WBias,
WBiasinit => 1.895e-05
)
port map(
D => net9,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net10,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net10,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net10,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clk_gen is
end clk_gen;
architecture behavior of clk_gen is
component filter
port( data_ext: in std_logic_vector( 7 downto 0);
clock, start, rst: in std_logic;
done: out std_logic);
end component;
signal data_ext: std_logic_vector( 7 downto 0);
signal int_data: integer:=0;
signal clk, start, rst: std_logic;
signal done: std_logic;
signal resettato: integer:=0;
begin
clock_process : process
begin
clk<= '0'; wait for 100 ns; clk <= '1'; wait for 100 ns;
int_data<=int_data+1;
data_ext<=std_logic_vector(to_unsigned(int_data,8));
if(resettato=2) then
start<='0';
end if;
if(resettato=1) then
rst <= '1';
resettato<=2;
end if;
if(resettato=0) then
rst <= '0';
start<='1';
resettato<=1;
end if;
end process;
stimulate: filter port map(data_ext, clk, start, rst, done);
end behavior;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2721.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p04n01i02721ent IS
END c13s04b02x00p04n01i02721ent;
ARCHITECTURE c13s04b02x00p04n01i02721arch OF c13s04b02x00p04n01i02721ent IS
constant T3 : Integer := 2#1111_11__1111# ; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s04b02x00p04n01i02721 - Consecutive underlines are not allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p04n01i02721arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2721.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p04n01i02721ent IS
END c13s04b02x00p04n01i02721ent;
ARCHITECTURE c13s04b02x00p04n01i02721arch OF c13s04b02x00p04n01i02721ent IS
constant T3 : Integer := 2#1111_11__1111# ; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s04b02x00p04n01i02721 - Consecutive underlines are not allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p04n01i02721arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2721.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p04n01i02721ent IS
END c13s04b02x00p04n01i02721ent;
ARCHITECTURE c13s04b02x00p04n01i02721arch OF c13s04b02x00p04n01i02721ent IS
constant T3 : Integer := 2#1111_11__1111# ; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s04b02x00p04n01i02721 - Consecutive underlines are not allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p04n01i02721arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mcmgmt is
port
(
mcmgmt_clk: in std_logic;
mcmgmt_rst: in std_logic;
mcmgmt_port_mem1_oe: out std_logic;
mcmgmt_port_mem1_we: out std_logic;
mcmgmt_port_mem1_en: out std_logic;
mcmgmt_port_mem1_addr: out std_logic_vector(17 downto 0);
mcmgmt_port_mem1_data: inout std_logic_vector(15 downto 0);
mcmgmt_port_mem2_oe: out std_logic;
mcmgmt_port_mem2_we: out std_logic;
mcmgmt_port_mem2_en: out std_logic;
mcmgmt_port_mem2_addr: out std_logic_vector(17 downto 0);
mcmgmt_port_mem2_data: inout std_logic_vector(15 downto 0);
mcmgmt_port_com_data_ready: in std_logic;
mcmgmt_port_com_rdn: out std_logic;
mcmgmt_port_com_tbre: inout std_logic;
mcmgmt_port_com_tsre: inout std_logic;
mcmgmt_port_com_wrn: out std_logic;
mcmgmt_addr: in std_logic_vector(19 downto 0);
mcmgmt_idata: in std_logic_vector(15 downto 0);
mcmgmt_odata: out std_logic_vector(15 downto 0);
mcmgmt_rw: in std_logic;
mcmgmt_by_byte: in std_logic;
mcmgmt_byte_select: in std_logic;
mcmgmt_free: out std_logic;
mcmgmt_int: out std_logic;
mcmgmt_debug_status: out std_logic_vector(4 downto 0)
);
end mcmgmt;
architecture Behavioral of mcmgmt is
signal mcmgmt_status: std_logic_vector(4 downto 0) := "00001";
signal mcmgmt_rst_cache: std_logic := '1';
begin
mcmgmt_debug_status <= mcmgmt_status;
process (mcmgmt_clk)
begin
mcmgmt_rst_cache <= mcmgmt_rst;
mcmgmt_debug_status <= mcmgmt_status;
if (mcmgmt_rst = '0' and mcmgmt_rst_cache = '1') then
mcmgmt_status <= "00000";
mcmgmt_odata <= "0000000000000000";
--mcmgmt_free <= '1';
--mcmgmt_int <= '0';
mcmgmt_odata <= "0000000000000000";
else
if (rising_edge(mcmgmt_clk)) then
if (mcmgmt_status = "00000") then
mcmgmt_free <= '1';
mcmgmt_int <= '0';
mcmgmt_odata <= "0000000000000000";
else
case mcmgmt_status is
when "00001" =>
mcmgmt_port_mem1_en <= '0';
mcmgmt_port_mem1_oe <= '1';
mcmgmt_port_mem1_we <= '1';
mcmgmt_port_mem1_addr <= "000100000000000000";
mcmgmt_port_mem1_data <= "1101010101010100";
mcmgmt_port_com_rdn <= '1';
mcmgmt_free <= '1';
mcmgmt_status <= "00010";
when "00010" =>
mcmgmt_port_mem1_oe <= '1';
mcmgmt_port_mem1_en <= '0';
mcmgmt_port_mem1_we <= '0';
mcmgmt_port_com_rdn <= '1';
mcmgmt_status <= "00000";
when "00101" =>
mcmgmt_status <= "00100";
mcmgmt_port_mem1_we <= '1';
mcmgmt_port_com_rdn <= '1';
when "00110" =>
mcmgmt_port_mem1_oe <= '0';
mcmgmt_port_mem1_en <= '0';
mcmgmt_port_mem1_we <= '1';
mcmgmt_port_com_rdn <= '1';
mcmgmt_port_mem1_addr <= "000100000000000000";
mcmgmt_port_mem1_data <= "ZZZZZZZZZZZZZZZZ";
mcmgmt_status <= "00101";
when "00111" =>
mcmgmt_status <= "00000";
mcmgmt_odata <= mcmgmt_port_mem1_data;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:33:37 11/19/2014
-- Design Name:
-- Module Name: pwm_generator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pwm_generator is
Port ( clk : in STD_LOGIC;
top : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
duty_cycle : in STD_LOGIC_VECTOR (31 downto 0);
enable : in STD_LOGIC;
output : out STD_LOGIC);
end pwm_generator;
architecture Behavioral of pwm_generator is
signal timer_count : unsigned(31 downto 0);
signal out_signal : std_logic;
begin
pwm_proc: process(clk, rst)
begin
if(rst = '1') then
timer_count <= (others => '0');
out_signal <= '1';
elsif(rising_edge(Clock)) then
if(enable = '1') then
timer_count <= timer_count + 1;
end if;
if(timer_count > unsigned(top)) then
timer_count <= (others => '0');
end if;
if(timer_count < unsigned(duty_cycle)) then
out_signal <= '0';
else
out_signal <= '1';
end if;
end if;
end process;
output <= out_signal;
end Behavioral;
|
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