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-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ecb_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ecb_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:05 wig Exp $
-- $Date: 2004/04/06 10:50:05 $
-- $Log: inst_ecb_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:05 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ecb_e
--
architecture rtl of inst_ecb_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A.
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 1-408-826-6000 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
--
-- Simulation Library File for EC/XP
--
-- $Header: G:\\CVS_REPOSITORY\\CVS_MACROS/LEON3SDE/ALTERA/grlib-eval-1.0.4/lib/tech/ec/ec/ORCA_L.vhd,v 1.1 2005/12/06 13:00:23 tame Exp $
--
library std;
use std.textio.all;
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- ************************************************************************
-- Entity definition
-- "generic" members
-- ************************************************************************
entity SC_BRAM_16K_L is
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 262144;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := ""
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end SC_BRAM_16K_L;
-- ************************************************************************
-- Architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_BRAM_16K_L is
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (WDATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to WDATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + WDATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------
--------- Local signals used to propagate input wire delay ---------------
signal WADA_node : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node : std_logic := 'X';
signal WDA_node : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node : std_logic := 'X';
signal RDA_node : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RDA_temp : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal WADB_node : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node : std_logic := 'X';
signal WDB_node : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node : std_logic := 'X';
signal RDB_node : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RDB_temp : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
-- architecture
begin
WADA_node <= WADA;
WEA_node <= WEA;
WDA_node <= WDA;
RADA_node <= RADA;
REA_node <= REA;
RDA <= RDA_TEMP;
WADB_node <= WADB;
WEB_node <= WEB;
WDB_node <= WDB;
RADB_node <= RADB;
REB_node <= REB;
RDB <= RDB_TEMP;
RDB_process: process(RDB_node, WEB_node)
begin
if (WEB_node = '1') then
if (BWRITE_MODE = "WRITETHROUGH") then
RDB_temp <= RDB_node;
elsif (BWRITE_MODE = "NORMAL") then
RDB_temp <= RDB_temp;
end if;
else
RDB_temp <= RDB_node;
end if;
end process;
RDA_process: process(RDA_node, WEA_node)
begin
if (WEA_node = '1') then
if (AWRITE_MODE = "WRITETHROUGH") then
RDA_temp <= RDA_node;
elsif (AWRITE_MODE = "NORMAL") then
RDA_temp <= RDA_temp;
end if;
else
RDA_temp <= RDA_node;
end if;
end process;
-----------------------------------------
--------- Behavior process -------------
-----------------------------------------
KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
--TSPEC: A note about sram initial values and rom mode:
-- If the user does not provide any values, ... default 0
-- for all ram locations in JECED
--QQ 7_17 variable v_MEM : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
variable v_MEM : std_logic_vector(ARRAY_SIZE*WDATA_WIDTH_A + WDATA_WIDTH_A - 1 downto 0) := ( others => '0' );
variable v_INI_DONE : boolean := FALSE;
variable v_WADDR_A : integer;
variable v_RADDR_A : integer;
variable v_WADDR_B : integer;
variable v_RADDR_B : integer;
variable v_WADDRA_Valid_Flag : boolean := TRUE;
variable v_WADDRB_Valid_Flag : boolean := TRUE;
variable v_RADDRA_Valid_Flag : boolean := TRUE;
variable v_RADDRB_Valid_Flag : boolean := TRUE;
begin -- Process
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
v_INI_DONE := TRUE;
end if;
-- Address Check
v_WADDRA_Valid_Flag := Valid_Address(WADA_node);
v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
v_RADDRA_Valid_Flag := Valid_Address(RADA_node);
v_RADDRB_Valid_Flag := Valid_Address(RADB_node);
if ( v_WADDRA_Valid_Flag = TRUE ) then
v_WADDR_A := CONV_INTEGER(WADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_WADDRB_Valid_Flag = TRUE ) then
v_WADDR_B := CONV_INTEGER(WADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressB of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRA_Valid_Flag = TRUE ) then
v_RADDR_A := CONV_INTEGER(RADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRB_Valid_Flag = TRUE ) then
v_RADDR_B := CONV_INTEGER(RADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressB of Port contains invalid bit!"
-- severity warning;
end if;
-- CHECK Operation
if (WEA = '1' and WEB = '1' and
not(
(v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B)
or
(v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
)
) then
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity warning;
end if;
-- MEM Operation
if (WEA_node = '1') then
v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
end if;
if (WEB_node = '1') then
v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
end if;
if (REA_node = '1') then
RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
-- else
-- RDA_node <= ( others => 'X');
end if;
if (REB_node = '1') then
RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
-- else
-- RDB_node <= ( others => 'X');
end if;
end process KERNEL_BEHAV;
end LATTICE_BEHAV;
-- ************************************************************************
--
-- Block Memory: Behavioral Model
-- The kernel of other RAM applications
-- ************************************************************************
--
-- Filename: SC_BLOCK_RAM_L.vhd
-- Description: BRAM behavioral model.
-- ************************************************************************
library std;
use std.textio.all;
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- ************************************************************************
-- Entity definition
-- "generic" members
-- ************************************************************************
entity SC_BRAM_16K_L_SYNC is
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 262144;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := ""
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
WCLK : in STD_LOGIC;
RCLK : in STD_LOGIC
);
end SC_BRAM_16K_L_SYNC;
-- ************************************************************************
-- Architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_BRAM_16K_L_SYNC is
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (WDATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to WDATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + WDATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------
--------- Local signals used to propagate input wire delay ---------------
signal WADA_node : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node : std_logic := 'X';
signal WDA_node : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node : std_logic := 'X';
signal RDA_node : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal WADB_node : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node : std_logic := 'X';
signal WDB_node : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node : std_logic := 'X';
signal RDB_node : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal WCLK_node : std_logic := 'X';
signal RCLK_node : std_logic := 'X';
-- architecture
begin
WADA_node <= WADA;
WEA_node <= WEA;
WDA_node <= WDA;
RADA_node <= RADA;
REA_node <= REA;
RDA <= RDA_node;
WADB_node <= WADB;
WEB_node <= WEB;
WDB_node <= WDB;
RADB_node <= RADB;
REB_node <= REB;
RDB <= RDB_node;
WCLK_node <= WCLK;
RCLK_node <= RCLK;
-----------------------------------------
--------- Behavior process -------------
-----------------------------------------
--KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
KERNEL_BEHAV : process( WCLK_node, RCLK_node)
--TSPEC: A note about sram initial values and rom mode:
-- If the user does not provide any values, ... default 0
-- for all ram locations in JECED
variable v_MEM : std_logic_vector(ARRAY_SIZE*WDATA_WIDTH_A - 1 downto 0) := ( others => '0' );
variable v_INI_DONE : boolean := FALSE;
variable v_WADDR_A : integer;
variable v_RADDR_A : integer;
variable v_WADDR_B : integer;
variable v_RADDR_B : integer;
variable v_WADDRA_Valid_Flag : boolean := TRUE;
variable v_WADDRB_Valid_Flag : boolean := TRUE;
variable v_RADDRA_Valid_Flag : boolean := TRUE;
variable v_RADDRB_Valid_Flag : boolean := TRUE;
begin -- Process
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
v_INI_DONE := TRUE;
end if;
-- Address Check
v_WADDRA_Valid_Flag := Valid_Address(WADA_node);
v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
v_RADDRA_Valid_Flag := Valid_Address(RADA_node);
v_RADDRB_Valid_Flag := Valid_Address(RADB_node);
if ( v_WADDRA_Valid_Flag = TRUE ) then
v_WADDR_A := CONV_INTEGER(WADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_WADDRB_Valid_Flag = TRUE ) then
v_WADDR_B := CONV_INTEGER(WADB_node);
else
-- assert (Now = 0 ps)
-- report "Write AddressB of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRA_Valid_Flag = TRUE ) then
v_RADDR_A := CONV_INTEGER(RADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRB_Valid_Flag = TRUE ) then
v_RADDR_B := CONV_INTEGER(RADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressB of Port contains invalid bit!"
-- severity warning;
end if;
-- CHECK Operation
if (WEA = '1' and WEB = '1' and
not(
(v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B)
or
(v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
)
) then
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity warning;
end if;
-- MEM Operation
if (WEA_node = '1' and WCLK_node'event and WCLK_node = '1' ) then
v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
end if;
if (WEB_node = '1' and WCLK_node'event and WCLK_node = '1') then
v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
end if;
if (REA_node = '1' and RCLK_node'event and RCLK_node = '1') then
RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
-- else
-- RDA_node <= ( others => 'X');
end if;
if (REB_node = '1' and RCLK_node'event and RCLK_node = '1') then
RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
-- else
-- RDB_node <= ( others => 'X');
end if;
end process KERNEL_BEHAV;
end LATTICE_BEHAV;
library std;
use std.textio.all;
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- ************************************************************************
-- Entity definition
-- "generic" members
-- ************************************************************************
entity SC_BRAM_PDP_16K_L is
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 262144;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := ""
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end SC_BRAM_PDP_16K_L;
-- ************************************************************************
-- Architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_BRAM_PDP_16K_L is
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (WDATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to WDATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + WDATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------
--------- Local signals used to propagate input wire delay ---------------
signal WADA_node : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node : std_logic := 'X';
signal WDA_node : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node : std_logic := 'X';
signal RDA_node : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal WADB_node : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node : std_logic := 'X';
signal WDB_node : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node : std_logic := 'X';
signal RDB_node : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
-- architecture
begin
WADA_node <= WADA;
WEA_node <= WEA;
WDA_node <= WDA;
RADA_node <= RADA;
REA_node <= REA;
RDA <= RDA_node;
WADB_node <= WADB;
WEB_node <= WEB;
WDB_node <= WDB;
RADB_node <= RADB;
REB_node <= REB;
RDB <= RDB_node;
-----------------------------------------
--------- Behavior process -------------
-----------------------------------------
KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
--TSPEC: A note about sram initial values and rom mode:
-- If the user does not provide any values, ... default 0
-- for all ram locations in JECED
variable v_MEM : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
variable v_INI_DONE : boolean := FALSE;
variable v_WADDR_A : integer;
variable v_RADDR_A : integer;
variable v_WADDR_B : integer;
variable v_RADDR_B : integer;
variable v_WADDRA_Valid_Flag : boolean := TRUE;
variable v_WADDRB_Valid_Flag : boolean := TRUE;
variable v_RADDRA_Valid_Flag : boolean := TRUE;
variable v_RADDRB_Valid_Flag : boolean := TRUE;
begin -- Process
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
v_INI_DONE := TRUE;
end if;
-- Address Check
v_WADDRA_Valid_Flag := Valid_Address(WADA_node);
v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
v_RADDRA_Valid_Flag := Valid_Address(RADA_node);
v_RADDRB_Valid_Flag := Valid_Address(RADB_node);
if ( v_WADDRA_Valid_Flag = TRUE ) then
v_WADDR_A := CONV_INTEGER(WADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_WADDRB_Valid_Flag = TRUE ) then
v_WADDR_B := CONV_INTEGER(WADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressB of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRA_Valid_Flag = TRUE ) then
v_RADDR_A := CONV_INTEGER(RADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRB_Valid_Flag = TRUE ) then
v_RADDR_B := CONV_INTEGER(RADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressB of Port contains invalid bit!"
-- severity warning;
end if;
-- CHECK Operation
if (WEA = '1' and WEB = '1' and
not(
(v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B)
or
(v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
)
) then
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity warning;
end if;
-- MEM Operation
if (WEA_node = '1') then
v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
end if;
if (WEB_node = '1') then
v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
end if;
if (REA_node = '1') then
RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
-- else
-- RDA_node <= ( others => 'X');
end if;
if (REB_node = '1') then
RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
-- else
-- RDB_node <= ( others => 'X');
end if;
end process KERNEL_BEHAV;
end LATTICE_BEHAV;
---************* SC_FIFO_L **************************
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity READ_POINTER_CTRL is
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end READ_POINTER_CTRL;
architecture LATTICE_BEHAV of READ_POINTER_CTRL is
signal s_READ_POINTER : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
begin
READ_POINTER <= s_READ_POINTER;
process (GLOBAL_RST, RESET_RP, READ_EN, READ_CLK)
variable v_READ_POINTER: STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' or RESET_RP = '1' then
s_READ_POINTER <= (others => '0');
elsif (READ_CLK'EVENT and READ_CLK = '1') then
if (READ_EN = '1' and EMPTY_FLAG = '1') then
v_READ_POINTER := s_READ_POINTER + '1';
else
v_READ_POINTER := s_READ_POINTER;
end if;
if (v_READ_POINTER = TERMINAL_COUNT + 1) then
s_READ_POINTER <= (others => '0');
else
s_READ_POINTER <= v_READ_POINTER;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO COMPONENTS WRITE_POINTER_CTRL
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity WRITE_POINTER_CTRL is
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end WRITE_POINTER_CTRL;
architecture LATTICE_BEHAV of WRITE_POINTER_CTRL is
signal s_WRITE_POINTER : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
WRITE_POINTER <= s_WRITE_POINTER;
process (GLOBAL_RST, WRITE_EN, WRITE_CLK)
variable v_WRITE_POINTER: STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' then
s_WRITE_POINTER <= (others => '0');
elsif (WRITE_CLK'EVENT and WRITE_CLK = '1') then
if (WRITE_EN = '1' and FULL_FLAG /= '1') then
v_WRITE_POINTER := s_WRITE_POINTER + '1';
else
v_WRITE_POINTER := s_WRITE_POINTER ;
end if;
if (v_WRITE_POINTER = TERMINAL_COUNT + 1) then
s_WRITE_POINTER <= (others => '0');
else
s_WRITE_POINTER <= v_WRITE_POINTER;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO COMPONENTS FLAG LOGIC
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity FLAG_LOGIC is
generic (
WPOINTER_WIDTH : integer := 9;
RPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0) := (others => '0');--QQ
R_POINTER : in STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
W_POINTER : in STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0');
GLOBAL_RST : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end FLAG_LOGIC;
architecture LATTICE_BEHAV of FLAG_LOGIC is
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Pointer (
IN_ADDR : in STD_LOGIC_VECTOR
) return BOOLEAN is
variable v_Valid_Flag : BOOLEAN := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Pointer;
--------------------------------------------------------------------------
-- Function: Calculate_Offset
-- Description:
--------------------------------------------------------------------------
function Calculate_Offset (
IN_TC : in STD_LOGIC_VECTOR;
TC_LENGTH: in INTEGER
) return STD_LOGIC_VECTOR is
variable vTC_FULL: STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '1');
variable vTC_TEMP: STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '0');
variable vOFFSET : STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '0');
begin
vTC_TEMP := IN_TC;
vOFFSET := vTC_FULL-vTC_TEMP;
return vOFFSET;
end Calculate_Offset;
begin
--------------------------------------------------------------------------
-- Function: Main Process
-- Description:
--------------------------------------------------------------------------
FULL_AMFULL: process (GLOBAL_RST, WRITE_EN, WRITE_CLK, W_POINTER, R_POINTER)
variable v_WP_Valid_Flag : boolean := TRUE;
variable v_RP_Valid_Flag : boolean := TRUE;
--variable v_WP_Check_FULL_TMP : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_WP_Check_AMFL_TMP : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
variable v_WP_Check_AMFL_TMP1 : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
variable v_WP_Check_FULL : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
variable v_WP_Check_AMFL : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
begin
v_WP_Valid_Flag := Valid_Pointer(W_POINTER);
v_RP_Valid_Flag := Valid_Pointer(R_POINTER);
if( v_WP_Valid_Flag = TRUE) then
v_WP_Check_AMFL_TMP := W_POINTER + AMFULL_X + 1;
end if;
v_WP_Check_AMFL_TMP1 := v_WP_Check_AMFL_TMP + Calculate_Offset(TERMINAL_COUNT, WPOINTER_WIDTH);
if ( v_WP_Valid_Flag = TRUE and W_POINTER = TERMINAL_COUNT ) then
v_WP_Check_FULL := (others => '0');
elsif( v_WP_Valid_Flag = TRUE ) then
v_WP_Check_FULL := W_POINTER + 1;
end if;
if GLOBAL_RST = '1' then
FULL_D <= '0';
AMFULL_D <= '0';
elsif( v_WP_Valid_Flag = TRUE and v_RP_Valid_Flag = TRUE) then
if R_POINTER = v_WP_Check_FULL then
FULL_D <= '1';
else
FULL_D <= '0';
end if;
if (W_POINTER > R_POINTER) then
if (v_WP_Check_AMFL_TMP1 < W_POINTER) then
if v_WP_Check_AMFL_TMP1 >= R_POINTER then
AMFULL_D <= '1';
else
AMFULL_D <= '0';
end if;
else
AMFULL_D <= '0';
end if;
elsif (W_POINTER < R_POINTER) then
if (v_WP_Check_AMFL_TMP1 < W_POINTER) then
AMFULL_D <= '1';
elsif (v_WP_Check_AMFL_TMP >= R_POINTER) then
AMFULL_D <= '1';
else
AMFULL_D <= '0';
end if;
end if;
end if;
end process FULL_AMFULL;
EMPTY_AMEMPTY: process (GLOBAL_RST, READ_EN, READ_CLK, W_POINTER, R_POINTER)
variable v_WP_Valid_Flag : boolean := TRUE;
variable v_RP_Valid_Flag : boolean := TRUE;
variable v_RP_Check_EMPT_TMP : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_RP_Check_AMET_TMP : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_RP_Check_AMET_TMP1 : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
--variable v_RP_Check_EMPT : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_RP_Check_AMET : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
begin
v_WP_Valid_Flag := Valid_Pointer(W_POINTER);
v_RP_Valid_Flag := Valid_Pointer(R_POINTER);
if( v_RP_Valid_Flag = TRUE and v_WP_Valid_Flag = TRUE) then
v_RP_Check_AMET_TMP := R_POINTER + AMEMPTY_Y ; -- Different from TSPEC QQ 07 17,2002
end if;
v_RP_Check_AMET_TMP1 := v_RP_Check_AMET_TMP + Calculate_Offset(TERMINAL_COUNT, RPOINTER_WIDTH);
if GLOBAL_RST = '1' then
EMPTY_D <= '0';
AMEMPTY_D <= '0';
elsif( v_WP_Valid_Flag = TRUE and v_RP_Valid_Flag = TRUE) then
if R_POINTER = W_POINTER then -- Different from TSPEC QQ 07 17,2002
EMPTY_D <= '0';
else
EMPTY_D <= '1';
end if;
if (W_POINTER < R_POINTER) then
if (v_RP_Check_AMET_TMP1 < R_POINTER) then
v_RP_Check_AMET := v_RP_Check_AMET_TMP + Calculate_Offset(TERMINAL_COUNT, RPOINTER_WIDTH);
if v_RP_Check_AMET >= W_POINTER then
AMEMPTY_D <= '0';
else
AMEMPTY_D <= '1';
end if;
else
AMEMPTY_D <= '1';
end if;
elsif (W_POINTER > R_POINTER) then
if (v_RP_Check_AMET_TMP1 < R_POINTER) then
AMEMPTY_D <= '0';
elsif (v_RP_Check_AMET_TMP >= W_POINTER) then
AMEMPTY_D <= '0';
else
AMEMPTY_D <= '1';
end if;
elsif (W_POINTER = R_POINTER) then
AMEMPTY_D <= '0';
end if;
end if;
end process EMPTY_AMEMPTY;
end LATTICE_BEHAV;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
---USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
--LIBRARY SC_LIB;
--USE SC_LIB.SC_FIFO_COMPS.ALL;
entity SC_FIFO_16K_L is
generic (
TERMINAL_COUNT : integer := 511; --QQ: Word number < 2**WADDR_WIDTH
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 9;
RDATA_WIDTH : integer := 32;
ALMOST_FULL_X : integer := 1;
ALMOST_EMPTY_Y : integer := 1;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end SC_FIFO_16K_L;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_FIFO_16K_L is
---------------------------------------------------------
-- Function: TO_STD_VECTOR
---------------------------------------------------------
function TO_STD_VECTOR ( INPUT_STRING : string; INPUT_LENGTH: integer)
return std_logic_vector is
variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
variable vTRANS: string(INPUT_LENGTH downto 1) := (others => '0');
begin
vTRANS := INPUT_STRING;
for i in INPUT_LENGTH downto 1 loop
if (vTRANS(i) = '1') then
vDATA_STD_VEC(i-1) := '1';
elsif ( vTRANS(i) ='0') then
vDATA_STD_VEC(i-1) := '0';
end if;
end loop;
return vDATA_STD_VEC;
end TO_STD_VECTOR;
---------------------------------------------------------
-- Function: INT_TO_VEC
---------------------------------------------------------
function INT_TO_VEC ( INPUT_INT : integer; INPUT_LENGTH: integer)
return std_logic_vector is
variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
variable vTRANS: integer := 0;
variable vQUOTIENT: integer := 0;
begin
vQUOTIENT := INPUT_INT;
for i in 0 to INPUT_LENGTH -1 loop
vTRANS := 0;
while vQUOTIENT >1 loop
vQUOTIENT := vQUOTIENT - 2;
vTRANS := vTRANS + 1;
end loop;
case vQUOTIENT is
when 1 =>
vDATA_STD_VEC(i) := '1';
when 0 =>
vDATA_STD_VEC(i) := '0';
when others =>
null;
end case;
vQUOTIENT := vTRANS;
end loop;
return vDATA_STD_VEC;
end INT_TO_VEC;
---------------------------------------------------------
-- Components Definition
---------------------------------------------------------
component SC_BRAM_16K_L_SYNC
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
WCLK : in STD_LOGIC;
RCLK : in STD_LOGIC
);
end component;
component READ_POINTER_CTRL
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end component;
component WRITE_POINTER_CTRL
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end component;
component FLAG_LOGIC
generic (
WPOINTER_WIDTH : integer := 9;
RPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
R_POINTER : in STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0);
W_POINTER : in STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0);
GLOBAL_RST : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end component;
-- Signal Declaration
signal WE_node : STD_LOGIC := '0';
signal WCLK_node : STD_LOGIC := '0';
signal RST_node : STD_LOGIC := '0';
signal RPRST_node : STD_LOGIC := '0';
signal RE_node : STD_LOGIC := '0';
signal RCLK_node : STD_LOGIC := '0';
signal FULLIN_node : STD_LOGIC := '0';
signal EMPTYIN_node : STD_LOGIC := '0';
signal DI_node : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => '0');
signal DI_reg : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => '0');
signal FULLIN_reg : STD_LOGIC := '0';
signal EMPTYIN_reg : STD_LOGIC := '0';
signal FULL_node : STD_LOGIC := '0';
signal EMPTY_node : STD_LOGIC := '0';
signal AMFULL_node : STD_LOGIC := '0';
signal AMEMPTY_node : STD_LOGIC := '0';
signal DO_node : STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => '0');
signal TC_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
signal FULL_reg : STD_LOGIC := '0';
signal EMPTY_reg : STD_LOGIC := '0';
signal AMFULL_reg : STD_LOGIC := '0';
signal AMEMPTY_reg : STD_LOGIC := '0';
signal RP_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => '0');
signal WP_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
signal GND_sig : STD_LOGIC := '0';
-- architecture
begin
GND_sig <= '0';
WE_node <= WE and not(FULL_node);
WCLK_node <= WCLK;
RST_node <= RST;
RPRST_node <= RPRST;
RE_node <= RE and EMPTY_node;
RCLK_node <= RCLK;
FULLIN_node <= FULLIN;
EMPTYIN_node <= EMPTYIN;
DI_node <= DI;
--TC_node <= TO_STD_VECTOR(TERMINAL_COUNT,WADDR_WIDTH);
TC_node <= INT_TO_VEC(TERMINAL_COUNT,WADDR_WIDTH);
--FULL <= FULL_node;
FULL <= FULL_node when (RE_node = '0') else FULL_reg;
--AMFULL <= AMFULL_node;
AMFULL <= AMFULL_node when (RE_node = '0') else AMFULL_reg;
EMPTY <= not EMPTY_node;
AMEMPTY <= not AMEMPTY_node;
DO <= DO_node;
-- Register Port DI inputs
register_DI_inputs: process (RST_node, WCLK_node)
begin
if (RST_node = '1') then
DI_reg <= (others =>'0');
elsif (WCLK_node'event and WCLK_node = '1') then
if (WE_node = '1') then
DI_reg <= DI_node after 1 ps;
end if;
end if;
end process register_DI_inputs;
-- Register flag inputs
register_flag_inputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULLIN_reg <= '0';
EMPTYIN_reg <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
-- WE_reg <= WE_node and not (FULL_reg); --QQ
if (WE_node = '1') then
FULLIN_reg <= FULLIN_node;
end if;
end if;
if (RCLK_node'event and RCLK_node = '1') then
-- RE_reg <= RE_node and EMPTY_reg; --QQ
if (RE_node = '1') then
EMPTYIN_reg <= EMPTYIN_node;
end if;
end if;
end if;
end process register_flag_inputs;
-- Register flag outputs
register_flag_outputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULL_node <= '0';
AMFULL_node <= '0';
EMPTY_node <= '0';
AMEMPTY_node <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
FULL_node <= FULL_reg;
AMFULL_node <= AMFULL_reg;
end if;
if (RCLK_node'event and RCLK_node = '1') then
EMPTY_node <= EMPTY_reg;
AMEMPTY_node <= AMEMPTY_reg;
end if;
end if;
end process register_flag_outputs;
-- READ_POINTER_CTRL instance for FIFO
FIFO_RPC_INST: READ_POINTER_CTRL
generic map (
RPOINTER_WIDTH => RADDR_WIDTH
)
port map (
TERMINAL_COUNT => TC_node,
GLOBAL_RST => RST_node,
RESET_RP => RPRST_node,
READ_EN => RE_node,
READ_CLK => RCLK_node,
EMPTY_FLAG => EMPTY_reg,
READ_POINTER => RP_node
);
-- WRITE_POINTER_CTRL instance for FIFO
FIFO_WPC_INST: WRITE_POINTER_CTRL
generic map (
WPOINTER_WIDTH => WADDR_WIDTH,
WDATA_WIDTH => WDATA_WIDTH
)
port map (
TERMINAL_COUNT => TC_node,
GLOBAL_RST => RST_node,
WRITE_EN => WE_node,
WRITE_CLK => WCLK_node,
FULL_FLAG => FULL_reg,
WRITE_POINTER => WP_node
);
-- FLAG_LOGIC instance for FIFO
FIFO_FL_INST: FLAG_LOGIC
generic map (
WPOINTER_WIDTH => WADDR_WIDTH,
RPOINTER_WIDTH => RADDR_WIDTH,
WDATA_WIDTH => WDATA_WIDTH,
RDATA_WIDTH => RDATA_WIDTH,
AMFULL_X => ALMOST_FULL_X,
AMEMPTY_Y => ALMOST_EMPTY_Y
)
port map(
TERMINAL_COUNT => TC_node,
R_POINTER => RP_node,
W_POINTER => WP_node,
GLOBAL_RST => RST_node,
READ_EN => RE_node,
READ_CLK => RCLK_node,
WRITE_EN => WE_node,
WRITE_CLK => WCLK_node,
FULL_D => FULL_reg,
EMPTY_D => EMPTY_reg,
AMFULL_D => AMFULL_reg,
AMEMPTY_D => AMEMPTY_reg
);
-- BRAM instance for FIFO
FIFO_BRAM_INST: SC_BRAM_16K_L_SYNC
generic map(
WADDR_WIDTH_A => WADDR_WIDTH,
RADDR_WIDTH_A => RADDR_WIDTH,
WADDR_WIDTH_B => WADDR_WIDTH,
RADDR_WIDTH_B => RADDR_WIDTH,
WDATA_WIDTH_A => WDATA_WIDTH,
RDATA_WIDTH_A => RDATA_WIDTH,
WDATA_WIDTH_B => WDATA_WIDTH,
RDATA_WIDTH_B => RDATA_WIDTH,
ARRAY_SIZE => open,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => WP_node,
WEA => WE_node,
WDA => DI_node,
RADA => RP_node,
REA => RE_node,
RDA => DO_node,
WADB => WP_node,
WEB => GND_sig,
WDB => DI_node,
RADB => RP_node,
REB => GND_sig,
RDB => open,
WCLK => WCLK_node,
RCLK => RCLK_node
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- FIFO V2: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_FIFO_V2.vhd
-- Description: FIFO behavioral model.
-- ************************************************************************
-- FIFO COMPONENTS READ_POINTER_CTRL_V2
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity READ_POINTER_CTRL_V2 is
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end READ_POINTER_CTRL_V2;
architecture LATTICE_BEHAV of READ_POINTER_CTRL_V2 is
signal s_READ_POINTER : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
begin
READ_POINTER <= s_READ_POINTER;
process (GLOBAL_RST, RESET_RP, READ_EN, READ_CLK)
variable v_READ_POINTER: STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' or RESET_RP = '1' then
s_READ_POINTER <= TERMINAL_COUNT;
elsif (READ_CLK'EVENT and READ_CLK = '1') then
if (READ_EN = '1' and EMPTY_FLAG = '1') then
v_READ_POINTER := s_READ_POINTER + '1';
else
v_READ_POINTER := s_READ_POINTER;
end if;
if (v_READ_POINTER = TERMINAL_COUNT + 1) then
s_READ_POINTER <= (others => '0');
else
s_READ_POINTER <= v_READ_POINTER;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO COMPONENTS WRITE_POINTER_CTRL_V2
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity WRITE_POINTER_CTRL_V2 is
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end WRITE_POINTER_CTRL_V2;
architecture LATTICE_BEHAV of WRITE_POINTER_CTRL_V2 is
signal s_WRITE_POINTER : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
WRITE_POINTER <= s_WRITE_POINTER;
process (GLOBAL_RST, WRITE_EN, WRITE_CLK)
variable v_WRITE_POINTER: STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' then
s_WRITE_POINTER <= TERMINAL_COUNT ;
elsif (WRITE_CLK'EVENT and WRITE_CLK = '1') then
if (WRITE_EN = '1' and FULL_FLAG /= '1') then
v_WRITE_POINTER := s_WRITE_POINTER + '1';
else
v_WRITE_POINTER := s_WRITE_POINTER ;
end if;
if (v_WRITE_POINTER = TERMINAL_COUNT + 1) then
s_WRITE_POINTER <= (others => '0');
else
s_WRITE_POINTER <= v_WRITE_POINTER ;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO V2 COMPONENTS FLAG LOGIC
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
entity FLAG_LOGIC_V2 is
generic (
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
GLOBAL_RST : in STD_LOGIC ;
FIFO_CAP : in integer ;
FIFO_PTR : in integer ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end FLAG_LOGIC_V2;
architecture LATTICE_BEHAV of FLAG_LOGIC_V2 is
begin
--------------------------------------------------------------------------
-- Function: Main Process
-- Description:
--------------------------------------------------------------------------
FULL_AMFULL_EMPTY_AMEMPTY: process (GLOBAL_RST, FIFO_CAP, FIFO_PTR)
begin
if GLOBAL_RST = '1' then
FULL_D <= '0';
AMFULL_D <= '0';
EMPTY_D <= '0';
AMEMPTY_D <= '0';
else
if (FIFO_CAP - FIFO_PTR < WDATA_WIDTH) then
FULL_D <= '1';
else
FULL_D <= '0';
end if;
if (FIFO_CAP - FIFO_PTR < WDATA_WIDTH + AMFULL_X * WDATA_WIDTH) then
AMFULL_D <= '1';
else
AMFULL_D <= '0';
end if;
if (FIFO_PTR < RDATA_WIDTH) then
EMPTY_D <= '0';
else
EMPTY_D <= '1';
end if;
if (FIFO_PTR < RDATA_WIDTH + AMEMPTY_Y * RDATA_WIDTH) then
AMEMPTY_D <= '0';
else
AMEMPTY_D <= '1';
end if;
end if;
end process FULL_AMFULL_EMPTY_AMEMPTY;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO V2 Main Body
-- READ_POINTER_CTRL_V2
-- WRITE_POINTER_CTRL_V2
-- FLAG_LOGIC_V2
-- SC_BRAM_16K
-- ************************************************************************
-- ************************************************************************
-- Top Design Entity definition
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity SC_FIFO_V2_16K_L is
generic (
TERMINAL_COUNT : integer := 511; --QQ: Word number < 2**WADDR_WIDTH
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 8;
RDATA_WIDTH : integer := 64;
ALMOST_FULL_X : integer := 2;
ALMOST_EMPTY_Y : integer := 2;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end SC_FIFO_V2_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_FIFO_V2_16K_L is
---------------------------------------------------------
-- Function: TO_STD_VECTOR
---------------------------------------------------------
function TO_STD_VECTOR ( INPUT_STRING : string; INPUT_LENGTH: integer)
return std_logic_vector is
variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
variable vTRANS: string(INPUT_LENGTH downto 1) := (others => '0');
begin
vTRANS := INPUT_STRING;
for i in INPUT_LENGTH downto 1 loop
if (vTRANS(i) = '1') then
vDATA_STD_VEC(i-1) := '1';
elsif ( vTRANS(i) ='0') then
vDATA_STD_VEC(i-1) := '0';
end if;
end loop;
return vDATA_STD_VEC;
end TO_STD_VECTOR;
---------------------------------------------------------
-- Components Definition
---------------------------------------------------------
component SC_BRAM_16K_L
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
component READ_POINTER_CTRL_V2
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end component;
component WRITE_POINTER_CTRL_V2
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end component;
component FLAG_LOGIC_V2
generic (
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
GLOBAL_RST : in STD_LOGIC ;
FIFO_CAP : in integer ;
FIFO_PTR : in integer ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end component;
-- Signal Declaration
signal WE_node : STD_LOGIC := 'X';
signal WCLK_node : STD_LOGIC := 'X';
signal RST_node : STD_LOGIC := 'X';
signal RPRST_node : STD_LOGIC := 'X';
signal RE_node : STD_LOGIC := 'X';
signal RCLK_node : STD_LOGIC := 'X';
signal FULLIN_node : STD_LOGIC := 'X';
signal EMPTYIN_node : STD_LOGIC := 'X';
signal DI_node : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal DI_reg : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal WE_reg : STD_LOGIC := 'X';
signal RE_reg : STD_LOGIC := 'X';
signal FULLIN_reg : STD_LOGIC := 'X';
signal EMPTYIN_reg : STD_LOGIC := 'X';
signal FULL_node : STD_LOGIC := 'X';
signal EMPTY_node : STD_LOGIC := 'X';
signal AMFULL_node : STD_LOGIC := 'X';
signal AMEMPTY_node : STD_LOGIC := 'X';
signal DO_node : STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');
signal TC_W_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
signal TC_R_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal FULL_reg : STD_LOGIC := 'X';
signal EMPTY_reg : STD_LOGIC := 'X';
signal AMFULL_reg : STD_LOGIC := 'X';
signal AMEMPTY_reg : STD_LOGIC := 'X';
signal RP_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal WP_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
signal GND_sig : STD_LOGIC := 'X';
--QQ FIFOV2
signal FIFO_capacity : integer := 0;
signal FIFO_pointer : integer := 0;
-- architecture
begin
FIFO_capacity <= (TERMINAL_COUNT + 1) * WDATA_WIDTH;
GND_sig <= '0';
WE_node <= WE and not (FULL_node);
WCLK_node <= WCLK;
RST_node <= RST;
RPRST_node <= RPRST;
RE_node <= RE;
RCLK_node <= RCLK;
FULLIN_node <= FULLIN;
EMPTYIN_node <= EMPTYIN;
DI_node <= DI;
TC_W_node <= CONV_STD_LOGIC_VECTOR(TERMINAL_COUNT,WADDR_WIDTH);
TC_R_node <= CONV_STD_LOGIC_VECTOR((TERMINAL_COUNT+1)*(WDATA_WIDTH/RDATA_WIDTH)-1,RADDR_WIDTH);
--FULL <= FULL_node;
FULL <= FULL_node when (RE_node = '0') else FULL_reg;
--AMFULL <= AMFULL_node;
AMFULL <= AMFULL_node when (RE_node = '0') else AMFULL_reg;
EMPTY <= not EMPTY_node;
AMEMPTY <= not AMEMPTY_node;
DO <= DO_node;
-- Register Port DI inputs
register_DI_inputs: process (RST_node, WCLK_node)
begin
if (RST_node = '1') then
DI_reg <= (others =>'0');
elsif (WCLK_node'event and WCLK_node = '1') then
if (WE_node = '1') then
DI_reg <= DI_node after 1 ps;
end if;
end if;
end process register_DI_inputs;
-- Register flag inputs
register_flag_inputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULLIN_reg <= '0';
EMPTYIN_reg <= '0';
WE_reg <= '0';
RE_reg <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
WE_reg <= WE_node and not FULL_reg; --Fix DTS14659
--WE_reg <= WE_node;
if (WE_node = '1') then
FULLIN_reg <= FULLIN_node;
end if;
end if;
if (RCLK_node'event and RCLK_node = '1') then
RE_reg <= RE_node and EMPTY_reg;
if (RE_node = '1') then
EMPTYIN_reg <= EMPTYIN_node;
end if;
end if;
end if;
end process register_flag_inputs;
-- Register flag outputs
register_flag_outputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULL_node <= '0';
AMFULL_node <= '0';
EMPTY_node <= '0';
AMEMPTY_node <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
FULL_node <= FULL_reg;
AMFULL_node <= AMFULL_reg;
end if;
if (RCLK_node'event and RCLK_node = '1') then
EMPTY_node <= EMPTY_reg;
AMEMPTY_node <= AMEMPTY_reg;
end if;
end if;
end process register_flag_outputs;
-- Set FIFO_pointer
FIFO_CAP_POINTER: process ( RP_node, WP_node, RST_node, RPRST_node)
begin
--WP ++, FIFO_CAP --
if (WP_node'event and RP_node'event) then
FIFO_pointer <= FIFO_pointer + WDATA_WIDTH - RDATA_WIDTH;
elsif(WP_node'event) then
FIFO_pointer <= FIFO_pointer + WDATA_WIDTH;
end if;
--RPRST Active, FIFO_CAP --
--RP ++, FIFO_CAP ++
if (RST_node = '1') then
FIFO_pointer <= 0;
elsif (RPRST_node = '1') then
FIFO_pointer <= (CONV_INTEGER(WP_node)+1) * WDATA_WIDTH;
elsif (RP_node'event and not(WP_node'event)) then
FIFO_pointer <= FIFO_pointer - RDATA_WIDTH;
end if;
end process FIFO_CAP_POINTER;
-- READ_POINTER_CTRL_V2 instance for FIFO
FIFO_RPC_INST: READ_POINTER_CTRL_V2
generic map (
RPOINTER_WIDTH => RADDR_WIDTH
)
port map (
TERMINAL_COUNT => TC_R_node,
GLOBAL_RST => RST_node,
RESET_RP => RPRST_node,
READ_EN => RE_node,
READ_CLK => RCLK_node,
EMPTY_FLAG => EMPTY_reg,
READ_POINTER => RP_node
);
-- WRITE_POINTER_CTRL_V2 instance for FIFO
FIFO_WPC_INST: WRITE_POINTER_CTRL_V2
generic map (
WPOINTER_WIDTH => WADDR_WIDTH,
WDATA_WIDTH => WDATA_WIDTH
)
port map (
TERMINAL_COUNT => TC_W_node,
GLOBAL_RST => RST_node,
WRITE_EN => WE_node,
WRITE_CLK => WCLK_node,
FULL_FLAG => FULL_reg,
WRITE_POINTER => WP_node
);
-- FLAG_LOGIC_V2 instance for FIFO
FIFO_FL_INST: FLAG_LOGIC_V2
generic map (
WDATA_WIDTH => WDATA_WIDTH,
RDATA_WIDTH => RDATA_WIDTH,
AMFULL_X => ALMOST_FULL_X,
AMEMPTY_Y => ALMOST_EMPTY_Y
)
port map(
GLOBAL_RST => RST_node,
FIFO_CAP => FIFO_capacity,
FIFO_PTR => FIFO_pointer,
FULL_D => FULL_reg,
EMPTY_D => EMPTY_reg,
AMFULL_D => AMFULL_reg,
AMEMPTY_D => AMEMPTY_reg
);
-- BRAM instance for FIFO
FIFO_BRAM_INST: SC_BRAM_16K_L
generic map(
WADDR_WIDTH_A => WADDR_WIDTH,
RADDR_WIDTH_A => RADDR_WIDTH,
WADDR_WIDTH_B => WADDR_WIDTH,
RADDR_WIDTH_B => RADDR_WIDTH,
WDATA_WIDTH_A => WDATA_WIDTH,
RDATA_WIDTH_A => RDATA_WIDTH,
WDATA_WIDTH_B => WDATA_WIDTH,
RDATA_WIDTH_B => RDATA_WIDTH,
ARRAY_SIZE => open,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => WP_node,
WEA => WE_reg,
WDA => DI_reg,
RADA => RP_node,
REA => RE_reg,
RDA => DO_node,
WADB => WP_node,
WEB => GND_sig,
WDB => DI_reg,
RADB => RP_node,
REB => GND_sig,
RDB => open
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- DPRAM: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_DP_RAM.vhd
-- Description: Single Port BRAM behavioral model.
-- History:
-- May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
LIBRARY ieee, std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.all;
USE work.components.all;
-- ************************************************************************
-- Entity definition
-- Draft "generic" members
-- ************************************************************************
entity SC_DPRAM_16K_L is
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
ADDR_WIDTH_A : integer := 13;
DATA_WIDTH_A : integer := 2;
ADDR_WIDTH_B : integer := 14;
DATA_WIDTH_B : integer := 1;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
CENA : in STD_LOGIC ;
CLKA : in STD_LOGIC ;
WRA : in STD_LOGIC ;
CSA : in STD_LOGIC_VECTOR (1 downto 0);
RSTA : in STD_LOGIC ;
DIA : in STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
ADA : in STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
DOA : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
CENB : in STD_LOGIC ;
CLKB : in STD_LOGIC ;
WRB : in STD_LOGIC ;
CSB : in STD_LOGIC_VECTOR (1 downto 0);
RSTB : in STD_LOGIC ;
DIB : in STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
ADB : in STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
DOB : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
);
end SC_DPRAM_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_DPRAM_16K_L is
component SC_BRAM_16K_L
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (DATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**ADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to DATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + DATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
-- Signal Declaration
signal CENA_node : STD_LOGIC := 'X';
signal CLKA_node : STD_LOGIC := 'X';
signal WRA_node : STD_LOGIC := 'X';
signal CSA_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RSTA_node : STD_LOGIC := 'X';
signal DIA_node : STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
signal ADA_node : STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0) := (others => '0');
signal DOA_node : STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
signal DIA_reg : STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
signal ADA_reg : STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0) := (others => 'X');
signal ENA_reg : STD_LOGIC := 'X';
signal RENA_reg : STD_LOGIC := 'X';
signal CENB_node : STD_LOGIC := 'X';
signal CLKB_node : STD_LOGIC := 'X';
signal WRB_node : STD_LOGIC := 'X';
signal CSB_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RSTB_node : STD_LOGIC := 'X';
signal DIB_node : STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
signal ADB_node : STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0) := (others => 'X');
signal DOB_node : STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
signal DIB_reg : STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
signal ADB_reg : STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0) := (others => 'X');
signal ENB_reg : STD_LOGIC := 'X';
signal RENB_reg : STD_LOGIC := 'X';
signal v_MEM : STD_LOGIC_VECTOR(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
signal v_ADA : INTEGER;
signal v_ADB : INTEGER;
-- architecture
begin
CENA_node <= CENA;
CLKA_node <= CLKA;
WRA_node <= WRA;
CSA_node <= CSA;
RSTA_node <= RSTA;
DIA_node <= DIA;
ADA_node <= ADA;
-- DOA <= DOA_node;
CENB_node <= CENB;
CLKB_node <= CLKB;
WRB_node <= WRB;
CSB_node <= CSB;
RSTB_node <= RSTB;
DIB_node <= DIB;
ADB_node <= ADB;
-- DOB <= DOB_node;
init_process : process
variable v_INI_DONE : boolean := FALSE;
variable v_MEM_i : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
begin
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM_i);
v_INI_DONE := TRUE;
end if;
v_MEM <= v_MEM_i;
wait;
end process;
process(ADA_node, ADB_node)
begin
if (Valid_Address(ADA_node) = TRUE) then
v_ADA <= CONV_INTEGER(ADA_node);
end if;
if (Valid_Address(ADB_node) = TRUE) then
v_ADB <= CONV_INTEGER(ADB_node);
end if;
end process;
-- Register Port A DI/ AD / Enable inputs
register_A_inputs: process (CLKA_node, RSTA_node)
begin
if (RSTA_node = '1') then
DIA_reg <= (others =>'0');
ADA_reg <= (others =>'0');
ENA_reg <= '0';
RENA_reg <= '1';
elsif (CLKA_node'event and CLKA_node = '1') then
if (CENA_node = '1') then
DIA_reg <= DIA_node;
ADA_reg <= ADA_node;
ENA_reg <= WRA_node and CSA_node(0) and CSA_node(1);
RENA_reg <= '1';
end if;
end if;
end process register_A_inputs;
-- Register Port B DI/ AD / Enable inputs
register_B_inputs: process (CLKB_node, RSTB_node)
begin
if (RSTB_node = '1') then
DIB_reg <= (others =>'0');
ADB_reg <= (others =>'0');
ENB_reg <= '0';
RENB_reg <= '1';
elsif (CLKB_node'event and CLKB_node = '1') then
if (CENB_node = '1') then
DIB_reg <= DIB_node;
ADB_reg <= ADB_node;
ENB_reg <= WRB_node and CSB_node(0) and CSB_node(1);
RENB_reg <= '1';
end if;
end if;
end process register_B_inputs;
v_MEM_process: process (CLKA_node, CLKB_node)
begin
if (ENA_reg = '1' and CENA_node = '1') then
if (CLKA_node'event and CLKA_node = '1') then
for i in 0 to DATA_WIDTH_A - 1 loop
v_MEM(v_ADA*DATA_WIDTH_A+i) <= DIA_node(i) after 1 ps;
end loop;
end if;
end if;
if (ENB_reg = '1' and CENB_node = '1') then
if (CLKB_node'event and CLKB_node = '1') then
for i in 0 to DATA_WIDTH_B - 1 loop
v_MEM(v_ADB*DATA_WIDTH_B+i) <= DIB_node(i) after 1 ps;
end loop;
end if;
end if;
end process;
DOA_output_process: process (RSTA_node, ENA_reg, CENA_node, DOA_node, CLKA_node)
begin
if (RSTA_node = '1') then
DOA <= (others => '0');
elsif (CLKA_node = '1' and CENA_node = '1') then
if (ENA_reg = '1') then
if (AWRITE_MODE = "RD_BEFORE_WR") then
for j in 0 to DATA_WIDTH_A - 1 loop
DOA(j) <= v_MEM(v_ADA*DATA_WIDTH_A+j);
end loop;
else
DOA <= DOA_node;
end if;
else
DOA <= DOA_node;
end if;
end if;
end process;
DOB_output_process: process (RSTB_node, ENB_reg, CENB_node, DOB_node, CLKB_node)
begin
if (RSTB_node = '1') then
DOB <= (others => '0');
elsif (CLKB_node = '1' and CENB_node = '1') then
if (ENB_reg = '1') then
if (BWRITE_MODE = "RD_BEFORE_WR") then
for j in 0 to DATA_WIDTH_B - 1 loop
DOB(j) <= v_MEM(v_ADB*DATA_WIDTH_B+j);
end loop;
else
DOB <= DOB_node;
end if;
else
DOB <= DOB_node;
end if;
end if;
end process;
-- BRAM instance for SPRAM
DPRAM_INST: SC_BRAM_16K_L
generic map(
AWRITE_MODE => AWRITE_MODE,
BWRITE_MODE => BWRITE_MODE,
WADDR_WIDTH_A => ADDR_WIDTH_A,
RADDR_WIDTH_A => ADDR_WIDTH_A,
WADDR_WIDTH_B => ADDR_WIDTH_B,
RADDR_WIDTH_B => ADDR_WIDTH_B,
WDATA_WIDTH_A => DATA_WIDTH_A,
RDATA_WIDTH_A => DATA_WIDTH_A,
WDATA_WIDTH_B => DATA_WIDTH_B,
RDATA_WIDTH_B => DATA_WIDTH_B,
ARRAY_SIZE => ARRAY_SIZE,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => ADA_reg,
WEA => ENA_reg,
WDA => DIA_reg,
RADA => ADA_reg,
REA => RENA_reg,
RDA => DOA_node,
WADB => ADB_reg,
WEB => ENB_reg,
WDB => DIB_reg,
RADB => ADB_reg,
REB => RENB_reg,
RDB => DOB_node
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- PseudoDPRAM: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_PDP_RAM.vhd
-- Description: Pseudo Dual Port BRAM behavioral model.
-- History:
-- May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
-- ************************************************************************
-- Entity definition
-- Draft "generic" members
-- ************************************************************************
entity SC_PDPRAM_16K_L is
generic (
WADDR_WIDTH : integer := 13;
WDATA_WIDTH : integer := 2;
RADDR_WIDTH : integer := 13;
RDATA_WIDTH : integer := 2;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WCEN : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
WE : in STD_LOGIC ;
WCS : in STD_LOGIC_VECTOR (1 downto 0);
RCLK : in STD_LOGIC;
RCEN : in STD_LOGIC;
RST : in STD_LOGIC ;
WD : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
WAD : in STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
RAD : in STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
RD : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end SC_PDPRAM_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_PDPRAM_16K_L is
component SC_BRAM_16K_L
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
-- Signal Declaration
signal WCEN_node : STD_LOGIC := 'X';
signal WCLK_node : STD_LOGIC := 'X';
signal WE_node : STD_LOGIC := 'X';
signal WCS_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RCEN_node : STD_LOGIC := 'X';
signal RCLK_node : STD_LOGIC := 'X';
signal RST_node : STD_LOGIC := 'X';
signal WD_node : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal WAD_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
signal RD_node : STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');
signal RAD_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal WD_reg : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal WAD_reg : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
signal RAD_reg : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal EN_reg : STD_LOGIC := 'X';
signal REN_reg : STD_LOGIC := 'X';
signal GND_sig : STD_LOGIC;
signal VCC_sig : STD_LOGIC;
-- architecture
begin
GND_sig <= '0';
VCC_sig <= '1';
WCEN_node <= WCEN;
WCLK_node <= WCLK;
WE_node <= WE;
WCS_node <= WCS;
RCEN_node <= RCEN;
RCLK_node <= RCLK;
RST_node <= RST;
WD_node <= WD;
WAD_node <= WAD;
RAD_node <= RAD;
-- RD <= RD_node;
RD_output : process (RD_node, RST_node)
begin
if (RST_node = '1') then
RD <= (others => '0');
else
RD <= RD_node;
end if;
end process;
-- Register WD/WAD/ Enable inputs
register_write_inputs: process (WCLK_node, RST_node)
begin
if (RST_node = '1') then
WD_reg <= (others =>'0');
WAD_reg <= (others =>'0');
EN_reg <= '0';
REN_reg <= '1';
elsif (WCLK_node'event and WCLK_node = '1') then
if (WCEN_node = '1') then
WD_reg <= WD_node;
WAD_reg <= WAD_node;
EN_reg <= WE_node and WCS_node(0) and WCS_node(1);
REN_reg <= '1';
end if;
end if;
end process register_write_inputs;
-- Register RAD inputs
register_read_inputs: process (RCLK_node, RST_node)
begin
if (RST_node = '1') then
RAD_reg <= (others =>'0');
elsif (RCLK_node'event and RCLK_node = '1') then
if (RCEN_node = '1') then
RAD_reg <= RAD_node;
end if;
end if;
end process register_read_inputs;
-- BRAM instance for SPRAM
PDPRAM_INST: SC_BRAM_16K_L
generic map(
WADDR_WIDTH_A => WADDR_WIDTH,
RADDR_WIDTH_A => RADDR_WIDTH,
WADDR_WIDTH_B => WADDR_WIDTH,
RADDR_WIDTH_B => RADDR_WIDTH,
WDATA_WIDTH_A => WDATA_WIDTH,
RDATA_WIDTH_A => RDATA_WIDTH,
WDATA_WIDTH_B => WDATA_WIDTH,
RDATA_WIDTH_B => RDATA_WIDTH,
ARRAY_SIZE => ARRAY_SIZE,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => WAD_reg,
WEA => EN_reg,
WDA => WD_reg,
RADA => RAD_reg,
REA => REN_reg,
RDA => RD_node,
WADB => WAD_reg,
WEB => GND_sig,
WDB => WD_reg,
RADB => RAD_reg,
REB => GND_sig,
RDB => open
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- SPRAM: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_SP_RAM.vhd
-- Description: Single Port BRAM behavioral model.
-- History:
-- May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
LIBRARY ieee, std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.all;
USE work.components.all;
-- ************************************************************************
-- Entity definition
-- Draft "generic" members
-- ************************************************************************
entity SC_SPRAM_16K_L is
generic (
WRITE_MODE : string := "NORMAL";
ADDR_WIDTH : integer := 13;
DATA_WIDTH : integer := 2;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FILE : string := "qq.dat"
);
port (
CEN : in STD_LOGIC ;
CLK : in STD_LOGIC ;
WR : in STD_LOGIC ;
CS : in STD_LOGIC_VECTOR (1 downto 0);
RST : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
AD : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end SC_SPRAM_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_SPRAM_16K_L is
component SC_BRAM_16K_L
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 1;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (DATA_WIDTH downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**ADDR_WIDTH)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to DATA_WIDTH - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + DATA_WIDTH;
end loop;
end READ_MEM_INIT_FILE;
-- Signal Declaration
signal CEN_node : STD_LOGIC := 'X';
signal CLK_node : STD_LOGIC := 'X';
signal WR_node : STD_LOGIC := 'X';
signal CS_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RST_node : STD_LOGIC := 'X';
signal DI_node : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
signal AD_node : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => '0');
signal DO_node : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
signal DI_reg : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
signal AD_reg : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => 'X');
signal EN_reg : STD_LOGIC := 'X';
signal REN_reg : STD_LOGIC := 'X';
signal GND_sig : STD_LOGIC;
signal VCC_sig : STD_LOGIC;
signal v_MEM : STD_LOGIC_VECTOR((2**ADDR_WIDTH) * DATA_WIDTH-1 downto 0) := (others => '0');
signal v_AD : integer;
-- architecture
begin
GND_sig <= '0';
VCC_sig <= '1';
CEN_node <= CEN;
CLK_node <= CLK;
WR_node <= WR;
CS_node <= CS;
RST_node <= RST;
DI_node <= DI;
AD_node <= AD;
-- DO <= DO_node;
init_process : process
variable v_INI_DONE : boolean := FALSE;
variable v_MEM_i : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
begin
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM_i);
v_INI_DONE := TRUE;
end if;
v_MEM <= v_MEM_i;
wait;
end process;
process(AD_node)
begin
if (Valid_Address(AD_node) = TRUE) then
v_AD <= CONV_INTEGER(AD_node);
end if;
end process;
-- Register DI/ AD / Enable inputs
register_inputs: process (CLK_node, RST_node)
begin
if (RST_node = '1') then
DI_reg <= (others =>'0');
AD_reg <= (others =>'0');
EN_reg <= '0';
REN_reg <= '1';
elsif (CLK_node'event and CLK_node = '1') then
if (CEN_node = '1') then
DI_reg <= DI_node;
AD_reg <= AD_node;
EN_reg <= WR_node and CS_node(0) and CS_node(1);
REN_reg <= '1';
end if;
end if;
end process register_inputs;
v_MEM_process: process (EN_reg, DI_node, v_AD, CLK_node)
begin
if (CLK_node'event and CLK_node = '1') then
if (EN_reg = '1' and CEN_node = '1') then
for i in 0 to DATA_WIDTH - 1 loop
v_MEM(v_AD*DATA_WIDTH+i) <= DI_node(i) after 1 ps;
end loop;
end if;
end if;
end process;
DO_output_process: process (RST_node, EN_reg, DO_node, CLK_node)
begin
if (RST_node = '1') then
DO <= (others => '0');
elsif (CLK_node = '1' and CEN_node = '1') then
if (EN_reg = '1') then
if (WRITE_MODE = "RD_BEFORE_WR") then
for j in 0 to DATA_WIDTH - 1 loop
DO(j) <= v_MEM(v_AD*DATA_WIDTH+j);
end loop;
else
DO <= DO_node;
end if;
else
DO <= DO_node;
end if;
end if;
end process;
-- BRAM instance for SPRAM
SPRAM_INST: SC_BRAM_16K_L
generic map(
AWRITE_MODE => WRITE_MODE,
WADDR_WIDTH_A => ADDR_WIDTH,
RADDR_WIDTH_A => ADDR_WIDTH,
WADDR_WIDTH_B => ADDR_WIDTH,
RADDR_WIDTH_B => ADDR_WIDTH,
WDATA_WIDTH_A => DATA_WIDTH,
RDATA_WIDTH_A => DATA_WIDTH,
WDATA_WIDTH_B => DATA_WIDTH,
RDATA_WIDTH_B => DATA_WIDTH,
ARRAY_SIZE => open,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => AD_reg,
WEA => EN_reg,
WDA => DI_reg,
RADA => AD_reg,
REA => REN_reg,
RDA => DO_node,
WADB => AD_reg,
WEB => GND_sig,
WDB => DI_reg,
RADB => AD_reg,
REB => GND_sig,
RDB => open
);
end LATTICE_BEHAV;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
entity fifo_dc is
generic (
module_type : string := "FIFO_DC";
module_width : integer := 1;
module_widthu : integer := 1;
module_numwords : integer := 2;
module_amfull_flag : integer := 1;
module_amempty_flag : integer := 1;
module_hint : string := "UNUSED");
port (
Data : in std_logic_vector (module_width-1 downto 0);
WrClock : in std_logic;
WrEn : in std_logic;
RdClock : in std_logic;
RdEn : in std_logic;
Reset : in std_logic;
RPReset : in std_logic;
Q : out std_logic_vector (module_width-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
AlmostFull : out std_logic;
AlmostEmpty : out std_logic);
end fifo_dc;
architecture fun_simulation of fifo_dc is
component SC_FIFO_16K_L
generic (
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 9;
RDATA_WIDTH : integer := 32;
ALMOST_FULL_X : integer := 1;
ALMOST_EMPTY_Y : integer := 1;
MEM_INIT_FLAG : integer := 0;
TERMINAL_COUNT : integer := 511;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end component;
signal Rst, FullIn, EmptyIn : std_logic;
begin
Rst <= '1';
FullIn <= '0';
EmptyIn <= '1';
SC_FIFO_inst : SC_FIFO_16K_L
generic map (
WADDR_WIDTH => module_widthu,
WDATA_WIDTH => module_width,
RADDR_WIDTH => module_widthu,
RDATA_WIDTH => module_width,
ALMOST_FULL_X => module_amfull_flag,
ALMOST_EMPTY_Y => module_amempty_flag,
MEM_INIT_FLAG => 0,
TERMINAL_COUNT => module_numwords - 1,
MEM_INIT_FILE => open )
port map (
WE => WrEn,
WCLK => WrClock,
RST => Reset,
RPRST => RPReset,
RE => RdEn,
RCLK => RdClock,
FULLIN => FullIn,
EMPTYIN => EmptyIn,
DI => Data,
FULL => Full,
EMPTY => Empty,
AMFULL => AlmostFull,
AMEMPTY => AlmostEmpty,
DO => Q
);
end;library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
entity fifo_dcx is
generic (
module_type : string := "FIFO_DCX";
module_widthw : integer := 1;
module_widthr : integer := 1;
module_widthuw : integer := 1;
module_widthur : integer := 1;
module_numwordsw : integer := 2;
module_numwordsr : integer := 2;
module_amfull_flag : integer := 1;
module_amempty_flag : integer := 1;
module_hint : string := "UNUSED");
port (
Data : in std_logic_vector (module_widthw-1 downto 0);
WrClock : in std_logic;
WrEn : in std_logic;
RdClock : in std_logic;
RdEn : in std_logic;
Reset : in std_logic;
RPReset : in std_logic;
Q : out std_logic_vector (module_widthr-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
AlmostFull : out std_logic;
AlmostEmpty : out std_logic);
end fifo_dcx;
architecture fun_simulation of fifo_dcx is
component SC_FIFO_V2_16K_L
generic (
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 9;
RDATA_WIDTH : integer := 32;
ALMOST_FULL_X : integer := 1;
ALMOST_EMPTY_Y : integer := 1;
MEM_INIT_FLAG : integer := 0;
TERMINAL_COUNT : integer := 511;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end component;
signal FullIn, EmptyIn : std_logic;
begin
FullIn <= '0';
EmptyIn <= '1';
SC_FIFO_inst : SC_FIFO_V2_16K_L
generic map (
WADDR_WIDTH => module_widthuw,
WDATA_WIDTH => module_widthw,
RADDR_WIDTH => module_widthur,
RDATA_WIDTH => module_widthr,
ALMOST_FULL_X => module_amfull_flag,
ALMOST_EMPTY_Y => module_amempty_flag,
MEM_INIT_FLAG => 0,
TERMINAL_COUNT => module_numwordsw - 1,
MEM_INIT_FILE => open )
port map (
WE => WrEn,
WCLK => WrClock,
RST => Reset,
RPRST => RPReset,
RE => RdEn,
RCLK => RdClock,
FULLIN => FullIn,
EMPTYIN => EmptyIn,
DI => Data,
FULL => Full,
EMPTY => Empty,
AMFULL => AlmostFull,
AMEMPTY => AlmostEmpty,
DO => Q
);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use work.components.all;
entity ram_dp is
generic(
module_type : string := "RAM_DP";
module_widthw : integer := 1;
module_widthr : integer := 1;
module_numwordsw : integer := 1;
module_widthadw : integer := 1;
module_widthadr : integer := 1;
module_numwordsr : integer := 1;
module_indata : string := "REGISTERED";
module_outdata : string := "UNREGISTERED";
module_addressw_control : string := "REGISTERED";
module_addressr_control : string := "REGISTERED";
module_gsr : string := "DISABLED";
module_hint : string := "UNUSED";
module_init_file : string := "");
port(
Data : in std_logic_vector (module_widthw-1 downto 0);
WrAddress : in std_logic_vector (module_widthadw-1 downto 0);
RdAddress : in std_logic_vector (module_widthadr-1 downto 0);
WrClock : in std_logic;
WrClockEn : in std_logic;
RdClock : in std_logic;
RdClockEn : in std_logic;
WE : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector (module_widthr-1 downto 0));
end ram_dp;
architecture fun_simulation of ram_dp is
component SC_PDPRAM_16K_L
generic (
WADDR_WIDTH : integer := 13;
WDATA_WIDTH : integer := 2;
RADDR_WIDTH : integer := 13;
RDATA_WIDTH : integer := 2;
ARRAY_SIZE : integer := 511;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WCEN : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
WE : in STD_LOGIC ;
WCS : in STD_LOGIC_VECTOR (1 downto 0);
RCLK : in STD_LOGIC;
RCEN : in STD_LOGIC;
RST : in STD_LOGIC ;
WD : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
WAD : in STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
RAD : in STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
RD : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end component;
signal cs : std_logic_vector ( 1 downto 0);
signal Q_K : std_logic_vector (module_widthr-1 downto 0);
signal Q_K_reg : std_logic_vector (module_widthr-1 downto 0);
CONSTANT module_init_flag : integer := init_flag(module_init_file);
begin
cs <= "11";
OutRegister : process(RdClock, Reset)
begin
if (Reset = '1') then
Q_K_reg <= (others => '0');
elsif (RdClock'EVENT and RdClock = '1') then
if (RdClockEn = '1') then
Q_K_reg <= Q_K;
elsif (RdClockEn /= '0') then
Q_K_reg <= (others => 'X');
end if;
end if;
end process;
SelectOut : process (Q_K , Q_K_reg)
begin
if(module_outdata = "UNREGISTERED" and module_addressr_control = "REGISTERED") then
Q <= Q_K;
elsif(module_outdata = "REGISTERED" and module_addressr_control = "REGISTERED") then
Q <= Q_K_reg;
elsif(module_indata = "UNREGISTERED") then
assert false report "Error: module_indata should be REGISTERED" severity ERROR;
elsif(module_addressw_control = "UNREGISTERED") then
assert false report "Error: module_addressw_control should be REGISTERED" severity ERROR;
elsif(module_addressr_control = "UNREGISTERED") then
assert false report "Error: module_addressr_control should be REGISTERED" severity ERROR;
end if;
end process;
PDPRAM_inst : SC_PDPRAM_16K_L
generic map(
WADDR_WIDTH => module_widthadw,
WDATA_WIDTH => module_widthw,
RADDR_WIDTH => module_widthadr,
RDATA_WIDTH => module_widthr,
MEM_INIT_FLAG => module_init_flag,
ARRAY_SIZE => module_numwordsw*module_widthw,
MEM_INIT_FILE => module_init_file)
port map(
WCEN => WrClockEn,
WCLK => WrClock,
WE => WE,
WCS => cs,
RCLK => RdClock,
RCEN => RdClockEn,
RST => Reset,
WD => Data,
WAD => WrAddress,
RAD => RdAddress,
RD => Q_K
);
end;library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use work.components.all;
entity ram_dp_true is
generic (
module_type : string := "RAM_DP_TRUE";
module_widtha : positive;
module_widthada : positive;
module_numwordsa : positive;
module_widthb : positive;
module_widthadb : positive;
module_numwordsb : positive;
module_indata : string :="REGISTERED";
module_outdata : string :="UNREGISTERED";
module_addressa_control : string :="REGISTERED";
module_addressb_control : string :="REGISTERED";
module_init_file : string := "";
module_hint : string :="UNUSED";
module_gsr : string := "DISABLED";
module_writemode_a : string := "NORMAL";
module_writemode_b : string := "NORMAL");
port (
DataInA : in std_logic_vector(module_widtha-1 downto 0);
AddressA : in std_logic_vector(module_widthada-1 downto 0);
DataInB : in std_logic_vector(module_widthb-1 downto 0);
AddressB : in std_logic_vector(module_widthadb-1 downto 0);
ClockA : in std_logic := '0';
ClockEnA : in std_logic := '0';
ClockB : in std_logic := '0';
ClockEnB : in std_logic := '0';
WrA : in std_logic;
WrB : in std_logic;
ResetA : in std_logic;
ResetB : in std_logic;
QA : out std_logic_vector(module_widtha-1 downto 0);
QB : out std_logic_vector(module_widthb-1 downto 0));
end ram_dp_true;
architecture fun_simulation of ram_dp_true is
component SC_DPRAM_16K_L
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
ADDR_WIDTH_A : integer := 13;
DATA_WIDTH_A : integer := 2;
ADDR_WIDTH_B : integer := 14;
DATA_WIDTH_B : integer := 1;
MEM_INIT_FLAG : integer := 0;
ARRAY_SIZE : integer := 511;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
CENA : in STD_LOGIC ;
CLKA : in STD_LOGIC ;
WRA : in STD_LOGIC ;
CSA : in STD_LOGIC_VECTOR (1 downto 0);
RSTA : in STD_LOGIC ;
DIA : in STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
ADA : in STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
DOA : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
CENB : in STD_LOGIC ;
CLKB : in STD_LOGIC ;
WRB : in STD_LOGIC ;
CSB : in STD_LOGIC_VECTOR (1 downto 0);
RSTB : in STD_LOGIC ;
DIB : in STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
ADB : in STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
DOB : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
);
end component;
signal CS : std_logic_vector ( 1 downto 0);
signal QA_int, QA_int_reg : std_logic_vector(module_widtha-1 downto 0);
signal QB_int, QB_int_reg : std_logic_vector(module_widthb-1 downto 0);
CONSTANT module_init_flag : integer := init_flag(module_init_file);
begin
CS <= "11";
OutRegisterA : process(ClockA, ResetA)
begin
if(ResetA = '1') then QA_int_reg <= (others => '0');
elsif (ClockA'EVENT and ClockA = '1') then
if (ClockEnA = '1') then
QA_int_reg <= QA_int;
elsif (ClockEnA /= '0') then
QA_int_reg <= (others => 'X');
end if;
end if;
end process;
OutRegisterB : process(ClockB, ResetB)
begin
if(ResetB = '1') then QB_int_reg <= (others => '0');
elsif (ClockB'EVENT and ClockB = '1') then
if (ClockEnB = '1') then
QB_int_reg <= QB_int;
elsif (ClockEnB /= '0') then
QB_int_reg <= (others => 'X');
end if;
end if;
end process;
SelectA : process (QA_int , QA_int_reg)
begin
if(module_outdata = "UNREGISTERED" and module_addressa_control = "REGISTERED") then
QA <= QA_int;
elsif(module_outdata = "REGISTERED" and module_addressa_control = "REGISTERED") then
QA <= QA_int_reg;
elsif(module_indata = "UNREGISTERED") then
assert false report "Error: module_indata should be REGISTERED" severity ERROR;
elsif(module_addressa_control = "UNREGISTERED") then
assert false report "Error: module_addressa_control should be REGISTERED" severity ERROR;
end if;
end process;
SelectB : process (QB_int , QB_int_reg)
begin
if(module_outdata = "UNREGISTERED" and module_addressb_control = "REGISTERED") then
QB <= QB_int;
elsif(module_outdata = "REGISTERED" and module_addressb_control = "REGISTERED") then
QB <= QB_int_reg;
elsif(module_addressa_control = "UNREGISTERED") then
assert false report "Error: module_addressa_control should be REGISTERED" severity ERROR;
end if;
end process;
RAM_DP_INST : SC_DPRAM_16K_L
generic map(
ADDR_WIDTH_A => module_widthada,
DATA_WIDTH_A => module_widtha,
ADDR_WIDTH_B => module_widthadb,
DATA_WIDTH_B => module_widthb,
MEM_INIT_FLAG => module_init_flag,
ARRAY_SIZE => module_numwordsa*module_widtha,
MEM_INIT_FILE => module_init_file,
AWRITE_MODE => module_writemode_a,
BWRITE_MODE => module_writemode_b
)
port map (
CENA => ClockEnA,
CLKA => ClockA,
WRA => WrA,
CSA => CS,
RSTA => ResetA,
DIA => DataInA,
ADA => AddressA,
DOA => QA_int,
CENB => ClockEnB,
CLKB => ClockB,
WRB => WrB,
CSB => CS,
RSTB => ResetB,
DIB => DataInB,
ADB => AddressB,
DOB => QB_int
);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use work.components.all;
entity ram_dq is
generic(
module_type : string := "RAM_DQ";
module_width : integer := 1;
module_numwords : integer := 1;
module_widthad : integer := 1;
module_indata : string := "REGISTERED";
module_outdata : string := "UNREGISTERED";
module_address_control : string := "REGISTERED";
module_init_file : string := "";
module_hint : string := "UNUSED";
module_gsr : string := "DISABLED";
module_writemode : string := "NORMAL");
port(
Data : in std_logic_vector (module_width-1 downto 0);
Address : in std_logic_vector (module_widthad-1 downto 0);
Clock : in std_logic;
ClockEn : in std_logic;
WE : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector (module_width-1 downto 0));
end ram_dq;
architecture fun_simulation of ram_dq is
component SC_SPRAM_16K_L
generic (
WRITE_MODE : string := "NORMAL";
ADDR_WIDTH : integer := 13;
DATA_WIDTH : integer := 2;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 511;
MEM_INIT_FILE : string := "qq.dat"
);
port (
CEN : in STD_LOGIC ;
CLK : in STD_LOGIC ;
WR : in STD_LOGIC ;
CS : in STD_LOGIC_VECTOR (1 downto 0);
RST : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
AD : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
signal cs : std_logic_vector (1 downto 0);
signal Q_K : std_logic_vector (module_width-1 downto 0);
signal Q_K_reg : std_logic_vector (module_width-1 downto 0);
CONSTANT module_init_flag : integer := init_flag(module_init_file);
begin
cs <= "11";
OutRegister : process(Clock, Reset)
begin
if (Reset = '1') then
Q_K_reg <= (others => '0');
elsif (Clock'EVENT and Clock = '1') then
if (ClockEn = '1') then
Q_K_reg <= Q_K;
elsif (ClockEn /= '0') then
Q_K_reg <= (others => 'X');
end if;
end if;
end process;
SelectOut : process (Q_K , Q_K_reg)
begin
if(module_outdata = "UNREGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K;
elsif(module_outdata = "REGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K_reg;
elsif(module_indata = "UNREGISTERED") then
assert false report "Error: module_indata should be REGISTERED" severity ERROR;
elsif(module_address_control = "UNREGISTERED") then
assert false report "Error: module_address_control should be REGISTERED" severity ERROR;
end if;
end process;
SPRAM_inst : SC_SPRAM_16K_L
generic map (
ADDR_WIDTH => module_widthad,
DATA_WIDTH => module_width,
MEM_INIT_FLAG => module_init_flag,
ARRAY_SIZE => module_numwords * module_width,
MEM_INIT_FILE => module_init_file,
WRITE_MODE => module_writemode)
port map (
CEN => ClockEn,
CLK => Clock,
WR => WE,
CS => cs,
RST => Reset,
DI => Data,
AD => Address,
DO => Q_K
);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
entity rom is
generic (
module_type : string := "ROM";
module_width : integer := 1;
module_numwords : integer := 1;
module_widthad : integer := 1;
module_outdata : string := "REGISTERED";
module_address_control : string := "REGISTERED";
module_init_file : string := "init_file";
module_gsr : string := "DISABLED";
module_hint : string := "UNUSED");
port (
Address : in std_logic_vector (module_widthad-1 downto 0);
OutClock : in std_logic;
OutClockEn : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector (module_width-1 downto 0));
end rom;
architecture fun_simulation of rom is
component SC_SPRAM_16K_L
generic (
ADDR_WIDTH : integer := 13;
DATA_WIDTH : integer := 2;
ARRAY_SIZE : integer := 511;
MEM_INIT_FLAG : integer := 1;
MEM_INIT_FILE : string := "qq.dat"
);
port (
CEN : in STD_LOGIC ;
CLK : in STD_LOGIC ;
WR : in STD_LOGIC ;
CS : in STD_LOGIC_VECTOR (1 downto 0);
RST : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
AD : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
signal cs : std_logic_vector ( 1 downto 0);
signal DI_sig : std_logic_vector (module_width-1 downto 0);
signal WE_sig : std_logic;
signal Q_K : std_logic_vector (module_width-1 downto 0);
signal Q_K_reg : std_logic_vector (module_width-1 downto 0);
begin
cs <= "11";
WE_sig <= '0';
OutRegister : process(OutClock, Reset)
begin
if (Reset = '1') then
Q_K_reg <= (others => '0');
elsif (OutClock'EVENT and OutClock = '1') then
if(OutClockEn = '1') then
Q_K_reg <= Q_K;
elsif(OutClockEn /= '0') then
Q_K_reg <= (others => 'X' );
end if;
end if;
end process;
SelectOut : process (Q_K , Q_K_reg)
begin
if(module_outdata = "UNREGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K;
elsif(module_outdata = "REGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K_reg;
elsif(module_address_control = "UNREGISTERED") then
assert false report "Error: module_address_control should be REGISTERED" severity ERROR;
end if;
end process;
SPRAM_inst : SC_SPRAM_16K_L
generic map(
ADDR_WIDTH => module_widthad,
DATA_WIDTH => module_width,
MEM_INIT_FLAG => 1,
ARRAY_SIZE => module_numwords * module_width,
MEM_INIT_FILE => module_init_file)
port map(
CEN => OutClockEn,
CLK => OutClock,
WR => WE_sig,
CS => cs,
RST => Reset,
DI => DI_sig,
AD => Address,
DO => Q_K
);
end;
|
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A.
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 1-408-826-6000 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
--
-- Simulation Library File for EC/XP
--
-- $Header: G:\\CVS_REPOSITORY\\CVS_MACROS/LEON3SDE/ALTERA/grlib-eval-1.0.4/lib/tech/ec/ec/ORCA_L.vhd,v 1.1 2005/12/06 13:00:23 tame Exp $
--
library std;
use std.textio.all;
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- ************************************************************************
-- Entity definition
-- "generic" members
-- ************************************************************************
entity SC_BRAM_16K_L is
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 262144;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := ""
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end SC_BRAM_16K_L;
-- ************************************************************************
-- Architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_BRAM_16K_L is
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (WDATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to WDATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + WDATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------
--------- Local signals used to propagate input wire delay ---------------
signal WADA_node : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node : std_logic := 'X';
signal WDA_node : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node : std_logic := 'X';
signal RDA_node : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RDA_temp : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal WADB_node : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node : std_logic := 'X';
signal WDB_node : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node : std_logic := 'X';
signal RDB_node : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RDB_temp : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
-- architecture
begin
WADA_node <= WADA;
WEA_node <= WEA;
WDA_node <= WDA;
RADA_node <= RADA;
REA_node <= REA;
RDA <= RDA_TEMP;
WADB_node <= WADB;
WEB_node <= WEB;
WDB_node <= WDB;
RADB_node <= RADB;
REB_node <= REB;
RDB <= RDB_TEMP;
RDB_process: process(RDB_node, WEB_node)
begin
if (WEB_node = '1') then
if (BWRITE_MODE = "WRITETHROUGH") then
RDB_temp <= RDB_node;
elsif (BWRITE_MODE = "NORMAL") then
RDB_temp <= RDB_temp;
end if;
else
RDB_temp <= RDB_node;
end if;
end process;
RDA_process: process(RDA_node, WEA_node)
begin
if (WEA_node = '1') then
if (AWRITE_MODE = "WRITETHROUGH") then
RDA_temp <= RDA_node;
elsif (AWRITE_MODE = "NORMAL") then
RDA_temp <= RDA_temp;
end if;
else
RDA_temp <= RDA_node;
end if;
end process;
-----------------------------------------
--------- Behavior process -------------
-----------------------------------------
KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
--TSPEC: A note about sram initial values and rom mode:
-- If the user does not provide any values, ... default 0
-- for all ram locations in JECED
--QQ 7_17 variable v_MEM : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
variable v_MEM : std_logic_vector(ARRAY_SIZE*WDATA_WIDTH_A + WDATA_WIDTH_A - 1 downto 0) := ( others => '0' );
variable v_INI_DONE : boolean := FALSE;
variable v_WADDR_A : integer;
variable v_RADDR_A : integer;
variable v_WADDR_B : integer;
variable v_RADDR_B : integer;
variable v_WADDRA_Valid_Flag : boolean := TRUE;
variable v_WADDRB_Valid_Flag : boolean := TRUE;
variable v_RADDRA_Valid_Flag : boolean := TRUE;
variable v_RADDRB_Valid_Flag : boolean := TRUE;
begin -- Process
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
v_INI_DONE := TRUE;
end if;
-- Address Check
v_WADDRA_Valid_Flag := Valid_Address(WADA_node);
v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
v_RADDRA_Valid_Flag := Valid_Address(RADA_node);
v_RADDRB_Valid_Flag := Valid_Address(RADB_node);
if ( v_WADDRA_Valid_Flag = TRUE ) then
v_WADDR_A := CONV_INTEGER(WADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_WADDRB_Valid_Flag = TRUE ) then
v_WADDR_B := CONV_INTEGER(WADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressB of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRA_Valid_Flag = TRUE ) then
v_RADDR_A := CONV_INTEGER(RADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRB_Valid_Flag = TRUE ) then
v_RADDR_B := CONV_INTEGER(RADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressB of Port contains invalid bit!"
-- severity warning;
end if;
-- CHECK Operation
if (WEA = '1' and WEB = '1' and
not(
(v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B)
or
(v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
)
) then
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity warning;
end if;
-- MEM Operation
if (WEA_node = '1') then
v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
end if;
if (WEB_node = '1') then
v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
end if;
if (REA_node = '1') then
RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
-- else
-- RDA_node <= ( others => 'X');
end if;
if (REB_node = '1') then
RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
-- else
-- RDB_node <= ( others => 'X');
end if;
end process KERNEL_BEHAV;
end LATTICE_BEHAV;
-- ************************************************************************
--
-- Block Memory: Behavioral Model
-- The kernel of other RAM applications
-- ************************************************************************
--
-- Filename: SC_BLOCK_RAM_L.vhd
-- Description: BRAM behavioral model.
-- ************************************************************************
library std;
use std.textio.all;
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- ************************************************************************
-- Entity definition
-- "generic" members
-- ************************************************************************
entity SC_BRAM_16K_L_SYNC is
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 262144;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := ""
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
WCLK : in STD_LOGIC;
RCLK : in STD_LOGIC
);
end SC_BRAM_16K_L_SYNC;
-- ************************************************************************
-- Architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_BRAM_16K_L_SYNC is
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (WDATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to WDATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + WDATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------
--------- Local signals used to propagate input wire delay ---------------
signal WADA_node : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node : std_logic := 'X';
signal WDA_node : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node : std_logic := 'X';
signal RDA_node : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal WADB_node : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node : std_logic := 'X';
signal WDB_node : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node : std_logic := 'X';
signal RDB_node : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal WCLK_node : std_logic := 'X';
signal RCLK_node : std_logic := 'X';
-- architecture
begin
WADA_node <= WADA;
WEA_node <= WEA;
WDA_node <= WDA;
RADA_node <= RADA;
REA_node <= REA;
RDA <= RDA_node;
WADB_node <= WADB;
WEB_node <= WEB;
WDB_node <= WDB;
RADB_node <= RADB;
REB_node <= REB;
RDB <= RDB_node;
WCLK_node <= WCLK;
RCLK_node <= RCLK;
-----------------------------------------
--------- Behavior process -------------
-----------------------------------------
--KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
KERNEL_BEHAV : process( WCLK_node, RCLK_node)
--TSPEC: A note about sram initial values and rom mode:
-- If the user does not provide any values, ... default 0
-- for all ram locations in JECED
variable v_MEM : std_logic_vector(ARRAY_SIZE*WDATA_WIDTH_A - 1 downto 0) := ( others => '0' );
variable v_INI_DONE : boolean := FALSE;
variable v_WADDR_A : integer;
variable v_RADDR_A : integer;
variable v_WADDR_B : integer;
variable v_RADDR_B : integer;
variable v_WADDRA_Valid_Flag : boolean := TRUE;
variable v_WADDRB_Valid_Flag : boolean := TRUE;
variable v_RADDRA_Valid_Flag : boolean := TRUE;
variable v_RADDRB_Valid_Flag : boolean := TRUE;
begin -- Process
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
v_INI_DONE := TRUE;
end if;
-- Address Check
v_WADDRA_Valid_Flag := Valid_Address(WADA_node);
v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
v_RADDRA_Valid_Flag := Valid_Address(RADA_node);
v_RADDRB_Valid_Flag := Valid_Address(RADB_node);
if ( v_WADDRA_Valid_Flag = TRUE ) then
v_WADDR_A := CONV_INTEGER(WADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_WADDRB_Valid_Flag = TRUE ) then
v_WADDR_B := CONV_INTEGER(WADB_node);
else
-- assert (Now = 0 ps)
-- report "Write AddressB of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRA_Valid_Flag = TRUE ) then
v_RADDR_A := CONV_INTEGER(RADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRB_Valid_Flag = TRUE ) then
v_RADDR_B := CONV_INTEGER(RADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressB of Port contains invalid bit!"
-- severity warning;
end if;
-- CHECK Operation
if (WEA = '1' and WEB = '1' and
not(
(v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B)
or
(v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
)
) then
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity warning;
end if;
-- MEM Operation
if (WEA_node = '1' and WCLK_node'event and WCLK_node = '1' ) then
v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
end if;
if (WEB_node = '1' and WCLK_node'event and WCLK_node = '1') then
v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
end if;
if (REA_node = '1' and RCLK_node'event and RCLK_node = '1') then
RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
-- else
-- RDA_node <= ( others => 'X');
end if;
if (REB_node = '1' and RCLK_node'event and RCLK_node = '1') then
RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
-- else
-- RDB_node <= ( others => 'X');
end if;
end process KERNEL_BEHAV;
end LATTICE_BEHAV;
library std;
use std.textio.all;
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- ************************************************************************
-- Entity definition
-- "generic" members
-- ************************************************************************
entity SC_BRAM_PDP_16K_L is
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 262144;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := ""
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end SC_BRAM_PDP_16K_L;
-- ************************************************************************
-- Architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_BRAM_PDP_16K_L is
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (WDATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to WDATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + WDATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------
--------- Local signals used to propagate input wire delay ---------------
signal WADA_node : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node : std_logic := 'X';
signal WDA_node : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node : std_logic := 'X';
signal RDA_node : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal WADB_node : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node : std_logic := 'X';
signal WDB_node : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node : std_logic := 'X';
signal RDB_node : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
-- architecture
begin
WADA_node <= WADA;
WEA_node <= WEA;
WDA_node <= WDA;
RADA_node <= RADA;
REA_node <= REA;
RDA <= RDA_node;
WADB_node <= WADB;
WEB_node <= WEB;
WDB_node <= WDB;
RADB_node <= RADB;
REB_node <= REB;
RDB <= RDB_node;
-----------------------------------------
--------- Behavior process -------------
-----------------------------------------
KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
--TSPEC: A note about sram initial values and rom mode:
-- If the user does not provide any values, ... default 0
-- for all ram locations in JECED
variable v_MEM : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
variable v_INI_DONE : boolean := FALSE;
variable v_WADDR_A : integer;
variable v_RADDR_A : integer;
variable v_WADDR_B : integer;
variable v_RADDR_B : integer;
variable v_WADDRA_Valid_Flag : boolean := TRUE;
variable v_WADDRB_Valid_Flag : boolean := TRUE;
variable v_RADDRA_Valid_Flag : boolean := TRUE;
variable v_RADDRB_Valid_Flag : boolean := TRUE;
begin -- Process
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
v_INI_DONE := TRUE;
end if;
-- Address Check
v_WADDRA_Valid_Flag := Valid_Address(WADA_node);
v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
v_RADDRA_Valid_Flag := Valid_Address(RADA_node);
v_RADDRB_Valid_Flag := Valid_Address(RADB_node);
if ( v_WADDRA_Valid_Flag = TRUE ) then
v_WADDR_A := CONV_INTEGER(WADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_WADDRB_Valid_Flag = TRUE ) then
v_WADDR_B := CONV_INTEGER(WADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressB of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRA_Valid_Flag = TRUE ) then
v_RADDR_A := CONV_INTEGER(RADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRB_Valid_Flag = TRUE ) then
v_RADDR_B := CONV_INTEGER(RADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressB of Port contains invalid bit!"
-- severity warning;
end if;
-- CHECK Operation
if (WEA = '1' and WEB = '1' and
not(
(v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B)
or
(v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
)
) then
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity warning;
end if;
-- MEM Operation
if (WEA_node = '1') then
v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
end if;
if (WEB_node = '1') then
v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
end if;
if (REA_node = '1') then
RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
-- else
-- RDA_node <= ( others => 'X');
end if;
if (REB_node = '1') then
RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
-- else
-- RDB_node <= ( others => 'X');
end if;
end process KERNEL_BEHAV;
end LATTICE_BEHAV;
---************* SC_FIFO_L **************************
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity READ_POINTER_CTRL is
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end READ_POINTER_CTRL;
architecture LATTICE_BEHAV of READ_POINTER_CTRL is
signal s_READ_POINTER : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
begin
READ_POINTER <= s_READ_POINTER;
process (GLOBAL_RST, RESET_RP, READ_EN, READ_CLK)
variable v_READ_POINTER: STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' or RESET_RP = '1' then
s_READ_POINTER <= (others => '0');
elsif (READ_CLK'EVENT and READ_CLK = '1') then
if (READ_EN = '1' and EMPTY_FLAG = '1') then
v_READ_POINTER := s_READ_POINTER + '1';
else
v_READ_POINTER := s_READ_POINTER;
end if;
if (v_READ_POINTER = TERMINAL_COUNT + 1) then
s_READ_POINTER <= (others => '0');
else
s_READ_POINTER <= v_READ_POINTER;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO COMPONENTS WRITE_POINTER_CTRL
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity WRITE_POINTER_CTRL is
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end WRITE_POINTER_CTRL;
architecture LATTICE_BEHAV of WRITE_POINTER_CTRL is
signal s_WRITE_POINTER : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
WRITE_POINTER <= s_WRITE_POINTER;
process (GLOBAL_RST, WRITE_EN, WRITE_CLK)
variable v_WRITE_POINTER: STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' then
s_WRITE_POINTER <= (others => '0');
elsif (WRITE_CLK'EVENT and WRITE_CLK = '1') then
if (WRITE_EN = '1' and FULL_FLAG /= '1') then
v_WRITE_POINTER := s_WRITE_POINTER + '1';
else
v_WRITE_POINTER := s_WRITE_POINTER ;
end if;
if (v_WRITE_POINTER = TERMINAL_COUNT + 1) then
s_WRITE_POINTER <= (others => '0');
else
s_WRITE_POINTER <= v_WRITE_POINTER;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO COMPONENTS FLAG LOGIC
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity FLAG_LOGIC is
generic (
WPOINTER_WIDTH : integer := 9;
RPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0) := (others => '0');--QQ
R_POINTER : in STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
W_POINTER : in STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0');
GLOBAL_RST : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end FLAG_LOGIC;
architecture LATTICE_BEHAV of FLAG_LOGIC is
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Pointer (
IN_ADDR : in STD_LOGIC_VECTOR
) return BOOLEAN is
variable v_Valid_Flag : BOOLEAN := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Pointer;
--------------------------------------------------------------------------
-- Function: Calculate_Offset
-- Description:
--------------------------------------------------------------------------
function Calculate_Offset (
IN_TC : in STD_LOGIC_VECTOR;
TC_LENGTH: in INTEGER
) return STD_LOGIC_VECTOR is
variable vTC_FULL: STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '1');
variable vTC_TEMP: STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '0');
variable vOFFSET : STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '0');
begin
vTC_TEMP := IN_TC;
vOFFSET := vTC_FULL-vTC_TEMP;
return vOFFSET;
end Calculate_Offset;
begin
--------------------------------------------------------------------------
-- Function: Main Process
-- Description:
--------------------------------------------------------------------------
FULL_AMFULL: process (GLOBAL_RST, WRITE_EN, WRITE_CLK, W_POINTER, R_POINTER)
variable v_WP_Valid_Flag : boolean := TRUE;
variable v_RP_Valid_Flag : boolean := TRUE;
--variable v_WP_Check_FULL_TMP : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_WP_Check_AMFL_TMP : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
variable v_WP_Check_AMFL_TMP1 : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
variable v_WP_Check_FULL : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
variable v_WP_Check_AMFL : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
begin
v_WP_Valid_Flag := Valid_Pointer(W_POINTER);
v_RP_Valid_Flag := Valid_Pointer(R_POINTER);
if( v_WP_Valid_Flag = TRUE) then
v_WP_Check_AMFL_TMP := W_POINTER + AMFULL_X + 1;
end if;
v_WP_Check_AMFL_TMP1 := v_WP_Check_AMFL_TMP + Calculate_Offset(TERMINAL_COUNT, WPOINTER_WIDTH);
if ( v_WP_Valid_Flag = TRUE and W_POINTER = TERMINAL_COUNT ) then
v_WP_Check_FULL := (others => '0');
elsif( v_WP_Valid_Flag = TRUE ) then
v_WP_Check_FULL := W_POINTER + 1;
end if;
if GLOBAL_RST = '1' then
FULL_D <= '0';
AMFULL_D <= '0';
elsif( v_WP_Valid_Flag = TRUE and v_RP_Valid_Flag = TRUE) then
if R_POINTER = v_WP_Check_FULL then
FULL_D <= '1';
else
FULL_D <= '0';
end if;
if (W_POINTER > R_POINTER) then
if (v_WP_Check_AMFL_TMP1 < W_POINTER) then
if v_WP_Check_AMFL_TMP1 >= R_POINTER then
AMFULL_D <= '1';
else
AMFULL_D <= '0';
end if;
else
AMFULL_D <= '0';
end if;
elsif (W_POINTER < R_POINTER) then
if (v_WP_Check_AMFL_TMP1 < W_POINTER) then
AMFULL_D <= '1';
elsif (v_WP_Check_AMFL_TMP >= R_POINTER) then
AMFULL_D <= '1';
else
AMFULL_D <= '0';
end if;
end if;
end if;
end process FULL_AMFULL;
EMPTY_AMEMPTY: process (GLOBAL_RST, READ_EN, READ_CLK, W_POINTER, R_POINTER)
variable v_WP_Valid_Flag : boolean := TRUE;
variable v_RP_Valid_Flag : boolean := TRUE;
variable v_RP_Check_EMPT_TMP : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_RP_Check_AMET_TMP : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_RP_Check_AMET_TMP1 : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
--variable v_RP_Check_EMPT : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_RP_Check_AMET : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
begin
v_WP_Valid_Flag := Valid_Pointer(W_POINTER);
v_RP_Valid_Flag := Valid_Pointer(R_POINTER);
if( v_RP_Valid_Flag = TRUE and v_WP_Valid_Flag = TRUE) then
v_RP_Check_AMET_TMP := R_POINTER + AMEMPTY_Y ; -- Different from TSPEC QQ 07 17,2002
end if;
v_RP_Check_AMET_TMP1 := v_RP_Check_AMET_TMP + Calculate_Offset(TERMINAL_COUNT, RPOINTER_WIDTH);
if GLOBAL_RST = '1' then
EMPTY_D <= '0';
AMEMPTY_D <= '0';
elsif( v_WP_Valid_Flag = TRUE and v_RP_Valid_Flag = TRUE) then
if R_POINTER = W_POINTER then -- Different from TSPEC QQ 07 17,2002
EMPTY_D <= '0';
else
EMPTY_D <= '1';
end if;
if (W_POINTER < R_POINTER) then
if (v_RP_Check_AMET_TMP1 < R_POINTER) then
v_RP_Check_AMET := v_RP_Check_AMET_TMP + Calculate_Offset(TERMINAL_COUNT, RPOINTER_WIDTH);
if v_RP_Check_AMET >= W_POINTER then
AMEMPTY_D <= '0';
else
AMEMPTY_D <= '1';
end if;
else
AMEMPTY_D <= '1';
end if;
elsif (W_POINTER > R_POINTER) then
if (v_RP_Check_AMET_TMP1 < R_POINTER) then
AMEMPTY_D <= '0';
elsif (v_RP_Check_AMET_TMP >= W_POINTER) then
AMEMPTY_D <= '0';
else
AMEMPTY_D <= '1';
end if;
elsif (W_POINTER = R_POINTER) then
AMEMPTY_D <= '0';
end if;
end if;
end process EMPTY_AMEMPTY;
end LATTICE_BEHAV;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
---USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
--LIBRARY SC_LIB;
--USE SC_LIB.SC_FIFO_COMPS.ALL;
entity SC_FIFO_16K_L is
generic (
TERMINAL_COUNT : integer := 511; --QQ: Word number < 2**WADDR_WIDTH
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 9;
RDATA_WIDTH : integer := 32;
ALMOST_FULL_X : integer := 1;
ALMOST_EMPTY_Y : integer := 1;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end SC_FIFO_16K_L;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_FIFO_16K_L is
---------------------------------------------------------
-- Function: TO_STD_VECTOR
---------------------------------------------------------
function TO_STD_VECTOR ( INPUT_STRING : string; INPUT_LENGTH: integer)
return std_logic_vector is
variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
variable vTRANS: string(INPUT_LENGTH downto 1) := (others => '0');
begin
vTRANS := INPUT_STRING;
for i in INPUT_LENGTH downto 1 loop
if (vTRANS(i) = '1') then
vDATA_STD_VEC(i-1) := '1';
elsif ( vTRANS(i) ='0') then
vDATA_STD_VEC(i-1) := '0';
end if;
end loop;
return vDATA_STD_VEC;
end TO_STD_VECTOR;
---------------------------------------------------------
-- Function: INT_TO_VEC
---------------------------------------------------------
function INT_TO_VEC ( INPUT_INT : integer; INPUT_LENGTH: integer)
return std_logic_vector is
variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
variable vTRANS: integer := 0;
variable vQUOTIENT: integer := 0;
begin
vQUOTIENT := INPUT_INT;
for i in 0 to INPUT_LENGTH -1 loop
vTRANS := 0;
while vQUOTIENT >1 loop
vQUOTIENT := vQUOTIENT - 2;
vTRANS := vTRANS + 1;
end loop;
case vQUOTIENT is
when 1 =>
vDATA_STD_VEC(i) := '1';
when 0 =>
vDATA_STD_VEC(i) := '0';
when others =>
null;
end case;
vQUOTIENT := vTRANS;
end loop;
return vDATA_STD_VEC;
end INT_TO_VEC;
---------------------------------------------------------
-- Components Definition
---------------------------------------------------------
component SC_BRAM_16K_L_SYNC
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
WCLK : in STD_LOGIC;
RCLK : in STD_LOGIC
);
end component;
component READ_POINTER_CTRL
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end component;
component WRITE_POINTER_CTRL
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end component;
component FLAG_LOGIC
generic (
WPOINTER_WIDTH : integer := 9;
RPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
R_POINTER : in STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0);
W_POINTER : in STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0);
GLOBAL_RST : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end component;
-- Signal Declaration
signal WE_node : STD_LOGIC := '0';
signal WCLK_node : STD_LOGIC := '0';
signal RST_node : STD_LOGIC := '0';
signal RPRST_node : STD_LOGIC := '0';
signal RE_node : STD_LOGIC := '0';
signal RCLK_node : STD_LOGIC := '0';
signal FULLIN_node : STD_LOGIC := '0';
signal EMPTYIN_node : STD_LOGIC := '0';
signal DI_node : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => '0');
signal DI_reg : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => '0');
signal FULLIN_reg : STD_LOGIC := '0';
signal EMPTYIN_reg : STD_LOGIC := '0';
signal FULL_node : STD_LOGIC := '0';
signal EMPTY_node : STD_LOGIC := '0';
signal AMFULL_node : STD_LOGIC := '0';
signal AMEMPTY_node : STD_LOGIC := '0';
signal DO_node : STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => '0');
signal TC_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
signal FULL_reg : STD_LOGIC := '0';
signal EMPTY_reg : STD_LOGIC := '0';
signal AMFULL_reg : STD_LOGIC := '0';
signal AMEMPTY_reg : STD_LOGIC := '0';
signal RP_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => '0');
signal WP_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
signal GND_sig : STD_LOGIC := '0';
-- architecture
begin
GND_sig <= '0';
WE_node <= WE and not(FULL_node);
WCLK_node <= WCLK;
RST_node <= RST;
RPRST_node <= RPRST;
RE_node <= RE and EMPTY_node;
RCLK_node <= RCLK;
FULLIN_node <= FULLIN;
EMPTYIN_node <= EMPTYIN;
DI_node <= DI;
--TC_node <= TO_STD_VECTOR(TERMINAL_COUNT,WADDR_WIDTH);
TC_node <= INT_TO_VEC(TERMINAL_COUNT,WADDR_WIDTH);
--FULL <= FULL_node;
FULL <= FULL_node when (RE_node = '0') else FULL_reg;
--AMFULL <= AMFULL_node;
AMFULL <= AMFULL_node when (RE_node = '0') else AMFULL_reg;
EMPTY <= not EMPTY_node;
AMEMPTY <= not AMEMPTY_node;
DO <= DO_node;
-- Register Port DI inputs
register_DI_inputs: process (RST_node, WCLK_node)
begin
if (RST_node = '1') then
DI_reg <= (others =>'0');
elsif (WCLK_node'event and WCLK_node = '1') then
if (WE_node = '1') then
DI_reg <= DI_node after 1 ps;
end if;
end if;
end process register_DI_inputs;
-- Register flag inputs
register_flag_inputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULLIN_reg <= '0';
EMPTYIN_reg <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
-- WE_reg <= WE_node and not (FULL_reg); --QQ
if (WE_node = '1') then
FULLIN_reg <= FULLIN_node;
end if;
end if;
if (RCLK_node'event and RCLK_node = '1') then
-- RE_reg <= RE_node and EMPTY_reg; --QQ
if (RE_node = '1') then
EMPTYIN_reg <= EMPTYIN_node;
end if;
end if;
end if;
end process register_flag_inputs;
-- Register flag outputs
register_flag_outputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULL_node <= '0';
AMFULL_node <= '0';
EMPTY_node <= '0';
AMEMPTY_node <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
FULL_node <= FULL_reg;
AMFULL_node <= AMFULL_reg;
end if;
if (RCLK_node'event and RCLK_node = '1') then
EMPTY_node <= EMPTY_reg;
AMEMPTY_node <= AMEMPTY_reg;
end if;
end if;
end process register_flag_outputs;
-- READ_POINTER_CTRL instance for FIFO
FIFO_RPC_INST: READ_POINTER_CTRL
generic map (
RPOINTER_WIDTH => RADDR_WIDTH
)
port map (
TERMINAL_COUNT => TC_node,
GLOBAL_RST => RST_node,
RESET_RP => RPRST_node,
READ_EN => RE_node,
READ_CLK => RCLK_node,
EMPTY_FLAG => EMPTY_reg,
READ_POINTER => RP_node
);
-- WRITE_POINTER_CTRL instance for FIFO
FIFO_WPC_INST: WRITE_POINTER_CTRL
generic map (
WPOINTER_WIDTH => WADDR_WIDTH,
WDATA_WIDTH => WDATA_WIDTH
)
port map (
TERMINAL_COUNT => TC_node,
GLOBAL_RST => RST_node,
WRITE_EN => WE_node,
WRITE_CLK => WCLK_node,
FULL_FLAG => FULL_reg,
WRITE_POINTER => WP_node
);
-- FLAG_LOGIC instance for FIFO
FIFO_FL_INST: FLAG_LOGIC
generic map (
WPOINTER_WIDTH => WADDR_WIDTH,
RPOINTER_WIDTH => RADDR_WIDTH,
WDATA_WIDTH => WDATA_WIDTH,
RDATA_WIDTH => RDATA_WIDTH,
AMFULL_X => ALMOST_FULL_X,
AMEMPTY_Y => ALMOST_EMPTY_Y
)
port map(
TERMINAL_COUNT => TC_node,
R_POINTER => RP_node,
W_POINTER => WP_node,
GLOBAL_RST => RST_node,
READ_EN => RE_node,
READ_CLK => RCLK_node,
WRITE_EN => WE_node,
WRITE_CLK => WCLK_node,
FULL_D => FULL_reg,
EMPTY_D => EMPTY_reg,
AMFULL_D => AMFULL_reg,
AMEMPTY_D => AMEMPTY_reg
);
-- BRAM instance for FIFO
FIFO_BRAM_INST: SC_BRAM_16K_L_SYNC
generic map(
WADDR_WIDTH_A => WADDR_WIDTH,
RADDR_WIDTH_A => RADDR_WIDTH,
WADDR_WIDTH_B => WADDR_WIDTH,
RADDR_WIDTH_B => RADDR_WIDTH,
WDATA_WIDTH_A => WDATA_WIDTH,
RDATA_WIDTH_A => RDATA_WIDTH,
WDATA_WIDTH_B => WDATA_WIDTH,
RDATA_WIDTH_B => RDATA_WIDTH,
ARRAY_SIZE => open,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => WP_node,
WEA => WE_node,
WDA => DI_node,
RADA => RP_node,
REA => RE_node,
RDA => DO_node,
WADB => WP_node,
WEB => GND_sig,
WDB => DI_node,
RADB => RP_node,
REB => GND_sig,
RDB => open,
WCLK => WCLK_node,
RCLK => RCLK_node
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- FIFO V2: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_FIFO_V2.vhd
-- Description: FIFO behavioral model.
-- ************************************************************************
-- FIFO COMPONENTS READ_POINTER_CTRL_V2
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity READ_POINTER_CTRL_V2 is
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end READ_POINTER_CTRL_V2;
architecture LATTICE_BEHAV of READ_POINTER_CTRL_V2 is
signal s_READ_POINTER : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
begin
READ_POINTER <= s_READ_POINTER;
process (GLOBAL_RST, RESET_RP, READ_EN, READ_CLK)
variable v_READ_POINTER: STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' or RESET_RP = '1' then
s_READ_POINTER <= TERMINAL_COUNT;
elsif (READ_CLK'EVENT and READ_CLK = '1') then
if (READ_EN = '1' and EMPTY_FLAG = '1') then
v_READ_POINTER := s_READ_POINTER + '1';
else
v_READ_POINTER := s_READ_POINTER;
end if;
if (v_READ_POINTER = TERMINAL_COUNT + 1) then
s_READ_POINTER <= (others => '0');
else
s_READ_POINTER <= v_READ_POINTER;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO COMPONENTS WRITE_POINTER_CTRL_V2
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity WRITE_POINTER_CTRL_V2 is
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end WRITE_POINTER_CTRL_V2;
architecture LATTICE_BEHAV of WRITE_POINTER_CTRL_V2 is
signal s_WRITE_POINTER : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
WRITE_POINTER <= s_WRITE_POINTER;
process (GLOBAL_RST, WRITE_EN, WRITE_CLK)
variable v_WRITE_POINTER: STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' then
s_WRITE_POINTER <= TERMINAL_COUNT ;
elsif (WRITE_CLK'EVENT and WRITE_CLK = '1') then
if (WRITE_EN = '1' and FULL_FLAG /= '1') then
v_WRITE_POINTER := s_WRITE_POINTER + '1';
else
v_WRITE_POINTER := s_WRITE_POINTER ;
end if;
if (v_WRITE_POINTER = TERMINAL_COUNT + 1) then
s_WRITE_POINTER <= (others => '0');
else
s_WRITE_POINTER <= v_WRITE_POINTER ;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO V2 COMPONENTS FLAG LOGIC
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
entity FLAG_LOGIC_V2 is
generic (
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
GLOBAL_RST : in STD_LOGIC ;
FIFO_CAP : in integer ;
FIFO_PTR : in integer ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end FLAG_LOGIC_V2;
architecture LATTICE_BEHAV of FLAG_LOGIC_V2 is
begin
--------------------------------------------------------------------------
-- Function: Main Process
-- Description:
--------------------------------------------------------------------------
FULL_AMFULL_EMPTY_AMEMPTY: process (GLOBAL_RST, FIFO_CAP, FIFO_PTR)
begin
if GLOBAL_RST = '1' then
FULL_D <= '0';
AMFULL_D <= '0';
EMPTY_D <= '0';
AMEMPTY_D <= '0';
else
if (FIFO_CAP - FIFO_PTR < WDATA_WIDTH) then
FULL_D <= '1';
else
FULL_D <= '0';
end if;
if (FIFO_CAP - FIFO_PTR < WDATA_WIDTH + AMFULL_X * WDATA_WIDTH) then
AMFULL_D <= '1';
else
AMFULL_D <= '0';
end if;
if (FIFO_PTR < RDATA_WIDTH) then
EMPTY_D <= '0';
else
EMPTY_D <= '1';
end if;
if (FIFO_PTR < RDATA_WIDTH + AMEMPTY_Y * RDATA_WIDTH) then
AMEMPTY_D <= '0';
else
AMEMPTY_D <= '1';
end if;
end if;
end process FULL_AMFULL_EMPTY_AMEMPTY;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO V2 Main Body
-- READ_POINTER_CTRL_V2
-- WRITE_POINTER_CTRL_V2
-- FLAG_LOGIC_V2
-- SC_BRAM_16K
-- ************************************************************************
-- ************************************************************************
-- Top Design Entity definition
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity SC_FIFO_V2_16K_L is
generic (
TERMINAL_COUNT : integer := 511; --QQ: Word number < 2**WADDR_WIDTH
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 8;
RDATA_WIDTH : integer := 64;
ALMOST_FULL_X : integer := 2;
ALMOST_EMPTY_Y : integer := 2;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end SC_FIFO_V2_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_FIFO_V2_16K_L is
---------------------------------------------------------
-- Function: TO_STD_VECTOR
---------------------------------------------------------
function TO_STD_VECTOR ( INPUT_STRING : string; INPUT_LENGTH: integer)
return std_logic_vector is
variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
variable vTRANS: string(INPUT_LENGTH downto 1) := (others => '0');
begin
vTRANS := INPUT_STRING;
for i in INPUT_LENGTH downto 1 loop
if (vTRANS(i) = '1') then
vDATA_STD_VEC(i-1) := '1';
elsif ( vTRANS(i) ='0') then
vDATA_STD_VEC(i-1) := '0';
end if;
end loop;
return vDATA_STD_VEC;
end TO_STD_VECTOR;
---------------------------------------------------------
-- Components Definition
---------------------------------------------------------
component SC_BRAM_16K_L
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
component READ_POINTER_CTRL_V2
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end component;
component WRITE_POINTER_CTRL_V2
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end component;
component FLAG_LOGIC_V2
generic (
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
GLOBAL_RST : in STD_LOGIC ;
FIFO_CAP : in integer ;
FIFO_PTR : in integer ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end component;
-- Signal Declaration
signal WE_node : STD_LOGIC := 'X';
signal WCLK_node : STD_LOGIC := 'X';
signal RST_node : STD_LOGIC := 'X';
signal RPRST_node : STD_LOGIC := 'X';
signal RE_node : STD_LOGIC := 'X';
signal RCLK_node : STD_LOGIC := 'X';
signal FULLIN_node : STD_LOGIC := 'X';
signal EMPTYIN_node : STD_LOGIC := 'X';
signal DI_node : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal DI_reg : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal WE_reg : STD_LOGIC := 'X';
signal RE_reg : STD_LOGIC := 'X';
signal FULLIN_reg : STD_LOGIC := 'X';
signal EMPTYIN_reg : STD_LOGIC := 'X';
signal FULL_node : STD_LOGIC := 'X';
signal EMPTY_node : STD_LOGIC := 'X';
signal AMFULL_node : STD_LOGIC := 'X';
signal AMEMPTY_node : STD_LOGIC := 'X';
signal DO_node : STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');
signal TC_W_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
signal TC_R_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal FULL_reg : STD_LOGIC := 'X';
signal EMPTY_reg : STD_LOGIC := 'X';
signal AMFULL_reg : STD_LOGIC := 'X';
signal AMEMPTY_reg : STD_LOGIC := 'X';
signal RP_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal WP_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
signal GND_sig : STD_LOGIC := 'X';
--QQ FIFOV2
signal FIFO_capacity : integer := 0;
signal FIFO_pointer : integer := 0;
-- architecture
begin
FIFO_capacity <= (TERMINAL_COUNT + 1) * WDATA_WIDTH;
GND_sig <= '0';
WE_node <= WE and not (FULL_node);
WCLK_node <= WCLK;
RST_node <= RST;
RPRST_node <= RPRST;
RE_node <= RE;
RCLK_node <= RCLK;
FULLIN_node <= FULLIN;
EMPTYIN_node <= EMPTYIN;
DI_node <= DI;
TC_W_node <= CONV_STD_LOGIC_VECTOR(TERMINAL_COUNT,WADDR_WIDTH);
TC_R_node <= CONV_STD_LOGIC_VECTOR((TERMINAL_COUNT+1)*(WDATA_WIDTH/RDATA_WIDTH)-1,RADDR_WIDTH);
--FULL <= FULL_node;
FULL <= FULL_node when (RE_node = '0') else FULL_reg;
--AMFULL <= AMFULL_node;
AMFULL <= AMFULL_node when (RE_node = '0') else AMFULL_reg;
EMPTY <= not EMPTY_node;
AMEMPTY <= not AMEMPTY_node;
DO <= DO_node;
-- Register Port DI inputs
register_DI_inputs: process (RST_node, WCLK_node)
begin
if (RST_node = '1') then
DI_reg <= (others =>'0');
elsif (WCLK_node'event and WCLK_node = '1') then
if (WE_node = '1') then
DI_reg <= DI_node after 1 ps;
end if;
end if;
end process register_DI_inputs;
-- Register flag inputs
register_flag_inputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULLIN_reg <= '0';
EMPTYIN_reg <= '0';
WE_reg <= '0';
RE_reg <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
WE_reg <= WE_node and not FULL_reg; --Fix DTS14659
--WE_reg <= WE_node;
if (WE_node = '1') then
FULLIN_reg <= FULLIN_node;
end if;
end if;
if (RCLK_node'event and RCLK_node = '1') then
RE_reg <= RE_node and EMPTY_reg;
if (RE_node = '1') then
EMPTYIN_reg <= EMPTYIN_node;
end if;
end if;
end if;
end process register_flag_inputs;
-- Register flag outputs
register_flag_outputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULL_node <= '0';
AMFULL_node <= '0';
EMPTY_node <= '0';
AMEMPTY_node <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
FULL_node <= FULL_reg;
AMFULL_node <= AMFULL_reg;
end if;
if (RCLK_node'event and RCLK_node = '1') then
EMPTY_node <= EMPTY_reg;
AMEMPTY_node <= AMEMPTY_reg;
end if;
end if;
end process register_flag_outputs;
-- Set FIFO_pointer
FIFO_CAP_POINTER: process ( RP_node, WP_node, RST_node, RPRST_node)
begin
--WP ++, FIFO_CAP --
if (WP_node'event and RP_node'event) then
FIFO_pointer <= FIFO_pointer + WDATA_WIDTH - RDATA_WIDTH;
elsif(WP_node'event) then
FIFO_pointer <= FIFO_pointer + WDATA_WIDTH;
end if;
--RPRST Active, FIFO_CAP --
--RP ++, FIFO_CAP ++
if (RST_node = '1') then
FIFO_pointer <= 0;
elsif (RPRST_node = '1') then
FIFO_pointer <= (CONV_INTEGER(WP_node)+1) * WDATA_WIDTH;
elsif (RP_node'event and not(WP_node'event)) then
FIFO_pointer <= FIFO_pointer - RDATA_WIDTH;
end if;
end process FIFO_CAP_POINTER;
-- READ_POINTER_CTRL_V2 instance for FIFO
FIFO_RPC_INST: READ_POINTER_CTRL_V2
generic map (
RPOINTER_WIDTH => RADDR_WIDTH
)
port map (
TERMINAL_COUNT => TC_R_node,
GLOBAL_RST => RST_node,
RESET_RP => RPRST_node,
READ_EN => RE_node,
READ_CLK => RCLK_node,
EMPTY_FLAG => EMPTY_reg,
READ_POINTER => RP_node
);
-- WRITE_POINTER_CTRL_V2 instance for FIFO
FIFO_WPC_INST: WRITE_POINTER_CTRL_V2
generic map (
WPOINTER_WIDTH => WADDR_WIDTH,
WDATA_WIDTH => WDATA_WIDTH
)
port map (
TERMINAL_COUNT => TC_W_node,
GLOBAL_RST => RST_node,
WRITE_EN => WE_node,
WRITE_CLK => WCLK_node,
FULL_FLAG => FULL_reg,
WRITE_POINTER => WP_node
);
-- FLAG_LOGIC_V2 instance for FIFO
FIFO_FL_INST: FLAG_LOGIC_V2
generic map (
WDATA_WIDTH => WDATA_WIDTH,
RDATA_WIDTH => RDATA_WIDTH,
AMFULL_X => ALMOST_FULL_X,
AMEMPTY_Y => ALMOST_EMPTY_Y
)
port map(
GLOBAL_RST => RST_node,
FIFO_CAP => FIFO_capacity,
FIFO_PTR => FIFO_pointer,
FULL_D => FULL_reg,
EMPTY_D => EMPTY_reg,
AMFULL_D => AMFULL_reg,
AMEMPTY_D => AMEMPTY_reg
);
-- BRAM instance for FIFO
FIFO_BRAM_INST: SC_BRAM_16K_L
generic map(
WADDR_WIDTH_A => WADDR_WIDTH,
RADDR_WIDTH_A => RADDR_WIDTH,
WADDR_WIDTH_B => WADDR_WIDTH,
RADDR_WIDTH_B => RADDR_WIDTH,
WDATA_WIDTH_A => WDATA_WIDTH,
RDATA_WIDTH_A => RDATA_WIDTH,
WDATA_WIDTH_B => WDATA_WIDTH,
RDATA_WIDTH_B => RDATA_WIDTH,
ARRAY_SIZE => open,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => WP_node,
WEA => WE_reg,
WDA => DI_reg,
RADA => RP_node,
REA => RE_reg,
RDA => DO_node,
WADB => WP_node,
WEB => GND_sig,
WDB => DI_reg,
RADB => RP_node,
REB => GND_sig,
RDB => open
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- DPRAM: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_DP_RAM.vhd
-- Description: Single Port BRAM behavioral model.
-- History:
-- May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
LIBRARY ieee, std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.all;
USE work.components.all;
-- ************************************************************************
-- Entity definition
-- Draft "generic" members
-- ************************************************************************
entity SC_DPRAM_16K_L is
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
ADDR_WIDTH_A : integer := 13;
DATA_WIDTH_A : integer := 2;
ADDR_WIDTH_B : integer := 14;
DATA_WIDTH_B : integer := 1;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
CENA : in STD_LOGIC ;
CLKA : in STD_LOGIC ;
WRA : in STD_LOGIC ;
CSA : in STD_LOGIC_VECTOR (1 downto 0);
RSTA : in STD_LOGIC ;
DIA : in STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
ADA : in STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
DOA : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
CENB : in STD_LOGIC ;
CLKB : in STD_LOGIC ;
WRB : in STD_LOGIC ;
CSB : in STD_LOGIC_VECTOR (1 downto 0);
RSTB : in STD_LOGIC ;
DIB : in STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
ADB : in STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
DOB : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
);
end SC_DPRAM_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_DPRAM_16K_L is
component SC_BRAM_16K_L
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (DATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**ADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to DATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + DATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
-- Signal Declaration
signal CENA_node : STD_LOGIC := 'X';
signal CLKA_node : STD_LOGIC := 'X';
signal WRA_node : STD_LOGIC := 'X';
signal CSA_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RSTA_node : STD_LOGIC := 'X';
signal DIA_node : STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
signal ADA_node : STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0) := (others => '0');
signal DOA_node : STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
signal DIA_reg : STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
signal ADA_reg : STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0) := (others => 'X');
signal ENA_reg : STD_LOGIC := 'X';
signal RENA_reg : STD_LOGIC := 'X';
signal CENB_node : STD_LOGIC := 'X';
signal CLKB_node : STD_LOGIC := 'X';
signal WRB_node : STD_LOGIC := 'X';
signal CSB_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RSTB_node : STD_LOGIC := 'X';
signal DIB_node : STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
signal ADB_node : STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0) := (others => 'X');
signal DOB_node : STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
signal DIB_reg : STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
signal ADB_reg : STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0) := (others => 'X');
signal ENB_reg : STD_LOGIC := 'X';
signal RENB_reg : STD_LOGIC := 'X';
signal v_MEM : STD_LOGIC_VECTOR(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
signal v_ADA : INTEGER;
signal v_ADB : INTEGER;
-- architecture
begin
CENA_node <= CENA;
CLKA_node <= CLKA;
WRA_node <= WRA;
CSA_node <= CSA;
RSTA_node <= RSTA;
DIA_node <= DIA;
ADA_node <= ADA;
-- DOA <= DOA_node;
CENB_node <= CENB;
CLKB_node <= CLKB;
WRB_node <= WRB;
CSB_node <= CSB;
RSTB_node <= RSTB;
DIB_node <= DIB;
ADB_node <= ADB;
-- DOB <= DOB_node;
init_process : process
variable v_INI_DONE : boolean := FALSE;
variable v_MEM_i : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
begin
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM_i);
v_INI_DONE := TRUE;
end if;
v_MEM <= v_MEM_i;
wait;
end process;
process(ADA_node, ADB_node)
begin
if (Valid_Address(ADA_node) = TRUE) then
v_ADA <= CONV_INTEGER(ADA_node);
end if;
if (Valid_Address(ADB_node) = TRUE) then
v_ADB <= CONV_INTEGER(ADB_node);
end if;
end process;
-- Register Port A DI/ AD / Enable inputs
register_A_inputs: process (CLKA_node, RSTA_node)
begin
if (RSTA_node = '1') then
DIA_reg <= (others =>'0');
ADA_reg <= (others =>'0');
ENA_reg <= '0';
RENA_reg <= '1';
elsif (CLKA_node'event and CLKA_node = '1') then
if (CENA_node = '1') then
DIA_reg <= DIA_node;
ADA_reg <= ADA_node;
ENA_reg <= WRA_node and CSA_node(0) and CSA_node(1);
RENA_reg <= '1';
end if;
end if;
end process register_A_inputs;
-- Register Port B DI/ AD / Enable inputs
register_B_inputs: process (CLKB_node, RSTB_node)
begin
if (RSTB_node = '1') then
DIB_reg <= (others =>'0');
ADB_reg <= (others =>'0');
ENB_reg <= '0';
RENB_reg <= '1';
elsif (CLKB_node'event and CLKB_node = '1') then
if (CENB_node = '1') then
DIB_reg <= DIB_node;
ADB_reg <= ADB_node;
ENB_reg <= WRB_node and CSB_node(0) and CSB_node(1);
RENB_reg <= '1';
end if;
end if;
end process register_B_inputs;
v_MEM_process: process (CLKA_node, CLKB_node)
begin
if (ENA_reg = '1' and CENA_node = '1') then
if (CLKA_node'event and CLKA_node = '1') then
for i in 0 to DATA_WIDTH_A - 1 loop
v_MEM(v_ADA*DATA_WIDTH_A+i) <= DIA_node(i) after 1 ps;
end loop;
end if;
end if;
if (ENB_reg = '1' and CENB_node = '1') then
if (CLKB_node'event and CLKB_node = '1') then
for i in 0 to DATA_WIDTH_B - 1 loop
v_MEM(v_ADB*DATA_WIDTH_B+i) <= DIB_node(i) after 1 ps;
end loop;
end if;
end if;
end process;
DOA_output_process: process (RSTA_node, ENA_reg, CENA_node, DOA_node, CLKA_node)
begin
if (RSTA_node = '1') then
DOA <= (others => '0');
elsif (CLKA_node = '1' and CENA_node = '1') then
if (ENA_reg = '1') then
if (AWRITE_MODE = "RD_BEFORE_WR") then
for j in 0 to DATA_WIDTH_A - 1 loop
DOA(j) <= v_MEM(v_ADA*DATA_WIDTH_A+j);
end loop;
else
DOA <= DOA_node;
end if;
else
DOA <= DOA_node;
end if;
end if;
end process;
DOB_output_process: process (RSTB_node, ENB_reg, CENB_node, DOB_node, CLKB_node)
begin
if (RSTB_node = '1') then
DOB <= (others => '0');
elsif (CLKB_node = '1' and CENB_node = '1') then
if (ENB_reg = '1') then
if (BWRITE_MODE = "RD_BEFORE_WR") then
for j in 0 to DATA_WIDTH_B - 1 loop
DOB(j) <= v_MEM(v_ADB*DATA_WIDTH_B+j);
end loop;
else
DOB <= DOB_node;
end if;
else
DOB <= DOB_node;
end if;
end if;
end process;
-- BRAM instance for SPRAM
DPRAM_INST: SC_BRAM_16K_L
generic map(
AWRITE_MODE => AWRITE_MODE,
BWRITE_MODE => BWRITE_MODE,
WADDR_WIDTH_A => ADDR_WIDTH_A,
RADDR_WIDTH_A => ADDR_WIDTH_A,
WADDR_WIDTH_B => ADDR_WIDTH_B,
RADDR_WIDTH_B => ADDR_WIDTH_B,
WDATA_WIDTH_A => DATA_WIDTH_A,
RDATA_WIDTH_A => DATA_WIDTH_A,
WDATA_WIDTH_B => DATA_WIDTH_B,
RDATA_WIDTH_B => DATA_WIDTH_B,
ARRAY_SIZE => ARRAY_SIZE,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => ADA_reg,
WEA => ENA_reg,
WDA => DIA_reg,
RADA => ADA_reg,
REA => RENA_reg,
RDA => DOA_node,
WADB => ADB_reg,
WEB => ENB_reg,
WDB => DIB_reg,
RADB => ADB_reg,
REB => RENB_reg,
RDB => DOB_node
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- PseudoDPRAM: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_PDP_RAM.vhd
-- Description: Pseudo Dual Port BRAM behavioral model.
-- History:
-- May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
-- ************************************************************************
-- Entity definition
-- Draft "generic" members
-- ************************************************************************
entity SC_PDPRAM_16K_L is
generic (
WADDR_WIDTH : integer := 13;
WDATA_WIDTH : integer := 2;
RADDR_WIDTH : integer := 13;
RDATA_WIDTH : integer := 2;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WCEN : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
WE : in STD_LOGIC ;
WCS : in STD_LOGIC_VECTOR (1 downto 0);
RCLK : in STD_LOGIC;
RCEN : in STD_LOGIC;
RST : in STD_LOGIC ;
WD : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
WAD : in STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
RAD : in STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
RD : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end SC_PDPRAM_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_PDPRAM_16K_L is
component SC_BRAM_16K_L
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
-- Signal Declaration
signal WCEN_node : STD_LOGIC := 'X';
signal WCLK_node : STD_LOGIC := 'X';
signal WE_node : STD_LOGIC := 'X';
signal WCS_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RCEN_node : STD_LOGIC := 'X';
signal RCLK_node : STD_LOGIC := 'X';
signal RST_node : STD_LOGIC := 'X';
signal WD_node : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal WAD_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
signal RD_node : STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');
signal RAD_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal WD_reg : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal WAD_reg : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
signal RAD_reg : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal EN_reg : STD_LOGIC := 'X';
signal REN_reg : STD_LOGIC := 'X';
signal GND_sig : STD_LOGIC;
signal VCC_sig : STD_LOGIC;
-- architecture
begin
GND_sig <= '0';
VCC_sig <= '1';
WCEN_node <= WCEN;
WCLK_node <= WCLK;
WE_node <= WE;
WCS_node <= WCS;
RCEN_node <= RCEN;
RCLK_node <= RCLK;
RST_node <= RST;
WD_node <= WD;
WAD_node <= WAD;
RAD_node <= RAD;
-- RD <= RD_node;
RD_output : process (RD_node, RST_node)
begin
if (RST_node = '1') then
RD <= (others => '0');
else
RD <= RD_node;
end if;
end process;
-- Register WD/WAD/ Enable inputs
register_write_inputs: process (WCLK_node, RST_node)
begin
if (RST_node = '1') then
WD_reg <= (others =>'0');
WAD_reg <= (others =>'0');
EN_reg <= '0';
REN_reg <= '1';
elsif (WCLK_node'event and WCLK_node = '1') then
if (WCEN_node = '1') then
WD_reg <= WD_node;
WAD_reg <= WAD_node;
EN_reg <= WE_node and WCS_node(0) and WCS_node(1);
REN_reg <= '1';
end if;
end if;
end process register_write_inputs;
-- Register RAD inputs
register_read_inputs: process (RCLK_node, RST_node)
begin
if (RST_node = '1') then
RAD_reg <= (others =>'0');
elsif (RCLK_node'event and RCLK_node = '1') then
if (RCEN_node = '1') then
RAD_reg <= RAD_node;
end if;
end if;
end process register_read_inputs;
-- BRAM instance for SPRAM
PDPRAM_INST: SC_BRAM_16K_L
generic map(
WADDR_WIDTH_A => WADDR_WIDTH,
RADDR_WIDTH_A => RADDR_WIDTH,
WADDR_WIDTH_B => WADDR_WIDTH,
RADDR_WIDTH_B => RADDR_WIDTH,
WDATA_WIDTH_A => WDATA_WIDTH,
RDATA_WIDTH_A => RDATA_WIDTH,
WDATA_WIDTH_B => WDATA_WIDTH,
RDATA_WIDTH_B => RDATA_WIDTH,
ARRAY_SIZE => ARRAY_SIZE,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => WAD_reg,
WEA => EN_reg,
WDA => WD_reg,
RADA => RAD_reg,
REA => REN_reg,
RDA => RD_node,
WADB => WAD_reg,
WEB => GND_sig,
WDB => WD_reg,
RADB => RAD_reg,
REB => GND_sig,
RDB => open
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- SPRAM: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_SP_RAM.vhd
-- Description: Single Port BRAM behavioral model.
-- History:
-- May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
LIBRARY ieee, std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.all;
USE work.components.all;
-- ************************************************************************
-- Entity definition
-- Draft "generic" members
-- ************************************************************************
entity SC_SPRAM_16K_L is
generic (
WRITE_MODE : string := "NORMAL";
ADDR_WIDTH : integer := 13;
DATA_WIDTH : integer := 2;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FILE : string := "qq.dat"
);
port (
CEN : in STD_LOGIC ;
CLK : in STD_LOGIC ;
WR : in STD_LOGIC ;
CS : in STD_LOGIC_VECTOR (1 downto 0);
RST : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
AD : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end SC_SPRAM_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_SPRAM_16K_L is
component SC_BRAM_16K_L
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 1;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (DATA_WIDTH downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**ADDR_WIDTH)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to DATA_WIDTH - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + DATA_WIDTH;
end loop;
end READ_MEM_INIT_FILE;
-- Signal Declaration
signal CEN_node : STD_LOGIC := 'X';
signal CLK_node : STD_LOGIC := 'X';
signal WR_node : STD_LOGIC := 'X';
signal CS_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RST_node : STD_LOGIC := 'X';
signal DI_node : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
signal AD_node : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => '0');
signal DO_node : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
signal DI_reg : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
signal AD_reg : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => 'X');
signal EN_reg : STD_LOGIC := 'X';
signal REN_reg : STD_LOGIC := 'X';
signal GND_sig : STD_LOGIC;
signal VCC_sig : STD_LOGIC;
signal v_MEM : STD_LOGIC_VECTOR((2**ADDR_WIDTH) * DATA_WIDTH-1 downto 0) := (others => '0');
signal v_AD : integer;
-- architecture
begin
GND_sig <= '0';
VCC_sig <= '1';
CEN_node <= CEN;
CLK_node <= CLK;
WR_node <= WR;
CS_node <= CS;
RST_node <= RST;
DI_node <= DI;
AD_node <= AD;
-- DO <= DO_node;
init_process : process
variable v_INI_DONE : boolean := FALSE;
variable v_MEM_i : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
begin
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM_i);
v_INI_DONE := TRUE;
end if;
v_MEM <= v_MEM_i;
wait;
end process;
process(AD_node)
begin
if (Valid_Address(AD_node) = TRUE) then
v_AD <= CONV_INTEGER(AD_node);
end if;
end process;
-- Register DI/ AD / Enable inputs
register_inputs: process (CLK_node, RST_node)
begin
if (RST_node = '1') then
DI_reg <= (others =>'0');
AD_reg <= (others =>'0');
EN_reg <= '0';
REN_reg <= '1';
elsif (CLK_node'event and CLK_node = '1') then
if (CEN_node = '1') then
DI_reg <= DI_node;
AD_reg <= AD_node;
EN_reg <= WR_node and CS_node(0) and CS_node(1);
REN_reg <= '1';
end if;
end if;
end process register_inputs;
v_MEM_process: process (EN_reg, DI_node, v_AD, CLK_node)
begin
if (CLK_node'event and CLK_node = '1') then
if (EN_reg = '1' and CEN_node = '1') then
for i in 0 to DATA_WIDTH - 1 loop
v_MEM(v_AD*DATA_WIDTH+i) <= DI_node(i) after 1 ps;
end loop;
end if;
end if;
end process;
DO_output_process: process (RST_node, EN_reg, DO_node, CLK_node)
begin
if (RST_node = '1') then
DO <= (others => '0');
elsif (CLK_node = '1' and CEN_node = '1') then
if (EN_reg = '1') then
if (WRITE_MODE = "RD_BEFORE_WR") then
for j in 0 to DATA_WIDTH - 1 loop
DO(j) <= v_MEM(v_AD*DATA_WIDTH+j);
end loop;
else
DO <= DO_node;
end if;
else
DO <= DO_node;
end if;
end if;
end process;
-- BRAM instance for SPRAM
SPRAM_INST: SC_BRAM_16K_L
generic map(
AWRITE_MODE => WRITE_MODE,
WADDR_WIDTH_A => ADDR_WIDTH,
RADDR_WIDTH_A => ADDR_WIDTH,
WADDR_WIDTH_B => ADDR_WIDTH,
RADDR_WIDTH_B => ADDR_WIDTH,
WDATA_WIDTH_A => DATA_WIDTH,
RDATA_WIDTH_A => DATA_WIDTH,
WDATA_WIDTH_B => DATA_WIDTH,
RDATA_WIDTH_B => DATA_WIDTH,
ARRAY_SIZE => open,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => AD_reg,
WEA => EN_reg,
WDA => DI_reg,
RADA => AD_reg,
REA => REN_reg,
RDA => DO_node,
WADB => AD_reg,
WEB => GND_sig,
WDB => DI_reg,
RADB => AD_reg,
REB => GND_sig,
RDB => open
);
end LATTICE_BEHAV;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
entity fifo_dc is
generic (
module_type : string := "FIFO_DC";
module_width : integer := 1;
module_widthu : integer := 1;
module_numwords : integer := 2;
module_amfull_flag : integer := 1;
module_amempty_flag : integer := 1;
module_hint : string := "UNUSED");
port (
Data : in std_logic_vector (module_width-1 downto 0);
WrClock : in std_logic;
WrEn : in std_logic;
RdClock : in std_logic;
RdEn : in std_logic;
Reset : in std_logic;
RPReset : in std_logic;
Q : out std_logic_vector (module_width-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
AlmostFull : out std_logic;
AlmostEmpty : out std_logic);
end fifo_dc;
architecture fun_simulation of fifo_dc is
component SC_FIFO_16K_L
generic (
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 9;
RDATA_WIDTH : integer := 32;
ALMOST_FULL_X : integer := 1;
ALMOST_EMPTY_Y : integer := 1;
MEM_INIT_FLAG : integer := 0;
TERMINAL_COUNT : integer := 511;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end component;
signal Rst, FullIn, EmptyIn : std_logic;
begin
Rst <= '1';
FullIn <= '0';
EmptyIn <= '1';
SC_FIFO_inst : SC_FIFO_16K_L
generic map (
WADDR_WIDTH => module_widthu,
WDATA_WIDTH => module_width,
RADDR_WIDTH => module_widthu,
RDATA_WIDTH => module_width,
ALMOST_FULL_X => module_amfull_flag,
ALMOST_EMPTY_Y => module_amempty_flag,
MEM_INIT_FLAG => 0,
TERMINAL_COUNT => module_numwords - 1,
MEM_INIT_FILE => open )
port map (
WE => WrEn,
WCLK => WrClock,
RST => Reset,
RPRST => RPReset,
RE => RdEn,
RCLK => RdClock,
FULLIN => FullIn,
EMPTYIN => EmptyIn,
DI => Data,
FULL => Full,
EMPTY => Empty,
AMFULL => AlmostFull,
AMEMPTY => AlmostEmpty,
DO => Q
);
end;library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
entity fifo_dcx is
generic (
module_type : string := "FIFO_DCX";
module_widthw : integer := 1;
module_widthr : integer := 1;
module_widthuw : integer := 1;
module_widthur : integer := 1;
module_numwordsw : integer := 2;
module_numwordsr : integer := 2;
module_amfull_flag : integer := 1;
module_amempty_flag : integer := 1;
module_hint : string := "UNUSED");
port (
Data : in std_logic_vector (module_widthw-1 downto 0);
WrClock : in std_logic;
WrEn : in std_logic;
RdClock : in std_logic;
RdEn : in std_logic;
Reset : in std_logic;
RPReset : in std_logic;
Q : out std_logic_vector (module_widthr-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
AlmostFull : out std_logic;
AlmostEmpty : out std_logic);
end fifo_dcx;
architecture fun_simulation of fifo_dcx is
component SC_FIFO_V2_16K_L
generic (
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 9;
RDATA_WIDTH : integer := 32;
ALMOST_FULL_X : integer := 1;
ALMOST_EMPTY_Y : integer := 1;
MEM_INIT_FLAG : integer := 0;
TERMINAL_COUNT : integer := 511;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end component;
signal FullIn, EmptyIn : std_logic;
begin
FullIn <= '0';
EmptyIn <= '1';
SC_FIFO_inst : SC_FIFO_V2_16K_L
generic map (
WADDR_WIDTH => module_widthuw,
WDATA_WIDTH => module_widthw,
RADDR_WIDTH => module_widthur,
RDATA_WIDTH => module_widthr,
ALMOST_FULL_X => module_amfull_flag,
ALMOST_EMPTY_Y => module_amempty_flag,
MEM_INIT_FLAG => 0,
TERMINAL_COUNT => module_numwordsw - 1,
MEM_INIT_FILE => open )
port map (
WE => WrEn,
WCLK => WrClock,
RST => Reset,
RPRST => RPReset,
RE => RdEn,
RCLK => RdClock,
FULLIN => FullIn,
EMPTYIN => EmptyIn,
DI => Data,
FULL => Full,
EMPTY => Empty,
AMFULL => AlmostFull,
AMEMPTY => AlmostEmpty,
DO => Q
);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use work.components.all;
entity ram_dp is
generic(
module_type : string := "RAM_DP";
module_widthw : integer := 1;
module_widthr : integer := 1;
module_numwordsw : integer := 1;
module_widthadw : integer := 1;
module_widthadr : integer := 1;
module_numwordsr : integer := 1;
module_indata : string := "REGISTERED";
module_outdata : string := "UNREGISTERED";
module_addressw_control : string := "REGISTERED";
module_addressr_control : string := "REGISTERED";
module_gsr : string := "DISABLED";
module_hint : string := "UNUSED";
module_init_file : string := "");
port(
Data : in std_logic_vector (module_widthw-1 downto 0);
WrAddress : in std_logic_vector (module_widthadw-1 downto 0);
RdAddress : in std_logic_vector (module_widthadr-1 downto 0);
WrClock : in std_logic;
WrClockEn : in std_logic;
RdClock : in std_logic;
RdClockEn : in std_logic;
WE : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector (module_widthr-1 downto 0));
end ram_dp;
architecture fun_simulation of ram_dp is
component SC_PDPRAM_16K_L
generic (
WADDR_WIDTH : integer := 13;
WDATA_WIDTH : integer := 2;
RADDR_WIDTH : integer := 13;
RDATA_WIDTH : integer := 2;
ARRAY_SIZE : integer := 511;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WCEN : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
WE : in STD_LOGIC ;
WCS : in STD_LOGIC_VECTOR (1 downto 0);
RCLK : in STD_LOGIC;
RCEN : in STD_LOGIC;
RST : in STD_LOGIC ;
WD : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
WAD : in STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
RAD : in STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
RD : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end component;
signal cs : std_logic_vector ( 1 downto 0);
signal Q_K : std_logic_vector (module_widthr-1 downto 0);
signal Q_K_reg : std_logic_vector (module_widthr-1 downto 0);
CONSTANT module_init_flag : integer := init_flag(module_init_file);
begin
cs <= "11";
OutRegister : process(RdClock, Reset)
begin
if (Reset = '1') then
Q_K_reg <= (others => '0');
elsif (RdClock'EVENT and RdClock = '1') then
if (RdClockEn = '1') then
Q_K_reg <= Q_K;
elsif (RdClockEn /= '0') then
Q_K_reg <= (others => 'X');
end if;
end if;
end process;
SelectOut : process (Q_K , Q_K_reg)
begin
if(module_outdata = "UNREGISTERED" and module_addressr_control = "REGISTERED") then
Q <= Q_K;
elsif(module_outdata = "REGISTERED" and module_addressr_control = "REGISTERED") then
Q <= Q_K_reg;
elsif(module_indata = "UNREGISTERED") then
assert false report "Error: module_indata should be REGISTERED" severity ERROR;
elsif(module_addressw_control = "UNREGISTERED") then
assert false report "Error: module_addressw_control should be REGISTERED" severity ERROR;
elsif(module_addressr_control = "UNREGISTERED") then
assert false report "Error: module_addressr_control should be REGISTERED" severity ERROR;
end if;
end process;
PDPRAM_inst : SC_PDPRAM_16K_L
generic map(
WADDR_WIDTH => module_widthadw,
WDATA_WIDTH => module_widthw,
RADDR_WIDTH => module_widthadr,
RDATA_WIDTH => module_widthr,
MEM_INIT_FLAG => module_init_flag,
ARRAY_SIZE => module_numwordsw*module_widthw,
MEM_INIT_FILE => module_init_file)
port map(
WCEN => WrClockEn,
WCLK => WrClock,
WE => WE,
WCS => cs,
RCLK => RdClock,
RCEN => RdClockEn,
RST => Reset,
WD => Data,
WAD => WrAddress,
RAD => RdAddress,
RD => Q_K
);
end;library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use work.components.all;
entity ram_dp_true is
generic (
module_type : string := "RAM_DP_TRUE";
module_widtha : positive;
module_widthada : positive;
module_numwordsa : positive;
module_widthb : positive;
module_widthadb : positive;
module_numwordsb : positive;
module_indata : string :="REGISTERED";
module_outdata : string :="UNREGISTERED";
module_addressa_control : string :="REGISTERED";
module_addressb_control : string :="REGISTERED";
module_init_file : string := "";
module_hint : string :="UNUSED";
module_gsr : string := "DISABLED";
module_writemode_a : string := "NORMAL";
module_writemode_b : string := "NORMAL");
port (
DataInA : in std_logic_vector(module_widtha-1 downto 0);
AddressA : in std_logic_vector(module_widthada-1 downto 0);
DataInB : in std_logic_vector(module_widthb-1 downto 0);
AddressB : in std_logic_vector(module_widthadb-1 downto 0);
ClockA : in std_logic := '0';
ClockEnA : in std_logic := '0';
ClockB : in std_logic := '0';
ClockEnB : in std_logic := '0';
WrA : in std_logic;
WrB : in std_logic;
ResetA : in std_logic;
ResetB : in std_logic;
QA : out std_logic_vector(module_widtha-1 downto 0);
QB : out std_logic_vector(module_widthb-1 downto 0));
end ram_dp_true;
architecture fun_simulation of ram_dp_true is
component SC_DPRAM_16K_L
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
ADDR_WIDTH_A : integer := 13;
DATA_WIDTH_A : integer := 2;
ADDR_WIDTH_B : integer := 14;
DATA_WIDTH_B : integer := 1;
MEM_INIT_FLAG : integer := 0;
ARRAY_SIZE : integer := 511;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
CENA : in STD_LOGIC ;
CLKA : in STD_LOGIC ;
WRA : in STD_LOGIC ;
CSA : in STD_LOGIC_VECTOR (1 downto 0);
RSTA : in STD_LOGIC ;
DIA : in STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
ADA : in STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
DOA : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
CENB : in STD_LOGIC ;
CLKB : in STD_LOGIC ;
WRB : in STD_LOGIC ;
CSB : in STD_LOGIC_VECTOR (1 downto 0);
RSTB : in STD_LOGIC ;
DIB : in STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
ADB : in STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
DOB : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
);
end component;
signal CS : std_logic_vector ( 1 downto 0);
signal QA_int, QA_int_reg : std_logic_vector(module_widtha-1 downto 0);
signal QB_int, QB_int_reg : std_logic_vector(module_widthb-1 downto 0);
CONSTANT module_init_flag : integer := init_flag(module_init_file);
begin
CS <= "11";
OutRegisterA : process(ClockA, ResetA)
begin
if(ResetA = '1') then QA_int_reg <= (others => '0');
elsif (ClockA'EVENT and ClockA = '1') then
if (ClockEnA = '1') then
QA_int_reg <= QA_int;
elsif (ClockEnA /= '0') then
QA_int_reg <= (others => 'X');
end if;
end if;
end process;
OutRegisterB : process(ClockB, ResetB)
begin
if(ResetB = '1') then QB_int_reg <= (others => '0');
elsif (ClockB'EVENT and ClockB = '1') then
if (ClockEnB = '1') then
QB_int_reg <= QB_int;
elsif (ClockEnB /= '0') then
QB_int_reg <= (others => 'X');
end if;
end if;
end process;
SelectA : process (QA_int , QA_int_reg)
begin
if(module_outdata = "UNREGISTERED" and module_addressa_control = "REGISTERED") then
QA <= QA_int;
elsif(module_outdata = "REGISTERED" and module_addressa_control = "REGISTERED") then
QA <= QA_int_reg;
elsif(module_indata = "UNREGISTERED") then
assert false report "Error: module_indata should be REGISTERED" severity ERROR;
elsif(module_addressa_control = "UNREGISTERED") then
assert false report "Error: module_addressa_control should be REGISTERED" severity ERROR;
end if;
end process;
SelectB : process (QB_int , QB_int_reg)
begin
if(module_outdata = "UNREGISTERED" and module_addressb_control = "REGISTERED") then
QB <= QB_int;
elsif(module_outdata = "REGISTERED" and module_addressb_control = "REGISTERED") then
QB <= QB_int_reg;
elsif(module_addressa_control = "UNREGISTERED") then
assert false report "Error: module_addressa_control should be REGISTERED" severity ERROR;
end if;
end process;
RAM_DP_INST : SC_DPRAM_16K_L
generic map(
ADDR_WIDTH_A => module_widthada,
DATA_WIDTH_A => module_widtha,
ADDR_WIDTH_B => module_widthadb,
DATA_WIDTH_B => module_widthb,
MEM_INIT_FLAG => module_init_flag,
ARRAY_SIZE => module_numwordsa*module_widtha,
MEM_INIT_FILE => module_init_file,
AWRITE_MODE => module_writemode_a,
BWRITE_MODE => module_writemode_b
)
port map (
CENA => ClockEnA,
CLKA => ClockA,
WRA => WrA,
CSA => CS,
RSTA => ResetA,
DIA => DataInA,
ADA => AddressA,
DOA => QA_int,
CENB => ClockEnB,
CLKB => ClockB,
WRB => WrB,
CSB => CS,
RSTB => ResetB,
DIB => DataInB,
ADB => AddressB,
DOB => QB_int
);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use work.components.all;
entity ram_dq is
generic(
module_type : string := "RAM_DQ";
module_width : integer := 1;
module_numwords : integer := 1;
module_widthad : integer := 1;
module_indata : string := "REGISTERED";
module_outdata : string := "UNREGISTERED";
module_address_control : string := "REGISTERED";
module_init_file : string := "";
module_hint : string := "UNUSED";
module_gsr : string := "DISABLED";
module_writemode : string := "NORMAL");
port(
Data : in std_logic_vector (module_width-1 downto 0);
Address : in std_logic_vector (module_widthad-1 downto 0);
Clock : in std_logic;
ClockEn : in std_logic;
WE : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector (module_width-1 downto 0));
end ram_dq;
architecture fun_simulation of ram_dq is
component SC_SPRAM_16K_L
generic (
WRITE_MODE : string := "NORMAL";
ADDR_WIDTH : integer := 13;
DATA_WIDTH : integer := 2;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 511;
MEM_INIT_FILE : string := "qq.dat"
);
port (
CEN : in STD_LOGIC ;
CLK : in STD_LOGIC ;
WR : in STD_LOGIC ;
CS : in STD_LOGIC_VECTOR (1 downto 0);
RST : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
AD : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
signal cs : std_logic_vector (1 downto 0);
signal Q_K : std_logic_vector (module_width-1 downto 0);
signal Q_K_reg : std_logic_vector (module_width-1 downto 0);
CONSTANT module_init_flag : integer := init_flag(module_init_file);
begin
cs <= "11";
OutRegister : process(Clock, Reset)
begin
if (Reset = '1') then
Q_K_reg <= (others => '0');
elsif (Clock'EVENT and Clock = '1') then
if (ClockEn = '1') then
Q_K_reg <= Q_K;
elsif (ClockEn /= '0') then
Q_K_reg <= (others => 'X');
end if;
end if;
end process;
SelectOut : process (Q_K , Q_K_reg)
begin
if(module_outdata = "UNREGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K;
elsif(module_outdata = "REGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K_reg;
elsif(module_indata = "UNREGISTERED") then
assert false report "Error: module_indata should be REGISTERED" severity ERROR;
elsif(module_address_control = "UNREGISTERED") then
assert false report "Error: module_address_control should be REGISTERED" severity ERROR;
end if;
end process;
SPRAM_inst : SC_SPRAM_16K_L
generic map (
ADDR_WIDTH => module_widthad,
DATA_WIDTH => module_width,
MEM_INIT_FLAG => module_init_flag,
ARRAY_SIZE => module_numwords * module_width,
MEM_INIT_FILE => module_init_file,
WRITE_MODE => module_writemode)
port map (
CEN => ClockEn,
CLK => Clock,
WR => WE,
CS => cs,
RST => Reset,
DI => Data,
AD => Address,
DO => Q_K
);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
entity rom is
generic (
module_type : string := "ROM";
module_width : integer := 1;
module_numwords : integer := 1;
module_widthad : integer := 1;
module_outdata : string := "REGISTERED";
module_address_control : string := "REGISTERED";
module_init_file : string := "init_file";
module_gsr : string := "DISABLED";
module_hint : string := "UNUSED");
port (
Address : in std_logic_vector (module_widthad-1 downto 0);
OutClock : in std_logic;
OutClockEn : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector (module_width-1 downto 0));
end rom;
architecture fun_simulation of rom is
component SC_SPRAM_16K_L
generic (
ADDR_WIDTH : integer := 13;
DATA_WIDTH : integer := 2;
ARRAY_SIZE : integer := 511;
MEM_INIT_FLAG : integer := 1;
MEM_INIT_FILE : string := "qq.dat"
);
port (
CEN : in STD_LOGIC ;
CLK : in STD_LOGIC ;
WR : in STD_LOGIC ;
CS : in STD_LOGIC_VECTOR (1 downto 0);
RST : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
AD : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
signal cs : std_logic_vector ( 1 downto 0);
signal DI_sig : std_logic_vector (module_width-1 downto 0);
signal WE_sig : std_logic;
signal Q_K : std_logic_vector (module_width-1 downto 0);
signal Q_K_reg : std_logic_vector (module_width-1 downto 0);
begin
cs <= "11";
WE_sig <= '0';
OutRegister : process(OutClock, Reset)
begin
if (Reset = '1') then
Q_K_reg <= (others => '0');
elsif (OutClock'EVENT and OutClock = '1') then
if(OutClockEn = '1') then
Q_K_reg <= Q_K;
elsif(OutClockEn /= '0') then
Q_K_reg <= (others => 'X' );
end if;
end if;
end process;
SelectOut : process (Q_K , Q_K_reg)
begin
if(module_outdata = "UNREGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K;
elsif(module_outdata = "REGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K_reg;
elsif(module_address_control = "UNREGISTERED") then
assert false report "Error: module_address_control should be REGISTERED" severity ERROR;
end if;
end process;
SPRAM_inst : SC_SPRAM_16K_L
generic map(
ADDR_WIDTH => module_widthad,
DATA_WIDTH => module_width,
MEM_INIT_FLAG => 1,
ARRAY_SIZE => module_numwords * module_width,
MEM_INIT_FILE => module_init_file)
port map(
CEN => OutClockEn,
CLK => OutClock,
WR => WE_sig,
CS => cs,
RST => Reset,
DI => DI_sig,
AD => Address,
DO => Q_K
);
end;
|
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A.
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 1-408-826-6000 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
--
-- Simulation Library File for EC/XP
--
-- $Header: G:\\CVS_REPOSITORY\\CVS_MACROS/LEON3SDE/ALTERA/grlib-eval-1.0.4/lib/tech/ec/ec/ORCA_L.vhd,v 1.1 2005/12/06 13:00:23 tame Exp $
--
library std;
use std.textio.all;
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- ************************************************************************
-- Entity definition
-- "generic" members
-- ************************************************************************
entity SC_BRAM_16K_L is
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 262144;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := ""
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end SC_BRAM_16K_L;
-- ************************************************************************
-- Architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_BRAM_16K_L is
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (WDATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to WDATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + WDATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------
--------- Local signals used to propagate input wire delay ---------------
signal WADA_node : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node : std_logic := 'X';
signal WDA_node : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node : std_logic := 'X';
signal RDA_node : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RDA_temp : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal WADB_node : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node : std_logic := 'X';
signal WDB_node : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node : std_logic := 'X';
signal RDB_node : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RDB_temp : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
-- architecture
begin
WADA_node <= WADA;
WEA_node <= WEA;
WDA_node <= WDA;
RADA_node <= RADA;
REA_node <= REA;
RDA <= RDA_TEMP;
WADB_node <= WADB;
WEB_node <= WEB;
WDB_node <= WDB;
RADB_node <= RADB;
REB_node <= REB;
RDB <= RDB_TEMP;
RDB_process: process(RDB_node, WEB_node)
begin
if (WEB_node = '1') then
if (BWRITE_MODE = "WRITETHROUGH") then
RDB_temp <= RDB_node;
elsif (BWRITE_MODE = "NORMAL") then
RDB_temp <= RDB_temp;
end if;
else
RDB_temp <= RDB_node;
end if;
end process;
RDA_process: process(RDA_node, WEA_node)
begin
if (WEA_node = '1') then
if (AWRITE_MODE = "WRITETHROUGH") then
RDA_temp <= RDA_node;
elsif (AWRITE_MODE = "NORMAL") then
RDA_temp <= RDA_temp;
end if;
else
RDA_temp <= RDA_node;
end if;
end process;
-----------------------------------------
--------- Behavior process -------------
-----------------------------------------
KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
--TSPEC: A note about sram initial values and rom mode:
-- If the user does not provide any values, ... default 0
-- for all ram locations in JECED
--QQ 7_17 variable v_MEM : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
variable v_MEM : std_logic_vector(ARRAY_SIZE*WDATA_WIDTH_A + WDATA_WIDTH_A - 1 downto 0) := ( others => '0' );
variable v_INI_DONE : boolean := FALSE;
variable v_WADDR_A : integer;
variable v_RADDR_A : integer;
variable v_WADDR_B : integer;
variable v_RADDR_B : integer;
variable v_WADDRA_Valid_Flag : boolean := TRUE;
variable v_WADDRB_Valid_Flag : boolean := TRUE;
variable v_RADDRA_Valid_Flag : boolean := TRUE;
variable v_RADDRB_Valid_Flag : boolean := TRUE;
begin -- Process
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
v_INI_DONE := TRUE;
end if;
-- Address Check
v_WADDRA_Valid_Flag := Valid_Address(WADA_node);
v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
v_RADDRA_Valid_Flag := Valid_Address(RADA_node);
v_RADDRB_Valid_Flag := Valid_Address(RADB_node);
if ( v_WADDRA_Valid_Flag = TRUE ) then
v_WADDR_A := CONV_INTEGER(WADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_WADDRB_Valid_Flag = TRUE ) then
v_WADDR_B := CONV_INTEGER(WADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressB of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRA_Valid_Flag = TRUE ) then
v_RADDR_A := CONV_INTEGER(RADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRB_Valid_Flag = TRUE ) then
v_RADDR_B := CONV_INTEGER(RADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressB of Port contains invalid bit!"
-- severity warning;
end if;
-- CHECK Operation
if (WEA = '1' and WEB = '1' and
not(
(v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B)
or
(v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
)
) then
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity warning;
end if;
-- MEM Operation
if (WEA_node = '1') then
v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
end if;
if (WEB_node = '1') then
v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
end if;
if (REA_node = '1') then
RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
-- else
-- RDA_node <= ( others => 'X');
end if;
if (REB_node = '1') then
RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
-- else
-- RDB_node <= ( others => 'X');
end if;
end process KERNEL_BEHAV;
end LATTICE_BEHAV;
-- ************************************************************************
--
-- Block Memory: Behavioral Model
-- The kernel of other RAM applications
-- ************************************************************************
--
-- Filename: SC_BLOCK_RAM_L.vhd
-- Description: BRAM behavioral model.
-- ************************************************************************
library std;
use std.textio.all;
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- ************************************************************************
-- Entity definition
-- "generic" members
-- ************************************************************************
entity SC_BRAM_16K_L_SYNC is
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 262144;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := ""
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
WCLK : in STD_LOGIC;
RCLK : in STD_LOGIC
);
end SC_BRAM_16K_L_SYNC;
-- ************************************************************************
-- Architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_BRAM_16K_L_SYNC is
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (WDATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to WDATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + WDATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------
--------- Local signals used to propagate input wire delay ---------------
signal WADA_node : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node : std_logic := 'X';
signal WDA_node : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node : std_logic := 'X';
signal RDA_node : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal WADB_node : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node : std_logic := 'X';
signal WDB_node : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node : std_logic := 'X';
signal RDB_node : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal WCLK_node : std_logic := 'X';
signal RCLK_node : std_logic := 'X';
-- architecture
begin
WADA_node <= WADA;
WEA_node <= WEA;
WDA_node <= WDA;
RADA_node <= RADA;
REA_node <= REA;
RDA <= RDA_node;
WADB_node <= WADB;
WEB_node <= WEB;
WDB_node <= WDB;
RADB_node <= RADB;
REB_node <= REB;
RDB <= RDB_node;
WCLK_node <= WCLK;
RCLK_node <= RCLK;
-----------------------------------------
--------- Behavior process -------------
-----------------------------------------
--KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
KERNEL_BEHAV : process( WCLK_node, RCLK_node)
--TSPEC: A note about sram initial values and rom mode:
-- If the user does not provide any values, ... default 0
-- for all ram locations in JECED
variable v_MEM : std_logic_vector(ARRAY_SIZE*WDATA_WIDTH_A - 1 downto 0) := ( others => '0' );
variable v_INI_DONE : boolean := FALSE;
variable v_WADDR_A : integer;
variable v_RADDR_A : integer;
variable v_WADDR_B : integer;
variable v_RADDR_B : integer;
variable v_WADDRA_Valid_Flag : boolean := TRUE;
variable v_WADDRB_Valid_Flag : boolean := TRUE;
variable v_RADDRA_Valid_Flag : boolean := TRUE;
variable v_RADDRB_Valid_Flag : boolean := TRUE;
begin -- Process
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
v_INI_DONE := TRUE;
end if;
-- Address Check
v_WADDRA_Valid_Flag := Valid_Address(WADA_node);
v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
v_RADDRA_Valid_Flag := Valid_Address(RADA_node);
v_RADDRB_Valid_Flag := Valid_Address(RADB_node);
if ( v_WADDRA_Valid_Flag = TRUE ) then
v_WADDR_A := CONV_INTEGER(WADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_WADDRB_Valid_Flag = TRUE ) then
v_WADDR_B := CONV_INTEGER(WADB_node);
else
-- assert (Now = 0 ps)
-- report "Write AddressB of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRA_Valid_Flag = TRUE ) then
v_RADDR_A := CONV_INTEGER(RADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRB_Valid_Flag = TRUE ) then
v_RADDR_B := CONV_INTEGER(RADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressB of Port contains invalid bit!"
-- severity warning;
end if;
-- CHECK Operation
if (WEA = '1' and WEB = '1' and
not(
(v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B)
or
(v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
)
) then
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity warning;
end if;
-- MEM Operation
if (WEA_node = '1' and WCLK_node'event and WCLK_node = '1' ) then
v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
end if;
if (WEB_node = '1' and WCLK_node'event and WCLK_node = '1') then
v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
end if;
if (REA_node = '1' and RCLK_node'event and RCLK_node = '1') then
RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
-- else
-- RDA_node <= ( others => 'X');
end if;
if (REB_node = '1' and RCLK_node'event and RCLK_node = '1') then
RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
-- else
-- RDB_node <= ( others => 'X');
end if;
end process KERNEL_BEHAV;
end LATTICE_BEHAV;
library std;
use std.textio.all;
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- ************************************************************************
-- Entity definition
-- "generic" members
-- ************************************************************************
entity SC_BRAM_PDP_16K_L is
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 262144;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := ""
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end SC_BRAM_PDP_16K_L;
-- ************************************************************************
-- Architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_BRAM_PDP_16K_L is
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (WDATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to WDATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + WDATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------
--------- Local signals used to propagate input wire delay ---------------
signal WADA_node : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node : std_logic := 'X';
signal WDA_node : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node : std_logic := 'X';
signal RDA_node : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal WADB_node : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node : std_logic := 'X';
signal WDB_node : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node : std_logic := 'X';
signal RDB_node : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
-- architecture
begin
WADA_node <= WADA;
WEA_node <= WEA;
WDA_node <= WDA;
RADA_node <= RADA;
REA_node <= REA;
RDA <= RDA_node;
WADB_node <= WADB;
WEB_node <= WEB;
WDB_node <= WDB;
RADB_node <= RADB;
REB_node <= REB;
RDB <= RDB_node;
-----------------------------------------
--------- Behavior process -------------
-----------------------------------------
KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
--TSPEC: A note about sram initial values and rom mode:
-- If the user does not provide any values, ... default 0
-- for all ram locations in JECED
variable v_MEM : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
variable v_INI_DONE : boolean := FALSE;
variable v_WADDR_A : integer;
variable v_RADDR_A : integer;
variable v_WADDR_B : integer;
variable v_RADDR_B : integer;
variable v_WADDRA_Valid_Flag : boolean := TRUE;
variable v_WADDRB_Valid_Flag : boolean := TRUE;
variable v_RADDRA_Valid_Flag : boolean := TRUE;
variable v_RADDRB_Valid_Flag : boolean := TRUE;
begin -- Process
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
v_INI_DONE := TRUE;
end if;
-- Address Check
v_WADDRA_Valid_Flag := Valid_Address(WADA_node);
v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
v_RADDRA_Valid_Flag := Valid_Address(RADA_node);
v_RADDRB_Valid_Flag := Valid_Address(RADB_node);
if ( v_WADDRA_Valid_Flag = TRUE ) then
v_WADDR_A := CONV_INTEGER(WADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_WADDRB_Valid_Flag = TRUE ) then
v_WADDR_B := CONV_INTEGER(WADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressB of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRA_Valid_Flag = TRUE ) then
v_RADDR_A := CONV_INTEGER(RADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRB_Valid_Flag = TRUE ) then
v_RADDR_B := CONV_INTEGER(RADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressB of Port contains invalid bit!"
-- severity warning;
end if;
-- CHECK Operation
if (WEA = '1' and WEB = '1' and
not(
(v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B)
or
(v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
)
) then
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity warning;
end if;
-- MEM Operation
if (WEA_node = '1') then
v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
end if;
if (WEB_node = '1') then
v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
end if;
if (REA_node = '1') then
RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
-- else
-- RDA_node <= ( others => 'X');
end if;
if (REB_node = '1') then
RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
-- else
-- RDB_node <= ( others => 'X');
end if;
end process KERNEL_BEHAV;
end LATTICE_BEHAV;
---************* SC_FIFO_L **************************
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity READ_POINTER_CTRL is
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end READ_POINTER_CTRL;
architecture LATTICE_BEHAV of READ_POINTER_CTRL is
signal s_READ_POINTER : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
begin
READ_POINTER <= s_READ_POINTER;
process (GLOBAL_RST, RESET_RP, READ_EN, READ_CLK)
variable v_READ_POINTER: STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' or RESET_RP = '1' then
s_READ_POINTER <= (others => '0');
elsif (READ_CLK'EVENT and READ_CLK = '1') then
if (READ_EN = '1' and EMPTY_FLAG = '1') then
v_READ_POINTER := s_READ_POINTER + '1';
else
v_READ_POINTER := s_READ_POINTER;
end if;
if (v_READ_POINTER = TERMINAL_COUNT + 1) then
s_READ_POINTER <= (others => '0');
else
s_READ_POINTER <= v_READ_POINTER;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO COMPONENTS WRITE_POINTER_CTRL
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity WRITE_POINTER_CTRL is
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end WRITE_POINTER_CTRL;
architecture LATTICE_BEHAV of WRITE_POINTER_CTRL is
signal s_WRITE_POINTER : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
WRITE_POINTER <= s_WRITE_POINTER;
process (GLOBAL_RST, WRITE_EN, WRITE_CLK)
variable v_WRITE_POINTER: STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' then
s_WRITE_POINTER <= (others => '0');
elsif (WRITE_CLK'EVENT and WRITE_CLK = '1') then
if (WRITE_EN = '1' and FULL_FLAG /= '1') then
v_WRITE_POINTER := s_WRITE_POINTER + '1';
else
v_WRITE_POINTER := s_WRITE_POINTER ;
end if;
if (v_WRITE_POINTER = TERMINAL_COUNT + 1) then
s_WRITE_POINTER <= (others => '0');
else
s_WRITE_POINTER <= v_WRITE_POINTER;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO COMPONENTS FLAG LOGIC
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity FLAG_LOGIC is
generic (
WPOINTER_WIDTH : integer := 9;
RPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0) := (others => '0');--QQ
R_POINTER : in STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
W_POINTER : in STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0');
GLOBAL_RST : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end FLAG_LOGIC;
architecture LATTICE_BEHAV of FLAG_LOGIC is
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Pointer (
IN_ADDR : in STD_LOGIC_VECTOR
) return BOOLEAN is
variable v_Valid_Flag : BOOLEAN := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Pointer;
--------------------------------------------------------------------------
-- Function: Calculate_Offset
-- Description:
--------------------------------------------------------------------------
function Calculate_Offset (
IN_TC : in STD_LOGIC_VECTOR;
TC_LENGTH: in INTEGER
) return STD_LOGIC_VECTOR is
variable vTC_FULL: STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '1');
variable vTC_TEMP: STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '0');
variable vOFFSET : STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '0');
begin
vTC_TEMP := IN_TC;
vOFFSET := vTC_FULL-vTC_TEMP;
return vOFFSET;
end Calculate_Offset;
begin
--------------------------------------------------------------------------
-- Function: Main Process
-- Description:
--------------------------------------------------------------------------
FULL_AMFULL: process (GLOBAL_RST, WRITE_EN, WRITE_CLK, W_POINTER, R_POINTER)
variable v_WP_Valid_Flag : boolean := TRUE;
variable v_RP_Valid_Flag : boolean := TRUE;
--variable v_WP_Check_FULL_TMP : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_WP_Check_AMFL_TMP : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
variable v_WP_Check_AMFL_TMP1 : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
variable v_WP_Check_FULL : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
variable v_WP_Check_AMFL : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
begin
v_WP_Valid_Flag := Valid_Pointer(W_POINTER);
v_RP_Valid_Flag := Valid_Pointer(R_POINTER);
if( v_WP_Valid_Flag = TRUE) then
v_WP_Check_AMFL_TMP := W_POINTER + AMFULL_X + 1;
end if;
v_WP_Check_AMFL_TMP1 := v_WP_Check_AMFL_TMP + Calculate_Offset(TERMINAL_COUNT, WPOINTER_WIDTH);
if ( v_WP_Valid_Flag = TRUE and W_POINTER = TERMINAL_COUNT ) then
v_WP_Check_FULL := (others => '0');
elsif( v_WP_Valid_Flag = TRUE ) then
v_WP_Check_FULL := W_POINTER + 1;
end if;
if GLOBAL_RST = '1' then
FULL_D <= '0';
AMFULL_D <= '0';
elsif( v_WP_Valid_Flag = TRUE and v_RP_Valid_Flag = TRUE) then
if R_POINTER = v_WP_Check_FULL then
FULL_D <= '1';
else
FULL_D <= '0';
end if;
if (W_POINTER > R_POINTER) then
if (v_WP_Check_AMFL_TMP1 < W_POINTER) then
if v_WP_Check_AMFL_TMP1 >= R_POINTER then
AMFULL_D <= '1';
else
AMFULL_D <= '0';
end if;
else
AMFULL_D <= '0';
end if;
elsif (W_POINTER < R_POINTER) then
if (v_WP_Check_AMFL_TMP1 < W_POINTER) then
AMFULL_D <= '1';
elsif (v_WP_Check_AMFL_TMP >= R_POINTER) then
AMFULL_D <= '1';
else
AMFULL_D <= '0';
end if;
end if;
end if;
end process FULL_AMFULL;
EMPTY_AMEMPTY: process (GLOBAL_RST, READ_EN, READ_CLK, W_POINTER, R_POINTER)
variable v_WP_Valid_Flag : boolean := TRUE;
variable v_RP_Valid_Flag : boolean := TRUE;
variable v_RP_Check_EMPT_TMP : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_RP_Check_AMET_TMP : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_RP_Check_AMET_TMP1 : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
--variable v_RP_Check_EMPT : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_RP_Check_AMET : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
begin
v_WP_Valid_Flag := Valid_Pointer(W_POINTER);
v_RP_Valid_Flag := Valid_Pointer(R_POINTER);
if( v_RP_Valid_Flag = TRUE and v_WP_Valid_Flag = TRUE) then
v_RP_Check_AMET_TMP := R_POINTER + AMEMPTY_Y ; -- Different from TSPEC QQ 07 17,2002
end if;
v_RP_Check_AMET_TMP1 := v_RP_Check_AMET_TMP + Calculate_Offset(TERMINAL_COUNT, RPOINTER_WIDTH);
if GLOBAL_RST = '1' then
EMPTY_D <= '0';
AMEMPTY_D <= '0';
elsif( v_WP_Valid_Flag = TRUE and v_RP_Valid_Flag = TRUE) then
if R_POINTER = W_POINTER then -- Different from TSPEC QQ 07 17,2002
EMPTY_D <= '0';
else
EMPTY_D <= '1';
end if;
if (W_POINTER < R_POINTER) then
if (v_RP_Check_AMET_TMP1 < R_POINTER) then
v_RP_Check_AMET := v_RP_Check_AMET_TMP + Calculate_Offset(TERMINAL_COUNT, RPOINTER_WIDTH);
if v_RP_Check_AMET >= W_POINTER then
AMEMPTY_D <= '0';
else
AMEMPTY_D <= '1';
end if;
else
AMEMPTY_D <= '1';
end if;
elsif (W_POINTER > R_POINTER) then
if (v_RP_Check_AMET_TMP1 < R_POINTER) then
AMEMPTY_D <= '0';
elsif (v_RP_Check_AMET_TMP >= W_POINTER) then
AMEMPTY_D <= '0';
else
AMEMPTY_D <= '1';
end if;
elsif (W_POINTER = R_POINTER) then
AMEMPTY_D <= '0';
end if;
end if;
end process EMPTY_AMEMPTY;
end LATTICE_BEHAV;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
---USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
--LIBRARY SC_LIB;
--USE SC_LIB.SC_FIFO_COMPS.ALL;
entity SC_FIFO_16K_L is
generic (
TERMINAL_COUNT : integer := 511; --QQ: Word number < 2**WADDR_WIDTH
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 9;
RDATA_WIDTH : integer := 32;
ALMOST_FULL_X : integer := 1;
ALMOST_EMPTY_Y : integer := 1;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end SC_FIFO_16K_L;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_FIFO_16K_L is
---------------------------------------------------------
-- Function: TO_STD_VECTOR
---------------------------------------------------------
function TO_STD_VECTOR ( INPUT_STRING : string; INPUT_LENGTH: integer)
return std_logic_vector is
variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
variable vTRANS: string(INPUT_LENGTH downto 1) := (others => '0');
begin
vTRANS := INPUT_STRING;
for i in INPUT_LENGTH downto 1 loop
if (vTRANS(i) = '1') then
vDATA_STD_VEC(i-1) := '1';
elsif ( vTRANS(i) ='0') then
vDATA_STD_VEC(i-1) := '0';
end if;
end loop;
return vDATA_STD_VEC;
end TO_STD_VECTOR;
---------------------------------------------------------
-- Function: INT_TO_VEC
---------------------------------------------------------
function INT_TO_VEC ( INPUT_INT : integer; INPUT_LENGTH: integer)
return std_logic_vector is
variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
variable vTRANS: integer := 0;
variable vQUOTIENT: integer := 0;
begin
vQUOTIENT := INPUT_INT;
for i in 0 to INPUT_LENGTH -1 loop
vTRANS := 0;
while vQUOTIENT >1 loop
vQUOTIENT := vQUOTIENT - 2;
vTRANS := vTRANS + 1;
end loop;
case vQUOTIENT is
when 1 =>
vDATA_STD_VEC(i) := '1';
when 0 =>
vDATA_STD_VEC(i) := '0';
when others =>
null;
end case;
vQUOTIENT := vTRANS;
end loop;
return vDATA_STD_VEC;
end INT_TO_VEC;
---------------------------------------------------------
-- Components Definition
---------------------------------------------------------
component SC_BRAM_16K_L_SYNC
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
WCLK : in STD_LOGIC;
RCLK : in STD_LOGIC
);
end component;
component READ_POINTER_CTRL
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end component;
component WRITE_POINTER_CTRL
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end component;
component FLAG_LOGIC
generic (
WPOINTER_WIDTH : integer := 9;
RPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
R_POINTER : in STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0);
W_POINTER : in STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0);
GLOBAL_RST : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end component;
-- Signal Declaration
signal WE_node : STD_LOGIC := '0';
signal WCLK_node : STD_LOGIC := '0';
signal RST_node : STD_LOGIC := '0';
signal RPRST_node : STD_LOGIC := '0';
signal RE_node : STD_LOGIC := '0';
signal RCLK_node : STD_LOGIC := '0';
signal FULLIN_node : STD_LOGIC := '0';
signal EMPTYIN_node : STD_LOGIC := '0';
signal DI_node : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => '0');
signal DI_reg : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => '0');
signal FULLIN_reg : STD_LOGIC := '0';
signal EMPTYIN_reg : STD_LOGIC := '0';
signal FULL_node : STD_LOGIC := '0';
signal EMPTY_node : STD_LOGIC := '0';
signal AMFULL_node : STD_LOGIC := '0';
signal AMEMPTY_node : STD_LOGIC := '0';
signal DO_node : STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => '0');
signal TC_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
signal FULL_reg : STD_LOGIC := '0';
signal EMPTY_reg : STD_LOGIC := '0';
signal AMFULL_reg : STD_LOGIC := '0';
signal AMEMPTY_reg : STD_LOGIC := '0';
signal RP_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => '0');
signal WP_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
signal GND_sig : STD_LOGIC := '0';
-- architecture
begin
GND_sig <= '0';
WE_node <= WE and not(FULL_node);
WCLK_node <= WCLK;
RST_node <= RST;
RPRST_node <= RPRST;
RE_node <= RE and EMPTY_node;
RCLK_node <= RCLK;
FULLIN_node <= FULLIN;
EMPTYIN_node <= EMPTYIN;
DI_node <= DI;
--TC_node <= TO_STD_VECTOR(TERMINAL_COUNT,WADDR_WIDTH);
TC_node <= INT_TO_VEC(TERMINAL_COUNT,WADDR_WIDTH);
--FULL <= FULL_node;
FULL <= FULL_node when (RE_node = '0') else FULL_reg;
--AMFULL <= AMFULL_node;
AMFULL <= AMFULL_node when (RE_node = '0') else AMFULL_reg;
EMPTY <= not EMPTY_node;
AMEMPTY <= not AMEMPTY_node;
DO <= DO_node;
-- Register Port DI inputs
register_DI_inputs: process (RST_node, WCLK_node)
begin
if (RST_node = '1') then
DI_reg <= (others =>'0');
elsif (WCLK_node'event and WCLK_node = '1') then
if (WE_node = '1') then
DI_reg <= DI_node after 1 ps;
end if;
end if;
end process register_DI_inputs;
-- Register flag inputs
register_flag_inputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULLIN_reg <= '0';
EMPTYIN_reg <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
-- WE_reg <= WE_node and not (FULL_reg); --QQ
if (WE_node = '1') then
FULLIN_reg <= FULLIN_node;
end if;
end if;
if (RCLK_node'event and RCLK_node = '1') then
-- RE_reg <= RE_node and EMPTY_reg; --QQ
if (RE_node = '1') then
EMPTYIN_reg <= EMPTYIN_node;
end if;
end if;
end if;
end process register_flag_inputs;
-- Register flag outputs
register_flag_outputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULL_node <= '0';
AMFULL_node <= '0';
EMPTY_node <= '0';
AMEMPTY_node <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
FULL_node <= FULL_reg;
AMFULL_node <= AMFULL_reg;
end if;
if (RCLK_node'event and RCLK_node = '1') then
EMPTY_node <= EMPTY_reg;
AMEMPTY_node <= AMEMPTY_reg;
end if;
end if;
end process register_flag_outputs;
-- READ_POINTER_CTRL instance for FIFO
FIFO_RPC_INST: READ_POINTER_CTRL
generic map (
RPOINTER_WIDTH => RADDR_WIDTH
)
port map (
TERMINAL_COUNT => TC_node,
GLOBAL_RST => RST_node,
RESET_RP => RPRST_node,
READ_EN => RE_node,
READ_CLK => RCLK_node,
EMPTY_FLAG => EMPTY_reg,
READ_POINTER => RP_node
);
-- WRITE_POINTER_CTRL instance for FIFO
FIFO_WPC_INST: WRITE_POINTER_CTRL
generic map (
WPOINTER_WIDTH => WADDR_WIDTH,
WDATA_WIDTH => WDATA_WIDTH
)
port map (
TERMINAL_COUNT => TC_node,
GLOBAL_RST => RST_node,
WRITE_EN => WE_node,
WRITE_CLK => WCLK_node,
FULL_FLAG => FULL_reg,
WRITE_POINTER => WP_node
);
-- FLAG_LOGIC instance for FIFO
FIFO_FL_INST: FLAG_LOGIC
generic map (
WPOINTER_WIDTH => WADDR_WIDTH,
RPOINTER_WIDTH => RADDR_WIDTH,
WDATA_WIDTH => WDATA_WIDTH,
RDATA_WIDTH => RDATA_WIDTH,
AMFULL_X => ALMOST_FULL_X,
AMEMPTY_Y => ALMOST_EMPTY_Y
)
port map(
TERMINAL_COUNT => TC_node,
R_POINTER => RP_node,
W_POINTER => WP_node,
GLOBAL_RST => RST_node,
READ_EN => RE_node,
READ_CLK => RCLK_node,
WRITE_EN => WE_node,
WRITE_CLK => WCLK_node,
FULL_D => FULL_reg,
EMPTY_D => EMPTY_reg,
AMFULL_D => AMFULL_reg,
AMEMPTY_D => AMEMPTY_reg
);
-- BRAM instance for FIFO
FIFO_BRAM_INST: SC_BRAM_16K_L_SYNC
generic map(
WADDR_WIDTH_A => WADDR_WIDTH,
RADDR_WIDTH_A => RADDR_WIDTH,
WADDR_WIDTH_B => WADDR_WIDTH,
RADDR_WIDTH_B => RADDR_WIDTH,
WDATA_WIDTH_A => WDATA_WIDTH,
RDATA_WIDTH_A => RDATA_WIDTH,
WDATA_WIDTH_B => WDATA_WIDTH,
RDATA_WIDTH_B => RDATA_WIDTH,
ARRAY_SIZE => open,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => WP_node,
WEA => WE_node,
WDA => DI_node,
RADA => RP_node,
REA => RE_node,
RDA => DO_node,
WADB => WP_node,
WEB => GND_sig,
WDB => DI_node,
RADB => RP_node,
REB => GND_sig,
RDB => open,
WCLK => WCLK_node,
RCLK => RCLK_node
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- FIFO V2: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_FIFO_V2.vhd
-- Description: FIFO behavioral model.
-- ************************************************************************
-- FIFO COMPONENTS READ_POINTER_CTRL_V2
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity READ_POINTER_CTRL_V2 is
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end READ_POINTER_CTRL_V2;
architecture LATTICE_BEHAV of READ_POINTER_CTRL_V2 is
signal s_READ_POINTER : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
begin
READ_POINTER <= s_READ_POINTER;
process (GLOBAL_RST, RESET_RP, READ_EN, READ_CLK)
variable v_READ_POINTER: STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' or RESET_RP = '1' then
s_READ_POINTER <= TERMINAL_COUNT;
elsif (READ_CLK'EVENT and READ_CLK = '1') then
if (READ_EN = '1' and EMPTY_FLAG = '1') then
v_READ_POINTER := s_READ_POINTER + '1';
else
v_READ_POINTER := s_READ_POINTER;
end if;
if (v_READ_POINTER = TERMINAL_COUNT + 1) then
s_READ_POINTER <= (others => '0');
else
s_READ_POINTER <= v_READ_POINTER;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO COMPONENTS WRITE_POINTER_CTRL_V2
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity WRITE_POINTER_CTRL_V2 is
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end WRITE_POINTER_CTRL_V2;
architecture LATTICE_BEHAV of WRITE_POINTER_CTRL_V2 is
signal s_WRITE_POINTER : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
WRITE_POINTER <= s_WRITE_POINTER;
process (GLOBAL_RST, WRITE_EN, WRITE_CLK)
variable v_WRITE_POINTER: STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' then
s_WRITE_POINTER <= TERMINAL_COUNT ;
elsif (WRITE_CLK'EVENT and WRITE_CLK = '1') then
if (WRITE_EN = '1' and FULL_FLAG /= '1') then
v_WRITE_POINTER := s_WRITE_POINTER + '1';
else
v_WRITE_POINTER := s_WRITE_POINTER ;
end if;
if (v_WRITE_POINTER = TERMINAL_COUNT + 1) then
s_WRITE_POINTER <= (others => '0');
else
s_WRITE_POINTER <= v_WRITE_POINTER ;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO V2 COMPONENTS FLAG LOGIC
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
entity FLAG_LOGIC_V2 is
generic (
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
GLOBAL_RST : in STD_LOGIC ;
FIFO_CAP : in integer ;
FIFO_PTR : in integer ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end FLAG_LOGIC_V2;
architecture LATTICE_BEHAV of FLAG_LOGIC_V2 is
begin
--------------------------------------------------------------------------
-- Function: Main Process
-- Description:
--------------------------------------------------------------------------
FULL_AMFULL_EMPTY_AMEMPTY: process (GLOBAL_RST, FIFO_CAP, FIFO_PTR)
begin
if GLOBAL_RST = '1' then
FULL_D <= '0';
AMFULL_D <= '0';
EMPTY_D <= '0';
AMEMPTY_D <= '0';
else
if (FIFO_CAP - FIFO_PTR < WDATA_WIDTH) then
FULL_D <= '1';
else
FULL_D <= '0';
end if;
if (FIFO_CAP - FIFO_PTR < WDATA_WIDTH + AMFULL_X * WDATA_WIDTH) then
AMFULL_D <= '1';
else
AMFULL_D <= '0';
end if;
if (FIFO_PTR < RDATA_WIDTH) then
EMPTY_D <= '0';
else
EMPTY_D <= '1';
end if;
if (FIFO_PTR < RDATA_WIDTH + AMEMPTY_Y * RDATA_WIDTH) then
AMEMPTY_D <= '0';
else
AMEMPTY_D <= '1';
end if;
end if;
end process FULL_AMFULL_EMPTY_AMEMPTY;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO V2 Main Body
-- READ_POINTER_CTRL_V2
-- WRITE_POINTER_CTRL_V2
-- FLAG_LOGIC_V2
-- SC_BRAM_16K
-- ************************************************************************
-- ************************************************************************
-- Top Design Entity definition
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity SC_FIFO_V2_16K_L is
generic (
TERMINAL_COUNT : integer := 511; --QQ: Word number < 2**WADDR_WIDTH
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 8;
RDATA_WIDTH : integer := 64;
ALMOST_FULL_X : integer := 2;
ALMOST_EMPTY_Y : integer := 2;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end SC_FIFO_V2_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_FIFO_V2_16K_L is
---------------------------------------------------------
-- Function: TO_STD_VECTOR
---------------------------------------------------------
function TO_STD_VECTOR ( INPUT_STRING : string; INPUT_LENGTH: integer)
return std_logic_vector is
variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
variable vTRANS: string(INPUT_LENGTH downto 1) := (others => '0');
begin
vTRANS := INPUT_STRING;
for i in INPUT_LENGTH downto 1 loop
if (vTRANS(i) = '1') then
vDATA_STD_VEC(i-1) := '1';
elsif ( vTRANS(i) ='0') then
vDATA_STD_VEC(i-1) := '0';
end if;
end loop;
return vDATA_STD_VEC;
end TO_STD_VECTOR;
---------------------------------------------------------
-- Components Definition
---------------------------------------------------------
component SC_BRAM_16K_L
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
component READ_POINTER_CTRL_V2
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end component;
component WRITE_POINTER_CTRL_V2
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end component;
component FLAG_LOGIC_V2
generic (
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
GLOBAL_RST : in STD_LOGIC ;
FIFO_CAP : in integer ;
FIFO_PTR : in integer ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end component;
-- Signal Declaration
signal WE_node : STD_LOGIC := 'X';
signal WCLK_node : STD_LOGIC := 'X';
signal RST_node : STD_LOGIC := 'X';
signal RPRST_node : STD_LOGIC := 'X';
signal RE_node : STD_LOGIC := 'X';
signal RCLK_node : STD_LOGIC := 'X';
signal FULLIN_node : STD_LOGIC := 'X';
signal EMPTYIN_node : STD_LOGIC := 'X';
signal DI_node : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal DI_reg : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal WE_reg : STD_LOGIC := 'X';
signal RE_reg : STD_LOGIC := 'X';
signal FULLIN_reg : STD_LOGIC := 'X';
signal EMPTYIN_reg : STD_LOGIC := 'X';
signal FULL_node : STD_LOGIC := 'X';
signal EMPTY_node : STD_LOGIC := 'X';
signal AMFULL_node : STD_LOGIC := 'X';
signal AMEMPTY_node : STD_LOGIC := 'X';
signal DO_node : STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');
signal TC_W_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
signal TC_R_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal FULL_reg : STD_LOGIC := 'X';
signal EMPTY_reg : STD_LOGIC := 'X';
signal AMFULL_reg : STD_LOGIC := 'X';
signal AMEMPTY_reg : STD_LOGIC := 'X';
signal RP_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal WP_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
signal GND_sig : STD_LOGIC := 'X';
--QQ FIFOV2
signal FIFO_capacity : integer := 0;
signal FIFO_pointer : integer := 0;
-- architecture
begin
FIFO_capacity <= (TERMINAL_COUNT + 1) * WDATA_WIDTH;
GND_sig <= '0';
WE_node <= WE and not (FULL_node);
WCLK_node <= WCLK;
RST_node <= RST;
RPRST_node <= RPRST;
RE_node <= RE;
RCLK_node <= RCLK;
FULLIN_node <= FULLIN;
EMPTYIN_node <= EMPTYIN;
DI_node <= DI;
TC_W_node <= CONV_STD_LOGIC_VECTOR(TERMINAL_COUNT,WADDR_WIDTH);
TC_R_node <= CONV_STD_LOGIC_VECTOR((TERMINAL_COUNT+1)*(WDATA_WIDTH/RDATA_WIDTH)-1,RADDR_WIDTH);
--FULL <= FULL_node;
FULL <= FULL_node when (RE_node = '0') else FULL_reg;
--AMFULL <= AMFULL_node;
AMFULL <= AMFULL_node when (RE_node = '0') else AMFULL_reg;
EMPTY <= not EMPTY_node;
AMEMPTY <= not AMEMPTY_node;
DO <= DO_node;
-- Register Port DI inputs
register_DI_inputs: process (RST_node, WCLK_node)
begin
if (RST_node = '1') then
DI_reg <= (others =>'0');
elsif (WCLK_node'event and WCLK_node = '1') then
if (WE_node = '1') then
DI_reg <= DI_node after 1 ps;
end if;
end if;
end process register_DI_inputs;
-- Register flag inputs
register_flag_inputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULLIN_reg <= '0';
EMPTYIN_reg <= '0';
WE_reg <= '0';
RE_reg <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
WE_reg <= WE_node and not FULL_reg; --Fix DTS14659
--WE_reg <= WE_node;
if (WE_node = '1') then
FULLIN_reg <= FULLIN_node;
end if;
end if;
if (RCLK_node'event and RCLK_node = '1') then
RE_reg <= RE_node and EMPTY_reg;
if (RE_node = '1') then
EMPTYIN_reg <= EMPTYIN_node;
end if;
end if;
end if;
end process register_flag_inputs;
-- Register flag outputs
register_flag_outputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULL_node <= '0';
AMFULL_node <= '0';
EMPTY_node <= '0';
AMEMPTY_node <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
FULL_node <= FULL_reg;
AMFULL_node <= AMFULL_reg;
end if;
if (RCLK_node'event and RCLK_node = '1') then
EMPTY_node <= EMPTY_reg;
AMEMPTY_node <= AMEMPTY_reg;
end if;
end if;
end process register_flag_outputs;
-- Set FIFO_pointer
FIFO_CAP_POINTER: process ( RP_node, WP_node, RST_node, RPRST_node)
begin
--WP ++, FIFO_CAP --
if (WP_node'event and RP_node'event) then
FIFO_pointer <= FIFO_pointer + WDATA_WIDTH - RDATA_WIDTH;
elsif(WP_node'event) then
FIFO_pointer <= FIFO_pointer + WDATA_WIDTH;
end if;
--RPRST Active, FIFO_CAP --
--RP ++, FIFO_CAP ++
if (RST_node = '1') then
FIFO_pointer <= 0;
elsif (RPRST_node = '1') then
FIFO_pointer <= (CONV_INTEGER(WP_node)+1) * WDATA_WIDTH;
elsif (RP_node'event and not(WP_node'event)) then
FIFO_pointer <= FIFO_pointer - RDATA_WIDTH;
end if;
end process FIFO_CAP_POINTER;
-- READ_POINTER_CTRL_V2 instance for FIFO
FIFO_RPC_INST: READ_POINTER_CTRL_V2
generic map (
RPOINTER_WIDTH => RADDR_WIDTH
)
port map (
TERMINAL_COUNT => TC_R_node,
GLOBAL_RST => RST_node,
RESET_RP => RPRST_node,
READ_EN => RE_node,
READ_CLK => RCLK_node,
EMPTY_FLAG => EMPTY_reg,
READ_POINTER => RP_node
);
-- WRITE_POINTER_CTRL_V2 instance for FIFO
FIFO_WPC_INST: WRITE_POINTER_CTRL_V2
generic map (
WPOINTER_WIDTH => WADDR_WIDTH,
WDATA_WIDTH => WDATA_WIDTH
)
port map (
TERMINAL_COUNT => TC_W_node,
GLOBAL_RST => RST_node,
WRITE_EN => WE_node,
WRITE_CLK => WCLK_node,
FULL_FLAG => FULL_reg,
WRITE_POINTER => WP_node
);
-- FLAG_LOGIC_V2 instance for FIFO
FIFO_FL_INST: FLAG_LOGIC_V2
generic map (
WDATA_WIDTH => WDATA_WIDTH,
RDATA_WIDTH => RDATA_WIDTH,
AMFULL_X => ALMOST_FULL_X,
AMEMPTY_Y => ALMOST_EMPTY_Y
)
port map(
GLOBAL_RST => RST_node,
FIFO_CAP => FIFO_capacity,
FIFO_PTR => FIFO_pointer,
FULL_D => FULL_reg,
EMPTY_D => EMPTY_reg,
AMFULL_D => AMFULL_reg,
AMEMPTY_D => AMEMPTY_reg
);
-- BRAM instance for FIFO
FIFO_BRAM_INST: SC_BRAM_16K_L
generic map(
WADDR_WIDTH_A => WADDR_WIDTH,
RADDR_WIDTH_A => RADDR_WIDTH,
WADDR_WIDTH_B => WADDR_WIDTH,
RADDR_WIDTH_B => RADDR_WIDTH,
WDATA_WIDTH_A => WDATA_WIDTH,
RDATA_WIDTH_A => RDATA_WIDTH,
WDATA_WIDTH_B => WDATA_WIDTH,
RDATA_WIDTH_B => RDATA_WIDTH,
ARRAY_SIZE => open,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => WP_node,
WEA => WE_reg,
WDA => DI_reg,
RADA => RP_node,
REA => RE_reg,
RDA => DO_node,
WADB => WP_node,
WEB => GND_sig,
WDB => DI_reg,
RADB => RP_node,
REB => GND_sig,
RDB => open
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- DPRAM: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_DP_RAM.vhd
-- Description: Single Port BRAM behavioral model.
-- History:
-- May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
LIBRARY ieee, std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.all;
USE work.components.all;
-- ************************************************************************
-- Entity definition
-- Draft "generic" members
-- ************************************************************************
entity SC_DPRAM_16K_L is
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
ADDR_WIDTH_A : integer := 13;
DATA_WIDTH_A : integer := 2;
ADDR_WIDTH_B : integer := 14;
DATA_WIDTH_B : integer := 1;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
CENA : in STD_LOGIC ;
CLKA : in STD_LOGIC ;
WRA : in STD_LOGIC ;
CSA : in STD_LOGIC_VECTOR (1 downto 0);
RSTA : in STD_LOGIC ;
DIA : in STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
ADA : in STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
DOA : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
CENB : in STD_LOGIC ;
CLKB : in STD_LOGIC ;
WRB : in STD_LOGIC ;
CSB : in STD_LOGIC_VECTOR (1 downto 0);
RSTB : in STD_LOGIC ;
DIB : in STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
ADB : in STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
DOB : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
);
end SC_DPRAM_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_DPRAM_16K_L is
component SC_BRAM_16K_L
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (DATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**ADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to DATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + DATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
-- Signal Declaration
signal CENA_node : STD_LOGIC := 'X';
signal CLKA_node : STD_LOGIC := 'X';
signal WRA_node : STD_LOGIC := 'X';
signal CSA_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RSTA_node : STD_LOGIC := 'X';
signal DIA_node : STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
signal ADA_node : STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0) := (others => '0');
signal DOA_node : STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
signal DIA_reg : STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
signal ADA_reg : STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0) := (others => 'X');
signal ENA_reg : STD_LOGIC := 'X';
signal RENA_reg : STD_LOGIC := 'X';
signal CENB_node : STD_LOGIC := 'X';
signal CLKB_node : STD_LOGIC := 'X';
signal WRB_node : STD_LOGIC := 'X';
signal CSB_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RSTB_node : STD_LOGIC := 'X';
signal DIB_node : STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
signal ADB_node : STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0) := (others => 'X');
signal DOB_node : STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
signal DIB_reg : STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
signal ADB_reg : STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0) := (others => 'X');
signal ENB_reg : STD_LOGIC := 'X';
signal RENB_reg : STD_LOGIC := 'X';
signal v_MEM : STD_LOGIC_VECTOR(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
signal v_ADA : INTEGER;
signal v_ADB : INTEGER;
-- architecture
begin
CENA_node <= CENA;
CLKA_node <= CLKA;
WRA_node <= WRA;
CSA_node <= CSA;
RSTA_node <= RSTA;
DIA_node <= DIA;
ADA_node <= ADA;
-- DOA <= DOA_node;
CENB_node <= CENB;
CLKB_node <= CLKB;
WRB_node <= WRB;
CSB_node <= CSB;
RSTB_node <= RSTB;
DIB_node <= DIB;
ADB_node <= ADB;
-- DOB <= DOB_node;
init_process : process
variable v_INI_DONE : boolean := FALSE;
variable v_MEM_i : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
begin
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM_i);
v_INI_DONE := TRUE;
end if;
v_MEM <= v_MEM_i;
wait;
end process;
process(ADA_node, ADB_node)
begin
if (Valid_Address(ADA_node) = TRUE) then
v_ADA <= CONV_INTEGER(ADA_node);
end if;
if (Valid_Address(ADB_node) = TRUE) then
v_ADB <= CONV_INTEGER(ADB_node);
end if;
end process;
-- Register Port A DI/ AD / Enable inputs
register_A_inputs: process (CLKA_node, RSTA_node)
begin
if (RSTA_node = '1') then
DIA_reg <= (others =>'0');
ADA_reg <= (others =>'0');
ENA_reg <= '0';
RENA_reg <= '1';
elsif (CLKA_node'event and CLKA_node = '1') then
if (CENA_node = '1') then
DIA_reg <= DIA_node;
ADA_reg <= ADA_node;
ENA_reg <= WRA_node and CSA_node(0) and CSA_node(1);
RENA_reg <= '1';
end if;
end if;
end process register_A_inputs;
-- Register Port B DI/ AD / Enable inputs
register_B_inputs: process (CLKB_node, RSTB_node)
begin
if (RSTB_node = '1') then
DIB_reg <= (others =>'0');
ADB_reg <= (others =>'0');
ENB_reg <= '0';
RENB_reg <= '1';
elsif (CLKB_node'event and CLKB_node = '1') then
if (CENB_node = '1') then
DIB_reg <= DIB_node;
ADB_reg <= ADB_node;
ENB_reg <= WRB_node and CSB_node(0) and CSB_node(1);
RENB_reg <= '1';
end if;
end if;
end process register_B_inputs;
v_MEM_process: process (CLKA_node, CLKB_node)
begin
if (ENA_reg = '1' and CENA_node = '1') then
if (CLKA_node'event and CLKA_node = '1') then
for i in 0 to DATA_WIDTH_A - 1 loop
v_MEM(v_ADA*DATA_WIDTH_A+i) <= DIA_node(i) after 1 ps;
end loop;
end if;
end if;
if (ENB_reg = '1' and CENB_node = '1') then
if (CLKB_node'event and CLKB_node = '1') then
for i in 0 to DATA_WIDTH_B - 1 loop
v_MEM(v_ADB*DATA_WIDTH_B+i) <= DIB_node(i) after 1 ps;
end loop;
end if;
end if;
end process;
DOA_output_process: process (RSTA_node, ENA_reg, CENA_node, DOA_node, CLKA_node)
begin
if (RSTA_node = '1') then
DOA <= (others => '0');
elsif (CLKA_node = '1' and CENA_node = '1') then
if (ENA_reg = '1') then
if (AWRITE_MODE = "RD_BEFORE_WR") then
for j in 0 to DATA_WIDTH_A - 1 loop
DOA(j) <= v_MEM(v_ADA*DATA_WIDTH_A+j);
end loop;
else
DOA <= DOA_node;
end if;
else
DOA <= DOA_node;
end if;
end if;
end process;
DOB_output_process: process (RSTB_node, ENB_reg, CENB_node, DOB_node, CLKB_node)
begin
if (RSTB_node = '1') then
DOB <= (others => '0');
elsif (CLKB_node = '1' and CENB_node = '1') then
if (ENB_reg = '1') then
if (BWRITE_MODE = "RD_BEFORE_WR") then
for j in 0 to DATA_WIDTH_B - 1 loop
DOB(j) <= v_MEM(v_ADB*DATA_WIDTH_B+j);
end loop;
else
DOB <= DOB_node;
end if;
else
DOB <= DOB_node;
end if;
end if;
end process;
-- BRAM instance for SPRAM
DPRAM_INST: SC_BRAM_16K_L
generic map(
AWRITE_MODE => AWRITE_MODE,
BWRITE_MODE => BWRITE_MODE,
WADDR_WIDTH_A => ADDR_WIDTH_A,
RADDR_WIDTH_A => ADDR_WIDTH_A,
WADDR_WIDTH_B => ADDR_WIDTH_B,
RADDR_WIDTH_B => ADDR_WIDTH_B,
WDATA_WIDTH_A => DATA_WIDTH_A,
RDATA_WIDTH_A => DATA_WIDTH_A,
WDATA_WIDTH_B => DATA_WIDTH_B,
RDATA_WIDTH_B => DATA_WIDTH_B,
ARRAY_SIZE => ARRAY_SIZE,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => ADA_reg,
WEA => ENA_reg,
WDA => DIA_reg,
RADA => ADA_reg,
REA => RENA_reg,
RDA => DOA_node,
WADB => ADB_reg,
WEB => ENB_reg,
WDB => DIB_reg,
RADB => ADB_reg,
REB => RENB_reg,
RDB => DOB_node
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- PseudoDPRAM: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_PDP_RAM.vhd
-- Description: Pseudo Dual Port BRAM behavioral model.
-- History:
-- May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
-- ************************************************************************
-- Entity definition
-- Draft "generic" members
-- ************************************************************************
entity SC_PDPRAM_16K_L is
generic (
WADDR_WIDTH : integer := 13;
WDATA_WIDTH : integer := 2;
RADDR_WIDTH : integer := 13;
RDATA_WIDTH : integer := 2;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WCEN : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
WE : in STD_LOGIC ;
WCS : in STD_LOGIC_VECTOR (1 downto 0);
RCLK : in STD_LOGIC;
RCEN : in STD_LOGIC;
RST : in STD_LOGIC ;
WD : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
WAD : in STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
RAD : in STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
RD : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end SC_PDPRAM_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_PDPRAM_16K_L is
component SC_BRAM_16K_L
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
-- Signal Declaration
signal WCEN_node : STD_LOGIC := 'X';
signal WCLK_node : STD_LOGIC := 'X';
signal WE_node : STD_LOGIC := 'X';
signal WCS_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RCEN_node : STD_LOGIC := 'X';
signal RCLK_node : STD_LOGIC := 'X';
signal RST_node : STD_LOGIC := 'X';
signal WD_node : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal WAD_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
signal RD_node : STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');
signal RAD_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal WD_reg : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal WAD_reg : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
signal RAD_reg : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal EN_reg : STD_LOGIC := 'X';
signal REN_reg : STD_LOGIC := 'X';
signal GND_sig : STD_LOGIC;
signal VCC_sig : STD_LOGIC;
-- architecture
begin
GND_sig <= '0';
VCC_sig <= '1';
WCEN_node <= WCEN;
WCLK_node <= WCLK;
WE_node <= WE;
WCS_node <= WCS;
RCEN_node <= RCEN;
RCLK_node <= RCLK;
RST_node <= RST;
WD_node <= WD;
WAD_node <= WAD;
RAD_node <= RAD;
-- RD <= RD_node;
RD_output : process (RD_node, RST_node)
begin
if (RST_node = '1') then
RD <= (others => '0');
else
RD <= RD_node;
end if;
end process;
-- Register WD/WAD/ Enable inputs
register_write_inputs: process (WCLK_node, RST_node)
begin
if (RST_node = '1') then
WD_reg <= (others =>'0');
WAD_reg <= (others =>'0');
EN_reg <= '0';
REN_reg <= '1';
elsif (WCLK_node'event and WCLK_node = '1') then
if (WCEN_node = '1') then
WD_reg <= WD_node;
WAD_reg <= WAD_node;
EN_reg <= WE_node and WCS_node(0) and WCS_node(1);
REN_reg <= '1';
end if;
end if;
end process register_write_inputs;
-- Register RAD inputs
register_read_inputs: process (RCLK_node, RST_node)
begin
if (RST_node = '1') then
RAD_reg <= (others =>'0');
elsif (RCLK_node'event and RCLK_node = '1') then
if (RCEN_node = '1') then
RAD_reg <= RAD_node;
end if;
end if;
end process register_read_inputs;
-- BRAM instance for SPRAM
PDPRAM_INST: SC_BRAM_16K_L
generic map(
WADDR_WIDTH_A => WADDR_WIDTH,
RADDR_WIDTH_A => RADDR_WIDTH,
WADDR_WIDTH_B => WADDR_WIDTH,
RADDR_WIDTH_B => RADDR_WIDTH,
WDATA_WIDTH_A => WDATA_WIDTH,
RDATA_WIDTH_A => RDATA_WIDTH,
WDATA_WIDTH_B => WDATA_WIDTH,
RDATA_WIDTH_B => RDATA_WIDTH,
ARRAY_SIZE => ARRAY_SIZE,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => WAD_reg,
WEA => EN_reg,
WDA => WD_reg,
RADA => RAD_reg,
REA => REN_reg,
RDA => RD_node,
WADB => WAD_reg,
WEB => GND_sig,
WDB => WD_reg,
RADB => RAD_reg,
REB => GND_sig,
RDB => open
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- SPRAM: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_SP_RAM.vhd
-- Description: Single Port BRAM behavioral model.
-- History:
-- May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
LIBRARY ieee, std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.all;
USE work.components.all;
-- ************************************************************************
-- Entity definition
-- Draft "generic" members
-- ************************************************************************
entity SC_SPRAM_16K_L is
generic (
WRITE_MODE : string := "NORMAL";
ADDR_WIDTH : integer := 13;
DATA_WIDTH : integer := 2;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FILE : string := "qq.dat"
);
port (
CEN : in STD_LOGIC ;
CLK : in STD_LOGIC ;
WR : in STD_LOGIC ;
CS : in STD_LOGIC_VECTOR (1 downto 0);
RST : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
AD : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end SC_SPRAM_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_SPRAM_16K_L is
component SC_BRAM_16K_L
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 1;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (DATA_WIDTH downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**ADDR_WIDTH)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to DATA_WIDTH - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + DATA_WIDTH;
end loop;
end READ_MEM_INIT_FILE;
-- Signal Declaration
signal CEN_node : STD_LOGIC := 'X';
signal CLK_node : STD_LOGIC := 'X';
signal WR_node : STD_LOGIC := 'X';
signal CS_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RST_node : STD_LOGIC := 'X';
signal DI_node : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
signal AD_node : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => '0');
signal DO_node : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
signal DI_reg : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
signal AD_reg : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => 'X');
signal EN_reg : STD_LOGIC := 'X';
signal REN_reg : STD_LOGIC := 'X';
signal GND_sig : STD_LOGIC;
signal VCC_sig : STD_LOGIC;
signal v_MEM : STD_LOGIC_VECTOR((2**ADDR_WIDTH) * DATA_WIDTH-1 downto 0) := (others => '0');
signal v_AD : integer;
-- architecture
begin
GND_sig <= '0';
VCC_sig <= '1';
CEN_node <= CEN;
CLK_node <= CLK;
WR_node <= WR;
CS_node <= CS;
RST_node <= RST;
DI_node <= DI;
AD_node <= AD;
-- DO <= DO_node;
init_process : process
variable v_INI_DONE : boolean := FALSE;
variable v_MEM_i : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
begin
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM_i);
v_INI_DONE := TRUE;
end if;
v_MEM <= v_MEM_i;
wait;
end process;
process(AD_node)
begin
if (Valid_Address(AD_node) = TRUE) then
v_AD <= CONV_INTEGER(AD_node);
end if;
end process;
-- Register DI/ AD / Enable inputs
register_inputs: process (CLK_node, RST_node)
begin
if (RST_node = '1') then
DI_reg <= (others =>'0');
AD_reg <= (others =>'0');
EN_reg <= '0';
REN_reg <= '1';
elsif (CLK_node'event and CLK_node = '1') then
if (CEN_node = '1') then
DI_reg <= DI_node;
AD_reg <= AD_node;
EN_reg <= WR_node and CS_node(0) and CS_node(1);
REN_reg <= '1';
end if;
end if;
end process register_inputs;
v_MEM_process: process (EN_reg, DI_node, v_AD, CLK_node)
begin
if (CLK_node'event and CLK_node = '1') then
if (EN_reg = '1' and CEN_node = '1') then
for i in 0 to DATA_WIDTH - 1 loop
v_MEM(v_AD*DATA_WIDTH+i) <= DI_node(i) after 1 ps;
end loop;
end if;
end if;
end process;
DO_output_process: process (RST_node, EN_reg, DO_node, CLK_node)
begin
if (RST_node = '1') then
DO <= (others => '0');
elsif (CLK_node = '1' and CEN_node = '1') then
if (EN_reg = '1') then
if (WRITE_MODE = "RD_BEFORE_WR") then
for j in 0 to DATA_WIDTH - 1 loop
DO(j) <= v_MEM(v_AD*DATA_WIDTH+j);
end loop;
else
DO <= DO_node;
end if;
else
DO <= DO_node;
end if;
end if;
end process;
-- BRAM instance for SPRAM
SPRAM_INST: SC_BRAM_16K_L
generic map(
AWRITE_MODE => WRITE_MODE,
WADDR_WIDTH_A => ADDR_WIDTH,
RADDR_WIDTH_A => ADDR_WIDTH,
WADDR_WIDTH_B => ADDR_WIDTH,
RADDR_WIDTH_B => ADDR_WIDTH,
WDATA_WIDTH_A => DATA_WIDTH,
RDATA_WIDTH_A => DATA_WIDTH,
WDATA_WIDTH_B => DATA_WIDTH,
RDATA_WIDTH_B => DATA_WIDTH,
ARRAY_SIZE => open,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => AD_reg,
WEA => EN_reg,
WDA => DI_reg,
RADA => AD_reg,
REA => REN_reg,
RDA => DO_node,
WADB => AD_reg,
WEB => GND_sig,
WDB => DI_reg,
RADB => AD_reg,
REB => GND_sig,
RDB => open
);
end LATTICE_BEHAV;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
entity fifo_dc is
generic (
module_type : string := "FIFO_DC";
module_width : integer := 1;
module_widthu : integer := 1;
module_numwords : integer := 2;
module_amfull_flag : integer := 1;
module_amempty_flag : integer := 1;
module_hint : string := "UNUSED");
port (
Data : in std_logic_vector (module_width-1 downto 0);
WrClock : in std_logic;
WrEn : in std_logic;
RdClock : in std_logic;
RdEn : in std_logic;
Reset : in std_logic;
RPReset : in std_logic;
Q : out std_logic_vector (module_width-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
AlmostFull : out std_logic;
AlmostEmpty : out std_logic);
end fifo_dc;
architecture fun_simulation of fifo_dc is
component SC_FIFO_16K_L
generic (
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 9;
RDATA_WIDTH : integer := 32;
ALMOST_FULL_X : integer := 1;
ALMOST_EMPTY_Y : integer := 1;
MEM_INIT_FLAG : integer := 0;
TERMINAL_COUNT : integer := 511;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end component;
signal Rst, FullIn, EmptyIn : std_logic;
begin
Rst <= '1';
FullIn <= '0';
EmptyIn <= '1';
SC_FIFO_inst : SC_FIFO_16K_L
generic map (
WADDR_WIDTH => module_widthu,
WDATA_WIDTH => module_width,
RADDR_WIDTH => module_widthu,
RDATA_WIDTH => module_width,
ALMOST_FULL_X => module_amfull_flag,
ALMOST_EMPTY_Y => module_amempty_flag,
MEM_INIT_FLAG => 0,
TERMINAL_COUNT => module_numwords - 1,
MEM_INIT_FILE => open )
port map (
WE => WrEn,
WCLK => WrClock,
RST => Reset,
RPRST => RPReset,
RE => RdEn,
RCLK => RdClock,
FULLIN => FullIn,
EMPTYIN => EmptyIn,
DI => Data,
FULL => Full,
EMPTY => Empty,
AMFULL => AlmostFull,
AMEMPTY => AlmostEmpty,
DO => Q
);
end;library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
entity fifo_dcx is
generic (
module_type : string := "FIFO_DCX";
module_widthw : integer := 1;
module_widthr : integer := 1;
module_widthuw : integer := 1;
module_widthur : integer := 1;
module_numwordsw : integer := 2;
module_numwordsr : integer := 2;
module_amfull_flag : integer := 1;
module_amempty_flag : integer := 1;
module_hint : string := "UNUSED");
port (
Data : in std_logic_vector (module_widthw-1 downto 0);
WrClock : in std_logic;
WrEn : in std_logic;
RdClock : in std_logic;
RdEn : in std_logic;
Reset : in std_logic;
RPReset : in std_logic;
Q : out std_logic_vector (module_widthr-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
AlmostFull : out std_logic;
AlmostEmpty : out std_logic);
end fifo_dcx;
architecture fun_simulation of fifo_dcx is
component SC_FIFO_V2_16K_L
generic (
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 9;
RDATA_WIDTH : integer := 32;
ALMOST_FULL_X : integer := 1;
ALMOST_EMPTY_Y : integer := 1;
MEM_INIT_FLAG : integer := 0;
TERMINAL_COUNT : integer := 511;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end component;
signal FullIn, EmptyIn : std_logic;
begin
FullIn <= '0';
EmptyIn <= '1';
SC_FIFO_inst : SC_FIFO_V2_16K_L
generic map (
WADDR_WIDTH => module_widthuw,
WDATA_WIDTH => module_widthw,
RADDR_WIDTH => module_widthur,
RDATA_WIDTH => module_widthr,
ALMOST_FULL_X => module_amfull_flag,
ALMOST_EMPTY_Y => module_amempty_flag,
MEM_INIT_FLAG => 0,
TERMINAL_COUNT => module_numwordsw - 1,
MEM_INIT_FILE => open )
port map (
WE => WrEn,
WCLK => WrClock,
RST => Reset,
RPRST => RPReset,
RE => RdEn,
RCLK => RdClock,
FULLIN => FullIn,
EMPTYIN => EmptyIn,
DI => Data,
FULL => Full,
EMPTY => Empty,
AMFULL => AlmostFull,
AMEMPTY => AlmostEmpty,
DO => Q
);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use work.components.all;
entity ram_dp is
generic(
module_type : string := "RAM_DP";
module_widthw : integer := 1;
module_widthr : integer := 1;
module_numwordsw : integer := 1;
module_widthadw : integer := 1;
module_widthadr : integer := 1;
module_numwordsr : integer := 1;
module_indata : string := "REGISTERED";
module_outdata : string := "UNREGISTERED";
module_addressw_control : string := "REGISTERED";
module_addressr_control : string := "REGISTERED";
module_gsr : string := "DISABLED";
module_hint : string := "UNUSED";
module_init_file : string := "");
port(
Data : in std_logic_vector (module_widthw-1 downto 0);
WrAddress : in std_logic_vector (module_widthadw-1 downto 0);
RdAddress : in std_logic_vector (module_widthadr-1 downto 0);
WrClock : in std_logic;
WrClockEn : in std_logic;
RdClock : in std_logic;
RdClockEn : in std_logic;
WE : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector (module_widthr-1 downto 0));
end ram_dp;
architecture fun_simulation of ram_dp is
component SC_PDPRAM_16K_L
generic (
WADDR_WIDTH : integer := 13;
WDATA_WIDTH : integer := 2;
RADDR_WIDTH : integer := 13;
RDATA_WIDTH : integer := 2;
ARRAY_SIZE : integer := 511;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WCEN : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
WE : in STD_LOGIC ;
WCS : in STD_LOGIC_VECTOR (1 downto 0);
RCLK : in STD_LOGIC;
RCEN : in STD_LOGIC;
RST : in STD_LOGIC ;
WD : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
WAD : in STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
RAD : in STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
RD : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end component;
signal cs : std_logic_vector ( 1 downto 0);
signal Q_K : std_logic_vector (module_widthr-1 downto 0);
signal Q_K_reg : std_logic_vector (module_widthr-1 downto 0);
CONSTANT module_init_flag : integer := init_flag(module_init_file);
begin
cs <= "11";
OutRegister : process(RdClock, Reset)
begin
if (Reset = '1') then
Q_K_reg <= (others => '0');
elsif (RdClock'EVENT and RdClock = '1') then
if (RdClockEn = '1') then
Q_K_reg <= Q_K;
elsif (RdClockEn /= '0') then
Q_K_reg <= (others => 'X');
end if;
end if;
end process;
SelectOut : process (Q_K , Q_K_reg)
begin
if(module_outdata = "UNREGISTERED" and module_addressr_control = "REGISTERED") then
Q <= Q_K;
elsif(module_outdata = "REGISTERED" and module_addressr_control = "REGISTERED") then
Q <= Q_K_reg;
elsif(module_indata = "UNREGISTERED") then
assert false report "Error: module_indata should be REGISTERED" severity ERROR;
elsif(module_addressw_control = "UNREGISTERED") then
assert false report "Error: module_addressw_control should be REGISTERED" severity ERROR;
elsif(module_addressr_control = "UNREGISTERED") then
assert false report "Error: module_addressr_control should be REGISTERED" severity ERROR;
end if;
end process;
PDPRAM_inst : SC_PDPRAM_16K_L
generic map(
WADDR_WIDTH => module_widthadw,
WDATA_WIDTH => module_widthw,
RADDR_WIDTH => module_widthadr,
RDATA_WIDTH => module_widthr,
MEM_INIT_FLAG => module_init_flag,
ARRAY_SIZE => module_numwordsw*module_widthw,
MEM_INIT_FILE => module_init_file)
port map(
WCEN => WrClockEn,
WCLK => WrClock,
WE => WE,
WCS => cs,
RCLK => RdClock,
RCEN => RdClockEn,
RST => Reset,
WD => Data,
WAD => WrAddress,
RAD => RdAddress,
RD => Q_K
);
end;library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use work.components.all;
entity ram_dp_true is
generic (
module_type : string := "RAM_DP_TRUE";
module_widtha : positive;
module_widthada : positive;
module_numwordsa : positive;
module_widthb : positive;
module_widthadb : positive;
module_numwordsb : positive;
module_indata : string :="REGISTERED";
module_outdata : string :="UNREGISTERED";
module_addressa_control : string :="REGISTERED";
module_addressb_control : string :="REGISTERED";
module_init_file : string := "";
module_hint : string :="UNUSED";
module_gsr : string := "DISABLED";
module_writemode_a : string := "NORMAL";
module_writemode_b : string := "NORMAL");
port (
DataInA : in std_logic_vector(module_widtha-1 downto 0);
AddressA : in std_logic_vector(module_widthada-1 downto 0);
DataInB : in std_logic_vector(module_widthb-1 downto 0);
AddressB : in std_logic_vector(module_widthadb-1 downto 0);
ClockA : in std_logic := '0';
ClockEnA : in std_logic := '0';
ClockB : in std_logic := '0';
ClockEnB : in std_logic := '0';
WrA : in std_logic;
WrB : in std_logic;
ResetA : in std_logic;
ResetB : in std_logic;
QA : out std_logic_vector(module_widtha-1 downto 0);
QB : out std_logic_vector(module_widthb-1 downto 0));
end ram_dp_true;
architecture fun_simulation of ram_dp_true is
component SC_DPRAM_16K_L
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
ADDR_WIDTH_A : integer := 13;
DATA_WIDTH_A : integer := 2;
ADDR_WIDTH_B : integer := 14;
DATA_WIDTH_B : integer := 1;
MEM_INIT_FLAG : integer := 0;
ARRAY_SIZE : integer := 511;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
CENA : in STD_LOGIC ;
CLKA : in STD_LOGIC ;
WRA : in STD_LOGIC ;
CSA : in STD_LOGIC_VECTOR (1 downto 0);
RSTA : in STD_LOGIC ;
DIA : in STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
ADA : in STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
DOA : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
CENB : in STD_LOGIC ;
CLKB : in STD_LOGIC ;
WRB : in STD_LOGIC ;
CSB : in STD_LOGIC_VECTOR (1 downto 0);
RSTB : in STD_LOGIC ;
DIB : in STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
ADB : in STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
DOB : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
);
end component;
signal CS : std_logic_vector ( 1 downto 0);
signal QA_int, QA_int_reg : std_logic_vector(module_widtha-1 downto 0);
signal QB_int, QB_int_reg : std_logic_vector(module_widthb-1 downto 0);
CONSTANT module_init_flag : integer := init_flag(module_init_file);
begin
CS <= "11";
OutRegisterA : process(ClockA, ResetA)
begin
if(ResetA = '1') then QA_int_reg <= (others => '0');
elsif (ClockA'EVENT and ClockA = '1') then
if (ClockEnA = '1') then
QA_int_reg <= QA_int;
elsif (ClockEnA /= '0') then
QA_int_reg <= (others => 'X');
end if;
end if;
end process;
OutRegisterB : process(ClockB, ResetB)
begin
if(ResetB = '1') then QB_int_reg <= (others => '0');
elsif (ClockB'EVENT and ClockB = '1') then
if (ClockEnB = '1') then
QB_int_reg <= QB_int;
elsif (ClockEnB /= '0') then
QB_int_reg <= (others => 'X');
end if;
end if;
end process;
SelectA : process (QA_int , QA_int_reg)
begin
if(module_outdata = "UNREGISTERED" and module_addressa_control = "REGISTERED") then
QA <= QA_int;
elsif(module_outdata = "REGISTERED" and module_addressa_control = "REGISTERED") then
QA <= QA_int_reg;
elsif(module_indata = "UNREGISTERED") then
assert false report "Error: module_indata should be REGISTERED" severity ERROR;
elsif(module_addressa_control = "UNREGISTERED") then
assert false report "Error: module_addressa_control should be REGISTERED" severity ERROR;
end if;
end process;
SelectB : process (QB_int , QB_int_reg)
begin
if(module_outdata = "UNREGISTERED" and module_addressb_control = "REGISTERED") then
QB <= QB_int;
elsif(module_outdata = "REGISTERED" and module_addressb_control = "REGISTERED") then
QB <= QB_int_reg;
elsif(module_addressa_control = "UNREGISTERED") then
assert false report "Error: module_addressa_control should be REGISTERED" severity ERROR;
end if;
end process;
RAM_DP_INST : SC_DPRAM_16K_L
generic map(
ADDR_WIDTH_A => module_widthada,
DATA_WIDTH_A => module_widtha,
ADDR_WIDTH_B => module_widthadb,
DATA_WIDTH_B => module_widthb,
MEM_INIT_FLAG => module_init_flag,
ARRAY_SIZE => module_numwordsa*module_widtha,
MEM_INIT_FILE => module_init_file,
AWRITE_MODE => module_writemode_a,
BWRITE_MODE => module_writemode_b
)
port map (
CENA => ClockEnA,
CLKA => ClockA,
WRA => WrA,
CSA => CS,
RSTA => ResetA,
DIA => DataInA,
ADA => AddressA,
DOA => QA_int,
CENB => ClockEnB,
CLKB => ClockB,
WRB => WrB,
CSB => CS,
RSTB => ResetB,
DIB => DataInB,
ADB => AddressB,
DOB => QB_int
);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use work.components.all;
entity ram_dq is
generic(
module_type : string := "RAM_DQ";
module_width : integer := 1;
module_numwords : integer := 1;
module_widthad : integer := 1;
module_indata : string := "REGISTERED";
module_outdata : string := "UNREGISTERED";
module_address_control : string := "REGISTERED";
module_init_file : string := "";
module_hint : string := "UNUSED";
module_gsr : string := "DISABLED";
module_writemode : string := "NORMAL");
port(
Data : in std_logic_vector (module_width-1 downto 0);
Address : in std_logic_vector (module_widthad-1 downto 0);
Clock : in std_logic;
ClockEn : in std_logic;
WE : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector (module_width-1 downto 0));
end ram_dq;
architecture fun_simulation of ram_dq is
component SC_SPRAM_16K_L
generic (
WRITE_MODE : string := "NORMAL";
ADDR_WIDTH : integer := 13;
DATA_WIDTH : integer := 2;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 511;
MEM_INIT_FILE : string := "qq.dat"
);
port (
CEN : in STD_LOGIC ;
CLK : in STD_LOGIC ;
WR : in STD_LOGIC ;
CS : in STD_LOGIC_VECTOR (1 downto 0);
RST : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
AD : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
signal cs : std_logic_vector (1 downto 0);
signal Q_K : std_logic_vector (module_width-1 downto 0);
signal Q_K_reg : std_logic_vector (module_width-1 downto 0);
CONSTANT module_init_flag : integer := init_flag(module_init_file);
begin
cs <= "11";
OutRegister : process(Clock, Reset)
begin
if (Reset = '1') then
Q_K_reg <= (others => '0');
elsif (Clock'EVENT and Clock = '1') then
if (ClockEn = '1') then
Q_K_reg <= Q_K;
elsif (ClockEn /= '0') then
Q_K_reg <= (others => 'X');
end if;
end if;
end process;
SelectOut : process (Q_K , Q_K_reg)
begin
if(module_outdata = "UNREGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K;
elsif(module_outdata = "REGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K_reg;
elsif(module_indata = "UNREGISTERED") then
assert false report "Error: module_indata should be REGISTERED" severity ERROR;
elsif(module_address_control = "UNREGISTERED") then
assert false report "Error: module_address_control should be REGISTERED" severity ERROR;
end if;
end process;
SPRAM_inst : SC_SPRAM_16K_L
generic map (
ADDR_WIDTH => module_widthad,
DATA_WIDTH => module_width,
MEM_INIT_FLAG => module_init_flag,
ARRAY_SIZE => module_numwords * module_width,
MEM_INIT_FILE => module_init_file,
WRITE_MODE => module_writemode)
port map (
CEN => ClockEn,
CLK => Clock,
WR => WE,
CS => cs,
RST => Reset,
DI => Data,
AD => Address,
DO => Q_K
);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
entity rom is
generic (
module_type : string := "ROM";
module_width : integer := 1;
module_numwords : integer := 1;
module_widthad : integer := 1;
module_outdata : string := "REGISTERED";
module_address_control : string := "REGISTERED";
module_init_file : string := "init_file";
module_gsr : string := "DISABLED";
module_hint : string := "UNUSED");
port (
Address : in std_logic_vector (module_widthad-1 downto 0);
OutClock : in std_logic;
OutClockEn : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector (module_width-1 downto 0));
end rom;
architecture fun_simulation of rom is
component SC_SPRAM_16K_L
generic (
ADDR_WIDTH : integer := 13;
DATA_WIDTH : integer := 2;
ARRAY_SIZE : integer := 511;
MEM_INIT_FLAG : integer := 1;
MEM_INIT_FILE : string := "qq.dat"
);
port (
CEN : in STD_LOGIC ;
CLK : in STD_LOGIC ;
WR : in STD_LOGIC ;
CS : in STD_LOGIC_VECTOR (1 downto 0);
RST : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
AD : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
signal cs : std_logic_vector ( 1 downto 0);
signal DI_sig : std_logic_vector (module_width-1 downto 0);
signal WE_sig : std_logic;
signal Q_K : std_logic_vector (module_width-1 downto 0);
signal Q_K_reg : std_logic_vector (module_width-1 downto 0);
begin
cs <= "11";
WE_sig <= '0';
OutRegister : process(OutClock, Reset)
begin
if (Reset = '1') then
Q_K_reg <= (others => '0');
elsif (OutClock'EVENT and OutClock = '1') then
if(OutClockEn = '1') then
Q_K_reg <= Q_K;
elsif(OutClockEn /= '0') then
Q_K_reg <= (others => 'X' );
end if;
end if;
end process;
SelectOut : process (Q_K , Q_K_reg)
begin
if(module_outdata = "UNREGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K;
elsif(module_outdata = "REGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K_reg;
elsif(module_address_control = "UNREGISTERED") then
assert false report "Error: module_address_control should be REGISTERED" severity ERROR;
end if;
end process;
SPRAM_inst : SC_SPRAM_16K_L
generic map(
ADDR_WIDTH => module_widthad,
DATA_WIDTH => module_width,
MEM_INIT_FLAG => 1,
ARRAY_SIZE => module_numwords * module_width,
MEM_INIT_FILE => module_init_file)
port map(
CEN => OutClockEn,
CLK => OutClock,
WR => WE_sig,
CS => cs,
RST => Reset,
DI => DI_sig,
AD => Address,
DO => Q_K
);
end;
|
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A.
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 1-408-826-6000 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
--
-- Simulation Library File for EC/XP
--
-- $Header: G:\\CVS_REPOSITORY\\CVS_MACROS/LEON3SDE/ALTERA/grlib-eval-1.0.4/lib/tech/ec/ec/ORCA_L.vhd,v 1.1 2005/12/06 13:00:23 tame Exp $
--
library std;
use std.textio.all;
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- ************************************************************************
-- Entity definition
-- "generic" members
-- ************************************************************************
entity SC_BRAM_16K_L is
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 262144;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := ""
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end SC_BRAM_16K_L;
-- ************************************************************************
-- Architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_BRAM_16K_L is
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (WDATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to WDATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + WDATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------
--------- Local signals used to propagate input wire delay ---------------
signal WADA_node : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node : std_logic := 'X';
signal WDA_node : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node : std_logic := 'X';
signal RDA_node : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RDA_temp : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal WADB_node : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node : std_logic := 'X';
signal WDB_node : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node : std_logic := 'X';
signal RDB_node : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RDB_temp : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
-- architecture
begin
WADA_node <= WADA;
WEA_node <= WEA;
WDA_node <= WDA;
RADA_node <= RADA;
REA_node <= REA;
RDA <= RDA_TEMP;
WADB_node <= WADB;
WEB_node <= WEB;
WDB_node <= WDB;
RADB_node <= RADB;
REB_node <= REB;
RDB <= RDB_TEMP;
RDB_process: process(RDB_node, WEB_node)
begin
if (WEB_node = '1') then
if (BWRITE_MODE = "WRITETHROUGH") then
RDB_temp <= RDB_node;
elsif (BWRITE_MODE = "NORMAL") then
RDB_temp <= RDB_temp;
end if;
else
RDB_temp <= RDB_node;
end if;
end process;
RDA_process: process(RDA_node, WEA_node)
begin
if (WEA_node = '1') then
if (AWRITE_MODE = "WRITETHROUGH") then
RDA_temp <= RDA_node;
elsif (AWRITE_MODE = "NORMAL") then
RDA_temp <= RDA_temp;
end if;
else
RDA_temp <= RDA_node;
end if;
end process;
-----------------------------------------
--------- Behavior process -------------
-----------------------------------------
KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
--TSPEC: A note about sram initial values and rom mode:
-- If the user does not provide any values, ... default 0
-- for all ram locations in JECED
--QQ 7_17 variable v_MEM : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
variable v_MEM : std_logic_vector(ARRAY_SIZE*WDATA_WIDTH_A + WDATA_WIDTH_A - 1 downto 0) := ( others => '0' );
variable v_INI_DONE : boolean := FALSE;
variable v_WADDR_A : integer;
variable v_RADDR_A : integer;
variable v_WADDR_B : integer;
variable v_RADDR_B : integer;
variable v_WADDRA_Valid_Flag : boolean := TRUE;
variable v_WADDRB_Valid_Flag : boolean := TRUE;
variable v_RADDRA_Valid_Flag : boolean := TRUE;
variable v_RADDRB_Valid_Flag : boolean := TRUE;
begin -- Process
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
v_INI_DONE := TRUE;
end if;
-- Address Check
v_WADDRA_Valid_Flag := Valid_Address(WADA_node);
v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
v_RADDRA_Valid_Flag := Valid_Address(RADA_node);
v_RADDRB_Valid_Flag := Valid_Address(RADB_node);
if ( v_WADDRA_Valid_Flag = TRUE ) then
v_WADDR_A := CONV_INTEGER(WADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_WADDRB_Valid_Flag = TRUE ) then
v_WADDR_B := CONV_INTEGER(WADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressB of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRA_Valid_Flag = TRUE ) then
v_RADDR_A := CONV_INTEGER(RADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRB_Valid_Flag = TRUE ) then
v_RADDR_B := CONV_INTEGER(RADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressB of Port contains invalid bit!"
-- severity warning;
end if;
-- CHECK Operation
if (WEA = '1' and WEB = '1' and
not(
(v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B)
or
(v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
)
) then
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity warning;
end if;
-- MEM Operation
if (WEA_node = '1') then
v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
end if;
if (WEB_node = '1') then
v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
end if;
if (REA_node = '1') then
RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
-- else
-- RDA_node <= ( others => 'X');
end if;
if (REB_node = '1') then
RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
-- else
-- RDB_node <= ( others => 'X');
end if;
end process KERNEL_BEHAV;
end LATTICE_BEHAV;
-- ************************************************************************
--
-- Block Memory: Behavioral Model
-- The kernel of other RAM applications
-- ************************************************************************
--
-- Filename: SC_BLOCK_RAM_L.vhd
-- Description: BRAM behavioral model.
-- ************************************************************************
library std;
use std.textio.all;
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- ************************************************************************
-- Entity definition
-- "generic" members
-- ************************************************************************
entity SC_BRAM_16K_L_SYNC is
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 262144;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := ""
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
WCLK : in STD_LOGIC;
RCLK : in STD_LOGIC
);
end SC_BRAM_16K_L_SYNC;
-- ************************************************************************
-- Architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_BRAM_16K_L_SYNC is
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (WDATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to WDATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + WDATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------
--------- Local signals used to propagate input wire delay ---------------
signal WADA_node : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node : std_logic := 'X';
signal WDA_node : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node : std_logic := 'X';
signal RDA_node : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal WADB_node : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node : std_logic := 'X';
signal WDB_node : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node : std_logic := 'X';
signal RDB_node : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal WCLK_node : std_logic := 'X';
signal RCLK_node : std_logic := 'X';
-- architecture
begin
WADA_node <= WADA;
WEA_node <= WEA;
WDA_node <= WDA;
RADA_node <= RADA;
REA_node <= REA;
RDA <= RDA_node;
WADB_node <= WADB;
WEB_node <= WEB;
WDB_node <= WDB;
RADB_node <= RADB;
REB_node <= REB;
RDB <= RDB_node;
WCLK_node <= WCLK;
RCLK_node <= RCLK;
-----------------------------------------
--------- Behavior process -------------
-----------------------------------------
--KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
KERNEL_BEHAV : process( WCLK_node, RCLK_node)
--TSPEC: A note about sram initial values and rom mode:
-- If the user does not provide any values, ... default 0
-- for all ram locations in JECED
variable v_MEM : std_logic_vector(ARRAY_SIZE*WDATA_WIDTH_A - 1 downto 0) := ( others => '0' );
variable v_INI_DONE : boolean := FALSE;
variable v_WADDR_A : integer;
variable v_RADDR_A : integer;
variable v_WADDR_B : integer;
variable v_RADDR_B : integer;
variable v_WADDRA_Valid_Flag : boolean := TRUE;
variable v_WADDRB_Valid_Flag : boolean := TRUE;
variable v_RADDRA_Valid_Flag : boolean := TRUE;
variable v_RADDRB_Valid_Flag : boolean := TRUE;
begin -- Process
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
v_INI_DONE := TRUE;
end if;
-- Address Check
v_WADDRA_Valid_Flag := Valid_Address(WADA_node);
v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
v_RADDRA_Valid_Flag := Valid_Address(RADA_node);
v_RADDRB_Valid_Flag := Valid_Address(RADB_node);
if ( v_WADDRA_Valid_Flag = TRUE ) then
v_WADDR_A := CONV_INTEGER(WADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_WADDRB_Valid_Flag = TRUE ) then
v_WADDR_B := CONV_INTEGER(WADB_node);
else
-- assert (Now = 0 ps)
-- report "Write AddressB of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRA_Valid_Flag = TRUE ) then
v_RADDR_A := CONV_INTEGER(RADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRB_Valid_Flag = TRUE ) then
v_RADDR_B := CONV_INTEGER(RADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressB of Port contains invalid bit!"
-- severity warning;
end if;
-- CHECK Operation
if (WEA = '1' and WEB = '1' and
not(
(v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B)
or
(v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
)
) then
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity warning;
end if;
-- MEM Operation
if (WEA_node = '1' and WCLK_node'event and WCLK_node = '1' ) then
v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
end if;
if (WEB_node = '1' and WCLK_node'event and WCLK_node = '1') then
v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
end if;
if (REA_node = '1' and RCLK_node'event and RCLK_node = '1') then
RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
-- else
-- RDA_node <= ( others => 'X');
end if;
if (REB_node = '1' and RCLK_node'event and RCLK_node = '1') then
RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
-- else
-- RDB_node <= ( others => 'X');
end if;
end process KERNEL_BEHAV;
end LATTICE_BEHAV;
library std;
use std.textio.all;
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- ************************************************************************
-- Entity definition
-- "generic" members
-- ************************************************************************
entity SC_BRAM_PDP_16K_L is
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 262144;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := ""
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end SC_BRAM_PDP_16K_L;
-- ************************************************************************
-- Architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_BRAM_PDP_16K_L is
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (WDATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to WDATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + WDATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------
--------- Local signals used to propagate input wire delay ---------------
signal WADA_node : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node : std_logic := 'X';
signal WDA_node : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node : std_logic := 'X';
signal RDA_node : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal WADB_node : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node : std_logic := 'X';
signal WDB_node : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node : std_logic := 'X';
signal RDB_node : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
-- architecture
begin
WADA_node <= WADA;
WEA_node <= WEA;
WDA_node <= WDA;
RADA_node <= RADA;
REA_node <= REA;
RDA <= RDA_node;
WADB_node <= WADB;
WEB_node <= WEB;
WDB_node <= WDB;
RADB_node <= RADB;
REB_node <= REB;
RDB <= RDB_node;
-----------------------------------------
--------- Behavior process -------------
-----------------------------------------
KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
--TSPEC: A note about sram initial values and rom mode:
-- If the user does not provide any values, ... default 0
-- for all ram locations in JECED
variable v_MEM : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
variable v_INI_DONE : boolean := FALSE;
variable v_WADDR_A : integer;
variable v_RADDR_A : integer;
variable v_WADDR_B : integer;
variable v_RADDR_B : integer;
variable v_WADDRA_Valid_Flag : boolean := TRUE;
variable v_WADDRB_Valid_Flag : boolean := TRUE;
variable v_RADDRA_Valid_Flag : boolean := TRUE;
variable v_RADDRB_Valid_Flag : boolean := TRUE;
begin -- Process
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
v_INI_DONE := TRUE;
end if;
-- Address Check
v_WADDRA_Valid_Flag := Valid_Address(WADA_node);
v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
v_RADDRA_Valid_Flag := Valid_Address(RADA_node);
v_RADDRB_Valid_Flag := Valid_Address(RADB_node);
if ( v_WADDRA_Valid_Flag = TRUE ) then
v_WADDR_A := CONV_INTEGER(WADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_WADDRB_Valid_Flag = TRUE ) then
v_WADDR_B := CONV_INTEGER(WADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressB of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRA_Valid_Flag = TRUE ) then
v_RADDR_A := CONV_INTEGER(RADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRB_Valid_Flag = TRUE ) then
v_RADDR_B := CONV_INTEGER(RADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressB of Port contains invalid bit!"
-- severity warning;
end if;
-- CHECK Operation
if (WEA = '1' and WEB = '1' and
not(
(v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B)
or
(v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
)
) then
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity warning;
end if;
-- MEM Operation
if (WEA_node = '1') then
v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
end if;
if (WEB_node = '1') then
v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
end if;
if (REA_node = '1') then
RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
-- else
-- RDA_node <= ( others => 'X');
end if;
if (REB_node = '1') then
RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
-- else
-- RDB_node <= ( others => 'X');
end if;
end process KERNEL_BEHAV;
end LATTICE_BEHAV;
---************* SC_FIFO_L **************************
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity READ_POINTER_CTRL is
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end READ_POINTER_CTRL;
architecture LATTICE_BEHAV of READ_POINTER_CTRL is
signal s_READ_POINTER : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
begin
READ_POINTER <= s_READ_POINTER;
process (GLOBAL_RST, RESET_RP, READ_EN, READ_CLK)
variable v_READ_POINTER: STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' or RESET_RP = '1' then
s_READ_POINTER <= (others => '0');
elsif (READ_CLK'EVENT and READ_CLK = '1') then
if (READ_EN = '1' and EMPTY_FLAG = '1') then
v_READ_POINTER := s_READ_POINTER + '1';
else
v_READ_POINTER := s_READ_POINTER;
end if;
if (v_READ_POINTER = TERMINAL_COUNT + 1) then
s_READ_POINTER <= (others => '0');
else
s_READ_POINTER <= v_READ_POINTER;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO COMPONENTS WRITE_POINTER_CTRL
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity WRITE_POINTER_CTRL is
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end WRITE_POINTER_CTRL;
architecture LATTICE_BEHAV of WRITE_POINTER_CTRL is
signal s_WRITE_POINTER : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
WRITE_POINTER <= s_WRITE_POINTER;
process (GLOBAL_RST, WRITE_EN, WRITE_CLK)
variable v_WRITE_POINTER: STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' then
s_WRITE_POINTER <= (others => '0');
elsif (WRITE_CLK'EVENT and WRITE_CLK = '1') then
if (WRITE_EN = '1' and FULL_FLAG /= '1') then
v_WRITE_POINTER := s_WRITE_POINTER + '1';
else
v_WRITE_POINTER := s_WRITE_POINTER ;
end if;
if (v_WRITE_POINTER = TERMINAL_COUNT + 1) then
s_WRITE_POINTER <= (others => '0');
else
s_WRITE_POINTER <= v_WRITE_POINTER;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO COMPONENTS FLAG LOGIC
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity FLAG_LOGIC is
generic (
WPOINTER_WIDTH : integer := 9;
RPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0) := (others => '0');--QQ
R_POINTER : in STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
W_POINTER : in STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0');
GLOBAL_RST : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end FLAG_LOGIC;
architecture LATTICE_BEHAV of FLAG_LOGIC is
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Pointer (
IN_ADDR : in STD_LOGIC_VECTOR
) return BOOLEAN is
variable v_Valid_Flag : BOOLEAN := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Pointer;
--------------------------------------------------------------------------
-- Function: Calculate_Offset
-- Description:
--------------------------------------------------------------------------
function Calculate_Offset (
IN_TC : in STD_LOGIC_VECTOR;
TC_LENGTH: in INTEGER
) return STD_LOGIC_VECTOR is
variable vTC_FULL: STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '1');
variable vTC_TEMP: STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '0');
variable vOFFSET : STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '0');
begin
vTC_TEMP := IN_TC;
vOFFSET := vTC_FULL-vTC_TEMP;
return vOFFSET;
end Calculate_Offset;
begin
--------------------------------------------------------------------------
-- Function: Main Process
-- Description:
--------------------------------------------------------------------------
FULL_AMFULL: process (GLOBAL_RST, WRITE_EN, WRITE_CLK, W_POINTER, R_POINTER)
variable v_WP_Valid_Flag : boolean := TRUE;
variable v_RP_Valid_Flag : boolean := TRUE;
--variable v_WP_Check_FULL_TMP : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_WP_Check_AMFL_TMP : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
variable v_WP_Check_AMFL_TMP1 : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
variable v_WP_Check_FULL : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
variable v_WP_Check_AMFL : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
begin
v_WP_Valid_Flag := Valid_Pointer(W_POINTER);
v_RP_Valid_Flag := Valid_Pointer(R_POINTER);
if( v_WP_Valid_Flag = TRUE) then
v_WP_Check_AMFL_TMP := W_POINTER + AMFULL_X + 1;
end if;
v_WP_Check_AMFL_TMP1 := v_WP_Check_AMFL_TMP + Calculate_Offset(TERMINAL_COUNT, WPOINTER_WIDTH);
if ( v_WP_Valid_Flag = TRUE and W_POINTER = TERMINAL_COUNT ) then
v_WP_Check_FULL := (others => '0');
elsif( v_WP_Valid_Flag = TRUE ) then
v_WP_Check_FULL := W_POINTER + 1;
end if;
if GLOBAL_RST = '1' then
FULL_D <= '0';
AMFULL_D <= '0';
elsif( v_WP_Valid_Flag = TRUE and v_RP_Valid_Flag = TRUE) then
if R_POINTER = v_WP_Check_FULL then
FULL_D <= '1';
else
FULL_D <= '0';
end if;
if (W_POINTER > R_POINTER) then
if (v_WP_Check_AMFL_TMP1 < W_POINTER) then
if v_WP_Check_AMFL_TMP1 >= R_POINTER then
AMFULL_D <= '1';
else
AMFULL_D <= '0';
end if;
else
AMFULL_D <= '0';
end if;
elsif (W_POINTER < R_POINTER) then
if (v_WP_Check_AMFL_TMP1 < W_POINTER) then
AMFULL_D <= '1';
elsif (v_WP_Check_AMFL_TMP >= R_POINTER) then
AMFULL_D <= '1';
else
AMFULL_D <= '0';
end if;
end if;
end if;
end process FULL_AMFULL;
EMPTY_AMEMPTY: process (GLOBAL_RST, READ_EN, READ_CLK, W_POINTER, R_POINTER)
variable v_WP_Valid_Flag : boolean := TRUE;
variable v_RP_Valid_Flag : boolean := TRUE;
variable v_RP_Check_EMPT_TMP : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_RP_Check_AMET_TMP : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_RP_Check_AMET_TMP1 : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
--variable v_RP_Check_EMPT : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_RP_Check_AMET : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
begin
v_WP_Valid_Flag := Valid_Pointer(W_POINTER);
v_RP_Valid_Flag := Valid_Pointer(R_POINTER);
if( v_RP_Valid_Flag = TRUE and v_WP_Valid_Flag = TRUE) then
v_RP_Check_AMET_TMP := R_POINTER + AMEMPTY_Y ; -- Different from TSPEC QQ 07 17,2002
end if;
v_RP_Check_AMET_TMP1 := v_RP_Check_AMET_TMP + Calculate_Offset(TERMINAL_COUNT, RPOINTER_WIDTH);
if GLOBAL_RST = '1' then
EMPTY_D <= '0';
AMEMPTY_D <= '0';
elsif( v_WP_Valid_Flag = TRUE and v_RP_Valid_Flag = TRUE) then
if R_POINTER = W_POINTER then -- Different from TSPEC QQ 07 17,2002
EMPTY_D <= '0';
else
EMPTY_D <= '1';
end if;
if (W_POINTER < R_POINTER) then
if (v_RP_Check_AMET_TMP1 < R_POINTER) then
v_RP_Check_AMET := v_RP_Check_AMET_TMP + Calculate_Offset(TERMINAL_COUNT, RPOINTER_WIDTH);
if v_RP_Check_AMET >= W_POINTER then
AMEMPTY_D <= '0';
else
AMEMPTY_D <= '1';
end if;
else
AMEMPTY_D <= '1';
end if;
elsif (W_POINTER > R_POINTER) then
if (v_RP_Check_AMET_TMP1 < R_POINTER) then
AMEMPTY_D <= '0';
elsif (v_RP_Check_AMET_TMP >= W_POINTER) then
AMEMPTY_D <= '0';
else
AMEMPTY_D <= '1';
end if;
elsif (W_POINTER = R_POINTER) then
AMEMPTY_D <= '0';
end if;
end if;
end process EMPTY_AMEMPTY;
end LATTICE_BEHAV;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
---USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
--LIBRARY SC_LIB;
--USE SC_LIB.SC_FIFO_COMPS.ALL;
entity SC_FIFO_16K_L is
generic (
TERMINAL_COUNT : integer := 511; --QQ: Word number < 2**WADDR_WIDTH
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 9;
RDATA_WIDTH : integer := 32;
ALMOST_FULL_X : integer := 1;
ALMOST_EMPTY_Y : integer := 1;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end SC_FIFO_16K_L;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_FIFO_16K_L is
---------------------------------------------------------
-- Function: TO_STD_VECTOR
---------------------------------------------------------
function TO_STD_VECTOR ( INPUT_STRING : string; INPUT_LENGTH: integer)
return std_logic_vector is
variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
variable vTRANS: string(INPUT_LENGTH downto 1) := (others => '0');
begin
vTRANS := INPUT_STRING;
for i in INPUT_LENGTH downto 1 loop
if (vTRANS(i) = '1') then
vDATA_STD_VEC(i-1) := '1';
elsif ( vTRANS(i) ='0') then
vDATA_STD_VEC(i-1) := '0';
end if;
end loop;
return vDATA_STD_VEC;
end TO_STD_VECTOR;
---------------------------------------------------------
-- Function: INT_TO_VEC
---------------------------------------------------------
function INT_TO_VEC ( INPUT_INT : integer; INPUT_LENGTH: integer)
return std_logic_vector is
variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
variable vTRANS: integer := 0;
variable vQUOTIENT: integer := 0;
begin
vQUOTIENT := INPUT_INT;
for i in 0 to INPUT_LENGTH -1 loop
vTRANS := 0;
while vQUOTIENT >1 loop
vQUOTIENT := vQUOTIENT - 2;
vTRANS := vTRANS + 1;
end loop;
case vQUOTIENT is
when 1 =>
vDATA_STD_VEC(i) := '1';
when 0 =>
vDATA_STD_VEC(i) := '0';
when others =>
null;
end case;
vQUOTIENT := vTRANS;
end loop;
return vDATA_STD_VEC;
end INT_TO_VEC;
---------------------------------------------------------
-- Components Definition
---------------------------------------------------------
component SC_BRAM_16K_L_SYNC
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
WCLK : in STD_LOGIC;
RCLK : in STD_LOGIC
);
end component;
component READ_POINTER_CTRL
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end component;
component WRITE_POINTER_CTRL
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end component;
component FLAG_LOGIC
generic (
WPOINTER_WIDTH : integer := 9;
RPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
R_POINTER : in STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0);
W_POINTER : in STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0);
GLOBAL_RST : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end component;
-- Signal Declaration
signal WE_node : STD_LOGIC := '0';
signal WCLK_node : STD_LOGIC := '0';
signal RST_node : STD_LOGIC := '0';
signal RPRST_node : STD_LOGIC := '0';
signal RE_node : STD_LOGIC := '0';
signal RCLK_node : STD_LOGIC := '0';
signal FULLIN_node : STD_LOGIC := '0';
signal EMPTYIN_node : STD_LOGIC := '0';
signal DI_node : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => '0');
signal DI_reg : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => '0');
signal FULLIN_reg : STD_LOGIC := '0';
signal EMPTYIN_reg : STD_LOGIC := '0';
signal FULL_node : STD_LOGIC := '0';
signal EMPTY_node : STD_LOGIC := '0';
signal AMFULL_node : STD_LOGIC := '0';
signal AMEMPTY_node : STD_LOGIC := '0';
signal DO_node : STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => '0');
signal TC_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
signal FULL_reg : STD_LOGIC := '0';
signal EMPTY_reg : STD_LOGIC := '0';
signal AMFULL_reg : STD_LOGIC := '0';
signal AMEMPTY_reg : STD_LOGIC := '0';
signal RP_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => '0');
signal WP_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
signal GND_sig : STD_LOGIC := '0';
-- architecture
begin
GND_sig <= '0';
WE_node <= WE and not(FULL_node);
WCLK_node <= WCLK;
RST_node <= RST;
RPRST_node <= RPRST;
RE_node <= RE and EMPTY_node;
RCLK_node <= RCLK;
FULLIN_node <= FULLIN;
EMPTYIN_node <= EMPTYIN;
DI_node <= DI;
--TC_node <= TO_STD_VECTOR(TERMINAL_COUNT,WADDR_WIDTH);
TC_node <= INT_TO_VEC(TERMINAL_COUNT,WADDR_WIDTH);
--FULL <= FULL_node;
FULL <= FULL_node when (RE_node = '0') else FULL_reg;
--AMFULL <= AMFULL_node;
AMFULL <= AMFULL_node when (RE_node = '0') else AMFULL_reg;
EMPTY <= not EMPTY_node;
AMEMPTY <= not AMEMPTY_node;
DO <= DO_node;
-- Register Port DI inputs
register_DI_inputs: process (RST_node, WCLK_node)
begin
if (RST_node = '1') then
DI_reg <= (others =>'0');
elsif (WCLK_node'event and WCLK_node = '1') then
if (WE_node = '1') then
DI_reg <= DI_node after 1 ps;
end if;
end if;
end process register_DI_inputs;
-- Register flag inputs
register_flag_inputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULLIN_reg <= '0';
EMPTYIN_reg <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
-- WE_reg <= WE_node and not (FULL_reg); --QQ
if (WE_node = '1') then
FULLIN_reg <= FULLIN_node;
end if;
end if;
if (RCLK_node'event and RCLK_node = '1') then
-- RE_reg <= RE_node and EMPTY_reg; --QQ
if (RE_node = '1') then
EMPTYIN_reg <= EMPTYIN_node;
end if;
end if;
end if;
end process register_flag_inputs;
-- Register flag outputs
register_flag_outputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULL_node <= '0';
AMFULL_node <= '0';
EMPTY_node <= '0';
AMEMPTY_node <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
FULL_node <= FULL_reg;
AMFULL_node <= AMFULL_reg;
end if;
if (RCLK_node'event and RCLK_node = '1') then
EMPTY_node <= EMPTY_reg;
AMEMPTY_node <= AMEMPTY_reg;
end if;
end if;
end process register_flag_outputs;
-- READ_POINTER_CTRL instance for FIFO
FIFO_RPC_INST: READ_POINTER_CTRL
generic map (
RPOINTER_WIDTH => RADDR_WIDTH
)
port map (
TERMINAL_COUNT => TC_node,
GLOBAL_RST => RST_node,
RESET_RP => RPRST_node,
READ_EN => RE_node,
READ_CLK => RCLK_node,
EMPTY_FLAG => EMPTY_reg,
READ_POINTER => RP_node
);
-- WRITE_POINTER_CTRL instance for FIFO
FIFO_WPC_INST: WRITE_POINTER_CTRL
generic map (
WPOINTER_WIDTH => WADDR_WIDTH,
WDATA_WIDTH => WDATA_WIDTH
)
port map (
TERMINAL_COUNT => TC_node,
GLOBAL_RST => RST_node,
WRITE_EN => WE_node,
WRITE_CLK => WCLK_node,
FULL_FLAG => FULL_reg,
WRITE_POINTER => WP_node
);
-- FLAG_LOGIC instance for FIFO
FIFO_FL_INST: FLAG_LOGIC
generic map (
WPOINTER_WIDTH => WADDR_WIDTH,
RPOINTER_WIDTH => RADDR_WIDTH,
WDATA_WIDTH => WDATA_WIDTH,
RDATA_WIDTH => RDATA_WIDTH,
AMFULL_X => ALMOST_FULL_X,
AMEMPTY_Y => ALMOST_EMPTY_Y
)
port map(
TERMINAL_COUNT => TC_node,
R_POINTER => RP_node,
W_POINTER => WP_node,
GLOBAL_RST => RST_node,
READ_EN => RE_node,
READ_CLK => RCLK_node,
WRITE_EN => WE_node,
WRITE_CLK => WCLK_node,
FULL_D => FULL_reg,
EMPTY_D => EMPTY_reg,
AMFULL_D => AMFULL_reg,
AMEMPTY_D => AMEMPTY_reg
);
-- BRAM instance for FIFO
FIFO_BRAM_INST: SC_BRAM_16K_L_SYNC
generic map(
WADDR_WIDTH_A => WADDR_WIDTH,
RADDR_WIDTH_A => RADDR_WIDTH,
WADDR_WIDTH_B => WADDR_WIDTH,
RADDR_WIDTH_B => RADDR_WIDTH,
WDATA_WIDTH_A => WDATA_WIDTH,
RDATA_WIDTH_A => RDATA_WIDTH,
WDATA_WIDTH_B => WDATA_WIDTH,
RDATA_WIDTH_B => RDATA_WIDTH,
ARRAY_SIZE => open,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => WP_node,
WEA => WE_node,
WDA => DI_node,
RADA => RP_node,
REA => RE_node,
RDA => DO_node,
WADB => WP_node,
WEB => GND_sig,
WDB => DI_node,
RADB => RP_node,
REB => GND_sig,
RDB => open,
WCLK => WCLK_node,
RCLK => RCLK_node
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- FIFO V2: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_FIFO_V2.vhd
-- Description: FIFO behavioral model.
-- ************************************************************************
-- FIFO COMPONENTS READ_POINTER_CTRL_V2
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity READ_POINTER_CTRL_V2 is
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end READ_POINTER_CTRL_V2;
architecture LATTICE_BEHAV of READ_POINTER_CTRL_V2 is
signal s_READ_POINTER : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
begin
READ_POINTER <= s_READ_POINTER;
process (GLOBAL_RST, RESET_RP, READ_EN, READ_CLK)
variable v_READ_POINTER: STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' or RESET_RP = '1' then
s_READ_POINTER <= TERMINAL_COUNT;
elsif (READ_CLK'EVENT and READ_CLK = '1') then
if (READ_EN = '1' and EMPTY_FLAG = '1') then
v_READ_POINTER := s_READ_POINTER + '1';
else
v_READ_POINTER := s_READ_POINTER;
end if;
if (v_READ_POINTER = TERMINAL_COUNT + 1) then
s_READ_POINTER <= (others => '0');
else
s_READ_POINTER <= v_READ_POINTER;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO COMPONENTS WRITE_POINTER_CTRL_V2
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity WRITE_POINTER_CTRL_V2 is
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end WRITE_POINTER_CTRL_V2;
architecture LATTICE_BEHAV of WRITE_POINTER_CTRL_V2 is
signal s_WRITE_POINTER : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
WRITE_POINTER <= s_WRITE_POINTER;
process (GLOBAL_RST, WRITE_EN, WRITE_CLK)
variable v_WRITE_POINTER: STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' then
s_WRITE_POINTER <= TERMINAL_COUNT ;
elsif (WRITE_CLK'EVENT and WRITE_CLK = '1') then
if (WRITE_EN = '1' and FULL_FLAG /= '1') then
v_WRITE_POINTER := s_WRITE_POINTER + '1';
else
v_WRITE_POINTER := s_WRITE_POINTER ;
end if;
if (v_WRITE_POINTER = TERMINAL_COUNT + 1) then
s_WRITE_POINTER <= (others => '0');
else
s_WRITE_POINTER <= v_WRITE_POINTER ;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO V2 COMPONENTS FLAG LOGIC
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
entity FLAG_LOGIC_V2 is
generic (
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
GLOBAL_RST : in STD_LOGIC ;
FIFO_CAP : in integer ;
FIFO_PTR : in integer ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end FLAG_LOGIC_V2;
architecture LATTICE_BEHAV of FLAG_LOGIC_V2 is
begin
--------------------------------------------------------------------------
-- Function: Main Process
-- Description:
--------------------------------------------------------------------------
FULL_AMFULL_EMPTY_AMEMPTY: process (GLOBAL_RST, FIFO_CAP, FIFO_PTR)
begin
if GLOBAL_RST = '1' then
FULL_D <= '0';
AMFULL_D <= '0';
EMPTY_D <= '0';
AMEMPTY_D <= '0';
else
if (FIFO_CAP - FIFO_PTR < WDATA_WIDTH) then
FULL_D <= '1';
else
FULL_D <= '0';
end if;
if (FIFO_CAP - FIFO_PTR < WDATA_WIDTH + AMFULL_X * WDATA_WIDTH) then
AMFULL_D <= '1';
else
AMFULL_D <= '0';
end if;
if (FIFO_PTR < RDATA_WIDTH) then
EMPTY_D <= '0';
else
EMPTY_D <= '1';
end if;
if (FIFO_PTR < RDATA_WIDTH + AMEMPTY_Y * RDATA_WIDTH) then
AMEMPTY_D <= '0';
else
AMEMPTY_D <= '1';
end if;
end if;
end process FULL_AMFULL_EMPTY_AMEMPTY;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO V2 Main Body
-- READ_POINTER_CTRL_V2
-- WRITE_POINTER_CTRL_V2
-- FLAG_LOGIC_V2
-- SC_BRAM_16K
-- ************************************************************************
-- ************************************************************************
-- Top Design Entity definition
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity SC_FIFO_V2_16K_L is
generic (
TERMINAL_COUNT : integer := 511; --QQ: Word number < 2**WADDR_WIDTH
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 8;
RDATA_WIDTH : integer := 64;
ALMOST_FULL_X : integer := 2;
ALMOST_EMPTY_Y : integer := 2;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end SC_FIFO_V2_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_FIFO_V2_16K_L is
---------------------------------------------------------
-- Function: TO_STD_VECTOR
---------------------------------------------------------
function TO_STD_VECTOR ( INPUT_STRING : string; INPUT_LENGTH: integer)
return std_logic_vector is
variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
variable vTRANS: string(INPUT_LENGTH downto 1) := (others => '0');
begin
vTRANS := INPUT_STRING;
for i in INPUT_LENGTH downto 1 loop
if (vTRANS(i) = '1') then
vDATA_STD_VEC(i-1) := '1';
elsif ( vTRANS(i) ='0') then
vDATA_STD_VEC(i-1) := '0';
end if;
end loop;
return vDATA_STD_VEC;
end TO_STD_VECTOR;
---------------------------------------------------------
-- Components Definition
---------------------------------------------------------
component SC_BRAM_16K_L
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
component READ_POINTER_CTRL_V2
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end component;
component WRITE_POINTER_CTRL_V2
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end component;
component FLAG_LOGIC_V2
generic (
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
GLOBAL_RST : in STD_LOGIC ;
FIFO_CAP : in integer ;
FIFO_PTR : in integer ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end component;
-- Signal Declaration
signal WE_node : STD_LOGIC := 'X';
signal WCLK_node : STD_LOGIC := 'X';
signal RST_node : STD_LOGIC := 'X';
signal RPRST_node : STD_LOGIC := 'X';
signal RE_node : STD_LOGIC := 'X';
signal RCLK_node : STD_LOGIC := 'X';
signal FULLIN_node : STD_LOGIC := 'X';
signal EMPTYIN_node : STD_LOGIC := 'X';
signal DI_node : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal DI_reg : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal WE_reg : STD_LOGIC := 'X';
signal RE_reg : STD_LOGIC := 'X';
signal FULLIN_reg : STD_LOGIC := 'X';
signal EMPTYIN_reg : STD_LOGIC := 'X';
signal FULL_node : STD_LOGIC := 'X';
signal EMPTY_node : STD_LOGIC := 'X';
signal AMFULL_node : STD_LOGIC := 'X';
signal AMEMPTY_node : STD_LOGIC := 'X';
signal DO_node : STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');
signal TC_W_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
signal TC_R_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal FULL_reg : STD_LOGIC := 'X';
signal EMPTY_reg : STD_LOGIC := 'X';
signal AMFULL_reg : STD_LOGIC := 'X';
signal AMEMPTY_reg : STD_LOGIC := 'X';
signal RP_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal WP_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
signal GND_sig : STD_LOGIC := 'X';
--QQ FIFOV2
signal FIFO_capacity : integer := 0;
signal FIFO_pointer : integer := 0;
-- architecture
begin
FIFO_capacity <= (TERMINAL_COUNT + 1) * WDATA_WIDTH;
GND_sig <= '0';
WE_node <= WE and not (FULL_node);
WCLK_node <= WCLK;
RST_node <= RST;
RPRST_node <= RPRST;
RE_node <= RE;
RCLK_node <= RCLK;
FULLIN_node <= FULLIN;
EMPTYIN_node <= EMPTYIN;
DI_node <= DI;
TC_W_node <= CONV_STD_LOGIC_VECTOR(TERMINAL_COUNT,WADDR_WIDTH);
TC_R_node <= CONV_STD_LOGIC_VECTOR((TERMINAL_COUNT+1)*(WDATA_WIDTH/RDATA_WIDTH)-1,RADDR_WIDTH);
--FULL <= FULL_node;
FULL <= FULL_node when (RE_node = '0') else FULL_reg;
--AMFULL <= AMFULL_node;
AMFULL <= AMFULL_node when (RE_node = '0') else AMFULL_reg;
EMPTY <= not EMPTY_node;
AMEMPTY <= not AMEMPTY_node;
DO <= DO_node;
-- Register Port DI inputs
register_DI_inputs: process (RST_node, WCLK_node)
begin
if (RST_node = '1') then
DI_reg <= (others =>'0');
elsif (WCLK_node'event and WCLK_node = '1') then
if (WE_node = '1') then
DI_reg <= DI_node after 1 ps;
end if;
end if;
end process register_DI_inputs;
-- Register flag inputs
register_flag_inputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULLIN_reg <= '0';
EMPTYIN_reg <= '0';
WE_reg <= '0';
RE_reg <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
WE_reg <= WE_node and not FULL_reg; --Fix DTS14659
--WE_reg <= WE_node;
if (WE_node = '1') then
FULLIN_reg <= FULLIN_node;
end if;
end if;
if (RCLK_node'event and RCLK_node = '1') then
RE_reg <= RE_node and EMPTY_reg;
if (RE_node = '1') then
EMPTYIN_reg <= EMPTYIN_node;
end if;
end if;
end if;
end process register_flag_inputs;
-- Register flag outputs
register_flag_outputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULL_node <= '0';
AMFULL_node <= '0';
EMPTY_node <= '0';
AMEMPTY_node <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
FULL_node <= FULL_reg;
AMFULL_node <= AMFULL_reg;
end if;
if (RCLK_node'event and RCLK_node = '1') then
EMPTY_node <= EMPTY_reg;
AMEMPTY_node <= AMEMPTY_reg;
end if;
end if;
end process register_flag_outputs;
-- Set FIFO_pointer
FIFO_CAP_POINTER: process ( RP_node, WP_node, RST_node, RPRST_node)
begin
--WP ++, FIFO_CAP --
if (WP_node'event and RP_node'event) then
FIFO_pointer <= FIFO_pointer + WDATA_WIDTH - RDATA_WIDTH;
elsif(WP_node'event) then
FIFO_pointer <= FIFO_pointer + WDATA_WIDTH;
end if;
--RPRST Active, FIFO_CAP --
--RP ++, FIFO_CAP ++
if (RST_node = '1') then
FIFO_pointer <= 0;
elsif (RPRST_node = '1') then
FIFO_pointer <= (CONV_INTEGER(WP_node)+1) * WDATA_WIDTH;
elsif (RP_node'event and not(WP_node'event)) then
FIFO_pointer <= FIFO_pointer - RDATA_WIDTH;
end if;
end process FIFO_CAP_POINTER;
-- READ_POINTER_CTRL_V2 instance for FIFO
FIFO_RPC_INST: READ_POINTER_CTRL_V2
generic map (
RPOINTER_WIDTH => RADDR_WIDTH
)
port map (
TERMINAL_COUNT => TC_R_node,
GLOBAL_RST => RST_node,
RESET_RP => RPRST_node,
READ_EN => RE_node,
READ_CLK => RCLK_node,
EMPTY_FLAG => EMPTY_reg,
READ_POINTER => RP_node
);
-- WRITE_POINTER_CTRL_V2 instance for FIFO
FIFO_WPC_INST: WRITE_POINTER_CTRL_V2
generic map (
WPOINTER_WIDTH => WADDR_WIDTH,
WDATA_WIDTH => WDATA_WIDTH
)
port map (
TERMINAL_COUNT => TC_W_node,
GLOBAL_RST => RST_node,
WRITE_EN => WE_node,
WRITE_CLK => WCLK_node,
FULL_FLAG => FULL_reg,
WRITE_POINTER => WP_node
);
-- FLAG_LOGIC_V2 instance for FIFO
FIFO_FL_INST: FLAG_LOGIC_V2
generic map (
WDATA_WIDTH => WDATA_WIDTH,
RDATA_WIDTH => RDATA_WIDTH,
AMFULL_X => ALMOST_FULL_X,
AMEMPTY_Y => ALMOST_EMPTY_Y
)
port map(
GLOBAL_RST => RST_node,
FIFO_CAP => FIFO_capacity,
FIFO_PTR => FIFO_pointer,
FULL_D => FULL_reg,
EMPTY_D => EMPTY_reg,
AMFULL_D => AMFULL_reg,
AMEMPTY_D => AMEMPTY_reg
);
-- BRAM instance for FIFO
FIFO_BRAM_INST: SC_BRAM_16K_L
generic map(
WADDR_WIDTH_A => WADDR_WIDTH,
RADDR_WIDTH_A => RADDR_WIDTH,
WADDR_WIDTH_B => WADDR_WIDTH,
RADDR_WIDTH_B => RADDR_WIDTH,
WDATA_WIDTH_A => WDATA_WIDTH,
RDATA_WIDTH_A => RDATA_WIDTH,
WDATA_WIDTH_B => WDATA_WIDTH,
RDATA_WIDTH_B => RDATA_WIDTH,
ARRAY_SIZE => open,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => WP_node,
WEA => WE_reg,
WDA => DI_reg,
RADA => RP_node,
REA => RE_reg,
RDA => DO_node,
WADB => WP_node,
WEB => GND_sig,
WDB => DI_reg,
RADB => RP_node,
REB => GND_sig,
RDB => open
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- DPRAM: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_DP_RAM.vhd
-- Description: Single Port BRAM behavioral model.
-- History:
-- May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
LIBRARY ieee, std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.all;
USE work.components.all;
-- ************************************************************************
-- Entity definition
-- Draft "generic" members
-- ************************************************************************
entity SC_DPRAM_16K_L is
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
ADDR_WIDTH_A : integer := 13;
DATA_WIDTH_A : integer := 2;
ADDR_WIDTH_B : integer := 14;
DATA_WIDTH_B : integer := 1;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
CENA : in STD_LOGIC ;
CLKA : in STD_LOGIC ;
WRA : in STD_LOGIC ;
CSA : in STD_LOGIC_VECTOR (1 downto 0);
RSTA : in STD_LOGIC ;
DIA : in STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
ADA : in STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
DOA : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
CENB : in STD_LOGIC ;
CLKB : in STD_LOGIC ;
WRB : in STD_LOGIC ;
CSB : in STD_LOGIC_VECTOR (1 downto 0);
RSTB : in STD_LOGIC ;
DIB : in STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
ADB : in STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
DOB : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
);
end SC_DPRAM_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_DPRAM_16K_L is
component SC_BRAM_16K_L
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (DATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**ADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to DATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + DATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
-- Signal Declaration
signal CENA_node : STD_LOGIC := 'X';
signal CLKA_node : STD_LOGIC := 'X';
signal WRA_node : STD_LOGIC := 'X';
signal CSA_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RSTA_node : STD_LOGIC := 'X';
signal DIA_node : STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
signal ADA_node : STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0) := (others => '0');
signal DOA_node : STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
signal DIA_reg : STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
signal ADA_reg : STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0) := (others => 'X');
signal ENA_reg : STD_LOGIC := 'X';
signal RENA_reg : STD_LOGIC := 'X';
signal CENB_node : STD_LOGIC := 'X';
signal CLKB_node : STD_LOGIC := 'X';
signal WRB_node : STD_LOGIC := 'X';
signal CSB_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RSTB_node : STD_LOGIC := 'X';
signal DIB_node : STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
signal ADB_node : STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0) := (others => 'X');
signal DOB_node : STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
signal DIB_reg : STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
signal ADB_reg : STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0) := (others => 'X');
signal ENB_reg : STD_LOGIC := 'X';
signal RENB_reg : STD_LOGIC := 'X';
signal v_MEM : STD_LOGIC_VECTOR(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
signal v_ADA : INTEGER;
signal v_ADB : INTEGER;
-- architecture
begin
CENA_node <= CENA;
CLKA_node <= CLKA;
WRA_node <= WRA;
CSA_node <= CSA;
RSTA_node <= RSTA;
DIA_node <= DIA;
ADA_node <= ADA;
-- DOA <= DOA_node;
CENB_node <= CENB;
CLKB_node <= CLKB;
WRB_node <= WRB;
CSB_node <= CSB;
RSTB_node <= RSTB;
DIB_node <= DIB;
ADB_node <= ADB;
-- DOB <= DOB_node;
init_process : process
variable v_INI_DONE : boolean := FALSE;
variable v_MEM_i : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
begin
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM_i);
v_INI_DONE := TRUE;
end if;
v_MEM <= v_MEM_i;
wait;
end process;
process(ADA_node, ADB_node)
begin
if (Valid_Address(ADA_node) = TRUE) then
v_ADA <= CONV_INTEGER(ADA_node);
end if;
if (Valid_Address(ADB_node) = TRUE) then
v_ADB <= CONV_INTEGER(ADB_node);
end if;
end process;
-- Register Port A DI/ AD / Enable inputs
register_A_inputs: process (CLKA_node, RSTA_node)
begin
if (RSTA_node = '1') then
DIA_reg <= (others =>'0');
ADA_reg <= (others =>'0');
ENA_reg <= '0';
RENA_reg <= '1';
elsif (CLKA_node'event and CLKA_node = '1') then
if (CENA_node = '1') then
DIA_reg <= DIA_node;
ADA_reg <= ADA_node;
ENA_reg <= WRA_node and CSA_node(0) and CSA_node(1);
RENA_reg <= '1';
end if;
end if;
end process register_A_inputs;
-- Register Port B DI/ AD / Enable inputs
register_B_inputs: process (CLKB_node, RSTB_node)
begin
if (RSTB_node = '1') then
DIB_reg <= (others =>'0');
ADB_reg <= (others =>'0');
ENB_reg <= '0';
RENB_reg <= '1';
elsif (CLKB_node'event and CLKB_node = '1') then
if (CENB_node = '1') then
DIB_reg <= DIB_node;
ADB_reg <= ADB_node;
ENB_reg <= WRB_node and CSB_node(0) and CSB_node(1);
RENB_reg <= '1';
end if;
end if;
end process register_B_inputs;
v_MEM_process: process (CLKA_node, CLKB_node)
begin
if (ENA_reg = '1' and CENA_node = '1') then
if (CLKA_node'event and CLKA_node = '1') then
for i in 0 to DATA_WIDTH_A - 1 loop
v_MEM(v_ADA*DATA_WIDTH_A+i) <= DIA_node(i) after 1 ps;
end loop;
end if;
end if;
if (ENB_reg = '1' and CENB_node = '1') then
if (CLKB_node'event and CLKB_node = '1') then
for i in 0 to DATA_WIDTH_B - 1 loop
v_MEM(v_ADB*DATA_WIDTH_B+i) <= DIB_node(i) after 1 ps;
end loop;
end if;
end if;
end process;
DOA_output_process: process (RSTA_node, ENA_reg, CENA_node, DOA_node, CLKA_node)
begin
if (RSTA_node = '1') then
DOA <= (others => '0');
elsif (CLKA_node = '1' and CENA_node = '1') then
if (ENA_reg = '1') then
if (AWRITE_MODE = "RD_BEFORE_WR") then
for j in 0 to DATA_WIDTH_A - 1 loop
DOA(j) <= v_MEM(v_ADA*DATA_WIDTH_A+j);
end loop;
else
DOA <= DOA_node;
end if;
else
DOA <= DOA_node;
end if;
end if;
end process;
DOB_output_process: process (RSTB_node, ENB_reg, CENB_node, DOB_node, CLKB_node)
begin
if (RSTB_node = '1') then
DOB <= (others => '0');
elsif (CLKB_node = '1' and CENB_node = '1') then
if (ENB_reg = '1') then
if (BWRITE_MODE = "RD_BEFORE_WR") then
for j in 0 to DATA_WIDTH_B - 1 loop
DOB(j) <= v_MEM(v_ADB*DATA_WIDTH_B+j);
end loop;
else
DOB <= DOB_node;
end if;
else
DOB <= DOB_node;
end if;
end if;
end process;
-- BRAM instance for SPRAM
DPRAM_INST: SC_BRAM_16K_L
generic map(
AWRITE_MODE => AWRITE_MODE,
BWRITE_MODE => BWRITE_MODE,
WADDR_WIDTH_A => ADDR_WIDTH_A,
RADDR_WIDTH_A => ADDR_WIDTH_A,
WADDR_WIDTH_B => ADDR_WIDTH_B,
RADDR_WIDTH_B => ADDR_WIDTH_B,
WDATA_WIDTH_A => DATA_WIDTH_A,
RDATA_WIDTH_A => DATA_WIDTH_A,
WDATA_WIDTH_B => DATA_WIDTH_B,
RDATA_WIDTH_B => DATA_WIDTH_B,
ARRAY_SIZE => ARRAY_SIZE,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => ADA_reg,
WEA => ENA_reg,
WDA => DIA_reg,
RADA => ADA_reg,
REA => RENA_reg,
RDA => DOA_node,
WADB => ADB_reg,
WEB => ENB_reg,
WDB => DIB_reg,
RADB => ADB_reg,
REB => RENB_reg,
RDB => DOB_node
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- PseudoDPRAM: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_PDP_RAM.vhd
-- Description: Pseudo Dual Port BRAM behavioral model.
-- History:
-- May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
-- ************************************************************************
-- Entity definition
-- Draft "generic" members
-- ************************************************************************
entity SC_PDPRAM_16K_L is
generic (
WADDR_WIDTH : integer := 13;
WDATA_WIDTH : integer := 2;
RADDR_WIDTH : integer := 13;
RDATA_WIDTH : integer := 2;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WCEN : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
WE : in STD_LOGIC ;
WCS : in STD_LOGIC_VECTOR (1 downto 0);
RCLK : in STD_LOGIC;
RCEN : in STD_LOGIC;
RST : in STD_LOGIC ;
WD : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
WAD : in STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
RAD : in STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
RD : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end SC_PDPRAM_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_PDPRAM_16K_L is
component SC_BRAM_16K_L
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
-- Signal Declaration
signal WCEN_node : STD_LOGIC := 'X';
signal WCLK_node : STD_LOGIC := 'X';
signal WE_node : STD_LOGIC := 'X';
signal WCS_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RCEN_node : STD_LOGIC := 'X';
signal RCLK_node : STD_LOGIC := 'X';
signal RST_node : STD_LOGIC := 'X';
signal WD_node : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal WAD_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
signal RD_node : STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');
signal RAD_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal WD_reg : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal WAD_reg : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
signal RAD_reg : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal EN_reg : STD_LOGIC := 'X';
signal REN_reg : STD_LOGIC := 'X';
signal GND_sig : STD_LOGIC;
signal VCC_sig : STD_LOGIC;
-- architecture
begin
GND_sig <= '0';
VCC_sig <= '1';
WCEN_node <= WCEN;
WCLK_node <= WCLK;
WE_node <= WE;
WCS_node <= WCS;
RCEN_node <= RCEN;
RCLK_node <= RCLK;
RST_node <= RST;
WD_node <= WD;
WAD_node <= WAD;
RAD_node <= RAD;
-- RD <= RD_node;
RD_output : process (RD_node, RST_node)
begin
if (RST_node = '1') then
RD <= (others => '0');
else
RD <= RD_node;
end if;
end process;
-- Register WD/WAD/ Enable inputs
register_write_inputs: process (WCLK_node, RST_node)
begin
if (RST_node = '1') then
WD_reg <= (others =>'0');
WAD_reg <= (others =>'0');
EN_reg <= '0';
REN_reg <= '1';
elsif (WCLK_node'event and WCLK_node = '1') then
if (WCEN_node = '1') then
WD_reg <= WD_node;
WAD_reg <= WAD_node;
EN_reg <= WE_node and WCS_node(0) and WCS_node(1);
REN_reg <= '1';
end if;
end if;
end process register_write_inputs;
-- Register RAD inputs
register_read_inputs: process (RCLK_node, RST_node)
begin
if (RST_node = '1') then
RAD_reg <= (others =>'0');
elsif (RCLK_node'event and RCLK_node = '1') then
if (RCEN_node = '1') then
RAD_reg <= RAD_node;
end if;
end if;
end process register_read_inputs;
-- BRAM instance for SPRAM
PDPRAM_INST: SC_BRAM_16K_L
generic map(
WADDR_WIDTH_A => WADDR_WIDTH,
RADDR_WIDTH_A => RADDR_WIDTH,
WADDR_WIDTH_B => WADDR_WIDTH,
RADDR_WIDTH_B => RADDR_WIDTH,
WDATA_WIDTH_A => WDATA_WIDTH,
RDATA_WIDTH_A => RDATA_WIDTH,
WDATA_WIDTH_B => WDATA_WIDTH,
RDATA_WIDTH_B => RDATA_WIDTH,
ARRAY_SIZE => ARRAY_SIZE,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => WAD_reg,
WEA => EN_reg,
WDA => WD_reg,
RADA => RAD_reg,
REA => REN_reg,
RDA => RD_node,
WADB => WAD_reg,
WEB => GND_sig,
WDB => WD_reg,
RADB => RAD_reg,
REB => GND_sig,
RDB => open
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- SPRAM: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_SP_RAM.vhd
-- Description: Single Port BRAM behavioral model.
-- History:
-- May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
LIBRARY ieee, std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.all;
USE work.components.all;
-- ************************************************************************
-- Entity definition
-- Draft "generic" members
-- ************************************************************************
entity SC_SPRAM_16K_L is
generic (
WRITE_MODE : string := "NORMAL";
ADDR_WIDTH : integer := 13;
DATA_WIDTH : integer := 2;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FILE : string := "qq.dat"
);
port (
CEN : in STD_LOGIC ;
CLK : in STD_LOGIC ;
WR : in STD_LOGIC ;
CS : in STD_LOGIC_VECTOR (1 downto 0);
RST : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
AD : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end SC_SPRAM_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_SPRAM_16K_L is
component SC_BRAM_16K_L
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 1;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (DATA_WIDTH downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**ADDR_WIDTH)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to DATA_WIDTH - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + DATA_WIDTH;
end loop;
end READ_MEM_INIT_FILE;
-- Signal Declaration
signal CEN_node : STD_LOGIC := 'X';
signal CLK_node : STD_LOGIC := 'X';
signal WR_node : STD_LOGIC := 'X';
signal CS_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RST_node : STD_LOGIC := 'X';
signal DI_node : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
signal AD_node : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => '0');
signal DO_node : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
signal DI_reg : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
signal AD_reg : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => 'X');
signal EN_reg : STD_LOGIC := 'X';
signal REN_reg : STD_LOGIC := 'X';
signal GND_sig : STD_LOGIC;
signal VCC_sig : STD_LOGIC;
signal v_MEM : STD_LOGIC_VECTOR((2**ADDR_WIDTH) * DATA_WIDTH-1 downto 0) := (others => '0');
signal v_AD : integer;
-- architecture
begin
GND_sig <= '0';
VCC_sig <= '1';
CEN_node <= CEN;
CLK_node <= CLK;
WR_node <= WR;
CS_node <= CS;
RST_node <= RST;
DI_node <= DI;
AD_node <= AD;
-- DO <= DO_node;
init_process : process
variable v_INI_DONE : boolean := FALSE;
variable v_MEM_i : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
begin
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM_i);
v_INI_DONE := TRUE;
end if;
v_MEM <= v_MEM_i;
wait;
end process;
process(AD_node)
begin
if (Valid_Address(AD_node) = TRUE) then
v_AD <= CONV_INTEGER(AD_node);
end if;
end process;
-- Register DI/ AD / Enable inputs
register_inputs: process (CLK_node, RST_node)
begin
if (RST_node = '1') then
DI_reg <= (others =>'0');
AD_reg <= (others =>'0');
EN_reg <= '0';
REN_reg <= '1';
elsif (CLK_node'event and CLK_node = '1') then
if (CEN_node = '1') then
DI_reg <= DI_node;
AD_reg <= AD_node;
EN_reg <= WR_node and CS_node(0) and CS_node(1);
REN_reg <= '1';
end if;
end if;
end process register_inputs;
v_MEM_process: process (EN_reg, DI_node, v_AD, CLK_node)
begin
if (CLK_node'event and CLK_node = '1') then
if (EN_reg = '1' and CEN_node = '1') then
for i in 0 to DATA_WIDTH - 1 loop
v_MEM(v_AD*DATA_WIDTH+i) <= DI_node(i) after 1 ps;
end loop;
end if;
end if;
end process;
DO_output_process: process (RST_node, EN_reg, DO_node, CLK_node)
begin
if (RST_node = '1') then
DO <= (others => '0');
elsif (CLK_node = '1' and CEN_node = '1') then
if (EN_reg = '1') then
if (WRITE_MODE = "RD_BEFORE_WR") then
for j in 0 to DATA_WIDTH - 1 loop
DO(j) <= v_MEM(v_AD*DATA_WIDTH+j);
end loop;
else
DO <= DO_node;
end if;
else
DO <= DO_node;
end if;
end if;
end process;
-- BRAM instance for SPRAM
SPRAM_INST: SC_BRAM_16K_L
generic map(
AWRITE_MODE => WRITE_MODE,
WADDR_WIDTH_A => ADDR_WIDTH,
RADDR_WIDTH_A => ADDR_WIDTH,
WADDR_WIDTH_B => ADDR_WIDTH,
RADDR_WIDTH_B => ADDR_WIDTH,
WDATA_WIDTH_A => DATA_WIDTH,
RDATA_WIDTH_A => DATA_WIDTH,
WDATA_WIDTH_B => DATA_WIDTH,
RDATA_WIDTH_B => DATA_WIDTH,
ARRAY_SIZE => open,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => AD_reg,
WEA => EN_reg,
WDA => DI_reg,
RADA => AD_reg,
REA => REN_reg,
RDA => DO_node,
WADB => AD_reg,
WEB => GND_sig,
WDB => DI_reg,
RADB => AD_reg,
REB => GND_sig,
RDB => open
);
end LATTICE_BEHAV;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
entity fifo_dc is
generic (
module_type : string := "FIFO_DC";
module_width : integer := 1;
module_widthu : integer := 1;
module_numwords : integer := 2;
module_amfull_flag : integer := 1;
module_amempty_flag : integer := 1;
module_hint : string := "UNUSED");
port (
Data : in std_logic_vector (module_width-1 downto 0);
WrClock : in std_logic;
WrEn : in std_logic;
RdClock : in std_logic;
RdEn : in std_logic;
Reset : in std_logic;
RPReset : in std_logic;
Q : out std_logic_vector (module_width-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
AlmostFull : out std_logic;
AlmostEmpty : out std_logic);
end fifo_dc;
architecture fun_simulation of fifo_dc is
component SC_FIFO_16K_L
generic (
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 9;
RDATA_WIDTH : integer := 32;
ALMOST_FULL_X : integer := 1;
ALMOST_EMPTY_Y : integer := 1;
MEM_INIT_FLAG : integer := 0;
TERMINAL_COUNT : integer := 511;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end component;
signal Rst, FullIn, EmptyIn : std_logic;
begin
Rst <= '1';
FullIn <= '0';
EmptyIn <= '1';
SC_FIFO_inst : SC_FIFO_16K_L
generic map (
WADDR_WIDTH => module_widthu,
WDATA_WIDTH => module_width,
RADDR_WIDTH => module_widthu,
RDATA_WIDTH => module_width,
ALMOST_FULL_X => module_amfull_flag,
ALMOST_EMPTY_Y => module_amempty_flag,
MEM_INIT_FLAG => 0,
TERMINAL_COUNT => module_numwords - 1,
MEM_INIT_FILE => open )
port map (
WE => WrEn,
WCLK => WrClock,
RST => Reset,
RPRST => RPReset,
RE => RdEn,
RCLK => RdClock,
FULLIN => FullIn,
EMPTYIN => EmptyIn,
DI => Data,
FULL => Full,
EMPTY => Empty,
AMFULL => AlmostFull,
AMEMPTY => AlmostEmpty,
DO => Q
);
end;library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
entity fifo_dcx is
generic (
module_type : string := "FIFO_DCX";
module_widthw : integer := 1;
module_widthr : integer := 1;
module_widthuw : integer := 1;
module_widthur : integer := 1;
module_numwordsw : integer := 2;
module_numwordsr : integer := 2;
module_amfull_flag : integer := 1;
module_amempty_flag : integer := 1;
module_hint : string := "UNUSED");
port (
Data : in std_logic_vector (module_widthw-1 downto 0);
WrClock : in std_logic;
WrEn : in std_logic;
RdClock : in std_logic;
RdEn : in std_logic;
Reset : in std_logic;
RPReset : in std_logic;
Q : out std_logic_vector (module_widthr-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
AlmostFull : out std_logic;
AlmostEmpty : out std_logic);
end fifo_dcx;
architecture fun_simulation of fifo_dcx is
component SC_FIFO_V2_16K_L
generic (
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 9;
RDATA_WIDTH : integer := 32;
ALMOST_FULL_X : integer := 1;
ALMOST_EMPTY_Y : integer := 1;
MEM_INIT_FLAG : integer := 0;
TERMINAL_COUNT : integer := 511;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end component;
signal FullIn, EmptyIn : std_logic;
begin
FullIn <= '0';
EmptyIn <= '1';
SC_FIFO_inst : SC_FIFO_V2_16K_L
generic map (
WADDR_WIDTH => module_widthuw,
WDATA_WIDTH => module_widthw,
RADDR_WIDTH => module_widthur,
RDATA_WIDTH => module_widthr,
ALMOST_FULL_X => module_amfull_flag,
ALMOST_EMPTY_Y => module_amempty_flag,
MEM_INIT_FLAG => 0,
TERMINAL_COUNT => module_numwordsw - 1,
MEM_INIT_FILE => open )
port map (
WE => WrEn,
WCLK => WrClock,
RST => Reset,
RPRST => RPReset,
RE => RdEn,
RCLK => RdClock,
FULLIN => FullIn,
EMPTYIN => EmptyIn,
DI => Data,
FULL => Full,
EMPTY => Empty,
AMFULL => AlmostFull,
AMEMPTY => AlmostEmpty,
DO => Q
);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use work.components.all;
entity ram_dp is
generic(
module_type : string := "RAM_DP";
module_widthw : integer := 1;
module_widthr : integer := 1;
module_numwordsw : integer := 1;
module_widthadw : integer := 1;
module_widthadr : integer := 1;
module_numwordsr : integer := 1;
module_indata : string := "REGISTERED";
module_outdata : string := "UNREGISTERED";
module_addressw_control : string := "REGISTERED";
module_addressr_control : string := "REGISTERED";
module_gsr : string := "DISABLED";
module_hint : string := "UNUSED";
module_init_file : string := "");
port(
Data : in std_logic_vector (module_widthw-1 downto 0);
WrAddress : in std_logic_vector (module_widthadw-1 downto 0);
RdAddress : in std_logic_vector (module_widthadr-1 downto 0);
WrClock : in std_logic;
WrClockEn : in std_logic;
RdClock : in std_logic;
RdClockEn : in std_logic;
WE : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector (module_widthr-1 downto 0));
end ram_dp;
architecture fun_simulation of ram_dp is
component SC_PDPRAM_16K_L
generic (
WADDR_WIDTH : integer := 13;
WDATA_WIDTH : integer := 2;
RADDR_WIDTH : integer := 13;
RDATA_WIDTH : integer := 2;
ARRAY_SIZE : integer := 511;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WCEN : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
WE : in STD_LOGIC ;
WCS : in STD_LOGIC_VECTOR (1 downto 0);
RCLK : in STD_LOGIC;
RCEN : in STD_LOGIC;
RST : in STD_LOGIC ;
WD : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
WAD : in STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
RAD : in STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
RD : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end component;
signal cs : std_logic_vector ( 1 downto 0);
signal Q_K : std_logic_vector (module_widthr-1 downto 0);
signal Q_K_reg : std_logic_vector (module_widthr-1 downto 0);
CONSTANT module_init_flag : integer := init_flag(module_init_file);
begin
cs <= "11";
OutRegister : process(RdClock, Reset)
begin
if (Reset = '1') then
Q_K_reg <= (others => '0');
elsif (RdClock'EVENT and RdClock = '1') then
if (RdClockEn = '1') then
Q_K_reg <= Q_K;
elsif (RdClockEn /= '0') then
Q_K_reg <= (others => 'X');
end if;
end if;
end process;
SelectOut : process (Q_K , Q_K_reg)
begin
if(module_outdata = "UNREGISTERED" and module_addressr_control = "REGISTERED") then
Q <= Q_K;
elsif(module_outdata = "REGISTERED" and module_addressr_control = "REGISTERED") then
Q <= Q_K_reg;
elsif(module_indata = "UNREGISTERED") then
assert false report "Error: module_indata should be REGISTERED" severity ERROR;
elsif(module_addressw_control = "UNREGISTERED") then
assert false report "Error: module_addressw_control should be REGISTERED" severity ERROR;
elsif(module_addressr_control = "UNREGISTERED") then
assert false report "Error: module_addressr_control should be REGISTERED" severity ERROR;
end if;
end process;
PDPRAM_inst : SC_PDPRAM_16K_L
generic map(
WADDR_WIDTH => module_widthadw,
WDATA_WIDTH => module_widthw,
RADDR_WIDTH => module_widthadr,
RDATA_WIDTH => module_widthr,
MEM_INIT_FLAG => module_init_flag,
ARRAY_SIZE => module_numwordsw*module_widthw,
MEM_INIT_FILE => module_init_file)
port map(
WCEN => WrClockEn,
WCLK => WrClock,
WE => WE,
WCS => cs,
RCLK => RdClock,
RCEN => RdClockEn,
RST => Reset,
WD => Data,
WAD => WrAddress,
RAD => RdAddress,
RD => Q_K
);
end;library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use work.components.all;
entity ram_dp_true is
generic (
module_type : string := "RAM_DP_TRUE";
module_widtha : positive;
module_widthada : positive;
module_numwordsa : positive;
module_widthb : positive;
module_widthadb : positive;
module_numwordsb : positive;
module_indata : string :="REGISTERED";
module_outdata : string :="UNREGISTERED";
module_addressa_control : string :="REGISTERED";
module_addressb_control : string :="REGISTERED";
module_init_file : string := "";
module_hint : string :="UNUSED";
module_gsr : string := "DISABLED";
module_writemode_a : string := "NORMAL";
module_writemode_b : string := "NORMAL");
port (
DataInA : in std_logic_vector(module_widtha-1 downto 0);
AddressA : in std_logic_vector(module_widthada-1 downto 0);
DataInB : in std_logic_vector(module_widthb-1 downto 0);
AddressB : in std_logic_vector(module_widthadb-1 downto 0);
ClockA : in std_logic := '0';
ClockEnA : in std_logic := '0';
ClockB : in std_logic := '0';
ClockEnB : in std_logic := '0';
WrA : in std_logic;
WrB : in std_logic;
ResetA : in std_logic;
ResetB : in std_logic;
QA : out std_logic_vector(module_widtha-1 downto 0);
QB : out std_logic_vector(module_widthb-1 downto 0));
end ram_dp_true;
architecture fun_simulation of ram_dp_true is
component SC_DPRAM_16K_L
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
ADDR_WIDTH_A : integer := 13;
DATA_WIDTH_A : integer := 2;
ADDR_WIDTH_B : integer := 14;
DATA_WIDTH_B : integer := 1;
MEM_INIT_FLAG : integer := 0;
ARRAY_SIZE : integer := 511;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
CENA : in STD_LOGIC ;
CLKA : in STD_LOGIC ;
WRA : in STD_LOGIC ;
CSA : in STD_LOGIC_VECTOR (1 downto 0);
RSTA : in STD_LOGIC ;
DIA : in STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
ADA : in STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
DOA : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
CENB : in STD_LOGIC ;
CLKB : in STD_LOGIC ;
WRB : in STD_LOGIC ;
CSB : in STD_LOGIC_VECTOR (1 downto 0);
RSTB : in STD_LOGIC ;
DIB : in STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
ADB : in STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
DOB : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
);
end component;
signal CS : std_logic_vector ( 1 downto 0);
signal QA_int, QA_int_reg : std_logic_vector(module_widtha-1 downto 0);
signal QB_int, QB_int_reg : std_logic_vector(module_widthb-1 downto 0);
CONSTANT module_init_flag : integer := init_flag(module_init_file);
begin
CS <= "11";
OutRegisterA : process(ClockA, ResetA)
begin
if(ResetA = '1') then QA_int_reg <= (others => '0');
elsif (ClockA'EVENT and ClockA = '1') then
if (ClockEnA = '1') then
QA_int_reg <= QA_int;
elsif (ClockEnA /= '0') then
QA_int_reg <= (others => 'X');
end if;
end if;
end process;
OutRegisterB : process(ClockB, ResetB)
begin
if(ResetB = '1') then QB_int_reg <= (others => '0');
elsif (ClockB'EVENT and ClockB = '1') then
if (ClockEnB = '1') then
QB_int_reg <= QB_int;
elsif (ClockEnB /= '0') then
QB_int_reg <= (others => 'X');
end if;
end if;
end process;
SelectA : process (QA_int , QA_int_reg)
begin
if(module_outdata = "UNREGISTERED" and module_addressa_control = "REGISTERED") then
QA <= QA_int;
elsif(module_outdata = "REGISTERED" and module_addressa_control = "REGISTERED") then
QA <= QA_int_reg;
elsif(module_indata = "UNREGISTERED") then
assert false report "Error: module_indata should be REGISTERED" severity ERROR;
elsif(module_addressa_control = "UNREGISTERED") then
assert false report "Error: module_addressa_control should be REGISTERED" severity ERROR;
end if;
end process;
SelectB : process (QB_int , QB_int_reg)
begin
if(module_outdata = "UNREGISTERED" and module_addressb_control = "REGISTERED") then
QB <= QB_int;
elsif(module_outdata = "REGISTERED" and module_addressb_control = "REGISTERED") then
QB <= QB_int_reg;
elsif(module_addressa_control = "UNREGISTERED") then
assert false report "Error: module_addressa_control should be REGISTERED" severity ERROR;
end if;
end process;
RAM_DP_INST : SC_DPRAM_16K_L
generic map(
ADDR_WIDTH_A => module_widthada,
DATA_WIDTH_A => module_widtha,
ADDR_WIDTH_B => module_widthadb,
DATA_WIDTH_B => module_widthb,
MEM_INIT_FLAG => module_init_flag,
ARRAY_SIZE => module_numwordsa*module_widtha,
MEM_INIT_FILE => module_init_file,
AWRITE_MODE => module_writemode_a,
BWRITE_MODE => module_writemode_b
)
port map (
CENA => ClockEnA,
CLKA => ClockA,
WRA => WrA,
CSA => CS,
RSTA => ResetA,
DIA => DataInA,
ADA => AddressA,
DOA => QA_int,
CENB => ClockEnB,
CLKB => ClockB,
WRB => WrB,
CSB => CS,
RSTB => ResetB,
DIB => DataInB,
ADB => AddressB,
DOB => QB_int
);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use work.components.all;
entity ram_dq is
generic(
module_type : string := "RAM_DQ";
module_width : integer := 1;
module_numwords : integer := 1;
module_widthad : integer := 1;
module_indata : string := "REGISTERED";
module_outdata : string := "UNREGISTERED";
module_address_control : string := "REGISTERED";
module_init_file : string := "";
module_hint : string := "UNUSED";
module_gsr : string := "DISABLED";
module_writemode : string := "NORMAL");
port(
Data : in std_logic_vector (module_width-1 downto 0);
Address : in std_logic_vector (module_widthad-1 downto 0);
Clock : in std_logic;
ClockEn : in std_logic;
WE : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector (module_width-1 downto 0));
end ram_dq;
architecture fun_simulation of ram_dq is
component SC_SPRAM_16K_L
generic (
WRITE_MODE : string := "NORMAL";
ADDR_WIDTH : integer := 13;
DATA_WIDTH : integer := 2;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 511;
MEM_INIT_FILE : string := "qq.dat"
);
port (
CEN : in STD_LOGIC ;
CLK : in STD_LOGIC ;
WR : in STD_LOGIC ;
CS : in STD_LOGIC_VECTOR (1 downto 0);
RST : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
AD : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
signal cs : std_logic_vector (1 downto 0);
signal Q_K : std_logic_vector (module_width-1 downto 0);
signal Q_K_reg : std_logic_vector (module_width-1 downto 0);
CONSTANT module_init_flag : integer := init_flag(module_init_file);
begin
cs <= "11";
OutRegister : process(Clock, Reset)
begin
if (Reset = '1') then
Q_K_reg <= (others => '0');
elsif (Clock'EVENT and Clock = '1') then
if (ClockEn = '1') then
Q_K_reg <= Q_K;
elsif (ClockEn /= '0') then
Q_K_reg <= (others => 'X');
end if;
end if;
end process;
SelectOut : process (Q_K , Q_K_reg)
begin
if(module_outdata = "UNREGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K;
elsif(module_outdata = "REGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K_reg;
elsif(module_indata = "UNREGISTERED") then
assert false report "Error: module_indata should be REGISTERED" severity ERROR;
elsif(module_address_control = "UNREGISTERED") then
assert false report "Error: module_address_control should be REGISTERED" severity ERROR;
end if;
end process;
SPRAM_inst : SC_SPRAM_16K_L
generic map (
ADDR_WIDTH => module_widthad,
DATA_WIDTH => module_width,
MEM_INIT_FLAG => module_init_flag,
ARRAY_SIZE => module_numwords * module_width,
MEM_INIT_FILE => module_init_file,
WRITE_MODE => module_writemode)
port map (
CEN => ClockEn,
CLK => Clock,
WR => WE,
CS => cs,
RST => Reset,
DI => Data,
AD => Address,
DO => Q_K
);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
entity rom is
generic (
module_type : string := "ROM";
module_width : integer := 1;
module_numwords : integer := 1;
module_widthad : integer := 1;
module_outdata : string := "REGISTERED";
module_address_control : string := "REGISTERED";
module_init_file : string := "init_file";
module_gsr : string := "DISABLED";
module_hint : string := "UNUSED");
port (
Address : in std_logic_vector (module_widthad-1 downto 0);
OutClock : in std_logic;
OutClockEn : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector (module_width-1 downto 0));
end rom;
architecture fun_simulation of rom is
component SC_SPRAM_16K_L
generic (
ADDR_WIDTH : integer := 13;
DATA_WIDTH : integer := 2;
ARRAY_SIZE : integer := 511;
MEM_INIT_FLAG : integer := 1;
MEM_INIT_FILE : string := "qq.dat"
);
port (
CEN : in STD_LOGIC ;
CLK : in STD_LOGIC ;
WR : in STD_LOGIC ;
CS : in STD_LOGIC_VECTOR (1 downto 0);
RST : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
AD : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
signal cs : std_logic_vector ( 1 downto 0);
signal DI_sig : std_logic_vector (module_width-1 downto 0);
signal WE_sig : std_logic;
signal Q_K : std_logic_vector (module_width-1 downto 0);
signal Q_K_reg : std_logic_vector (module_width-1 downto 0);
begin
cs <= "11";
WE_sig <= '0';
OutRegister : process(OutClock, Reset)
begin
if (Reset = '1') then
Q_K_reg <= (others => '0');
elsif (OutClock'EVENT and OutClock = '1') then
if(OutClockEn = '1') then
Q_K_reg <= Q_K;
elsif(OutClockEn /= '0') then
Q_K_reg <= (others => 'X' );
end if;
end if;
end process;
SelectOut : process (Q_K , Q_K_reg)
begin
if(module_outdata = "UNREGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K;
elsif(module_outdata = "REGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K_reg;
elsif(module_address_control = "UNREGISTERED") then
assert false report "Error: module_address_control should be REGISTERED" severity ERROR;
end if;
end process;
SPRAM_inst : SC_SPRAM_16K_L
generic map(
ADDR_WIDTH => module_widthad,
DATA_WIDTH => module_width,
MEM_INIT_FLAG => 1,
ARRAY_SIZE => module_numwords * module_width,
MEM_INIT_FILE => module_init_file)
port map(
CEN => OutClockEn,
CLK => OutClock,
WR => WE_sig,
CS => cs,
RST => Reset,
DI => DI_sig,
AD => Address,
DO => Q_K
);
end;
|
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A.
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 1-408-826-6000 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
--
-- Simulation Library File for EC/XP
--
-- $Header: G:\\CVS_REPOSITORY\\CVS_MACROS/LEON3SDE/ALTERA/grlib-eval-1.0.4/lib/tech/ec/ec/ORCA_L.vhd,v 1.1 2005/12/06 13:00:23 tame Exp $
--
library std;
use std.textio.all;
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- ************************************************************************
-- Entity definition
-- "generic" members
-- ************************************************************************
entity SC_BRAM_16K_L is
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 262144;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := ""
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end SC_BRAM_16K_L;
-- ************************************************************************
-- Architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_BRAM_16K_L is
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (WDATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to WDATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + WDATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------
--------- Local signals used to propagate input wire delay ---------------
signal WADA_node : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node : std_logic := 'X';
signal WDA_node : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node : std_logic := 'X';
signal RDA_node : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RDA_temp : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal WADB_node : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node : std_logic := 'X';
signal WDB_node : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node : std_logic := 'X';
signal RDB_node : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RDB_temp : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
-- architecture
begin
WADA_node <= WADA;
WEA_node <= WEA;
WDA_node <= WDA;
RADA_node <= RADA;
REA_node <= REA;
RDA <= RDA_TEMP;
WADB_node <= WADB;
WEB_node <= WEB;
WDB_node <= WDB;
RADB_node <= RADB;
REB_node <= REB;
RDB <= RDB_TEMP;
RDB_process: process(RDB_node, WEB_node)
begin
if (WEB_node = '1') then
if (BWRITE_MODE = "WRITETHROUGH") then
RDB_temp <= RDB_node;
elsif (BWRITE_MODE = "NORMAL") then
RDB_temp <= RDB_temp;
end if;
else
RDB_temp <= RDB_node;
end if;
end process;
RDA_process: process(RDA_node, WEA_node)
begin
if (WEA_node = '1') then
if (AWRITE_MODE = "WRITETHROUGH") then
RDA_temp <= RDA_node;
elsif (AWRITE_MODE = "NORMAL") then
RDA_temp <= RDA_temp;
end if;
else
RDA_temp <= RDA_node;
end if;
end process;
-----------------------------------------
--------- Behavior process -------------
-----------------------------------------
KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
--TSPEC: A note about sram initial values and rom mode:
-- If the user does not provide any values, ... default 0
-- for all ram locations in JECED
--QQ 7_17 variable v_MEM : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
variable v_MEM : std_logic_vector(ARRAY_SIZE*WDATA_WIDTH_A + WDATA_WIDTH_A - 1 downto 0) := ( others => '0' );
variable v_INI_DONE : boolean := FALSE;
variable v_WADDR_A : integer;
variable v_RADDR_A : integer;
variable v_WADDR_B : integer;
variable v_RADDR_B : integer;
variable v_WADDRA_Valid_Flag : boolean := TRUE;
variable v_WADDRB_Valid_Flag : boolean := TRUE;
variable v_RADDRA_Valid_Flag : boolean := TRUE;
variable v_RADDRB_Valid_Flag : boolean := TRUE;
begin -- Process
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
v_INI_DONE := TRUE;
end if;
-- Address Check
v_WADDRA_Valid_Flag := Valid_Address(WADA_node);
v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
v_RADDRA_Valid_Flag := Valid_Address(RADA_node);
v_RADDRB_Valid_Flag := Valid_Address(RADB_node);
if ( v_WADDRA_Valid_Flag = TRUE ) then
v_WADDR_A := CONV_INTEGER(WADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_WADDRB_Valid_Flag = TRUE ) then
v_WADDR_B := CONV_INTEGER(WADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressB of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRA_Valid_Flag = TRUE ) then
v_RADDR_A := CONV_INTEGER(RADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRB_Valid_Flag = TRUE ) then
v_RADDR_B := CONV_INTEGER(RADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressB of Port contains invalid bit!"
-- severity warning;
end if;
-- CHECK Operation
if (WEA = '1' and WEB = '1' and
not(
(v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B)
or
(v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
)
) then
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity warning;
end if;
-- MEM Operation
if (WEA_node = '1') then
v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
end if;
if (WEB_node = '1') then
v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
end if;
if (REA_node = '1') then
RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
-- else
-- RDA_node <= ( others => 'X');
end if;
if (REB_node = '1') then
RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
-- else
-- RDB_node <= ( others => 'X');
end if;
end process KERNEL_BEHAV;
end LATTICE_BEHAV;
-- ************************************************************************
--
-- Block Memory: Behavioral Model
-- The kernel of other RAM applications
-- ************************************************************************
--
-- Filename: SC_BLOCK_RAM_L.vhd
-- Description: BRAM behavioral model.
-- ************************************************************************
library std;
use std.textio.all;
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- ************************************************************************
-- Entity definition
-- "generic" members
-- ************************************************************************
entity SC_BRAM_16K_L_SYNC is
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 262144;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := ""
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
WCLK : in STD_LOGIC;
RCLK : in STD_LOGIC
);
end SC_BRAM_16K_L_SYNC;
-- ************************************************************************
-- Architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_BRAM_16K_L_SYNC is
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (WDATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to WDATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + WDATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------
--------- Local signals used to propagate input wire delay ---------------
signal WADA_node : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node : std_logic := 'X';
signal WDA_node : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node : std_logic := 'X';
signal RDA_node : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal WADB_node : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node : std_logic := 'X';
signal WDB_node : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node : std_logic := 'X';
signal RDB_node : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal WCLK_node : std_logic := 'X';
signal RCLK_node : std_logic := 'X';
-- architecture
begin
WADA_node <= WADA;
WEA_node <= WEA;
WDA_node <= WDA;
RADA_node <= RADA;
REA_node <= REA;
RDA <= RDA_node;
WADB_node <= WADB;
WEB_node <= WEB;
WDB_node <= WDB;
RADB_node <= RADB;
REB_node <= REB;
RDB <= RDB_node;
WCLK_node <= WCLK;
RCLK_node <= RCLK;
-----------------------------------------
--------- Behavior process -------------
-----------------------------------------
--KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
KERNEL_BEHAV : process( WCLK_node, RCLK_node)
--TSPEC: A note about sram initial values and rom mode:
-- If the user does not provide any values, ... default 0
-- for all ram locations in JECED
variable v_MEM : std_logic_vector(ARRAY_SIZE*WDATA_WIDTH_A - 1 downto 0) := ( others => '0' );
variable v_INI_DONE : boolean := FALSE;
variable v_WADDR_A : integer;
variable v_RADDR_A : integer;
variable v_WADDR_B : integer;
variable v_RADDR_B : integer;
variable v_WADDRA_Valid_Flag : boolean := TRUE;
variable v_WADDRB_Valid_Flag : boolean := TRUE;
variable v_RADDRA_Valid_Flag : boolean := TRUE;
variable v_RADDRB_Valid_Flag : boolean := TRUE;
begin -- Process
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
v_INI_DONE := TRUE;
end if;
-- Address Check
v_WADDRA_Valid_Flag := Valid_Address(WADA_node);
v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
v_RADDRA_Valid_Flag := Valid_Address(RADA_node);
v_RADDRB_Valid_Flag := Valid_Address(RADB_node);
if ( v_WADDRA_Valid_Flag = TRUE ) then
v_WADDR_A := CONV_INTEGER(WADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_WADDRB_Valid_Flag = TRUE ) then
v_WADDR_B := CONV_INTEGER(WADB_node);
else
-- assert (Now = 0 ps)
-- report "Write AddressB of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRA_Valid_Flag = TRUE ) then
v_RADDR_A := CONV_INTEGER(RADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRB_Valid_Flag = TRUE ) then
v_RADDR_B := CONV_INTEGER(RADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressB of Port contains invalid bit!"
-- severity warning;
end if;
-- CHECK Operation
if (WEA = '1' and WEB = '1' and
not(
(v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B)
or
(v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
)
) then
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity warning;
end if;
-- MEM Operation
if (WEA_node = '1' and WCLK_node'event and WCLK_node = '1' ) then
v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
end if;
if (WEB_node = '1' and WCLK_node'event and WCLK_node = '1') then
v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
end if;
if (REA_node = '1' and RCLK_node'event and RCLK_node = '1') then
RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
-- else
-- RDA_node <= ( others => 'X');
end if;
if (REB_node = '1' and RCLK_node'event and RCLK_node = '1') then
RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
-- else
-- RDB_node <= ( others => 'X');
end if;
end process KERNEL_BEHAV;
end LATTICE_BEHAV;
library std;
use std.textio.all;
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- ************************************************************************
-- Entity definition
-- "generic" members
-- ************************************************************************
entity SC_BRAM_PDP_16K_L is
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 262144;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := ""
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end SC_BRAM_PDP_16K_L;
-- ************************************************************************
-- Architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_BRAM_PDP_16K_L is
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (WDATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to WDATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + WDATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------
--------- Local signals used to propagate input wire delay ---------------
signal WADA_node : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node : std_logic := 'X';
signal WDA_node : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node : std_logic := 'X';
signal RDA_node : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal WADB_node : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node : std_logic := 'X';
signal WDB_node : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node : std_logic := 'X';
signal RDB_node : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
-- architecture
begin
WADA_node <= WADA;
WEA_node <= WEA;
WDA_node <= WDA;
RADA_node <= RADA;
REA_node <= REA;
RDA <= RDA_node;
WADB_node <= WADB;
WEB_node <= WEB;
WDB_node <= WDB;
RADB_node <= RADB;
REB_node <= REB;
RDB <= RDB_node;
-----------------------------------------
--------- Behavior process -------------
-----------------------------------------
KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
--TSPEC: A note about sram initial values and rom mode:
-- If the user does not provide any values, ... default 0
-- for all ram locations in JECED
variable v_MEM : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
variable v_INI_DONE : boolean := FALSE;
variable v_WADDR_A : integer;
variable v_RADDR_A : integer;
variable v_WADDR_B : integer;
variable v_RADDR_B : integer;
variable v_WADDRA_Valid_Flag : boolean := TRUE;
variable v_WADDRB_Valid_Flag : boolean := TRUE;
variable v_RADDRA_Valid_Flag : boolean := TRUE;
variable v_RADDRB_Valid_Flag : boolean := TRUE;
begin -- Process
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
v_INI_DONE := TRUE;
end if;
-- Address Check
v_WADDRA_Valid_Flag := Valid_Address(WADA_node);
v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
v_RADDRA_Valid_Flag := Valid_Address(RADA_node);
v_RADDRB_Valid_Flag := Valid_Address(RADB_node);
if ( v_WADDRA_Valid_Flag = TRUE ) then
v_WADDR_A := CONV_INTEGER(WADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_WADDRB_Valid_Flag = TRUE ) then
v_WADDR_B := CONV_INTEGER(WADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Write AddressB of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRA_Valid_Flag = TRUE ) then
v_RADDR_A := CONV_INTEGER(RADA_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressA of Port contains invalid bit!"
-- severity warning;
end if;
if (v_RADDRB_Valid_Flag = TRUE ) then
v_RADDR_B := CONV_INTEGER(RADB_node);
-- else
-- assert (Now = 0 ps)
-- report "Read AddressB of Port contains invalid bit!"
-- severity warning;
end if;
-- CHECK Operation
if (WEA = '1' and WEB = '1' and
not(
(v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B)
or
(v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
)
) then
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity warning;
end if;
-- MEM Operation
if (WEA_node = '1') then
v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
end if;
if (WEB_node = '1') then
v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
end if;
if (REA_node = '1') then
RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
-- else
-- RDA_node <= ( others => 'X');
end if;
if (REB_node = '1') then
RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
-- else
-- RDB_node <= ( others => 'X');
end if;
end process KERNEL_BEHAV;
end LATTICE_BEHAV;
---************* SC_FIFO_L **************************
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity READ_POINTER_CTRL is
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end READ_POINTER_CTRL;
architecture LATTICE_BEHAV of READ_POINTER_CTRL is
signal s_READ_POINTER : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
begin
READ_POINTER <= s_READ_POINTER;
process (GLOBAL_RST, RESET_RP, READ_EN, READ_CLK)
variable v_READ_POINTER: STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' or RESET_RP = '1' then
s_READ_POINTER <= (others => '0');
elsif (READ_CLK'EVENT and READ_CLK = '1') then
if (READ_EN = '1' and EMPTY_FLAG = '1') then
v_READ_POINTER := s_READ_POINTER + '1';
else
v_READ_POINTER := s_READ_POINTER;
end if;
if (v_READ_POINTER = TERMINAL_COUNT + 1) then
s_READ_POINTER <= (others => '0');
else
s_READ_POINTER <= v_READ_POINTER;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO COMPONENTS WRITE_POINTER_CTRL
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity WRITE_POINTER_CTRL is
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end WRITE_POINTER_CTRL;
architecture LATTICE_BEHAV of WRITE_POINTER_CTRL is
signal s_WRITE_POINTER : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
WRITE_POINTER <= s_WRITE_POINTER;
process (GLOBAL_RST, WRITE_EN, WRITE_CLK)
variable v_WRITE_POINTER: STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' then
s_WRITE_POINTER <= (others => '0');
elsif (WRITE_CLK'EVENT and WRITE_CLK = '1') then
if (WRITE_EN = '1' and FULL_FLAG /= '1') then
v_WRITE_POINTER := s_WRITE_POINTER + '1';
else
v_WRITE_POINTER := s_WRITE_POINTER ;
end if;
if (v_WRITE_POINTER = TERMINAL_COUNT + 1) then
s_WRITE_POINTER <= (others => '0');
else
s_WRITE_POINTER <= v_WRITE_POINTER;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO COMPONENTS FLAG LOGIC
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity FLAG_LOGIC is
generic (
WPOINTER_WIDTH : integer := 9;
RPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0) := (others => '0');--QQ
R_POINTER : in STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
W_POINTER : in STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0');
GLOBAL_RST : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end FLAG_LOGIC;
architecture LATTICE_BEHAV of FLAG_LOGIC is
--------------------------------------------------------------------------
-- Function: Valid_Address
-- Description:
--------------------------------------------------------------------------
function Valid_Pointer (
IN_ADDR : in STD_LOGIC_VECTOR
) return BOOLEAN is
variable v_Valid_Flag : BOOLEAN := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Pointer;
--------------------------------------------------------------------------
-- Function: Calculate_Offset
-- Description:
--------------------------------------------------------------------------
function Calculate_Offset (
IN_TC : in STD_LOGIC_VECTOR;
TC_LENGTH: in INTEGER
) return STD_LOGIC_VECTOR is
variable vTC_FULL: STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '1');
variable vTC_TEMP: STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '0');
variable vOFFSET : STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '0');
begin
vTC_TEMP := IN_TC;
vOFFSET := vTC_FULL-vTC_TEMP;
return vOFFSET;
end Calculate_Offset;
begin
--------------------------------------------------------------------------
-- Function: Main Process
-- Description:
--------------------------------------------------------------------------
FULL_AMFULL: process (GLOBAL_RST, WRITE_EN, WRITE_CLK, W_POINTER, R_POINTER)
variable v_WP_Valid_Flag : boolean := TRUE;
variable v_RP_Valid_Flag : boolean := TRUE;
--variable v_WP_Check_FULL_TMP : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_WP_Check_AMFL_TMP : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
variable v_WP_Check_AMFL_TMP1 : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
variable v_WP_Check_FULL : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
variable v_WP_Check_AMFL : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
begin
v_WP_Valid_Flag := Valid_Pointer(W_POINTER);
v_RP_Valid_Flag := Valid_Pointer(R_POINTER);
if( v_WP_Valid_Flag = TRUE) then
v_WP_Check_AMFL_TMP := W_POINTER + AMFULL_X + 1;
end if;
v_WP_Check_AMFL_TMP1 := v_WP_Check_AMFL_TMP + Calculate_Offset(TERMINAL_COUNT, WPOINTER_WIDTH);
if ( v_WP_Valid_Flag = TRUE and W_POINTER = TERMINAL_COUNT ) then
v_WP_Check_FULL := (others => '0');
elsif( v_WP_Valid_Flag = TRUE ) then
v_WP_Check_FULL := W_POINTER + 1;
end if;
if GLOBAL_RST = '1' then
FULL_D <= '0';
AMFULL_D <= '0';
elsif( v_WP_Valid_Flag = TRUE and v_RP_Valid_Flag = TRUE) then
if R_POINTER = v_WP_Check_FULL then
FULL_D <= '1';
else
FULL_D <= '0';
end if;
if (W_POINTER > R_POINTER) then
if (v_WP_Check_AMFL_TMP1 < W_POINTER) then
if v_WP_Check_AMFL_TMP1 >= R_POINTER then
AMFULL_D <= '1';
else
AMFULL_D <= '0';
end if;
else
AMFULL_D <= '0';
end if;
elsif (W_POINTER < R_POINTER) then
if (v_WP_Check_AMFL_TMP1 < W_POINTER) then
AMFULL_D <= '1';
elsif (v_WP_Check_AMFL_TMP >= R_POINTER) then
AMFULL_D <= '1';
else
AMFULL_D <= '0';
end if;
end if;
end if;
end process FULL_AMFULL;
EMPTY_AMEMPTY: process (GLOBAL_RST, READ_EN, READ_CLK, W_POINTER, R_POINTER)
variable v_WP_Valid_Flag : boolean := TRUE;
variable v_RP_Valid_Flag : boolean := TRUE;
variable v_RP_Check_EMPT_TMP : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_RP_Check_AMET_TMP : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_RP_Check_AMET_TMP1 : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
--variable v_RP_Check_EMPT : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
variable v_RP_Check_AMET : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
begin
v_WP_Valid_Flag := Valid_Pointer(W_POINTER);
v_RP_Valid_Flag := Valid_Pointer(R_POINTER);
if( v_RP_Valid_Flag = TRUE and v_WP_Valid_Flag = TRUE) then
v_RP_Check_AMET_TMP := R_POINTER + AMEMPTY_Y ; -- Different from TSPEC QQ 07 17,2002
end if;
v_RP_Check_AMET_TMP1 := v_RP_Check_AMET_TMP + Calculate_Offset(TERMINAL_COUNT, RPOINTER_WIDTH);
if GLOBAL_RST = '1' then
EMPTY_D <= '0';
AMEMPTY_D <= '0';
elsif( v_WP_Valid_Flag = TRUE and v_RP_Valid_Flag = TRUE) then
if R_POINTER = W_POINTER then -- Different from TSPEC QQ 07 17,2002
EMPTY_D <= '0';
else
EMPTY_D <= '1';
end if;
if (W_POINTER < R_POINTER) then
if (v_RP_Check_AMET_TMP1 < R_POINTER) then
v_RP_Check_AMET := v_RP_Check_AMET_TMP + Calculate_Offset(TERMINAL_COUNT, RPOINTER_WIDTH);
if v_RP_Check_AMET >= W_POINTER then
AMEMPTY_D <= '0';
else
AMEMPTY_D <= '1';
end if;
else
AMEMPTY_D <= '1';
end if;
elsif (W_POINTER > R_POINTER) then
if (v_RP_Check_AMET_TMP1 < R_POINTER) then
AMEMPTY_D <= '0';
elsif (v_RP_Check_AMET_TMP >= W_POINTER) then
AMEMPTY_D <= '0';
else
AMEMPTY_D <= '1';
end if;
elsif (W_POINTER = R_POINTER) then
AMEMPTY_D <= '0';
end if;
end if;
end process EMPTY_AMEMPTY;
end LATTICE_BEHAV;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
---USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
--LIBRARY SC_LIB;
--USE SC_LIB.SC_FIFO_COMPS.ALL;
entity SC_FIFO_16K_L is
generic (
TERMINAL_COUNT : integer := 511; --QQ: Word number < 2**WADDR_WIDTH
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 9;
RDATA_WIDTH : integer := 32;
ALMOST_FULL_X : integer := 1;
ALMOST_EMPTY_Y : integer := 1;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end SC_FIFO_16K_L;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_FIFO_16K_L is
---------------------------------------------------------
-- Function: TO_STD_VECTOR
---------------------------------------------------------
function TO_STD_VECTOR ( INPUT_STRING : string; INPUT_LENGTH: integer)
return std_logic_vector is
variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
variable vTRANS: string(INPUT_LENGTH downto 1) := (others => '0');
begin
vTRANS := INPUT_STRING;
for i in INPUT_LENGTH downto 1 loop
if (vTRANS(i) = '1') then
vDATA_STD_VEC(i-1) := '1';
elsif ( vTRANS(i) ='0') then
vDATA_STD_VEC(i-1) := '0';
end if;
end loop;
return vDATA_STD_VEC;
end TO_STD_VECTOR;
---------------------------------------------------------
-- Function: INT_TO_VEC
---------------------------------------------------------
function INT_TO_VEC ( INPUT_INT : integer; INPUT_LENGTH: integer)
return std_logic_vector is
variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
variable vTRANS: integer := 0;
variable vQUOTIENT: integer := 0;
begin
vQUOTIENT := INPUT_INT;
for i in 0 to INPUT_LENGTH -1 loop
vTRANS := 0;
while vQUOTIENT >1 loop
vQUOTIENT := vQUOTIENT - 2;
vTRANS := vTRANS + 1;
end loop;
case vQUOTIENT is
when 1 =>
vDATA_STD_VEC(i) := '1';
when 0 =>
vDATA_STD_VEC(i) := '0';
when others =>
null;
end case;
vQUOTIENT := vTRANS;
end loop;
return vDATA_STD_VEC;
end INT_TO_VEC;
---------------------------------------------------------
-- Components Definition
---------------------------------------------------------
component SC_BRAM_16K_L_SYNC
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
WCLK : in STD_LOGIC;
RCLK : in STD_LOGIC
);
end component;
component READ_POINTER_CTRL
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end component;
component WRITE_POINTER_CTRL
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end component;
component FLAG_LOGIC
generic (
WPOINTER_WIDTH : integer := 9;
RPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
R_POINTER : in STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0);
W_POINTER : in STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0);
GLOBAL_RST : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end component;
-- Signal Declaration
signal WE_node : STD_LOGIC := '0';
signal WCLK_node : STD_LOGIC := '0';
signal RST_node : STD_LOGIC := '0';
signal RPRST_node : STD_LOGIC := '0';
signal RE_node : STD_LOGIC := '0';
signal RCLK_node : STD_LOGIC := '0';
signal FULLIN_node : STD_LOGIC := '0';
signal EMPTYIN_node : STD_LOGIC := '0';
signal DI_node : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => '0');
signal DI_reg : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => '0');
signal FULLIN_reg : STD_LOGIC := '0';
signal EMPTYIN_reg : STD_LOGIC := '0';
signal FULL_node : STD_LOGIC := '0';
signal EMPTY_node : STD_LOGIC := '0';
signal AMFULL_node : STD_LOGIC := '0';
signal AMEMPTY_node : STD_LOGIC := '0';
signal DO_node : STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => '0');
signal TC_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
signal FULL_reg : STD_LOGIC := '0';
signal EMPTY_reg : STD_LOGIC := '0';
signal AMFULL_reg : STD_LOGIC := '0';
signal AMEMPTY_reg : STD_LOGIC := '0';
signal RP_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => '0');
signal WP_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
signal GND_sig : STD_LOGIC := '0';
-- architecture
begin
GND_sig <= '0';
WE_node <= WE and not(FULL_node);
WCLK_node <= WCLK;
RST_node <= RST;
RPRST_node <= RPRST;
RE_node <= RE and EMPTY_node;
RCLK_node <= RCLK;
FULLIN_node <= FULLIN;
EMPTYIN_node <= EMPTYIN;
DI_node <= DI;
--TC_node <= TO_STD_VECTOR(TERMINAL_COUNT,WADDR_WIDTH);
TC_node <= INT_TO_VEC(TERMINAL_COUNT,WADDR_WIDTH);
--FULL <= FULL_node;
FULL <= FULL_node when (RE_node = '0') else FULL_reg;
--AMFULL <= AMFULL_node;
AMFULL <= AMFULL_node when (RE_node = '0') else AMFULL_reg;
EMPTY <= not EMPTY_node;
AMEMPTY <= not AMEMPTY_node;
DO <= DO_node;
-- Register Port DI inputs
register_DI_inputs: process (RST_node, WCLK_node)
begin
if (RST_node = '1') then
DI_reg <= (others =>'0');
elsif (WCLK_node'event and WCLK_node = '1') then
if (WE_node = '1') then
DI_reg <= DI_node after 1 ps;
end if;
end if;
end process register_DI_inputs;
-- Register flag inputs
register_flag_inputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULLIN_reg <= '0';
EMPTYIN_reg <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
-- WE_reg <= WE_node and not (FULL_reg); --QQ
if (WE_node = '1') then
FULLIN_reg <= FULLIN_node;
end if;
end if;
if (RCLK_node'event and RCLK_node = '1') then
-- RE_reg <= RE_node and EMPTY_reg; --QQ
if (RE_node = '1') then
EMPTYIN_reg <= EMPTYIN_node;
end if;
end if;
end if;
end process register_flag_inputs;
-- Register flag outputs
register_flag_outputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULL_node <= '0';
AMFULL_node <= '0';
EMPTY_node <= '0';
AMEMPTY_node <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
FULL_node <= FULL_reg;
AMFULL_node <= AMFULL_reg;
end if;
if (RCLK_node'event and RCLK_node = '1') then
EMPTY_node <= EMPTY_reg;
AMEMPTY_node <= AMEMPTY_reg;
end if;
end if;
end process register_flag_outputs;
-- READ_POINTER_CTRL instance for FIFO
FIFO_RPC_INST: READ_POINTER_CTRL
generic map (
RPOINTER_WIDTH => RADDR_WIDTH
)
port map (
TERMINAL_COUNT => TC_node,
GLOBAL_RST => RST_node,
RESET_RP => RPRST_node,
READ_EN => RE_node,
READ_CLK => RCLK_node,
EMPTY_FLAG => EMPTY_reg,
READ_POINTER => RP_node
);
-- WRITE_POINTER_CTRL instance for FIFO
FIFO_WPC_INST: WRITE_POINTER_CTRL
generic map (
WPOINTER_WIDTH => WADDR_WIDTH,
WDATA_WIDTH => WDATA_WIDTH
)
port map (
TERMINAL_COUNT => TC_node,
GLOBAL_RST => RST_node,
WRITE_EN => WE_node,
WRITE_CLK => WCLK_node,
FULL_FLAG => FULL_reg,
WRITE_POINTER => WP_node
);
-- FLAG_LOGIC instance for FIFO
FIFO_FL_INST: FLAG_LOGIC
generic map (
WPOINTER_WIDTH => WADDR_WIDTH,
RPOINTER_WIDTH => RADDR_WIDTH,
WDATA_WIDTH => WDATA_WIDTH,
RDATA_WIDTH => RDATA_WIDTH,
AMFULL_X => ALMOST_FULL_X,
AMEMPTY_Y => ALMOST_EMPTY_Y
)
port map(
TERMINAL_COUNT => TC_node,
R_POINTER => RP_node,
W_POINTER => WP_node,
GLOBAL_RST => RST_node,
READ_EN => RE_node,
READ_CLK => RCLK_node,
WRITE_EN => WE_node,
WRITE_CLK => WCLK_node,
FULL_D => FULL_reg,
EMPTY_D => EMPTY_reg,
AMFULL_D => AMFULL_reg,
AMEMPTY_D => AMEMPTY_reg
);
-- BRAM instance for FIFO
FIFO_BRAM_INST: SC_BRAM_16K_L_SYNC
generic map(
WADDR_WIDTH_A => WADDR_WIDTH,
RADDR_WIDTH_A => RADDR_WIDTH,
WADDR_WIDTH_B => WADDR_WIDTH,
RADDR_WIDTH_B => RADDR_WIDTH,
WDATA_WIDTH_A => WDATA_WIDTH,
RDATA_WIDTH_A => RDATA_WIDTH,
WDATA_WIDTH_B => WDATA_WIDTH,
RDATA_WIDTH_B => RDATA_WIDTH,
ARRAY_SIZE => open,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => WP_node,
WEA => WE_node,
WDA => DI_node,
RADA => RP_node,
REA => RE_node,
RDA => DO_node,
WADB => WP_node,
WEB => GND_sig,
WDB => DI_node,
RADB => RP_node,
REB => GND_sig,
RDB => open,
WCLK => WCLK_node,
RCLK => RCLK_node
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- FIFO V2: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_FIFO_V2.vhd
-- Description: FIFO behavioral model.
-- ************************************************************************
-- FIFO COMPONENTS READ_POINTER_CTRL_V2
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity READ_POINTER_CTRL_V2 is
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end READ_POINTER_CTRL_V2;
architecture LATTICE_BEHAV of READ_POINTER_CTRL_V2 is
signal s_READ_POINTER : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
begin
READ_POINTER <= s_READ_POINTER;
process (GLOBAL_RST, RESET_RP, READ_EN, READ_CLK)
variable v_READ_POINTER: STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' or RESET_RP = '1' then
s_READ_POINTER <= TERMINAL_COUNT;
elsif (READ_CLK'EVENT and READ_CLK = '1') then
if (READ_EN = '1' and EMPTY_FLAG = '1') then
v_READ_POINTER := s_READ_POINTER + '1';
else
v_READ_POINTER := s_READ_POINTER;
end if;
if (v_READ_POINTER = TERMINAL_COUNT + 1) then
s_READ_POINTER <= (others => '0');
else
s_READ_POINTER <= v_READ_POINTER;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO COMPONENTS WRITE_POINTER_CTRL_V2
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity WRITE_POINTER_CTRL_V2 is
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end WRITE_POINTER_CTRL_V2;
architecture LATTICE_BEHAV of WRITE_POINTER_CTRL_V2 is
signal s_WRITE_POINTER : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
WRITE_POINTER <= s_WRITE_POINTER;
process (GLOBAL_RST, WRITE_EN, WRITE_CLK)
variable v_WRITE_POINTER: STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');
begin
if GLOBAL_RST = '1' then
s_WRITE_POINTER <= TERMINAL_COUNT ;
elsif (WRITE_CLK'EVENT and WRITE_CLK = '1') then
if (WRITE_EN = '1' and FULL_FLAG /= '1') then
v_WRITE_POINTER := s_WRITE_POINTER + '1';
else
v_WRITE_POINTER := s_WRITE_POINTER ;
end if;
if (v_WRITE_POINTER = TERMINAL_COUNT + 1) then
s_WRITE_POINTER <= (others => '0');
else
s_WRITE_POINTER <= v_WRITE_POINTER ;
end if;
end if;
end process;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO V2 COMPONENTS FLAG LOGIC
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
entity FLAG_LOGIC_V2 is
generic (
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
GLOBAL_RST : in STD_LOGIC ;
FIFO_CAP : in integer ;
FIFO_PTR : in integer ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end FLAG_LOGIC_V2;
architecture LATTICE_BEHAV of FLAG_LOGIC_V2 is
begin
--------------------------------------------------------------------------
-- Function: Main Process
-- Description:
--------------------------------------------------------------------------
FULL_AMFULL_EMPTY_AMEMPTY: process (GLOBAL_RST, FIFO_CAP, FIFO_PTR)
begin
if GLOBAL_RST = '1' then
FULL_D <= '0';
AMFULL_D <= '0';
EMPTY_D <= '0';
AMEMPTY_D <= '0';
else
if (FIFO_CAP - FIFO_PTR < WDATA_WIDTH) then
FULL_D <= '1';
else
FULL_D <= '0';
end if;
if (FIFO_CAP - FIFO_PTR < WDATA_WIDTH + AMFULL_X * WDATA_WIDTH) then
AMFULL_D <= '1';
else
AMFULL_D <= '0';
end if;
if (FIFO_PTR < RDATA_WIDTH) then
EMPTY_D <= '0';
else
EMPTY_D <= '1';
end if;
if (FIFO_PTR < RDATA_WIDTH + AMEMPTY_Y * RDATA_WIDTH) then
AMEMPTY_D <= '0';
else
AMEMPTY_D <= '1';
end if;
end if;
end process FULL_AMFULL_EMPTY_AMEMPTY;
end LATTICE_BEHAV;
-- ************************************************************************
-- FIFO V2 Main Body
-- READ_POINTER_CTRL_V2
-- WRITE_POINTER_CTRL_V2
-- FLAG_LOGIC_V2
-- SC_BRAM_16K
-- ************************************************************************
-- ************************************************************************
-- Top Design Entity definition
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity SC_FIFO_V2_16K_L is
generic (
TERMINAL_COUNT : integer := 511; --QQ: Word number < 2**WADDR_WIDTH
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 8;
RDATA_WIDTH : integer := 64;
ALMOST_FULL_X : integer := 2;
ALMOST_EMPTY_Y : integer := 2;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end SC_FIFO_V2_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_FIFO_V2_16K_L is
---------------------------------------------------------
-- Function: TO_STD_VECTOR
---------------------------------------------------------
function TO_STD_VECTOR ( INPUT_STRING : string; INPUT_LENGTH: integer)
return std_logic_vector is
variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
variable vTRANS: string(INPUT_LENGTH downto 1) := (others => '0');
begin
vTRANS := INPUT_STRING;
for i in INPUT_LENGTH downto 1 loop
if (vTRANS(i) = '1') then
vDATA_STD_VEC(i-1) := '1';
elsif ( vTRANS(i) ='0') then
vDATA_STD_VEC(i-1) := '0';
end if;
end loop;
return vDATA_STD_VEC;
end TO_STD_VECTOR;
---------------------------------------------------------
-- Components Definition
---------------------------------------------------------
component SC_BRAM_16K_L
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
component READ_POINTER_CTRL_V2
generic (
RPOINTER_WIDTH : integer := 9
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);
GLOBAL_RST : in STD_LOGIC ;
RESET_RP : in STD_LOGIC ;
READ_EN : in STD_LOGIC ;
READ_CLK : in STD_LOGIC ;
EMPTY_FLAG : in STD_LOGIC ;
READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
);
end component;
component WRITE_POINTER_CTRL_V2
generic (
WPOINTER_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32
);
port (
TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);
GLOBAL_RST : in STD_LOGIC ;
WRITE_EN : in STD_LOGIC ;
WRITE_CLK : in STD_LOGIC ;
FULL_FLAG : in STD_LOGIC ;
WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
);
end component;
component FLAG_LOGIC_V2
generic (
WDATA_WIDTH : integer := 32;
RDATA_WIDTH : integer := 32;
AMFULL_X : integer := 1;
AMEMPTY_Y : integer := 1
);
port (
GLOBAL_RST : in STD_LOGIC ;
FIFO_CAP : in integer ;
FIFO_PTR : in integer ;
FULL_D : out STD_LOGIC ;
EMPTY_D : out STD_LOGIC ;
AMFULL_D : out STD_LOGIC ;
AMEMPTY_D : out STD_LOGIC
);
end component;
-- Signal Declaration
signal WE_node : STD_LOGIC := 'X';
signal WCLK_node : STD_LOGIC := 'X';
signal RST_node : STD_LOGIC := 'X';
signal RPRST_node : STD_LOGIC := 'X';
signal RE_node : STD_LOGIC := 'X';
signal RCLK_node : STD_LOGIC := 'X';
signal FULLIN_node : STD_LOGIC := 'X';
signal EMPTYIN_node : STD_LOGIC := 'X';
signal DI_node : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal DI_reg : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal WE_reg : STD_LOGIC := 'X';
signal RE_reg : STD_LOGIC := 'X';
signal FULLIN_reg : STD_LOGIC := 'X';
signal EMPTYIN_reg : STD_LOGIC := 'X';
signal FULL_node : STD_LOGIC := 'X';
signal EMPTY_node : STD_LOGIC := 'X';
signal AMFULL_node : STD_LOGIC := 'X';
signal AMEMPTY_node : STD_LOGIC := 'X';
signal DO_node : STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');
signal TC_W_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
signal TC_R_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal FULL_reg : STD_LOGIC := 'X';
signal EMPTY_reg : STD_LOGIC := 'X';
signal AMFULL_reg : STD_LOGIC := 'X';
signal AMEMPTY_reg : STD_LOGIC := 'X';
signal RP_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal WP_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
signal GND_sig : STD_LOGIC := 'X';
--QQ FIFOV2
signal FIFO_capacity : integer := 0;
signal FIFO_pointer : integer := 0;
-- architecture
begin
FIFO_capacity <= (TERMINAL_COUNT + 1) * WDATA_WIDTH;
GND_sig <= '0';
WE_node <= WE and not (FULL_node);
WCLK_node <= WCLK;
RST_node <= RST;
RPRST_node <= RPRST;
RE_node <= RE;
RCLK_node <= RCLK;
FULLIN_node <= FULLIN;
EMPTYIN_node <= EMPTYIN;
DI_node <= DI;
TC_W_node <= CONV_STD_LOGIC_VECTOR(TERMINAL_COUNT,WADDR_WIDTH);
TC_R_node <= CONV_STD_LOGIC_VECTOR((TERMINAL_COUNT+1)*(WDATA_WIDTH/RDATA_WIDTH)-1,RADDR_WIDTH);
--FULL <= FULL_node;
FULL <= FULL_node when (RE_node = '0') else FULL_reg;
--AMFULL <= AMFULL_node;
AMFULL <= AMFULL_node when (RE_node = '0') else AMFULL_reg;
EMPTY <= not EMPTY_node;
AMEMPTY <= not AMEMPTY_node;
DO <= DO_node;
-- Register Port DI inputs
register_DI_inputs: process (RST_node, WCLK_node)
begin
if (RST_node = '1') then
DI_reg <= (others =>'0');
elsif (WCLK_node'event and WCLK_node = '1') then
if (WE_node = '1') then
DI_reg <= DI_node after 1 ps;
end if;
end if;
end process register_DI_inputs;
-- Register flag inputs
register_flag_inputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULLIN_reg <= '0';
EMPTYIN_reg <= '0';
WE_reg <= '0';
RE_reg <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
WE_reg <= WE_node and not FULL_reg; --Fix DTS14659
--WE_reg <= WE_node;
if (WE_node = '1') then
FULLIN_reg <= FULLIN_node;
end if;
end if;
if (RCLK_node'event and RCLK_node = '1') then
RE_reg <= RE_node and EMPTY_reg;
if (RE_node = '1') then
EMPTYIN_reg <= EMPTYIN_node;
end if;
end if;
end if;
end process register_flag_inputs;
-- Register flag outputs
register_flag_outputs: process (RST_node, WCLK_node, RCLK_node)
begin
if (RST_node = '1') then
FULL_node <= '0';
AMFULL_node <= '0';
EMPTY_node <= '0';
AMEMPTY_node <= '0';
else
if (WCLK_node'event and WCLK_node = '1') then
FULL_node <= FULL_reg;
AMFULL_node <= AMFULL_reg;
end if;
if (RCLK_node'event and RCLK_node = '1') then
EMPTY_node <= EMPTY_reg;
AMEMPTY_node <= AMEMPTY_reg;
end if;
end if;
end process register_flag_outputs;
-- Set FIFO_pointer
FIFO_CAP_POINTER: process ( RP_node, WP_node, RST_node, RPRST_node)
begin
--WP ++, FIFO_CAP --
if (WP_node'event and RP_node'event) then
FIFO_pointer <= FIFO_pointer + WDATA_WIDTH - RDATA_WIDTH;
elsif(WP_node'event) then
FIFO_pointer <= FIFO_pointer + WDATA_WIDTH;
end if;
--RPRST Active, FIFO_CAP --
--RP ++, FIFO_CAP ++
if (RST_node = '1') then
FIFO_pointer <= 0;
elsif (RPRST_node = '1') then
FIFO_pointer <= (CONV_INTEGER(WP_node)+1) * WDATA_WIDTH;
elsif (RP_node'event and not(WP_node'event)) then
FIFO_pointer <= FIFO_pointer - RDATA_WIDTH;
end if;
end process FIFO_CAP_POINTER;
-- READ_POINTER_CTRL_V2 instance for FIFO
FIFO_RPC_INST: READ_POINTER_CTRL_V2
generic map (
RPOINTER_WIDTH => RADDR_WIDTH
)
port map (
TERMINAL_COUNT => TC_R_node,
GLOBAL_RST => RST_node,
RESET_RP => RPRST_node,
READ_EN => RE_node,
READ_CLK => RCLK_node,
EMPTY_FLAG => EMPTY_reg,
READ_POINTER => RP_node
);
-- WRITE_POINTER_CTRL_V2 instance for FIFO
FIFO_WPC_INST: WRITE_POINTER_CTRL_V2
generic map (
WPOINTER_WIDTH => WADDR_WIDTH,
WDATA_WIDTH => WDATA_WIDTH
)
port map (
TERMINAL_COUNT => TC_W_node,
GLOBAL_RST => RST_node,
WRITE_EN => WE_node,
WRITE_CLK => WCLK_node,
FULL_FLAG => FULL_reg,
WRITE_POINTER => WP_node
);
-- FLAG_LOGIC_V2 instance for FIFO
FIFO_FL_INST: FLAG_LOGIC_V2
generic map (
WDATA_WIDTH => WDATA_WIDTH,
RDATA_WIDTH => RDATA_WIDTH,
AMFULL_X => ALMOST_FULL_X,
AMEMPTY_Y => ALMOST_EMPTY_Y
)
port map(
GLOBAL_RST => RST_node,
FIFO_CAP => FIFO_capacity,
FIFO_PTR => FIFO_pointer,
FULL_D => FULL_reg,
EMPTY_D => EMPTY_reg,
AMFULL_D => AMFULL_reg,
AMEMPTY_D => AMEMPTY_reg
);
-- BRAM instance for FIFO
FIFO_BRAM_INST: SC_BRAM_16K_L
generic map(
WADDR_WIDTH_A => WADDR_WIDTH,
RADDR_WIDTH_A => RADDR_WIDTH,
WADDR_WIDTH_B => WADDR_WIDTH,
RADDR_WIDTH_B => RADDR_WIDTH,
WDATA_WIDTH_A => WDATA_WIDTH,
RDATA_WIDTH_A => RDATA_WIDTH,
WDATA_WIDTH_B => WDATA_WIDTH,
RDATA_WIDTH_B => RDATA_WIDTH,
ARRAY_SIZE => open,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => WP_node,
WEA => WE_reg,
WDA => DI_reg,
RADA => RP_node,
REA => RE_reg,
RDA => DO_node,
WADB => WP_node,
WEB => GND_sig,
WDB => DI_reg,
RADB => RP_node,
REB => GND_sig,
RDB => open
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- DPRAM: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_DP_RAM.vhd
-- Description: Single Port BRAM behavioral model.
-- History:
-- May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
LIBRARY ieee, std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.all;
USE work.components.all;
-- ************************************************************************
-- Entity definition
-- Draft "generic" members
-- ************************************************************************
entity SC_DPRAM_16K_L is
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
ADDR_WIDTH_A : integer := 13;
DATA_WIDTH_A : integer := 2;
ADDR_WIDTH_B : integer := 14;
DATA_WIDTH_B : integer := 1;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
CENA : in STD_LOGIC ;
CLKA : in STD_LOGIC ;
WRA : in STD_LOGIC ;
CSA : in STD_LOGIC_VECTOR (1 downto 0);
RSTA : in STD_LOGIC ;
DIA : in STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
ADA : in STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
DOA : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
CENB : in STD_LOGIC ;
CLKB : in STD_LOGIC ;
WRB : in STD_LOGIC ;
CSB : in STD_LOGIC_VECTOR (1 downto 0);
RSTB : in STD_LOGIC ;
DIB : in STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
ADB : in STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
DOB : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
);
end SC_DPRAM_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_DPRAM_16K_L is
component SC_BRAM_16K_L
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (DATA_WIDTH_A downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**ADDR_WIDTH_A)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to DATA_WIDTH_A - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + DATA_WIDTH_A;
end loop;
end READ_MEM_INIT_FILE;
-- Signal Declaration
signal CENA_node : STD_LOGIC := 'X';
signal CLKA_node : STD_LOGIC := 'X';
signal WRA_node : STD_LOGIC := 'X';
signal CSA_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RSTA_node : STD_LOGIC := 'X';
signal DIA_node : STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
signal ADA_node : STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0) := (others => '0');
signal DOA_node : STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
signal DIA_reg : STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
signal ADA_reg : STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0) := (others => 'X');
signal ENA_reg : STD_LOGIC := 'X';
signal RENA_reg : STD_LOGIC := 'X';
signal CENB_node : STD_LOGIC := 'X';
signal CLKB_node : STD_LOGIC := 'X';
signal WRB_node : STD_LOGIC := 'X';
signal CSB_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RSTB_node : STD_LOGIC := 'X';
signal DIB_node : STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
signal ADB_node : STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0) := (others => 'X');
signal DOB_node : STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
signal DIB_reg : STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
signal ADB_reg : STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0) := (others => 'X');
signal ENB_reg : STD_LOGIC := 'X';
signal RENB_reg : STD_LOGIC := 'X';
signal v_MEM : STD_LOGIC_VECTOR(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
signal v_ADA : INTEGER;
signal v_ADB : INTEGER;
-- architecture
begin
CENA_node <= CENA;
CLKA_node <= CLKA;
WRA_node <= WRA;
CSA_node <= CSA;
RSTA_node <= RSTA;
DIA_node <= DIA;
ADA_node <= ADA;
-- DOA <= DOA_node;
CENB_node <= CENB;
CLKB_node <= CLKB;
WRB_node <= WRB;
CSB_node <= CSB;
RSTB_node <= RSTB;
DIB_node <= DIB;
ADB_node <= ADB;
-- DOB <= DOB_node;
init_process : process
variable v_INI_DONE : boolean := FALSE;
variable v_MEM_i : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
begin
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM_i);
v_INI_DONE := TRUE;
end if;
v_MEM <= v_MEM_i;
wait;
end process;
process(ADA_node, ADB_node)
begin
if (Valid_Address(ADA_node) = TRUE) then
v_ADA <= CONV_INTEGER(ADA_node);
end if;
if (Valid_Address(ADB_node) = TRUE) then
v_ADB <= CONV_INTEGER(ADB_node);
end if;
end process;
-- Register Port A DI/ AD / Enable inputs
register_A_inputs: process (CLKA_node, RSTA_node)
begin
if (RSTA_node = '1') then
DIA_reg <= (others =>'0');
ADA_reg <= (others =>'0');
ENA_reg <= '0';
RENA_reg <= '1';
elsif (CLKA_node'event and CLKA_node = '1') then
if (CENA_node = '1') then
DIA_reg <= DIA_node;
ADA_reg <= ADA_node;
ENA_reg <= WRA_node and CSA_node(0) and CSA_node(1);
RENA_reg <= '1';
end if;
end if;
end process register_A_inputs;
-- Register Port B DI/ AD / Enable inputs
register_B_inputs: process (CLKB_node, RSTB_node)
begin
if (RSTB_node = '1') then
DIB_reg <= (others =>'0');
ADB_reg <= (others =>'0');
ENB_reg <= '0';
RENB_reg <= '1';
elsif (CLKB_node'event and CLKB_node = '1') then
if (CENB_node = '1') then
DIB_reg <= DIB_node;
ADB_reg <= ADB_node;
ENB_reg <= WRB_node and CSB_node(0) and CSB_node(1);
RENB_reg <= '1';
end if;
end if;
end process register_B_inputs;
v_MEM_process: process (CLKA_node, CLKB_node)
begin
if (ENA_reg = '1' and CENA_node = '1') then
if (CLKA_node'event and CLKA_node = '1') then
for i in 0 to DATA_WIDTH_A - 1 loop
v_MEM(v_ADA*DATA_WIDTH_A+i) <= DIA_node(i) after 1 ps;
end loop;
end if;
end if;
if (ENB_reg = '1' and CENB_node = '1') then
if (CLKB_node'event and CLKB_node = '1') then
for i in 0 to DATA_WIDTH_B - 1 loop
v_MEM(v_ADB*DATA_WIDTH_B+i) <= DIB_node(i) after 1 ps;
end loop;
end if;
end if;
end process;
DOA_output_process: process (RSTA_node, ENA_reg, CENA_node, DOA_node, CLKA_node)
begin
if (RSTA_node = '1') then
DOA <= (others => '0');
elsif (CLKA_node = '1' and CENA_node = '1') then
if (ENA_reg = '1') then
if (AWRITE_MODE = "RD_BEFORE_WR") then
for j in 0 to DATA_WIDTH_A - 1 loop
DOA(j) <= v_MEM(v_ADA*DATA_WIDTH_A+j);
end loop;
else
DOA <= DOA_node;
end if;
else
DOA <= DOA_node;
end if;
end if;
end process;
DOB_output_process: process (RSTB_node, ENB_reg, CENB_node, DOB_node, CLKB_node)
begin
if (RSTB_node = '1') then
DOB <= (others => '0');
elsif (CLKB_node = '1' and CENB_node = '1') then
if (ENB_reg = '1') then
if (BWRITE_MODE = "RD_BEFORE_WR") then
for j in 0 to DATA_WIDTH_B - 1 loop
DOB(j) <= v_MEM(v_ADB*DATA_WIDTH_B+j);
end loop;
else
DOB <= DOB_node;
end if;
else
DOB <= DOB_node;
end if;
end if;
end process;
-- BRAM instance for SPRAM
DPRAM_INST: SC_BRAM_16K_L
generic map(
AWRITE_MODE => AWRITE_MODE,
BWRITE_MODE => BWRITE_MODE,
WADDR_WIDTH_A => ADDR_WIDTH_A,
RADDR_WIDTH_A => ADDR_WIDTH_A,
WADDR_WIDTH_B => ADDR_WIDTH_B,
RADDR_WIDTH_B => ADDR_WIDTH_B,
WDATA_WIDTH_A => DATA_WIDTH_A,
RDATA_WIDTH_A => DATA_WIDTH_A,
WDATA_WIDTH_B => DATA_WIDTH_B,
RDATA_WIDTH_B => DATA_WIDTH_B,
ARRAY_SIZE => ARRAY_SIZE,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => ADA_reg,
WEA => ENA_reg,
WDA => DIA_reg,
RADA => ADA_reg,
REA => RENA_reg,
RDA => DOA_node,
WADB => ADB_reg,
WEB => ENB_reg,
WDB => DIB_reg,
RADB => ADB_reg,
REB => RENB_reg,
RDB => DOB_node
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- PseudoDPRAM: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_PDP_RAM.vhd
-- Description: Pseudo Dual Port BRAM behavioral model.
-- History:
-- May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
-- ************************************************************************
-- Entity definition
-- Draft "generic" members
-- ************************************************************************
entity SC_PDPRAM_16K_L is
generic (
WADDR_WIDTH : integer := 13;
WDATA_WIDTH : integer := 2;
RADDR_WIDTH : integer := 13;
RDATA_WIDTH : integer := 2;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WCEN : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
WE : in STD_LOGIC ;
WCS : in STD_LOGIC_VECTOR (1 downto 0);
RCLK : in STD_LOGIC;
RCEN : in STD_LOGIC;
RST : in STD_LOGIC ;
WD : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
WAD : in STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
RAD : in STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
RD : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end SC_PDPRAM_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_PDPRAM_16K_L is
component SC_BRAM_16K_L
generic (
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
-- Signal Declaration
signal WCEN_node : STD_LOGIC := 'X';
signal WCLK_node : STD_LOGIC := 'X';
signal WE_node : STD_LOGIC := 'X';
signal WCS_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RCEN_node : STD_LOGIC := 'X';
signal RCLK_node : STD_LOGIC := 'X';
signal RST_node : STD_LOGIC := 'X';
signal WD_node : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal WAD_node : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
signal RD_node : STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');
signal RAD_node : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal WD_reg : STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
signal WAD_reg : STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
signal RAD_reg : STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
signal EN_reg : STD_LOGIC := 'X';
signal REN_reg : STD_LOGIC := 'X';
signal GND_sig : STD_LOGIC;
signal VCC_sig : STD_LOGIC;
-- architecture
begin
GND_sig <= '0';
VCC_sig <= '1';
WCEN_node <= WCEN;
WCLK_node <= WCLK;
WE_node <= WE;
WCS_node <= WCS;
RCEN_node <= RCEN;
RCLK_node <= RCLK;
RST_node <= RST;
WD_node <= WD;
WAD_node <= WAD;
RAD_node <= RAD;
-- RD <= RD_node;
RD_output : process (RD_node, RST_node)
begin
if (RST_node = '1') then
RD <= (others => '0');
else
RD <= RD_node;
end if;
end process;
-- Register WD/WAD/ Enable inputs
register_write_inputs: process (WCLK_node, RST_node)
begin
if (RST_node = '1') then
WD_reg <= (others =>'0');
WAD_reg <= (others =>'0');
EN_reg <= '0';
REN_reg <= '1';
elsif (WCLK_node'event and WCLK_node = '1') then
if (WCEN_node = '1') then
WD_reg <= WD_node;
WAD_reg <= WAD_node;
EN_reg <= WE_node and WCS_node(0) and WCS_node(1);
REN_reg <= '1';
end if;
end if;
end process register_write_inputs;
-- Register RAD inputs
register_read_inputs: process (RCLK_node, RST_node)
begin
if (RST_node = '1') then
RAD_reg <= (others =>'0');
elsif (RCLK_node'event and RCLK_node = '1') then
if (RCEN_node = '1') then
RAD_reg <= RAD_node;
end if;
end if;
end process register_read_inputs;
-- BRAM instance for SPRAM
PDPRAM_INST: SC_BRAM_16K_L
generic map(
WADDR_WIDTH_A => WADDR_WIDTH,
RADDR_WIDTH_A => RADDR_WIDTH,
WADDR_WIDTH_B => WADDR_WIDTH,
RADDR_WIDTH_B => RADDR_WIDTH,
WDATA_WIDTH_A => WDATA_WIDTH,
RDATA_WIDTH_A => RDATA_WIDTH,
WDATA_WIDTH_B => WDATA_WIDTH,
RDATA_WIDTH_B => RDATA_WIDTH,
ARRAY_SIZE => ARRAY_SIZE,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => WAD_reg,
WEA => EN_reg,
WDA => WD_reg,
RADA => RAD_reg,
REA => REN_reg,
RDA => RD_node,
WADB => WAD_reg,
WEB => GND_sig,
WDB => WD_reg,
RADB => RAD_reg,
REB => GND_sig,
RDB => open
);
end LATTICE_BEHAV;
-- ************************************************************************
--
-- SPRAM: Behavioral Model
-- ************************************************************************
--
-- Filename: SC_SP_RAM.vhd
-- Description: Single Port BRAM behavioral model.
-- History:
-- May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
LIBRARY ieee, std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.all;
USE work.components.all;
-- ************************************************************************
-- Entity definition
-- Draft "generic" members
-- ************************************************************************
entity SC_SPRAM_16K_L is
generic (
WRITE_MODE : string := "NORMAL";
ADDR_WIDTH : integer := 13;
DATA_WIDTH : integer := 2;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FILE : string := "qq.dat"
);
port (
CEN : in STD_LOGIC ;
CLK : in STD_LOGIC ;
WR : in STD_LOGIC ;
CS : in STD_LOGIC_VECTOR (1 downto 0);
RST : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
AD : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end SC_SPRAM_16K_L ;
-- ************************************************************************
-- architecture
-- ************************************************************************
architecture LATTICE_BEHAV of SC_SPRAM_16K_L is
component SC_BRAM_16K_L
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
WADDR_WIDTH_A : integer := 14;
RADDR_WIDTH_A : integer := 12;
WADDR_WIDTH_B : integer := 14;
RADDR_WIDTH_B : integer := 12;
WDATA_WIDTH_A : integer := 1;
RDATA_WIDTH_A : integer := 4;
WDATA_WIDTH_B : integer := 1;
RDATA_WIDTH_B : integer := 4;
ARRAY_SIZE : integer := 16384;
MEM_INIT_FLAG : integer := 1;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WADA : in STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
WEA : in STD_LOGIC ;
WDA : in STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
RADA : in STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
REA : in STD_LOGIC ;
RDA : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
WADB : in STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
WEB : in STD_LOGIC;
WDB : in STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
RADB : in STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
REB : in STD_LOGIC;
RDB : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
);
end component;
procedure READ_MEM_INIT_FILE(
f_name : IN STRING;
v_MEM : OUT STD_LOGIC_VECTOR
) IS
file f_INIT_FILE : TEXT is MEM_INIT_FILE;
variable v_WORD : line;
variable v_GOODFLAG : boolean;
variable v_WORD_BIT : string (DATA_WIDTH downto 1) ;
variable v_CHAR : character;
variable v_OFFSET : integer := 0;
variable v_LINE : integer := 0;
begin
while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**ADDR_WIDTH)) loop
readline(f_INIT_FILE, v_WORD);
read(v_WORD, v_WORD_BIT, v_GOODFLAG);
for k in 0 to DATA_WIDTH - 1 loop
v_CHAR := v_WORD_BIT (k + 1);
if (v_CHAR = '1') then
v_MEM(v_OFFSET + k) := '1';
elsif (v_CHAR = '0') then
v_MEM(v_OFFSET + k) := '0';
-- else
-- v_MEM(v_OFFSET + k) := 'X';
end if;
end loop;
v_LINE := v_LINE + 1;
v_OFFSET := v_OFFSET + DATA_WIDTH;
end loop;
end READ_MEM_INIT_FILE;
-- Signal Declaration
signal CEN_node : STD_LOGIC := 'X';
signal CLK_node : STD_LOGIC := 'X';
signal WR_node : STD_LOGIC := 'X';
signal CS_node : STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
signal RST_node : STD_LOGIC := 'X';
signal DI_node : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
signal AD_node : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => '0');
signal DO_node : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
signal DI_reg : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
signal AD_reg : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => 'X');
signal EN_reg : STD_LOGIC := 'X';
signal REN_reg : STD_LOGIC := 'X';
signal GND_sig : STD_LOGIC;
signal VCC_sig : STD_LOGIC;
signal v_MEM : STD_LOGIC_VECTOR((2**ADDR_WIDTH) * DATA_WIDTH-1 downto 0) := (others => '0');
signal v_AD : integer;
-- architecture
begin
GND_sig <= '0';
VCC_sig <= '1';
CEN_node <= CEN;
CLK_node <= CLK;
WR_node <= WR;
CS_node <= CS;
RST_node <= RST;
DI_node <= DI;
AD_node <= AD;
-- DO <= DO_node;
init_process : process
variable v_INI_DONE : boolean := FALSE;
variable v_MEM_i : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );
begin
if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM_i);
v_INI_DONE := TRUE;
end if;
v_MEM <= v_MEM_i;
wait;
end process;
process(AD_node)
begin
if (Valid_Address(AD_node) = TRUE) then
v_AD <= CONV_INTEGER(AD_node);
end if;
end process;
-- Register DI/ AD / Enable inputs
register_inputs: process (CLK_node, RST_node)
begin
if (RST_node = '1') then
DI_reg <= (others =>'0');
AD_reg <= (others =>'0');
EN_reg <= '0';
REN_reg <= '1';
elsif (CLK_node'event and CLK_node = '1') then
if (CEN_node = '1') then
DI_reg <= DI_node;
AD_reg <= AD_node;
EN_reg <= WR_node and CS_node(0) and CS_node(1);
REN_reg <= '1';
end if;
end if;
end process register_inputs;
v_MEM_process: process (EN_reg, DI_node, v_AD, CLK_node)
begin
if (CLK_node'event and CLK_node = '1') then
if (EN_reg = '1' and CEN_node = '1') then
for i in 0 to DATA_WIDTH - 1 loop
v_MEM(v_AD*DATA_WIDTH+i) <= DI_node(i) after 1 ps;
end loop;
end if;
end if;
end process;
DO_output_process: process (RST_node, EN_reg, DO_node, CLK_node)
begin
if (RST_node = '1') then
DO <= (others => '0');
elsif (CLK_node = '1' and CEN_node = '1') then
if (EN_reg = '1') then
if (WRITE_MODE = "RD_BEFORE_WR") then
for j in 0 to DATA_WIDTH - 1 loop
DO(j) <= v_MEM(v_AD*DATA_WIDTH+j);
end loop;
else
DO <= DO_node;
end if;
else
DO <= DO_node;
end if;
end if;
end process;
-- BRAM instance for SPRAM
SPRAM_INST: SC_BRAM_16K_L
generic map(
AWRITE_MODE => WRITE_MODE,
WADDR_WIDTH_A => ADDR_WIDTH,
RADDR_WIDTH_A => ADDR_WIDTH,
WADDR_WIDTH_B => ADDR_WIDTH,
RADDR_WIDTH_B => ADDR_WIDTH,
WDATA_WIDTH_A => DATA_WIDTH,
RDATA_WIDTH_A => DATA_WIDTH,
WDATA_WIDTH_B => DATA_WIDTH,
RDATA_WIDTH_B => DATA_WIDTH,
ARRAY_SIZE => open,
MEM_INIT_FLAG => MEM_INIT_FLAG,
MEM_INIT_FILE => MEM_INIT_FILE
)
port map (
WADA => AD_reg,
WEA => EN_reg,
WDA => DI_reg,
RADA => AD_reg,
REA => REN_reg,
RDA => DO_node,
WADB => AD_reg,
WEB => GND_sig,
WDB => DI_reg,
RADB => AD_reg,
REB => GND_sig,
RDB => open
);
end LATTICE_BEHAV;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
entity fifo_dc is
generic (
module_type : string := "FIFO_DC";
module_width : integer := 1;
module_widthu : integer := 1;
module_numwords : integer := 2;
module_amfull_flag : integer := 1;
module_amempty_flag : integer := 1;
module_hint : string := "UNUSED");
port (
Data : in std_logic_vector (module_width-1 downto 0);
WrClock : in std_logic;
WrEn : in std_logic;
RdClock : in std_logic;
RdEn : in std_logic;
Reset : in std_logic;
RPReset : in std_logic;
Q : out std_logic_vector (module_width-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
AlmostFull : out std_logic;
AlmostEmpty : out std_logic);
end fifo_dc;
architecture fun_simulation of fifo_dc is
component SC_FIFO_16K_L
generic (
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 9;
RDATA_WIDTH : integer := 32;
ALMOST_FULL_X : integer := 1;
ALMOST_EMPTY_Y : integer := 1;
MEM_INIT_FLAG : integer := 0;
TERMINAL_COUNT : integer := 511;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end component;
signal Rst, FullIn, EmptyIn : std_logic;
begin
Rst <= '1';
FullIn <= '0';
EmptyIn <= '1';
SC_FIFO_inst : SC_FIFO_16K_L
generic map (
WADDR_WIDTH => module_widthu,
WDATA_WIDTH => module_width,
RADDR_WIDTH => module_widthu,
RDATA_WIDTH => module_width,
ALMOST_FULL_X => module_amfull_flag,
ALMOST_EMPTY_Y => module_amempty_flag,
MEM_INIT_FLAG => 0,
TERMINAL_COUNT => module_numwords - 1,
MEM_INIT_FILE => open )
port map (
WE => WrEn,
WCLK => WrClock,
RST => Reset,
RPRST => RPReset,
RE => RdEn,
RCLK => RdClock,
FULLIN => FullIn,
EMPTYIN => EmptyIn,
DI => Data,
FULL => Full,
EMPTY => Empty,
AMFULL => AlmostFull,
AMEMPTY => AlmostEmpty,
DO => Q
);
end;library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
entity fifo_dcx is
generic (
module_type : string := "FIFO_DCX";
module_widthw : integer := 1;
module_widthr : integer := 1;
module_widthuw : integer := 1;
module_widthur : integer := 1;
module_numwordsw : integer := 2;
module_numwordsr : integer := 2;
module_amfull_flag : integer := 1;
module_amempty_flag : integer := 1;
module_hint : string := "UNUSED");
port (
Data : in std_logic_vector (module_widthw-1 downto 0);
WrClock : in std_logic;
WrEn : in std_logic;
RdClock : in std_logic;
RdEn : in std_logic;
Reset : in std_logic;
RPReset : in std_logic;
Q : out std_logic_vector (module_widthr-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
AlmostFull : out std_logic;
AlmostEmpty : out std_logic);
end fifo_dcx;
architecture fun_simulation of fifo_dcx is
component SC_FIFO_V2_16K_L
generic (
WADDR_WIDTH : integer := 9;
WDATA_WIDTH : integer := 32;
RADDR_WIDTH : integer := 9;
RDATA_WIDTH : integer := 32;
ALMOST_FULL_X : integer := 1;
ALMOST_EMPTY_Y : integer := 1;
MEM_INIT_FLAG : integer := 0;
TERMINAL_COUNT : integer := 511;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WE : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
RST : in STD_LOGIC ;
RPRST : in STD_LOGIC ;
RE : in STD_LOGIC ;
RCLK : in STD_LOGIC ;
FULLIN : in STD_LOGIC ;
EMPTYIN : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
FULL : out STD_LOGIC ;
EMPTY : out STD_LOGIC ;
AMFULL : out STD_LOGIC ;
AMEMPTY : out STD_LOGIC ;
DO : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end component;
signal FullIn, EmptyIn : std_logic;
begin
FullIn <= '0';
EmptyIn <= '1';
SC_FIFO_inst : SC_FIFO_V2_16K_L
generic map (
WADDR_WIDTH => module_widthuw,
WDATA_WIDTH => module_widthw,
RADDR_WIDTH => module_widthur,
RDATA_WIDTH => module_widthr,
ALMOST_FULL_X => module_amfull_flag,
ALMOST_EMPTY_Y => module_amempty_flag,
MEM_INIT_FLAG => 0,
TERMINAL_COUNT => module_numwordsw - 1,
MEM_INIT_FILE => open )
port map (
WE => WrEn,
WCLK => WrClock,
RST => Reset,
RPRST => RPReset,
RE => RdEn,
RCLK => RdClock,
FULLIN => FullIn,
EMPTYIN => EmptyIn,
DI => Data,
FULL => Full,
EMPTY => Empty,
AMFULL => AlmostFull,
AMEMPTY => AlmostEmpty,
DO => Q
);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use work.components.all;
entity ram_dp is
generic(
module_type : string := "RAM_DP";
module_widthw : integer := 1;
module_widthr : integer := 1;
module_numwordsw : integer := 1;
module_widthadw : integer := 1;
module_widthadr : integer := 1;
module_numwordsr : integer := 1;
module_indata : string := "REGISTERED";
module_outdata : string := "UNREGISTERED";
module_addressw_control : string := "REGISTERED";
module_addressr_control : string := "REGISTERED";
module_gsr : string := "DISABLED";
module_hint : string := "UNUSED";
module_init_file : string := "");
port(
Data : in std_logic_vector (module_widthw-1 downto 0);
WrAddress : in std_logic_vector (module_widthadw-1 downto 0);
RdAddress : in std_logic_vector (module_widthadr-1 downto 0);
WrClock : in std_logic;
WrClockEn : in std_logic;
RdClock : in std_logic;
RdClockEn : in std_logic;
WE : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector (module_widthr-1 downto 0));
end ram_dp;
architecture fun_simulation of ram_dp is
component SC_PDPRAM_16K_L
generic (
WADDR_WIDTH : integer := 13;
WDATA_WIDTH : integer := 2;
RADDR_WIDTH : integer := 13;
RDATA_WIDTH : integer := 2;
ARRAY_SIZE : integer := 511;
MEM_INIT_FLAG : integer := 0;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
WCEN : in STD_LOGIC ;
WCLK : in STD_LOGIC ;
WE : in STD_LOGIC ;
WCS : in STD_LOGIC_VECTOR (1 downto 0);
RCLK : in STD_LOGIC;
RCEN : in STD_LOGIC;
RST : in STD_LOGIC ;
WD : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
WAD : in STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
RAD : in STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);
RD : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
);
end component;
signal cs : std_logic_vector ( 1 downto 0);
signal Q_K : std_logic_vector (module_widthr-1 downto 0);
signal Q_K_reg : std_logic_vector (module_widthr-1 downto 0);
CONSTANT module_init_flag : integer := init_flag(module_init_file);
begin
cs <= "11";
OutRegister : process(RdClock, Reset)
begin
if (Reset = '1') then
Q_K_reg <= (others => '0');
elsif (RdClock'EVENT and RdClock = '1') then
if (RdClockEn = '1') then
Q_K_reg <= Q_K;
elsif (RdClockEn /= '0') then
Q_K_reg <= (others => 'X');
end if;
end if;
end process;
SelectOut : process (Q_K , Q_K_reg)
begin
if(module_outdata = "UNREGISTERED" and module_addressr_control = "REGISTERED") then
Q <= Q_K;
elsif(module_outdata = "REGISTERED" and module_addressr_control = "REGISTERED") then
Q <= Q_K_reg;
elsif(module_indata = "UNREGISTERED") then
assert false report "Error: module_indata should be REGISTERED" severity ERROR;
elsif(module_addressw_control = "UNREGISTERED") then
assert false report "Error: module_addressw_control should be REGISTERED" severity ERROR;
elsif(module_addressr_control = "UNREGISTERED") then
assert false report "Error: module_addressr_control should be REGISTERED" severity ERROR;
end if;
end process;
PDPRAM_inst : SC_PDPRAM_16K_L
generic map(
WADDR_WIDTH => module_widthadw,
WDATA_WIDTH => module_widthw,
RADDR_WIDTH => module_widthadr,
RDATA_WIDTH => module_widthr,
MEM_INIT_FLAG => module_init_flag,
ARRAY_SIZE => module_numwordsw*module_widthw,
MEM_INIT_FILE => module_init_file)
port map(
WCEN => WrClockEn,
WCLK => WrClock,
WE => WE,
WCS => cs,
RCLK => RdClock,
RCEN => RdClockEn,
RST => Reset,
WD => Data,
WAD => WrAddress,
RAD => RdAddress,
RD => Q_K
);
end;library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use work.components.all;
entity ram_dp_true is
generic (
module_type : string := "RAM_DP_TRUE";
module_widtha : positive;
module_widthada : positive;
module_numwordsa : positive;
module_widthb : positive;
module_widthadb : positive;
module_numwordsb : positive;
module_indata : string :="REGISTERED";
module_outdata : string :="UNREGISTERED";
module_addressa_control : string :="REGISTERED";
module_addressb_control : string :="REGISTERED";
module_init_file : string := "";
module_hint : string :="UNUSED";
module_gsr : string := "DISABLED";
module_writemode_a : string := "NORMAL";
module_writemode_b : string := "NORMAL");
port (
DataInA : in std_logic_vector(module_widtha-1 downto 0);
AddressA : in std_logic_vector(module_widthada-1 downto 0);
DataInB : in std_logic_vector(module_widthb-1 downto 0);
AddressB : in std_logic_vector(module_widthadb-1 downto 0);
ClockA : in std_logic := '0';
ClockEnA : in std_logic := '0';
ClockB : in std_logic := '0';
ClockEnB : in std_logic := '0';
WrA : in std_logic;
WrB : in std_logic;
ResetA : in std_logic;
ResetB : in std_logic;
QA : out std_logic_vector(module_widtha-1 downto 0);
QB : out std_logic_vector(module_widthb-1 downto 0));
end ram_dp_true;
architecture fun_simulation of ram_dp_true is
component SC_DPRAM_16K_L
generic (
AWRITE_MODE : string := "NORMAL";
BWRITE_MODE : string := "NORMAL";
ADDR_WIDTH_A : integer := 13;
DATA_WIDTH_A : integer := 2;
ADDR_WIDTH_B : integer := 14;
DATA_WIDTH_B : integer := 1;
MEM_INIT_FLAG : integer := 0;
ARRAY_SIZE : integer := 511;
MEM_INIT_FILE : string := "mem_init_file"
);
port (
CENA : in STD_LOGIC ;
CLKA : in STD_LOGIC ;
WRA : in STD_LOGIC ;
CSA : in STD_LOGIC_VECTOR (1 downto 0);
RSTA : in STD_LOGIC ;
DIA : in STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
ADA : in STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
DOA : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
CENB : in STD_LOGIC ;
CLKB : in STD_LOGIC ;
WRB : in STD_LOGIC ;
CSB : in STD_LOGIC_VECTOR (1 downto 0);
RSTB : in STD_LOGIC ;
DIB : in STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
ADB : in STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
DOB : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
);
end component;
signal CS : std_logic_vector ( 1 downto 0);
signal QA_int, QA_int_reg : std_logic_vector(module_widtha-1 downto 0);
signal QB_int, QB_int_reg : std_logic_vector(module_widthb-1 downto 0);
CONSTANT module_init_flag : integer := init_flag(module_init_file);
begin
CS <= "11";
OutRegisterA : process(ClockA, ResetA)
begin
if(ResetA = '1') then QA_int_reg <= (others => '0');
elsif (ClockA'EVENT and ClockA = '1') then
if (ClockEnA = '1') then
QA_int_reg <= QA_int;
elsif (ClockEnA /= '0') then
QA_int_reg <= (others => 'X');
end if;
end if;
end process;
OutRegisterB : process(ClockB, ResetB)
begin
if(ResetB = '1') then QB_int_reg <= (others => '0');
elsif (ClockB'EVENT and ClockB = '1') then
if (ClockEnB = '1') then
QB_int_reg <= QB_int;
elsif (ClockEnB /= '0') then
QB_int_reg <= (others => 'X');
end if;
end if;
end process;
SelectA : process (QA_int , QA_int_reg)
begin
if(module_outdata = "UNREGISTERED" and module_addressa_control = "REGISTERED") then
QA <= QA_int;
elsif(module_outdata = "REGISTERED" and module_addressa_control = "REGISTERED") then
QA <= QA_int_reg;
elsif(module_indata = "UNREGISTERED") then
assert false report "Error: module_indata should be REGISTERED" severity ERROR;
elsif(module_addressa_control = "UNREGISTERED") then
assert false report "Error: module_addressa_control should be REGISTERED" severity ERROR;
end if;
end process;
SelectB : process (QB_int , QB_int_reg)
begin
if(module_outdata = "UNREGISTERED" and module_addressb_control = "REGISTERED") then
QB <= QB_int;
elsif(module_outdata = "REGISTERED" and module_addressb_control = "REGISTERED") then
QB <= QB_int_reg;
elsif(module_addressa_control = "UNREGISTERED") then
assert false report "Error: module_addressa_control should be REGISTERED" severity ERROR;
end if;
end process;
RAM_DP_INST : SC_DPRAM_16K_L
generic map(
ADDR_WIDTH_A => module_widthada,
DATA_WIDTH_A => module_widtha,
ADDR_WIDTH_B => module_widthadb,
DATA_WIDTH_B => module_widthb,
MEM_INIT_FLAG => module_init_flag,
ARRAY_SIZE => module_numwordsa*module_widtha,
MEM_INIT_FILE => module_init_file,
AWRITE_MODE => module_writemode_a,
BWRITE_MODE => module_writemode_b
)
port map (
CENA => ClockEnA,
CLKA => ClockA,
WRA => WrA,
CSA => CS,
RSTA => ResetA,
DIA => DataInA,
ADA => AddressA,
DOA => QA_int,
CENB => ClockEnB,
CLKB => ClockB,
WRB => WrB,
CSB => CS,
RSTB => ResetB,
DIB => DataInB,
ADB => AddressB,
DOB => QB_int
);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use work.components.all;
entity ram_dq is
generic(
module_type : string := "RAM_DQ";
module_width : integer := 1;
module_numwords : integer := 1;
module_widthad : integer := 1;
module_indata : string := "REGISTERED";
module_outdata : string := "UNREGISTERED";
module_address_control : string := "REGISTERED";
module_init_file : string := "";
module_hint : string := "UNUSED";
module_gsr : string := "DISABLED";
module_writemode : string := "NORMAL");
port(
Data : in std_logic_vector (module_width-1 downto 0);
Address : in std_logic_vector (module_widthad-1 downto 0);
Clock : in std_logic;
ClockEn : in std_logic;
WE : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector (module_width-1 downto 0));
end ram_dq;
architecture fun_simulation of ram_dq is
component SC_SPRAM_16K_L
generic (
WRITE_MODE : string := "NORMAL";
ADDR_WIDTH : integer := 13;
DATA_WIDTH : integer := 2;
MEM_INIT_FLAG : integer := 1;
ARRAY_SIZE : integer := 511;
MEM_INIT_FILE : string := "qq.dat"
);
port (
CEN : in STD_LOGIC ;
CLK : in STD_LOGIC ;
WR : in STD_LOGIC ;
CS : in STD_LOGIC_VECTOR (1 downto 0);
RST : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
AD : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
signal cs : std_logic_vector (1 downto 0);
signal Q_K : std_logic_vector (module_width-1 downto 0);
signal Q_K_reg : std_logic_vector (module_width-1 downto 0);
CONSTANT module_init_flag : integer := init_flag(module_init_file);
begin
cs <= "11";
OutRegister : process(Clock, Reset)
begin
if (Reset = '1') then
Q_K_reg <= (others => '0');
elsif (Clock'EVENT and Clock = '1') then
if (ClockEn = '1') then
Q_K_reg <= Q_K;
elsif (ClockEn /= '0') then
Q_K_reg <= (others => 'X');
end if;
end if;
end process;
SelectOut : process (Q_K , Q_K_reg)
begin
if(module_outdata = "UNREGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K;
elsif(module_outdata = "REGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K_reg;
elsif(module_indata = "UNREGISTERED") then
assert false report "Error: module_indata should be REGISTERED" severity ERROR;
elsif(module_address_control = "UNREGISTERED") then
assert false report "Error: module_address_control should be REGISTERED" severity ERROR;
end if;
end process;
SPRAM_inst : SC_SPRAM_16K_L
generic map (
ADDR_WIDTH => module_widthad,
DATA_WIDTH => module_width,
MEM_INIT_FLAG => module_init_flag,
ARRAY_SIZE => module_numwords * module_width,
MEM_INIT_FILE => module_init_file,
WRITE_MODE => module_writemode)
port map (
CEN => ClockEn,
CLK => Clock,
WR => WE,
CS => cs,
RST => Reset,
DI => Data,
AD => Address,
DO => Q_K
);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
entity rom is
generic (
module_type : string := "ROM";
module_width : integer := 1;
module_numwords : integer := 1;
module_widthad : integer := 1;
module_outdata : string := "REGISTERED";
module_address_control : string := "REGISTERED";
module_init_file : string := "init_file";
module_gsr : string := "DISABLED";
module_hint : string := "UNUSED");
port (
Address : in std_logic_vector (module_widthad-1 downto 0);
OutClock : in std_logic;
OutClockEn : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector (module_width-1 downto 0));
end rom;
architecture fun_simulation of rom is
component SC_SPRAM_16K_L
generic (
ADDR_WIDTH : integer := 13;
DATA_WIDTH : integer := 2;
ARRAY_SIZE : integer := 511;
MEM_INIT_FLAG : integer := 1;
MEM_INIT_FILE : string := "qq.dat"
);
port (
CEN : in STD_LOGIC ;
CLK : in STD_LOGIC ;
WR : in STD_LOGIC ;
CS : in STD_LOGIC_VECTOR (1 downto 0);
RST : in STD_LOGIC ;
DI : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
AD : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
signal cs : std_logic_vector ( 1 downto 0);
signal DI_sig : std_logic_vector (module_width-1 downto 0);
signal WE_sig : std_logic;
signal Q_K : std_logic_vector (module_width-1 downto 0);
signal Q_K_reg : std_logic_vector (module_width-1 downto 0);
begin
cs <= "11";
WE_sig <= '0';
OutRegister : process(OutClock, Reset)
begin
if (Reset = '1') then
Q_K_reg <= (others => '0');
elsif (OutClock'EVENT and OutClock = '1') then
if(OutClockEn = '1') then
Q_K_reg <= Q_K;
elsif(OutClockEn /= '0') then
Q_K_reg <= (others => 'X' );
end if;
end if;
end process;
SelectOut : process (Q_K , Q_K_reg)
begin
if(module_outdata = "UNREGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K;
elsif(module_outdata = "REGISTERED" and module_address_control = "REGISTERED") then
Q <= Q_K_reg;
elsif(module_address_control = "UNREGISTERED") then
assert false report "Error: module_address_control should be REGISTERED" severity ERROR;
end if;
end process;
SPRAM_inst : SC_SPRAM_16K_L
generic map(
ADDR_WIDTH => module_widthad,
DATA_WIDTH => module_width,
MEM_INIT_FLAG => 1,
ARRAY_SIZE => module_numwords * module_width,
MEM_INIT_FILE => module_init_file)
port map(
CEN => OutClockEn,
CLK => OutClock,
WR => WE_sig,
CS => cs,
RST => Reset,
DI => DI_sig,
AD => Address,
DO => Q_K
);
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
--------------------------------------------------------------------------------
package lfsr_components is
component pulse is
generic (
G_lfsr_width : natural := 3;
G_period : natural := 7
);
port(
CLK : in std_logic;
RESET : in std_logic;
PULSE : out std_logic
);
end component;
end lfsr_components; |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: videorom.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 18.0.0 Build 614 04/24/2018 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2018 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY videorom IS
PORT
(
address : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rden : IN STD_LOGIC := '1';
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END videorom;
ARCHITECTURE SYN OF videorom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "NORMAL",
clock_enable_output_a => "BYPASS",
init_file => "test_videorom.hex",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=VROM",
lpm_type => "altsyncram",
numwords_a => 8192,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 13,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
clocken0 => clken,
data_a => data,
rden_a => rden,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: Clken NUMERIC "1"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "VROM"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "test_videorom.hex"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "test_videorom.hex"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=VROM"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL videorom.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL videorom.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL videorom.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL videorom.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL videorom_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Left/Right shifter arithmetic/logic 32/64 bits.
--!
--! @details Vivado synthesizer (2016.2) doesn't support shift
--! from dynamic value, so implement this mux.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
entity Shifter is
port (
i_a1 : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Operand 1
i_a2 : in std_logic_vector(5 downto 0); -- Shift bits number
o_sll : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Logical shift left 64-bits operand
o_sllw : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Logical shift left 32-bits operand
o_srl : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Logical shift 64 bits
o_sra : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Arith. shift 64 bits
o_srlw : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Logical shift 32 bits
o_sraw : out std_logic_vector(RISCV_ARCH-1 downto 0) -- Arith. shift 32 bits
);
end;
architecture arch_Shifter of Shifter is
begin
comb : process(i_a1, i_a2)
variable wb_sll : std_logic_vector(63 downto 0);
variable wb_srl : std_logic_vector(63 downto 0);
variable wb_sra : std_logic_vector(63 downto 0);
variable wb_sllw : std_logic_vector(63 downto 0);
variable wb_srlw : std_logic_vector(63 downto 0);
variable wb_sraw : std_logic_vector(63 downto 0);
variable v64 : std_logic_vector(63 downto 0);
variable v32 : std_logic_vector(31 downto 0);
variable msk64 : std_logic_vector(63 downto 0);
variable msk32 : std_logic_vector(63 downto 0);
variable shift64 : integer range 0 to 63;
variable shift32 : integer range 0 to 31;
begin
v64 := i_a1;
v32 := i_a1(31 downto 0);
msk64 := (others => i_a1(63));
msk32 := (others => i_a1(31));
shift64 := conv_integer(i_a2);
shift32 := conv_integer(i_a2(4 downto 0));
case shift64 is
when 0 =>
wb_sll := v64;
wb_srl := v64;
wb_sra := v64;
when 1 =>
wb_sll := v64(62 downto 0) & "0";
wb_srl := "0" & v64(63 downto 1);
wb_sra := (msk64(63 downto 63) & v64(63 downto 1));
when 2 =>
wb_sll := v64(61 downto 0) & "00";
wb_srl := "00" & v64(63 downto 2);
wb_sra := (msk64(63 downto 62) & v64(63 downto 2));
when 3 =>
wb_sll := v64(60 downto 0) & "000";
wb_srl := "000" & v64(63 downto 3);
wb_sra := (msk64(63 downto 61) & v64(63 downto 3));
when 4 =>
wb_sll := v64(59 downto 0) & X"0";
wb_srl := X"0" & v64(63 downto 4);
wb_sra := (msk64(63 downto 60) & v64(63 downto 4));
when 5 =>
wb_sll := v64(58 downto 0) & X"0" & "0";
wb_srl := X"0" & "0" & v64(63 downto 5);
wb_sra := (msk64(63 downto 59) & v64(63 downto 5));
when 6 =>
wb_sll := v64(57 downto 0) & X"0" & "00";
wb_srl := X"0" & "00" & v64(63 downto 6);
wb_sra := (msk64(63 downto 58) & v64(63 downto 6));
when 7 =>
wb_sll := v64(56 downto 0) & X"0" & "000";
wb_srl := X"0" & "000" & v64(63 downto 7);
wb_sra := (msk64(63 downto 57) & v64(63 downto 7));
when 8 =>
wb_sll := v64(55 downto 0) & X"00";
wb_srl := X"00" & v64(63 downto 8);
wb_sra := (msk64(63 downto 56) & v64(63 downto 8));
when 9 =>
wb_sll := v64(54 downto 0) & X"00" & "0";
wb_srl := X"00" & "0" & v64(63 downto 9);
wb_sra := (msk64(63 downto 55) & v64(63 downto 9));
when 10 =>
wb_sll := v64(53 downto 0) & X"00" & "00";
wb_srl := X"00" & "00" & v64(63 downto 10);
wb_sra := (msk64(63 downto 54) & v64(63 downto 10));
when 11 =>
wb_sll := v64(52 downto 0) & X"00" & "000";
wb_srl := X"00" & "000" & v64(63 downto 11);
wb_sra := (msk64(63 downto 53) & v64(63 downto 11));
when 12 =>
wb_sll := v64(51 downto 0) & X"000";
wb_srl := X"000" & v64(63 downto 12);
wb_sra := (msk64(63 downto 52) & v64(63 downto 12));
when 13 =>
wb_sll := v64(50 downto 0) & X"000" & "0";
wb_srl := X"000" & "0" & v64(63 downto 13);
wb_sra := (msk64(63 downto 51) & v64(63 downto 13));
when 14 =>
wb_sll := v64(49 downto 0) & X"000" & "00";
wb_srl := X"000" & "00" & v64(63 downto 14);
wb_sra := (msk64(63 downto 50) & v64(63 downto 14));
when 15 =>
wb_sll := v64(48 downto 0) & X"000" & "000";
wb_srl := X"000" & "000" & v64(63 downto 15);
wb_sra := (msk64(63 downto 49) & v64(63 downto 15));
when 16 =>
wb_sll := v64(47 downto 0) & X"0000";
wb_srl := X"0000" & v64(63 downto 16);
wb_sra := (msk64(63 downto 48) & v64(63 downto 16));
when 17 =>
wb_sll := v64(46 downto 0) & X"0000" & "0";
wb_srl := X"0000" & "0" & v64(63 downto 17);
wb_sra := (msk64(63 downto 47) & v64(63 downto 17));
when 18 =>
wb_sll := v64(45 downto 0) & X"0000" & "00";
wb_srl := X"0000" & "00" & v64(63 downto 18);
wb_sra := (msk64(63 downto 46) & v64(63 downto 18));
when 19 =>
wb_sll := v64(44 downto 0) & X"0000" & "000";
wb_srl := X"0000" & "000" & v64(63 downto 19);
wb_sra := (msk64(63 downto 45) & v64(63 downto 19));
when 20 =>
wb_sll := v64(43 downto 0) & X"00000";
wb_srl := X"00000" & v64(63 downto 20);
wb_sra := (msk64(63 downto 44) & v64(63 downto 20));
when 21 =>
wb_sll := v64(42 downto 0) & X"00000" & "0";
wb_srl := X"00000" & "0" & v64(63 downto 21);
wb_sra := (msk64(63 downto 43) & v64(63 downto 21));
when 22 =>
wb_sll := v64(41 downto 0) & X"00000" & "00";
wb_srl := X"00000" & "00" & v64(63 downto 22);
wb_sra := (msk64(63 downto 42) & v64(63 downto 22));
when 23 =>
wb_sll := v64(40 downto 0) & X"00000" & "000";
wb_srl := X"00000" & "000" & v64(63 downto 23);
wb_sra := (msk64(63 downto 41) & v64(63 downto 23));
when 24 =>
wb_sll := v64(39 downto 0) & X"000000";
wb_srl := X"000000" & v64(63 downto 24);
wb_sra := (msk64(63 downto 40) & v64(63 downto 24));
when 25 =>
wb_sll := v64(38 downto 0) & X"000000" & "0";
wb_srl := X"000000" & "0" & v64(63 downto 25);
wb_sra := (msk64(63 downto 39) & v64(63 downto 25));
when 26 =>
wb_sll := v64(37 downto 0) & X"000000" & "00";
wb_srl := X"000000" & "00" & v64(63 downto 26);
wb_sra := (msk64(63 downto 38) & v64(63 downto 26));
when 27 =>
wb_sll := v64(36 downto 0) & X"000000" & "000";
wb_srl := X"000000" & "000" & v64(63 downto 27);
wb_sra := (msk64(63 downto 37) & v64(63 downto 27));
when 28 =>
wb_sll := v64(35 downto 0) & X"0000000";
wb_srl := X"0000000" & v64(63 downto 28);
wb_sra := (msk64(63 downto 36) & v64(63 downto 28));
when 29 =>
wb_sll := v64(34 downto 0) & X"0000000" & "0";
wb_srl := X"0000000" & "0" & v64(63 downto 29);
wb_sra := (msk64(63 downto 35) & v64(63 downto 29));
when 30 =>
wb_sll := v64(33 downto 0) & X"0000000" & "00";
wb_srl := X"0000000" & "00" & v64(63 downto 30);
wb_sra := (msk64(63 downto 34) & v64(63 downto 30));
when 31 =>
wb_sll := v64(32 downto 0) & X"0000000" & "000";
wb_srl := X"0000000" & "000" & v64(63 downto 31);
wb_sra := (msk64(63 downto 33) & v64(63 downto 31));
when 32 =>
wb_sll := v64(31 downto 0) & X"00000000";
wb_srl := X"00000000" & v64(63 downto 32);
wb_sra := (msk64(63 downto 32) & v64(63 downto 32));
when 33 =>
wb_sll := v64(30 downto 0) & X"00000000" & "0";
wb_srl := X"00000000" & "0" & v64(63 downto 33);
wb_sra := (msk64(63 downto 31) & v64(63 downto 33));
when 34 =>
wb_sll := v64(29 downto 0) & X"00000000" & "00";
wb_srl := X"00000000" & "00" & v64(63 downto 34);
wb_sra := (msk64(63 downto 30) & v64(63 downto 34));
when 35 =>
wb_sll := v64(28 downto 0) & X"00000000" & "000";
wb_srl := X"00000000" & "000" & v64(63 downto 35);
wb_sra := (msk64(63 downto 29) & v64(63 downto 35));
when 36 =>
wb_sll := v64(27 downto 0) & X"000000000";
wb_srl := X"000000000" & v64(63 downto 36);
wb_sra := (msk64(63 downto 28) & v64(63 downto 36));
when 37 =>
wb_sll := v64(26 downto 0) & X"000000000" & "0";
wb_srl := X"000000000" & "0" & v64(63 downto 37);
wb_sra := (msk64(63 downto 27) & v64(63 downto 37));
when 38 =>
wb_sll := v64(25 downto 0) & X"000000000" & "00";
wb_srl := X"000000000" & "00" & v64(63 downto 38);
wb_sra := (msk64(63 downto 26) & v64(63 downto 38));
when 39 =>
wb_sll := v64(24 downto 0) & X"000000000" & "000";
wb_srl := X"000000000" & "000" & v64(63 downto 39);
wb_sra := (msk64(63 downto 25) & v64(63 downto 39));
when 40 =>
wb_sll := v64(23 downto 0) & X"0000000000";
wb_srl := X"0000000000" & v64(63 downto 40);
wb_sra := (msk64(63 downto 24) & v64(63 downto 40));
when 41 =>
wb_sll := v64(22 downto 0) & X"0000000000" & "0";
wb_srl := X"0000000000" & "0" & v64(63 downto 41);
wb_sra := (msk64(63 downto 23) & v64(63 downto 41));
when 42 =>
wb_sll := v64(21 downto 0) & X"0000000000" & "00";
wb_srl := X"0000000000" & "00" & v64(63 downto 42);
wb_sra := (msk64(63 downto 22) & v64(63 downto 42));
when 43 =>
wb_sll := v64(20 downto 0) & X"0000000000" & "000";
wb_srl := X"0000000000" & "000" & v64(63 downto 43);
wb_sra := (msk64(63 downto 21) & v64(63 downto 43));
when 44 =>
wb_sll := v64(19 downto 0) & X"00000000000";
wb_srl := X"00000000000" & v64(63 downto 44);
wb_sra := (msk64(63 downto 20) & v64(63 downto 44));
when 45 =>
wb_sll := v64(18 downto 0) & X"00000000000" & "0";
wb_srl := X"00000000000" & "0" & v64(63 downto 45);
wb_sra := (msk64(63 downto 19) & v64(63 downto 45));
when 46 =>
wb_sll := v64(17 downto 0) & X"00000000000" & "00";
wb_srl := X"00000000000" & "00" & v64(63 downto 46);
wb_sra := (msk64(63 downto 18) & v64(63 downto 46));
when 47 =>
wb_sll := v64(16 downto 0) & X"00000000000" & "000";
wb_srl := X"00000000000" & "000" & v64(63 downto 47);
wb_sra := (msk64(63 downto 17) & v64(63 downto 47));
when 48 =>
wb_sll := v64(15 downto 0) & X"000000000000";
wb_srl := X"000000000000" & v64(63 downto 48);
wb_sra := (msk64(63 downto 16) & v64(63 downto 48));
when 49 =>
wb_sll := v64(14 downto 0) & X"000000000000" & "0";
wb_srl := X"000000000000" & "0" & v64(63 downto 49);
wb_sra := (msk64(63 downto 15) & v64(63 downto 49));
when 50 =>
wb_sll := v64(13 downto 0) & X"000000000000" & "00";
wb_srl := X"000000000000" & "00" & v64(63 downto 50);
wb_sra := (msk64(63 downto 14) & v64(63 downto 50));
when 51 =>
wb_sll := v64(12 downto 0) & X"000000000000" & "000";
wb_srl := X"000000000000" & "000" & v64(63 downto 51);
wb_sra := (msk64(63 downto 13) & v64(63 downto 51));
when 52 =>
wb_sll := v64(11 downto 0) & X"0000000000000";
wb_srl := X"0000000000000" & v64(63 downto 52);
wb_sra := (msk64(63 downto 12) & v64(63 downto 52));
when 53 =>
wb_sll := v64(10 downto 0) & X"0000000000000" & "0";
wb_srl := X"0000000000000" & "0" & v64(63 downto 53);
wb_sra := (msk64(63 downto 11) & v64(63 downto 53));
when 54 =>
wb_sll := v64(9 downto 0) & X"0000000000000" & "00";
wb_srl := X"0000000000000" & "00" & v64(63 downto 54);
wb_sra := (msk64(63 downto 10) & v64(63 downto 54));
when 55 =>
wb_sll := v64(8 downto 0) & X"0000000000000" & "000";
wb_srl := X"0000000000000" & "000" & v64(63 downto 55);
wb_sra := (msk64(63 downto 9) & v64(63 downto 55));
when 56 =>
wb_sll := v64(7 downto 0) & X"00000000000000";
wb_srl := X"00000000000000" & v64(63 downto 56);
wb_sra := (msk64(63 downto 8) & v64(63 downto 56));
when 57 =>
wb_sll := v64(6 downto 0) & X"00000000000000" & "0";
wb_srl := X"00000000000000" & "0" & v64(63 downto 57);
wb_sra := (msk64(63 downto 7) & v64(63 downto 57));
when 58 =>
wb_sll := v64(5 downto 0) & X"00000000000000" & "00";
wb_srl := X"00000000000000" & "00" & v64(63 downto 58);
wb_sra := (msk64(63 downto 6) & v64(63 downto 58));
when 59 =>
wb_sll := v64(4 downto 0) & X"00000000000000" & "000";
wb_srl := X"00000000000000" & "000" & v64(63 downto 59);
wb_sra := (msk64(63 downto 5) & v64(63 downto 59));
when 60 =>
wb_sll := v64(3 downto 0) & X"000000000000000";
wb_srl := X"000000000000000" & v64(63 downto 60);
wb_sra := (msk64(63 downto 4) & v64(63 downto 60));
when 61 =>
wb_sll := v64(2 downto 0) & X"000000000000000" & "0";
wb_srl := X"000000000000000" & "0" & v64(63 downto 61);
wb_sra := (msk64(63 downto 3) & v64(63 downto 61));
when 62 =>
wb_sll := v64(1 downto 0) & X"000000000000000" & "00";
wb_srl := X"000000000000000" & "00" & v64(63 downto 62);
wb_sra := (msk64(63 downto 2) & v64(63 downto 62));
when 63 =>
wb_sll := v64(0) & X"000000000000000" & "000";
wb_srl := X"000000000000000" & "000" & v64(63);
wb_sra := (msk64(63 downto 1) & v64(63));
end case;
case shift32 is
when 0 =>
wb_sllw(31 downto 0) := v32;
wb_srlw(31 downto 0) := v32;
wb_sraw := (msk32(63 downto 32) & v32);
when 1 =>
wb_sllw(31 downto 0) := v32(30 downto 0) & "0";
wb_srlw(31 downto 0) := "0" & v32(31 downto 1);
wb_sraw := (msk32(63 downto 31) & v32(31 downto 1));
when 2 =>
wb_sllw(31 downto 0) := v32(29 downto 0) & "00";
wb_srlw(31 downto 0) := "00" & v32(31 downto 2);
wb_sraw := (msk32(63 downto 30) & v32(31 downto 2));
when 3 =>
wb_sllw(31 downto 0) := v32(28 downto 0) & "000";
wb_srlw(31 downto 0) := "000" & v32(31 downto 3);
wb_sraw := (msk32(63 downto 29) & v32(31 downto 3));
when 4 =>
wb_sllw(31 downto 0) := v32(27 downto 0) & X"0";
wb_srlw(31 downto 0) := X"0" & v32(31 downto 4);
wb_sraw := (msk32(63 downto 28) & v32(31 downto 4));
when 5 =>
wb_sllw(31 downto 0) := v32(26 downto 0) & X"0" & "0";
wb_srlw(31 downto 0) := X"0" & "0" & v32(31 downto 5);
wb_sraw := (msk32(63 downto 27) & v32(31 downto 5));
when 6 =>
wb_sllw(31 downto 0) := v32(25 downto 0) & X"0" & "00";
wb_srlw(31 downto 0) := X"0" & "00" & v32(31 downto 6);
wb_sraw := (msk32(63 downto 26) & v32(31 downto 6));
when 7 =>
wb_sllw(31 downto 0) := v32(24 downto 0) & X"0" & "000";
wb_srlw(31 downto 0) := X"0" & "000" & v32(31 downto 7);
wb_sraw := (msk32(63 downto 25) & v32(31 downto 7));
when 8 =>
wb_sllw(31 downto 0) := v32(23 downto 0) & X"00";
wb_srlw(31 downto 0) := X"00" & v32(31 downto 8);
wb_sraw := (msk32(63 downto 24) & v32(31 downto 8));
when 9 =>
wb_sllw(31 downto 0) := v32(22 downto 0) & X"00" & "0";
wb_srlw(31 downto 0) := X"00" & "0" & v32(31 downto 9);
wb_sraw := (msk32(63 downto 23) & v32(31 downto 9));
when 10 =>
wb_sllw(31 downto 0) := v32(21 downto 0) & X"00" & "00";
wb_srlw(31 downto 0) := X"00" & "00" & v32(31 downto 10);
wb_sraw := (msk32(63 downto 22) & v32(31 downto 10));
when 11 =>
wb_sllw(31 downto 0) := v32(20 downto 0) & X"00" & "000";
wb_srlw(31 downto 0) := X"00" & "000" & v32(31 downto 11);
wb_sraw := (msk32(63 downto 21) & v32(31 downto 11));
when 12 =>
wb_sllw(31 downto 0) := v32(19 downto 0) & X"000";
wb_srlw(31 downto 0) := X"000" & v32(31 downto 12);
wb_sraw := (msk32(63 downto 20) & v32(31 downto 12));
when 13 =>
wb_sllw(31 downto 0) := v32(18 downto 0) & X"000" & "0";
wb_srlw(31 downto 0) := X"000" & "0" & v32(31 downto 13);
wb_sraw := (msk32(63 downto 19) & v32(31 downto 13));
when 14 =>
wb_sllw(31 downto 0) := v32(17 downto 0) & X"000" & "00";
wb_srlw(31 downto 0) := X"000" & "00" & v32(31 downto 14);
wb_sraw := (msk32(63 downto 18) & v32(31 downto 14));
when 15 =>
wb_sllw(31 downto 0) := v32(16 downto 0) & X"000" & "000";
wb_srlw(31 downto 0) := X"000" & "000" & v32(31 downto 15);
wb_sraw := (msk32(63 downto 17) & v32(31 downto 15));
when 16 =>
wb_sllw(31 downto 0) := v32(15 downto 0) & X"0000";
wb_srlw(31 downto 0) := X"0000" & v32(31 downto 16);
wb_sraw := (msk32(63 downto 16) & v32(31 downto 16));
when 17 =>
wb_sllw(31 downto 0) := v32(14 downto 0) & X"0000" & "0";
wb_srlw(31 downto 0) := X"0000" & "0" & v32(31 downto 17);
wb_sraw := (msk32(63 downto 15) & v32(31 downto 17));
when 18 =>
wb_sllw(31 downto 0) := v32(13 downto 0) & X"0000" & "00";
wb_srlw(31 downto 0) := X"0000" & "00" & v32(31 downto 18);
wb_sraw := (msk32(63 downto 14) & v32(31 downto 18));
when 19 =>
wb_sllw(31 downto 0) := v32(12 downto 0) & X"0000" & "000";
wb_srlw(31 downto 0) := X"0000" & "000" & v32(31 downto 19);
wb_sraw := (msk32(63 downto 13) & v32(31 downto 19));
when 20 =>
wb_sllw(31 downto 0) := v32(11 downto 0) & X"00000";
wb_srlw(31 downto 0) := X"00000" & v32(31 downto 20);
wb_sraw := (msk32(63 downto 12) & v32(31 downto 20));
when 21 =>
wb_sllw(31 downto 0) := v32(10 downto 0) & X"00000" & "0";
wb_srlw(31 downto 0) := X"00000" & "0" & v32(31 downto 21);
wb_sraw := (msk32(63 downto 11) & v32(31 downto 21));
when 22 =>
wb_sllw(31 downto 0) := v32(9 downto 0) & X"00000" & "00";
wb_srlw(31 downto 0) := X"00000" & "00" & v32(31 downto 22);
wb_sraw := (msk32(63 downto 10) & v32(31 downto 22));
when 23 =>
wb_sllw(31 downto 0) := v32(8 downto 0) & X"00000" & "000";
wb_srlw(31 downto 0) := X"00000" & "000" & v32(31 downto 23);
wb_sraw := (msk32(63 downto 9) & v32(31 downto 23));
when 24 =>
wb_sllw(31 downto 0) := v32(7 downto 0) & X"000000";
wb_srlw(31 downto 0) := X"000000" & v32(31 downto 24);
wb_sraw := (msk32(63 downto 8) & v32(31 downto 24));
when 25 =>
wb_sllw(31 downto 0) := v32(6 downto 0) & X"000000" & "0";
wb_srlw(31 downto 0) := X"000000" & "0" & v32(31 downto 25);
wb_sraw := (msk32(63 downto 7) & v32(31 downto 25));
when 26 =>
wb_sllw(31 downto 0) := v32(5 downto 0) & X"000000" & "00";
wb_srlw(31 downto 0) := X"000000" & "00" & v32(31 downto 26);
wb_sraw := (msk32(63 downto 6) & v32(31 downto 26));
when 27 =>
wb_sllw(31 downto 0) := v32(4 downto 0) & X"000000" & "000";
wb_srlw(31 downto 0) := X"000000" & "000" & v32(31 downto 27);
wb_sraw := (msk32(63 downto 5) & v32(31 downto 27));
when 28 =>
wb_sllw(31 downto 0) := v32(3 downto 0) & X"0000000";
wb_srlw(31 downto 0) := X"0000000" & v32(31 downto 28);
wb_sraw := (msk32(63 downto 4) & v32(31 downto 28));
when 29 =>
wb_sllw(31 downto 0) := v32(2 downto 0) & X"0000000" & "0";
wb_srlw(31 downto 0) := X"0000000" & "0" & v32(31 downto 29);
wb_sraw := (msk32(63 downto 3) & v32(31 downto 29));
when 30 =>
wb_sllw(31 downto 0) := v32(1 downto 0) & X"0000000" & "00";
wb_srlw(31 downto 0) := X"0000000" & "00" & v32(31 downto 30);
wb_sraw := (msk32(63 downto 2) & v32(31 downto 30));
when 31 =>
wb_sllw(31 downto 0) := v32(0) & X"0000000" & "000";
wb_srlw(31 downto 0) := X"0000000" & "000" & v32(31 downto 31);
wb_sraw := (msk32(63 downto 1) & v32(31 downto 31));
end case;
-- Take into account case when shift = 0 and input value a[31]=1
wb_srlw(63 downto 32) := (others => wb_srlw(31));
wb_sllw(63 downto 32) := (others => wb_sllw(31));
o_sll <= wb_sll;
o_srl <= wb_srl;
o_sra <= wb_sra;
o_sllw <= wb_sllw;
o_srlw <= wb_srlw;
o_sraw <= wb_sraw;
end process;
end;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:26:45 10/11/2015
-- Design Name:
-- Module Name: C:/Users/Felipe/Desktop/sparcv8/sparcv8_v2_tb.vhd
-- Project Name: sparcv8
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: sparcv8_v2
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY sparcv8_v2_tb IS
END sparcv8_v2_tb;
ARCHITECTURE behavior OF sparcv8_v2_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sparcv8_v2
PORT(
clk : IN std_logic;
reset : IN std_logic;
alurs : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal alurs : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sparcv8_v2 PORT MAP (
clk => clk,
reset => reset,
alurs => alurs
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for clk_period;
reset <= '0';
wait;
end process;
END;
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
port map (
PORT_1 => w_port_1-- Comment
);
U_INST1 : INST1
port map (
PORT_1 => w_port_1-- Comment
);
U_INST1 : INST1
port map (
PORT_1 => w_port_1 -- Comment
);
U_INST1 : INST1
port map (
PORT_1 => w_port_1 -- Comment
);
U_INST1 : INST1
port map (
PORT_1 => w_port_1 -- Comment
);-- Comment2
U_INST1 : INST1
port map (
PORT_1 => w_port_1 -- Comment
);-- Comment2
U_INST1 : INST1
port map (
PORT_1 => w_port_1 -- Comment
); -- Comment2
U_INST1 : INST1
port map (
PORT_1 => w_port_1 -- Comment
); -- Comment2
end architecture ARCH;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--lab1_three_leds UNISIM;
--use UNISIM.VComponents.all;
entity lab1_three_leds is
Port ( dipsw1 : in std_logic_vector(7 downto 0);
dipsw2 : in std_logic_vector(7 downto 0);
dipsw3 : in std_logic_vector(7 downto 0);
led1 : out std_logic_vector(7 downto 0);
led2 : out std_logic_vector(7 downto 0);
led3 : out std_logic_vector(7 downto 0));
end lab1_three_leds;
architecture Behavioral of lab1_three_leds is
begin
led1 <= dipsw1;
led2 <= dipsw2;
led3 <= dipsw3;
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity testcase is
end testcase;
|
--
-- Author: Pawel Szostek ([email protected])
-- Date: 27.07.2011
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity match_bits is
port (a,b: in std_logic_vector(7 downto 0);
matches : out std_logic_vector(7 downto 0)
);
end;
architecture behaviour of match_bits is
begin
process(a, b) begin
for i in 7 downto 0 loop
matches(i) <= not (a(i) xor b(i));
end loop;
end process;
end;
|
--
-- Author: Pawel Szostek ([email protected])
-- Date: 27.07.2011
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity match_bits is
port (a,b: in std_logic_vector(7 downto 0);
matches : out std_logic_vector(7 downto 0)
);
end;
architecture behaviour of match_bits is
begin
process(a, b) begin
for i in 7 downto 0 loop
matches(i) <= not (a(i) xor b(i));
end loop;
end process;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use gaisler.misc.all;
entity ahbstat is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
stati : in ahbstat_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end entity;
architecture rtl of ahbstat is
type reg_type is record
addr : std_logic_vector(31 downto 0); --failing address
hsize : std_logic_vector(2 downto 0); --ahb signals for failing op.
hmaster : std_logic_vector(3 downto 0);
hwrite : std_ulogic;
hresp : std_logic_vector(1 downto 0);
newerr : std_ulogic; --new error detected
cerror : std_ulogic; --correctable error detected
pirq : std_ulogic;
end record;
signal r, rin : reg_type;
constant VERSION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_AHBSTAT, 0, VERSION, pirq),
1 => apb_iobar(paddr, pmask));
begin
comb : process(rst, ahbmi, ahbsi, stati, apbi, r) is
variable v : reg_type;
variable prdata : std_logic_vector(31 downto 0);
variable vpirq : std_logic_vector(NAHBIRQ - 1 downto 0);
variable ce : std_ulogic; --correctable error
begin
v := r; vpirq := (others => '0'); prdata := (others => '0'); v.pirq := '0';
ce := orv(stati.cerror(0 to nftslv-1));
case apbi.paddr(2) is
when '0' => --status values
prdata(2 downto 0) := r.hsize;
prdata(6 downto 3) := r.hmaster;
prdata(7) := r.hwrite;
prdata(8) := r.newerr;
prdata(9) := r.cerror;
when others => --failing address
prdata := r.addr;
end case;
--writes. data is written in setup cycle so that r.newerr is updated
--when hready = '1'
if (apbi.psel(pindex) and not apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(2) is
when '0' =>
v.newerr := apbi.pwdata(8);
v.cerror := apbi.pwdata(9);
when others => null;
end case;
end if;
v.hresp := ahbmi.hresp;
if (ahbsi.hready = '1') and (r.newerr = '0') then
if (r.hresp = HRESP_ERROR) or (ce = '1') then v.newerr := '1';
v.cerror := ce;
else
v.addr := ahbsi.haddr;
v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hwrite := ahbsi.hwrite;
end if;
end if;
--irq generation
v.pirq := v.newerr and not r.newerr;
vpirq(pirq) := r.pirq;
--reset
if rst = '0' then
v.newerr := '0'; v.cerror := '0';
end if;
rin <= v;
apbo.prdata <= prdata;
apbo.pirq <= vpirq;
end process;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("ahbstat" & tost(pindex) &
": AHB status unit rev " & tost(VERSION) &
", irq " & tost(pirq));
-- pragma translate_on
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use gaisler.misc.all;
entity ahbstat is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
stati : in ahbstat_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end entity;
architecture rtl of ahbstat is
type reg_type is record
addr : std_logic_vector(31 downto 0); --failing address
hsize : std_logic_vector(2 downto 0); --ahb signals for failing op.
hmaster : std_logic_vector(3 downto 0);
hwrite : std_ulogic;
hresp : std_logic_vector(1 downto 0);
newerr : std_ulogic; --new error detected
cerror : std_ulogic; --correctable error detected
pirq : std_ulogic;
end record;
signal r, rin : reg_type;
constant VERSION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_AHBSTAT, 0, VERSION, pirq),
1 => apb_iobar(paddr, pmask));
begin
comb : process(rst, ahbmi, ahbsi, stati, apbi, r) is
variable v : reg_type;
variable prdata : std_logic_vector(31 downto 0);
variable vpirq : std_logic_vector(NAHBIRQ - 1 downto 0);
variable ce : std_ulogic; --correctable error
begin
v := r; vpirq := (others => '0'); prdata := (others => '0'); v.pirq := '0';
ce := orv(stati.cerror(0 to nftslv-1));
case apbi.paddr(2) is
when '0' => --status values
prdata(2 downto 0) := r.hsize;
prdata(6 downto 3) := r.hmaster;
prdata(7) := r.hwrite;
prdata(8) := r.newerr;
prdata(9) := r.cerror;
when others => --failing address
prdata := r.addr;
end case;
--writes. data is written in setup cycle so that r.newerr is updated
--when hready = '1'
if (apbi.psel(pindex) and not apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(2) is
when '0' =>
v.newerr := apbi.pwdata(8);
v.cerror := apbi.pwdata(9);
when others => null;
end case;
end if;
v.hresp := ahbmi.hresp;
if (ahbsi.hready = '1') and (r.newerr = '0') then
if (r.hresp = HRESP_ERROR) or (ce = '1') then v.newerr := '1';
v.cerror := ce;
else
v.addr := ahbsi.haddr;
v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hwrite := ahbsi.hwrite;
end if;
end if;
--irq generation
v.pirq := v.newerr and not r.newerr;
vpirq(pirq) := r.pirq;
--reset
if rst = '0' then
v.newerr := '0'; v.cerror := '0';
end if;
rin <= v;
apbo.prdata <= prdata;
apbo.pirq <= vpirq;
end process;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("ahbstat" & tost(pindex) &
": AHB status unit rev " & tost(VERSION) &
", irq " & tost(pirq));
-- pragma translate_on
end architecture;
|
-------------------------------------------------------------------------------
-- $Id: dynshreg2_f.vhd,v 1.1.4.50 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- dynshreg2_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg2_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
-- This version differs from dynshreg_f only in that it
-- has a work around needed to get the C_DEPTH = 1 case
-- past a target synthesis tool.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- Functionally identical but with work-around
-- as noted in the description.
--
-- ~~~~~~
-- FLO MM/DD/YYYY
-- ^^^^^^
-- History comment.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.clog2;
entity dynshreg2_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg2_f;
library proc_common_v3_00_a;
use proc_common_v3_00_a.family_support.all;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture behavioral of dynshreg2_f is
constant K_FAMILY : families_type := str2fam(C_FAMILY);
--
constant W32 : boolean := supported(K_FAMILY, u_SRLC32E) and
(C_DEPTH > 16 or not supported(K_FAMILY, u_SRL16E));
constant W16 : boolean := supported(K_FAMILY, u_SRLC16E) and not W32;
-- XST faster if these two constants are declared here
-- instead of in STRUCTURAL_A_GEN. (I.25)
--
function power_of_2(n: positive) return boolean is
variable i: positive := 1;
begin
while n > i loop i := i*2; end loop;
return n = i;
end power_of_2;
--
constant USE_ONEDEEP : boolean := (C_DEPTH = 1); -- Case needing XST workaround
--
constant USE_INFERRED : boolean := not USE_ONEDEEP
and
(
( power_of_2(C_DEPTH)
and ( (W16 and C_DEPTH >= 16)
or (W32 and C_DEPTH >= 32)
)
)
or (not W32 and not W16)
);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
constant USE_STRUCTURAL_A : boolean := not USE_INFERRED and not USE_ONEDEEP;
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component SRLC16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
Q15 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component SRLC32E
generic
(
INIT : bit_vector := X"00000000"
);
port
(
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
begin
---(
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A = true generate
type bo2na_type is array(boolean) of natural;
constant bo2na : bo2na_type := (false => 0, true => 1);
constant BPSRL : natural := bo2na(W16)*16 + bo2na(W32)*32; -- Bits per SRL
constant BTASRL : natural := clog2(BPSRL); -- Bits To Address SRL
constant NUM_SRLS_DEEP : natural := (C_DEPTH + BPSRL-1)/BPSRL;
constant ADDR_BITS : integer := Addr'length;
signal dynshreg_addr : std_logic_vector(ADDR_BITS-1 downto 0);
signal cascade_sigs : std_logic_vector(0 to C_DWIDTH*(NUM_SRLS_DEEP+1) - 1);
-- The data signals at the inputs and daisy-chain outputs of SRLs.
-- The last signal of each cascade is not used.
--
signal q_sigs : std_logic_vector(0 to C_DWIDTH*NUM_SRLS_DEEP - 1);
-- The data signals at the addressble outputs of SRLs.
---)(
begin
DIN_TO_CASCADE_GEN : for i in 0 to C_DWIDTH-1 generate
cascade_sigs(i*(NUM_SRLS_DEEP+1)) <= Din(i);
end generate;
dynshreg_addr(ADDR_BITS-1 downto 0) <= Addr(0 to ADDR_BITS-1);
BIT_OF_WIDTH_GEN : for i in 0 to C_DWIDTH-1 generate
CASCADES_GEN : for j in 0 to NUM_SRLS_DEEP-1 generate
signal srl_addr: std_logic_vector(4 downto 0);
begin
-- Here we form the address for the SRL elements. This is just
-- the corresponding low-order bits of dynshreg_addr but we
-- also handle the case where we have to zero-pad to the left
-- a dynshreg_addr that is smaller than the SRL address port.
SRL_ADDR_LO_GEN : for i in 0 to min(ADDR_BITS-1,4) generate
srl_addr(i) <= dynshreg_addr(i);
end generate;
SRL_ADDR_HI_GEN : for i in min(ADDR_BITS-1,4)+1 to 4 generate
srl_addr(i) <= '0';
end generate;
W16_GEN : if W16 generate
SRLC16E_I : component SRLC16E
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q15 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A0 => srl_addr(0),
A1 => srl_addr(1),
A2 => srl_addr(2),
A3 => srl_addr(3),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
W32_GEN : if W32 generate
begin
SRLC32E_I : component SRLC32E
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q31 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A => srl_addr(4 downto 0),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
end generate CASCADES_GEN;
end generate BIT_OF_WIDTH_GEN;
----------------------------------------------------------------------------
-- Generate a MUXFn structure to select the proper SRL
-- as the output of each shift register.
----------------------------------------------------------------------------
SINGLE_SRL_GEN : if NUM_SRLS_DEEP = 1 generate
Dout <= q_sigs;
end generate;
--
MULTI_SRL_GEN : if NUM_SRLS_DEEP > 1 generate
PER_BIT_GEN : for i in 0 to C_DWIDTH-1 generate
begin
MUXF_STRUCT_I0 : entity proc_common_v3_00_a.muxf_struct_f
generic map (
C_START_LEVEL => native_lut_size(fam => K_FAMILY,
no_lut_return_val => 10000),
-- Artificially high value for C_START_LEVEL when no LUT is
-- supported will cause muxf_struct_f to default to inferred
-- multiplexers.
C_NUM_INPUTS => NUM_SRLS_DEEP,
C_FAMILY => C_FAMILY
)
port map (
O => Dout(i),
Iv => q_sigs(i * (NUM_SRLS_DEEP) to
(i+1) * (NUM_SRLS_DEEP) - 1),
Sel => dynshreg_addr(ADDR_BITS-1 downto BTASRL)
--Bits To Addr SRL
)
;
end generate;
end generate;
end generate STRUCTURAL_A_GEN;
---)
---(
INFERRED_GEN : if USE_INFERRED = true generate
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
signal data: dataType;
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
---(
INFERRED_ONEDEEP : if USE_ONEDEEP = true generate
signal data: std_logic_vector (0 to C_DWIDTH-1);
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din;
end if;
end if;
end process;
Dout <= data;
end generate INFERRED_ONEDEEP;
---)
end behavioral;
---)
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ic+e2vwK5Q7PgjSgvwMH2WoojQ4BbTVuQzxkOMVjPI/VZ5NZbfo+pDZV2xAqhpQmyQ9GvI+HXb1j
HmlK88vB0Q==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
EhYQ5ehP63YE16bz7Bs+Jp6XRtGGK+uBxpAwDXHwR28I2BtSgb9ncXucOpIeu0UTEMLqbvoLfbxU
MKaMrYPMo8RM/a2HDSBr9m9kqrCswhqrsj7+l6YpDAYmcCTq9T3FOkfhQRKFn0OQ/XIIbTvvITnM
Im9Df+3DnhnBsRIa6b8=
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
h0YJz7QAV8KNys9f0Mxlf+pNNU8LPo3hH7TmUMyrhw3lSO+kM5IGhIhrK6tA/vHS9HjpGQeWP4CV
hUv0PJuDbFRDQozJGwYt7sEJSKD17mUe+oi8D93Qmbv3URq5Gi+VGUtURDK7m9vfm75L8tyy5ql9
qECsNvUIWukIEumtJEY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pP+6eQFqDiaeKP3BC0Vnjvzv+UaX8yu0QFcUAsHG6nA3D6UEozm0SxdJ2iFfFcGPTkGK1rJp3wQa
XKLNY1k0r+8h6/HdEgYrEoLQxiu0rGTrMwFGkm5IpBA5qyUQJ9BOMA3RodmPZroFnpuOiQG9fXXi
E9pTQFAqbQwJUIKn68iPFrjVm+q4qLqQgrHvjKnf6JEciMX/HO234NTOg6COPSv7Uyo3FXOOpRHp
TCTyJBrP+6/0PD1dPLxzogieQ1fECqhCHlBWg5ARc7Wy8Nrvyugiw7tyWe9OCXkF34mphNHjHAfM
kre/l/mYmZh4jzXcx586HHX8Gny5RYaZ4KoAiA==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
DtRivEEQldRL8LC1umq+yZAExH6mDpzyWG1k5T3n0AafinwOAShYDeN3xJBVTROrx8yaZtcjOIVo
RTz2YCioii4y47KGQkU7qOYGP1IL16aZBaLHN0ikiASZGuT2wIZ7vBOHDkXuyg7SHEzSut20MVdH
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SpXZOqr7kFUwCnN2dJO5bhUtoF+y3GgfGerZaQ==
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pemFOX3XLyQdy4vtMYjiFXTZP+XlsBGKuE92WyWU4tr/zi/kdVNH1ODTNxNJ5DXwFjsQE3XaQKcO
QVG3dkRqyxkufPvrynU460117JgXGW15a8rem6Dsd8qn7VgNRECRRwFEFLE3bFhFjG5aqlEDnd56
Jtv/dX2cI0okyfMCEOBuMBd48KhjQsDycf7KtJc5LpL06fv+nYIvBQGKfMIkl6F4N9MkpkCF18HN
sm252Xem8SRCkTNQW6+o1yOVN45d9b+5a9+kx3Hc+5oEfCtymCxxbWIPnLnMAGhORy7lTFlrznDF
KTRSVyP9INWg2r5KEz1jo7u/eNIyiLfueJeDjg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5312)
`protect data_block
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pwKE7jI1z3e+v2BVU3pviQRu4Lz6ZpHq47DbmsjJdPNuAvCy1lXKhMAl5RUHAAHsTEnDAIcKmUIe
zpCTr6bjbDtmeEybza0diDN9DQV9/JCh0uLlsyyFtykb1pM9XZDildiNJTRP8zqycJ5uYSLDBF39
21yy/chK+5M/3/tLMfmc+tB0LMwnHYAPCoq4kodMpfuNoMhoUiBRch8eOQ+VzntKQ7Z9lOthUbnd
LmP/8OFkzFfeOTg44p0nQ4bYLfoPbMPrp9h4blR+tRklvt8gXwVxAET3VCDwre5pUCp9Y0skYyaJ
F5tjc+frCA5szZBHY1dIhrEAdMFCErWNZzrKRaEmlMjff4Zc52Kk7TdmaH2oX+E5CBLfAorgZrSt
UixYqC+TrDLFCih2Bq3/Ba4K+JqnfbE6C0fGdPfPkDFSanezeQf9vY3TLEEiDtwg8yL8qbZxFXo3
tW/ATQ1Miwn1NLtITQteDtpLohgBo/6S4oICSlW7KdZnruZR35QWSI5CoFlOBqO4yq+K2MADgpS/
8+qPal9KpNccavBukh3kf4bxXkoFp5zLRIlL4DIMlvCO+WW1SAUjdQt/a9agUrdkNSeA+DWgoOft
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GYyhN7/7GJe/oPM=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ic+e2vwK5Q7PgjSgvwMH2WoojQ4BbTVuQzxkOMVjPI/VZ5NZbfo+pDZV2xAqhpQmyQ9GvI+HXb1j
HmlK88vB0Q==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
EhYQ5ehP63YE16bz7Bs+Jp6XRtGGK+uBxpAwDXHwR28I2BtSgb9ncXucOpIeu0UTEMLqbvoLfbxU
MKaMrYPMo8RM/a2HDSBr9m9kqrCswhqrsj7+l6YpDAYmcCTq9T3FOkfhQRKFn0OQ/XIIbTvvITnM
Im9Df+3DnhnBsRIa6b8=
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
h0YJz7QAV8KNys9f0Mxlf+pNNU8LPo3hH7TmUMyrhw3lSO+kM5IGhIhrK6tA/vHS9HjpGQeWP4CV
hUv0PJuDbFRDQozJGwYt7sEJSKD17mUe+oi8D93Qmbv3URq5Gi+VGUtURDK7m9vfm75L8tyy5ql9
qECsNvUIWukIEumtJEY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pP+6eQFqDiaeKP3BC0Vnjvzv+UaX8yu0QFcUAsHG6nA3D6UEozm0SxdJ2iFfFcGPTkGK1rJp3wQa
XKLNY1k0r+8h6/HdEgYrEoLQxiu0rGTrMwFGkm5IpBA5qyUQJ9BOMA3RodmPZroFnpuOiQG9fXXi
E9pTQFAqbQwJUIKn68iPFrjVm+q4qLqQgrHvjKnf6JEciMX/HO234NTOg6COPSv7Uyo3FXOOpRHp
TCTyJBrP+6/0PD1dPLxzogieQ1fECqhCHlBWg5ARc7Wy8Nrvyugiw7tyWe9OCXkF34mphNHjHAfM
kre/l/mYmZh4jzXcx586HHX8Gny5RYaZ4KoAiA==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5312)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5312)
`protect data_block
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`protect end_protected
|
`protect begin_protected
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`protect begin_protected
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|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5312)
`protect data_block
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`protect end_protected
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:41:25 11/30/2015
-- Design Name:
-- Module Name: Tin_Counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.PKG_ROBOT_SUMO.all;
entity Tin_Counter is
port (
in_clk : in STD_LOGIC;
in_time_base : in STD_LOGIC;
in_pres_state : in ultrasonic_state_values;
out_measurement : out integer := 0);
end Tin_Counter;
architecture Behavioral of Tin_Counter is
signal Measurement: integer := 0; -- centimeters
signal tIN : integer range 0 to 20_000; -- should be 18500 but we are givin some room
begin
--Regla calcular distancia
-- x = tin * 300 / 18500
-- Generate a TimeBase of one second
-- measurement equations
Measurement <= (tIN * 300) / 18500;
out_measurement <= Measurement;
--process that count to obtain T_in
tIn_Counter: process(in_clk, in_time_base, tIN)
begin
if(rising_edge(in_clk) and in_time_base = '1') then
if(in_pres_state = WaitForResponse) then
tIN <= 0;
elsif (in_pres_state = UltrasonicResponse) then
tIN <= tIN + 1;
elsif (in_pres_state = WaitForNewStart) then
end if;
end if;
end process tIn_Counter;
end Behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_19.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_19 is
end entity fg_07_19;
architecture test of fg_07_19 is
constant Thold_d_clk : delay_length := 3 ns;
signal clk, d : bit := '0';
begin
-- code from book
hold_time_checker : process ( clk, d ) is
variable last_clk_edge_time : time := 0 fs;
begin
if clk'event and clk = '1' then
last_clk_edge_time := now;
end if;
if d'event then
assert now - last_clk_edge_time >= Thold_d_clk
report "hold time violation";
end if;
end process hold_time_checker;
-- end code from book
clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
stimulus : d <= '1' after 15 ns,
'0' after 53 ns,
'1' after 72 ns;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_19.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_19 is
end entity fg_07_19;
architecture test of fg_07_19 is
constant Thold_d_clk : delay_length := 3 ns;
signal clk, d : bit := '0';
begin
-- code from book
hold_time_checker : process ( clk, d ) is
variable last_clk_edge_time : time := 0 fs;
begin
if clk'event and clk = '1' then
last_clk_edge_time := now;
end if;
if d'event then
assert now - last_clk_edge_time >= Thold_d_clk
report "hold time violation";
end if;
end process hold_time_checker;
-- end code from book
clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
stimulus : d <= '1' after 15 ns,
'0' after 53 ns,
'1' after 72 ns;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_19.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_19 is
end entity fg_07_19;
architecture test of fg_07_19 is
constant Thold_d_clk : delay_length := 3 ns;
signal clk, d : bit := '0';
begin
-- code from book
hold_time_checker : process ( clk, d ) is
variable last_clk_edge_time : time := 0 fs;
begin
if clk'event and clk = '1' then
last_clk_edge_time := now;
end if;
if d'event then
assert now - last_clk_edge_time >= Thold_d_clk
report "hold time violation";
end if;
end process hold_time_checker;
-- end code from book
clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
stimulus : d <= '1' after 15 ns,
'0' after 53 ns,
'1' after 72 ns;
end architecture test;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1037.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s04b00x00p02n01i01037pkg is
type THREE is range 1 to 3;
type A1 is array (THREE) of BOOLEAN;
function Af1 (g : integer) return A1;
end c06s04b00x00p02n01i01037pkg;
package body c06s04b00x00p02n01i01037pkg is
function Af1 (g : integer) return A1 is
variable vaf1 : A1;
begin
return Vaf1;
end Af1;
end c06s04b00x00p02n01i01037pkg;
use work.c06s04b00x00p02n01i01037pkg.all;
ENTITY c06s04b00x00p02n01i01037ent IS
generic (g : integer := 2);
port (PT: BOOLEAN) ;
attribute AT1 : A1;
attribute AT1 of PT : signal is Af1(g) ;
END c06s04b00x00p02n01i01037ent;
ARCHITECTURE c06s04b00x00p02n01i01037arch OF c06s04b00x00p02n01i01037ent IS
BEGIN
TESTING: PROCESS
variable V: BOOLEAN;
BEGIN
V := PT'AT1(1);
assert NOT(V=false)
report "***PASSED TEST: c06s04b00x00p02n01i01037"
severity NOTE;
assert (V=false)
report "***FAILED TEST: c06s04b00x00p02n01i01037 - Indexed name be an attribute name test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p02n01i01037arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1037.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s04b00x00p02n01i01037pkg is
type THREE is range 1 to 3;
type A1 is array (THREE) of BOOLEAN;
function Af1 (g : integer) return A1;
end c06s04b00x00p02n01i01037pkg;
package body c06s04b00x00p02n01i01037pkg is
function Af1 (g : integer) return A1 is
variable vaf1 : A1;
begin
return Vaf1;
end Af1;
end c06s04b00x00p02n01i01037pkg;
use work.c06s04b00x00p02n01i01037pkg.all;
ENTITY c06s04b00x00p02n01i01037ent IS
generic (g : integer := 2);
port (PT: BOOLEAN) ;
attribute AT1 : A1;
attribute AT1 of PT : signal is Af1(g) ;
END c06s04b00x00p02n01i01037ent;
ARCHITECTURE c06s04b00x00p02n01i01037arch OF c06s04b00x00p02n01i01037ent IS
BEGIN
TESTING: PROCESS
variable V: BOOLEAN;
BEGIN
V := PT'AT1(1);
assert NOT(V=false)
report "***PASSED TEST: c06s04b00x00p02n01i01037"
severity NOTE;
assert (V=false)
report "***FAILED TEST: c06s04b00x00p02n01i01037 - Indexed name be an attribute name test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p02n01i01037arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1037.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s04b00x00p02n01i01037pkg is
type THREE is range 1 to 3;
type A1 is array (THREE) of BOOLEAN;
function Af1 (g : integer) return A1;
end c06s04b00x00p02n01i01037pkg;
package body c06s04b00x00p02n01i01037pkg is
function Af1 (g : integer) return A1 is
variable vaf1 : A1;
begin
return Vaf1;
end Af1;
end c06s04b00x00p02n01i01037pkg;
use work.c06s04b00x00p02n01i01037pkg.all;
ENTITY c06s04b00x00p02n01i01037ent IS
generic (g : integer := 2);
port (PT: BOOLEAN) ;
attribute AT1 : A1;
attribute AT1 of PT : signal is Af1(g) ;
END c06s04b00x00p02n01i01037ent;
ARCHITECTURE c06s04b00x00p02n01i01037arch OF c06s04b00x00p02n01i01037ent IS
BEGIN
TESTING: PROCESS
variable V: BOOLEAN;
BEGIN
V := PT'AT1(1);
assert NOT(V=false)
report "***PASSED TEST: c06s04b00x00p02n01i01037"
severity NOTE;
assert (V=false)
report "***FAILED TEST: c06s04b00x00p02n01i01037 - Indexed name be an attribute name test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p02n01i01037arch;
|
context c1 is
end context c1;
context c1 is
end context;
context c1 is
end;
|
-------------------------------------------------------------------------------
-- axi_datamover_rddata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rddata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_rddata_cntl.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
-- DET 6/20/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Added 512 and 1024 data width support
-- ^^^^^^
--
-- DET 9/1/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Fixed Lint reported excesive line length for lines 242 and 844.
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_rdmux;
-------------------------------------------------------------------------------
entity axi_datamover_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
-- Indicates if the DRE interface is used
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
-- Sets the width of the DRE Alignment controls
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Mux read data from a wider AXI4 Read
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------
-- Soft Shutdown internal interface -----------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
-----------------------------------------------------------------------
-- External Address Pipelining Contol support -------------------------
--
mm2s_rd_xfer_cmplt : out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single read data transfer on the AXI4 Read Data Channel. --
-- This signal escentially echos the assertion of rlast received --
-- from the AXI4. --
-----------------------------------------------------------------------
-- AXI Read Data Channel I/O ---------------------------------------------
--
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
--
mm2s_rresp : In std_logic_vector(1 downto 0); --
-- AXI Read response input --
--
mm2s_rlast : In std_logic; --
-- AXI Read LAST input --
--
mm2s_rvalid : In std_logic; --
-- AXI Read VALID input --
--
mm2s_rready : Out std_logic; --
-- AXI Read data READY output --
--------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
mm2s_dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
mm2s_dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
mm2s_dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- AXI Master Stream Channel------------------------------------------------------
--
mm2s_strm_wvalid : Out std_logic; --
-- AXI Stream VALID Output --
--
mm2s_strm_wready : In Std_logic; --
-- AXI Stream READY input --
--
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
mm2s_strm_wlast : Out std_logic; --
-- AXI Stream LAST output --
---------------------------------------------------------------------------------
-- MM2S Store and Forward Supplimental Control --------------------------------
-- This output is time aligned and qualified with the AXI Master Stream Channel--
--
mm2s_data2sf_cmd_cmplt : out std_logic; --
--
---------------------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address Channel --
--
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
---------------------------------------------------------------------------------
-- Address Controller Interface -------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
---------------------------------------------------------------------------------
-- Data Controller General Halted Status ----------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
---------------------------------------------------------------------------------
-- Output Stream Skid Buffer Halt control ---------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
---------------------------------------------------------------------------------
-- Read Status Controller Interface ------------------------------------------------
--
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The propagated command tag from the Command Calculator --
--
data2rsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a propagated calculation error from the Command Calculator --
--
data2rsc_okay : Out std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : in std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : Out std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
--
rsc2mstr_halt_pipe : In std_logic --
-- Status Flag indicating the Status Controller needs to stall the command --
-- execution pipe due to a Status flow issue or internal error. Generally --
-- this will occur if the Status FIFO is not being serviced fast enough to --
-- keep ahead of the command execution. --
------------------------------------------------------------------------------------
);
end entity axi_datamover_rddata_cntl;
architecture implementation of axi_datamover_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
mm2s_rready <= sig_data2mmap_ready;
sig_mmap2data_valid <= mm2s_rvalid ;
sig_mmap2data_last <= mm2s_rlast ;
-- Read Status Block interface
data2rsc_valid <= sig_coelsc_reg_full ;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
data2rsc_cmd_cmplt <= sig_coelsc_cmd_cmplt_reg ;
-- AXI MM2S Stream Channel Port assignments
mm2s_strm_wvalid <= (mm2s_rvalid and
sig_advance_pipe) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error
mm2s_strm_wlast <= (mm2s_rlast and
sig_next_eof_reg) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error;
GEN_MM2S_TKEEP_ENABLE5 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- Generate the Write Strobes for the Stream interface
mm2s_strm_wstrb <= (others => '1')
When (sig_halt_reg = '1') -- Force tstrb high on a Halt
else sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
end generate GEN_MM2S_TKEEP_ENABLE5;
GEN_MM2S_TKEEP_DISABLE5 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- Generate the Write Strobes for the Stream interface
mm2s_strm_wstrb <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE5;
-- MM2S Supplimental Controls
mm2s_data2sf_cmd_cmplt <= (mm2s_rlast and
sig_next_cmd_cmplt_reg) or
(sig_halt_reg and
sig_dqual_reg_full and
not(sig_no_posted_cmds) and
not(sig_calc_error_reg));
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Read Transfer Completed Status output
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
-- Internal logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RD_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a read data
-- transfer has completed. This is an echo of a rlast assertion
-- and a qualified data beat on the AXI4 Read Data Channel
-- inputs.
--
-------------------------------------------------------------
IMP_RD_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_rd_xfer_cmplt <= '0';
else
sig_rd_xfer_cmplt <= sig_mmap2data_last and
sig_good_mmap_dbeat;
end if;
end if;
end process IMP_RD_CMPLT_FLAG;
-- General flag for advancing the MMap Read and the Stream
-- data pipelines
sig_advance_pipe <= sig_addr_chan_rdy and
sig_dqual_rdy and
not(sig_coelsc_reg_full) and -- new status back-pressure term
not(sig_calc_error_reg);
-- test for Kevin's status throttle case
sig_data2mmap_ready <= (mm2s_strm_wready or
sig_halt_reg) and -- Ignore the Stream ready on a Halt request
sig_advance_pipe;
sig_good_mmap_dbeat <= sig_data2mmap_ready and
sig_mmap2data_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_mmap2data_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
------------------------------------------------------------
-- Instance: I_READ_MUX
--
-- Description:
-- Instance of the MM2S Read Data Channel Read Mux
--
------------------------------------------------------------
I_READ_MUX : entity axi_datamover_v5_1.axi_datamover_rdmux
generic map (
C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH ,
C_MMAP_DWIDTH => C_MMAP_DWIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH
)
port map (
mmap_read_data_in => mm2s_rdata ,
mux_data_out => mm2s_strm_wdata ,
mstr2data_saddr_lsb => sig_addr_lsb_reg
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an incoming read data channel
-- has been received. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
mstr2data_dre_src_align &
mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_SRC_STRT_INDEX);
sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_DEST_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
-- Flag indicating that there are no posted commands to AXI
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0';
sig_next_cmd_cmplt_reg <= '0';
sig_next_sequential_reg <= '0';
sig_next_calc_error_reg <= '0';
sig_next_dre_src_align_reg <= (others => '0');
sig_next_dre_dest_align_reg <= (others => '0');
sig_dqual_reg_empty <= '1';
sig_dqual_reg_full <= '0';
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Read Data Mux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1' and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
----- Address posted Counter logic --------------------------------
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a register for the Address
-- Posted FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detirmination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
else
null; -- hols current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds and
(sig_calc_error_reg or
rst2data_stop_request);
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
--
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------ Read Response Status Logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: LD_NEW_CMD_PULSE
--
-- Process Description:
-- Generate a 1 Clock wide pulse when a new command has been
-- loaded into the Command Register
--
-------------------------------------------------------------
LD_NEW_CMD_PULSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_ld_new_cmd_reg <= '1';
else
null; -- hold State
end if;
end if;
end process LD_NEW_CMD_PULSE;
sig_pop_coelsc_reg <= sig_coelsc_reg_full and
sig_rsc2data_ready ;
sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
not(sig_coelsc_reg_full)) or
(sig_ld_new_cmd_reg and
sig_calc_error_reg) ;
sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
sig_calc_error_reg;
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When mm2s_rresp = DECERR
Else '0';
sig_slverr <= '1'
When mm2s_rresp = SLVERR
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: RD_RESP_COELESC_REG
--
-- Process Description:
-- Implement the Read error/status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status Controller.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_cmd_cmplt_reg <= '0';
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_interr_reg <= sig_calc_error_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr or
sig_calc_error_reg );
sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DRE
--
-- If Generate Description:
-- Ties off DRE Control signals to logic low when DRE is
-- omitted from the MM2S functionality.
--
--
------------------------------------------------------------
GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
begin
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
end generate GEN_NO_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE_CNTLS
--
-- If Generate Description:
-- Implements the DRE Control logic when MM2S DRE is enabled.
--
-- - The DRE needs to have forced alignment at a SOF assertion
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
-- local signals
signal lsig_s_h_dre_autodest : std_logic := '0';
signal lsig_s_h_dre_new_align : std_logic := '0';
begin
mm2s_dre_new_align <= lsig_s_h_dre_new_align;
-- Autodest is asserted on a new parent command and the
-- previous parent command was not delimited with a EOF
mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
-- Assign the DRE Source and Destination Alignments
-- Only used when mm2s_dre_new_align is asserted
mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
-- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- asserted and the next transfer is not sequential and not the last
-- transfer of a packet.
mm2s_dre_flush <= mm2s_rlast and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_NEW_ALIGN
--
-- Process Description:
-- Generates the new alignment command flag to the DRE.
--
-------------------------------------------------------------
IMP_S_H_NEW_ALIGN : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_new_align <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_new_align <= '1';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_new_align <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_NEW_ALIGN;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_AUTODEST
--
-- Process Description:
-- Generates the control for the DRE indicating whether the
-- DRE destination alignment should be derived from the write
-- strobe stat of the last completed data-beat to the AXI
-- stream output.
--
-------------------------------------------------------------
IMP_S_H_AUTODEST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_autodest <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_autodest <= '0';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (lsig_s_h_dre_new_align = '1' and
sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_autodest <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_AUTODEST;
end generate GEN_INCLUDE_DRE_CNTLS;
------- Soft Shutdown Logic -------------------------------
-- Assign the output port skid buf control
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the output
-- stream skid buffer to shut down its outputs
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1302.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p06n01i01302ent IS
END c08s04b00x00p06n01i01302ent;
ARCHITECTURE c08s04b00x00p06n01i01302arch OF c08s04b00x00p06n01i01302ent IS
signal X : integer := 5;
BEGIN
TESTING: PROCESS
BEGIN
ch0804_par00601_09_arch <= X;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p06n01i01302 - the name of a body declaration can not appear on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p06n01i01302arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1302.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p06n01i01302ent IS
END c08s04b00x00p06n01i01302ent;
ARCHITECTURE c08s04b00x00p06n01i01302arch OF c08s04b00x00p06n01i01302ent IS
signal X : integer := 5;
BEGIN
TESTING: PROCESS
BEGIN
ch0804_par00601_09_arch <= X;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p06n01i01302 - the name of a body declaration can not appear on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p06n01i01302arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1302.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p06n01i01302ent IS
END c08s04b00x00p06n01i01302ent;
ARCHITECTURE c08s04b00x00p06n01i01302arch OF c08s04b00x00p06n01i01302ent IS
signal X : integer := 5;
BEGIN
TESTING: PROCESS
BEGIN
ch0804_par00601_09_arch <= X;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p06n01i01302 - the name of a body declaration can not appear on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p06n01i01302arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1333.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n03i01333ent IS
END c08s04b01x00p04n03i01333ent;
ARCHITECTURE c08s04b01x00p04n03i01333arch OF c08s04b01x00p04n03i01333ent IS
signal S : Bit;
BEGIN
TESTING: PROCESS
constant t1 : time := 10 ns;
constant t2 : time := 100 ns;
BEGIN
S <= '0' after (t1 - t2);
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b01x00p04n03i01333 - Time expression must be positive"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n03i01333arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1333.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n03i01333ent IS
END c08s04b01x00p04n03i01333ent;
ARCHITECTURE c08s04b01x00p04n03i01333arch OF c08s04b01x00p04n03i01333ent IS
signal S : Bit;
BEGIN
TESTING: PROCESS
constant t1 : time := 10 ns;
constant t2 : time := 100 ns;
BEGIN
S <= '0' after (t1 - t2);
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b01x00p04n03i01333 - Time expression must be positive"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n03i01333arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1333.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n03i01333ent IS
END c08s04b01x00p04n03i01333ent;
ARCHITECTURE c08s04b01x00p04n03i01333arch OF c08s04b01x00p04n03i01333ent IS
signal S : Bit;
BEGIN
TESTING: PROCESS
constant t1 : time := 10 ns;
constant t2 : time := 100 ns;
BEGIN
S <= '0' after (t1 - t2);
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b01x00p04n03i01333 - Time expression must be positive"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n03i01333arch;
|
-- ======================================================================
-- DES encryption/decryption
-- package file with functions
-- Copyright (C) 2007 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
-- Revision 1.0 2007/02/04
-- Initial release
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
PACKAGE des_pkg IS
FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector;
FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector;
FUNCTION s1 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
FUNCTION s2 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
FUNCTION s3 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
FUNCTION s4 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
FUNCTION s5 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
FUNCTION s6 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
FUNCTION s7 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
FUNCTION s8 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector;
FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector;
TYPE ip_matrix IS ARRAY (0 TO 63) OF natural RANGE 0 TO 63;
constant ip_table : ip_matrix := (57, 49, 41, 33, 25, 17, 9, 1,
59, 51, 43, 35, 27, 19, 11, 3,
61, 53, 45, 37, 29, 21, 13, 5,
63, 55, 47, 39, 31, 23, 15, 7,
56, 48, 40, 32, 24, 16, 8, 0,
58, 50, 42, 34, 26, 18, 10, 2,
60, 52, 44, 36, 28, 20, 12, 4,
62, 54, 46, 38, 30, 22, 14, 6);
constant ipn_table : ip_matrix := (39, 7, 47, 15, 55, 23, 63, 31,
38, 6, 46, 14, 54, 22, 62, 30,
37, 5, 45, 13, 53, 21, 61, 29,
36, 4, 44, 12, 52, 20, 60, 28,
35, 3, 43, 11, 51, 19, 59, 27,
34, 2, 42, 10, 50, 18, 58, 26,
33, 1, 41, 9, 49, 17, 57, 25,
32, 0, 40, 8, 48, 16, 56, 24);
TYPE e_matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 31;
constant e_table : e_matrix := (31, 0, 1, 2, 3, 4,
3, 4, 5, 6, 7, 8,
7, 8, 9, 10, 11, 12,
11, 12, 13, 14, 15, 16,
15, 16, 17, 18, 19, 20,
19, 20, 21, 22, 23, 24,
23, 24, 25, 26, 27, 28,
27, 28, 29, 30, 31, 0);
TYPE s_matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15;
constant s1_table : s_matrix := (0 => (14, 4, 13, 1, 2, 15, 11, 8, 3, 10, 6, 12, 5, 9, 0, 7),
1 => ( 0, 15, 7, 4, 14, 2, 13, 1, 10, 6, 12, 11, 9, 5, 3, 8),
2 => ( 4, 1, 14, 8, 13, 6, 2, 11, 15, 12, 9, 7, 3, 10, 5, 0),
3 => (15, 12, 8, 2, 4, 9, 1, 7, 5, 11, 3, 14, 10, 0, 6, 13));
constant s2_table : s_matrix := (0 => (15, 1, 8, 14, 6, 11, 3, 4, 9, 7, 2, 13, 12, 0, 5, 10),
1 => ( 3, 13, 4, 7, 15, 2, 8, 14, 12, 0, 1, 10, 6, 9, 11, 5),
2 => ( 0, 14, 7, 11, 10, 4, 13, 1, 5, 8, 12, 6, 9, 3, 2, 15),
3 => (13, 8, 10, 1, 3, 15, 4, 2, 11, 6, 7, 12, 0, 5, 14, 9));
constant s3_table : s_matrix := (0 => (10, 0, 9, 14, 6, 3, 15, 5, 1, 13, 12, 7, 11, 4, 2, 8),
1 => (13, 7, 0, 9, 3, 4, 6, 10, 2, 8, 5, 14, 12, 11, 15, 1),
2 => (13, 6, 4, 9, 8, 15, 3, 0, 11, 1, 2, 12, 5, 10, 14, 7),
3 => ( 1, 10, 13, 0, 6, 9, 8, 7, 4, 15, 14, 3, 11, 5, 2, 12));
constant s4_table : s_matrix := (0 => ( 7, 13, 14, 3, 0, 6, 9, 10, 1, 2, 8, 5, 11, 12, 4, 15),
1 => (13, 8, 11, 5, 6, 15, 0, 3, 4, 7, 2, 12, 1, 10, 14, 9),
2 => (10, 6, 9, 0, 12, 11, 7, 13, 15, 1, 3, 14, 5, 2, 8, 4),
3 => ( 3, 15, 0, 6, 10, 1, 13, 8, 9, 4, 5, 11, 12, 7, 2, 14));
constant s5_table : s_matrix := (0 => ( 2, 12, 4, 1, 7, 10, 11, 6, 8, 5, 3, 15, 13, 0, 14, 9),
1 => (14, 11, 2, 12, 4, 7, 13, 1, 5, 0, 15, 10, 3, 9, 8, 6),
2 => ( 4, 2, 1, 11, 10, 13, 7, 8, 15, 9, 12, 5, 6, 3, 0, 14),
3 => (11, 8, 12, 7, 1, 14, 2, 13, 6, 15, 0, 9, 10, 4, 5, 3));
constant s6_table : s_matrix := (0 => (12, 1, 10, 15, 9, 2, 6, 8, 0, 13, 3, 4, 14, 7, 5, 11),
1 => (10, 15, 4, 2, 7, 12, 9, 5, 6, 1, 13, 14, 0, 11, 3, 8),
2 => ( 9, 14, 15, 5, 2, 8, 12, 3, 7, 0, 4, 10, 1, 13, 11, 6),
3 => ( 4, 3, 2, 12, 9, 5, 15, 10, 11, 14, 1, 7, 6, 0, 8, 13));
constant s7_table : s_matrix := (0 => ( 4, 11, 2, 14, 15, 0, 8, 13, 3, 12, 9, 7, 5, 10, 6, 1),
1 => (13, 0, 11, 7, 4, 9, 1, 10, 14, 3, 5, 12, 2, 15, 8, 6),
2 => ( 1, 4, 11, 13, 12, 3, 7, 14, 10, 15, 6, 8, 0, 5, 9, 2),
3 => ( 6, 11, 13, 8, 1, 4, 10, 7, 9, 5, 0, 15, 14, 2, 3, 12));
constant s8_table : s_matrix := (0 => (13, 2, 8, 4, 6, 15, 11, 1, 10, 9, 3, 14, 5, 0, 12, 7),
1 => ( 1, 15, 13, 8, 10, 3, 7, 4, 12, 5, 6, 11, 0, 14, 9, 2),
2 => ( 7, 11, 4, 1, 9, 12, 14, 2, 0, 6, 10, 13, 15, 3, 5, 8),
3 => ( 2, 1, 14, 7, 4, 10, 8, 13, 15, 12, 9, 0, 3, 5, 6, 11));
type pc_matrix IS ARRAY (0 TO 27) OF natural RANGE 0 TO 63;
constant pc1c_table : pc_matrix := (56, 48, 40, 32, 24, 16, 8,
0, 57, 49, 41, 33, 25, 17,
9, 1, 58, 50, 42, 34, 26,
18, 10, 2, 59, 51, 43, 35);
constant pc1d_table : pc_matrix := (62, 54, 46, 38, 30, 22, 14,
6, 61, 53, 45, 37, 29, 21,
13, 5, 60, 52, 44, 36, 28,
20, 12, 4, 27, 19, 11, 3);
type p_matrix IS ARRAY (0 TO 31) OF natural RANGE 0 TO 31;
constant p_table : p_matrix := (15, 6, 19, 20,
28, 11, 27, 16,
0, 14, 22, 25,
4, 17, 30, 9,
1, 7, 23, 13,
31, 26, 2, 8,
18, 12, 29, 5,
21, 10, 3, 24);
type pc2_matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 63;
constant pc2_table : pc2_matrix := (13, 16, 10, 23, 0, 4,
2, 27, 14, 5, 20, 9,
22, 18, 11, 3, 25, 7,
15, 6, 26, 19, 12, 1,
40, 51, 30, 36, 46, 54,
29, 39, 50, 44, 32, 47,
43, 48, 38, 55, 33, 52,
45, 41, 49, 35, 28, 31);
END PACKAGE des_pkg;
PACKAGE BODY des_pkg IS
FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(0 TO 63);
BEGIN
FOR index IN 0 TO 63 LOOP
result( index ) := input_vector( ip_table( index ) );
END LOOP;
RETURN result;
END FUNCTION ip;
FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(0 TO 63);
BEGIN
FOR index IN 0 TO 63 LOOP
result( index ) := input_vector( ipn_table( index ) );
END LOOP;
RETURN result;
END FUNCTION ipn;
FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(0 TO 47);
BEGIN
FOR index IN 0 TO 47 LOOP
result( index ) := input_vector( e_table( index ) );
END LOOP;
RETURN result;
END FUNCTION e;
FUNCTION s1 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
VARIABLE int : std_logic_vector(0 TO 1);
VARIABLE i : integer RANGE 0 TO 3;
VARIABLE j : integer RANGE 0 TO 15;
VARIABLE result : std_logic_vector(0 TO 3);
BEGIN
int := input_vector( 0 ) & input_vector( 5 );
i := to_integer( unsigned( int ) );
j := to_integer( unsigned( input_vector( 1 TO 4) ) );
result := std_logic_vector( to_unsigned( s1_table( i, j ), 4 ) );
RETURN result;
END FUNCTION s1;
FUNCTION s2 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
VARIABLE int : std_logic_vector(0 TO 1);
VARIABLE i : integer RANGE 0 TO 3;
VARIABLE j : integer RANGE 0 TO 15;
VARIABLE result : std_logic_vector(0 TO 3);
BEGIN
int := input_vector( 0 ) & input_vector( 5 );
i := to_integer( unsigned( int ) );
j := to_integer( unsigned( input_vector( 1 TO 4) ) );
result := std_logic_vector( to_unsigned( s2_table( i, j ), 4 ) );
RETURN result;
END FUNCTION s2;
FUNCTION s3 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
VARIABLE int : std_logic_vector(0 TO 1);
VARIABLE i : integer RANGE 0 TO 3;
VARIABLE j : integer RANGE 0 TO 15;
VARIABLE result : std_logic_vector(0 TO 3);
BEGIN
int := input_vector( 0 ) & input_vector( 5 );
i := to_integer( unsigned( int ) );
j := to_integer( unsigned( input_vector( 1 TO 4) ) );
result := std_logic_vector( to_unsigned( s3_table( i, j ), 4 ) );
RETURN result;
END FUNCTION s3;
FUNCTION s4 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
VARIABLE int : std_logic_vector(0 TO 1);
VARIABLE i : integer RANGE 0 TO 3;
VARIABLE j : integer RANGE 0 TO 15;
VARIABLE result : std_logic_vector(0 TO 3);
BEGIN
int := input_vector( 0 ) & input_vector( 5 );
i := to_integer( unsigned( int ) );
j := to_integer( unsigned( input_vector( 1 TO 4) ) );
result := std_logic_vector( to_unsigned( s4_table( i, j ), 4 ) );
RETURN result;
END FUNCTION s4;
FUNCTION s5 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
VARIABLE int : std_logic_vector(0 TO 1);
VARIABLE i : integer RANGE 0 TO 3;
VARIABLE j : integer RANGE 0 TO 15;
VARIABLE result : std_logic_vector(0 TO 3);
BEGIN
int := input_vector( 0 ) & input_vector( 5 );
i := to_integer( unsigned( int ) );
j := to_integer( unsigned( input_vector( 1 TO 4) ) );
result := std_logic_vector( to_unsigned( s5_table( i, j ), 4 ) );
RETURN result;
END FUNCTION s5;
FUNCTION s6 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
VARIABLE int : std_logic_vector(0 TO 1);
VARIABLE i : integer RANGE 0 TO 3;
VARIABLE j : integer RANGE 0 TO 15;
VARIABLE result : std_logic_vector(0 TO 3);
BEGIN
int := input_vector( 0 ) & input_vector( 5 );
i := to_integer( unsigned( int ) );
j := to_integer( unsigned( input_vector( 1 TO 4) ) );
result := std_logic_vector( to_unsigned( s6_table( i, j ), 4 ) );
RETURN result;
END FUNCTION s6;
FUNCTION s7 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
VARIABLE int : std_logic_vector(0 TO 1);
VARIABLE i : integer RANGE 0 TO 3;
VARIABLE j : integer RANGE 0 TO 15;
VARIABLE result : std_logic_vector(0 TO 3);
BEGIN
int := input_vector( 0 ) & input_vector( 5 );
i := to_integer( unsigned( int ) );
j := to_integer( unsigned( input_vector( 1 TO 4) ) );
result := std_logic_vector( to_unsigned( s7_table( i, j ), 4 ) );
RETURN result;
END FUNCTION s7;
FUNCTION s8 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
VARIABLE int : std_logic_vector(0 TO 1);
VARIABLE i : integer RANGE 0 TO 3;
VARIABLE j : integer RANGE 0 TO 15;
VARIABLE result : std_logic_vector(0 TO 3);
BEGIN
int := input_vector( 0 ) & input_vector( 5 );
i := to_integer( unsigned( int ) );
j := to_integer( unsigned( input_vector( 1 TO 4) ) );
result := std_logic_vector( to_unsigned( s8_table( i, j ), 4 ) );
RETURN result;
END FUNCTION s8;
FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(0 TO 31);
BEGIN
FOR index IN 0 TO 31 LOOP
result( index ) := input_vector( p_table( index ) );
END LOOP;
RETURN result;
END FUNCTION p;
FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector IS
VARIABLE intern : std_logic_vector(0 TO 47);
VARIABLE result : std_logic_vector(0 TO 31);
BEGIN
intern := e( input_r ) xor input_key;
result := p( s1( intern(0 TO 5) ) & s2( intern(6 TO 11) ) & s3( intern(12 TO 17) ) & s4( intern(18 TO 23) ) &
s5( intern(24 TO 29) ) & s6( intern(30 TO 35) ) & s7( intern(36 TO 41) ) & s8( intern(42 TO 47) ) );
RETURN result;
END FUNCTION f;
FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(0 TO 27);
BEGIN
FOR index IN 0 TO 27 LOOP
result( index ) := input_vector( pc1c_table( index ) );
END LOOP;
RETURN result;
END FUNCTION pc1_c;
FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(0 TO 27);
BEGIN
FOR index IN 0 TO 27 LOOP
result( index ) := input_vector( pc1d_table( index ) );
END LOOP;
RETURN result;
END FUNCTION pc1_d;
FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(0 TO 47);
BEGIN
FOR index IN 0 TO 47 LOOP
result( index ) := input_vector( pc2_table( index ) );
END LOOP;
RETURN result;
END FUNCTION pc2;
END PACKAGE BODY des_pkg;
|
entity array3 is
end entity;
architecture test of array3 is
type matrix2x4 is array (1 to 2, 1 to 4) of integer;
signal m : matrix2x4;
begin
process is
begin
assert m(2, 2) = integer'left;
m(2, 2) <= 5;
wait for 1 ns;
assert m(2, 2) = 5;
m(2, 3) <= m(2, 2);
wait for 1 ns;
assert m(2, 3) = 5;
m <= ( (1, 2, 3, 4),
(5, 6, 7, 8) );
wait for 1 ns;
assert m(2, 4) = 8;
wait;
end process;
end architecture;
|
entity array3 is
end entity;
architecture test of array3 is
type matrix2x4 is array (1 to 2, 1 to 4) of integer;
signal m : matrix2x4;
begin
process is
begin
assert m(2, 2) = integer'left;
m(2, 2) <= 5;
wait for 1 ns;
assert m(2, 2) = 5;
m(2, 3) <= m(2, 2);
wait for 1 ns;
assert m(2, 3) = 5;
m <= ( (1, 2, 3, 4),
(5, 6, 7, 8) );
wait for 1 ns;
assert m(2, 4) = 8;
wait;
end process;
end architecture;
|
entity array3 is
end entity;
architecture test of array3 is
type matrix2x4 is array (1 to 2, 1 to 4) of integer;
signal m : matrix2x4;
begin
process is
begin
assert m(2, 2) = integer'left;
m(2, 2) <= 5;
wait for 1 ns;
assert m(2, 2) = 5;
m(2, 3) <= m(2, 2);
wait for 1 ns;
assert m(2, 3) = 5;
m <= ( (1, 2, 3, 4),
(5, 6, 7, 8) );
wait for 1 ns;
assert m(2, 4) = 8;
wait;
end process;
end architecture;
|
entity array3 is
end entity;
architecture test of array3 is
type matrix2x4 is array (1 to 2, 1 to 4) of integer;
signal m : matrix2x4;
begin
process is
begin
assert m(2, 2) = integer'left;
m(2, 2) <= 5;
wait for 1 ns;
assert m(2, 2) = 5;
m(2, 3) <= m(2, 2);
wait for 1 ns;
assert m(2, 3) = 5;
m <= ( (1, 2, 3, 4),
(5, 6, 7, 8) );
wait for 1 ns;
assert m(2, 4) = 8;
wait;
end process;
end architecture;
|
entity array3 is
end entity;
architecture test of array3 is
type matrix2x4 is array (1 to 2, 1 to 4) of integer;
signal m : matrix2x4;
begin
process is
begin
assert m(2, 2) = integer'left;
m(2, 2) <= 5;
wait for 1 ns;
assert m(2, 2) = 5;
m(2, 3) <= m(2, 2);
wait for 1 ns;
assert m(2, 3) = 5;
m <= ( (1, 2, 3, 4),
(5, 6, 7, 8) );
wait for 1 ns;
assert m(2, 4) = 8;
wait;
end process;
end architecture;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1_nov is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s1_nov;
architecture behaviour of s1_nov is
constant st0: std_logic_vector(4 downto 0) := "10110";
constant st1: std_logic_vector(4 downto 0) := "11010";
constant st2: std_logic_vector(4 downto 0) := "10101";
constant st3: std_logic_vector(4 downto 0) := "01010";
constant st4: std_logic_vector(4 downto 0) := "11001";
constant st5: std_logic_vector(4 downto 0) := "00110";
constant st6: std_logic_vector(4 downto 0) := "00011";
constant st7: std_logic_vector(4 downto 0) := "01110";
constant st8: std_logic_vector(4 downto 0) := "00000";
constant st9: std_logic_vector(4 downto 0) := "11111";
constant st10: std_logic_vector(4 downto 0) := "00100";
constant st11: std_logic_vector(4 downto 0) := "01001";
constant st12: std_logic_vector(4 downto 0) := "00001";
constant st13: std_logic_vector(4 downto 0) := "10001";
constant st14: std_logic_vector(4 downto 0) := "10010";
constant st15: std_logic_vector(4 downto 0) := "11100";
constant st16: std_logic_vector(4 downto 0) := "11110";
constant st17: std_logic_vector(4 downto 0) := "01101";
constant st18: std_logic_vector(4 downto 0) := "00010";
constant st19: std_logic_vector(4 downto 0) := "11101";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "------";
case current_state is
when st0 =>
if std_match(input, "-1-00---") then next_state <= st0; output <= "000001";
elsif std_match(input, "00--0---") then next_state <= st0; output <= "000001";
elsif std_match(input, "-0--1---") then next_state <= st1; output <= "000011";
elsif std_match(input, "-1-01---") then next_state <= st1; output <= "000011";
elsif std_match(input, "01-10---") then next_state <= st2; output <= "001001";
elsif std_match(input, "11-10---") then next_state <= st5; output <= "011001";
elsif std_match(input, "-1-11---") then next_state <= st3; output <= "001011";
elsif std_match(input, "10--0---") then next_state <= st4; output <= "010001";
end if;
when st1 =>
if std_match(input, "-0------") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-0----") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-1----") then next_state <= st7; output <= "001101";
end if;
when st2 =>
if std_match(input, "0---0---") then next_state <= st2; output <= "001001";
elsif std_match(input, "----1---") then next_state <= st3; output <= "001011";
elsif std_match(input, "1---0---") then next_state <= st5; output <= "011001";
end if;
when st3 =>
if std_match(input, "--------") then next_state <= st7; output <= "001101";
end if;
when st4 =>
if std_match(input, "--0-----") then next_state <= st12; output <= "100001";
elsif std_match(input, "--1-----") then next_state <= st13; output <= "101001";
end if;
when st5 =>
if std_match(input, "--------") then next_state <= st13; output <= "101001";
end if;
when st6 =>
if std_match(input, "-0--1---") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-01---") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-11---") then next_state <= st7; output <= "001101";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "011000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "010000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "001000";
end if;
when st7 =>
if std_match(input, "----1---") then next_state <= st7; output <= "001101";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "001000";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "011000";
end if;
when st8 =>
if std_match(input, "00--00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "00---1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-000--") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-0-1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "00--01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "-1-001-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "-0--11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "-1-011-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "10--01-1") then next_state <= st4; output <= "010001";
elsif std_match(input, "01-100--") then next_state <= st9; output <= "001000";
elsif std_match(input, "01-1-1--") then next_state <= st9; output <= "001000";
elsif std_match(input, "01-110--") then next_state <= st10; output <= "001010";
elsif std_match(input, "11-1----") then next_state <= st11; output <= "011000";
elsif std_match(input, "100-10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "-1-010--") then next_state <= st14; output <= "000010";
elsif std_match(input, "101-101-") then next_state <= st14; output <= "000010";
elsif std_match(input, "00--10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "10--00--") then next_state <= st15; output <= "010000";
elsif std_match(input, "10---1-0") then next_state <= st15; output <= "010000";
elsif std_match(input, "101-100-") then next_state <= st15; output <= "010000";
end if;
when st9 =>
if std_match(input, "0---00--") then next_state <= st9; output <= "001000";
elsif std_match(input, "0----1-0") then next_state <= st9; output <= "001000";
elsif std_match(input, "0---01-1") then next_state <= st2; output <= "001001";
elsif std_match(input, "0---10--") then next_state <= st10; output <= "001010";
elsif std_match(input, "0---11-1") then next_state <= st3; output <= "001011";
elsif std_match(input, "1----0--") then next_state <= st11; output <= "011000";
elsif std_match(input, "1----1-0") then next_state <= st11; output <= "011000";
elsif std_match(input, "1----1-1") then next_state <= st5; output <= "011001";
end if;
when st10 =>
if std_match(input, "------0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "------1-") then next_state <= st7; output <= "001101";
end if;
when st11 =>
if std_match(input, "-----1-1") then next_state <= st13; output <= "101001";
elsif std_match(input, "-----0--") then next_state <= st17; output <= "101000";
elsif std_match(input, "-----1-0") then next_state <= st17; output <= "101000";
end if;
when st12 =>
if std_match(input, "1-0-----") then next_state <= st12; output <= "100001";
elsif std_match(input, "1-1-----") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000011";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000001";
end if;
when st13 =>
if std_match(input, "1-------") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000011";
end if;
when st14 =>
if std_match(input, "---0--1-") then next_state <= st6; output <= "000101";
elsif std_match(input, "---0--0-") then next_state <= st18; output <= "000100";
elsif std_match(input, "-0-1----") then next_state <= st18; output <= "000100";
elsif std_match(input, "-1-1----") then next_state <= st16; output <= "001100";
end if;
when st15 =>
if std_match(input, "--0--0--") then next_state <= st19; output <= "100000";
elsif std_match(input, "--0--1-0") then next_state <= st19; output <= "100000";
elsif std_match(input, "--0--1-1") then next_state <= st12; output <= "100001";
elsif std_match(input, "--1-----") then next_state <= st17; output <= "101000";
end if;
when st16 =>
if std_match(input, "----1-0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "----1-1-") then next_state <= st7; output <= "001101";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "011000";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "001000";
end if;
when st17 =>
if std_match(input, "1----0--") then next_state <= st17; output <= "101000";
elsif std_match(input, "1----1-0") then next_state <= st17; output <= "101000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "1----1-1") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000010";
end if;
when st18 =>
if std_match(input, "----1-1-") then next_state <= st6; output <= "000101";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "001000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "011000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "010000";
elsif std_match(input, "-1-11-0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "-0--1-0-") then next_state <= st18; output <= "000100";
elsif std_match(input, "-1-01-0-") then next_state <= st18; output <= "000100";
end if;
when st19 =>
if std_match(input, "1-0--0--") then next_state <= st19; output <= "100000";
elsif std_match(input, "1-0--1-0") then next_state <= st19; output <= "100000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "1-0--1-1") then next_state <= st12; output <= "100001";
elsif std_match(input, "1-1-----") then next_state <= st17; output <= "101000";
end if;
when others => next_state <= "-----"; output <= "------";
end case;
end process;
end behaviour;
|
--------------------------------------------------------------------
-- Entity: SPI_OC
-- File: spi_oc.vhd
-- Author: Thomas Ameseder, Gleichmann Electronics
--
-- Description: VHDL wrapper for the Opencores SPI core with APB
-- interface
--------------------------------------------------------------------
-- CVS Entries:
-- $Date: 2006/12/04 14:44:05 $
-- $Author: tame $
-- $Log: spi_oc.vhd,v $
-- Revision 1.3 2006/12/04 14:44:05 tame
-- Changed interrupt output to LEON from a level (that is active until it is reset) to
-- a short pulse.
--
-- Revision 1.1 2006/11/17 12:28:56 tame
-- Added SPI files: Simple SPI package and a wrapper for the (modified)
-- OpenCores Simple SPI Core with APB interface.
--
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
library gleichmann;
use gleichmann.ocrcomp.all;
use gleichmann.sspi.all;
library opencores;
use opencores.occomp.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
entity spi_oc is
generic (
pindex : integer := 0; -- Leon-Index
paddr : integer := 0; -- Leon-Address
pmask : integer := 16#FFF#; -- Leon-Mask
pirq : integer := 0 -- Leon-IRQ
);
port (
rstn : in std_ulogic; -- global Reset, active low
clk : in std_ulogic; -- global Clock
apbi : in apb_slv_in_type; -- APB-Input
apbo : out apb_slv_out_type; -- APB-Output
spi_in : in spi_in_type; -- MultIO-Inputs
spi_out : out spi_out_type -- Spi-Outputs
);
end entity spi_oc;
architecture implementation of spi_oc is
constant data_width : integer := 8;
constant address_width : integer := 3;
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GLEICHMANN, GLEICHMANN_SPIOC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask)
);
signal irq : std_ulogic;
signal irq_1t : std_ulogic;
signal irq_adapt : std_ulogic; -- registered and converted to rising edge activity
begin
simple_spi_top_1 : simple_spi_top
port map (
prdata_o => apbo.prdata(data_width-1 downto 0),
pirq_o => irq,
sck_o => spi_out.sck,
mosi_o => spi_out.mosi,
ssn_o => spi_out.ssn,
pclk_i => clk,
prst_i => rstn,
psel_i => apbi.psel(pindex),
penable_i => apbi.penable,
paddr_i => apbi.paddr(address_width+1 downto 2), -- 32-bit addresses
pwrite_i => apbi.pwrite,
pwdata_i => apbi.pwdata(data_width-1 downto 0),
miso_i => spi_in.miso);
-- drive selected interrupt, remaining bits with zeroes
apbo.pirq(NAHBIRQ-1 downto pirq+1) <= (others => '0');
-- apbo.pirq(pirq) <= irq; -- corrected by MH, 28.11.2006
apbo.pirq(pirq) <= irq_adapt;
apbo.pirq(pirq-1 downto 0) <= (others => '0');
-- drive unused data bits with don't cares
apbo.prdata(31 downto data_width) <= (others => '0');
-- drive index for diagnostic use
apbo.pindex <= pindex;
-- drive slave configuration
apbo.pconfig <= pconfig;
---------------------------------------------------------------------------------------
-- Synchronous process to convert the high level interrupt from the core to
-- to an rising edge triggered interrupt to be suitable for the Leon IRQCTL
-- asynchronous low active reset like the open core simple SPI module !!!
---------------------------------------------------------------------------------------
irq_adaption: process (clk, rstn) -- added by MH, 28.11.2006
begin -- process irq_adaption)
if rstn = '0' then
irq_adapt <= '0';
irq_1t <= '0';
elsif clk'event and clk = '1' then
irq_1t <= irq;
irq_adapt <= irq and not irq_1t;
end if;
end process irq_adaption;
---------------------------------------------------------------------------------------
-- DEBUG SECTION
---------------------------------------------------------------------------------------
-- pragma translate_off
assert (pirq < 15 and pirq > 0 ) report
"Simple SPI Controller interrupt warning: " &
"0 does not exist, 15 is unmaskable, 16 to 31 are unused"
severity warning;
bootmsg : report_version
generic map ("SPI_OC: Simple SPI Controller rev " & tost(REVISION) &
", IRQ " & tost(pirq) &
", APB slave " & tost(pindex));
-- pragma translate_on
end architecture implementation;
|
--------------------------------------------------------------------
-- Entity: SPI_OC
-- File: spi_oc.vhd
-- Author: Thomas Ameseder, Gleichmann Electronics
--
-- Description: VHDL wrapper for the Opencores SPI core with APB
-- interface
--------------------------------------------------------------------
-- CVS Entries:
-- $Date: 2006/12/04 14:44:05 $
-- $Author: tame $
-- $Log: spi_oc.vhd,v $
-- Revision 1.3 2006/12/04 14:44:05 tame
-- Changed interrupt output to LEON from a level (that is active until it is reset) to
-- a short pulse.
--
-- Revision 1.1 2006/11/17 12:28:56 tame
-- Added SPI files: Simple SPI package and a wrapper for the (modified)
-- OpenCores Simple SPI Core with APB interface.
--
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
library gleichmann;
use gleichmann.ocrcomp.all;
use gleichmann.sspi.all;
library opencores;
use opencores.occomp.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
entity spi_oc is
generic (
pindex : integer := 0; -- Leon-Index
paddr : integer := 0; -- Leon-Address
pmask : integer := 16#FFF#; -- Leon-Mask
pirq : integer := 0 -- Leon-IRQ
);
port (
rstn : in std_ulogic; -- global Reset, active low
clk : in std_ulogic; -- global Clock
apbi : in apb_slv_in_type; -- APB-Input
apbo : out apb_slv_out_type; -- APB-Output
spi_in : in spi_in_type; -- MultIO-Inputs
spi_out : out spi_out_type -- Spi-Outputs
);
end entity spi_oc;
architecture implementation of spi_oc is
constant data_width : integer := 8;
constant address_width : integer := 3;
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GLEICHMANN, GLEICHMANN_SPIOC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask)
);
signal irq : std_ulogic;
signal irq_1t : std_ulogic;
signal irq_adapt : std_ulogic; -- registered and converted to rising edge activity
begin
simple_spi_top_1 : simple_spi_top
port map (
prdata_o => apbo.prdata(data_width-1 downto 0),
pirq_o => irq,
sck_o => spi_out.sck,
mosi_o => spi_out.mosi,
ssn_o => spi_out.ssn,
pclk_i => clk,
prst_i => rstn,
psel_i => apbi.psel(pindex),
penable_i => apbi.penable,
paddr_i => apbi.paddr(address_width+1 downto 2), -- 32-bit addresses
pwrite_i => apbi.pwrite,
pwdata_i => apbi.pwdata(data_width-1 downto 0),
miso_i => spi_in.miso);
-- drive selected interrupt, remaining bits with zeroes
apbo.pirq(NAHBIRQ-1 downto pirq+1) <= (others => '0');
-- apbo.pirq(pirq) <= irq; -- corrected by MH, 28.11.2006
apbo.pirq(pirq) <= irq_adapt;
apbo.pirq(pirq-1 downto 0) <= (others => '0');
-- drive unused data bits with don't cares
apbo.prdata(31 downto data_width) <= (others => '0');
-- drive index for diagnostic use
apbo.pindex <= pindex;
-- drive slave configuration
apbo.pconfig <= pconfig;
---------------------------------------------------------------------------------------
-- Synchronous process to convert the high level interrupt from the core to
-- to an rising edge triggered interrupt to be suitable for the Leon IRQCTL
-- asynchronous low active reset like the open core simple SPI module !!!
---------------------------------------------------------------------------------------
irq_adaption: process (clk, rstn) -- added by MH, 28.11.2006
begin -- process irq_adaption)
if rstn = '0' then
irq_adapt <= '0';
irq_1t <= '0';
elsif clk'event and clk = '1' then
irq_1t <= irq;
irq_adapt <= irq and not irq_1t;
end if;
end process irq_adaption;
---------------------------------------------------------------------------------------
-- DEBUG SECTION
---------------------------------------------------------------------------------------
-- pragma translate_off
assert (pirq < 15 and pirq > 0 ) report
"Simple SPI Controller interrupt warning: " &
"0 does not exist, 15 is unmaskable, 16 to 31 are unused"
severity warning;
bootmsg : report_version
generic map ("SPI_OC: Simple SPI Controller rev " & tost(REVISION) &
", IRQ " & tost(pirq) &
", APB slave " & tost(pindex));
-- pragma translate_on
end architecture implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ulpi_bus is
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- status
status : out std_logic_vector(7 downto 0);
-- register interface
reg_read : in std_logic;
reg_write : in std_logic;
reg_address : in std_logic_vector(5 downto 0);
reg_wdata : in std_logic_vector(7 downto 0);
reg_ack : out std_logic;
-- stream interface
tx_data : in std_logic_vector(7 downto 0);
tx_last : in std_logic;
tx_valid : in std_logic;
tx_start : in std_logic;
tx_next : out std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_register : out std_logic;
rx_last : out std_logic;
rx_valid : out std_logic;
rx_store : out std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of ulpi_bus : entity is "yes";
end ulpi_bus;
architecture gideon of ulpi_bus is
signal ulpi_data_out : std_logic_vector(7 downto 0);
signal ulpi_data_in : std_logic_vector(7 downto 0);
signal ulpi_dir_d1 : std_logic;
signal ulpi_dir_d2 : std_logic;
signal ulpi_dir_d3 : std_logic;
signal ulpi_nxt_d1 : std_logic;
signal ulpi_nxt_d2 : std_logic;
signal ulpi_nxt_d3 : std_logic;
signal reg_cmd_d2 : std_logic;
signal reg_cmd_d3 : std_logic;
signal reg_cmd_d4 : std_logic;
signal reg_cmd_d5 : std_logic;
signal rx_reg_i : std_logic;
signal tx_reg_i : std_logic;
signal rx_status_i : std_logic;
signal ulpi_stop : std_logic := '1';
signal ulpi_last : std_logic;
type t_state is ( idle, reading, writing, writing_data, transmit );
signal state : t_state;
attribute iob : string;
attribute iob of ulpi_data_in : signal is "true";
attribute iob of ulpi_dir_d1 : signal is "true";
attribute iob of ulpi_nxt_d1 : signal is "true";
attribute iob of ulpi_data_out : signal is "true";
attribute iob of ULPI_STP : signal is "true";
begin
-- Marking incoming data based on next/dir pattern
rx_data <= ulpi_data_in;
rx_store <= ulpi_dir_d1 and ulpi_dir_d2 and ulpi_nxt_d1;
rx_valid <= ulpi_dir_d1 and ulpi_dir_d2;
rx_last <= not ulpi_dir_d1 and ulpi_dir_d2;
rx_status_i <= ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_nxt_d1 and not rx_reg_i;
rx_reg_i <= (ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_dir_d3) and
(not ulpi_nxt_d1 and not ulpi_nxt_d2 and ulpi_nxt_d3) and
reg_cmd_d5;
rx_register <= rx_reg_i;
reg_ack <= rx_reg_i or tx_reg_i;
p_sample: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_data_in <= ULPI_DATA;
reg_cmd_d2 <= ulpi_data_in(7) and ulpi_data_in(6);
reg_cmd_d3 <= reg_cmd_d2;
reg_cmd_d4 <= reg_cmd_d3;
reg_cmd_d5 <= reg_cmd_d4;
ulpi_dir_d1 <= ULPI_DIR;
ulpi_dir_d2 <= ulpi_dir_d1;
ulpi_dir_d3 <= ulpi_dir_d2;
ulpi_nxt_d1 <= ULPI_NXT;
ulpi_nxt_d2 <= ulpi_nxt_d1;
ulpi_nxt_d3 <= ulpi_nxt_d2;
if rx_status_i='1' then
status <= ulpi_data_in;
end if;
if reset='1' then
status <= (others => '0');
end if;
end if;
end process;
p_tx_state: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_stop <= '0';
tx_reg_i <= '0';
case state is
when idle =>
ulpi_data_out <= X"00";
if reg_read='1' and rx_reg_i='0' then
ulpi_data_out <= "11" & reg_address;
state <= reading;
elsif reg_write='1' and tx_reg_i='0' then
ulpi_data_out <= "10" & reg_address;
state <= writing;
elsif tx_valid = '1' and tx_start = '1' and ULPI_DIR='0' then
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
state <= transmit;
end if;
when reading =>
if rx_reg_i='1' then
ulpi_data_out <= X"00";
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing =>
if ULPI_NXT='1' then
ulpi_data_out <= reg_wdata;
state <= writing_data;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing_data =>
if ULPI_NXT='1' and ULPI_DIR='0' then
tx_reg_i <= '1';
ulpi_stop <= '1';
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when transmit =>
if ULPI_NXT = '1' then
if ulpi_last='1' or tx_valid = '0' then
ulpi_data_out <= X"00";
ulpi_stop <= '1';
state <= idle;
else
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
ulpi_stop <= '0';
ulpi_last <= '0';
end if;
end if;
end process;
p_next: process(state, tx_valid, tx_start, rx_reg_i, tx_reg_i, ULPI_DIR, ULPI_NXT, ulpi_last, reg_read, reg_write)
begin
case state is
when idle =>
tx_next <= not ULPI_DIR and tx_valid and tx_start;
if reg_read='1' and rx_reg_i='0' then
tx_next <= '0';
end if;
if reg_write='1' and tx_reg_i='0' then
tx_next <= '0';
end if;
when transmit =>
tx_next <= ULPI_NXT and tx_valid and not ulpi_last;
when others =>
tx_next <= '0';
end case;
end process;
ULPI_STP <= ulpi_stop;
ULPI_DATA <= ulpi_data_out when ULPI_DIR='0' and ulpi_dir_d1='0' else (others => 'Z');
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ulpi_bus is
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- status
status : out std_logic_vector(7 downto 0);
-- register interface
reg_read : in std_logic;
reg_write : in std_logic;
reg_address : in std_logic_vector(5 downto 0);
reg_wdata : in std_logic_vector(7 downto 0);
reg_ack : out std_logic;
-- stream interface
tx_data : in std_logic_vector(7 downto 0);
tx_last : in std_logic;
tx_valid : in std_logic;
tx_start : in std_logic;
tx_next : out std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_register : out std_logic;
rx_last : out std_logic;
rx_valid : out std_logic;
rx_store : out std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of ulpi_bus : entity is "yes";
end ulpi_bus;
architecture gideon of ulpi_bus is
signal ulpi_data_out : std_logic_vector(7 downto 0);
signal ulpi_data_in : std_logic_vector(7 downto 0);
signal ulpi_dir_d1 : std_logic;
signal ulpi_dir_d2 : std_logic;
signal ulpi_dir_d3 : std_logic;
signal ulpi_nxt_d1 : std_logic;
signal ulpi_nxt_d2 : std_logic;
signal ulpi_nxt_d3 : std_logic;
signal reg_cmd_d2 : std_logic;
signal reg_cmd_d3 : std_logic;
signal reg_cmd_d4 : std_logic;
signal reg_cmd_d5 : std_logic;
signal rx_reg_i : std_logic;
signal tx_reg_i : std_logic;
signal rx_status_i : std_logic;
signal ulpi_stop : std_logic := '1';
signal ulpi_last : std_logic;
type t_state is ( idle, reading, writing, writing_data, transmit );
signal state : t_state;
attribute iob : string;
attribute iob of ulpi_data_in : signal is "true";
attribute iob of ulpi_dir_d1 : signal is "true";
attribute iob of ulpi_nxt_d1 : signal is "true";
attribute iob of ulpi_data_out : signal is "true";
attribute iob of ULPI_STP : signal is "true";
begin
-- Marking incoming data based on next/dir pattern
rx_data <= ulpi_data_in;
rx_store <= ulpi_dir_d1 and ulpi_dir_d2 and ulpi_nxt_d1;
rx_valid <= ulpi_dir_d1 and ulpi_dir_d2;
rx_last <= not ulpi_dir_d1 and ulpi_dir_d2;
rx_status_i <= ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_nxt_d1 and not rx_reg_i;
rx_reg_i <= (ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_dir_d3) and
(not ulpi_nxt_d1 and not ulpi_nxt_d2 and ulpi_nxt_d3) and
reg_cmd_d5;
rx_register <= rx_reg_i;
reg_ack <= rx_reg_i or tx_reg_i;
p_sample: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_data_in <= ULPI_DATA;
reg_cmd_d2 <= ulpi_data_in(7) and ulpi_data_in(6);
reg_cmd_d3 <= reg_cmd_d2;
reg_cmd_d4 <= reg_cmd_d3;
reg_cmd_d5 <= reg_cmd_d4;
ulpi_dir_d1 <= ULPI_DIR;
ulpi_dir_d2 <= ulpi_dir_d1;
ulpi_dir_d3 <= ulpi_dir_d2;
ulpi_nxt_d1 <= ULPI_NXT;
ulpi_nxt_d2 <= ulpi_nxt_d1;
ulpi_nxt_d3 <= ulpi_nxt_d2;
if rx_status_i='1' then
status <= ulpi_data_in;
end if;
if reset='1' then
status <= (others => '0');
end if;
end if;
end process;
p_tx_state: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_stop <= '0';
tx_reg_i <= '0';
case state is
when idle =>
ulpi_data_out <= X"00";
if reg_read='1' and rx_reg_i='0' then
ulpi_data_out <= "11" & reg_address;
state <= reading;
elsif reg_write='1' and tx_reg_i='0' then
ulpi_data_out <= "10" & reg_address;
state <= writing;
elsif tx_valid = '1' and tx_start = '1' and ULPI_DIR='0' then
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
state <= transmit;
end if;
when reading =>
if rx_reg_i='1' then
ulpi_data_out <= X"00";
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing =>
if ULPI_NXT='1' then
ulpi_data_out <= reg_wdata;
state <= writing_data;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing_data =>
if ULPI_NXT='1' and ULPI_DIR='0' then
tx_reg_i <= '1';
ulpi_stop <= '1';
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when transmit =>
if ULPI_NXT = '1' then
if ulpi_last='1' or tx_valid = '0' then
ulpi_data_out <= X"00";
ulpi_stop <= '1';
state <= idle;
else
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
ulpi_stop <= '0';
ulpi_last <= '0';
end if;
end if;
end process;
p_next: process(state, tx_valid, tx_start, rx_reg_i, tx_reg_i, ULPI_DIR, ULPI_NXT, ulpi_last, reg_read, reg_write)
begin
case state is
when idle =>
tx_next <= not ULPI_DIR and tx_valid and tx_start;
if reg_read='1' and rx_reg_i='0' then
tx_next <= '0';
end if;
if reg_write='1' and tx_reg_i='0' then
tx_next <= '0';
end if;
when transmit =>
tx_next <= ULPI_NXT and tx_valid and not ulpi_last;
when others =>
tx_next <= '0';
end case;
end process;
ULPI_STP <= ulpi_stop;
ULPI_DATA <= ulpi_data_out when ULPI_DIR='0' and ulpi_dir_d1='0' else (others => 'Z');
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ulpi_bus is
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- status
status : out std_logic_vector(7 downto 0);
-- register interface
reg_read : in std_logic;
reg_write : in std_logic;
reg_address : in std_logic_vector(5 downto 0);
reg_wdata : in std_logic_vector(7 downto 0);
reg_ack : out std_logic;
-- stream interface
tx_data : in std_logic_vector(7 downto 0);
tx_last : in std_logic;
tx_valid : in std_logic;
tx_start : in std_logic;
tx_next : out std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_register : out std_logic;
rx_last : out std_logic;
rx_valid : out std_logic;
rx_store : out std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of ulpi_bus : entity is "yes";
end ulpi_bus;
architecture gideon of ulpi_bus is
signal ulpi_data_out : std_logic_vector(7 downto 0);
signal ulpi_data_in : std_logic_vector(7 downto 0);
signal ulpi_dir_d1 : std_logic;
signal ulpi_dir_d2 : std_logic;
signal ulpi_dir_d3 : std_logic;
signal ulpi_nxt_d1 : std_logic;
signal ulpi_nxt_d2 : std_logic;
signal ulpi_nxt_d3 : std_logic;
signal reg_cmd_d2 : std_logic;
signal reg_cmd_d3 : std_logic;
signal reg_cmd_d4 : std_logic;
signal reg_cmd_d5 : std_logic;
signal rx_reg_i : std_logic;
signal tx_reg_i : std_logic;
signal rx_status_i : std_logic;
signal ulpi_stop : std_logic := '1';
signal ulpi_last : std_logic;
type t_state is ( idle, reading, writing, writing_data, transmit );
signal state : t_state;
attribute iob : string;
attribute iob of ulpi_data_in : signal is "true";
attribute iob of ulpi_dir_d1 : signal is "true";
attribute iob of ulpi_nxt_d1 : signal is "true";
attribute iob of ulpi_data_out : signal is "true";
attribute iob of ULPI_STP : signal is "true";
begin
-- Marking incoming data based on next/dir pattern
rx_data <= ulpi_data_in;
rx_store <= ulpi_dir_d1 and ulpi_dir_d2 and ulpi_nxt_d1;
rx_valid <= ulpi_dir_d1 and ulpi_dir_d2;
rx_last <= not ulpi_dir_d1 and ulpi_dir_d2;
rx_status_i <= ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_nxt_d1 and not rx_reg_i;
rx_reg_i <= (ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_dir_d3) and
(not ulpi_nxt_d1 and not ulpi_nxt_d2 and ulpi_nxt_d3) and
reg_cmd_d5;
rx_register <= rx_reg_i;
reg_ack <= rx_reg_i or tx_reg_i;
p_sample: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_data_in <= ULPI_DATA;
reg_cmd_d2 <= ulpi_data_in(7) and ulpi_data_in(6);
reg_cmd_d3 <= reg_cmd_d2;
reg_cmd_d4 <= reg_cmd_d3;
reg_cmd_d5 <= reg_cmd_d4;
ulpi_dir_d1 <= ULPI_DIR;
ulpi_dir_d2 <= ulpi_dir_d1;
ulpi_dir_d3 <= ulpi_dir_d2;
ulpi_nxt_d1 <= ULPI_NXT;
ulpi_nxt_d2 <= ulpi_nxt_d1;
ulpi_nxt_d3 <= ulpi_nxt_d2;
if rx_status_i='1' then
status <= ulpi_data_in;
end if;
if reset='1' then
status <= (others => '0');
end if;
end if;
end process;
p_tx_state: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_stop <= '0';
tx_reg_i <= '0';
case state is
when idle =>
ulpi_data_out <= X"00";
if reg_read='1' and rx_reg_i='0' then
ulpi_data_out <= "11" & reg_address;
state <= reading;
elsif reg_write='1' and tx_reg_i='0' then
ulpi_data_out <= "10" & reg_address;
state <= writing;
elsif tx_valid = '1' and tx_start = '1' and ULPI_DIR='0' then
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
state <= transmit;
end if;
when reading =>
if rx_reg_i='1' then
ulpi_data_out <= X"00";
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing =>
if ULPI_NXT='1' then
ulpi_data_out <= reg_wdata;
state <= writing_data;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing_data =>
if ULPI_NXT='1' and ULPI_DIR='0' then
tx_reg_i <= '1';
ulpi_stop <= '1';
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when transmit =>
if ULPI_NXT = '1' then
if ulpi_last='1' or tx_valid = '0' then
ulpi_data_out <= X"00";
ulpi_stop <= '1';
state <= idle;
else
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
ulpi_stop <= '0';
ulpi_last <= '0';
end if;
end if;
end process;
p_next: process(state, tx_valid, tx_start, rx_reg_i, tx_reg_i, ULPI_DIR, ULPI_NXT, ulpi_last, reg_read, reg_write)
begin
case state is
when idle =>
tx_next <= not ULPI_DIR and tx_valid and tx_start;
if reg_read='1' and rx_reg_i='0' then
tx_next <= '0';
end if;
if reg_write='1' and tx_reg_i='0' then
tx_next <= '0';
end if;
when transmit =>
tx_next <= ULPI_NXT and tx_valid and not ulpi_last;
when others =>
tx_next <= '0';
end case;
end process;
ULPI_STP <= ulpi_stop;
ULPI_DATA <= ulpi_data_out when ULPI_DIR='0' and ulpi_dir_d1='0' else (others => 'Z');
end gideon;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity downcounter is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
rst_val : in STD_LOGIC_VECTOR (15 downto 0);
trigger : out STD_LOGIC);
end downcounter;
architecture Behavioral of downcounter is
signal cnt : unsigned(22 downto 0);
begin
trigger <= '1' when cnt = 0 else '0';
process (clk, rst)
begin
if rst = '1' then
cnt <= unsigned(rst_val);
elsif rising_edge(clk) then
cnt <= cnt - 1;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
entity SramTestGen is
generic (
AddrW : positive;
DataW : positive);
port (
Clk : in bit1;
Rst_N : in bit1;
--
Btn0 : in bit1;
Btn1 : in bit1;
Btn2 : in bit1;
Btn3 : in bit1;
--
We : out bit1;
Re : out bit1;
Addr : out word(AddrW-1 downto 0);
Data : out word(DataW-1 downto 0)
);
end entity SramTestGen;
architecture rtl of SramTestGen is
constant StartCnt : positive := 25000000;
signal StartCnt_D, StartCnt_N : word(bits(StartCnt)-1 downto 0);
signal Data_D, Data_N : word(4-1 downto 0);
signal Addr_D, Addr_N : word(2-1 downto 0);
signal Btn_D : word(4-1 downto 0);
signal StrobeCnt_D, StrobeCnt_N : word(bits(StartCnt)-1 downto 0);
begin -- rtl
StimSync : process (Clk, Rst_N)
begin -- process Stim
if Rst_N = '0' then -- asynchronous reset (active low)
StartCnt_D <= conv_word(StartCnt, StartCnt_D'length);
Data_D <= (others => '0');
Addr_D <= (others => '0');
Btn_D <= (others => '1');
StrobeCnt_D <= conv_word(StartCnt, StrobeCnt_D'length);
elsif Clk'event and Clk = '1' then -- rising clock edge
StartCnt_D <= StartCnt_N;
Data_D <= Data_N;
Addr_D <= Addr_N;
Btn_D <= Btn3 & Btn2 & Btn1 & Btn0;
StrobeCnt_D <= StrobeCnt_N;
end if;
end process StimSync;
StimAsync : process (StartCnt_D, Data_D, Addr_D, StrobeCnt_D, Btn0, Btn1)
begin
StartCnt_N <= StartCnt_D;
StrobeCnt_N <= StrobeCnt_D - 1;
--
We <= '0';
Re <= '0';
Addr <= (others => '0');
Data <= (others => '0');
Data_N <= Data_D;
Addr_N <= Addr_D;
if StartCnt_D > 0 then
StartCnt_N <= StartCnt_D - 1;
end if;
-- Perform write
if StartCnt_D = 12 then
We <= '1';
Addr <= (others => '0');
Data <= xt0("1111", Data'length);
end if;
if StartCnt_D = 10 then
We <= '1';
Addr <= conv_word(1, Addr'length);
Data <= xt0("1110", Data'length);
end if;
if StartCnt_D = 8 then
We <= '1';
Addr <= conv_word(2, Addr'length);
Data <= xt0("1100", Data'length);
end if;
if StartCnt_D = 6 then
We <= '1';
Addr <= conv_word(3, Addr'length);
Data <= xt0("1000", Data'length);
end if;
-- Perform first read
if StartCnt_D = 1 then
Re <= '1';
Addr <= (others => '0');
end if;
if (StrobeCnt_D = 0) then
if (Btn0 = '0') then
Addr_N <= Addr_D + 1;
Re <= '1';
Addr <= xt0(Addr_D + 1, Addr'length);
end if;
if (Btn1 = '0') then
Addr_N <= Addr_D - 1;
Re <= '1';
Addr <= xt0(Addr_D - 1, Addr'length);
end if;
end if;
end process;
end rtl;
|
-- VHDL Entity R6502_TC.FSM_NMI.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:43:05 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity FSM_NMI is
port(
clk_clk_i : in std_logic;
fetch_i : in std_logic;
nmi_n_i : in std_logic;
rst_rst_n_i : in std_logic;
nmi_o : out std_logic
);
-- Declarations
end FSM_NMI ;
-- Jens-D. Gutschmidt Project: R6502_TC
-- [email protected]
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: not supported by cvs2svn $
-- <<-- more -->>
-- Title: FSM for NMI
-- Path: R6502_TC/FSM_NMI/fsm
-- Edited: by eda on 03 Jan 2009
--
-- VHDL Architecture R6502_TC.FSM_NMI.fsm
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:43:05 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture fsm of FSM_NMI is
type state_type is (
idle,
idle1,
idle2,
IMP
);
-- State vector declaration
attribute state_vector : string;
attribute state_vector of fsm : architecture is "current_state";
-- Declare current and next state signals
signal current_state : state_type;
signal next_state : state_type;
-- Declare any pre-registered internal signals
signal nmi_o_cld : std_logic ;
begin
-----------------------------------------------------------------
clocked_proc : process (
clk_clk_i,
rst_rst_n_i
)
-----------------------------------------------------------------
begin
if (rst_rst_n_i = '0') then
current_state <= idle;
-- Default Reset Values
nmi_o_cld <= '0';
elsif (clk_clk_i'event and clk_clk_i = '1') then
current_state <= next_state;
-- Default Assignment To Internals
nmi_o_cld <= '0';
-- Combined Actions
case current_state is
when IMP =>
nmi_o_cld <= '1';
when others =>
null;
end case;
end if;
end process clocked_proc;
-----------------------------------------------------------------
nextstate_proc : process (
current_state,
fetch_i,
nmi_n_i
)
-----------------------------------------------------------------
begin
case current_state is
-- <<< REQ1
when idle =>
if (nmi_n_i = '1') then
next_state <= idle1;
else
next_state <= idle;
end if;
when idle1 =>
if (nmi_n_i = '0') then
next_state <= idle2;
else
next_state <= idle1;
end if;
when idle2 =>
if (nmi_n_i = '0') then
next_state <= IMP;
else
next_state <= idle;
end if;
when IMP =>
if (fetch_i = '1') then
next_state <= idle;
else
next_state <= IMP;
end if;
when others =>
next_state <= idle;
end case;
end process nextstate_proc;
-- Concurrent Statements
-- Clocked output assignments
nmi_o <= nmi_o_cld;
end fsm;
|
-- VHDL Entity R6502_TC.FSM_NMI.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:43:05 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity FSM_NMI is
port(
clk_clk_i : in std_logic;
fetch_i : in std_logic;
nmi_n_i : in std_logic;
rst_rst_n_i : in std_logic;
nmi_o : out std_logic
);
-- Declarations
end FSM_NMI ;
-- Jens-D. Gutschmidt Project: R6502_TC
-- [email protected]
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: not supported by cvs2svn $
-- <<-- more -->>
-- Title: FSM for NMI
-- Path: R6502_TC/FSM_NMI/fsm
-- Edited: by eda on 03 Jan 2009
--
-- VHDL Architecture R6502_TC.FSM_NMI.fsm
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:43:05 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture fsm of FSM_NMI is
type state_type is (
idle,
idle1,
idle2,
IMP
);
-- State vector declaration
attribute state_vector : string;
attribute state_vector of fsm : architecture is "current_state";
-- Declare current and next state signals
signal current_state : state_type;
signal next_state : state_type;
-- Declare any pre-registered internal signals
signal nmi_o_cld : std_logic ;
begin
-----------------------------------------------------------------
clocked_proc : process (
clk_clk_i,
rst_rst_n_i
)
-----------------------------------------------------------------
begin
if (rst_rst_n_i = '0') then
current_state <= idle;
-- Default Reset Values
nmi_o_cld <= '0';
elsif (clk_clk_i'event and clk_clk_i = '1') then
current_state <= next_state;
-- Default Assignment To Internals
nmi_o_cld <= '0';
-- Combined Actions
case current_state is
when IMP =>
nmi_o_cld <= '1';
when others =>
null;
end case;
end if;
end process clocked_proc;
-----------------------------------------------------------------
nextstate_proc : process (
current_state,
fetch_i,
nmi_n_i
)
-----------------------------------------------------------------
begin
case current_state is
-- <<< REQ1
when idle =>
if (nmi_n_i = '1') then
next_state <= idle1;
else
next_state <= idle;
end if;
when idle1 =>
if (nmi_n_i = '0') then
next_state <= idle2;
else
next_state <= idle1;
end if;
when idle2 =>
if (nmi_n_i = '0') then
next_state <= IMP;
else
next_state <= idle;
end if;
when IMP =>
if (fetch_i = '1') then
next_state <= idle;
else
next_state <= IMP;
end if;
when others =>
next_state <= idle;
end case;
end process nextstate_proc;
-- Concurrent Statements
-- Clocked output assignments
nmi_o <= nmi_o_cld;
end fsm;
|
component usb_system is
port (
clk_clk : in std_logic := 'X'; -- clk
keycode_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_out_clk_clk : out std_logic; -- clk
sdram_wire_addr : out std_logic_vector(12 downto 0); -- addr
sdram_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_wire_cas_n : out std_logic; -- cas_n
sdram_wire_cke : out std_logic; -- cke
sdram_wire_cs_n : out std_logic; -- cs_n
sdram_wire_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- dq
sdram_wire_dqm : out std_logic_vector(3 downto 0); -- dqm
sdram_wire_ras_n : out std_logic; -- ras_n
sdram_wire_we_n : out std_logic; -- we_n
usb_DATA : inout std_logic_vector(15 downto 0) := (others => 'X'); -- DATA
usb_ADDR : out std_logic_vector(1 downto 0); -- ADDR
usb_RD_N : out std_logic; -- RD_N
usb_WR_N : out std_logic; -- WR_N
usb_CS_N : out std_logic; -- CS_N
usb_RST_N : out std_logic; -- RST_N
usb_INT : in std_logic := 'X'; -- INT
usb_out_clk_clk : out std_logic -- clk
);
end component usb_system;
u0 : component usb_system
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
keycode_export => CONNECTED_TO_keycode_export, -- keycode.export
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sdram_out_clk_clk => CONNECTED_TO_sdram_out_clk_clk, -- sdram_out_clk.clk
sdram_wire_addr => CONNECTED_TO_sdram_wire_addr, -- sdram_wire.addr
sdram_wire_ba => CONNECTED_TO_sdram_wire_ba, -- .ba
sdram_wire_cas_n => CONNECTED_TO_sdram_wire_cas_n, -- .cas_n
sdram_wire_cke => CONNECTED_TO_sdram_wire_cke, -- .cke
sdram_wire_cs_n => CONNECTED_TO_sdram_wire_cs_n, -- .cs_n
sdram_wire_dq => CONNECTED_TO_sdram_wire_dq, -- .dq
sdram_wire_dqm => CONNECTED_TO_sdram_wire_dqm, -- .dqm
sdram_wire_ras_n => CONNECTED_TO_sdram_wire_ras_n, -- .ras_n
sdram_wire_we_n => CONNECTED_TO_sdram_wire_we_n, -- .we_n
usb_DATA => CONNECTED_TO_usb_DATA, -- usb.DATA
usb_ADDR => CONNECTED_TO_usb_ADDR, -- .ADDR
usb_RD_N => CONNECTED_TO_usb_RD_N, -- .RD_N
usb_WR_N => CONNECTED_TO_usb_WR_N, -- .WR_N
usb_CS_N => CONNECTED_TO_usb_CS_N, -- .CS_N
usb_RST_N => CONNECTED_TO_usb_RST_N, -- .RST_N
usb_INT => CONNECTED_TO_usb_INT, -- .INT
usb_out_clk_clk => CONNECTED_TO_usb_out_clk_clk -- usb_out_clk.clk
);
|
library ieee;
use ieee.std_logic_1164.all;
entity repro is
end entity repro;
architecture a of repro is
signal clk : std_logic := '0';
signal check_stable_in_1 : std_logic_vector(1 to 5) := "00000";
alias check_stable_expr_1 : std_logic_vector(2 downto 0) is check_stable_in_1(3 to 5);
procedure check_stable(
signal clock : in std_logic;
signal expr : in std_logic_vector) is
begin
wait until rising_edge(clock);
end;
begin
clock : process is
begin
clk <= '1', '0' after 5 ns;
wait;
end process clock;
-- process
-- begin
-- check_stable(clk, check_stable_expr_1);
-- wait on clk, check_stable_expr_1;
-- assert check_stable_expr_1 = "000";
-- end process;
check_stable_1 : check_stable(clk, check_stable_expr_1);
end architecture;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: PicoBlaze General Perpose I/O Adapter
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
entity pb_GPIO_Adapter is
generic (
DEBUG : BOOLEAN := TRUE;
DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE;
BITS : POSITIVE := 8
);
port (
Clock : IN STD_LOGIC;
Reset : IN STD_LOGIC;
-- PicoBlaze interface
Address : IN T_SLV_8;
WriteStrobe : IN STD_LOGIC;
WriteStrobe_K : IN STD_LOGIC;
ReadStrobe : IN STD_LOGIC;
DataIn : IN T_SLV_8;
DataOut : OUT T_SLV_8;
Interrupt : OUT STD_LOGIC;
Interrupt_Ack : IN STD_LOGIC;
Message : OUT T_SLV_8;
-- GPIO interface
GPIO_Out : OUT STD_LOGIC_VECTOR(BITS - 1 downto 0);
GPIO_In : IN STD_LOGIC_VECTOR(BITS - 1 downto 0)
);
end entity;
architecture rtl of pb_GPIO_Adapter is
constant REG_RW_DATAOUT : UNSIGNED(0 downto 0) := "0";
constant REG_RO_DATAIN : UNSIGNED(0 downto 0) := "1";
signal AdrDec_we : STD_LOGIC;
signal AdrDec_re : STD_LOGIC;
signal AdrDec_WriteAddress : T_SLV_8;
signal AdrDec_ReadAddress : T_SLV_8;
signal AdrDec_Data : T_SLV_8;
signal Reg_DataOut : T_SLV_8 := (others => '0');
signal Reg_DataIn : T_SLV_8 := (others => '0');
begin
AdrDec : entity L_PicoBlaze.PicoBlaze_AddressDecoder
generic map (
DEVICE_NAME => str_trim(DEVICE_INSTANCE.DeviceShort),
BUS_NAME => str_trim(DEVICE_INSTANCE.BusShort),
READ_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_READ),
WRITE_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITE),
WRITEK_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITEK)
)
port map (
Clock => Clock,
Reset => Reset,
-- PicoBlaze interface
In_WriteStrobe => WriteStrobe,
In_WriteStrobe_K => WriteStrobe_K,
In_ReadStrobe => ReadStrobe,
In_Address => Address,
In_Data => DataIn,
Out_WriteStrobe => AdrDec_we,
Out_ReadStrobe => AdrDec_re,
Out_WriteAddress => AdrDec_WriteAddress,
Out_ReadAddress => AdrDec_ReadAddress,
Out_Data => AdrDec_Data
);
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
Reg_DataOut <= (others => '0');
Reg_DataIn <= (others => '0');
else
if (AdrDec_we = '1') THEN
case unsigned(AdrDec_WriteAddress(0 downto 0)) is
when REG_RW_DATAOUT =>
Reg_DataOut <= AdrDec_Data;
when others =>
null;
end case;
end if;
Reg_DataIn <= GPIO_In;
end if;
end if;
end process;
process(AdrDec_re, AdrDec_ReadAddress, Reg_DataIn, Reg_DataOut)
begin
DataOut <= Reg_DataIn;
case unsigned(AdrDec_ReadAddress(0 downto 0)) is
when REG_RW_DATAOUT =>
DataOut <= Reg_DataOut;
when REG_RO_DATAIN =>
DataOut <= Reg_DataIn;
when others =>
null;
end case;
end process;
Interrupt <= '0';
Message <= x"00";
GPIO_Out <= Reg_DataOut;
end;
|
library verilog;
use verilog.vl_types.all;
entity mist1032sa_uart_transmitter_async2sync is
generic(
N : integer := 1
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iSIGNAL : in vl_logic_vector;
oSIGNAL : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of N : constant is 1;
end mist1032sa_uart_transmitter_async2sync;
|
-- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo I2C_Controller.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- Modulo che si occupa della comunicazione con il chip audio
-- e i registri di controllo utilizzando il protocollo I2C.
-- **********************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity I2C_Controller is generic (
I2C_BUS_MODE: std_logic := '0'
);
port (
clk: in std_logic;
reset: in std_logic;
clear_ack: in std_logic;
clk_400KHz: in std_logic;
start_and_stop_en: in std_logic;
change_output_bit_en: in std_logic;
send_start_bit: in std_logic;
send_stop_bit: in std_logic;
data_in: in std_logic_vector(7 downto 0);
transfer_data: in std_logic;
read_byte: in std_logic;
num_bits_to_transfer: in integer; -- std_logic_vector(2 downto 0);
i2c_sdata: inout std_logic; -- I2C Data
i2c_sclk: out std_logic; -- I2C Clock
i2c_scen: out std_logic;
enable_clk: out std_logic;
ack: out std_logic;
data_from_i2c: buffer std_logic_vector(7 downto 0);
transfer_complete: out std_logic
);
end I2C_Controller;
architecture behaviour of I2C_Controller is
-- Stati della FSM
constant I2C_STATE_0_IDLE: std_logic_vector (2 downto 0) := "000";
constant I2C_STATE_1_PRE_START: std_logic_vector (2 downto 0) := "001";
constant I2C_STATE_2_START_BIT: std_logic_vector (2 downto 0) := "010";
constant I2C_STATE_3_TRANSFER_BYTE: std_logic_vector (2 downto 0) := "011";
constant I2C_STATE_4_TRANSFER_ACK: std_logic_vector (2 downto 0) := "100";
constant I2C_STATE_5_STOP_BIT: std_logic_vector (2 downto 0) := "101";
constant I2C_STATE_6_COMPLETE: std_logic_vector (2 downto 0) := "110";
signal current_bit: integer; --std_logic_vector (2 downto 0);
signal current_byte: std_logic_vector (7 downto 0);
signal ns_i2c_transceiver: std_logic_vector (2 downto 0);
signal s_i2c_transceiver: std_logic_vector (2 downto 0);
-- Segnali buffer
signal buff1: std_logic;
signal buff2: std_logic;
begin
buff1 <= '0' when s_i2c_transceiver = I2C_STATE_0_IDLE else '1';
buff2 <= '0' when s_i2c_transceiver = I2C_STATE_6_COMPLETE else '1';
i2c_sclk <= clk_400KHz when I2C_BUS_MODE = '0' else
clk_400KHz when ((s_i2c_transceiver = I2C_STATE_3_TRANSFER_BYTE)
or (s_i2c_transceiver = I2C_STATE_4_TRANSFER_ACK))
else '0';
i2c_sdata <=
'0' when (s_i2c_transceiver = I2C_STATE_2_START_BIT) else
'0' when (s_i2c_transceiver = I2C_STATE_5_STOP_BIT) else
'0' when ((s_i2c_transceiver = I2C_STATE_4_TRANSFER_ACK) and read_byte='1') else
current_byte(current_bit) when ((s_i2c_transceiver = I2C_STATE_3_TRANSFER_BYTE) and read_byte='0') else
'Z';
enable_clk <= buff1 and buff2;
transfer_complete <= '1' when (s_i2c_transceiver = I2C_STATE_6_COMPLETE) else '0';
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
s_i2c_transceiver <= I2C_STATE_0_IDLE;
else
s_i2c_transceiver <= ns_i2c_transceiver;
end if;
end if;
end process;
process(all)
begin
ns_i2c_transceiver <= I2C_STATE_0_IDLE;
if s_i2c_transceiver = I2C_STATE_0_IDLE then
if ((send_start_bit = '1') and (clk_400KHz = '0')) then
ns_i2c_transceiver <= I2C_STATE_1_PRE_START;
elsif (send_start_bit = '1') then
ns_i2c_transceiver <= I2C_STATE_2_START_BIT;
elsif (send_stop_bit = '1') then
ns_i2c_transceiver <= I2C_STATE_5_STOP_BIT;
elsif (transfer_data = '1') then
ns_i2c_transceiver <= I2C_STATE_3_TRANSFER_BYTE;
else
ns_i2c_transceiver <= I2C_STATE_0_IDLE;
end if;
elsif s_i2c_transceiver = I2C_STATE_1_PRE_START then
if (start_and_stop_en = '1') then
ns_i2c_transceiver <= I2C_STATE_2_START_BIT;
else
ns_i2c_transceiver <= I2C_STATE_1_PRE_START;
end if;
elsif s_i2c_transceiver = I2C_STATE_2_START_BIT then
if (change_output_bit_en = '1') then
if ((transfer_data = '1') and (I2C_BUS_MODE = '0')) then
ns_i2c_transceiver <= I2C_STATE_3_TRANSFER_BYTE;
else
ns_i2c_transceiver <= I2C_STATE_6_COMPLETE;
end if;
else
ns_i2c_transceiver <= I2C_STATE_2_START_BIT;
end if;
elsif s_i2c_transceiver = I2C_STATE_3_TRANSFER_BYTE then
if ((current_bit = 0) and (change_output_bit_en = '1')) then
if ((I2C_BUS_MODE = '0') or (num_bits_to_transfer = 6)) then
ns_i2c_transceiver <= I2C_STATE_4_TRANSFER_ACK;
else
ns_i2c_transceiver <= I2C_STATE_6_COMPLETE;
end if;
else
ns_i2c_transceiver <= I2C_STATE_3_TRANSFER_BYTE;
end if;
elsif s_i2c_transceiver = I2C_STATE_4_TRANSFER_ACK then
if (change_output_bit_en = '1') then
ns_i2c_transceiver <= I2C_STATE_6_COMPLETE;
else
ns_i2c_transceiver <= I2C_STATE_4_TRANSFER_ACK;
end if;
elsif s_i2c_transceiver = I2C_STATE_5_STOP_BIT then
if (start_and_stop_en = '1') then
ns_i2c_transceiver <= I2C_STATE_6_COMPLETE;
else
ns_i2c_transceiver <= I2C_STATE_5_STOP_BIT;
end if;
elsif s_i2c_transceiver = I2C_STATE_6_COMPLETE then
if (transfer_data = '0') then
ns_i2c_transceiver <= I2C_STATE_0_IDLE;
else
ns_i2c_transceiver <= I2C_STATE_6_COMPLETE;
end if;
else
ns_i2c_transceiver <= I2C_STATE_0_IDLE;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
i2c_scen <= '1';
elsif (change_output_bit_en='1' and (s_i2c_transceiver = I2C_STATE_2_START_BIT)) then
i2c_scen <= '0';
elsif (s_i2c_transceiver = I2C_STATE_5_STOP_BIT) then
i2c_scen <= '1';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
ack <= '0';
elsif (clear_ack = '1') then
ack <= '0';
elsif (start_and_stop_en='1' and (s_i2c_transceiver = I2C_STATE_4_TRANSFER_ACK)) then
ack <= i2c_sdata xor I2C_BUS_MODE;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
data_from_i2c <= "00000000";
elsif (start_and_stop_en='1' and (s_i2c_transceiver = I2C_STATE_3_TRANSFER_BYTE)) then
data_from_i2c <= data_from_i2c(6 downto 0) & i2c_sdata;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
current_bit <= 0;
elsif ((s_i2c_transceiver = I2C_STATE_3_TRANSFER_BYTE) and
(change_output_bit_en = '1')) then
current_bit <= current_bit - 1;
elsif not(s_i2c_transceiver = I2C_STATE_3_TRANSFER_BYTE) then
current_bit <= num_bits_to_transfer;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
current_byte <= "00000000";
elsif ((s_i2c_transceiver = I2C_STATE_0_IDLE) or
(s_i2c_transceiver = I2C_STATE_2_START_BIT)) then
current_byte <= data_in;
end if;
end if;
end process;
end behaviour; |
--
-- scandoubler.vhd
--
-- Copyright (c) 2015 Till Harbaum <[email protected]>
--
-- Migrated to VHDL by David Banks
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org/licenses/>.
-- TODO: Delay vsync one line
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity mist_scandoubler is
port (
-- system interface
clk : in std_logic; -- 32MHz
clk_16 : in std_logic; -- from shifter
clk_16_en : in std_logic;
scanlines : in std_logic;
-- shifter video interface
hs_in : in std_logic;
vs_in : in std_logic;
r_in : in std_logic;
g_in : in std_logic;
b_in : in std_logic;
-- output interface
hs_out : out std_logic;
vs_out : out std_logic;
r_out : out std_logic_vector(1 downto 0);
g_out : out std_logic_vector(1 downto 0);
b_out : out std_logic_vector(1 downto 0);
is15k : out std_logic
);
end entity;
architecture rtl of mist_scandoubler is
-- scan doubler output register
signal sd_out : std_logic_vector(2 downto 0);
-- --------------------- create output signals -----------------
-- latch everything once more to make it glitch free and apply scanline effect
signal scanline : std_logic;
-- 2 lines of 1024 pixels 3*4 bit RGB
type ram_type is array (2047 downto 0) of std_logic_vector (2 downto 0);
signal sd_buffer : ram_type;
-- use alternating sd_buffers when storing/reading data
signal vsD : std_logic;
signal line_toggle : std_logic;
-- total hsync time (in 16MHz cycles), hs_total reaches 1024
signal hs_max : std_logic_vector(9 downto 0);
signal hs_rise : std_logic_vector(9 downto 0);
signal hcnt : std_logic_vector(9 downto 0);
signal hsD : std_logic;
signal sd_hcnt : std_logic_vector(9 downto 0);
signal hs_sd : std_logic;
signal vs : std_logic;
signal hs : std_logic;
begin
hs_out <= hs;
vs_out <= vs;
process(clk)
begin
if rising_edge(clk) then
hs <= hs_sd;
vs <= vs_in;
-- reset scanlines at every new screen
if vs /= vs_in then
scanline <= '0';
end if;
-- toggle scanlines at begin of every hsync
if hs = '1' and hs_sd = '0' then
scanline <= not scanline;
end if;
-- if no scanlines or not a scanline
if scanlines = '0' or scanline = '0' then
r_out <= sd_out(2) & sd_out(2);
g_out <= sd_out(1) & sd_out(1);
b_out <= sd_out(0) & sd_out(0);
else
r_out <= '0' & sd_out(2);
g_out <= '0' & sd_out(1);
b_out <= '0' & sd_out(0);
end if;
end if;
end process;
-- ==================================================================
-- ======================== the line buffers ========================
-- ==================================================================
process(clk_16)
begin
if falling_edge(clk_16) then
if clk_16_en = '1' then
vsD <= vs_in;
if vsD /= vs_in then
line_toggle <= '0';
end if;
-- begin of incoming hsync
if hsD = '1' and hs_in = '0' then
line_toggle <= not line_toggle;
end if;
end if;
end if;
end process;
process(clk_16)
begin
if falling_edge(clk_16) then
if clk_16_en = '1' then
sd_buffer(conv_integer(line_toggle & hcnt)) <= r_in & g_in & b_in;
end if;
end if;
end process;
-- ==================================================================
-- =================== horizontal timing analysis ===================
-- ==================================================================
-- signal detection of 15khz if hsync frequency is less than 20KHz
is15k <= '1' when hs_max > (16000000/20000) else '0';
process(clk_16)
begin
if falling_edge(clk_16) then
if clk_16_en = '1' then
hsD <= hs_in;
-- falling edge of hsync indicates start of line
if hsD = '1' and hs_in = '0' then
hs_max <= hcnt;
hcnt <= (others => '0');
else
hcnt <= hcnt + 1;
end if;
-- save position of rising edge
if hsD = '0' and hs_in = '1' then
hs_rise <= hcnt;
end if;
end if;
end if;
end process;
-- ==================================================================
-- ==================== output timing generation ====================
-- ==================================================================
-- timing generation runs 32 MHz (twice the input signal analysis speed)
process(clk)
begin
if rising_edge(clk) then
-- output counter synchronous to input and at twice the rate
sd_hcnt <= sd_hcnt + 1;
if hsD = '1' and hs_in = '0' then
sd_hcnt <= hs_max;
end if;
if sd_hcnt = hs_max then
sd_hcnt <= (others => '0');
end if;
-- replicate horizontal sync at twice the speed
if sd_hcnt = hs_max then
hs_sd <= '0';
end if;
if sd_hcnt = hs_rise then
hs_sd <= '1';
end if;
-- read data from line sd_buffer
sd_out <= sd_buffer(conv_integer((not line_toggle) & sd_hcnt));
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_output_scalars_module.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2012-11-04
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.xd_output_scalars_fifo;
entity xd_output_scalars_module is
generic (
-- System generics:
C_FAMILY : string := "virtex6"; -- Xilinx FPGA family
C_MTBF_STAGES : integer;
C_PRMRY_IS_ACLK_ASYNC : integer;
C_MAX_N_OSCALARS : integer;
C_MAX_SCALAR_DWIDTH : integer;
C_N_OUTPUT_SCALARS : integer;
C_N_INOUT_SCALARS : integer;
C_OUTPUT_SCALAR_DWIDTH : std_logic_vector;
C_AP_OSCALAR_DIN_WIDTH : integer;
C_NONE : integer := 2);
port (
--- AP output arguments
ap_clk : in std_logic;
ap_rst : in std_logic;
ap_rst_s_axi_aclk : in std_logic;
ap_oscalar_vld : in std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
ap_oscalar_rdy : out std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
ap_oscalar_din : in std_logic_vector(C_AP_OSCALAR_DIN_WIDTH-1 downto 0);
clk : in std_logic;
rst : in std_logic;
oscalar_rst : in std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
oscalar_data : out std_logic_vector(C_MAX_N_OSCALARS*C_MAX_SCALAR_DWIDTH-1 downto 0);
oscalar_re : in std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
status_oscalar_empty : out std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
status_oscalar_full : out std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
status_oscalar_used : out std_logic_vector(C_MAX_N_OSCALARS*4-1 downto 0));
end entity;
architecture rtl of xd_output_scalars_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
signal status_oscalar_full_i : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
signal status_oscalar_full_i1 : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
signal ap_oscalar_rdy_i : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
signal ap_oscalar_rdy_i1 : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
begin
OUTPUT_SCALARS_GEN : for i in 0 to C_MAX_N_OSCALARS-1 generate
begin
ACTIVE_GEN : if (i < C_N_OUTPUT_SCALARS) generate
constant OSCALAR_DWIDTH : integer := get_int_element(C_OUTPUT_SCALAR_DWIDTH, i);
constant OSCALAR_LSB : integer := get_compact_LSB(C_OUTPUT_SCALAR_DWIDTH, i);
constant OSCALAR_MSB : integer := get_compact_MSB(C_OUTPUT_SCALAR_DWIDTH, i);
signal dout_i : std_logic_vector(OSCALAR_DWIDTH-1 downto 0);
signal fifo_rst_reg : std_logic;
begin
-- fifo_rst <= ap_rst_s_axi_aclk or oscalar_rst(i);
process(clk, ap_rst_s_axi_aclk)
begin
if(ap_rst_s_axi_aclk = '1') then
fifo_rst_reg <= '1';
elsif(clk'event and clk = '1') then
fifo_rst_reg <= oscalar_rst(i);
end if;
end process;
-- We might need to generate one hot for ap_oscalar_vld if there is no full handshake for output scalar vld
-- accelerator might hold valid high for more than one clock
-- TBD
-- oscalar_re signals are generated at the begining of the data phase;
-- not required a write-through fifo.
FIFO_I : entity axis_accelerator_adapter_v2_1_6.xd_output_scalars_fifo
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
WIDTH => OSCALAR_DWIDTH)
port map (
din => ap_oscalar_din(OSCALAR_MSB downto OSCALAR_LSB),
din_vld => ap_oscalar_vld(i),
din_rdy => ap_oscalar_rdy_i(i),
wr_clk => ap_clk,
dout => dout_i,
dout_vld => open,
dout_rdy => oscalar_re(i),
rd_used => status_oscalar_used(4*(i+1)-1 downto 4*i),
rd_empty => status_oscalar_empty(i),
rd_full => status_oscalar_full_i(i),
rd_clk => clk,
rst => fifo_rst_reg);
process(dout_i)
begin
oscalar_data((i+1)*C_MAX_SCALAR_DWIDTH-1 downto i*C_MAX_SCALAR_DWIDTH) <= (others => '0');
oscalar_data(i*C_MAX_SCALAR_DWIDTH+OSCALAR_DWIDTH-1 downto i*C_MAX_SCALAR_DWIDTH) <= dout_i;
end process;
EN_SYNC_GEN_OSCALAR : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
XD_OSCALAR_FULL_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_OSCALARS,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => '1',
prmry_in => status_oscalar_full_i(i),
prmry_vect_in => (others=>'0'),
scndry_aclk => clk,
scndry_resetn => '1',
scndry_out => status_oscalar_full(i),
scndry_vect_out => open
);
XD_OSCALAR_RDY_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_OSCALARS,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => '1',
prmry_in => ap_oscalar_rdy_i(i),
prmry_vect_in => (others=>'0'),
scndry_aclk => clk,
scndry_resetn => '1',
scndry_out => ap_oscalar_rdy(i),
scndry_vect_out => open
);
end generate EN_SYNC_GEN_OSCALAR;
NO_SYNC_GEN_OSCALAR : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
status_oscalar_full(i) <= status_oscalar_full_i(i);
ap_oscalar_rdy(i) <= ap_oscalar_rdy_i(i);
end generate NO_SYNC_GEN_OSCALAR;
end generate ACTIVE_GEN;
INACTIVE_GEN : if (i > C_N_OUTPUT_SCALARS-1 and i < 8) generate
begin
oscalar_data((i+1)*C_MAX_SCALAR_DWIDTH-1 downto i*C_MAX_SCALAR_DWIDTH) <= (others => '0');
-- A non used scalar is always ready:
ap_oscalar_rdy(i) <= '1';
status_oscalar_empty(i) <= '0';
status_oscalar_full(i) <= '0';
status_oscalar_used(4*(i+1)-1 downto 4*i) <= (others => '0');
end generate INACTIVE_GEN;
-- Pankaj
INOUT_ACTIVE_GEN : if (i > 7 and i < C_N_INOUT_SCALARS) generate
constant OSCALAR_DWIDTH : integer := get_int_element(C_OUTPUT_SCALAR_DWIDTH, i);
constant OSCALAR_LSB : integer := get_compact_LSB_IO(C_OUTPUT_SCALAR_DWIDTH, i);
constant OSCALAR_MSB : integer := get_compact_MSB_IO(C_OUTPUT_SCALAR_DWIDTH, i);
signal dout_i : std_logic_vector(OSCALAR_DWIDTH-1 downto 0);
signal fifo_rst_reg : std_logic;
begin
-- fifo_rst <= ap_rst_s_axi_aclk or oscalar_rst(i);
process(clk, ap_rst_s_axi_aclk)
begin
if(ap_rst_s_axi_aclk = '1') then
fifo_rst_reg <= '1';
elsif(clk'event and clk = '1') then
fifo_rst_reg <= oscalar_rst(i);
end if;
end process;
-- We might need to generate one hot for ap_oscalar_vld if there is no full handshake for output scalar vld
-- accelerator might hold valid high for more than one clock
-- TBD
-- oscalar_re signals are generated at the begining of the data phase;
-- not required a write-through fifo.
FIFO_I : entity axis_accelerator_adapter_v2_1_6.xd_output_scalars_fifo
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
WIDTH => OSCALAR_DWIDTH)
port map (
din => ap_oscalar_din(OSCALAR_MSB downto OSCALAR_LSB),
din_vld => ap_oscalar_vld(i),
din_rdy => ap_oscalar_rdy_i(i),
wr_clk => ap_clk,
dout => dout_i,
dout_vld => open,
dout_rdy => oscalar_re(i),
rd_used => status_oscalar_used(4*(i+1)-1 downto 4*i),
rd_empty => status_oscalar_empty(i),
rd_full => status_oscalar_full_i(i),
rd_clk => clk,
rst => fifo_rst_reg);
process(dout_i)
begin
oscalar_data((i+1)*C_MAX_SCALAR_DWIDTH-1 downto i*C_MAX_SCALAR_DWIDTH) <= (others => '0');
oscalar_data(i*C_MAX_SCALAR_DWIDTH+OSCALAR_DWIDTH-1 downto i*C_MAX_SCALAR_DWIDTH) <= dout_i;
end process;
EN_SYNC_GEN_OSCALAR : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
XD_OSCALAR_FULL_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_OSCALARS,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => '1',
prmry_in => status_oscalar_full_i(i),
prmry_vect_in => (others=>'0'),
scndry_aclk => clk,
scndry_resetn => '1',
scndry_out => status_oscalar_full(i),
scndry_vect_out => open
);
XD_OSCALAR_RDY_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_OSCALARS,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => '1',
prmry_in => ap_oscalar_rdy_i(i),
prmry_vect_in => (others=>'0'),
scndry_aclk => clk,
scndry_resetn => '1',
scndry_out => ap_oscalar_rdy(i),
scndry_vect_out => open
);
-- process(clk, rst)
-- begin
-- if(clk'event and clk = '1') then
-- if(rst = '1') then
-- status_oscalar_full_i1(i) <= '0';
-- status_oscalar_full(i) <= '0';
-- else
-- status_oscalar_full_i1(i) <=status_oscalar_full_i(i) ;
-- status_oscalar_full(i) <= status_oscalar_full_i1(i);
-- end if;
-- end if;
-- end process;
--
--
-- process(clk, rst)
-- begin
-- if(clk'event and clk = '1') then
-- if(rst = '1') then
-- ap_oscalar_rdy_i1(i) <= '1';
-- ap_oscalar_rdy(i) <= '1';
-- else
-- ap_oscalar_rdy_i1(i) <=ap_oscalar_rdy_i(i) ;
-- ap_oscalar_rdy(i) <= ap_oscalar_rdy_i1(i);
-- end if;
-- end if;
-- end process;
end generate EN_SYNC_GEN_OSCALAR;
NO_SYNC_GEN_OSCALAR : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
status_oscalar_full(i) <= status_oscalar_full_i(i);
ap_oscalar_rdy(i) <= ap_oscalar_rdy_i(i);
end generate NO_SYNC_GEN_OSCALAR;
end generate INOUT_ACTIVE_GEN;
INOUT_INACTIVE_GEN : if(i > C_N_INOUT_SCALARS-1) generate
begin
oscalar_data((i+1)*C_MAX_SCALAR_DWIDTH-1 downto i*C_MAX_SCALAR_DWIDTH) <= (others => '0');
-- A non used scalar is always ready:
ap_oscalar_rdy(i) <= '1';
status_oscalar_empty(i) <= '0';
status_oscalar_full(i) <= '0';
status_oscalar_used(4*(i+1)-1 downto 4*i) <= (others => '0');
end generate INOUT_INACTIVE_GEN;
---
end generate OUTPUT_SCALARS_GEN;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(A, B, Cin: in std_logic;
S, Cout: out std_logic
);
end entity ;
architecture full_adder of full_adder is
begin
S <= A xor B xor Cin;
Cout <= (A and B) or (A and Cin) or (B and Cin);
end architecture; |
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(A, B, Cin: in std_logic;
S, Cout: out std_logic
);
end entity ;
architecture full_adder of full_adder is
begin
S <= A xor B xor Cin;
Cout <= (A and B) or (A and Cin) or (B and Cin);
end architecture; |
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(A, B, Cin: in std_logic;
S, Cout: out std_logic
);
end entity ;
architecture full_adder of full_adder is
begin
S <= A xor B xor Cin;
Cout <= (A and B) or (A and Cin) or (B and Cin);
end architecture; |
----------------------------------------------------
-- Vladi & Adi --
-- TAU EE Senior year project --
-- --
--************************************************--
--****************** Octaver *********************--
--************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity octaver is
generic (
T: integer := 20000;
B: integer := 15 --15 bits for 20,000 memory places
);
Port ( x : in STD_LOGIC_VECTOR(31 downto 0);
y : out STD_LOGIC_VECTOR(31 downto 0);
clk_48: in std_logic;
options : in STD_LOGIC_VECTOR(0 to 3);
en : in STD_LOGIC_VECTOR(0 to 3)
);
end octaver;
architecture Behavioral of octaver is
signal y_temp_s : signed(31 downto 0):= x"00000000";
signal i : std_logic_vector (B-1 downto 0) := "000000000000000";
signal max_delay : integer := T-1;
--********************** BRAM signals
signal we : std_logic := '1';
signal addr1 : std_logic_vector(B-1 downto 0) := "000000000000000";
signal addr2 : std_logic_vector(B-1 downto 0):= "000000000000000";
signal data_in : std_logic_vector(31 downto 0); --32 bit word
signal data_out1 : std_logic_vector(31 downto 0);
signal data_out2 : std_logic_vector(31 downto 0);
--*************************
component bram_oct is
generic (
T: integer := 20000;
B: integer := 15 --15 bits for 20,000 memory places
);
port (
CLK : in std_logic;
WE : in std_logic;
ADDR1 : in std_logic_vector(B-1 downto 0);
ADDR2 : in std_logic_vector(B-1 downto 0);
DI : in std_logic_vector(31 downto 0); --32 bit word
DO1 : out std_logic_vector(31 downto 0);
DO2 : out std_logic_vector(31 downto 0)
);
end component bram_oct;
begin
--*********** temporary debugging signals *********
--addr1_temp0 <= "00000000000000000" & std_logic_vector(addr1);
--addr2_temp1 <= "00000000000000000" & std_logic_vector(addr2);
--*************************************************
bram_oct_inst : bram_oct
port map (
CLK => clk_48,
WE => we,
ADDR1 => addr1,
ADDR2 => addr2,
DI => data_in,
DO1 => data_out1,
DO2 => data_out2
);
mem:process(clk_48)
begin
if rising_edge(clk_48) then
if to_integer(unsigned(i))= max_delay-2 then
i<= "000000000000000";
else
i <= std_logic_vector(unsigned(i)+1);
end if;
end if;
end process;
addr_1:process(clk_48)
begin
if rising_edge(clk_48) then
if (to_integer(unsigned(addr1)) = max_delay-2) then
addr1 <= "000000000000000";
else
addr1 <= std_logic_vector(unsigned(addr1) + 1);
end if;
end if;
end process;
addr_2:process(clk_48)
begin
if rising_edge(clk_48) then
--*********************** 1 octave up ****************
if (options="1000" or options="1100" or options="1110" or options="0011" or options="1111" or options="0111") then
if (to_integer(unsigned(addr2)) >= max_delay-2) then
addr2 <= "000000000000000";
end if;
addr2 <= std_logic_vector(shift_left(unsigned(i),1) + 1);
end if;
--***************************************************
--*********************** 2 octaves up ****************
if (options="0100" or options="0001" ) then
if (to_integer(unsigned(addr2)) >= max_delay-2) then
addr2 <= "000000000000000";
end if;
addr2 <= std_logic_vector(shift_left(unsigned(i),2) + 1);
end if;
--***************************************************
--*********************** 1 octave dowm ****************
if (options="0010") then
if (to_integer(unsigned(addr2)) >= max_delay-2) then
addr2 <= "000000000000000";
end if;
addr2 <= std_logic_vector(shift_right(unsigned(i),1) + 1);
end if;
--***************************************************
end if;
end process;
process (clk_48, options)
begin
if en(1)= '1' then
if rising_edge(clk_48) then
if options="1000" then --fir, 1up, 3000
max_delay <= 3000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= x;
y <= std_logic_vector(y_temp_s);
end if;
if options="1100" then --fir, 1up, 8000
max_delay <= 8000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= x;
y <= std_logic_vector(y_temp_s);
end if;
if options="1110" then --fir, 1up, 15000
max_delay <= 15000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= x;
y <= std_logic_vector(y_temp_s);
end if;
if options="1111" then --iir, 1up, 5000 (T/4)
max_delay <= 5000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= std_logic_vector(y_temp_s);
y <= std_logic_vector(y_temp_s);
end if;
if options="0111" then --iir, 1up, 10000 (T/2)
max_delay <= 10000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= std_logic_vector(y_temp_s);
y <= std_logic_vector(y_temp_s);
end if;
if options="0011" then --iir, 1up, 19999 (T-1)
max_delay <= 19999;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= std_logic_vector(y_temp_s);
y <= std_logic_vector(y_temp_s);
end if;
--********************************************************
if options="0100" then --fir, 2up, 3000
max_delay <= 3000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= x;
y <= std_logic_vector(y_temp_s);
end if;
if options="0001" then --fir, 2up, 500 - robot sound
max_delay <= 500;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= x;
y <= std_logic_vector(y_temp_s);
end if;
--********************************************************
if options="0010" then --fir, 1down, 8000
max_delay <= 8000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= x;
y <= std_logic_vector(y_temp_s);
end if;
--********************************************************
end if;
else
y<=x;
end if;
end process;
end Behavioral;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_parity is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 60;
Cx_rst : integer := 10;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
DCTS_N, DCTS_E, DCTS_w, DCTS_S, DCTS_L: in std_logic;
DRTS_N, DRTS_E, DRTS_W, DRTS_S, DRTS_L: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_N, RTS_E, RTS_W, RTS_S, RTS_L: out std_logic;
CTS_N, CTS_E, CTS_w, CTS_S, CTS_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L:out std_logic;
healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L:out std_logic
);
end router_parity;
architecture behavior of router_parity is
COMPONENT parity_checker_packet_detector is
generic(DATA_WIDTH : integer := 32);
port(
reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
faulty_packet, healthy_packet: out std_logic
);
end COMPONENT;
COMPONENT FIFO
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector (DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT Arbiter
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic;
DCTS: in std_logic;
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic;
Xbar_sel : out std_logic_vector(4 downto 0);
RTS: out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 0;
Rxy_rst: integer := 60;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
begin
------------------------------------------------------------------------------------------------------------------------------
-- block diagram of one channel
--
-- .____________grant_________
-- | ▲
-- | _______ __|_______
-- | | | | |
-- | | LBDR |---req--->| Arbiter | <--handshake-->
-- | |_______| |__________| signals
-- | ▲ |
-- __▼___ | flit ___▼__
-- RX ----->| | | type | |
-- <-handshake->| FIFO |---o------------->| |-----> TX
-- signals |______| ------>| |
-- ------>| XBAR |
-- ------>| |
-- ------>| |
-- |______|
--
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the parity_checkers
PC_N: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_N, DRTS =>DRTS_N, faulty_packet => faulty_packet_N , healthy_packet => healthy_packet_N);
PC_E: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_E, DRTS =>DRTS_E, faulty_packet => faulty_packet_E , healthy_packet => healthy_packet_E);
PC_W: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_W, DRTS =>DRTS_W, faulty_packet => faulty_packet_W , healthy_packet => healthy_packet_W);
PC_S: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_S, DRTS =>DRTS_S, faulty_packet => faulty_packet_S , healthy_packet => healthy_packet_S);
PC_L: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_L, DRTS =>DRTS_L, faulty_packet => faulty_packet_L , healthy_packet => healthy_packet_L);
-- all the FIFOs
FIFO_N: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_N, DRTS => DRTS_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
CTS => CTS_N, empty_out => empty_N, Data_out => FIFO_D_out_N);
FIFO_E: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_E, DRTS => DRTS_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
CTS => CTS_E, empty_out => empty_E, Data_out => FIFO_D_out_E);
FIFO_W: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_W, DRTS => DRTS_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
CTS => CTS_W, empty_out => empty_W, Data_out => FIFO_D_out_W);
FIFO_S: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_S, DRTS => DRTS_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
CTS => CTS_S, empty_out => empty_S, Data_out => FIFO_D_out_S);
FIFO_L: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_L, DRTS => DRTS_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
CTS => CTS_L, empty_out => empty_L, Data_out => FIFO_D_out_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Arbiters
Arbiter_N: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => '0' , Req_E => Req_EN, Req_W => Req_WN, Req_S => Req_SN, Req_L => Req_LN,
DCTS => DCTS_N, Grant_N => Grant_NN, Grant_E => Grant_NE, Grant_W => Grant_NW, Grant_S => Grant_NS, Grant_L => Grant_NL,
Xbar_sel => Xbar_sel_N,
RTS => RTS_N
);
Arbiter_E: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NE , Req_E => '0', Req_W => Req_WE, Req_S => Req_SE, Req_L => Req_LE,
DCTS => DCTS_E, Grant_N => Grant_EN, Grant_E => Grant_EE, Grant_W => Grant_EW, Grant_S => Grant_ES, Grant_L => Grant_EL,
Xbar_sel => Xbar_sel_E,
RTS => RTS_E
);
Arbiter_W: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NW , Req_E => Req_EW, Req_W => '0', Req_S => Req_SW, Req_L => Req_LW,
DCTS => DCTS_W, Grant_N => Grant_WN, Grant_E => Grant_WE, Grant_W => Grant_WW, Grant_S => Grant_WS, Grant_L => Grant_WL,
Xbar_sel => Xbar_sel_W,
RTS => RTS_W
);
Arbiter_S: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NS , Req_E => Req_ES, Req_W => Req_WS, Req_S => '0', Req_L => Req_LS,
DCTS => DCTS_S, Grant_N => Grant_SN, Grant_E => Grant_SE, Grant_W => Grant_SW, Grant_S => Grant_SS, Grant_L => Grant_SL,
Xbar_sel => Xbar_sel_S,
RTS => RTS_S
);
Arbiter_L: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NL , Req_E => Req_EL, Req_W => Req_WL, Req_S => Req_SL, Req_L => '0',
DCTS => DCTS_L, Grant_N => Grant_LN, Grant_E => Grant_LE, Grant_W => Grant_LW, Grant_S => Grant_LS, Grant_L => Grant_LL,
Xbar_sel => Xbar_sel_L,
RTS => RTS_L
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_parity is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 60;
Cx_rst : integer := 10;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
DCTS_N, DCTS_E, DCTS_w, DCTS_S, DCTS_L: in std_logic;
DRTS_N, DRTS_E, DRTS_W, DRTS_S, DRTS_L: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_N, RTS_E, RTS_W, RTS_S, RTS_L: out std_logic;
CTS_N, CTS_E, CTS_w, CTS_S, CTS_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L:out std_logic;
healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L:out std_logic
);
end router_parity;
architecture behavior of router_parity is
COMPONENT parity_checker_packet_detector is
generic(DATA_WIDTH : integer := 32);
port(
reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
faulty_packet, healthy_packet: out std_logic
);
end COMPONENT;
COMPONENT FIFO
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector (DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT Arbiter
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic;
DCTS: in std_logic;
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic;
Xbar_sel : out std_logic_vector(4 downto 0);
RTS: out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 0;
Rxy_rst: integer := 60;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
begin
------------------------------------------------------------------------------------------------------------------------------
-- block diagram of one channel
--
-- .____________grant_________
-- | ▲
-- | _______ __|_______
-- | | | | |
-- | | LBDR |---req--->| Arbiter | <--handshake-->
-- | |_______| |__________| signals
-- | ▲ |
-- __▼___ | flit ___▼__
-- RX ----->| | | type | |
-- <-handshake->| FIFO |---o------------->| |-----> TX
-- signals |______| ------>| |
-- ------>| XBAR |
-- ------>| |
-- ------>| |
-- |______|
--
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the parity_checkers
PC_N: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_N, DRTS =>DRTS_N, faulty_packet => faulty_packet_N , healthy_packet => healthy_packet_N);
PC_E: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_E, DRTS =>DRTS_E, faulty_packet => faulty_packet_E , healthy_packet => healthy_packet_E);
PC_W: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_W, DRTS =>DRTS_W, faulty_packet => faulty_packet_W , healthy_packet => healthy_packet_W);
PC_S: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_S, DRTS =>DRTS_S, faulty_packet => faulty_packet_S , healthy_packet => healthy_packet_S);
PC_L: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_L, DRTS =>DRTS_L, faulty_packet => faulty_packet_L , healthy_packet => healthy_packet_L);
-- all the FIFOs
FIFO_N: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_N, DRTS => DRTS_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
CTS => CTS_N, empty_out => empty_N, Data_out => FIFO_D_out_N);
FIFO_E: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_E, DRTS => DRTS_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
CTS => CTS_E, empty_out => empty_E, Data_out => FIFO_D_out_E);
FIFO_W: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_W, DRTS => DRTS_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
CTS => CTS_W, empty_out => empty_W, Data_out => FIFO_D_out_W);
FIFO_S: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_S, DRTS => DRTS_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
CTS => CTS_S, empty_out => empty_S, Data_out => FIFO_D_out_S);
FIFO_L: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_L, DRTS => DRTS_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
CTS => CTS_L, empty_out => empty_L, Data_out => FIFO_D_out_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Arbiters
Arbiter_N: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => '0' , Req_E => Req_EN, Req_W => Req_WN, Req_S => Req_SN, Req_L => Req_LN,
DCTS => DCTS_N, Grant_N => Grant_NN, Grant_E => Grant_NE, Grant_W => Grant_NW, Grant_S => Grant_NS, Grant_L => Grant_NL,
Xbar_sel => Xbar_sel_N,
RTS => RTS_N
);
Arbiter_E: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NE , Req_E => '0', Req_W => Req_WE, Req_S => Req_SE, Req_L => Req_LE,
DCTS => DCTS_E, Grant_N => Grant_EN, Grant_E => Grant_EE, Grant_W => Grant_EW, Grant_S => Grant_ES, Grant_L => Grant_EL,
Xbar_sel => Xbar_sel_E,
RTS => RTS_E
);
Arbiter_W: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NW , Req_E => Req_EW, Req_W => '0', Req_S => Req_SW, Req_L => Req_LW,
DCTS => DCTS_W, Grant_N => Grant_WN, Grant_E => Grant_WE, Grant_W => Grant_WW, Grant_S => Grant_WS, Grant_L => Grant_WL,
Xbar_sel => Xbar_sel_W,
RTS => RTS_W
);
Arbiter_S: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NS , Req_E => Req_ES, Req_W => Req_WS, Req_S => '0', Req_L => Req_LS,
DCTS => DCTS_S, Grant_N => Grant_SN, Grant_E => Grant_SE, Grant_W => Grant_SW, Grant_S => Grant_SS, Grant_L => Grant_SL,
Xbar_sel => Xbar_sel_S,
RTS => RTS_S
);
Arbiter_L: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NL , Req_E => Req_EL, Req_W => Req_WL, Req_S => Req_SL, Req_L => '0',
DCTS => DCTS_L, Grant_N => Grant_LN, Grant_E => Grant_LE, Grant_W => Grant_LW, Grant_S => Grant_LS, Grant_L => Grant_LL,
Xbar_sel => Xbar_sel_L,
RTS => RTS_L
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
);
end;
architecture behavior of Arbiter is
-- next
-- Arbiter router or NI
-- --- ---------------------------- ---- ----
-- from LBDR ---> |Req(s) RTS | -----> |DRTS
-- To FIFO <--- |Grant(s) DCTS| <----- |CTS
-- to XBAR <--- |Xbar_sel | |
-- --- ---------------------------- ---- ----
--------------------------------------------------------------------------------------------
-- an example of a request/grant + handshake process with next router or NI
--CLK _|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|__
-- Req _____|'''''''''''''''''''''''''''''''''''''''''''|________
-- _________ ___________________ _______ _______ _______ ____
-- TX _________X_______HEADER______X_Body__X_Body__X__Tail_X____
-- Grant _________________________|'''|___|'''|___|'''|____________
-- RTs _________|'''''''''''''''''''|___|'''''''|___|'''''''|____
-- DCTS _________________________|'''|_______|'''|_______|'''|____
-- |<---------clear----------->|
-- | to send |
--------------------------------------------------------------------------------------------
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in, next_state : STATE_TYPE := IDLE;
SIGNAL RTS_FF, RTS_FF_in: std_logic;
begin
-- process for updating the state of arbiter's FSM, also setting RTS based on the state (if Grant is given or not)
process(clk, reset)begin
if reset = '0' then
state<=IDLE;
RTS_FF <= '0';
elsif clk'event and clk = '1' then
-- no grant given yet, it might be that there is no request to
-- arbiter or request is there, but the next router's/NI's FIFO is full
state <= state_in;
RTS_FF <= RTS_FF_in;
end if;
end process;
-- anything below here is pure combinational
RTS <= RTS_FF;
process(RTS_FF, DCTS, state, next_state)begin
if RTS_FF = '1' and DCTS = '0' then
state_in <= state;
else
state_in <= next_state;
end if;
end process;
process(state, RTS_FF, DCTS)begin
if state = IDLE then
RTS_FF_in <= '0';
-- if there was a grant given to one of the inputs,
-- tell the next router/NI that the output data is valid
else
if RTS_FF = '1' and DCTS = '1' then
RTS_FF_in <= '0';
else
RTS_FF_in <= '1';
end if;
end if ;
end process;
-- sets the grants using round robin
-- the order is L --> N --> E --> W --> S and then back to L
process(state, Req_N, Req_E, Req_W, Req_S, Req_L, DCTS, RTS_FF)begin
Grant_N <= '0';
Grant_E <= '0';
Grant_W <= '0';
Grant_S <= '0';
Grant_L <= '0';
Xbar_sel<= "00000";
case(state) is
when IDLE =>
Xbar_sel<= "00000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
when North =>
Grant_N <= DCTS and RTS_FF ;
Xbar_sel<= "00001";
If Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
else
next_state <= IDLE;
end if;
when East =>
Grant_E <= DCTS and RTS_FF;
Xbar_sel<= "00010";
If Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
else
next_state <= IDLE;
end if;
when West =>
Grant_W <= DCTS and RTS_FF;
Xbar_sel<= "00100";
If Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
else
next_state <= IDLE;
end if;
when South =>
Grant_S <= DCTS and RTS_FF;
Xbar_sel<= "01000";
If Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
else
next_state <= IDLE;
end if;
when others => -- Local
Grant_L <= DCTS and RTS_FF;
Xbar_sel<= "10000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
end case ;
end process;
end;
|
package test_pkg is
type t_axi_wr_slave_in_if is record
awid : bit_vector;
awaddr : bit_vector;
awlen : bit_vector(7 downto 0);
awsize : bit_vector(2 downto 0);
awburst : bit_vector(1 downto 0);
awlock : bit;
awcache : bit_vector(3 downto 0);
awprot : bit_vector(2 downto 0);
awqos : bit_vector(3 downto 0);
awregion : bit_vector(3 downto 0);
awuser : bit_vector;
awvalid : bit;
wdata : bit_vector;
wstrb : bit_vector;
wlast : bit;
wuser : bit_vector;
wvalid : bit;
bready : bit;
end record;
end package;
use work.test_pkg.all;
entity test2 is
port (
wr_port_in : in t_axi_wr_slave_in_if
);
end entity test2;
architecture beh of test2 is
begin
process is
begin
wait for 1 ns;
assert wr_port_in.wdata = (31 downto 0 => '1');
wait;
end process;
end architecture beh;
use work.test_pkg.all;
entity issue519 is
end entity issue519;
architecture beh of issue519 is
type t_axi_write_address_channel is record
awid : bit_vector;
awaddr : bit_vector;
awlen : bit_vector(7 downto 0);
awsize : bit_vector(2 downto 0);
awburst : bit_vector(1 downto 0);
awlock : bit;
awcache : bit_vector(3 downto 0);
awprot : bit_vector(2 downto 0);
awqos : bit_vector(3 downto 0);
awregion : bit_vector(3 downto 0);
awuser : bit_vector;
awvalid : bit;
awready : bit;
end record;
type t_axi_write_data_channel is record
wdata : bit_vector;
wstrb : bit_vector;
wlast : bit;
wuser : bit_vector;
wvalid : bit;
wready : bit;
end record;
type t_axi_write_response_channel is record
bid : bit_vector;
bresp : bit_vector(1 downto 0);
buser : bit_vector;
bvalid : bit;
bready : bit;
end record;
type t_axi_if is record
write_address_channel : t_axi_write_address_channel;
write_data_channel : t_axi_write_data_channel;
write_response_channel : t_axi_write_response_channel;
end record;
signal axi_if : t_axi_if( write_address_channel( awid( 8 -1 downto 0),
awaddr( 32-1 downto 0),
awuser( 8 -1 downto 0)),
write_data_channel( wdata( 32-1 downto 0),
wstrb( 4 -1 downto 0),
wuser( 8 -1 downto 0)),
write_response_channel(bid( 8 -1 downto 0),
buser( 8 -1 downto 0)));
begin
i_test : entity work.test2
port map (
wr_port_in.awid => axi_if.write_address_channel.awid,
wr_port_in.awaddr => axi_if.write_address_channel.awaddr,
wr_port_in.awlen => axi_if.write_address_channel.awlen,
wr_port_in.awsize => axi_if.write_address_channel.awsize,
wr_port_in.awburst => axi_if.write_address_channel.awburst,
wr_port_in.awlock => axi_if.write_address_channel.awlock,
wr_port_in.awcache => axi_if.write_address_channel.awcache,
wr_port_in.awprot => axi_if.write_address_channel.awprot,
wr_port_in.awqos => axi_if.write_address_channel.awqos,
wr_port_in.awregion => axi_if.write_address_channel.awregion,
wr_port_in.awuser => axi_if.write_address_channel.awuser,
wr_port_in.awvalid => axi_if.write_address_channel.awvalid,
wr_port_in.wdata => axi_if.write_data_channel.wdata,
wr_port_in.wstrb => axi_if.write_data_channel.wstrb,
wr_port_in.wlast => axi_if.write_data_channel.wlast,
wr_port_in.wuser => axi_if.write_data_channel.wuser,
wr_port_in.wvalid => axi_if.write_data_channel.wvalid,
wr_port_in.bready => axi_if.write_response_channel.bready
);
process
begin
axi_if.write_data_channel.wdata <= X"ffffffff";
wait;
end process;
end architecture beh;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_e_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_e_e-rtl-a.vhd,v 1.1 2004/04/06 10:49:55 wig Exp $
-- $Date: 2004/04/06 10:49:55 $
-- $Log: inst_e_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:49:55 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_e_e
--
architecture rtl of inst_e_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_ea_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ea_e
egi_scani : in std_ulogic_vector(10 downto 0);
egi_scano : out std_ulogic_vector(10 downto 0);
p_mix_cp_laddr_31_1_gi : in std_ulogic_vector(30 downto 0);
p_mix_cp_lcmd_6_6_gi : in std_ulogic;
p_mix_gpio_int_4_0_go : out std_ulogic_vector(4 downto 0);
p_mix_nreset_gi : in std_ulogic;
p_mix_nreset_s_gi : in std_ulogic;
p_mix_tmi_sbist_fail_11_10_gi : in std_ulogic_vector(1 downto 0);
p_mix_tmi_sbist_fail_9_0_go : out std_ulogic_vector(9 downto 0);
p_mix_tmu_dac_reset_go : out std_ulogic;
p_mix_v_select_2_2_gi : in std_ulogic;
p_mix_v_select_5_5_gi : in std_ulogic
-- End of Generated Port for Entity inst_ea_e
);
end component;
-- ---------
component inst_eb_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_eb_e
p_mix_nreset_gi : in std_ulogic;
p_mix_nreset_s_gi : in std_ulogic;
p_mix_tmi_sbist_fail_12_10_go : out std_ulogic_vector(2 downto 0);
p_mix_v_select_5_0_go : out std_ulogic_vector(5 downto 0);
vclkl27 : in std_ulogic;
vio_scani : in std_ulogic_vector(30 downto 0);
vio_scano : out std_ulogic_vector(30 downto 0)
-- End of Generated Port for Entity inst_eb_e
);
end component;
-- ---------
component inst_ec_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ec_e
p_mix_nreset_gi : in std_ulogic;
p_mix_nreset_s_gi : in std_ulogic;
p_mix_v_select_5_0_gi : in std_ulogic_vector(5 downto 0);
tpm_scani : in std_ulogic_vector(12 downto 0);
tpm_scano : out std_ulogic_vector(12 downto 0)
-- End of Generated Port for Entity inst_ec_e
);
end component;
-- ---------
component inst_ed_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ed_e
p_mix_acg_systime_init_30_0_gi : in std_ulogic_vector(30 downto 0);
p_mix_cgs_ramclk_go : out std_ulogic;
p_mix_gpio_int_2_0_gi : in std_ulogic_vector(2 downto 0);
p_mix_itm_scani_0_0_gi : in std_ulogic;
p_mix_nreset_go : out std_ulogic;
p_mix_nreset_s_go : out std_ulogic;
p_mix_tmi_scano_0_0_go : out std_ulogic;
p_mix_vclkl27_go : out std_ulogic
-- End of Generated Port for Entity inst_ed_e
);
end component;
-- ---------
component inst_ee_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ee_e
cgs_ramclk : in std_ulogic;
itm_scani : out std_ulogic_vector(70 downto 0);
nreset : in std_ulogic;
nreset_s : in std_ulogic;
si_vclkx2 : in std_ulogic;
tmi_sbist_fail : in std_ulogic_vector(12 downto 0);
tmi_scano : in std_ulogic_vector(70 downto 0)
-- End of Generated Port for Entity inst_ee_e
);
end component;
-- ---------
component inst_ef_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ef_e
cp_laddro : out std_ulogic_vector(31 downto 0);
cp_lcmd : out std_ulogic_vector(6 downto 0);
cpu_scani : in std_ulogic_vector(7 downto 0);
cpu_scano : out std_ulogic_vector(7 downto 0);
int23 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
int24 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
int25 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
int26 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
int27 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
nreset : in std_ulogic;
nreset_s : in std_ulogic;
tap_reset_n : in std_ulogic;
tap_reset_n_o : out std_ulogic
-- End of Generated Port for Entity inst_ef_e
);
end component;
-- ---------
component inst_eg_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_eg_e
acg_systime_init : out std_ulogic_vector(30 downto 0);
adp_scani : in std_ulogic_vector(6 downto 0);
adp_scano : out std_ulogic_vector(6 downto 0);
nreset : in std_ulogic;
nreset_s : in std_ulogic
-- End of Generated Port for Entity inst_eg_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal acg_systime_init : std_ulogic_vector(30 downto 0);
signal s_int_cgs_ramclk : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal cp_laddr : std_ulogic_vector(31 downto 0);
signal cp_lcmd : std_ulogic_vector(6 downto 0);
signal gpio_int : std_ulogic_vector(4 downto 0);
signal itm_scani : std_ulogic_vector(70 downto 0);
signal nreset : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nreset_s : std_ulogic;
signal tap_reset_n_o : std_ulogic;
signal tmi_sbist_fail : std_ulogic_vector(12 downto 0);
signal tmi_scano : std_ulogic_vector(70 downto 0);
signal v_select : std_ulogic_vector(5 downto 0);
signal s_int_vclkl27 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
cgs_ramclk <= s_int_cgs_ramclk; -- __I_O_BIT_PORT
p_mix_nreset_go <= nreset; -- __I_O_BIT_PORT
vclkl27 <= s_int_vclkl27; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_ea
inst_ea: inst_ea_e
port map (
egi_scani => itm_scani(31 downto 21),
egi_scano => tmi_scano(31 downto 21),
p_mix_cp_laddr_31_1_gi => cp_laddr(31 downto 1), -- GuestBusLBC(memorymappedI/O)InterfaceLBCinterfacetobeusecurrentlybyGuestBus
p_mix_cp_lcmd_6_6_gi => cp_lcmd(6), -- GuestBusLBC(memorymappedI/O)Interface
p_mix_gpio_int_4_0_go => gpio_int, -- GPIOWakeUPSignalsInterruptinputs
p_mix_nreset_gi => nreset, -- GlobalRESET(Verilogmacro)
p_mix_nreset_s_gi => nreset_s, -- GlobalRESET(Verilogmacro)
p_mix_tmi_sbist_fail_11_10_gi => tmi_sbist_fail(11 downto 10),
p_mix_tmi_sbist_fail_9_0_go => tmi_sbist_fail(9 downto 0),
p_mix_tmu_dac_reset_go => tmu_dac_reset, -- CADCTestModeRGBADAC
p_mix_v_select_2_2_gi => v_select(2), -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
p_mix_v_select_5_5_gi => v_select(5) -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
);
-- End of Generated Instance Port Map for inst_ea
-- Generated Instance Port Map for inst_eb
inst_eb: inst_eb_e
port map (
p_mix_nreset_gi => nreset, -- GlobalRESET(Verilogmacro)
p_mix_nreset_s_gi => nreset_s, -- GlobalRESET(Verilogmacro)
p_mix_tmi_sbist_fail_12_10_go => tmi_sbist_fail(12 downto 10),
p_mix_v_select_5_0_go => v_select, -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
vclkl27 => s_int_vclkl27, -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
vio_scani => itm_scani(70 downto 40),
vio_scano => tmi_scano(70 downto 40)
);
-- End of Generated Instance Port Map for inst_eb
-- Generated Instance Port Map for inst_ec
inst_ec: inst_ec_e
port map (
p_mix_nreset_gi => nreset, -- GlobalRESET(Verilogmacro)
p_mix_nreset_s_gi => nreset_s, -- GlobalRESET(Verilogmacro)
p_mix_v_select_5_0_gi => v_select, -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
tpm_scani => itm_scani(20 downto 8),
tpm_scano => tmi_scano(20 downto 8)
);
-- End of Generated Instance Port Map for inst_ec
-- Generated Instance Port Map for inst_ed
inst_ed: inst_ed_e
port map (
p_mix_acg_systime_init_30_0_gi => acg_systime_init, -- ADPinterfaceScan
p_mix_cgs_ramclk_go => s_int_cgs_ramclk, -- ClockSignalsESDRAMInterface
p_mix_gpio_int_2_0_gi => gpio_int(2 downto 0), -- GPIOWakeUPSignalsInterruptinputs
p_mix_itm_scani_0_0_gi => itm_scani(0),
p_mix_nreset_go => nreset, -- GlobalRESET(Verilogmacro)
p_mix_nreset_s_go => nreset_s, -- GlobalRESET(Verilogmacro)
p_mix_tmi_scano_0_0_go => tmi_scano(0),
p_mix_vclkl27_go => s_int_vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_ed
-- Generated Instance Port Map for inst_ee
inst_ee: inst_ee_e
port map (
cgs_ramclk => s_int_cgs_ramclk, -- ClockSignalsESDRAMInterface
itm_scani => itm_scani,
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
si_vclkx2 => si_vclkx2, -- DigitalVideoPort
tmi_sbist_fail => tmi_sbist_fail,
tmi_scano => tmi_scano
);
-- End of Generated Instance Port Map for inst_ee
-- Generated Instance Port Map for inst_ef
inst_ef: inst_ef_e
port map (
cp_laddro => cp_laddr, -- GuestBusLBC(memorymappedI/O)InterfaceLBCinterfacetobeusecurrentlybyGuestBus
cp_lcmd => cp_lcmd, -- GuestBusLBC(memorymappedI/O)Interface
cpu_scani => itm_scani(39 downto 32),
cpu_scano => tmi_scano(39 downto 32),
int23 => gpio_int(0), -- GPIOWakeUPSignalsInterruptinputs
int24 => gpio_int(1), -- GPIOWakeUPSignalsInterruptinputs
int25 => gpio_int(2), -- GPIOWakeUPSignalsInterruptinputs
int26 => gpio_int(3), -- GPIOWakeUPSignalsInterruptinputs
int27 => gpio_int(4), -- GPIOWakeUPSignalsInterruptinputs
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
tap_reset_n => tap_reset_n_o, -- RESETports
tap_reset_n_o => tap_reset_n_o -- RESETports
);
-- End of Generated Instance Port Map for inst_ef
-- Generated Instance Port Map for inst_eg
inst_eg: inst_eg_e
port map (
acg_systime_init => acg_systime_init, -- ADPinterfaceScan
adp_scani => itm_scani(7 downto 1),
adp_scano => tmi_scano(7 downto 1),
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s -- GlobalRESET(Verilogmacro)
);
-- End of Generated Instance Port Map for inst_eg
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.HammingPack16.all;
use work.NoCPackage.all;
entity SwitchControl is
generic(address : regflit := (others=>'0'));
port(
clock : in std_logic;
reset : in std_logic;
h : in regNport; -- solicitacoes de chaveamento
ack_h : out regNport; -- resposta para as solitacoes de chaveamento
data : in arrayNport_regflit; -- dado do buffer (contem o endereco destino)
c_ctrl : in std_logic; -- indica se foi lido ou criado de um pacote de controle pelo buffer
c_CodControle : in regflit; -- codigo de controle do pacote de controle (terceiro flit do pacote de controle)
c_BuffCtrl : in buffControl; -- linha correspondente a tabela de roteamento lido do pacote de controle que sera escrita na tabela
c_buffTabelaFalhas_in: in row_FaultTable_Nport_Ports;
c_ce : in std_logic; -- chip enable da tabela de roteamento. Indica que sera escrito na tabela de roteamento
c_ceTF_in : in regNport; -- ce (chip enable) para escrever/atualizar a tabela de falhas
c_error_dir: out regNport; -- indica qual direcao/porta de saida o pacote sera encaminhado
c_error_ArrayFind: out ArrayRouterControl; -- indica se terminou de achar uma porta de saida para o pacote conforme a tabela de roteamento
c_tabelaFalhas : out row_FaultTable_Ports; -- tabela de falhas atualizada/final
c_strLinkTst : in regNport; -- (start link test) indica que houve um pacote de controle do tipo TEST_LINKS para testar os links
c_faultTableFDM : in regNPort; -- tabela de falhas gerado pelo teste de links
sender : in regNport;
free : out regNport; -- portas de saida que estao livres
mux_in : out arrayNport_reg3;
mux_out : out arrayNport_reg3;
row_FaultTablePorts_in: in row_FaultTable_Ports; -- linhas a serem escritas na tabela (do FFPM)
write_FaultTable: in regHamm_Nport); -- sinal para indicar escrita na tabela (do FPPM)
end SwitchControl;
architecture RoutingTable of SwitchControl is
type state is (S0,S1,S2,S3,S4,S5);
signal ES, PES: state;
-- sinais do arbitro
signal ask: std_logic := '0';
signal sel,prox: integer range 0 to (NPORT-1) := 0;
signal incoming: reg3 := (others=> '0');
signal header : regflit := (others=> '0');
signal ready, enable : std_logic;
-- sinais do controle
signal indice_dir: integer range 0 to (NPORT-1) := 0;
signal auxfree: regNport := (others=> '0');
signal source: arrayNport_reg3 := (others=> (others=> '0'));
signal sender_ant: regNport := (others=> '0');
signal dir: std_logic_vector(NPORT-1 downto 0):= (others=> '0');
signal requests: regNport := (others=> '0');
-- sinais de controle da tabela
signal find: RouterControl;
signal ceTable: std_logic := '0';
-- sinais de controle de atualizacao da tabela de falhas
signal c_ceTF : std_logic := '0';
signal c_buffTabelaFalhas : row_FaultTable_Ports := (others=>(others=>'0'));
--sinais da Tabela de Falhas
signal tabelaDeFalhas : row_FaultTable_Ports := (others=>(others=>'0'));
signal c_checked: regNPort:= (others=>'0');
signal c_checkedArray: arrayRegNport :=(others=>(others=>'0'));
signal dirBuff : std_logic_vector(NPORT-1 downto 0):= (others=> '0');
signal strLinkTstAll : std_logic := '0';
signal ant_c_ceTF_in: regNPort:= (others=>'0');
signal selectedOutput : integer := 0;
signal isOutputSelected : std_logic;
begin
ask <= '1' when OR_REDUCTION(h) else '0';
incoming <= CONV_VECTOR(sel);
header <= data(to_integer(unsigned(incoming)));
RoundRobinArbiter : entity work.arbiter(RoundRobinArbiter)
generic map(size => requests'length)
port map(
requests => h,
enable => enable,
selectedOutput => prox,
isOutputSelected => ready
);
------------------------------------------------------------
--gravacao da tabela de falhas
------------------------------------------------------------
--registrador para tabela de falhas
process(reset,clock)
begin
if reset='1' then
tabelaDeFalhas <= (others=>(others=>'0'));
elsif clock'event and clock='0' then
ant_c_ceTF_in <= c_ceTF_in;
-- se receber um pacote de controle para escrever/atualizar a tabela, escreve na tabela conforme a tabela recebida no pacote
if c_ceTF='1' then
tabelaDeFalhas <= c_buffTabelaFalhas;
-- se tiver feito o teste dos links, atualiza a tabela de falha conforme o resultado do teste
elsif strLinkTstAll = '1' then
--tabelaDeFalhas <= c_faultTableFDM;
tabelaDeFalhas(EAST)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(EAST) & '0';
tabelaDeFalhas(WEST)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(WEST) & '0';
tabelaDeFalhas(NORTH)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(NORTH) & '0';
tabelaDeFalhas(SOUTH)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(SOUTH) & '0';
-- escrita na tabela de falhas pelo FPPM
elsif (unsigned(write_FaultTable) /= 0) then
-- escreve apenas se o sinal de escrit tiver ativo e se o sttus do link tiver uma severidade maior ou igual a contida na tabela
for i in 0 to HAMM_NPORT-1 loop
if (write_FaultTable(i) = '1' and row_FaultTablePorts_in(i)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) >= tabelaDeFalhas(i)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE)) then
tabelaDeFalhas(i) <= row_FaultTablePorts_in(i);
end if;
end loop;
end if;
end if;
end process;
-- '1' se em algum buffer houve o pedido de teste de link (por causa do pacote de controle do tipo TEST_LINKS)
strLinkTstAll <= '1' when OR_REDUCTION(c_strLinkTst) else '0';
-- "merge" das telas recebidas
process(c_ceTF_in)
variable achou: regHamm_Nport := (others=>'0');
begin
for i in 0 to NPORT-1 loop
if (ant_c_ceTF_in(i)='1' and c_ceTF_in(i)='0') then
achou := (others=>'0');
exit;
end if;
end loop;
-- pergunta para cada buffer quais que desejam escrever na tabela e, conforme os que desejam, copia as linhas da tabela do buffer que tiver como falha
for i in 0 to NPORT-1 loop
for j in 0 to HAMM_NPORT-1 loop
if (achou(j)='0' and c_ceTF_in(i)='1' and c_buffTabelaFalhas_in(i)(j)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) = "10") then
c_buffTabelaFalhas(j) <= c_buffTabelaFalhas_in(i)(j);
achou(j) := '1';
end if;
end loop;
end loop;
-- pergunta para cada buffer quais que desejam escrever na tabela e, conforme os que desejam, copia as linhas da tabela do buffer que tiver como tendencia de falha
for i in 0 to NPORT-1 loop
for j in 0 to HAMM_NPORT-1 loop
if (achou(j)='0' and c_ceTF_in(i)='1' and c_buffTabelaFalhas_in(i)(j)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) = "01") then
c_buffTabelaFalhas(j) <= c_buffTabelaFalhas_in(i)(j);
achou(j) := '1';
end if;
end loop;
end loop;
-- pergunta para cada buffer quais que desejam escrever na tabela e, conforme os que desejam, copia as linhas da tabela do buffer que tiver como sem falha
for i in 0 to NPORT-1 loop
for j in 0 to HAMM_NPORT-1 loop
if (achou(j)='0' and c_ceTF_in(i)='1' and c_buffTabelaFalhas_in(i)(j)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) = "00") then
c_buffTabelaFalhas(j) <= c_buffTabelaFalhas_in(i)(j);
achou(j) := '1';
end if;
end loop;
end loop;
end process;
-- '1' se em algum buffer tiver habilita o ce para escrever/atualizar a tabela de falhas
c_ceTF <= '1' when OR_REDUCTION(c_ceTF_in) else '0';
process(clock,reset)
begin
c_error_ArrayFind <= (others=>invalidRegion);
c_error_ArrayFind(sel) <= find;
end process;
c_error_dir <= dir;
c_tabelafalhas <= tabelaDeFalhas;
RoutingMechanism : entity work.routingMechanism
generic map(address => address)
port map(
clock => clock,
reset => reset,
buffCtrl => c_BuffCtrl, -- linha correspondente a tabela de roteamento lido do pacote de controle que sera escrita na tabela
ctrl=> c_Ctrl, -- indica se foi lido ou criado de um pacote de controle pelo buffer
operacao => c_CodControle, -- codigo de controle do pacote de controle (terceiro flit do pacote de controle)
ceT => c_ce, -- chip enable da tabela de roteamento. Indica que sera escrito na tabela de roteamento
oe => ceTable, -- usado para solicitar direcao/porta destino para a tabela de roteamento
dest => header, -- primeiro flit/header do pacote (contem o destino do pacote)
inputPort => sel, -- porta de entrada selecionada pelo arbitro para ser chaveada
outputPort => dir, -- indica qual porta de saida o pacote sera encaminhado
find => find -- indica se terminou de achar uma porta de saida para o pacote conforme a tabela de roteamento
);
FixedPriorityArbiter : entity work.arbiter(FixedPriorityArbiter)
generic map(size => requests'length)
port map(
requests => requests,
enable => '1',
isOutputSelected => isOutputSelected,
selectedOutput => selectedOutput
);
process(reset,clock)
begin
if reset='1' then
ES<=S0;
elsif clock'event and clock='1' then
ES<=PES;
end if;
end process;
process(ES, ask, find, isOutputSelected)
begin
case ES is
when S0 => PES <= S1;
when S1 =>
if ask='1' then
PES <= S2;
else
PES <= S1;
end if;
when S2 => PES <= S3;
when S3 =>
if(find = validRegion)then
if (isOutputSelected = '1') then
PES <= S4;
else
PES <= S1;
end if;
elsif(find = portError)then
PES <= S1;
else
PES <= S3;
end if;
when S4 => PES <= S5;
when S5 => PES <= S1;
end case;
end process;
------------------------------------------------------------------------------------------------------
-- executa as acoes correspondente ao estado atual da maquina de estados
------------------------------------------------------------------------------------------------------
process(clock)
begin
if clock'event and clock='1' then
case ES is
-- Zera variaveis
when S0 =>
ceTable <= '0';
sel <= 0;
ack_h <= (others => '0');
auxfree <= (others=> '1');
sender_ant <= (others=> '0');
mux_out <= (others=>(others=>'0'));
source <= (others=>(others=>'0'));
-- Chegou um header
when S1=>
enable <= ask;
ceTable <= '0';
ack_h <= (others => '0');
-- Seleciona quem tera direito a requisitar roteamento
when S2=>
sel <= prox;
enable <= not ready;
-- Aguarda resposta da Tabela
when S3 =>
if(find = validRegion and isOutputSelected = '1') then
indice_dir <= selectedOutput;
else
ceTable <= '1';
end if;
when S4 =>
source(to_integer(unsigned(incoming))) <= CONV_VECTOR(indice_dir);
mux_out(indice_dir) <= incoming;
auxfree(indice_dir) <= '0';
ack_h(sel) <= '1';
when others =>
ack_h(sel) <= '0';
ceTable <= '0';
end case;
sender_ant <= sender;
for i in EAST to LOCAL loop
if sender(i) = '0' and sender_ant(i) = '1' then
auxfree(to_integer(unsigned(source(i)))) <= '1';
end if;
end loop;
end if;
end process;
mux_in <= source;
free <= auxfree;
requests <= auxfree AND dir;
end RoutingTable;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.HammingPack16.all;
use work.NoCPackage.all;
entity SwitchControl is
generic(address : regflit := (others=>'0'));
port(
clock : in std_logic;
reset : in std_logic;
h : in regNport; -- solicitacoes de chaveamento
ack_h : out regNport; -- resposta para as solitacoes de chaveamento
data : in arrayNport_regflit; -- dado do buffer (contem o endereco destino)
c_ctrl : in std_logic; -- indica se foi lido ou criado de um pacote de controle pelo buffer
c_CodControle : in regflit; -- codigo de controle do pacote de controle (terceiro flit do pacote de controle)
c_BuffCtrl : in buffControl; -- linha correspondente a tabela de roteamento lido do pacote de controle que sera escrita na tabela
c_buffTabelaFalhas_in: in row_FaultTable_Nport_Ports;
c_ce : in std_logic; -- chip enable da tabela de roteamento. Indica que sera escrito na tabela de roteamento
c_ceTF_in : in regNport; -- ce (chip enable) para escrever/atualizar a tabela de falhas
c_error_dir: out regNport; -- indica qual direcao/porta de saida o pacote sera encaminhado
c_error_ArrayFind: out ArrayRouterControl; -- indica se terminou de achar uma porta de saida para o pacote conforme a tabela de roteamento
c_tabelaFalhas : out row_FaultTable_Ports; -- tabela de falhas atualizada/final
c_strLinkTst : in regNport; -- (start link test) indica que houve um pacote de controle do tipo TEST_LINKS para testar os links
c_faultTableFDM : in regNPort; -- tabela de falhas gerado pelo teste de links
sender : in regNport;
free : out regNport; -- portas de saida que estao livres
mux_in : out arrayNport_reg3;
mux_out : out arrayNport_reg3;
row_FaultTablePorts_in: in row_FaultTable_Ports; -- linhas a serem escritas na tabela (do FFPM)
write_FaultTable: in regHamm_Nport); -- sinal para indicar escrita na tabela (do FPPM)
end SwitchControl;
architecture RoutingTable of SwitchControl is
type state is (S0,S1,S2,S3,S4,S5);
signal ES, PES: state;
-- sinais do arbitro
signal ask: std_logic := '0';
signal sel,prox: integer range 0 to (NPORT-1) := 0;
signal incoming: reg3 := (others=> '0');
signal header : regflit := (others=> '0');
signal ready, enable : std_logic;
-- sinais do controle
signal indice_dir: integer range 0 to (NPORT-1) := 0;
signal auxfree: regNport := (others=> '0');
signal source: arrayNport_reg3 := (others=> (others=> '0'));
signal sender_ant: regNport := (others=> '0');
signal dir: std_logic_vector(NPORT-1 downto 0):= (others=> '0');
signal requests: regNport := (others=> '0');
-- sinais de controle da tabela
signal find: RouterControl;
signal ceTable: std_logic := '0';
-- sinais de controle de atualizacao da tabela de falhas
signal c_ceTF : std_logic := '0';
signal c_buffTabelaFalhas : row_FaultTable_Ports := (others=>(others=>'0'));
--sinais da Tabela de Falhas
signal tabelaDeFalhas : row_FaultTable_Ports := (others=>(others=>'0'));
signal c_checked: regNPort:= (others=>'0');
signal c_checkedArray: arrayRegNport :=(others=>(others=>'0'));
signal dirBuff : std_logic_vector(NPORT-1 downto 0):= (others=> '0');
signal strLinkTstAll : std_logic := '0';
signal ant_c_ceTF_in: regNPort:= (others=>'0');
signal selectedOutput : integer := 0;
signal isOutputSelected : std_logic;
begin
ask <= '1' when OR_REDUCTION(h) else '0';
incoming <= CONV_VECTOR(sel);
header <= data(to_integer(unsigned(incoming)));
RoundRobinArbiter : entity work.arbiter(RoundRobinArbiter)
generic map(size => requests'length)
port map(
requests => h,
enable => enable,
selectedOutput => prox,
isOutputSelected => ready
);
------------------------------------------------------------
--gravacao da tabela de falhas
------------------------------------------------------------
--registrador para tabela de falhas
process(reset,clock)
begin
if reset='1' then
tabelaDeFalhas <= (others=>(others=>'0'));
elsif clock'event and clock='0' then
ant_c_ceTF_in <= c_ceTF_in;
-- se receber um pacote de controle para escrever/atualizar a tabela, escreve na tabela conforme a tabela recebida no pacote
if c_ceTF='1' then
tabelaDeFalhas <= c_buffTabelaFalhas;
-- se tiver feito o teste dos links, atualiza a tabela de falha conforme o resultado do teste
elsif strLinkTstAll = '1' then
--tabelaDeFalhas <= c_faultTableFDM;
tabelaDeFalhas(EAST)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(EAST) & '0';
tabelaDeFalhas(WEST)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(WEST) & '0';
tabelaDeFalhas(NORTH)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(NORTH) & '0';
tabelaDeFalhas(SOUTH)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(SOUTH) & '0';
-- escrita na tabela de falhas pelo FPPM
elsif (unsigned(write_FaultTable) /= 0) then
-- escreve apenas se o sinal de escrit tiver ativo e se o sttus do link tiver uma severidade maior ou igual a contida na tabela
for i in 0 to HAMM_NPORT-1 loop
if (write_FaultTable(i) = '1' and row_FaultTablePorts_in(i)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) >= tabelaDeFalhas(i)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE)) then
tabelaDeFalhas(i) <= row_FaultTablePorts_in(i);
end if;
end loop;
end if;
end if;
end process;
-- '1' se em algum buffer houve o pedido de teste de link (por causa do pacote de controle do tipo TEST_LINKS)
strLinkTstAll <= '1' when OR_REDUCTION(c_strLinkTst) else '0';
-- "merge" das telas recebidas
process(c_ceTF_in)
variable achou: regHamm_Nport := (others=>'0');
begin
for i in 0 to NPORT-1 loop
if (ant_c_ceTF_in(i)='1' and c_ceTF_in(i)='0') then
achou := (others=>'0');
exit;
end if;
end loop;
-- pergunta para cada buffer quais que desejam escrever na tabela e, conforme os que desejam, copia as linhas da tabela do buffer que tiver como falha
for i in 0 to NPORT-1 loop
for j in 0 to HAMM_NPORT-1 loop
if (achou(j)='0' and c_ceTF_in(i)='1' and c_buffTabelaFalhas_in(i)(j)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) = "10") then
c_buffTabelaFalhas(j) <= c_buffTabelaFalhas_in(i)(j);
achou(j) := '1';
end if;
end loop;
end loop;
-- pergunta para cada buffer quais que desejam escrever na tabela e, conforme os que desejam, copia as linhas da tabela do buffer que tiver como tendencia de falha
for i in 0 to NPORT-1 loop
for j in 0 to HAMM_NPORT-1 loop
if (achou(j)='0' and c_ceTF_in(i)='1' and c_buffTabelaFalhas_in(i)(j)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) = "01") then
c_buffTabelaFalhas(j) <= c_buffTabelaFalhas_in(i)(j);
achou(j) := '1';
end if;
end loop;
end loop;
-- pergunta para cada buffer quais que desejam escrever na tabela e, conforme os que desejam, copia as linhas da tabela do buffer que tiver como sem falha
for i in 0 to NPORT-1 loop
for j in 0 to HAMM_NPORT-1 loop
if (achou(j)='0' and c_ceTF_in(i)='1' and c_buffTabelaFalhas_in(i)(j)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) = "00") then
c_buffTabelaFalhas(j) <= c_buffTabelaFalhas_in(i)(j);
achou(j) := '1';
end if;
end loop;
end loop;
end process;
-- '1' se em algum buffer tiver habilita o ce para escrever/atualizar a tabela de falhas
c_ceTF <= '1' when OR_REDUCTION(c_ceTF_in) else '0';
process(clock,reset)
begin
c_error_ArrayFind <= (others=>invalidRegion);
c_error_ArrayFind(sel) <= find;
end process;
c_error_dir <= dir;
c_tabelafalhas <= tabelaDeFalhas;
RoutingMechanism : entity work.routingMechanism
generic map(address => address)
port map(
clock => clock,
reset => reset,
buffCtrl => c_BuffCtrl, -- linha correspondente a tabela de roteamento lido do pacote de controle que sera escrita na tabela
ctrl=> c_Ctrl, -- indica se foi lido ou criado de um pacote de controle pelo buffer
operacao => c_CodControle, -- codigo de controle do pacote de controle (terceiro flit do pacote de controle)
ceT => c_ce, -- chip enable da tabela de roteamento. Indica que sera escrito na tabela de roteamento
oe => ceTable, -- usado para solicitar direcao/porta destino para a tabela de roteamento
dest => header, -- primeiro flit/header do pacote (contem o destino do pacote)
inputPort => sel, -- porta de entrada selecionada pelo arbitro para ser chaveada
outputPort => dir, -- indica qual porta de saida o pacote sera encaminhado
find => find -- indica se terminou de achar uma porta de saida para o pacote conforme a tabela de roteamento
);
FixedPriorityArbiter : entity work.arbiter(FixedPriorityArbiter)
generic map(size => requests'length)
port map(
requests => requests,
enable => '1',
isOutputSelected => isOutputSelected,
selectedOutput => selectedOutput
);
process(reset,clock)
begin
if reset='1' then
ES<=S0;
elsif clock'event and clock='1' then
ES<=PES;
end if;
end process;
process(ES, ask, find, isOutputSelected)
begin
case ES is
when S0 => PES <= S1;
when S1 =>
if ask='1' then
PES <= S2;
else
PES <= S1;
end if;
when S2 => PES <= S3;
when S3 =>
if(find = validRegion)then
if (isOutputSelected = '1') then
PES <= S4;
else
PES <= S1;
end if;
elsif(find = portError)then
PES <= S1;
else
PES <= S3;
end if;
when S4 => PES <= S5;
when S5 => PES <= S1;
end case;
end process;
------------------------------------------------------------------------------------------------------
-- executa as acoes correspondente ao estado atual da maquina de estados
------------------------------------------------------------------------------------------------------
process(clock)
begin
if clock'event and clock='1' then
case ES is
-- Zera variaveis
when S0 =>
ceTable <= '0';
sel <= 0;
ack_h <= (others => '0');
auxfree <= (others=> '1');
sender_ant <= (others=> '0');
mux_out <= (others=>(others=>'0'));
source <= (others=>(others=>'0'));
-- Chegou um header
when S1=>
enable <= ask;
ceTable <= '0';
ack_h <= (others => '0');
-- Seleciona quem tera direito a requisitar roteamento
when S2=>
sel <= prox;
enable <= not ready;
-- Aguarda resposta da Tabela
when S3 =>
if(find = validRegion and isOutputSelected = '1') then
indice_dir <= selectedOutput;
else
ceTable <= '1';
end if;
when S4 =>
source(to_integer(unsigned(incoming))) <= CONV_VECTOR(indice_dir);
mux_out(indice_dir) <= incoming;
auxfree(indice_dir) <= '0';
ack_h(sel) <= '1';
when others =>
ack_h(sel) <= '0';
ceTable <= '0';
end case;
sender_ant <= sender;
for i in EAST to LOCAL loop
if sender(i) = '0' and sender_ant(i) = '1' then
auxfree(to_integer(unsigned(source(i)))) <= '1';
end if;
end loop;
end if;
end process;
mux_in <= source;
free <= auxfree;
requests <= auxfree AND dir;
end RoutingTable;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
entity MMX_SUB_8b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of MMX_SUB_8b is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
REPORT "(IMS) MMX 8bis ADD RESSOURCE : ALLOCATION OK !";
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : STD_LOGIC_VECTOR(8 downto 0);
variable rTemp2 : STD_LOGIC_VECTOR(8 downto 0);
variable rTemp3 : STD_LOGIC_VECTOR(8 downto 0);
variable rTemp4 : STD_LOGIC_VECTOR(8 downto 0);
begin
rTemp1 := STD_LOGIC_VECTOR( SIGNED('0' & INPUT_1( 7 downto 0)) - SIGNED('0' & INPUT_2( 7 downto 0)) );
rTemp2 := STD_LOGIC_VECTOR( SIGNED('0' & INPUT_1(15 downto 8)) - SIGNED('0' & INPUT_2(15 downto 8)) );
rTemp3 := STD_LOGIC_VECTOR( SIGNED('0' & INPUT_1(23 downto 16)) - SIGNED('0' & INPUT_2(23 downto 16)) );
rTemp4 := STD_LOGIC_VECTOR( SIGNED('0' & INPUT_1(31 downto 24)) - SIGNED('0' & INPUT_2(31 downto 24)) );
if( rTemp1(8) = '1' ) then rTemp1(7 downto 0) := "00000000"; end if;
if( rTemp2(8) = '1' ) then rTemp2(7 downto 0) := "00000000"; end if;
if( rTemp3(8) = '1' ) then rTemp3(7 downto 0) := "00000000"; end if;
if( rTemp4(8) = '1' ) then rTemp4(7 downto 0) := "00000000"; end if;
OUTPUT_1 <= (rTemp4(7 downto 0) & rTemp3(7 downto 0) & rTemp2(7 downto 0) & rTemp1(7 downto 0));
end process;
-------------------------------------------------------------------------
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity test_bin2bcd is
port(
clk, reset: in std_logic;
switch: in std_logic_vector(3 downto 0);
led: out std_logic_vector(3 downto 0)
);
end test_bin2bcd;
architecture behaviour of test_bin2bcd is
constant NUMBER: integer := 65535;
signal binary: std_logic_vector(15 downto 0);
signal bcd0, bcd1, bcd2, bcd3, bcd4: std_logic_vector(3 downto 0);
begin
binary <= conv_std_logic_vector(NUMBER, 16);
converter:
entity work.bin2bcd(behaviour)
generic map(N_BIN => 16)
port map(
clk => clk, reset => reset,
binary_in => binary,
bcd0 => bcd0, bcd1 => bcd1,
bcd2 => bcd2, bcd3 => bcd3,
bcd4 => bcd4
);
with switch select
led <= bcd0 when "0000",
bcd1 when "0001",
bcd2 when "0010",
bcd3 when "0011",
bcd4 when others;
end behaviour; |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file addsb_11_0_a629aff4db5bb1c8.vhd when simulating
-- the core, addsb_11_0_a629aff4db5bb1c8. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY addsb_11_0_a629aff4db5bb1c8 IS
PORT (
a : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END addsb_11_0_a629aff4db5bb1c8;
ARCHITECTURE addsb_11_0_a629aff4db5bb1c8_a OF addsb_11_0_a629aff4db5bb1c8 IS
-- synthesis translate_off
COMPONENT wrapped_addsb_11_0_a629aff4db5bb1c8
PORT (
a : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_addsb_11_0_a629aff4db5bb1c8 USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral)
GENERIC MAP (
c_a_type => 1,
c_a_width => 12,
c_add_mode => 0,
c_ainit_val => "0",
c_b_constant => 0,
c_b_type => 1,
c_b_value => "000000000000",
c_b_width => 12,
c_borrow_low => 1,
c_bypass_low => 0,
c_ce_overrides_bypass => 1,
c_ce_overrides_sclr => 0,
c_has_bypass => 0,
c_has_c_in => 0,
c_has_c_out => 0,
c_has_ce => 0,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_implementation => 0,
c_latency => 0,
c_out_width => 12,
c_sclr_overrides_sset => 0,
c_sinit_val => "0",
c_verbosity => 0,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_addsb_11_0_a629aff4db5bb1c8
PORT MAP (
a => a,
b => b,
s => s
);
-- synthesis translate_on
END addsb_11_0_a629aff4db5bb1c8_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file addsb_11_0_c25f95ce6b0868c9.vhd when simulating
-- the core, addsb_11_0_c25f95ce6b0868c9. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY addsb_11_0_c25f95ce6b0868c9 IS
PORT (
a : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END addsb_11_0_c25f95ce6b0868c9;
ARCHITECTURE addsb_11_0_c25f95ce6b0868c9_a OF addsb_11_0_c25f95ce6b0868c9 IS
-- synthesis translate_off
COMPONENT wrapped_addsb_11_0_c25f95ce6b0868c9
PORT (
a : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_addsb_11_0_c25f95ce6b0868c9 USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral)
GENERIC MAP (
c_a_type => 1,
c_a_width => 11,
c_add_mode => 0,
c_ainit_val => "0",
c_b_constant => 0,
c_b_type => 1,
c_b_value => "00000000000",
c_b_width => 11,
c_borrow_low => 1,
c_bypass_low => 0,
c_ce_overrides_bypass => 1,
c_ce_overrides_sclr => 0,
c_has_bypass => 0,
c_has_c_in => 0,
c_has_c_out => 0,
c_has_ce => 0,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_implementation => 0,
c_latency => 0,
c_out_width => 11,
c_sclr_overrides_sset => 0,
c_sinit_val => "0",
c_verbosity => 0,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_addsb_11_0_c25f95ce6b0868c9
PORT MAP (
a => a,
b => b,
s => s
);
-- synthesis translate_on
END addsb_11_0_c25f95ce6b0868c9_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file bmg_62_2be284cffc9a51ef.vhd when simulating
-- the core, bmg_62_2be284cffc9a51ef. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY bmg_62_2be284cffc9a51ef IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END bmg_62_2be284cffc9a51ef;
ARCHITECTURE bmg_62_2be284cffc9a51ef_a OF bmg_62_2be284cffc9a51ef IS
-- synthesis translate_off
COMPONENT wrapped_bmg_62_2be284cffc9a51ef
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_bmg_62_2be284cffc9a51ef USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral)
GENERIC MAP (
c_addra_width => 11,
c_addrb_width => 11,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 1,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "bmg_62_2be284cffc9a51ef.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 2048,
c_read_depth_b => 2048,
c_read_width_a => 10,
c_read_width_b => 10,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 2048,
c_write_depth_b => 2048,
c_write_mode_a => "READ_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 10,
c_write_width_b => 10,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_bmg_62_2be284cffc9a51ef
PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END bmg_62_2be284cffc9a51ef_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file bmg_62_efdcd0e54d01b373.vhd when simulating
-- the core, bmg_62_efdcd0e54d01b373. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY bmg_62_efdcd0e54d01b373 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END bmg_62_efdcd0e54d01b373;
ARCHITECTURE bmg_62_efdcd0e54d01b373_a OF bmg_62_efdcd0e54d01b373 IS
-- synthesis translate_off
COMPONENT wrapped_bmg_62_efdcd0e54d01b373
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_bmg_62_efdcd0e54d01b373 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral)
GENERIC MAP (
c_addra_width => 8,
c_addrb_width => 8,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 1,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "bmg_62_efdcd0e54d01b373.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 255,
c_read_depth_b => 255,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 255,
c_write_depth_b => 255,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_bmg_62_efdcd0e54d01b373
PORT MAP (
clka => clka,
ena => ena,
addra => addra,
douta => douta
);
-- synthesis translate_on
END bmg_62_efdcd0e54d01b373_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cntr_11_0_3eb0c8dcd9c22b4d.vhd when simulating
-- the core, cntr_11_0_3eb0c8dcd9c22b4d. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cntr_11_0_3eb0c8dcd9c22b4d IS
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
sinit : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END cntr_11_0_3eb0c8dcd9c22b4d;
ARCHITECTURE cntr_11_0_3eb0c8dcd9c22b4d_a OF cntr_11_0_3eb0c8dcd9c22b4d IS
-- synthesis translate_off
COMPONENT wrapped_cntr_11_0_3eb0c8dcd9c22b4d
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
sinit : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cntr_11_0_3eb0c8dcd9c22b4d USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral)
GENERIC MAP (
c_ainit_val => "0",
c_ce_overrides_sync => 0,
c_count_by => "1",
c_count_mode => 0,
c_count_to => "1",
c_fb_latency => 0,
c_has_ce => 1,
c_has_load => 0,
c_has_sclr => 0,
c_has_sinit => 1,
c_has_sset => 0,
c_has_thresh0 => 0,
c_implementation => 0,
c_latency => 1,
c_load_low => 0,
c_restrict_count => 0,
c_sclr_overrides_sset => 1,
c_sinit_val => "0",
c_thresh0_value => "1",
c_verbosity => 0,
c_width => 12,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cntr_11_0_3eb0c8dcd9c22b4d
PORT MAP (
clk => clk,
ce => ce,
sinit => sinit,
q => q
);
-- synthesis translate_on
END cntr_11_0_3eb0c8dcd9c22b4d_a;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package conv_pkg is
constant simulating : boolean := false
-- synopsys translate_off
or true
-- synopsys translate_on
;
constant xlUnsigned : integer := 1;
constant xlSigned : integer := 2;
constant xlFloat : integer := 3;
constant xlWrap : integer := 1;
constant xlSaturate : integer := 2;
constant xlTruncate : integer := 1;
constant xlRound : integer := 2;
constant xlRoundBanker : integer := 3;
constant xlAddMode : integer := 1;
constant xlSubMode : integer := 2;
attribute black_box : boolean;
attribute syn_black_box : boolean;
attribute fpga_dont_touch: string;
attribute box_type : string;
attribute keep : string;
attribute syn_keep : boolean;
function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned;
function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector;
function std_logic_vector_to_signed(inp : std_logic_vector) return signed;
function signed_to_std_logic_vector(inp : signed) return std_logic_vector;
function unsigned_to_signed(inp : unsigned) return signed;
function signed_to_unsigned(inp : signed) return unsigned;
function pos(inp : std_logic_vector; arith : INTEGER) return boolean;
function all_same(inp: std_logic_vector) return boolean;
function all_zeros(inp: std_logic_vector) return boolean;
function is_point_five(inp: std_logic_vector) return boolean;
function all_ones(inp: std_logic_vector) return boolean;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector;
function cast (inp : std_logic_vector; old_bin_pt,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function shift_division_result(quotient, fraction: std_logic_vector;
fraction_width, shift_value, shift_dir: INTEGER)
return std_logic_vector;
function shift_op (inp: std_logic_vector;
result_width, shift_value, shift_dir: INTEGER)
return std_logic_vector;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned;
function s2s_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function u2s_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function s2u_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2u_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2v_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function s2v_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function max_signed(width : INTEGER) return std_logic_vector;
function min_signed(width : INTEGER) return std_logic_vector;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER) return std_logic_vector;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width, arith : integer)
return std_logic_vector;
function max(L, R: INTEGER) return INTEGER;
function min(L, R: INTEGER) return INTEGER;
function "="(left,right: STRING) return boolean;
function boolean_to_signed (inp : boolean; width: integer)
return signed;
function boolean_to_unsigned (inp : boolean; width: integer)
return unsigned;
function boolean_to_vector (inp : boolean)
return std_logic_vector;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector;
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector;
function hex_string_to_std_logic_vector (inp : string; width : integer)
return std_logic_vector;
function makeZeroBinStr (width : integer) return STRING;
function and_reduce(inp: std_logic_vector) return std_logic;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean;
function is_binary_string_undefined (inp : string)
return boolean;
function is_XorU(inp : std_logic_vector)
return boolean;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector;
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector;
constant display_precision : integer := 20;
function real_to_string (inp : real) return string;
function valid_bin_string(inp : string) return boolean;
function std_logic_vector_to_bin_string(inp : std_logic_vector) return string;
function std_logic_to_bin_string(inp : std_logic) return string;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string;
type stdlogic_to_char_t is array(std_logic) of character;
constant to_char : stdlogic_to_char_t := (
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-');
-- synopsys translate_on
end conv_pkg;
package body conv_pkg is
function std_logic_vector_to_unsigned(inp : std_logic_vector)
return unsigned
is
begin
return unsigned (inp);
end;
function unsigned_to_std_logic_vector(inp : unsigned)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function std_logic_vector_to_signed(inp : std_logic_vector)
return signed
is
begin
return signed (inp);
end;
function signed_to_std_logic_vector(inp : signed)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function unsigned_to_signed (inp : unsigned)
return signed
is
begin
return signed(std_logic_vector(inp));
end;
function signed_to_unsigned (inp : signed)
return unsigned
is
begin
return unsigned(std_logic_vector(inp));
end;
function pos(inp : std_logic_vector; arith : INTEGER)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
return true;
else
if vec(width-1) = '0' then
return true;
else
return false;
end if;
end if;
return true;
end;
function max_signed(width : INTEGER)
return std_logic_vector
is
variable ones : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
ones := (others => '1');
result(width-1) := '0';
result(width-2 downto 0) := ones;
return result;
end;
function min_signed(width : INTEGER)
return std_logic_vector
is
variable zeros : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
zeros := (others => '0');
result(width-1) := '1';
result(width-2 downto 0) := zeros;
return result;
end;
function and_reduce(inp: std_logic_vector) return std_logic
is
variable result: std_logic;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := vec(0);
if width > 1 then
for i in 1 to width-1 loop
result := result and vec(i);
end loop;
end if;
return result;
end;
function all_same(inp: std_logic_vector) return boolean
is
variable result: boolean;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := true;
if width > 0 then
for i in 1 to width-1 loop
if vec(i) /= vec(0) then
result := false;
end if;
end loop;
end if;
return result;
end;
function all_zeros(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable zero : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
zero := (others => '0');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then
result := true;
else
result := false;
end if;
return result;
end;
function is_point_five(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (width > 1) then
if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then
result := true;
else
result := false;
end if;
else
if (vec(width-1) = '1') then
result := true;
else
result := false;
end if;
end if;
return result;
end;
function all_ones(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable one : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
one := (others => '1');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then
result := true;
else
result := false;
end if;
return result;
end;
function full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return integer
is
variable result : integer;
begin
result := old_width + 2;
return result;
end;
function quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return integer
is
variable right_of_dp, left_of_dp, result : integer;
begin
right_of_dp := max(new_bin_pt, old_bin_pt);
left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt));
result := (old_width + 2) + (new_bin_pt - old_bin_pt);
return result;
end;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector
is
constant fp_width : integer :=
full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith, new_width,
new_bin_pt, new_arith);
constant fp_bin_pt : integer := old_bin_pt;
constant fp_arith : integer := old_arith;
variable full_precision_result : std_logic_vector(fp_width-1 downto 0);
constant q_width : integer :=
quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith);
constant q_bin_pt : integer := new_bin_pt;
constant q_arith : integer := old_arith;
variable quantized_result : std_logic_vector(q_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
result := (others => '0');
full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt,
fp_arith);
if (quantization = xlRound) then
quantized_result := round_towards_inf(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
elsif (quantization = xlRoundBanker) then
quantized_result := round_towards_even(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
else
quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt, q_arith);
end if;
if (overflow = xlSaturate) then
result := saturation_arith(quantized_result, q_width, q_bin_pt,
q_arith, new_width, new_bin_pt, new_arith);
else
result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith,
new_width, new_bin_pt, new_arith);
end if;
return result;
end;
function cast (inp : std_logic_vector; old_bin_pt, new_width,
new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
constant left_of_dp : integer := (new_width - new_bin_pt)
- (old_width - old_bin_pt);
constant right_of_dp : integer := (new_bin_pt - old_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable j : integer;
begin
vec := inp;
for i in new_width-1 downto 0 loop
j := i - right_of_dp;
if ( j > old_width-1) then
if (new_arith = xlUnsigned) then
result(i) := '0';
else
result(i) := vec(old_width-1);
end if;
elsif ( j >= 0) then
result(i) := vec(j);
else
result(i) := '0';
end if;
end loop;
return result;
end;
function shift_division_result(quotient, fraction: std_logic_vector;
fraction_width, shift_value, shift_dir: INTEGER)
return std_logic_vector
is
constant q_width : integer := quotient'length;
constant f_width : integer := fraction'length;
constant vec_MSB : integer := q_width+f_width-1;
constant result_MSB : integer := q_width+fraction_width-1;
constant result_LSB : integer := vec_MSB-result_MSB;
variable vec : std_logic_vector(vec_MSB downto 0);
variable result : std_logic_vector(result_MSB downto 0);
begin
vec := ( quotient & fraction );
if shift_dir = 1 then
for i in vec_MSB downto 0 loop
if (i < shift_value) then
vec(i) := '0';
else
vec(i) := vec(i-shift_value);
end if;
end loop;
else
for i in 0 to vec_MSB loop
if (i > vec_MSB-shift_value) then
vec(i) := vec(vec_MSB);
else
vec(i) := vec(i+shift_value);
end if;
end loop;
end if;
result := vec(vec_MSB downto result_LSB);
return result;
end;
function shift_op (inp: std_logic_vector;
result_width, shift_value, shift_dir: INTEGER)
return std_logic_vector
is
constant inp_width : integer := inp'length;
constant vec_MSB : integer := inp_width-1;
constant result_MSB : integer := result_width-1;
constant result_LSB : integer := vec_MSB-result_MSB;
variable vec : std_logic_vector(vec_MSB downto 0);
variable result : std_logic_vector(result_MSB downto 0);
begin
vec := inp;
if shift_dir = 1 then
for i in vec_MSB downto 0 loop
if (i < shift_value) then
vec(i) := '0';
else
vec(i) := vec(i-shift_value);
end if;
end loop;
else
for i in 0 to vec_MSB loop
if (i > vec_MSB-shift_value) then
vec(i) := vec(vec_MSB);
else
vec(i) := vec(i+shift_value);
end if;
end loop;
end if;
result := vec(vec_MSB downto result_LSB);
return result;
end;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector
is
begin
return inp(upper downto lower);
end;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function s2u_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function u2s_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2u_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2v_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned);
end;
function s2v_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned);
end;
function boolean_to_signed (inp : boolean; width : integer)
return signed
is
variable result : signed(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_unsigned (inp : boolean; width : integer)
return unsigned
is
variable result : unsigned(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_vector (inp : boolean)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result(0) := inp;
return result;
end;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
result := zero_ext(vec(old_width-1 downto right_of_dp), new_width);
else
result := sign_ext(vec(old_width-1 downto right_of_dp), new_width);
end if;
else
if new_arith = xlUnsigned then
result := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
result := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
return result;
end;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (new_arith = xlSigned) then
if (vec(old_width-1) = '0') then
one_or_zero(0) := '1';
end if;
if (right_of_dp >= 2) and (right_of_dp <= old_width) then
if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then
one_or_zero(0) := '1';
end if;
end if;
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if vec(right_of_dp-1) = '0' then
one_or_zero(0) := '0';
end if;
else
one_or_zero(0) := '0';
end if;
else
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
one_or_zero(0) := vec(right_of_dp-1);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then
one_or_zero(0) := vec(right_of_dp-1);
else
one_or_zero(0) := vec(right_of_dp);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant left_of_dp : integer := (old_width - old_bin_pt) -
(new_width - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable overflow : boolean;
begin
vec := inp;
overflow := true;
result := (others => '0');
if (new_width >= old_width) then
overflow := false;
end if;
if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if (old_arith = xlSigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
if (vec(new_width-1) = '0') then
overflow := false;
end if;
end if;
end if;
end if;
if (old_arith = xlUnsigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
overflow := false;
end if;
end if;
end if;
if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if overflow then
if new_arith = xlSigned then
if vec(old_width-1) = '0' then
result := max_signed(new_width);
else
result := min_signed(new_width);
end if;
else
if ((old_arith = xlSigned) and vec(old_width-1) = '1') then
result := (others => '0');
else
result := (others => '1');
end if;
end if;
else
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
if (vec(old_width-1) = '1') then
vec := (others => '0');
end if;
end if;
if new_width <= old_width then
result := vec(new_width-1 downto 0);
else
if new_arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
end if;
end if;
return result;
end;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
variable result_arith : integer;
begin
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
result_arith := xlSigned;
end if;
result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith);
return result;
end;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is
begin
return max(a_bin_pt, b_bin_pt);
end;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER is
begin
return max(a_width - a_bin_pt, b_width - b_bin_pt);
end;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
constant pad_pos : integer := new_width - orig_width - 1;
begin
vec := inp;
pos := new_width-1;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pad_pos >= 0 then
for i in pad_pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := vec(old_width-1);
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := '0';
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
begin
result(0) := inp;
for i in new_width-1 downto 1 loop
result(i) := '0';
end loop;
return result;
end;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
return result;
end;
function pad_LSB(inp : std_logic_vector; new_width, arith: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
begin
vec := inp;
pos := new_width-1;
if (arith = xlUnsigned) then
result(pos) := '0';
pos := pos - 1;
else
result(pos) := vec(orig_width-1);
pos := pos - 1;
end if;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pos >= 0 then
for i in pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector
is
variable vec : std_logic_vector(old_width-1 downto 0);
variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if delta > 0 then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
function "="(left,right: STRING) return boolean is
begin
if (left'length /= right'length) then
return false;
else
test : for i in 1 to left'length loop
if left(i) /= right(i) then
return false;
end if;
end loop test;
return true;
end if;
end;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'X' ) then
result := true;
end if;
end loop;
return result;
end;
function is_binary_string_undefined (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'U' ) then
result := true;
end if;
end loop;
return result;
end;
function is_XorU(inp : std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 0 to width-1 loop
if (vec(i) = 'U') or (vec(i) = 'X') then
result := true;
end if;
end loop;
return result;
end;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real
is
variable vec : std_logic_vector(inp'length-1 downto 0);
variable result, shift_val, undefined_real : real;
variable neg_num : boolean;
begin
vec := inp;
result := 0.0;
neg_num := false;
if vec(inp'length-1) = '1' then
neg_num := true;
end if;
for i in 0 to inp'length-1 loop
if vec(i) = 'U' or vec(i) = 'X' then
return undefined_real;
end if;
if arith = xlSigned then
if neg_num then
if vec(i) = '0' then
result := result + 2.0**i;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
end loop;
if arith = xlSigned then
if neg_num then
result := result + 1.0;
result := result * (-1.0);
end if;
end if;
shift_val := 2.0**(-1*bin_pt);
result := result * shift_val;
return result;
end;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real
is
variable result : real := 0.0;
begin
if inp = '1' then
result := 1.0;
end if;
if arith = xlSigned then
assert false
report "It doesn't make sense to convert a 1 bit number to a signed real.";
end if;
return result;
end;
-- synopsys translate_on
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
begin
if (arith = xlSigned) then
signed_val := to_signed(inp, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(inp, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer
is
constant width : integer := inp'length;
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
variable result : integer;
begin
if (arith = xlSigned) then
signed_val := std_logic_vector_to_signed(inp);
result := to_integer(signed_val);
else
unsigned_val := std_logic_vector_to_unsigned(inp);
result := to_integer(unsigned_val);
end if;
return result;
end;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer
is
begin
if inp = '1' then
return 1;
else
return 0;
end if;
end;
function makeZeroBinStr (width : integer) return STRING is
variable result : string(1 to width+3);
begin
result(1) := '0';
result(2) := 'b';
for i in 3 to width+2 loop
result(i) := '0';
end loop;
result(width+3) := '.';
return result;
end;
-- synopsys translate_off
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
begin
result := (others => '0');
return result;
end;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector
is
variable real_val : real;
variable int_val : integer;
variable result : std_logic_vector(width-1 downto 0) := (others => '0');
variable unsigned_val : unsigned(width-1 downto 0) := (others => '0');
variable signed_val : signed(width-1 downto 0) := (others => '0');
begin
real_val := inp;
int_val := integer(real_val * 2.0**(bin_pt));
if (arith = xlSigned) then
signed_val := to_signed(int_val, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(int_val, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
-- synopsys translate_on
function valid_bin_string (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
begin
vec := inp;
if (vec(1) = '0' and vec(2) = 'b') then
return true;
else
return false;
end if;
end;
function hex_string_to_std_logic_vector(inp: string; width : integer)
return std_logic_vector is
constant strlen : integer := inp'LENGTH;
variable result : std_logic_vector(width-1 downto 0);
variable bitval : std_logic_vector((strlen*4)-1 downto 0);
variable posn : integer;
variable ch : character;
variable vec : string(1 to strlen);
begin
vec := inp;
result := (others => '0');
posn := (strlen*4)-1;
for i in 1 to strlen loop
ch := vec(i);
case ch is
when '0' => bitval(posn downto posn-3) := "0000";
when '1' => bitval(posn downto posn-3) := "0001";
when '2' => bitval(posn downto posn-3) := "0010";
when '3' => bitval(posn downto posn-3) := "0011";
when '4' => bitval(posn downto posn-3) := "0100";
when '5' => bitval(posn downto posn-3) := "0101";
when '6' => bitval(posn downto posn-3) := "0110";
when '7' => bitval(posn downto posn-3) := "0111";
when '8' => bitval(posn downto posn-3) := "1000";
when '9' => bitval(posn downto posn-3) := "1001";
when 'A' | 'a' => bitval(posn downto posn-3) := "1010";
when 'B' | 'b' => bitval(posn downto posn-3) := "1011";
when 'C' | 'c' => bitval(posn downto posn-3) := "1100";
when 'D' | 'd' => bitval(posn downto posn-3) := "1101";
when 'E' | 'e' => bitval(posn downto posn-3) := "1110";
when 'F' | 'f' => bitval(posn downto posn-3) := "1111";
when others => bitval(posn downto posn-3) := "XXXX";
-- synopsys translate_off
ASSERT false
REPORT "Invalid hex value" SEVERITY ERROR;
-- synopsys translate_on
end case;
posn := posn - 4;
end loop;
if (width <= strlen*4) then
result := bitval(width-1 downto 0);
else
result((strlen*4)-1 downto 0) := bitval;
end if;
return result;
end;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector
is
variable pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(inp'length-1 downto 0);
begin
vec := inp;
pos := inp'length-1;
result := (others => '0');
for i in 1 to vec'length loop
-- synopsys translate_off
if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then
assert false
report "Input string is larger than output std_logic_vector. Truncating output.";
return result;
end if;
-- synopsys translate_on
if vec(i) = '0' then
result(pos) := '0';
pos := pos - 1;
end if;
if vec(i) = '1' then
result(pos) := '1';
pos := pos - 1;
end if;
-- synopsys translate_off
if (vec(i) = 'X' or vec(i) = 'U') then
result(pos) := 'U';
pos := pos - 1;
end if;
-- synopsys translate_on
end loop;
return result;
end;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector
is
constant str_width : integer := width + 4;
constant inp_len : integer := inp'length;
constant num_elements : integer := (inp_len + 1)/str_width;
constant reverse_index : integer := (num_elements-1) - index;
variable left_pos : integer;
variable right_pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := (others => '0');
if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := 1;
right_pos := width + 3;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := (reverse_index * str_width) + 1;
right_pos := left_pos + width + 2;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
return result;
end;
-- synopsys translate_off
function std_logic_vector_to_bin_string(inp : std_logic_vector)
return string
is
variable vec : std_logic_vector(1 to inp'length);
variable result : string(vec'range);
begin
vec := inp;
for i in vec'range loop
result(i) := to_char(vec(i));
end loop;
return result;
end;
function std_logic_to_bin_string(inp : std_logic)
return string
is
variable result : string(1 to 3);
begin
result(1) := '0';
result(2) := 'b';
result(3) := to_char(inp);
return result;
end;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string
is
variable width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable str_pos : integer;
variable result : string(1 to width+3);
begin
vec := inp;
str_pos := 1;
result(str_pos) := '0';
str_pos := 2;
result(str_pos) := 'b';
str_pos := 3;
for i in width-1 downto 0 loop
if (((width+3) - bin_pt) = str_pos) then
result(str_pos) := '.';
str_pos := str_pos + 1;
end if;
result(str_pos) := to_char(vec(i));
str_pos := str_pos + 1;
end loop;
if (bin_pt = 0) then
result(str_pos) := '.';
end if;
return result;
end;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string
is
variable result : string(1 to width);
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := real_to_std_logic_vector(inp, width, bin_pt, arith);
result := std_logic_vector_to_bin_string(vec);
return result;
end;
function real_to_string (inp : real) return string
is
variable result : string(1 to display_precision) := (others => ' ');
begin
result(real'image(inp)'range) := real'image(inp);
return result;
end;
-- synopsys translate_on
end conv_pkg;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity srl17e is
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end srl17e;
architecture structural of srl17e is
component SRL16E
port (D : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
attribute syn_black_box of SRL16E : component is true;
attribute fpga_dont_touch of SRL16E : component is "true";
component FDE
port(
Q : out STD_ULOGIC;
D : in STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC);
end component;
attribute syn_black_box of FDE : component is true;
attribute fpga_dont_touch of FDE : component is "true";
constant a : std_logic_vector(4 downto 0) :=
integer_to_std_logic_vector(latency-2,5,xlSigned);
signal d_delayed : std_logic_vector(width-1 downto 0);
signal srl16_out : std_logic_vector(width-1 downto 0);
begin
d_delayed <= d after 200 ps;
reg_array : for i in 0 to width-1 generate
srl16_used: if latency > 1 generate
u1 : srl16e port map(clk => clk,
d => d_delayed(i),
q => srl16_out(i),
ce => ce,
a0 => a(0),
a1 => a(1),
a2 => a(2),
a3 => a(3));
end generate;
srl16_not_used: if latency <= 1 generate
srl16_out(i) <= d_delayed(i);
end generate;
fde_used: if latency /= 0 generate
u2 : fde port map(c => clk,
d => srl16_out(i),
q => q(i),
ce => ce);
end generate;
fde_not_used: if latency = 0 generate
q(i) <= srl16_out(i);
end generate;
end generate;
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg;
architecture structural of synth_reg is
component srl17e
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end component;
function calc_num_srl17es (latency : integer)
return integer
is
variable remaining_latency : integer;
variable result : integer;
begin
result := latency / 17;
remaining_latency := latency - (result * 17);
if (remaining_latency /= 0) then
result := result + 1;
end if;
return result;
end;
constant complete_num_srl17es : integer := latency / 17;
constant num_srl17es : integer := calc_num_srl17es(latency);
constant remaining_latency : integer := latency - (complete_num_srl17es * 17);
type register_array is array (num_srl17es downto 0) of
std_logic_vector(width-1 downto 0);
signal z : register_array;
begin
z(0) <= i;
complete_ones : if complete_num_srl17es > 0 generate
srl17e_array: for i in 0 to complete_num_srl17es-1 generate
delay_comp : srl17e
generic map (width => width,
latency => 17)
port map (clk => clk,
ce => ce,
d => z(i),
q => z(i+1));
end generate;
end generate;
partial_one : if remaining_latency > 0 generate
last_srl17e : srl17e
generic map (width => width,
latency => remaining_latency)
port map (clk => clk,
ce => ce,
d => z(num_srl17es-1),
q => z(num_srl17es));
end generate;
o <= z(num_srl17es);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg_reg;
architecture behav of synth_reg_reg is
type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0);
signal reg_bank : reg_array_type := (others => (others => '0'));
signal reg_bank_in : reg_array_type := (others => (others => '0'));
attribute syn_allow_retiming : boolean;
attribute syn_srlstyle : string;
attribute syn_allow_retiming of reg_bank : signal is true;
attribute syn_allow_retiming of reg_bank_in : signal is true;
attribute syn_srlstyle of reg_bank : signal is "registers";
attribute syn_srlstyle of reg_bank_in : signal is "registers";
begin
latency_eq_0: if latency = 0 generate
o <= i;
end generate latency_eq_0;
latency_gt_0: if latency >= 1 generate
o <= reg_bank(latency-1);
reg_bank_in(0) <= i;
loop_gen: for idx in latency-2 downto 0 generate
reg_bank_in(idx+1) <= reg_bank(idx);
end generate loop_gen;
sync_loop: for sync_idx in latency-1 downto 0 generate
sync_proc: process (clk)
begin
if clk'event and clk = '1' then
if clr = '1' then
reg_bank_in <= (others => (others => '0'));
elsif ce = '1' then
reg_bank(sync_idx) <= reg_bank_in(sync_idx);
end if;
end if;
end process sync_proc;
end generate sync_loop;
end generate latency_gt_0;
end behav;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity single_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end single_reg_w_init;
architecture structural of single_reg_w_init is
function build_init_const(width: integer;
init_index: integer;
init_value: bit_vector)
return std_logic_vector
is
variable result: std_logic_vector(width - 1 downto 0);
begin
if init_index = 0 then
result := (others => '0');
elsif init_index = 1 then
result := (others => '0');
result(0) := '1';
else
result := to_stdlogicvector(init_value);
end if;
return result;
end;
component fdre
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
r: in std_ulogic
);
end component;
attribute syn_black_box of fdre: component is true;
attribute fpga_dont_touch of fdre: component is "true";
component fdse
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
s: in std_ulogic
);
end component;
attribute syn_black_box of fdse: component is true;
attribute fpga_dont_touch of fdse: component is "true";
constant init_const: std_logic_vector(width - 1 downto 0)
:= build_init_const(width, init_index, init_value);
begin
fd_prim_array: for index in 0 to width - 1 generate
bit_is_0: if (init_const(index) = '0') generate
fdre_comp: fdre
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
r => clr
);
end generate;
bit_is_1: if (init_const(index) = '1') generate
fdse_comp: fdse
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
s => clr
);
end generate;
end generate;
end architecture structural;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000";
latency: integer := 1
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end synth_reg_w_init;
architecture structural of synth_reg_w_init is
component single_reg_w_init
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0);
signal dly_clr: std_logic;
begin
latency_eq_0: if (latency = 0) generate
o <= i;
end generate;
latency_gt_0: if (latency >= 1) generate
dly_i((latency + 1) * width - 1 downto latency * width) <= i
after 200 ps;
dly_clr <= clr after 200 ps;
fd_array: for index in latency downto 1 generate
reg_comp: single_reg_w_init
generic map (
width => width,
init_index => init_index,
init_value => init_value
)
port map (
clk => clk,
i => dly_i((index + 1) * width - 1 downto index * width),
o => dly_i(index * width - 1 downto (index - 1) * width),
ce => ce,
clr => dly_clr
);
end generate;
o <= dly_i(width - 1 downto 0);
end generate;
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_963ed6358a is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_963ed6358a;
architecture behavior of constant_963ed6358a is
begin
op <= "0";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_f4d0462e0e is
port (
plbrst : in std_logic_vector((1 - 1) downto 0);
plbabus : in std_logic_vector((32 - 1) downto 0);
plbpavalid : in std_logic_vector((1 - 1) downto 0);
plbrnw : in std_logic_vector((1 - 1) downto 0);
plbwrdbus : in std_logic_vector((32 - 1) downto 0);
rddata : in std_logic_vector((32 - 1) downto 0);
addrpref : in std_logic_vector((20 - 1) downto 0);
wrdbusreg : out std_logic_vector((32 - 1) downto 0);
addrack : out std_logic_vector((1 - 1) downto 0);
rdcomp : out std_logic_vector((1 - 1) downto 0);
wrdack : out std_logic_vector((1 - 1) downto 0);
bankaddr : out std_logic_vector((2 - 1) downto 0);
rnwreg : out std_logic_vector((1 - 1) downto 0);
rddack : out std_logic_vector((1 - 1) downto 0);
rddbus : out std_logic_vector((32 - 1) downto 0);
linearaddr : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_f4d0462e0e;
architecture behavior of mcode_block_f4d0462e0e is
signal plbrst_1_110: unsigned((1 - 1) downto 0);
signal plbabus_1_118: unsigned((32 - 1) downto 0);
signal plbpavalid_1_127: unsigned((1 - 1) downto 0);
signal plbrnw_1_139: unsigned((1 - 1) downto 0);
signal plbwrdbus_1_147: unsigned((32 - 1) downto 0);
signal rddata_1_158: unsigned((32 - 1) downto 0);
signal addrpref_1_166: unsigned((20 - 1) downto 0);
signal plbrstreg_12_24_next: boolean;
signal plbrstreg_12_24: boolean := false;
signal plbabusreg_13_25_next: unsigned((32 - 1) downto 0);
signal plbabusreg_13_25: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal plbpavalidreg_14_28_next: boolean;
signal plbpavalidreg_14_28: boolean := false;
signal plbrnwreg_15_24_next: unsigned((1 - 1) downto 0);
signal plbrnwreg_15_24: unsigned((1 - 1) downto 0) := "0";
signal plbwrdbusreg_16_27_next: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_16_27: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal avalidreg_28_23_next: boolean;
signal avalidreg_28_23: boolean := false;
signal ps1reg_39_20_next: boolean;
signal ps1reg_39_20: boolean := false;
signal psreg_47_19_next: boolean;
signal psreg_47_19: boolean := false;
type array_type_rdcompdelay_58_25 is array (0 to (3 - 1)) of unsigned((1 - 1) downto 0);
signal rdcompdelay_58_25: array_type_rdcompdelay_58_25 := (
"0",
"0",
"0");
signal rdcompdelay_58_25_front_din: unsigned((1 - 1) downto 0);
signal rdcompdelay_58_25_back: unsigned((1 - 1) downto 0);
signal rdcompdelay_58_25_push_front_pop_back_en: std_logic;
signal rdcompreg_62_23_next: unsigned((1 - 1) downto 0);
signal rdcompreg_62_23: unsigned((1 - 1) downto 0) := "0";
signal rddackreg_66_23_next: unsigned((1 - 1) downto 0);
signal rddackreg_66_23: unsigned((1 - 1) downto 0) := "0";
signal wrdackreg_70_23_next: unsigned((1 - 1) downto 0);
signal wrdackreg_70_23: unsigned((1 - 1) downto 0) := "0";
signal rddbusreg_84_23_next: unsigned((32 - 1) downto 0);
signal rddbusreg_84_23: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_20_1_slice: unsigned((2 - 1) downto 0);
signal linearaddr_21_1_slice: unsigned((8 - 1) downto 0);
signal addrpref_in_32_1_slice: unsigned((20 - 1) downto 0);
signal rel_33_4: boolean;
signal ps1_join_33_1: boolean;
signal ps_42_1_bit: boolean;
signal bitnot_49_49: boolean;
signal bitnot_49_73: boolean;
signal bit_49_49: boolean;
signal addrack_49_1_convert: unsigned((1 - 1) downto 0);
signal bit_55_43: unsigned((1 - 1) downto 0);
signal bitnot_72_35: unsigned((1 - 1) downto 0);
signal wrdackreg_72_1_bit: unsigned((1 - 1) downto 0);
signal rdsel_76_1_bit: unsigned((1 - 1) downto 0);
signal rel_78_4: boolean;
signal rddbus1_join_78_1: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_97_1_slice: unsigned((32 - 1) downto 0);
signal plbrstreg_12_24_next_x_000000: boolean;
signal plbpavalidreg_14_28_next_x_000000: boolean;
begin
plbrst_1_110 <= std_logic_vector_to_unsigned(plbrst);
plbabus_1_118 <= std_logic_vector_to_unsigned(plbabus);
plbpavalid_1_127 <= std_logic_vector_to_unsigned(plbpavalid);
plbrnw_1_139 <= std_logic_vector_to_unsigned(plbrnw);
plbwrdbus_1_147 <= std_logic_vector_to_unsigned(plbwrdbus);
rddata_1_158 <= std_logic_vector_to_unsigned(rddata);
addrpref_1_166 <= std_logic_vector_to_unsigned(addrpref);
proc_plbrstreg_12_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrstreg_12_24 <= plbrstreg_12_24_next;
end if;
end if;
end process proc_plbrstreg_12_24;
proc_plbabusreg_13_25: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbabusreg_13_25 <= plbabusreg_13_25_next;
end if;
end if;
end process proc_plbabusreg_13_25;
proc_plbpavalidreg_14_28: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbpavalidreg_14_28 <= plbpavalidreg_14_28_next;
end if;
end if;
end process proc_plbpavalidreg_14_28;
proc_plbrnwreg_15_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrnwreg_15_24 <= plbrnwreg_15_24_next;
end if;
end if;
end process proc_plbrnwreg_15_24;
proc_plbwrdbusreg_16_27: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbwrdbusreg_16_27 <= plbwrdbusreg_16_27_next;
end if;
end if;
end process proc_plbwrdbusreg_16_27;
proc_avalidreg_28_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
avalidreg_28_23 <= avalidreg_28_23_next;
end if;
end if;
end process proc_avalidreg_28_23;
proc_ps1reg_39_20: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
ps1reg_39_20 <= ps1reg_39_20_next;
end if;
end if;
end process proc_ps1reg_39_20;
proc_psreg_47_19: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
psreg_47_19 <= psreg_47_19_next;
end if;
end if;
end process proc_psreg_47_19;
rdcompdelay_58_25_back <= rdcompdelay_58_25(2);
proc_rdcompdelay_58_25: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (rdcompdelay_58_25_push_front_pop_back_en = '1')) then
for i in 2 downto 1 loop
rdcompdelay_58_25(i) <= rdcompdelay_58_25(i-1);
end loop;
rdcompdelay_58_25(0) <= rdcompdelay_58_25_front_din;
end if;
end if;
end process proc_rdcompdelay_58_25;
proc_rdcompreg_62_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rdcompreg_62_23 <= rdcompreg_62_23_next;
end if;
end if;
end process proc_rdcompreg_62_23;
proc_rddackreg_66_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddackreg_66_23 <= rddackreg_66_23_next;
end if;
end if;
end process proc_rddackreg_66_23;
proc_wrdackreg_70_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
wrdackreg_70_23 <= wrdackreg_70_23_next;
end if;
end if;
end process proc_wrdackreg_70_23;
proc_rddbusreg_84_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddbusreg_84_23 <= rddbusreg_84_23_next;
end if;
end if;
end process proc_rddbusreg_84_23;
bankaddr_20_1_slice <= u2u_slice(plbabusreg_13_25, 11, 10);
linearaddr_21_1_slice <= u2u_slice(plbabusreg_13_25, 9, 2);
addrpref_in_32_1_slice <= u2u_slice(plbabusreg_13_25, 31, 12);
rel_33_4 <= addrpref_in_32_1_slice = addrpref_1_166;
proc_if_33_1: process (rel_33_4)
is
begin
if rel_33_4 then
ps1_join_33_1 <= true;
else
ps1_join_33_1 <= false;
end if;
end process proc_if_33_1;
ps_42_1_bit <= ((boolean_to_vector(ps1_join_33_1) and boolean_to_vector(plbpavalidreg_14_28)) = "1");
bitnot_49_49 <= ((not boolean_to_vector(plbrstreg_12_24)) = "1");
bitnot_49_73 <= ((not boolean_to_vector(psreg_47_19)) = "1");
bit_49_49 <= ((boolean_to_vector(bitnot_49_49) and boolean_to_vector(ps_42_1_bit) and boolean_to_vector(bitnot_49_73)) = "1");
addrack_49_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(bit_49_49)), 0, 1, 0);
bit_55_43 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(plbrnwreg_15_24));
bitnot_72_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(plbrnwreg_15_24));
wrdackreg_72_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(bitnot_72_35));
rdsel_76_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rdcompdelay_58_25_back) or unsigned_to_std_logic_vector(rdcompreg_62_23));
rel_78_4 <= rdsel_76_1_bit = std_logic_vector_to_unsigned("1");
proc_if_78_1: process (rddata_1_158, rel_78_4)
is
begin
if rel_78_4 then
rddbus1_join_78_1 <= rddata_1_158;
else
rddbus1_join_78_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
end if;
end process proc_if_78_1;
plbwrdbusreg_97_1_slice <= u2u_slice(plbwrdbus_1_147, 31, 0);
plbrstreg_12_24_next_x_000000 <= (plbrst_1_110 /= "0");
plbrstreg_12_24_next <= plbrstreg_12_24_next_x_000000;
plbabusreg_13_25_next <= plbabus_1_118;
plbpavalidreg_14_28_next_x_000000 <= (plbpavalid_1_127 /= "0");
plbpavalidreg_14_28_next <= plbpavalidreg_14_28_next_x_000000;
plbrnwreg_15_24_next <= plbrnw_1_139;
plbwrdbusreg_16_27_next <= plbwrdbusreg_97_1_slice;
avalidreg_28_23_next <= plbpavalidreg_14_28;
ps1reg_39_20_next <= ps1_join_33_1;
psreg_47_19_next <= ps_42_1_bit;
rdcompdelay_58_25_front_din <= bit_55_43;
rdcompdelay_58_25_push_front_pop_back_en <= '1';
rdcompreg_62_23_next <= rdcompdelay_58_25_back;
rddackreg_66_23_next <= rdcompreg_62_23;
wrdackreg_70_23_next <= wrdackreg_72_1_bit;
rddbusreg_84_23_next <= rddbus1_join_78_1;
wrdbusreg <= unsigned_to_std_logic_vector(plbwrdbusreg_16_27);
addrack <= unsigned_to_std_logic_vector(addrack_49_1_convert);
rdcomp <= unsigned_to_std_logic_vector(rdcompreg_62_23);
wrdack <= unsigned_to_std_logic_vector(wrdackreg_70_23);
bankaddr <= unsigned_to_std_logic_vector(bankaddr_20_1_slice);
rnwreg <= unsigned_to_std_logic_vector(plbrnwreg_15_24);
rddack <= unsigned_to_std_logic_vector(rddackreg_66_23);
rddbus <= unsigned_to_std_logic_vector(rddbusreg_84_23);
linearaddr <= unsigned_to_std_logic_vector(linearaddr_21_1_slice);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_2c4e41848b is
port (
wrdbus : in std_logic_vector((32 - 1) downto 0);
bankaddr : in std_logic_vector((2 - 1) downto 0);
linearaddr : in std_logic_vector((8 - 1) downto 0);
rnwreg : in std_logic_vector((1 - 1) downto 0);
addrack : in std_logic_vector((1 - 1) downto 0);
sm_bayer_ctrl : in std_logic_vector((32 - 1) downto 0);
read_bank_out : out std_logic_vector((32 - 1) downto 0);
sm_bayer_ctrl_din : out std_logic_vector((32 - 1) downto 0);
sm_bayer_ctrl_en : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_2c4e41848b;
architecture behavior of mcode_block_2c4e41848b is
signal wrdbus_1_76: unsigned((32 - 1) downto 0);
signal bankaddr_1_84: unsigned((2 - 1) downto 0);
signal linearaddr_1_94: unsigned((8 - 1) downto 0);
signal rnwreg_1_106: unsigned((1 - 1) downto 0);
signal addrack_1_114: unsigned((1 - 1) downto 0);
signal sm_bayer_ctrl_1_123: unsigned((32 - 1) downto 0);
signal reg_bank_out_reg_19_30_next: unsigned((32 - 1) downto 0);
signal reg_bank_out_reg_19_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal read_bank_out_reg_72_31_next: unsigned((32 - 1) downto 0);
signal read_bank_out_reg_72_31: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_reg_75_26_next: unsigned((2 - 1) downto 0);
signal bankaddr_reg_75_26: unsigned((2 - 1) downto 0) := "00";
signal opcode_31_1_concat: unsigned((12 - 1) downto 0);
signal rel_52_4: boolean;
signal sm_bayer_ctrl_en_join_52_1: boolean;
signal slice_67_38: unsigned((32 - 1) downto 0);
signal rel_77_4: boolean;
signal rel_80_8: boolean;
signal rel_83_8: boolean;
signal rel_86_8: boolean;
signal read_bank_out_reg_join_77_1: unsigned((32 - 1) downto 0);
begin
wrdbus_1_76 <= std_logic_vector_to_unsigned(wrdbus);
bankaddr_1_84 <= std_logic_vector_to_unsigned(bankaddr);
linearaddr_1_94 <= std_logic_vector_to_unsigned(linearaddr);
rnwreg_1_106 <= std_logic_vector_to_unsigned(rnwreg);
addrack_1_114 <= std_logic_vector_to_unsigned(addrack);
sm_bayer_ctrl_1_123 <= std_logic_vector_to_unsigned(sm_bayer_ctrl);
proc_reg_bank_out_reg_19_30: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
reg_bank_out_reg_19_30 <= reg_bank_out_reg_19_30_next;
end if;
end if;
end process proc_reg_bank_out_reg_19_30;
proc_read_bank_out_reg_72_31: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
read_bank_out_reg_72_31 <= read_bank_out_reg_72_31_next;
end if;
end if;
end process proc_read_bank_out_reg_72_31;
proc_bankaddr_reg_75_26: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
bankaddr_reg_75_26 <= bankaddr_reg_75_26_next;
end if;
end if;
end process proc_bankaddr_reg_75_26;
opcode_31_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_114) & unsigned_to_std_logic_vector(rnwreg_1_106) & unsigned_to_std_logic_vector(bankaddr_1_84) & unsigned_to_std_logic_vector(linearaddr_1_94));
rel_52_4 <= opcode_31_1_concat = std_logic_vector_to_unsigned("101000000000");
proc_if_52_1: process (rel_52_4)
is
begin
if rel_52_4 then
sm_bayer_ctrl_en_join_52_1 <= true;
else
sm_bayer_ctrl_en_join_52_1 <= false;
end if;
end process proc_if_52_1;
slice_67_38 <= u2u_slice(wrdbus_1_76, 31, 0);
rel_77_4 <= bankaddr_reg_75_26 = std_logic_vector_to_unsigned("00");
rel_80_8 <= bankaddr_reg_75_26 = std_logic_vector_to_unsigned("01");
rel_83_8 <= bankaddr_reg_75_26 = std_logic_vector_to_unsigned("10");
rel_86_8 <= bankaddr_reg_75_26 = std_logic_vector_to_unsigned("11");
proc_if_77_1: process (read_bank_out_reg_72_31, reg_bank_out_reg_19_30, rel_77_4, rel_80_8, rel_83_8, rel_86_8)
is
begin
if rel_77_4 then
read_bank_out_reg_join_77_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
elsif rel_80_8 then
read_bank_out_reg_join_77_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
elsif rel_83_8 then
read_bank_out_reg_join_77_1 <= reg_bank_out_reg_19_30;
elsif rel_86_8 then
read_bank_out_reg_join_77_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
else
read_bank_out_reg_join_77_1 <= read_bank_out_reg_72_31;
end if;
end process proc_if_77_1;
reg_bank_out_reg_19_30_next <= sm_bayer_ctrl_1_123;
read_bank_out_reg_72_31_next <= read_bank_out_reg_join_77_1;
bankaddr_reg_75_26_next <= bankaddr_1_84;
read_bank_out <= unsigned_to_std_logic_vector(read_bank_out_reg_72_31);
sm_bayer_ctrl_din <= unsigned_to_std_logic_vector(slice_67_38);
sm_bayer_ctrl_en <= boolean_to_vector(sm_bayer_ctrl_en_join_52_1);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_1a0db76efe is
port (
sel : in std_logic_vector((2 - 1) downto 0);
d0 : in std_logic_vector((2 - 1) downto 0);
d1 : in std_logic_vector((2 - 1) downto 0);
d2 : in std_logic_vector((2 - 1) downto 0);
d3 : in std_logic_vector((2 - 1) downto 0);
y : out std_logic_vector((2 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_1a0db76efe;
architecture behavior of mux_1a0db76efe is
signal sel_1_20: std_logic_vector((2 - 1) downto 0);
signal d0_1_24: std_logic_vector((2 - 1) downto 0);
signal d1_1_27: std_logic_vector((2 - 1) downto 0);
signal d2_1_30: std_logic_vector((2 - 1) downto 0);
signal d3_1_33: std_logic_vector((2 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((2 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, sel_1_20)
is
begin
case sel_1_20 is
when "00" =>
unregy_join_6_1 <= d0_1_24;
when "01" =>
unregy_join_6_1 <= d1_1_27;
when "10" =>
unregy_join_6_1 <= d2_1_30;
when others =>
unregy_join_6_1 <= d3_1_33;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlslice is
generic (
new_msb : integer := 9;
new_lsb : integer := 1;
x_width : integer := 16;
y_width : integer := 8);
port (
x : in std_logic_vector (x_width-1 downto 0);
y : out std_logic_vector (y_width-1 downto 0));
end xlslice;
architecture behavior of xlslice is
begin
y <= x(new_msb downto new_lsb);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_5753e4c658 is
port (
d : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_5753e4c658;
architecture behavior of delay_5753e4c658 is
signal d_1_22: std_logic_vector((1 - 1) downto 0);
type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
0 => "0");
signal op_mem_20_24_front_din: std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
begin
d_1_22 <= d;
op_mem_20_24_back <= op_mem_20_24(0);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
op_mem_20_24_front_din <= d_1_22;
op_mem_20_24_push_front_pop_back_en <= '1';
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_a3ccf865c7 is
port (
d : in std_logic_vector((1 - 1) downto 0);
en : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_a3ccf865c7;
architecture behavior of delay_a3ccf865c7 is
signal d_1_22: std_logic_vector((1 - 1) downto 0);
signal en_1_25: std_logic;
type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
0 => "0");
signal op_mem_20_24_front_din: std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
signal op_mem_shift_join_27_9: std_logic_vector((1 - 1) downto 0);
signal op_mem_shift_join_27_9_en: std_logic;
begin
d_1_22 <= d;
en_1_25 <= en(0);
op_mem_20_24_back <= op_mem_20_24(0);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
proc_if_27_9: process (d_1_22, en_1_25)
is
begin
if en_1_25 = '1' then
op_mem_shift_join_27_9_en <= '1';
else
op_mem_shift_join_27_9_en <= '0';
end if;
op_mem_shift_join_27_9 <= d_1_22;
end process proc_if_27_9;
op_mem_20_24_front_din <= op_mem_shift_join_27_9;
op_mem_20_24_push_front_pop_back_en <= op_mem_shift_join_27_9_en;
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity expr_332f1d2335 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
dout : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end expr_332f1d2335;
architecture behavior of expr_332f1d2335 is
signal d0_1_24: unsigned((1 - 1) downto 0);
signal d1_1_28: unsigned((1 - 1) downto 0);
signal bitnot_5_36: unsigned((1 - 1) downto 0);
signal fulldout_5_2_bit: unsigned((1 - 1) downto 0);
begin
d0_1_24 <= std_logic_vector_to_unsigned(d0);
d1_1_28 <= std_logic_vector_to_unsigned(d1);
bitnot_5_36 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(d0_1_24));
fulldout_5_2_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(d1_1_28) and unsigned_to_std_logic_vector(bitnot_5_36));
dout <= unsigned_to_std_logic_vector(fulldout_5_2_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity expr_3c2515cf08 is
port (
a : in std_logic_vector((1 - 1) downto 0);
b : in std_logic_vector((1 - 1) downto 0);
dout : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end expr_3c2515cf08;
architecture behavior of expr_3c2515cf08 is
signal a_1_24: boolean;
signal b_1_27: boolean;
signal fulldout_5_2_bit: boolean;
begin
a_1_24 <= ((a) = "1");
b_1_27 <= ((b) = "1");
fulldout_5_2_bit <= ((boolean_to_vector(b_1_27) and boolean_to_vector(a_1_24)) = "1");
dout <= boolean_to_vector(fulldout_5_2_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_e5b38cca3b is
port (
ip : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end inverter_e5b38cca3b;
architecture behavior of inverter_e5b38cca3b is
signal ip_1_26: boolean;
type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean;
signal op_mem_22_20: array_type_op_mem_22_20 := (
0 => false);
signal op_mem_22_20_front_din: boolean;
signal op_mem_22_20_back: boolean;
signal op_mem_22_20_push_front_pop_back_en: std_logic;
signal internal_ip_12_1_bitnot: boolean;
begin
ip_1_26 <= ((ip) = "1");
op_mem_22_20_back <= op_mem_22_20(0);
proc_op_mem_22_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
op_mem_22_20(0) <= op_mem_22_20_front_din;
end if;
end if;
end process proc_op_mem_22_20;
internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1");
op_mem_22_20_push_front_pop_back_en <= '0';
op <= boolean_to_vector(internal_ip_12_1_bitnot);
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlcounter_free is
generic (
core_name0: string := "";
op_width: integer := 5;
op_arith: integer := xlSigned
);
port (
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
op: out std_logic_vector(op_width - 1 downto 0);
up: in std_logic_vector(0 downto 0) := (others => '0');
load: in std_logic_vector(0 downto 0) := (others => '0');
din: in std_logic_vector(op_width - 1 downto 0) := (others => '0');
en: in std_logic_vector(0 downto 0);
rst: in std_logic_vector(0 downto 0)
);
end xlcounter_free ;
architecture behavior of xlcounter_free is
component cntr_11_0_3eb0c8dcd9c22b4d
port (
clk: in std_logic;
ce: in std_logic;
SINIT: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of cntr_11_0_3eb0c8dcd9c22b4d:
component is true;
attribute fpga_dont_touch of cntr_11_0_3eb0c8dcd9c22b4d:
component is "true";
attribute box_type of cntr_11_0_3eb0c8dcd9c22b4d:
component is "black_box";
-- synopsys translate_off
constant zeroVec: std_logic_vector(op_width - 1 downto 0) := (others => '0');
constant oneVec: std_logic_vector(op_width - 1 downto 0) := (others => '1');
constant zeroStr: string(1 to op_width) :=
std_logic_vector_to_bin_string(zeroVec);
constant oneStr: string(1 to op_width) :=
std_logic_vector_to_bin_string(oneVec);
-- synopsys translate_on
signal core_sinit: std_logic;
signal core_ce: std_logic;
signal op_net: std_logic_vector(op_width - 1 downto 0);
begin
core_ce <= ce and en(0);
core_sinit <= (clr or rst(0)) and ce;
op <= op_net;
comp0: if ((core_name0 = "cntr_11_0_3eb0c8dcd9c22b4d")) generate
core_instance0: cntr_11_0_3eb0c8dcd9c22b4d
port map (
clk => clk,
ce => core_ce,
SINIT => core_sinit,
q => op_net
);
end generate;
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity convert_func_call is
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end convert_func_call;
architecture behavior of convert_func_call is
begin
result <= convert_type(din, din_width, din_bin_pt, din_arith,
dout_width, dout_bin_pt, dout_arith,
quantization, overflow);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlconvert is
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
en_width : integer := 1;
en_bin_pt : integer := 0;
en_arith : integer := xlUnsigned;
bool_conversion : integer :=0;
latency : integer := 0;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
en : in std_logic_vector (en_width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
dout : out std_logic_vector (dout_width-1 downto 0));
end xlconvert;
architecture behavior of xlconvert is
component synth_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
component convert_func_call
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end component;
-- synopsys translate_off
-- synopsys translate_on
signal result : std_logic_vector(dout_width-1 downto 0);
signal internal_ce : std_logic;
begin
-- synopsys translate_off
-- synopsys translate_on
internal_ce <= ce and en(0);
bool_conversion_generate : if (bool_conversion = 1)
generate
result <= din;
end generate;
std_conversion_generate : if (bool_conversion = 0)
generate
convert : convert_func_call
generic map (
din_width => din_width,
din_bin_pt => din_bin_pt,
din_arith => din_arith,
dout_width => dout_width,
dout_bin_pt => dout_bin_pt,
dout_arith => dout_arith,
quantization => quantization,
overflow => overflow)
port map (
din => din,
result => result);
end generate;
latency_test : if (latency > 0) generate
reg : synth_reg
generic map (
width => dout_width,
latency => latency
)
port map (
i => result,
ce => internal_ce,
clr => clr,
clk => clk,
o => dout
);
end generate;
latency0 : if (latency = 0)
generate
dout <= result;
end generate latency0;
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xladdsub is
generic (
core_name0: string := "";
a_width: integer := 16;
a_bin_pt: integer := 4;
a_arith: integer := xlUnsigned;
c_in_width: integer := 16;
c_in_bin_pt: integer := 4;
c_in_arith: integer := xlUnsigned;
c_out_width: integer := 16;
c_out_bin_pt: integer := 4;
c_out_arith: integer := xlUnsigned;
b_width: integer := 8;
b_bin_pt: integer := 2;
b_arith: integer := xlUnsigned;
s_width: integer := 17;
s_bin_pt: integer := 4;
s_arith: integer := xlUnsigned;
rst_width: integer := 1;
rst_bin_pt: integer := 0;
rst_arith: integer := xlUnsigned;
en_width: integer := 1;
en_bin_pt: integer := 0;
en_arith: integer := xlUnsigned;
full_s_width: integer := 17;
full_s_arith: integer := xlUnsigned;
mode: integer := xlAddMode;
extra_registers: integer := 0;
latency: integer := 0;
quantization: integer := xlTruncate;
overflow: integer := xlWrap;
c_latency: integer := 0;
c_output_width: integer := 17;
c_has_c_in : integer := 0;
c_has_c_out : integer := 0
);
port (
a: in std_logic_vector(a_width - 1 downto 0);
b: in std_logic_vector(b_width - 1 downto 0);
c_in : in std_logic_vector (0 downto 0) := "0";
ce: in std_logic;
clr: in std_logic := '0';
clk: in std_logic;
rst: in std_logic_vector(rst_width - 1 downto 0) := "0";
en: in std_logic_vector(en_width - 1 downto 0) := "1";
c_out : out std_logic_vector (0 downto 0);
s: out std_logic_vector(s_width - 1 downto 0)
);
end xladdsub;
architecture behavior of xladdsub is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function format_input(inp: std_logic_vector; old_width, delta, new_arith,
new_width: integer)
return std_logic_vector
is
variable vec: std_logic_vector(old_width-1 downto 0);
variable padded_inp: std_logic_vector((old_width + delta)-1 downto 0);
variable result: std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if (delta > 0) then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
constant full_s_bin_pt: integer := fractional_bits(a_bin_pt, b_bin_pt);
constant full_a_width: integer := full_s_width;
constant full_b_width: integer := full_s_width;
signal full_a: std_logic_vector(full_a_width - 1 downto 0);
signal full_b: std_logic_vector(full_b_width - 1 downto 0);
signal core_s: std_logic_vector(full_s_width - 1 downto 0);
signal conv_s: std_logic_vector(s_width - 1 downto 0);
signal temp_cout : std_logic;
signal internal_clr: std_logic;
signal internal_ce: std_logic;
signal extra_reg_ce: std_logic;
signal override: std_logic;
signal logic1: std_logic_vector(0 downto 0);
component addsb_11_0_c25f95ce6b0868c9
port (
a: in std_logic_vector(11 - 1 downto 0);
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(11 - 1 downto 0)
);
end component;
attribute syn_black_box of addsb_11_0_c25f95ce6b0868c9:
component is true;
attribute fpga_dont_touch of addsb_11_0_c25f95ce6b0868c9:
component is "true";
attribute box_type of addsb_11_0_c25f95ce6b0868c9:
component is "black_box";
component addsb_11_0_a629aff4db5bb1c8
port (
a: in std_logic_vector(12 - 1 downto 0);
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(12 - 1 downto 0)
);
end component;
attribute syn_black_box of addsb_11_0_a629aff4db5bb1c8:
component is true;
attribute fpga_dont_touch of addsb_11_0_a629aff4db5bb1c8:
component is "true";
attribute box_type of addsb_11_0_a629aff4db5bb1c8:
component is "black_box";
begin
internal_clr <= (clr or (rst(0))) and ce;
internal_ce <= ce and en(0);
logic1(0) <= '1';
addsub_process: process (a, b, core_s)
begin
full_a <= format_input (a, a_width, b_bin_pt - a_bin_pt, a_arith,
full_a_width);
full_b <= format_input (b, b_width, a_bin_pt - b_bin_pt, b_arith,
full_b_width);
conv_s <= convert_type (core_s, full_s_width, full_s_bin_pt, full_s_arith,
s_width, s_bin_pt, s_arith, quantization, overflow);
end process addsub_process;
comp0: if ((core_name0 = "addsb_11_0_c25f95ce6b0868c9")) generate
core_instance0: addsb_11_0_c25f95ce6b0868c9
port map (
a => full_a,
s => core_s,
b => full_b
);
end generate;
comp1: if ((core_name0 = "addsb_11_0_a629aff4db5bb1c8")) generate
core_instance1: addsb_11_0_a629aff4db5bb1c8
port map (
a => full_a,
s => core_s,
b => full_b
);
end generate;
latency_test: if (extra_registers > 0) generate
override_test: if (c_latency > 1) generate
override_pipe: synth_reg
generic map (
width => 1,
latency => c_latency
)
port map (
i => logic1,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o(0) => override);
extra_reg_ce <= ce and en(0) and override;
end generate override_test;
no_override: if ((c_latency = 0) or (c_latency = 1)) generate
extra_reg_ce <= ce and en(0);
end generate no_override;
extra_reg: synth_reg
generic map (
width => s_width,
latency => extra_registers
)
port map (
i => conv_s,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => s
);
cout_test: if (c_has_c_out = 1) generate
c_out_extra_reg: synth_reg
generic map (
width => 1,
latency => extra_registers
)
port map (
i(0) => temp_cout,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => c_out
);
end generate cout_test;
end generate;
latency_s: if ((latency = 0) or (extra_registers = 0)) generate
s <= conv_s;
end generate latency_s;
latency0: if (((latency = 0) or (extra_registers = 0)) and
(c_has_c_out = 1)) generate
c_out(0) <= temp_cout;
end generate latency0;
tie_dangling_cout: if (c_has_c_out = 0) generate
c_out <= "0";
end generate tie_dangling_cout;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_e6f5ee726b is
port (
in0 : in std_logic_vector((1 - 1) downto 0);
in1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((2 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_e6f5ee726b;
architecture behavior of concat_e6f5ee726b is
signal in0_1_23: unsigned((1 - 1) downto 0);
signal in1_1_27: unsigned((1 - 1) downto 0);
signal y_2_1_concat: unsigned((2 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_d0d1b9533e is
port (
in0 : in std_logic_vector((8 - 1) downto 0);
in1 : in std_logic_vector((8 - 1) downto 0);
in2 : in std_logic_vector((8 - 1) downto 0);
y : out std_logic_vector((24 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_d0d1b9533e;
architecture behavior of concat_d0d1b9533e is
signal in0_1_23: unsigned((8 - 1) downto 0);
signal in1_1_27: unsigned((8 - 1) downto 0);
signal in2_1_31: unsigned((8 - 1) downto 0);
signal y_2_1_concat: unsigned((24 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
in2_1_31 <= std_logic_vector_to_unsigned(in2);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_33cb3f7e58 is
port (
d : in std_logic_vector((10 - 1) downto 0);
en : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((10 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_33cb3f7e58;
architecture behavior of delay_33cb3f7e58 is
signal d_1_22: std_logic_vector((10 - 1) downto 0);
signal en_1_25: std_logic;
type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((10 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
0 => "0000000000");
signal op_mem_20_24_front_din: std_logic_vector((10 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((10 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
signal op_mem_shift_join_27_9: std_logic_vector((10 - 1) downto 0);
signal op_mem_shift_join_27_9_en: std_logic;
begin
d_1_22 <= d;
en_1_25 <= en(0);
op_mem_20_24_back <= op_mem_20_24(0);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
proc_if_27_9: process (d_1_22, en_1_25)
is
begin
if en_1_25 = '1' then
op_mem_shift_join_27_9_en <= '1';
else
op_mem_shift_join_27_9_en <= '0';
end if;
op_mem_shift_join_27_9 <= d_1_22;
end process proc_if_27_9;
op_mem_20_24_front_din <= op_mem_shift_join_27_9;
op_mem_20_24_push_front_pop_back_en <= op_mem_shift_join_27_9_en;
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_0025330cf4 is
port (
d : in std_logic_vector((2 - 1) downto 0);
en : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((2 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_0025330cf4;
architecture behavior of delay_0025330cf4 is
signal d_1_22: std_logic_vector((2 - 1) downto 0);
signal en_1_25: std_logic;
type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((2 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
0 => "00");
signal op_mem_20_24_front_din: std_logic_vector((2 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((2 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
signal op_mem_shift_join_27_9: std_logic_vector((2 - 1) downto 0);
signal op_mem_shift_join_27_9_en: std_logic;
begin
d_1_22 <= d;
en_1_25 <= en(0);
op_mem_20_24_back <= op_mem_20_24(0);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
proc_if_27_9: process (d_1_22, en_1_25)
is
begin
if en_1_25 = '1' then
op_mem_shift_join_27_9_en <= '1';
else
op_mem_shift_join_27_9_en <= '0';
end if;
op_mem_shift_join_27_9 <= d_1_22;
end process proc_if_27_9;
op_mem_20_24_front_din <= op_mem_shift_join_27_9;
op_mem_20_24_push_front_pop_back_en <= op_mem_shift_join_27_9_en;
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_ec78404abf is
port (
d : in std_logic_vector((12 - 1) downto 0);
en : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((12 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_ec78404abf;
architecture behavior of delay_ec78404abf is
signal d_1_22: std_logic_vector((12 - 1) downto 0);
signal en_1_25: std_logic;
type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((12 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
0 => "000000000000");
signal op_mem_20_24_front_din: std_logic_vector((12 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((12 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
signal op_mem_shift_join_27_9: std_logic_vector((12 - 1) downto 0);
signal op_mem_shift_join_27_9_en: std_logic;
begin
d_1_22 <= d;
en_1_25 <= en(0);
op_mem_20_24_back <= op_mem_20_24(0);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
proc_if_27_9: process (d_1_22, en_1_25)
is
begin
if en_1_25 = '1' then
op_mem_shift_join_27_9_en <= '1';
else
op_mem_shift_join_27_9_en <= '0';
end if;
op_mem_shift_join_27_9 <= d_1_22;
end process proc_if_27_9;
op_mem_20_24_front_din <= op_mem_shift_join_27_9;
op_mem_20_24_push_front_pop_back_en <= op_mem_shift_join_27_9_en;
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_0fbdd36101 is
port (
d : in std_logic_vector((10 - 1) downto 0);
en : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((10 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_0fbdd36101;
architecture behavior of delay_0fbdd36101 is
signal d_1_22: std_logic_vector((10 - 1) downto 0);
signal en_1_25: std_logic;
type array_type_op_mem_20_24 is array (0 to (2 - 1)) of std_logic_vector((10 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
"0000000000",
"0000000000");
signal op_mem_20_24_front_din: std_logic_vector((10 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((10 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
signal op_mem_shift_join_27_9: std_logic_vector((10 - 1) downto 0);
signal op_mem_shift_join_27_9_en: std_logic;
begin
d_1_22 <= d;
en_1_25 <= en(0);
op_mem_20_24_back <= op_mem_20_24(1);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
for i in 1 downto 1 loop
op_mem_20_24(i) <= op_mem_20_24(i-1);
end loop;
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
proc_if_27_9: process (d_1_22, en_1_25)
is
begin
if en_1_25 = '1' then
op_mem_shift_join_27_9_en <= '1';
else
op_mem_shift_join_27_9_en <= '0';
end if;
op_mem_shift_join_27_9 <= d_1_22;
end process proc_if_27_9;
op_mem_20_24_front_din <= op_mem_shift_join_27_9;
op_mem_20_24_push_front_pop_back_en <= op_mem_shift_join_27_9_en;
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_4fe5face7f is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((10 - 1) downto 0);
d1 : in std_logic_vector((10 - 1) downto 0);
y : out std_logic_vector((10 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_4fe5face7f;
architecture behavior of mux_4fe5face7f is
signal sel_1_20: std_logic_vector((1 - 1) downto 0);
signal d0_1_24: std_logic_vector((10 - 1) downto 0);
signal d1_1_27: std_logic_vector((10 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((10 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_1_20)
is
begin
case sel_1_20 is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_61418c8488 is
port (
sel : in std_logic_vector((2 - 1) downto 0);
d0 : in std_logic_vector((10 - 1) downto 0);
d1 : in std_logic_vector((10 - 1) downto 0);
d2 : in std_logic_vector((10 - 1) downto 0);
d3 : in std_logic_vector((10 - 1) downto 0);
y : out std_logic_vector((10 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_61418c8488;
architecture behavior of mux_61418c8488 is
signal sel_1_20: std_logic_vector((2 - 1) downto 0);
signal d0_1_24: std_logic_vector((10 - 1) downto 0);
signal d1_1_27: std_logic_vector((10 - 1) downto 0);
signal d2_1_30: std_logic_vector((10 - 1) downto 0);
signal d3_1_33: std_logic_vector((10 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((10 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, sel_1_20)
is
begin
case sel_1_20 is
when "00" =>
unregy_join_6_1 <= d0_1_24;
when "01" =>
unregy_join_6_1 <= d1_1_27;
when "10" =>
unregy_join_6_1 <= d2_1_30;
when others =>
unregy_join_6_1 <= d3_1_33;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity shift_d9577b2c80 is
port (
ip : in std_logic_vector((11 - 1) downto 0);
op : out std_logic_vector((12 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end shift_d9577b2c80;
architecture behavior of shift_d9577b2c80 is
signal ip_1_23: unsigned((11 - 1) downto 0);
type array_type_op_mem_46_20 is array (0 to (1 - 1)) of unsigned((12 - 1) downto 0);
signal op_mem_46_20: array_type_op_mem_46_20 := (
0 => "000000000000");
signal op_mem_46_20_front_din: unsigned((12 - 1) downto 0);
signal op_mem_46_20_back: unsigned((12 - 1) downto 0);
signal op_mem_46_20_push_front_pop_back_en: std_logic;
signal cast_internal_ip_25_3_lsh: unsigned((12 - 1) downto 0);
begin
ip_1_23 <= std_logic_vector_to_unsigned(ip);
op_mem_46_20_back <= op_mem_46_20(0);
proc_op_mem_46_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_46_20_push_front_pop_back_en = '1')) then
op_mem_46_20(0) <= op_mem_46_20_front_din;
end if;
end if;
end process proc_op_mem_46_20;
cast_internal_ip_25_3_lsh <= u2u_cast(ip_1_23, 0, 12, 1);
op_mem_46_20_push_front_pop_back_en <= '0';
op <= unsigned_to_std_logic_vector(cast_internal_ip_25_3_lsh);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity shift_0a73a8a346 is
port (
ip : in std_logic_vector((10 - 1) downto 0);
op : out std_logic_vector((12 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end shift_0a73a8a346;
architecture behavior of shift_0a73a8a346 is
signal ip_1_23: unsigned((10 - 1) downto 0);
type array_type_op_mem_46_20 is array (0 to (1 - 1)) of unsigned((12 - 1) downto 0);
signal op_mem_46_20: array_type_op_mem_46_20 := (
0 => "000000000000");
signal op_mem_46_20_front_din: unsigned((12 - 1) downto 0);
signal op_mem_46_20_back: unsigned((12 - 1) downto 0);
signal op_mem_46_20_push_front_pop_back_en: std_logic;
signal cast_internal_ip_25_3_lsh: unsigned((12 - 1) downto 0);
begin
ip_1_23 <= std_logic_vector_to_unsigned(ip);
op_mem_46_20_back <= op_mem_46_20(0);
proc_op_mem_46_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_46_20_push_front_pop_back_en = '1')) then
op_mem_46_20(0) <= op_mem_46_20_front_din;
end if;
end if;
end process proc_op_mem_46_20;
cast_internal_ip_25_3_lsh <= u2u_cast(ip_1_23, 0, 12, 2);
op_mem_46_20_push_front_pop_back_en <= '0';
op <= unsigned_to_std_logic_vector(cast_internal_ip_25_3_lsh);
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlspram is
generic (
core_name0: string := "";
c_width: integer := 12;
c_address_width: integer := 4;
latency: integer := 1
);
port (
data_in: in std_logic_vector(c_width - 1 downto 0);
addr: in std_logic_vector(c_address_width - 1 downto 0);
we: in std_logic_vector(0 downto 0);
en: in std_logic_vector(0 downto 0);
rst: in std_logic_vector(0 downto 0);
ce: in std_logic;
clk: in std_logic;
data_out: out std_logic_vector(c_width - 1 downto 0)
);
end xlspram ;
architecture behavior of xlspram is
component synth_reg
generic (
width: integer;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
signal core_data_out, dly_data_out: std_logic_vector(c_width - 1 downto 0);
signal core_we, core_ce, sinit: std_logic;
component bmg_62_2be284cffc9a51ef
port (
addra: in std_logic_vector(c_address_width - 1 downto 0);
clka: in std_logic;
dina: in std_logic_vector(c_width - 1 downto 0);
wea: in std_logic_vector(0 downto 0);
ena: in std_logic;
douta: out std_logic_vector(c_width - 1 downto 0)
);
end component;
attribute syn_black_box of bmg_62_2be284cffc9a51ef:
component is true;
attribute fpga_dont_touch of bmg_62_2be284cffc9a51ef:
component is "true";
attribute box_type of bmg_62_2be284cffc9a51ef:
component is "black_box";
begin
data_out <= dly_data_out;
core_we <= we(0);
core_ce <= ce and en(0);
sinit <= rst(0) and ce;
comp0: if ((core_name0 = "bmg_62_2be284cffc9a51ef")) generate
core_instance0: bmg_62_2be284cffc9a51ef
port map (
addra => addr,
clka => clk,
dina => data_in,
wea(0) => core_we,
ena => core_ce,
douta => core_data_out
);
end generate;
latency_test: if (latency > 1) generate
reg: synth_reg
generic map (
width => c_width,
latency => latency - 1
)
port map (
i => core_data_out,
ce => core_ce,
clr => '0',
clk => clk,
o => dly_data_out
);
end generate;
latency_1: if (latency <= 1) generate
dly_data_out <= core_data_out;
end generate;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_1b0d89c05a is
port (
d : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_1b0d89c05a;
architecture behavior of delay_1b0d89c05a is
signal d_1_22: std_logic_vector((1 - 1) downto 0);
type array_type_op_mem_20_24 is array (0 to (7 - 1)) of std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
"0",
"0",
"0",
"0",
"0",
"0",
"0");
signal op_mem_20_24_front_din: std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
begin
d_1_22 <= d;
op_mem_20_24_back <= op_mem_20_24(6);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
for i in 6 downto 1 loop
op_mem_20_24(i) <= op_mem_20_24(i-1);
end loop;
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
op_mem_20_24_front_din <= d_1_22;
op_mem_20_24_push_front_pop_back_en <= '1';
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_e1f6cb3ad9 is
port (
d : in std_logic_vector((24 - 1) downto 0);
q : out std_logic_vector((24 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_e1f6cb3ad9;
architecture behavior of delay_e1f6cb3ad9 is
signal d_1_22: std_logic_vector((24 - 1) downto 0);
type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((24 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
0 => "000000000000000000000000");
signal op_mem_20_24_front_din: std_logic_vector((24 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((24 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
begin
d_1_22 <= d;
op_mem_20_24_back <= op_mem_20_24(0);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
op_mem_20_24_front_din <= d_1_22;
op_mem_20_24_push_front_pop_back_en <= '1';
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_6293007044 is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_6293007044;
architecture behavior of constant_6293007044 is
begin
op <= "1";
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlsprom is
generic (
core_name0: string := "";
c_width: integer := 12;
c_address_width: integer := 4;
latency: integer := 1
);
port (
addr: in std_logic_vector(c_address_width - 1 downto 0);
en: in std_logic_vector(0 downto 0);
rst: in std_logic_vector(0 downto 0);
ce: in std_logic;
clk: in std_logic;
data: out std_logic_vector(c_width - 1 downto 0)
);
end xlsprom ;
architecture behavior of xlsprom is
component synth_reg
generic (
width: integer;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
signal core_addr: std_logic_vector(c_address_width - 1 downto 0);
signal core_data_out: std_logic_vector(c_width - 1 downto 0);
signal core_ce, sinit: std_logic;
component bmg_62_efdcd0e54d01b373
port (
addra: in std_logic_vector(c_address_width - 1 downto 0);
clka: in std_logic;
ena: in std_logic;
douta: out std_logic_vector(c_width - 1 downto 0)
);
end component;
attribute syn_black_box of bmg_62_efdcd0e54d01b373:
component is true;
attribute fpga_dont_touch of bmg_62_efdcd0e54d01b373:
component is "true";
attribute box_type of bmg_62_efdcd0e54d01b373:
component is "black_box";
begin
core_addr <= addr;
core_ce <= ce and en(0);
sinit <= rst(0) and ce;
comp0: if ((core_name0 = "bmg_62_efdcd0e54d01b373")) generate
core_instance0: bmg_62_efdcd0e54d01b373
port map (
addra => core_addr,
clka => clk,
ena => core_ce,
douta => core_data_out
);
end generate;
latency_test: if (latency > 1) generate
reg: synth_reg
generic map (
width => c_width,
latency => latency - 1
)
port map (
i => core_data_out,
ce => core_ce,
clr => '0',
clk => clk,
o => data
);
end generate;
latency_1: if (latency <= 1) generate
data <= core_data_out;
end generate;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_8712d31083 is
port (
in0 : in std_logic_vector((8 - 1) downto 0);
in1 : in std_logic_vector((2 - 1) downto 0);
y : out std_logic_vector((10 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_8712d31083;
architecture behavior of concat_8712d31083 is
signal in0_1_23: unsigned((8 - 1) downto 0);
signal in1_1_27: unsigned((2 - 1) downto 0);
signal y_2_1_concat: unsigned((10 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_cda50df78a is
port (
op : out std_logic_vector((2 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_cda50df78a;
architecture behavior of constant_cda50df78a is
begin
op <= "00";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_cfa_gamma/EDK Processor"
entity edk_processor_entity_33f025737d is
port (
plb_abus: in std_logic_vector(31 downto 0);
plb_ce_1: in std_logic;
plb_clk_1: in std_logic;
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
to_register: in std_logic_vector(31 downto 0);
constant5_x0: out std_logic;
plb_decode_x0: out std_logic;
plb_decode_x1: out std_logic;
plb_decode_x2: out std_logic;
plb_decode_x3: out std_logic;
plb_decode_x4: out std_logic_vector(31 downto 0);
plb_memmap_x0: out std_logic_vector(31 downto 0);
plb_memmap_x1: out std_logic
);
end edk_processor_entity_33f025737d;
architecture structural of edk_processor_entity_33f025737d is
signal bankaddr: std_logic_vector(1 downto 0);
signal bayer_ctrl_din_x0: std_logic_vector(31 downto 0);
signal bayer_ctrl_dout_x0: std_logic_vector(31 downto 0);
signal bayer_ctrl_en_x0: std_logic;
signal linearaddr: std_logic_vector(7 downto 0);
signal plb_abus_net_x0: std_logic_vector(31 downto 0);
signal plb_ce_1_sg_x0: std_logic;
signal plb_clk_1_sg_x0: std_logic;
signal plb_pavalid_net_x0: std_logic;
signal plb_rnw_net_x0: std_logic;
signal plb_wrdbus_net_x0: std_logic_vector(31 downto 0);
signal rddata: std_logic_vector(31 downto 0);
signal rnwreg: std_logic;
signal sg_plb_addrpref_net_x0: std_logic_vector(19 downto 0);
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_rddbus_x0: std_logic_vector(31 downto 0);
signal sl_wait_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_net_x0: std_logic;
signal wrdbusreg: std_logic_vector(31 downto 0);
begin
plb_abus_net_x0 <= plb_abus;
plb_ce_1_sg_x0 <= plb_ce_1;
plb_clk_1_sg_x0 <= plb_clk_1;
plb_pavalid_net_x0 <= plb_pavalid;
plb_rnw_net_x0 <= plb_rnw;
plb_wrdbus_net_x0 <= plb_wrdbus;
sg_plb_addrpref_net_x0 <= sg_plb_addrpref;
splb_rst_net_x0 <= splb_rst;
bayer_ctrl_dout_x0 <= to_register;
constant5_x0 <= sl_wait_x0;
plb_decode_x0 <= sl_addrack_x0;
plb_decode_x1 <= sl_rdcomp_x0;
plb_decode_x2 <= sl_wrdack_x0;
plb_decode_x3 <= sl_rddack_x0;
plb_decode_x4 <= sl_rddbus_x0;
plb_memmap_x0 <= bayer_ctrl_din_x0;
plb_memmap_x1 <= bayer_ctrl_en_x0;
constant5: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => sl_wait_x0
);
plb_decode: entity work.mcode_block_f4d0462e0e
port map (
addrpref => sg_plb_addrpref_net_x0,
ce => plb_ce_1_sg_x0,
clk => plb_clk_1_sg_x0,
clr => '0',
plbabus => plb_abus_net_x0,
plbpavalid(0) => plb_pavalid_net_x0,
plbrnw(0) => plb_rnw_net_x0,
plbrst(0) => splb_rst_net_x0,
plbwrdbus => plb_wrdbus_net_x0,
rddata => rddata,
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
linearaddr => linearaddr,
rdcomp(0) => sl_rdcomp_x0,
rddack(0) => sl_rddack_x0,
rddbus => sl_rddbus_x0,
rnwreg(0) => rnwreg,
wrdack(0) => sl_wrdack_x0,
wrdbusreg => wrdbusreg
);
plb_memmap: entity work.mcode_block_2c4e41848b
port map (
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
ce => plb_ce_1_sg_x0,
clk => plb_clk_1_sg_x0,
clr => '0',
linearaddr => linearaddr,
rnwreg(0) => rnwreg,
sm_bayer_ctrl => bayer_ctrl_dout_x0,
wrdbus => wrdbusreg,
read_bank_out => rddata,
sm_bayer_ctrl_din => bayer_ctrl_din_x0,
sm_bayer_ctrl_en(0) => bayer_ctrl_en_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_cfa_gamma/bayer/Subsystem"
entity subsystem_entity_387011edf3 is
port (
from_register: in std_logic_vector(31 downto 0);
pos: in std_logic_vector(1 downto 0);
bsel: out std_logic_vector(1 downto 0);
gsel: out std_logic;
rsel: out std_logic_vector(1 downto 0)
);
end subsystem_entity_387011edf3;
architecture structural of subsystem_entity_387011edf3 is
signal delay15_q_net_x0: std_logic_vector(1 downto 0);
signal from_register_data_out_net_x0: std_logic_vector(31 downto 0);
signal mux7_y_net_x0: std_logic_vector(1 downto 0);
signal mux8_y_net: std_logic_vector(1 downto 0);
signal mux9_y_net_x0: std_logic_vector(1 downto 0);
signal slice10_y_net: std_logic_vector(1 downto 0);
signal slice11_y_net: std_logic_vector(1 downto 0);
signal slice12_y_net: std_logic_vector(1 downto 0);
signal slice13_y_net: std_logic_vector(1 downto 0);
signal slice14_y_net: std_logic_vector(1 downto 0);
signal slice17_y_net_x0: std_logic;
signal slice3_y_net: std_logic_vector(1 downto 0);
signal slice4_y_net: std_logic_vector(1 downto 0);
signal slice5_y_net: std_logic_vector(1 downto 0);
signal slice6_y_net: std_logic_vector(1 downto 0);
signal slice7_y_net: std_logic_vector(1 downto 0);
signal slice8_y_net: std_logic_vector(1 downto 0);
signal slice9_y_net: std_logic_vector(1 downto 0);
begin
from_register_data_out_net_x0 <= from_register;
delay15_q_net_x0 <= pos;
bsel <= mux9_y_net_x0;
gsel <= slice17_y_net_x0;
rsel <= mux7_y_net_x0;
mux7: entity work.mux_1a0db76efe
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => slice5_y_net,
d1 => slice4_y_net,
d2 => slice3_y_net,
d3 => slice6_y_net,
sel => delay15_q_net_x0,
y => mux7_y_net_x0
);
mux8: entity work.mux_1a0db76efe
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => slice9_y_net,
d1 => slice8_y_net,
d2 => slice7_y_net,
d3 => slice10_y_net,
sel => delay15_q_net_x0,
y => mux8_y_net
);
mux9: entity work.mux_1a0db76efe
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => slice14_y_net,
d1 => slice13_y_net,
d2 => slice12_y_net,
d3 => slice11_y_net,
sel => delay15_q_net_x0,
y => mux9_y_net_x0
);
slice10: entity work.xlslice
generic map (
new_lsb => 14,
new_msb => 15,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice10_y_net
);
slice11: entity work.xlslice
generic map (
new_lsb => 6,
new_msb => 7,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice11_y_net
);
slice12: entity work.xlslice
generic map (
new_lsb => 4,
new_msb => 5,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice12_y_net
);
slice13: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 3,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice13_y_net
);
slice14: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 1,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice14_y_net
);
slice17: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 2,
y_width => 1
)
port map (
x => mux8_y_net,
y(0) => slice17_y_net_x0
);
slice3: entity work.xlslice
generic map (
new_lsb => 20,
new_msb => 21,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice3_y_net
);
slice4: entity work.xlslice
generic map (
new_lsb => 18,
new_msb => 19,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice4_y_net
);
slice5: entity work.xlslice
generic map (
new_lsb => 16,
new_msb => 17,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice5_y_net
);
slice6: entity work.xlslice
generic map (
new_lsb => 22,
new_msb => 23,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice6_y_net
);
slice7: entity work.xlslice
generic map (
new_lsb => 12,
new_msb => 13,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice7_y_net
);
slice8: entity work.xlslice
generic map (
new_lsb => 10,
new_msb => 11,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice8_y_net
);
slice9: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 9,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice9_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_cfa_gamma/bayer/xy_ctrs"
entity xy_ctrs_entity_9e9b1c9cc9 is
port (
av: in std_logic;
ce_1: in std_logic;
clk_1: in std_logic;
en: in std_logic;
vb: in std_logic;
x: out std_logic_vector(11 downto 0);
y: out std_logic_vector(11 downto 0)
);
end xy_ctrs_entity_9e9b1c9cc9;
architecture structural of xy_ctrs_entity_9e9b1c9cc9 is
signal active_video_i_net_x0: std_logic;
signal bool1_dout_net: std_logic;
signal bool2_dout_net: std_logic;
signal bool3_dout_net: std_logic;
signal ce_1_sg_x0: std_logic;
signal clk_1_sg_x0: std_logic;
signal delay20_q_net: std_logic;
signal delay21_q_net: std_logic;
signal enable_op_net_x0: std_logic;
signal expression1_dout_net: std_logic;
signal expression3_dout_net: std_logic;
signal expression_dout_net: std_logic;
signal inverter_op_net: std_logic;
signal vblank_i_net_x0: std_logic;
signal xcounter_op_net_x0: std_logic_vector(11 downto 0);
signal ycounter_op_net_x0: std_logic_vector(11 downto 0);
begin
active_video_i_net_x0 <= av;
ce_1_sg_x0 <= ce_1;
clk_1_sg_x0 <= clk_1;
enable_op_net_x0 <= en;
vblank_i_net_x0 <= vb;
x <= xcounter_op_net_x0;
y <= ycounter_op_net_x0;
bool1: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
din(0) => expression3_dout_net,
en => "1",
dout(0) => bool1_dout_net
);
bool2: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
din(0) => active_video_i_net_x0,
en => "1",
dout(0) => bool2_dout_net
);
bool3: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
din(0) => expression_dout_net,
en => "1",
dout(0) => bool3_dout_net
);
delay20: entity work.delay_5753e4c658
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
d(0) => vblank_i_net_x0,
q(0) => delay20_q_net
);
delay21: entity work.delay_a3ccf865c7
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
d(0) => active_video_i_net_x0,
en(0) => enable_op_net_x0,
q(0) => delay21_q_net
);
expression: entity work.expr_332f1d2335
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => vblank_i_net_x0,
d1(0) => delay20_q_net,
dout(0) => expression_dout_net
);
expression1: entity work.expr_3c2515cf08
port map (
a(0) => bool1_dout_net,
b(0) => enable_op_net_x0,
ce => '0',
clk => '0',
clr => '0',
dout(0) => expression1_dout_net
);
expression3: entity work.expr_332f1d2335
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => active_video_i_net_x0,
d1(0) => delay21_q_net,
dout(0) => expression3_dout_net
);
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
ip(0) => bool2_dout_net,
op(0) => inverter_op_net
);
xcounter: entity work.xlcounter_free
generic map (
core_name0 => "cntr_11_0_3eb0c8dcd9c22b4d",
op_arith => xlUnsigned,
op_width => 12
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
en(0) => enable_op_net_x0,
rst(0) => inverter_op_net,
op => xcounter_op_net_x0
);
ycounter: entity work.xlcounter_free
generic map (
core_name0 => "cntr_11_0_3eb0c8dcd9c22b4d",
op_arith => xlUnsigned,
op_width => 12
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
en(0) => expression1_dout_net,
rst(0) => bool3_dout_net,
op => ycounter_op_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_cfa_gamma/bayer"
entity bayer_entity_7e9fc9cbc8 is
port (
avi: in std_logic;
ce_1: in std_logic;
clk_1: in std_logic;
from_register: in std_logic_vector(31 downto 0);
hbi: in std_logic;
hsi: in std_logic;
vbi: in std_logic;
vdi: in std_logic_vector(9 downto 0);
vsi: in std_logic;
avo: out std_logic;
hbo: out std_logic;
hso: out std_logic;
vbo: out std_logic;
vdo: out std_logic_vector(23 downto 0);
vso: out std_logic
);
end bayer_entity_7e9fc9cbc8;
architecture structural of bayer_entity_7e9fc9cbc8 is
signal active_video_delay_q_net_x0: std_logic;
signal active_video_i_net_x1: std_logic;
signal addsub1_s_net: std_logic_vector(10 downto 0);
signal addsub5_s_net: std_logic_vector(10 downto 0);
signal bayer_conv: std_logic_vector(9 downto 0);
signal blue: std_logic_vector(9 downto 0);
signal ce_1_sg_x1: std_logic;
signal clk_1_sg_x1: std_logic;
signal concat1_y_net: std_logic_vector(23 downto 0);
signal concat2_y_net_x0: std_logic_vector(9 downto 0);
signal concat_y_net: std_logic_vector(1 downto 0);
signal convert_dout_net: std_logic;
signal d0: std_logic_vector(9 downto 0);
signal d1: std_logic_vector(9 downto 0);
signal d3: std_logic_vector(9 downto 0);
signal data_delay_q_net_x0: std_logic_vector(23 downto 0);
signal davg: std_logic_vector(11 downto 0);
signal davg_x0: std_logic_vector(11 downto 0);
signal davg_x1: std_logic_vector(9 downto 0);
signal delay10_q_net: std_logic_vector(9 downto 0);
signal delay11_q_net: std_logic_vector(9 downto 0);
signal delay12_q_net: std_logic_vector(9 downto 0);
signal delay13_q_net: std_logic_vector(9 downto 0);
signal delay14_q_net: std_logic_vector(9 downto 0);
signal delay15_q_net_x0: std_logic_vector(1 downto 0);
signal delay17_q_net: std_logic_vector(11 downto 0);
signal delay19_q_net: std_logic_vector(11 downto 0);
signal delay1_q_net: std_logic_vector(9 downto 0);
signal delay20_q_net: std_logic_vector(11 downto 0);
signal delay5_q_net: std_logic_vector(11 downto 0);
signal delay6_q_net: std_logic_vector(11 downto 0);
signal delay9_q_net: std_logic_vector(9 downto 0);
signal dir: std_logic_vector(11 downto 0);
signal dir_x0: std_logic_vector(9 downto 0);
signal enable_op_net_x0: std_logic;
signal from_register_data_out_net_x1: std_logic_vector(31 downto 0);
signal green: std_logic_vector(9 downto 0);
signal havg: std_logic_vector(10 downto 0);
signal havg_x0: std_logic_vector(11 downto 0);
signal havg_x1: std_logic_vector(9 downto 0);
signal hblank_delay_q_net_x0: std_logic;
signal hblank_i_net_x0: std_logic;
signal hsync_delay_q_net_x0: std_logic;
signal hsync_i_net_x0: std_logic;
signal mux7_y_net_x0: std_logic_vector(1 downto 0);
signal mux9_y_net_x0: std_logic_vector(1 downto 0);
signal red: std_logic_vector(9 downto 0);
signal single_port_ram_data_out_net: std_logic_vector(9 downto 0);
signal slice15_y_net: std_logic_vector(10 downto 0);
signal slice16_y_net: std_logic_vector(10 downto 0);
signal slice17_y_net_x0: std_logic;
signal slice6_y_net: std_logic;
signal slice7_y_net: std_logic_vector(7 downto 0);
signal slice8_y_net: std_logic_vector(7 downto 0);
signal slice9_y_net: std_logic_vector(7 downto 0);
signal slice_y_net: std_logic;
signal vavg: std_logic_vector(10 downto 0);
signal vavg_x0: std_logic_vector(11 downto 0);
signal vavg_x1: std_logic_vector(9 downto 0);
signal vblank_delay_q_net_x0: std_logic;
signal vblank_i_net_x1: std_logic;
signal vsync_delay_q_net_x0: std_logic;
signal vsync_i_net_x0: std_logic;
signal xavg: std_logic_vector(9 downto 0);
signal xcounter_op_net_x0: std_logic_vector(11 downto 0);
signal ycounter_op_net_x0: std_logic_vector(11 downto 0);
begin
active_video_i_net_x1 <= avi;
ce_1_sg_x1 <= ce_1;
clk_1_sg_x1 <= clk_1;
from_register_data_out_net_x1 <= from_register;
hblank_i_net_x0 <= hbi;
hsync_i_net_x0 <= hsi;
vblank_i_net_x1 <= vbi;
concat2_y_net_x0 <= vdi;
vsync_i_net_x0 <= vsi;
avo <= active_video_delay_q_net_x0;
hbo <= hblank_delay_q_net_x0;
hso <= hsync_delay_q_net_x0;
vbo <= vblank_delay_q_net_x0;
vdo <= data_delay_q_net_x0;
vso <= vsync_delay_q_net_x0;
active_video_delay: entity work.delay_1b0d89c05a
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d(0) => active_video_i_net_x1,
q(0) => active_video_delay_q_net_x0
);
addsub1: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 10,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 10,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 11,
core_name0 => "addsb_11_0_c25f95ce6b0868c9",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 11,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 11
)
port map (
a => d0,
b => delay12_q_net,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
en => "1",
s => addsub1_s_net
);
addsub2: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 10,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 10,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 11,
core_name0 => "addsb_11_0_c25f95ce6b0868c9",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 11,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 11
)
port map (
a => delay1_q_net,
b => delay11_q_net,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
en => "1",
s => vavg
);
addsub3: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 11,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 11,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 12,
core_name0 => "addsb_11_0_a629aff4db5bb1c8",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 12,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 12
)
port map (
a => havg,
b => vavg,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
en => "1",
s => davg
);
addsub5: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 10,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 10,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 11,
core_name0 => "addsb_11_0_c25f95ce6b0868c9",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 11,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 11
)
port map (
a => d3,
b => delay14_q_net,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
en => "1",
s => addsub5_s_net
);
addsub6: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 10,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 10,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 11,
core_name0 => "addsb_11_0_c25f95ce6b0868c9",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 11,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 11
)
port map (
a => d1,
b => delay13_q_net,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
en => "1",
s => havg
);
addsub7: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 11,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 11,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 12,
core_name0 => "addsb_11_0_a629aff4db5bb1c8",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 12,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 12
)
port map (
a => addsub1_s_net,
b => addsub5_s_net,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
en => "1",
s => davg_x0
);
concat: entity work.concat_e6f5ee726b
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => slice_y_net,
in1(0) => slice6_y_net,
y => concat_y_net
);
concat1: entity work.concat_d0d1b9533e
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => slice7_y_net,
in1 => slice8_y_net,
in2 => slice9_y_net,
y => concat1_y_net
);
convert: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
din(0) => active_video_i_net_x1,
en => "1",
dout(0) => convert_dout_net
);
data_delay: entity work.delay_e1f6cb3ad9
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => concat1_y_net,
q => data_delay_q_net_x0
);
delay1: entity work.delay_33cb3f7e58
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => d0,
en(0) => enable_op_net_x0,
q => delay1_q_net
);
delay10: entity work.delay_33cb3f7e58
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => d1,
en(0) => enable_op_net_x0,
q => delay10_q_net
);
delay11: entity work.delay_33cb3f7e58
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => d3,
en(0) => enable_op_net_x0,
q => delay11_q_net
);
delay12: entity work.delay_33cb3f7e58
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => delay1_q_net,
en(0) => enable_op_net_x0,
q => delay12_q_net
);
delay13: entity work.delay_33cb3f7e58
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => delay10_q_net,
en(0) => enable_op_net_x0,
q => delay13_q_net
);
delay14: entity work.delay_33cb3f7e58
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => delay11_q_net,
en(0) => enable_op_net_x0,
q => delay14_q_net
);
delay15: entity work.delay_0025330cf4
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => concat_y_net,
en(0) => enable_op_net_x0,
q => delay15_q_net_x0
);
delay17: entity work.delay_ec78404abf
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => davg_x0,
en(0) => enable_op_net_x0,
q => delay17_q_net
);
delay19: entity work.delay_ec78404abf
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => dir,
en(0) => enable_op_net_x0,
q => delay19_q_net
);
delay20: entity work.delay_ec78404abf
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => davg,
en(0) => enable_op_net_x0,
q => delay20_q_net
);
delay5: entity work.delay_ec78404abf
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => havg_x0,
en(0) => enable_op_net_x0,
q => delay5_q_net
);
delay6: entity work.delay_ec78404abf
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => vavg_x0,
en(0) => enable_op_net_x0,
q => delay6_q_net
);
delay7: entity work.delay_0fbdd36101
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => delay9_q_net,
en(0) => enable_op_net_x0,
q => d0
);
delay8: entity work.delay_33cb3f7e58
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => single_port_ram_data_out_net,
en(0) => enable_op_net_x0,
q => d1
);
delay9: entity work.delay_0fbdd36101
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => bayer_conv,
en(0) => enable_op_net_x0,
q => delay9_q_net
);
enable: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => enable_op_net_x0
);
hblank_delay: entity work.delay_1b0d89c05a
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d(0) => hblank_i_net_x0,
q(0) => hblank_delay_q_net_x0
);
hsync_delay: entity work.delay_1b0d89c05a
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d(0) => hsync_i_net_x0,
q(0) => hsync_delay_q_net_x0
);
mux2: entity work.mux_4fe5face7f
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => dir_x0,
d1 => xavg,
sel(0) => slice17_y_net_x0,
y => green
);
mux3: entity work.mux_61418c8488
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => dir_x0,
d1 => havg_x1,
d2 => vavg_x1,
d3 => davg_x1,
sel => mux9_y_net_x0,
y => blue
);
mux4: entity work.mux_61418c8488
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => dir_x0,
d1 => havg_x1,
d2 => vavg_x1,
d3 => davg_x1,
sel => mux7_y_net_x0,
y => red
);
shift: entity work.shift_d9577b2c80
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
ip => havg,
op => havg_x0
);
shift1: entity work.shift_d9577b2c80
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
ip => vavg,
op => vavg_x0
);
shift2: entity work.shift_0a73a8a346
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
ip => delay10_q_net,
op => dir
);
single_port_ram: entity work.xlspram
generic map (
c_address_width => 11,
c_width => 10,
core_name0 => "bmg_62_2be284cffc9a51ef",
latency => 1
)
port map (
addr => slice15_y_net,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
data_in => delay9_q_net,
en(0) => enable_op_net_x0,
rst => "0",
we(0) => convert_dout_net,
data_out => single_port_ram_data_out_net
);
single_port_ram1: entity work.xlspram
generic map (
c_address_width => 11,
c_width => 10,
core_name0 => "bmg_62_2be284cffc9a51ef",
latency => 1
)
port map (
addr => slice16_y_net,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
data_in => single_port_ram_data_out_net,
en(0) => enable_op_net_x0,
rst => "0",
we(0) => convert_dout_net,
data_out => d3
);
slice: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 12,
y_width => 1
)
port map (
x => ycounter_op_net_x0,
y(0) => slice_y_net
);
slice1: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 11,
x_width => 12,
y_width => 10
)
port map (
x => delay17_q_net,
y => davg_x1
);
slice10: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 9,
x_width => 10,
y_width => 10
)
port map (
x => concat2_y_net_x0,
y => bayer_conv
);
slice15: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 10,
x_width => 12,
y_width => 11
)
port map (
x => xcounter_op_net_x0,
y => slice15_y_net
);
slice16: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 10,
x_width => 12,
y_width => 11
)
port map (
x => xcounter_op_net_x0,
y => slice16_y_net
);
slice2: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 11,
x_width => 12,
y_width => 10
)
port map (
x => delay5_q_net,
y => havg_x1
);
slice3: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 11,
x_width => 12,
y_width => 10
)
port map (
x => delay19_q_net,
y => dir_x0
);
slice4: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 11,
x_width => 12,
y_width => 10
)
port map (
x => delay6_q_net,
y => vavg_x1
);
slice5: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 11,
x_width => 12,
y_width => 10
)
port map (
x => delay20_q_net,
y => xavg
);
slice6: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 12,
y_width => 1
)
port map (
x => xcounter_op_net_x0,
y(0) => slice6_y_net
);
slice7: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 9,
x_width => 10,
y_width => 8
)
port map (
x => red,
y => slice7_y_net
);
slice8: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 9,
x_width => 10,
y_width => 8
)
port map (
x => green,
y => slice8_y_net
);
slice9: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 9,
x_width => 10,
y_width => 8
)
port map (
x => blue,
y => slice9_y_net
);
subsystem_387011edf3: entity work.subsystem_entity_387011edf3
port map (
from_register => from_register_data_out_net_x1,
pos => delay15_q_net_x0,
bsel => mux9_y_net_x0,
gsel => slice17_y_net_x0,
rsel => mux7_y_net_x0
);
vblank_delay: entity work.delay_1b0d89c05a
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d(0) => vblank_i_net_x1,
q(0) => vblank_delay_q_net_x0
);
vsync_delay: entity work.delay_1b0d89c05a
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d(0) => vsync_i_net_x0,
q(0) => vsync_delay_q_net_x0
);
xy_ctrs_9e9b1c9cc9: entity work.xy_ctrs_entity_9e9b1c9cc9
port map (
av => active_video_i_net_x1,
ce_1 => ce_1_sg_x1,
clk_1 => clk_1_sg_x1,
en => enable_op_net_x0,
vb => vblank_i_net_x1,
x => xcounter_op_net_x0,
y => ycounter_op_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_cfa_gamma/gamma"
entity gamma_entity_43073d24ce is
port (
ce_1: in std_logic;
clk_1: in std_logic;
in1: in std_logic_vector(23 downto 0);
out1: out std_logic_vector(23 downto 0)
);
end gamma_entity_43073d24ce;
architecture structural of gamma_entity_43073d24ce is
signal blue: std_logic_vector(7 downto 0);
signal ce_1_sg_x2: std_logic;
signal clk_1_sg_x2: std_logic;
signal concat_y_net_x0: std_logic_vector(23 downto 0);
signal data_delay_q_net_x1: std_logic_vector(23 downto 0);
signal green: std_logic_vector(7 downto 0);
signal red: std_logic_vector(7 downto 0);
signal rom_blue_data_net: std_logic_vector(7 downto 0);
signal rom_green_data_net: std_logic_vector(7 downto 0);
signal rom_red_data_net: std_logic_vector(7 downto 0);
begin
ce_1_sg_x2 <= ce_1;
clk_1_sg_x2 <= clk_1;
data_delay_q_net_x1 <= in1;
out1 <= concat_y_net_x0;
concat: entity work.concat_d0d1b9533e
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => rom_red_data_net,
in1 => rom_green_data_net,
in2 => rom_blue_data_net,
y => concat_y_net_x0
);
rom_blue: entity work.xlsprom
generic map (
c_address_width => 8,
c_width => 8,
core_name0 => "bmg_62_efdcd0e54d01b373",
latency => 1
)
port map (
addr => blue,
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
en => "1",
rst => "0",
data => rom_blue_data_net
);
rom_green: entity work.xlsprom
generic map (
c_address_width => 8,
c_width => 8,
core_name0 => "bmg_62_efdcd0e54d01b373",
latency => 1
)
port map (
addr => green,
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
en => "1",
rst => "0",
data => rom_green_data_net
);
rom_red: entity work.xlsprom
generic map (
c_address_width => 8,
c_width => 8,
core_name0 => "bmg_62_efdcd0e54d01b373",
latency => 1
)
port map (
addr => red,
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
en => "1",
rst => "0",
data => rom_red_data_net
);
slice15downto8: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 15,
x_width => 24,
y_width => 8
)
port map (
x => data_delay_q_net_x1,
y => green
);
slice23downto16: entity work.xlslice
generic map (
new_lsb => 16,
new_msb => 23,
x_width => 24,
y_width => 8
)
port map (
x => data_delay_q_net_x1,
y => red
);
slice7downto0: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 7,
x_width => 24,
y_width => 8
)
port map (
x => data_delay_q_net_x1,
y => blue
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_cfa_gamma"
entity sg_cfa_gamma is
port (
active_video_i: in std_logic;
ce_1: in std_logic;
clk_1: in std_logic;
data_out: in std_logic_vector(31 downto 0);
dout: in std_logic_vector(31 downto 0);
hblank_i: in std_logic;
hsync_i: in std_logic;
plb_abus: in std_logic_vector(31 downto 0);
plb_ce_1: in std_logic;
plb_clk_1: in std_logic;
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
vblank_i: in std_logic;
video_data_i: in std_logic_vector(7 downto 0);
vsync_i: in std_logic;
active_video_o: out std_logic;
data_in: out std_logic_vector(31 downto 0);
en: out std_logic;
hblank_o: out std_logic;
hsync_o: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
vblank_o: out std_logic;
video_data_o: out std_logic_vector(23 downto 0);
vsync_o: out std_logic
);
end sg_cfa_gamma;
architecture structural of sg_cfa_gamma is
attribute core_generation_info: string;
attribute core_generation_info of structural : architecture is "sg_cfa_gamma,sysgen_core,{clock_period=10.00000000,clocking=Clock_Enables,sample_periods=1.00000000000 1.00000000000,testbench=0,total_blocks=223,xilinx_adder_subtracter_block=6,xilinx_binary_shift_operator_block=3,xilinx_bit_slice_extractor_block=29,xilinx_bitwise_expression_evaluator_block=3,xilinx_bus_concatenator_block=4,xilinx_bus_multiplexer_block=6,xilinx_constant_block_block=3,xilinx_counter_block=2,xilinx_delay_block=28,xilinx_edk_processor_block=1,xilinx_gateway_in_block=12,xilinx_gateway_out_block=22,xilinx_inverter_block=1,xilinx_mcode_block_block=2,xilinx_shared_memory_based_from_register_block=1,xilinx_shared_memory_based_to_register_block=1,xilinx_single_port_random_access_memory_block=2,xilinx_single_port_read_only_memory_block=3,xilinx_system_generator_block=1,xilinx_type_converter_block=4,}";
signal active_video_delay_q_net_x0: std_logic;
signal active_video_i_net: std_logic;
signal active_video_o_net: std_logic;
signal ce_1_sg_x3: std_logic;
signal clk_1_sg_x3: std_logic;
signal concat2_y_net_x0: std_logic_vector(9 downto 0);
signal constant_op_net: std_logic_vector(1 downto 0);
signal data_delay_q_net_x1: std_logic_vector(23 downto 0);
signal data_in_net: std_logic_vector(31 downto 0);
signal data_out_net: std_logic_vector(31 downto 0);
signal dout_net: std_logic_vector(31 downto 0);
signal en_net: std_logic;
signal hblank_delay_q_net_x0: std_logic;
signal hblank_i_net: std_logic;
signal hblank_o_net: std_logic;
signal hsync_delay_q_net_x0: std_logic;
signal hsync_i_net: std_logic;
signal hsync_o_net: std_logic;
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_ce_1_sg_x1: std_logic;
signal plb_clk_1_sg_x1: std_logic;
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal sg_plb_addrpref_net: std_logic_vector(19 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal splb_rst_net: std_logic;
signal vblank_delay_q_net_x0: std_logic;
signal vblank_i_net: std_logic;
signal vblank_o_net: std_logic;
signal video_data_i_net: std_logic_vector(7 downto 0);
signal video_data_o_net: std_logic_vector(23 downto 0);
signal vsync_delay_q_net_x0: std_logic;
signal vsync_i_net: std_logic;
signal vsync_o_net: std_logic;
begin
active_video_i_net <= active_video_i;
ce_1_sg_x3 <= ce_1;
clk_1_sg_x3 <= clk_1;
data_out_net <= data_out;
dout_net <= dout;
hblank_i_net <= hblank_i;
hsync_i_net <= hsync_i;
plb_abus_net <= plb_abus;
plb_ce_1_sg_x1 <= plb_ce_1;
plb_clk_1_sg_x1 <= plb_clk_1;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
vblank_i_net <= vblank_i;
video_data_i_net <= video_data_i;
vsync_i_net <= vsync_i;
active_video_o <= active_video_o_net;
data_in <= data_in_net;
en <= en_net;
hblank_o <= hblank_o_net;
hsync_o <= hsync_o_net;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x1;
sl_wrdack <= sl_wrdack_x1;
vblank_o <= vblank_o_net;
video_data_o <= video_data_o_net;
vsync_o <= vsync_o_net;
bayer_7e9fc9cbc8: entity work.bayer_entity_7e9fc9cbc8
port map (
avi => active_video_i_net,
ce_1 => ce_1_sg_x3,
clk_1 => clk_1_sg_x3,
from_register => data_out_net,
hbi => hblank_i_net,
hsi => hsync_i_net,
vbi => vblank_i_net,
vdi => concat2_y_net_x0,
vsi => vsync_i_net,
avo => active_video_delay_q_net_x0,
hbo => hblank_delay_q_net_x0,
hso => hsync_delay_q_net_x0,
vbo => vblank_delay_q_net_x0,
vdo => data_delay_q_net_x1,
vso => vsync_delay_q_net_x0
);
concat2: entity work.concat_8712d31083
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => video_data_i_net,
in1 => constant_op_net,
y => concat2_y_net_x0
);
constant_x0: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
delay1: entity work.delay_5753e4c658
port map (
ce => ce_1_sg_x3,
clk => clk_1_sg_x3,
clr => '0',
d(0) => hsync_delay_q_net_x0,
q(0) => hsync_o_net
);
delay2: entity work.delay_5753e4c658
port map (
ce => ce_1_sg_x3,
clk => clk_1_sg_x3,
clr => '0',
d(0) => vblank_delay_q_net_x0,
q(0) => vblank_o_net
);
delay3: entity work.delay_5753e4c658
port map (
ce => ce_1_sg_x3,
clk => clk_1_sg_x3,
clr => '0',
d(0) => hblank_delay_q_net_x0,
q(0) => hblank_o_net
);
delay4: entity work.delay_5753e4c658
port map (
ce => ce_1_sg_x3,
clk => clk_1_sg_x3,
clr => '0',
d(0) => vsync_delay_q_net_x0,
q(0) => vsync_o_net
);
delay5: entity work.delay_5753e4c658
port map (
ce => ce_1_sg_x3,
clk => clk_1_sg_x3,
clr => '0',
d(0) => active_video_delay_q_net_x0,
q(0) => active_video_o_net
);
edk_processor_33f025737d: entity work.edk_processor_entity_33f025737d
port map (
plb_abus => plb_abus_net,
plb_ce_1 => plb_ce_1_sg_x1,
plb_clk_1 => plb_clk_1_sg_x1,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
sg_plb_addrpref => sg_plb_addrpref_net,
splb_rst => splb_rst_net,
to_register => dout_net,
constant5_x0 => sl_wait_net,
plb_decode_x0 => sl_addrack_net,
plb_decode_x1 => sl_rdcomp_net,
plb_decode_x2 => sl_wrdack_x1,
plb_decode_x3 => sl_rddack_net,
plb_decode_x4 => sl_rddbus_net,
plb_memmap_x0 => data_in_net,
plb_memmap_x1 => en_net
);
gamma_43073d24ce: entity work.gamma_entity_43073d24ce
port map (
ce_1 => ce_1_sg_x3,
clk_1 => clk_1_sg_x3,
in1 => data_delay_q_net_x1,
out1 => video_data_o_net
);
end structural;
|
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
library work;
use work.mips_defs.ALL;
entity cpu is
port (clk : in std_logic;
rst : in std_logic;
mem_halt : in std_logic;
pc : out std_logic_vector(31 downto 0);
instr : in std_logic_vector(31 downto 0);
data_addr : out std_logic_vector(31 downto 0);
data_read : out std_logic;
data_in : in std_logic_vector(31 downto 0);
data_write : out std_logic;
data_out : out std_logic_vector(31 downto 0));
end entity cpu;
architecture rtl of cpu is
component register_file is
port (clk : in std_logic;
rst : in std_logic;
a1 : in std_logic_vector(4 downto 0);
a2 : in std_logic_vector(4 downto 0);
a3 : in std_logic_vector(4 downto 0);
wd3 : in std_logic_vector(31 downto 0);
we3 : in std_logic;
rd1 : out std_logic_vector(31 downto 0);
rd2 : out std_logic_vector(31 downto 0));
end component register_file;
component cpu_fetch is
port (pc : in std_logic_vector(31 downto 0);
pcbranch : in std_logic_vector(31 downto 0);
pcsrc : in std_logic;
instr_n : out std_logic_vector(31 downto 0);
pcplus4_n : out std_logic_vector(31 downto 0);
pc_n : out std_logic_vector(31 downto 0);
imem_addr : out std_logic_vector(31 downto 0);
imem_data : in std_logic_vector(31 downto 0));
end component cpu_fetch;
component cpu_decode is
port (instr : in std_logic_vector(31 downto 0);
pcplus4 : in std_logic_vector(31 downto 0);
rs_n : out std_logic_vector(4 downto 0);
rt_n : out std_logic_vector(4 downto 0);
rd_n : out std_logic_vector(4 downto 0);
shamt_n : out std_logic_vector(4 downto 0);
imm_n : out std_logic_vector(31 downto 0);
alusrc_n : out std_logic;
regdst_n : out std_logic;
alucontrol_n : out alucontrol_type;
ovf_en_n : out std_logic;
regwrite_n : out std_logic;
memtoreg_n : out std_logic;
memread_n : out std_logic;
memwrite_n : out std_logic;
rd1_n : out std_logic_vector(31 downto 0);
rd2_n : out std_logic_vector(31 downto 0);
pcsrc_n : out std_logic;
branch_n : out std_logic;
pcbranch_n : out std_logic_vector(31 downto 0);
-- Forward
forward_a : in std_logic;
forward_b : in std_logic;
aluout_fwd : in std_logic_vector(31 downto 0);
-- Register file
reg_a1 : out std_logic_vector(4 downto 0);
reg_a2 : out std_logic_vector(4 downto 0);
reg_rd1 : in std_logic_vector(31 downto 0);
reg_rd2 : in std_logic_vector(31 downto 0));
end component cpu_decode;
component cpu_execute is
port (rt : in std_logic_vector(4 downto 0);
rd : in std_logic_vector(4 downto 0);
shamt : in std_logic_vector(4 downto 0);
imm : in std_logic_vector(31 downto 0);
alusrc : in std_logic;
regdst : in std_logic;
alucontrol : in alucontrol_type;
ovf_en : in std_logic;
rd1 : in std_logic_vector(31 downto 0);
rd2 : in std_logic_vector(31 downto 0);
regwrite : in std_logic;
memtoreg : in std_logic;
memread : in std_logic;
memwrite : in std_logic;
regwrite_n : out std_logic;
memtoreg_n : out std_logic;
memread_n : out std_logic;
memwrite_n : out std_logic;
aluout_n : out std_logic_vector(31 downto 0);
writedata_n : out std_logic_vector(31 downto 0);
writereg_n : out std_logic_vector(4 downto 0);
-- Forward
forward_a : in std_logic_vector(1 downto 0);
forward_b : in std_logic_vector(1 downto 0);
aluout_fwd : in std_logic_vector(31 downto 0);
result_fwd : in std_logic_vector(31 downto 0));
end component cpu_execute;
component cpu_memory is
port (regwrite : in std_logic;
memtoreg : in std_logic;
memread : in std_logic;
memwrite : in std_logic;
aluout : in std_logic_vector(31 downto 0);
writedata : in std_logic_vector(31 downto 0);
writereg : in std_logic_vector(4 downto 0);
regwrite_n : out std_logic;
memtoreg_n : out std_logic;
aluout_n : out std_logic_vector(31 downto 0);
readdata_n : out std_logic_vector(31 downto 0);
writereg_n : out std_logic_vector(4 downto 0);
data_addr : out std_logic_vector(31 downto 0);
data_read : out std_logic;
data_in : in std_logic_vector(31 downto 0);
data_write : out std_logic;
data_out : out std_logic_vector(31 downto 0));
end component cpu_memory;
component cpu_writeback is
port (regwrite : in std_logic;
memtoreg : in std_logic;
aluout : in std_logic_vector(31 downto 0);
readdata : in std_logic_vector(31 downto 0);
writereg : in std_logic_vector(4 downto 0);
writereg_n : out std_logic_vector(4 downto 0);
result_n : out std_logic_vector(31 downto 0);
regwrite_n : out std_logic);
end component cpu_writeback;
component hazard is
port (branch_d : in std_logic;
rs_d : in std_logic_vector(4 downto 0);
rt_d : in std_logic_vector(4 downto 0);
rs_e : in std_logic_vector(4 downto 0);
rt_e : in std_logic_vector(4 downto 0);
writereg_e : in std_logic_vector(4 downto 0);
memtoreg_e : in std_logic;
regwrite_e : in std_logic;
writereg_m : in std_logic_vector(4 downto 0);
memtoreg_m : in std_logic;
regwrite_m : in std_logic;
writereg_w : in std_logic_vector(4 downto 0);
regwrite_w : in std_logic;
forward_ad : out std_logic;
forward_bd : out std_logic;
forward_ae : out std_logic_vector(1 downto 0);
forward_be : out std_logic_vector(1 downto 0);
stall : out std_logic);
end component hazard;
type fetch_state is record
pc : std_logic_vector(31 downto 0);
end record;
constant fetch_reset : fetch_state := (pc => (others => '0'));
signal fetch_reg, fetch_next : fetch_state;
type decode_state is record
instr : std_logic_vector(31 downto 0);
pcplus4 : std_logic_vector(31 downto 0);
end record;
constant decode_reset : decode_state := (instr => (others => '0'),
pcplus4 => (others => '0'));
signal decode_reg, decode_next : decode_state;
type execute_state is record
rs : std_logic_vector(4 downto 0);
rt : std_logic_vector(4 downto 0);
rd : std_logic_vector(4 downto 0);
shamt : std_logic_vector(4 downto 0);
imm : std_logic_vector(31 downto 0);
alusrc : std_logic;
regdst : std_logic;
alucontrol : alucontrol_type;
ovf_en : std_logic;
regwrite : std_logic;
memtoreg : std_logic;
memread : std_logic;
memwrite : std_logic;
rd1 : std_logic_vector(31 downto 0);
rd2 : std_logic_vector(31 downto 0);
end record;
constant execute_reset : execute_state := (rs => "00000",
rt => "00000",
rd => "00000",
shamt => "00000",
imm => (others => '0'),
alusrc => '0',
regdst => '0',
alucontrol => ALU_SLL,
ovf_en => '0',
regwrite => '0',
memtoreg => '0',
memread => '0',
memwrite => '0',
rd1 => (others => '0'),
rd2 => (others => '0'));
signal execute_reg, execute_next : execute_state;
type memory_state is record
regwrite : std_logic;
memtoreg : std_logic;
memread : std_logic;
memwrite : std_logic;
aluout : std_logic_vector(31 downto 0);
writedata : std_logic_vector(31 downto 0);
writereg : std_logic_vector(4 downto 0);
end record;
constant memory_reset : memory_state := (regwrite => '0',
memtoreg => '0',
memread => '0',
memwrite => '0',
aluout => (others => '0'),
writedata => (others => '0'),
writereg => "00000");
signal memory_reg, memory_next : memory_state;
type writeback_state is record
regwrite : std_logic;
memtoreg : std_logic;
aluout : std_logic_vector(31 downto 0);
readdata : std_logic_vector(31 downto 0);
writereg : std_logic_vector(4 downto 0);
end record;
constant writeback_reset : writeback_state := (regwrite => '0',
memtoreg => '0',
aluout => (others => '0'),
readdata => (others => '0'),
writereg => "00000");
signal writeback_reg, writeback_next : writeback_state;
signal halt : std_logic;
-- register file
signal rs : std_logic_vector(4 downto 0);
signal rt : std_logic_vector(4 downto 0);
signal writereg : std_logic_vector(4 downto 0);
signal result : std_logic_vector(31 downto 0);
signal regwrite : std_logic;
signal reg_rd1 : std_logic_vector(31 downto 0);
signal reg_rd2 : std_logic_vector(31 downto 0);
-- Jump / Branch
signal pcbranch : std_logic_vector(31 downto 0);
signal pcsrc : std_logic;
signal branch : std_logic;
-- Bypass / Forward
signal decode_forward_a, decode_forward_b : std_logic;
signal execute_forward_a, execute_forward_b : std_logic_vector(1 downto 0);
-- Pipeline stall
signal stall : std_logic;
begin
halt <= mem_halt;
reg_file0: register_file
port map (clk => clk,
rst => rst,
a1 => rs,
a2 => rt,
a3 => writereg,
wd3 => result,
we3 => regwrite,
rd1 => reg_rd1,
rd2 => reg_rd2);
fetch0: cpu_fetch
port map (pc => fetch_reg.pc,
pcbranch => pcbranch,
pcsrc => pcsrc,
instr_n => decode_next.instr,
pcplus4_n => decode_next.pcplus4,
pc_n => fetch_next.pc,
imem_addr => pc,
imem_data => instr);
decode0: cpu_decode
port map (instr => decode_reg.instr,
pcplus4 => decode_reg.pcplus4,
rs_n => execute_next.rs,
rt_n => execute_next.rt,
rd_n => execute_next.rd,
shamt_n => execute_next.shamt,
imm_n => execute_next.imm,
alusrc_n => execute_next.alusrc,
regdst_n => execute_next.regdst,
alucontrol_n => execute_next.alucontrol,
ovf_en_n => execute_next.ovf_en,
regwrite_n => execute_next.regwrite,
memtoreg_n => execute_next.memtoreg,
memread_n => execute_next.memread,
memwrite_n => execute_next.memwrite,
rd1_n => execute_next.rd1,
rd2_n => execute_next.rd2,
pcsrc_n => pcsrc,
branch_n => branch,
pcbranch_n => pcbranch,
forward_a => decode_forward_a,
forward_b => decode_forward_b,
aluout_fwd => memory_reg.aluout,
reg_a1 => rs,
reg_a2 => rt,
reg_rd1 => reg_rd1,
reg_rd2 => reg_rd2);
execute0: cpu_execute
port map (rt => execute_reg.rt,
rd => execute_reg.rd,
shamt => execute_reg.shamt,
imm => execute_reg.imm,
alusrc => execute_reg.alusrc,
regdst => execute_reg.regdst,
alucontrol => execute_reg.alucontrol,
ovf_en => execute_reg.ovf_en,
rd1 => execute_reg.rd1,
rd2 => execute_reg.rd2,
regwrite => execute_reg.regwrite,
memtoreg => execute_reg.memtoreg,
memread => execute_reg.memread,
memwrite => execute_reg.memwrite,
regwrite_n => memory_next.regwrite,
memtoreg_n => memory_next.memtoreg,
memread_n => memory_next.memread,
memwrite_n => memory_next.memwrite,
aluout_n => memory_next.aluout,
writedata_n => memory_next.writedata,
writereg_n => memory_next.writereg,
forward_a => execute_forward_a,
forward_b => execute_forward_b,
aluout_fwd => memory_reg.aluout,
result_fwd => result);
memory0 : cpu_memory
port map (regwrite => memory_reg.regwrite,
memtoreg => memory_reg.memtoreg,
memread => memory_reg.memread,
memwrite => memory_reg.memwrite,
aluout => memory_reg.aluout,
writedata => memory_reg.writedata,
writereg => memory_reg.writereg,
regwrite_n => writeback_next.regwrite,
memtoreg_n => writeback_next.memtoreg,
aluout_n => writeback_next.aluout,
readdata_n => writeback_next.readdata,
writereg_n => writeback_next.writereg,
data_addr => data_addr,
data_read => data_read,
data_in => data_in,
data_write => data_write,
data_out => data_out);
writeback0 : cpu_writeback
port map (regwrite => writeback_reg.regwrite,
memtoreg => writeback_reg.memtoreg,
aluout => writeback_reg.aluout,
readdata => writeback_reg.readdata,
writereg => writeback_reg.writereg,
writereg_n => writereg,
result_n => result,
regwrite_n => regwrite);
hazard0 : hazard
port map (branch_d => branch,
rs_d => rs,
rt_d => rt,
rs_e => execute_reg.rs,
rt_e => execute_reg.rt,
writereg_e => memory_next.writereg,
memtoreg_e => execute_reg.memtoreg,
regwrite_e => execute_reg.regwrite,
writereg_m => memory_reg.writereg,
memtoreg_m => memory_reg.memtoreg,
regwrite_m => memory_reg.regwrite,
writereg_w => writeback_reg.writereg,
regwrite_w => writeback_reg.regwrite,
forward_ad => decode_forward_a,
forward_bd => decode_forward_b,
forward_ae => execute_forward_a,
forward_be => execute_forward_b,
stall => stall);
process (clk, rst)
begin
if rst = '1' then
fetch_reg <= fetch_reset;
decode_reg <= decode_reset;
execute_reg <= execute_reset;
memory_reg <= memory_reset;
writeback_reg <= writeback_reset;
elsif rising_edge(clk) then
if halt = '0' then
if stall = '1' then
execute_reg <= execute_reset;
memory_reg <= memory_next;
writeback_reg <= writeback_next;
else
fetch_reg <= fetch_next;
decode_reg <= decode_next;
execute_reg <= execute_next;
memory_reg <= memory_next;
writeback_reg <= writeback_next;
end if;
end if;
end if;
end process;
end architecture rtl;
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
SETUP_1,
SETUP_2,
SETUP_3,
SETUP_4,
SETUP_5,
SETUP_6,
WHILE_LOOP_1,
WHILE_LOOP_2,
WHILE_LOOP_3,
WHILE_LOOP_4,
WHILE_LOOP_4a,
WHILE_LOOP_5,
WHILE_LOOP_6,
WHILE_LOOP_7,
WHILE_LOOP_8,
WHILE_LOOP_9,
FUNCTION_EXIT_1,
FUNCTION_EXIT_2,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_WHILE_LOOP_3 : std_logic_vector(0 to 15) := x"0103";
constant U_WHILE_LOOP_6 : std_logic_vector(0 to 15) := x"0106";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
-- constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
-- constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
-- constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
-- constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
-- constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
-- constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
-- constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
-- constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
-- constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
-- constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
-- constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
-- constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal structAddr, structAddr_next : std_logic_vector(0 to 31);
signal size, size_next : std_logic_vector(0 to 31);
signal index, index_next : std_logic_vector(0 to 31);
signal xAddr, xAddr_next : std_logic_vector(0 to 31);
signal yAddr, yAddr_next : std_logic_vector(0 to 31);
signal zAddr, zAddr_next : std_logic_vector(0 to 31);
signal xVal, xVal_next : std_logic_vector(0 to 31);
signal yVal, yVal_next : std_logic_vector(0 to 31);
signal mutexAddr, mutexAddr_next : std_logic_vector(0 to 31);
signal count, count_next : std_logic_vector(0 to 31);
-- misc constants
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
structAddr <= structAddr_next;
size <= size_next;
index <= index_next;
xAddr <= xAddr_next;
yAddr <= yAddr_next;
zAddr <= zAddr_next;
xVal <= xVal_next;
yVal <= yVal_next;
mutexAddr <= mutexAddr_next;
count <= count_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_WHILE_LOOP_3 =>
current_state <= WHILE_LOOP_3;
when U_WHILE_LOOP_6 =>
current_state <= WHILE_LOOP_6;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
structAddr_next <= structAddr;
size_next <= size;
index_next <= index;
xAddr_next <= xAddr;
yAddr_next <= yAddr;
zAddr_next <= zAddr;
xVal_next <= xVal;
yVal_next <= yVal;
mutexAddr_next <= mutexAddr;
count_next <= count;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
when FUNCTION_START =>
-- POP the argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_value <= Z32;
count_next <= Z32;
next_state <= WAIT_STATE;
return_state_next <= SETUP_1;
when SETUP_1 =>
-- Read the argument, which is an address of a struct
structAddr_next <= toUser_value;
-- Initiate the reading of the first variable in the struct, size
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= toUser_value;
next_state <= WAIT_STATE;
return_state_next <= SETUP_2;
when SETUP_2 =>
-- Read the value of size
size_next <= toUser_value;
-- Initiate the reading of the third variable in the struct, xAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= SETUP_3;
when SETUP_3 =>
-- Read the value of xAddr
xAddr_next <= toUser_value;
-- Initiate the reading of the fourth variable in the struct, yAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= SETUP_4;
when SETUP_4 =>
-- Read the value of yAddr
yAddr_next <= toUser_value;
-- Initiate the reading of the fifth variable in the struct, zAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000010";
next_state <= WAIT_STATE;
return_state_next <= SETUP_5;
when SETUP_5 =>
-- Read the value of zAddr
zAddr_next <= toUser_value;
-- Initiate the reading of the sixth variable in the struct, mutexAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000014";
next_state <= WAIT_STATE;
return_state_next <= SETUP_6;
when SETUP_6 =>
-- Read the value of mutexAddr
mutexAddr_next <= toUser_value;
next_state <= WHILE_LOOP_1;
when WHILE_LOOP_1 =>
-- Lock the mutex, push the address of the mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexAddr;
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_2;
when WHILE_LOOP_2 =>
-- Call mutex lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_TRYLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_WHILE_LOOP_3;
next_state <= WAIT_STATE;
when WHILE_LOOP_3 =>
-- We now have a lock on index, initiate the read on index
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_4;
when WHILE_LOOP_4 =>
index_next <= toUser_value;
-- increment index
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= structAddr + x"00000004";
thrd2intrfc_value <= toUser_value + x"00000001";
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_4a;
when WHILE_LOOP_4a =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexAddr;
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_5;
when WHILE_LOOP_5 =>
-- Unlock the mutex
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_WHILE_LOOP_6;
next_state <= WAIT_STATE;
when WHILE_LOOP_6 =>
-- Check to see if the index is over the size
if ( index < size ) then
-- More work to be done
-- Initiate the read of the X matrix
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= xAddr + (index(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_7;
else
-- we may exit
next_state <= FUNCTION_EXIT_1;
end if;
when WHILE_LOOP_7 =>
xVal_next <= ToUser_value;
-- Initiate the read of the Y matrix
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= yAddr + (index(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_8;
when WHILE_LOOP_8 =>
yVal_next <= ToUser_value;
next_state <= WHILE_LOOP_9;
when WHILE_LOOP_9 =>
-- Initiate the writing of the Z matrix
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= zAddr + (index(2 to 31) & "00");
thrd2intrfc_value <= xVal + yVal;
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_1;
-- Increment count
count_next <= count + x"00000001";
when FUNCTION_EXIT_1 =>
thrd2intrfc_value <= count;
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= FUNCTION_EXIT_2;
when FUNCTION_EXIT_2 =>
--Immediatly exit
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
thrd2intrfc_value <= Z32(0 to 15) & U_FUNCTION_RESET;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity quad_opamp_wa is
port (terminal n1, n2, output : electrical_vector(1 to 4));
end entity quad_opamp_wa ;
----------------------------------------------------------------
architecture slew_limited of quad_opamp_wa is
quantity vin across n1 to n2;
quantity vout across iout through output;
quantity vamp1 : real;
quantity vamp2 : real;
quantity vamp3 : real;
quantity vamp4 : real;
constant gain : real := 50.0;
begin
vamp1 == gain*vin(1);
vamp2 == gain*vin(2);
vamp3 == gain*vin(3);
vamp4 == gain*vin(4);
vout(1) == vamp1'slew(1.0e6,-1.0e6);
vout(2) == vamp2'slew(1.0e6,-1.0e6);
vout(3) == vamp3'slew(1.0e6,-1.0e6);
vout(4) == vamp4'slew(1.0e6,-1.0e6);
end architecture slew_limited ;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity quad_opamp_wa is
port (terminal n1, n2, output : electrical_vector(1 to 4));
end entity quad_opamp_wa ;
----------------------------------------------------------------
architecture slew_limited of quad_opamp_wa is
quantity vin across n1 to n2;
quantity vout across iout through output;
quantity vamp1 : real;
quantity vamp2 : real;
quantity vamp3 : real;
quantity vamp4 : real;
constant gain : real := 50.0;
begin
vamp1 == gain*vin(1);
vamp2 == gain*vin(2);
vamp3 == gain*vin(3);
vamp4 == gain*vin(4);
vout(1) == vamp1'slew(1.0e6,-1.0e6);
vout(2) == vamp2'slew(1.0e6,-1.0e6);
vout(3) == vamp3'slew(1.0e6,-1.0e6);
vout(4) == vamp4'slew(1.0e6,-1.0e6);
end architecture slew_limited ;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity quad_opamp_wa is
port (terminal n1, n2, output : electrical_vector(1 to 4));
end entity quad_opamp_wa ;
----------------------------------------------------------------
architecture slew_limited of quad_opamp_wa is
quantity vin across n1 to n2;
quantity vout across iout through output;
quantity vamp1 : real;
quantity vamp2 : real;
quantity vamp3 : real;
quantity vamp4 : real;
constant gain : real := 50.0;
begin
vamp1 == gain*vin(1);
vamp2 == gain*vin(2);
vamp3 == gain*vin(3);
vamp4 == gain*vin(4);
vout(1) == vamp1'slew(1.0e6,-1.0e6);
vout(2) == vamp2'slew(1.0e6,-1.0e6);
vout(3) == vamp3'slew(1.0e6,-1.0e6);
vout(4) == vamp4'slew(1.0e6,-1.0e6);
end architecture slew_limited ;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
pb_sw : in std_logic_vector (4 downto 1); -- push buttons
pll_clk : in std_ulogic; -- PLL clock
led : out std_logic_vector(8 downto 1);
flash_a : out std_logic_vector(20 downto 0);
flash_d : inout std_logic_vector(15 downto 0);
sdram_a : out std_logic_vector(11 downto 0);
sdram_d : inout std_logic_vector(31 downto 0);
sdram_ba : out std_logic_vector(3 downto 0);
sdram_dqm : out std_logic_vector(3 downto 0);
sdram_clk : inout std_ulogic;
sdram_cke : out std_ulogic; -- sdram clock enable
sdram_csn : out std_ulogic; -- sdram chip select
sdram_wen : out std_ulogic; -- sdram write enable
sdram_rasn : out std_ulogic; -- sdram ras
sdram_casn : out std_ulogic; -- sdram cas
uart1_txd : out std_ulogic;
uart1_rxd : in std_ulogic;
uart1_rts : out std_ulogic;
uart1_cts : in std_ulogic;
uart2_txd : out std_ulogic;
uart2_rxd : in std_ulogic;
uart2_rts : out std_ulogic;
uart2_cts : in std_ulogic;
flash_oen : out std_ulogic;
flash_wen : out std_ulogic;
flash_cen : out std_ulogic;
flash_byte : out std_ulogic;
flash_ready : in std_ulogic;
flash_rpn : out std_ulogic;
flash_wpn : out std_ulogic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(3 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(3 downto 0);
phy_tx_en : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_100 : in std_ulogic; -- 100 Mbit indicator
phy_rst_n : out std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
-- lcd_data : inout std_logic_vector(7 downto 0);
-- lcd_rs : out std_ulogic;
-- lcd_rw : out std_ulogic;
-- lcd_en : out std_ulogic;
-- lcd_backl : out std_ulogic;
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
smsc_addr : out std_logic_vector(14 downto 0);
smsc_data : inout std_logic_vector(31 downto 0);
smsc_nbe : out std_logic_vector(3 downto 0);
smsc_resetn : out std_ulogic;
smsc_ardy : in std_ulogic;
-- smsc_intr : in std_ulogic;
smsc_nldev : in std_ulogic;
smsc_nrd : out std_ulogic;
smsc_nwr : out std_ulogic;
smsc_ncs : out std_ulogic;
smsc_aen : out std_ulogic;
smsc_lclk : out std_ulogic;
smsc_wnr : out std_ulogic;
smsc_rdyrtn : out std_ulogic;
smsc_cycle : out std_ulogic;
smsc_nads : out std_ulogic
);
end;
architecture rtl of leon3mp is
signal vcc, gnd : std_logic_vector(7 downto 0);
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_ulogic;
signal lclk, pci_lclk, sdfb : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal resetn : std_ulogic;
signal pbsw : std_logic_vector(4 downto 1);
signal ledo : std_logic_vector(8 downto 1);
signal memi : memory_in_type;
signal memo : memory_out_type;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal s_eth_din : std_logic_vector(31 downto 0);
constant ahbmmax : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+ CFG_GRETH;
constant BOARD_FREQ : integer := 50000; -- board frequency in KHz
constant CPU_FREQ : integer := (BOARD_FREQ*CFG_CLKMUL)/CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
sdram_clk_pad : skew_outpad
generic map (tech => padtech, slew => 1, strength => 24, skew => -60)
port map (sdram_clk, sdclkl, rstn);
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
resetn <= pbsw(4);
ledo(2) <= not cgo.clklock;
ledo(3) <= pbsw(3);
clk_pad : clkpad generic map (tech => padtech) port map (pll_clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
nahbm => ahbmmax, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
ledo(8) <= dbgo(0).error;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1'; dsui.break <= pbsw(1); ledo(1) <= not dsuo.active;
end generate;
end generate;
nodcom : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= u2i.rxd; u2o.txd <= duo.txd; u2o.rtsn <= gnd(0);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- PROM/SDRAM Memory controller ------------------------------------
----------------------------------------------------------------------
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111";
memi.bwidth <= "00" when CFG_MCTRL_RAM16BIT = 0 else "01";
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : entity work.smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4+CFG_MCTRL_5CS, sden => CFG_MCTRL_SDEN,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS,
sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0),
wpo, sdo, s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe, s_eth_din);
addr_pad : outpadv generic map (width => 21, tech => padtech)
port map (flash_a(20 downto 0), memo.address(21 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (flash_cen, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (flash_wen, memo.writen);
rom8 : if CFG_MCTRL_RAM16BIT = 0 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (flash_d(7 downto 0), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
data15_pad : iopad generic map (tech => padtech)
port map (flash_d(15), memo.address(0), gnd(0), open);
end generate;
rom16 : if CFG_MCTRL_RAM16BIT = 1 generate
data_pad : iopadv generic map (tech => padtech, width => 16)
port map (flash_d(15 downto 0), memo.data(31 downto 16),
memo.bdrive(0), memi.data(31 downto 16));
end generate;
sa_pad : outpadv generic map (width => 12, tech => padtech)
port map (sdram_a, memo.sa(11 downto 0));
sba1_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdram_ba(1 downto 0), memo.sa(14 downto 13));
sba2_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdram_ba(3 downto 2), memo.sa(14 downto 13));
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sdram_d(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
end generate;
sdcke_pad : outpad generic map (tech => padtech)
port map (sdram_cke, sdo.sdcke(0));
sdwen_pad : outpad generic map (tech => padtech)
port map (sdram_wen, sdo.sdwen);
sdcsn_pad : outpad generic map (tech => padtech)
port map (sdram_csn, sdo.sdcsn(0));
sdras_pad : outpad generic map (tech => padtech)
port map (sdram_rasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdram_casn, sdo.casn);
sddqm_pad : outpadv generic map (width => 4, tech => padtech)
port map (sdram_dqm, sdo.dqm(3 downto 0));
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech)
port map (sdram_cke, gnd(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (sdram_csn, vcc(0));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 4, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(4));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(4) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua1rx_pad : inpad generic map (tech => padtech) port map (uart1_rxd, u1i.rxd);
ua1tx_pad : outpad generic map (tech => padtech) port map (uart1_txd, u1o.txd);
ua1cts_pad : inpad generic map (tech => padtech) port map (uart1_cts, u1i.ctsn);
ua1rts_pad : outpad generic map (tech => padtech) port map (uart1_rts, u1o.rtsn);
ua2 : if (CFG_UART2_ENABLE /= 0) and (CFG_AHB_UART = 0) generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.extclk <= '0';
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
ua2rx_pad : inpad generic map (tech => padtech) port map (uart2_rxd, u2i.rxd);
ua2tx_pad : outpad generic map (tech => padtech) port map (uart2_txd, u2o.txd);
ua2cts_pad : inpad generic map (tech => padtech) port map (uart2_cts, u2i.ctsn);
ua2rts_pad : outpad generic map (tech => padtech) port map (uart2_rts, u2o.rtsn);
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
end generate;
ethpads : if CFG_GRETH = 0 generate -- no eth
etho <= eth_out_none;
end generate;
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 0)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 0)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (phy_rx_data, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (phy_tx_data, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
ereset_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
can_loopback : if CFG_CANLOOP = 1 generate
can_lrx <= can_ltx;
end generate;
can_pads : if CFG_CANLOOP = 0 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- I/O interface ---------------------------------------------------
-----------------------------------------------------------------------
pb_sw_pad : inpadv generic map (width => 4, tech => padtech)
port map (pb_sw, pbsw);
led_pad : outpadv generic map (width => 8, tech => padtech)
port map (led, ledo);
rom8 : if CFG_MCTRL_RAM16BIT = 0 generate
byte_pad : outpad generic map (tech => padtech) port map (flash_byte, gnd(0));
end generate;
rom16 : if CFG_MCTRL_RAM16BIT = 1 generate
byte_pad : outpad generic map (tech => padtech) port map (flash_byte, vcc(0));
end generate;
rpn_pad : outpad generic map (tech => padtech) port map (flash_rpn, rstn);
wpn_pad : outpad generic map (tech => padtech) port map (flash_wpn, vcc(0));
ready_pad : inpad generic map (tech => padtech) port map (flash_ready, open);
smsc_data_pads : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (smsc_data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), s_eth_din(31-i*8 downto 24-i*8));
end generate;
smsc_addr_pad : outpadv generic map (tech => padtech, width => 15)
port map (smsc_addr, memo.address(15 downto 1));
smsc_nbe_pad : outpadv generic map (tech => padtech, width => 4)
port map (smsc_nbe, s_eth_nbe);
smsc_reset_pad : outpad generic map (tech => padtech)
port map (smsc_resetn, rstn);
smsc_nrd_pad : outpad generic map (tech => padtech)
port map (smsc_nrd, s_eth_readn);
smsc_nwr_pad : outpad generic map (tech => padtech)
port map (smsc_nwr, s_eth_writen);
smsc_ncs_pad : outpad generic map (tech => padtech)
port map (smsc_ncs, memo.iosn);
smsc_aen_pad : outpad generic map (tech => padtech)
port map (smsc_aen, s_eth_aen);
smsc_lclk_pad : outpad generic map (tech => padtech)
port map (smsc_lclk, vcc(0));
smsc_wnr_pad : outpad generic map (tech => padtech)
port map (smsc_wnr, vcc(0));
smsc_rdyrtn_pad : outpad generic map (tech => padtech)
port map (smsc_rdyrtn, vcc(0));
smsc_cycle_pad : outpad generic map (tech => padtech)
port map (smsc_cycle, vcc(0));
smsc_nads_pad : outpad generic map (tech => padtech)
port map (smsc_nads, gnd(0));
-- lcd_data_pad : iopadv generic map (width => 8, tech => padtech)
-- port map (lcd_data, nuo.lcd_data, nuo.lcd_ben, nui.lcd_data);
-- lcd_rs_pad : outpad generic map (tech => padtech)
-- port map (lcd_rs, nuo.lcd_rs);
-- lcd_rw_pad : outpad generic map (tech => padtech)
-- port map (lcd_rw, nuo.lcd_rw );
-- lcd_en_pad : outpad generic map (tech => padtech)
-- port map (lcd_en, nuo.lcd_en);
-- lcd_backl_pad : outpad generic map (tech => padtech)
-- port map (lcd_backl, nuo.lcd_backl);
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Nuhorizon SP3 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1278.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01278ent IS
END c08s04b00x00p04n01i01278ent;
ARCHITECTURE c08s04b00x00p04n01i01278arch OF c08s04b00x00p04n01i01278ent IS
signal S1 : integer ;
BEGIN
TESTING: PROCESS
BEGIN
abs S1 <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01278 - Simple expressions are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01278arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1278.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01278ent IS
END c08s04b00x00p04n01i01278ent;
ARCHITECTURE c08s04b00x00p04n01i01278arch OF c08s04b00x00p04n01i01278ent IS
signal S1 : integer ;
BEGIN
TESTING: PROCESS
BEGIN
abs S1 <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01278 - Simple expressions are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01278arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1278.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01278ent IS
END c08s04b00x00p04n01i01278ent;
ARCHITECTURE c08s04b00x00p04n01i01278arch OF c08s04b00x00p04n01i01278ent IS
signal S1 : integer ;
BEGIN
TESTING: PROCESS
BEGIN
abs S1 <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01278 - Simple expressions are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01278arch;
|
----------------------------------------------------------------------------
---- Create Date: 14:30:08 07/28/2010 ----
---- Design Name: lfsr_pkg ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- This is the package file used in the lfsr_randgen project.The ----
---- package contain the function for XORing bits from various tap ----
---- locations depending on the generic parameter(width of lfsr ) ----
---- ----
----------------------------------------------------------------------------
---- ----
---- This file is a part of the lfsr_randgen project at ----
---- http://www.opencores.org/ ----
---- ----
---- Author(s): ----
---- Vipin Lal, [email protected] ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2010 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lfsr_pkg is
function xor_gates( random : std_logic_vector) return std_logic;
end lfsr_pkg;
--Package body starts from here.
package body lfsr_pkg is
--function for XORing from tap values.
function xor_gates( random : std_logic_vector ) return std_logic is
variable xor_out : std_logic:='0';
variable rand : std_logic_vector(random'length-1 downto 0):=random;
begin
if(rand'length = 3) then --3
xor_out := rand(2) xor rand(1);
elsif(rand'length = 2) then --2
xor_out := rand(1) xor rand(0);
elsif(rand'length = 4) then --4
xor_out := rand(3) xor rand(2);
elsif(rand'length = 5) then --5
xor_out := rand(4) xor rand(2);
elsif(rand'length = 6) then --6
xor_out := rand(5) xor rand(4);
elsif(rand'length = 7) then --7
xor_out := rand(6) xor rand(5);
elsif(rand'length = 8) then --8
xor_out := rand(7) xor rand(5) xor rand(4) xor rand(3);
elsif(rand'length = 9) then --9
xor_out := rand(8) xor rand(4);
elsif(rand'length = 10)then --10
xor_out := rand(9) xor rand(6);
elsif(rand'length =11) then --11
xor_out := rand(10) xor rand(8);
elsif(rand'length = 12) then --12
xor_out := rand(11) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 13) then --13
xor_out := rand(12) xor rand(3) xor rand(2) xor rand(0);
elsif(rand'length = 14) then --14
xor_out := rand(13) xor rand(4) xor rand(2) xor rand(0);
elsif(rand'length = 15) then --15
xor_out := rand(14) xor rand(13);
elsif(rand'length = 16) then --16
xor_out := rand(15) xor rand(14) xor rand(12) xor rand(3);
elsif(rand'length = 17) then --17
xor_out := rand(16) xor rand(13);
elsif(rand'length = 18) then --18
xor_out := rand(17) xor rand(10);
elsif(rand'length = 19) then --19
xor_out := rand(18) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 20) then --20
xor_out := rand(19) xor rand(16);
elsif(rand'length = 21) then --21
xor_out := rand(20) xor rand(18);
elsif(rand'length = 22) then --22
xor_out := rand(21) xor rand(20);
elsif(rand'length = 23) then --23
xor_out := rand(22) xor rand(17);
elsif(rand'length = 24) then --24
xor_out := rand(23) xor rand(22) xor rand(21) xor rand(16);
elsif(rand'length = 25) then --25
xor_out := rand(24) xor rand(21);
elsif(rand'length = 26) then --26
xor_out := rand(25) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 27) then --27
xor_out := rand(26) xor rand(4) xor rand(1) xor rand(0);
elsif(rand'length = 28) then --28
xor_out := rand(27) xor rand(24);
elsif(rand'length = 29) then --29
xor_out := rand(28) xor rand(26);
elsif(rand'length = 30) then --30
xor_out := rand(29) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 31) then --31
xor_out := rand(30) xor rand(27);
elsif(rand'length = 32) then --32
xor_out := rand(31) xor rand(21) xor rand(1) xor rand(0);
elsif(rand'length = 33) then --33
xor_out := rand(32) xor rand(19);
elsif(rand'length = 34) then --34
xor_out := rand(33) xor rand(26) xor rand(1) xor rand(0);
elsif(rand'length = 35) then --35
xor_out := rand(34) xor rand(32);
elsif(rand'length = 36) then --36
xor_out := rand(35) xor rand(24);
elsif(rand'length = 37) then --37
xor_out := rand(36) xor rand(4) xor rand(3) xor rand(2) xor rand(1) xor rand(0);
elsif(rand'length = 38) then --38
xor_out := rand(37) xor rand(5) xor rand(4) xor rand(0);
elsif(rand'length = 39) then --39
xor_out := rand(38) xor rand(34);
elsif(rand'length = 40) then --40
xor_out := rand(39) xor rand(37) xor rand(20) xor rand(18);
elsif(rand'length = 41) then --41
xor_out := rand(40) xor rand(37);
elsif(rand'length = 42) then --42
xor_out := rand(41) xor rand(40) xor rand(19) xor rand(18);
elsif(rand'length = 43) then --43
xor_out := rand(42) xor rand(41) xor rand(37) xor rand(36);
elsif(rand'length = 44) then --44
xor_out := rand(43) xor rand(42) xor rand(17) xor rand(16);
elsif(rand'length = 45) then --45
xor_out := rand(44) xor rand(43) xor rand(41) xor rand(40);
elsif(rand'length = 46) then --46
xor_out := rand(45) xor rand(44) xor rand(25) xor rand(24);
elsif(rand'length = 47) then --47
xor_out := rand(46) xor rand(41);
elsif(rand'length = 48) then --48
xor_out := rand(47) xor rand(46) xor rand(20) xor rand(19);
elsif(rand'length = 49) then --49
xor_out := rand(48) xor rand(39);
elsif(rand'length = 50) then --50
xor_out := rand(49) xor rand(48) xor rand(23) xor rand(22);
elsif(rand'length = 51) then --51
xor_out := rand(50) xor rand(49) xor rand(35) xor rand(34);
elsif(rand'length = 52) then --52
xor_out := rand(51) xor rand(48);
elsif(rand'length = 53) then --53
xor_out := rand(52) xor rand(51) xor rand(37) xor rand(36);
elsif(rand'length = 54) then --54
xor_out := rand(53) xor rand(52) xor rand(17) xor rand(16);
elsif(rand'length = 55) then --55
xor_out := rand(54) xor rand(30);
elsif(rand'length = 56) then --56
xor_out := rand(55) xor rand(54) xor rand(34) xor rand(33);
elsif(rand'length = 57) then --57
xor_out := rand(56) xor rand(49);
elsif(rand'length = 58) then --58
xor_out := rand(57) xor rand(38);
elsif(rand'length = 59) then --59
xor_out := rand(58) xor rand(57) xor rand(37) xor rand(36);
elsif(rand'length = 60) then --60
xor_out := rand(59) xor rand(58);
elsif(rand'length = 61) then --61
xor_out := rand(60) xor rand(59) xor rand(45) xor rand(44);
elsif(rand'length = 62) then --62
xor_out := rand(61) xor rand(60) xor rand(5) xor rand(4);
elsif(rand'length = 63) then --63
xor_out := rand(62) xor rand(61);
elsif(rand'length = 64) then --64
xor_out := rand(63) xor rand(62) xor rand(60) xor rand(59);
elsif(rand'length = 65) then --65
xor_out := rand(64) xor rand(46);
elsif(rand'length = 66) then --66
xor_out := rand(65) xor rand(64) xor rand(56) xor rand(55);
elsif(rand'length = 67) then --67
xor_out := rand(66) xor rand(65) xor rand(57) xor rand(56);
elsif(rand'length = 68) then --68
xor_out := rand(67) xor rand(58);
elsif(rand'length = 69) then --69
xor_out := rand(68) xor rand(66) xor rand(41) xor rand(39);
elsif(rand'length = 70) then --70
xor_out := rand(69) xor rand(68) xor rand(54) xor rand(53);
elsif(rand'length = 71) then --71
xor_out := rand(70) xor rand(64);
elsif(rand'length = 72) then --72
xor_out := rand(71) xor rand(65) xor rand(24) xor rand(18);
elsif(rand'length = 73) then --73
xor_out := rand(72) xor rand(47);
elsif(rand'length = 74) then --74
xor_out := rand(73) xor rand(72) xor rand(58) xor rand(57);
elsif(rand'length = 75) then --75
xor_out := rand(74) xor rand(73) xor rand(64) xor rand(63);
elsif(rand'length = 76) then --76
xor_out := rand(75) xor rand(74) xor rand(40) xor rand(39);
elsif(rand'length = 77) then --77
xor_out := rand(76) xor rand(75) xor rand(46) xor rand(45);
elsif(rand'length = 78) then --78
xor_out := rand(77) xor rand(76) xor rand(58) xor rand(57);
elsif(rand'length = 79) then --79
xor_out := rand(78) xor rand(69);
elsif(rand'length = 80) then --80
xor_out := rand(79) xor rand(78) xor rand(42) xor rand(41);
elsif(rand'length = 81) then --81
xor_out := rand(80) xor rand(76);
elsif(rand'length = 82) then --82
xor_out := rand(81) xor rand(78) xor rand(46) xor rand(43);
elsif(rand'length = 83) then --83
xor_out := rand(82) xor rand(81) xor rand(37) xor rand(36);
elsif(rand'length = 84) then --84
xor_out := rand(83) xor rand(70);
elsif(rand'length = 85) then --85
xor_out := rand(84) xor rand(83) xor rand(57) xor rand(56);
elsif(rand'length = 86) then --86
xor_out := rand(85) xor rand(84) xor rand(73) xor rand(72);
elsif(rand'length = 87) then --87
xor_out := rand(86) xor rand(73);
elsif(rand'length = 88) then --88
xor_out := rand(87) xor rand(86) xor rand(16) xor rand(15);
elsif(rand'length = 89) then --89
xor_out := rand(88) xor rand(50);
elsif(rand'length = 90) then --90
xor_out := rand(89) xor rand(88) xor rand(71) xor rand(70);
elsif(rand'length = 91) then --91
xor_out := rand(90) xor rand(89) xor rand(7) xor rand(6);
elsif(rand'length = 92) then --92
xor_out := rand(91) xor rand(90) xor rand(79) xor rand(78);
elsif(rand'length = 93) then --93
xor_out := rand(92) xor rand(90);
elsif(rand'length = 94) then --94
xor_out := rand(93) xor rand(72);
elsif(rand'length = 95) then --95
xor_out := rand(94) xor rand(83);
elsif(rand'length = 96) then --96
xor_out := rand(95) xor rand(93) xor rand(48) xor rand(46);
elsif(rand'length = 97) then --97
xor_out := rand(96) xor rand(90);
elsif(rand'length = 98) then --98
xor_out := rand(97) xor rand(86);
elsif(rand'length = 99) then --99
xor_out := rand(98) xor rand(96) xor rand(53) xor rand(51);
elsif(rand'length = 100) then --100
xor_out := rand(99) xor rand(62);
elsif(rand'length = 101) then --101
xor_out := rand(100) xor rand(99) xor rand(94) xor rand(93);
elsif(rand'length = 102) then --102
xor_out := rand(101) xor rand(100) xor rand(35) xor rand(34);
elsif(rand'length = 103) then --103
xor_out := rand(102) xor rand(93);
elsif(rand'length = 104) then --104
xor_out := rand(103) xor rand(102) xor rand(93) xor rand(92);
elsif(rand'length = 105) then --105
xor_out := rand(104) xor rand(88);
elsif(rand'length = 106) then --106
xor_out := rand(105) xor rand(90);
elsif(rand'length = 107) then --107
xor_out := rand(106) xor rand(104) xor rand(43) xor rand(41);
elsif(rand'length = 108) then --108
xor_out := rand(107) xor rand(76);
elsif(rand'length = 109) then --109
xor_out := rand(108) xor rand(107) xor rand(102) xor rand(101);
elsif(rand'length = 110)then --110
xor_out := rand(109) xor rand(108) xor rand(97) xor rand(96);
elsif(rand'length = 111) then --111
xor_out := rand(110) xor rand(100);
elsif(rand'length = 112) then --112
xor_out := rand(111) xor rand(109) xor rand(68) xor rand(66);
elsif(rand'length = 113) then --113
xor_out := rand(112) xor rand(103);
elsif(rand'length = 114) then --114
xor_out := rand(113) xor rand(112) xor rand(32) xor rand(31);
elsif(rand'length = 115) then --115
xor_out := rand(114) xor rand(113) xor rand(100) xor rand(99);
elsif(rand'length = 116) then --116
xor_out := rand(115) xor rand(114) xor rand(45) xor rand(44);
elsif(rand'length = 117) then --117
xor_out := rand(116) xor rand(114) xor rand(98) xor rand(96);
elsif(rand'length = 118) then --118
xor_out := rand(117) xor rand(84);
elsif(rand'length = 119) then --119
xor_out := rand(118) xor rand(110);
elsif(rand'length = 120) then --120
xor_out := rand(119) xor rand(112) xor rand(8) xor rand(1);
elsif(rand'length = 121) then --121
xor_out := rand(120) xor rand(102);
elsif(rand'length = 122) then --122
xor_out := rand(121) xor rand(120) xor rand(62) xor rand(61);
elsif(rand'length = 123) then --123
xor_out := rand(122) xor rand(120);
elsif(rand'length = 124) then --124
xor_out := rand(123) xor rand(86);
elsif(rand'length = 125) then --125
xor_out := rand(124) xor rand(123) xor rand(17) xor rand(16);
elsif(rand'length = 126) then --126
xor_out := rand(125) xor rand(124) xor rand(89) xor rand(88);
elsif(rand'length = 127) then --127
xor_out := rand(126) xor rand(125);
elsif(rand'length = 128) then --128
xor_out := rand(127) xor rand(125) xor rand(100) xor rand(98);
elsif(rand'length = 129) then --129
xor_out := rand(128) xor rand(123);
elsif(rand'length = 130) then --130
xor_out := rand(129) xor rand(126);
elsif(rand'length = 131) then --131
xor_out := rand(130) xor rand(129) xor rand(83) xor rand(82);
elsif(rand'length = 132) then --132
xor_out := rand(131) xor rand(102);
elsif(rand'length = 133) then --133
xor_out := rand(132) xor rand(131) xor rand(81) xor rand(80);
elsif(rand'length = 134) then --134
xor_out := rand(133) xor rand(76);
elsif(rand'length = 135) then --135
xor_out := rand(134) xor rand(123);
elsif(rand'length = 136) then --136
xor_out := rand(135) xor rand(134) xor rand(10) xor rand(9);
elsif(rand'length = 137) then --137
xor_out := rand(136) xor rand(115);
elsif(rand'length = 138) then --138
xor_out := rand(137) xor rand(136) xor rand(130) xor rand(129);
elsif(rand'length = 139) then --139
xor_out := rand(138) xor rand(135) xor rand(133) xor rand(130);
elsif(rand'length = 140) then --140
xor_out := rand(139) xor rand(110);
elsif(rand'length = 141) then --141
xor_out := rand(140) xor rand(139) xor rand(109) xor rand(108);
elsif(rand'length = 142) then --142
xor_out := rand(141) xor rand(120);
elsif(rand'length = 143) then --143
xor_out := rand(142) xor rand(141) xor rand(122) xor rand(121);
elsif(rand'length = 144) then --144
xor_out := rand(143) xor rand(142) xor rand(74) xor rand(73);
elsif(rand'length = 145) then --145
xor_out := rand(144) xor rand(92);
elsif(rand'length = 146) then --146
xor_out := rand(145) xor rand(144) xor rand(86) xor rand(85);
elsif(rand'length = 147) then --147
xor_out := rand(146) xor rand(145) xor rand(109) xor rand(108);
elsif(rand'length = 148) then --148
xor_out := rand(147) xor rand(120);
elsif(rand'length = 149) then --149
xor_out := rand(148) xor rand(147) xor rand(39) xor rand(38);
elsif(rand'length = 150) then --150
xor_out := rand(149) xor rand(96);
elsif(rand'length = 151) then --151
xor_out := rand(150) xor rand(147);
elsif(rand'length = 152) then --152
xor_out := rand(151) xor rand(150) xor rand(86) xor rand(85);
elsif(rand'length = 153) then --153
xor_out := rand(152) xor rand(151);
elsif(rand'length = 154) then --154
xor_out := rand(153) xor rand(151) xor rand(26) xor rand(24);
elsif(rand'length = 155) then --155
xor_out := rand(154) xor rand(153) xor rand(123) xor rand(122);
elsif(rand'length = 156) then --156
xor_out := rand(155) xor rand(154) xor rand(40) xor rand(39);
elsif(rand'length = 157) then --157
xor_out := rand(156) xor rand(155) xor rand(130) xor rand(129);
elsif(rand'length = 158) then --158
xor_out := rand(157) xor rand(156) xor rand(131) xor rand(130);
elsif(rand'length = 159) then --159
xor_out := rand(158) xor rand(127);
elsif(rand'length = 160) then --160
xor_out := rand(159) xor rand(158) xor rand(141) xor rand(140);
elsif(rand'length = 161) then --161
xor_out := rand(160) xor rand(142);
elsif(rand'length = 162) then --162
xor_out := rand(161) xor rand(160) xor rand(74) xor rand(73);
elsif(rand'length = 163) then --163
xor_out := rand(162) xor rand(161) xor rand(103) xor rand(102);
elsif(rand'length = 164) then --164
xor_out := rand(163) xor rand(162) xor rand(150) xor rand(149);
elsif(rand'length = 165) then --165
xor_out := rand(164) xor rand(163) xor rand(134) xor rand(133);
elsif(rand'length = 166) then --166
xor_out := rand(165) xor rand(164) xor rand(127) xor rand(126);
elsif(rand'length = 167) then --167
xor_out := rand(166) xor rand(160);
elsif(rand'length = 168) then --168
xor_out := rand(167) xor rand(165) xor rand(152) xor rand(150);
end if;
return xor_out;
end xor_gates;
--END function for XORing using tap values.
end lfsr_pkg;
--End of the package.
|
----------------------------------------------------------------------------
---- Create Date: 14:30:08 07/28/2010 ----
---- Design Name: lfsr_pkg ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- This is the package file used in the lfsr_randgen project.The ----
---- package contain the function for XORing bits from various tap ----
---- locations depending on the generic parameter(width of lfsr ) ----
---- ----
----------------------------------------------------------------------------
---- ----
---- This file is a part of the lfsr_randgen project at ----
---- http://www.opencores.org/ ----
---- ----
---- Author(s): ----
---- Vipin Lal, [email protected] ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2010 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lfsr_pkg is
function xor_gates( random : std_logic_vector) return std_logic;
end lfsr_pkg;
--Package body starts from here.
package body lfsr_pkg is
--function for XORing from tap values.
function xor_gates( random : std_logic_vector ) return std_logic is
variable xor_out : std_logic:='0';
variable rand : std_logic_vector(random'length-1 downto 0):=random;
begin
if(rand'length = 3) then --3
xor_out := rand(2) xor rand(1);
elsif(rand'length = 2) then --2
xor_out := rand(1) xor rand(0);
elsif(rand'length = 4) then --4
xor_out := rand(3) xor rand(2);
elsif(rand'length = 5) then --5
xor_out := rand(4) xor rand(2);
elsif(rand'length = 6) then --6
xor_out := rand(5) xor rand(4);
elsif(rand'length = 7) then --7
xor_out := rand(6) xor rand(5);
elsif(rand'length = 8) then --8
xor_out := rand(7) xor rand(5) xor rand(4) xor rand(3);
elsif(rand'length = 9) then --9
xor_out := rand(8) xor rand(4);
elsif(rand'length = 10)then --10
xor_out := rand(9) xor rand(6);
elsif(rand'length =11) then --11
xor_out := rand(10) xor rand(8);
elsif(rand'length = 12) then --12
xor_out := rand(11) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 13) then --13
xor_out := rand(12) xor rand(3) xor rand(2) xor rand(0);
elsif(rand'length = 14) then --14
xor_out := rand(13) xor rand(4) xor rand(2) xor rand(0);
elsif(rand'length = 15) then --15
xor_out := rand(14) xor rand(13);
elsif(rand'length = 16) then --16
xor_out := rand(15) xor rand(14) xor rand(12) xor rand(3);
elsif(rand'length = 17) then --17
xor_out := rand(16) xor rand(13);
elsif(rand'length = 18) then --18
xor_out := rand(17) xor rand(10);
elsif(rand'length = 19) then --19
xor_out := rand(18) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 20) then --20
xor_out := rand(19) xor rand(16);
elsif(rand'length = 21) then --21
xor_out := rand(20) xor rand(18);
elsif(rand'length = 22) then --22
xor_out := rand(21) xor rand(20);
elsif(rand'length = 23) then --23
xor_out := rand(22) xor rand(17);
elsif(rand'length = 24) then --24
xor_out := rand(23) xor rand(22) xor rand(21) xor rand(16);
elsif(rand'length = 25) then --25
xor_out := rand(24) xor rand(21);
elsif(rand'length = 26) then --26
xor_out := rand(25) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 27) then --27
xor_out := rand(26) xor rand(4) xor rand(1) xor rand(0);
elsif(rand'length = 28) then --28
xor_out := rand(27) xor rand(24);
elsif(rand'length = 29) then --29
xor_out := rand(28) xor rand(26);
elsif(rand'length = 30) then --30
xor_out := rand(29) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 31) then --31
xor_out := rand(30) xor rand(27);
elsif(rand'length = 32) then --32
xor_out := rand(31) xor rand(21) xor rand(1) xor rand(0);
elsif(rand'length = 33) then --33
xor_out := rand(32) xor rand(19);
elsif(rand'length = 34) then --34
xor_out := rand(33) xor rand(26) xor rand(1) xor rand(0);
elsif(rand'length = 35) then --35
xor_out := rand(34) xor rand(32);
elsif(rand'length = 36) then --36
xor_out := rand(35) xor rand(24);
elsif(rand'length = 37) then --37
xor_out := rand(36) xor rand(4) xor rand(3) xor rand(2) xor rand(1) xor rand(0);
elsif(rand'length = 38) then --38
xor_out := rand(37) xor rand(5) xor rand(4) xor rand(0);
elsif(rand'length = 39) then --39
xor_out := rand(38) xor rand(34);
elsif(rand'length = 40) then --40
xor_out := rand(39) xor rand(37) xor rand(20) xor rand(18);
elsif(rand'length = 41) then --41
xor_out := rand(40) xor rand(37);
elsif(rand'length = 42) then --42
xor_out := rand(41) xor rand(40) xor rand(19) xor rand(18);
elsif(rand'length = 43) then --43
xor_out := rand(42) xor rand(41) xor rand(37) xor rand(36);
elsif(rand'length = 44) then --44
xor_out := rand(43) xor rand(42) xor rand(17) xor rand(16);
elsif(rand'length = 45) then --45
xor_out := rand(44) xor rand(43) xor rand(41) xor rand(40);
elsif(rand'length = 46) then --46
xor_out := rand(45) xor rand(44) xor rand(25) xor rand(24);
elsif(rand'length = 47) then --47
xor_out := rand(46) xor rand(41);
elsif(rand'length = 48) then --48
xor_out := rand(47) xor rand(46) xor rand(20) xor rand(19);
elsif(rand'length = 49) then --49
xor_out := rand(48) xor rand(39);
elsif(rand'length = 50) then --50
xor_out := rand(49) xor rand(48) xor rand(23) xor rand(22);
elsif(rand'length = 51) then --51
xor_out := rand(50) xor rand(49) xor rand(35) xor rand(34);
elsif(rand'length = 52) then --52
xor_out := rand(51) xor rand(48);
elsif(rand'length = 53) then --53
xor_out := rand(52) xor rand(51) xor rand(37) xor rand(36);
elsif(rand'length = 54) then --54
xor_out := rand(53) xor rand(52) xor rand(17) xor rand(16);
elsif(rand'length = 55) then --55
xor_out := rand(54) xor rand(30);
elsif(rand'length = 56) then --56
xor_out := rand(55) xor rand(54) xor rand(34) xor rand(33);
elsif(rand'length = 57) then --57
xor_out := rand(56) xor rand(49);
elsif(rand'length = 58) then --58
xor_out := rand(57) xor rand(38);
elsif(rand'length = 59) then --59
xor_out := rand(58) xor rand(57) xor rand(37) xor rand(36);
elsif(rand'length = 60) then --60
xor_out := rand(59) xor rand(58);
elsif(rand'length = 61) then --61
xor_out := rand(60) xor rand(59) xor rand(45) xor rand(44);
elsif(rand'length = 62) then --62
xor_out := rand(61) xor rand(60) xor rand(5) xor rand(4);
elsif(rand'length = 63) then --63
xor_out := rand(62) xor rand(61);
elsif(rand'length = 64) then --64
xor_out := rand(63) xor rand(62) xor rand(60) xor rand(59);
elsif(rand'length = 65) then --65
xor_out := rand(64) xor rand(46);
elsif(rand'length = 66) then --66
xor_out := rand(65) xor rand(64) xor rand(56) xor rand(55);
elsif(rand'length = 67) then --67
xor_out := rand(66) xor rand(65) xor rand(57) xor rand(56);
elsif(rand'length = 68) then --68
xor_out := rand(67) xor rand(58);
elsif(rand'length = 69) then --69
xor_out := rand(68) xor rand(66) xor rand(41) xor rand(39);
elsif(rand'length = 70) then --70
xor_out := rand(69) xor rand(68) xor rand(54) xor rand(53);
elsif(rand'length = 71) then --71
xor_out := rand(70) xor rand(64);
elsif(rand'length = 72) then --72
xor_out := rand(71) xor rand(65) xor rand(24) xor rand(18);
elsif(rand'length = 73) then --73
xor_out := rand(72) xor rand(47);
elsif(rand'length = 74) then --74
xor_out := rand(73) xor rand(72) xor rand(58) xor rand(57);
elsif(rand'length = 75) then --75
xor_out := rand(74) xor rand(73) xor rand(64) xor rand(63);
elsif(rand'length = 76) then --76
xor_out := rand(75) xor rand(74) xor rand(40) xor rand(39);
elsif(rand'length = 77) then --77
xor_out := rand(76) xor rand(75) xor rand(46) xor rand(45);
elsif(rand'length = 78) then --78
xor_out := rand(77) xor rand(76) xor rand(58) xor rand(57);
elsif(rand'length = 79) then --79
xor_out := rand(78) xor rand(69);
elsif(rand'length = 80) then --80
xor_out := rand(79) xor rand(78) xor rand(42) xor rand(41);
elsif(rand'length = 81) then --81
xor_out := rand(80) xor rand(76);
elsif(rand'length = 82) then --82
xor_out := rand(81) xor rand(78) xor rand(46) xor rand(43);
elsif(rand'length = 83) then --83
xor_out := rand(82) xor rand(81) xor rand(37) xor rand(36);
elsif(rand'length = 84) then --84
xor_out := rand(83) xor rand(70);
elsif(rand'length = 85) then --85
xor_out := rand(84) xor rand(83) xor rand(57) xor rand(56);
elsif(rand'length = 86) then --86
xor_out := rand(85) xor rand(84) xor rand(73) xor rand(72);
elsif(rand'length = 87) then --87
xor_out := rand(86) xor rand(73);
elsif(rand'length = 88) then --88
xor_out := rand(87) xor rand(86) xor rand(16) xor rand(15);
elsif(rand'length = 89) then --89
xor_out := rand(88) xor rand(50);
elsif(rand'length = 90) then --90
xor_out := rand(89) xor rand(88) xor rand(71) xor rand(70);
elsif(rand'length = 91) then --91
xor_out := rand(90) xor rand(89) xor rand(7) xor rand(6);
elsif(rand'length = 92) then --92
xor_out := rand(91) xor rand(90) xor rand(79) xor rand(78);
elsif(rand'length = 93) then --93
xor_out := rand(92) xor rand(90);
elsif(rand'length = 94) then --94
xor_out := rand(93) xor rand(72);
elsif(rand'length = 95) then --95
xor_out := rand(94) xor rand(83);
elsif(rand'length = 96) then --96
xor_out := rand(95) xor rand(93) xor rand(48) xor rand(46);
elsif(rand'length = 97) then --97
xor_out := rand(96) xor rand(90);
elsif(rand'length = 98) then --98
xor_out := rand(97) xor rand(86);
elsif(rand'length = 99) then --99
xor_out := rand(98) xor rand(96) xor rand(53) xor rand(51);
elsif(rand'length = 100) then --100
xor_out := rand(99) xor rand(62);
elsif(rand'length = 101) then --101
xor_out := rand(100) xor rand(99) xor rand(94) xor rand(93);
elsif(rand'length = 102) then --102
xor_out := rand(101) xor rand(100) xor rand(35) xor rand(34);
elsif(rand'length = 103) then --103
xor_out := rand(102) xor rand(93);
elsif(rand'length = 104) then --104
xor_out := rand(103) xor rand(102) xor rand(93) xor rand(92);
elsif(rand'length = 105) then --105
xor_out := rand(104) xor rand(88);
elsif(rand'length = 106) then --106
xor_out := rand(105) xor rand(90);
elsif(rand'length = 107) then --107
xor_out := rand(106) xor rand(104) xor rand(43) xor rand(41);
elsif(rand'length = 108) then --108
xor_out := rand(107) xor rand(76);
elsif(rand'length = 109) then --109
xor_out := rand(108) xor rand(107) xor rand(102) xor rand(101);
elsif(rand'length = 110)then --110
xor_out := rand(109) xor rand(108) xor rand(97) xor rand(96);
elsif(rand'length = 111) then --111
xor_out := rand(110) xor rand(100);
elsif(rand'length = 112) then --112
xor_out := rand(111) xor rand(109) xor rand(68) xor rand(66);
elsif(rand'length = 113) then --113
xor_out := rand(112) xor rand(103);
elsif(rand'length = 114) then --114
xor_out := rand(113) xor rand(112) xor rand(32) xor rand(31);
elsif(rand'length = 115) then --115
xor_out := rand(114) xor rand(113) xor rand(100) xor rand(99);
elsif(rand'length = 116) then --116
xor_out := rand(115) xor rand(114) xor rand(45) xor rand(44);
elsif(rand'length = 117) then --117
xor_out := rand(116) xor rand(114) xor rand(98) xor rand(96);
elsif(rand'length = 118) then --118
xor_out := rand(117) xor rand(84);
elsif(rand'length = 119) then --119
xor_out := rand(118) xor rand(110);
elsif(rand'length = 120) then --120
xor_out := rand(119) xor rand(112) xor rand(8) xor rand(1);
elsif(rand'length = 121) then --121
xor_out := rand(120) xor rand(102);
elsif(rand'length = 122) then --122
xor_out := rand(121) xor rand(120) xor rand(62) xor rand(61);
elsif(rand'length = 123) then --123
xor_out := rand(122) xor rand(120);
elsif(rand'length = 124) then --124
xor_out := rand(123) xor rand(86);
elsif(rand'length = 125) then --125
xor_out := rand(124) xor rand(123) xor rand(17) xor rand(16);
elsif(rand'length = 126) then --126
xor_out := rand(125) xor rand(124) xor rand(89) xor rand(88);
elsif(rand'length = 127) then --127
xor_out := rand(126) xor rand(125);
elsif(rand'length = 128) then --128
xor_out := rand(127) xor rand(125) xor rand(100) xor rand(98);
elsif(rand'length = 129) then --129
xor_out := rand(128) xor rand(123);
elsif(rand'length = 130) then --130
xor_out := rand(129) xor rand(126);
elsif(rand'length = 131) then --131
xor_out := rand(130) xor rand(129) xor rand(83) xor rand(82);
elsif(rand'length = 132) then --132
xor_out := rand(131) xor rand(102);
elsif(rand'length = 133) then --133
xor_out := rand(132) xor rand(131) xor rand(81) xor rand(80);
elsif(rand'length = 134) then --134
xor_out := rand(133) xor rand(76);
elsif(rand'length = 135) then --135
xor_out := rand(134) xor rand(123);
elsif(rand'length = 136) then --136
xor_out := rand(135) xor rand(134) xor rand(10) xor rand(9);
elsif(rand'length = 137) then --137
xor_out := rand(136) xor rand(115);
elsif(rand'length = 138) then --138
xor_out := rand(137) xor rand(136) xor rand(130) xor rand(129);
elsif(rand'length = 139) then --139
xor_out := rand(138) xor rand(135) xor rand(133) xor rand(130);
elsif(rand'length = 140) then --140
xor_out := rand(139) xor rand(110);
elsif(rand'length = 141) then --141
xor_out := rand(140) xor rand(139) xor rand(109) xor rand(108);
elsif(rand'length = 142) then --142
xor_out := rand(141) xor rand(120);
elsif(rand'length = 143) then --143
xor_out := rand(142) xor rand(141) xor rand(122) xor rand(121);
elsif(rand'length = 144) then --144
xor_out := rand(143) xor rand(142) xor rand(74) xor rand(73);
elsif(rand'length = 145) then --145
xor_out := rand(144) xor rand(92);
elsif(rand'length = 146) then --146
xor_out := rand(145) xor rand(144) xor rand(86) xor rand(85);
elsif(rand'length = 147) then --147
xor_out := rand(146) xor rand(145) xor rand(109) xor rand(108);
elsif(rand'length = 148) then --148
xor_out := rand(147) xor rand(120);
elsif(rand'length = 149) then --149
xor_out := rand(148) xor rand(147) xor rand(39) xor rand(38);
elsif(rand'length = 150) then --150
xor_out := rand(149) xor rand(96);
elsif(rand'length = 151) then --151
xor_out := rand(150) xor rand(147);
elsif(rand'length = 152) then --152
xor_out := rand(151) xor rand(150) xor rand(86) xor rand(85);
elsif(rand'length = 153) then --153
xor_out := rand(152) xor rand(151);
elsif(rand'length = 154) then --154
xor_out := rand(153) xor rand(151) xor rand(26) xor rand(24);
elsif(rand'length = 155) then --155
xor_out := rand(154) xor rand(153) xor rand(123) xor rand(122);
elsif(rand'length = 156) then --156
xor_out := rand(155) xor rand(154) xor rand(40) xor rand(39);
elsif(rand'length = 157) then --157
xor_out := rand(156) xor rand(155) xor rand(130) xor rand(129);
elsif(rand'length = 158) then --158
xor_out := rand(157) xor rand(156) xor rand(131) xor rand(130);
elsif(rand'length = 159) then --159
xor_out := rand(158) xor rand(127);
elsif(rand'length = 160) then --160
xor_out := rand(159) xor rand(158) xor rand(141) xor rand(140);
elsif(rand'length = 161) then --161
xor_out := rand(160) xor rand(142);
elsif(rand'length = 162) then --162
xor_out := rand(161) xor rand(160) xor rand(74) xor rand(73);
elsif(rand'length = 163) then --163
xor_out := rand(162) xor rand(161) xor rand(103) xor rand(102);
elsif(rand'length = 164) then --164
xor_out := rand(163) xor rand(162) xor rand(150) xor rand(149);
elsif(rand'length = 165) then --165
xor_out := rand(164) xor rand(163) xor rand(134) xor rand(133);
elsif(rand'length = 166) then --166
xor_out := rand(165) xor rand(164) xor rand(127) xor rand(126);
elsif(rand'length = 167) then --167
xor_out := rand(166) xor rand(160);
elsif(rand'length = 168) then --168
xor_out := rand(167) xor rand(165) xor rand(152) xor rand(150);
end if;
return xor_out;
end xor_gates;
--END function for XORing using tap values.
end lfsr_pkg;
--End of the package.
|
----------------------------------------------------------------------------
---- Create Date: 14:30:08 07/28/2010 ----
---- Design Name: lfsr_pkg ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- This is the package file used in the lfsr_randgen project.The ----
---- package contain the function for XORing bits from various tap ----
---- locations depending on the generic parameter(width of lfsr ) ----
---- ----
----------------------------------------------------------------------------
---- ----
---- This file is a part of the lfsr_randgen project at ----
---- http://www.opencores.org/ ----
---- ----
---- Author(s): ----
---- Vipin Lal, [email protected] ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2010 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lfsr_pkg is
function xor_gates( random : std_logic_vector) return std_logic;
end lfsr_pkg;
--Package body starts from here.
package body lfsr_pkg is
--function for XORing from tap values.
function xor_gates( random : std_logic_vector ) return std_logic is
variable xor_out : std_logic:='0';
variable rand : std_logic_vector(random'length-1 downto 0):=random;
begin
if(rand'length = 3) then --3
xor_out := rand(2) xor rand(1);
elsif(rand'length = 2) then --2
xor_out := rand(1) xor rand(0);
elsif(rand'length = 4) then --4
xor_out := rand(3) xor rand(2);
elsif(rand'length = 5) then --5
xor_out := rand(4) xor rand(2);
elsif(rand'length = 6) then --6
xor_out := rand(5) xor rand(4);
elsif(rand'length = 7) then --7
xor_out := rand(6) xor rand(5);
elsif(rand'length = 8) then --8
xor_out := rand(7) xor rand(5) xor rand(4) xor rand(3);
elsif(rand'length = 9) then --9
xor_out := rand(8) xor rand(4);
elsif(rand'length = 10)then --10
xor_out := rand(9) xor rand(6);
elsif(rand'length =11) then --11
xor_out := rand(10) xor rand(8);
elsif(rand'length = 12) then --12
xor_out := rand(11) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 13) then --13
xor_out := rand(12) xor rand(3) xor rand(2) xor rand(0);
elsif(rand'length = 14) then --14
xor_out := rand(13) xor rand(4) xor rand(2) xor rand(0);
elsif(rand'length = 15) then --15
xor_out := rand(14) xor rand(13);
elsif(rand'length = 16) then --16
xor_out := rand(15) xor rand(14) xor rand(12) xor rand(3);
elsif(rand'length = 17) then --17
xor_out := rand(16) xor rand(13);
elsif(rand'length = 18) then --18
xor_out := rand(17) xor rand(10);
elsif(rand'length = 19) then --19
xor_out := rand(18) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 20) then --20
xor_out := rand(19) xor rand(16);
elsif(rand'length = 21) then --21
xor_out := rand(20) xor rand(18);
elsif(rand'length = 22) then --22
xor_out := rand(21) xor rand(20);
elsif(rand'length = 23) then --23
xor_out := rand(22) xor rand(17);
elsif(rand'length = 24) then --24
xor_out := rand(23) xor rand(22) xor rand(21) xor rand(16);
elsif(rand'length = 25) then --25
xor_out := rand(24) xor rand(21);
elsif(rand'length = 26) then --26
xor_out := rand(25) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 27) then --27
xor_out := rand(26) xor rand(4) xor rand(1) xor rand(0);
elsif(rand'length = 28) then --28
xor_out := rand(27) xor rand(24);
elsif(rand'length = 29) then --29
xor_out := rand(28) xor rand(26);
elsif(rand'length = 30) then --30
xor_out := rand(29) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 31) then --31
xor_out := rand(30) xor rand(27);
elsif(rand'length = 32) then --32
xor_out := rand(31) xor rand(21) xor rand(1) xor rand(0);
elsif(rand'length = 33) then --33
xor_out := rand(32) xor rand(19);
elsif(rand'length = 34) then --34
xor_out := rand(33) xor rand(26) xor rand(1) xor rand(0);
elsif(rand'length = 35) then --35
xor_out := rand(34) xor rand(32);
elsif(rand'length = 36) then --36
xor_out := rand(35) xor rand(24);
elsif(rand'length = 37) then --37
xor_out := rand(36) xor rand(4) xor rand(3) xor rand(2) xor rand(1) xor rand(0);
elsif(rand'length = 38) then --38
xor_out := rand(37) xor rand(5) xor rand(4) xor rand(0);
elsif(rand'length = 39) then --39
xor_out := rand(38) xor rand(34);
elsif(rand'length = 40) then --40
xor_out := rand(39) xor rand(37) xor rand(20) xor rand(18);
elsif(rand'length = 41) then --41
xor_out := rand(40) xor rand(37);
elsif(rand'length = 42) then --42
xor_out := rand(41) xor rand(40) xor rand(19) xor rand(18);
elsif(rand'length = 43) then --43
xor_out := rand(42) xor rand(41) xor rand(37) xor rand(36);
elsif(rand'length = 44) then --44
xor_out := rand(43) xor rand(42) xor rand(17) xor rand(16);
elsif(rand'length = 45) then --45
xor_out := rand(44) xor rand(43) xor rand(41) xor rand(40);
elsif(rand'length = 46) then --46
xor_out := rand(45) xor rand(44) xor rand(25) xor rand(24);
elsif(rand'length = 47) then --47
xor_out := rand(46) xor rand(41);
elsif(rand'length = 48) then --48
xor_out := rand(47) xor rand(46) xor rand(20) xor rand(19);
elsif(rand'length = 49) then --49
xor_out := rand(48) xor rand(39);
elsif(rand'length = 50) then --50
xor_out := rand(49) xor rand(48) xor rand(23) xor rand(22);
elsif(rand'length = 51) then --51
xor_out := rand(50) xor rand(49) xor rand(35) xor rand(34);
elsif(rand'length = 52) then --52
xor_out := rand(51) xor rand(48);
elsif(rand'length = 53) then --53
xor_out := rand(52) xor rand(51) xor rand(37) xor rand(36);
elsif(rand'length = 54) then --54
xor_out := rand(53) xor rand(52) xor rand(17) xor rand(16);
elsif(rand'length = 55) then --55
xor_out := rand(54) xor rand(30);
elsif(rand'length = 56) then --56
xor_out := rand(55) xor rand(54) xor rand(34) xor rand(33);
elsif(rand'length = 57) then --57
xor_out := rand(56) xor rand(49);
elsif(rand'length = 58) then --58
xor_out := rand(57) xor rand(38);
elsif(rand'length = 59) then --59
xor_out := rand(58) xor rand(57) xor rand(37) xor rand(36);
elsif(rand'length = 60) then --60
xor_out := rand(59) xor rand(58);
elsif(rand'length = 61) then --61
xor_out := rand(60) xor rand(59) xor rand(45) xor rand(44);
elsif(rand'length = 62) then --62
xor_out := rand(61) xor rand(60) xor rand(5) xor rand(4);
elsif(rand'length = 63) then --63
xor_out := rand(62) xor rand(61);
elsif(rand'length = 64) then --64
xor_out := rand(63) xor rand(62) xor rand(60) xor rand(59);
elsif(rand'length = 65) then --65
xor_out := rand(64) xor rand(46);
elsif(rand'length = 66) then --66
xor_out := rand(65) xor rand(64) xor rand(56) xor rand(55);
elsif(rand'length = 67) then --67
xor_out := rand(66) xor rand(65) xor rand(57) xor rand(56);
elsif(rand'length = 68) then --68
xor_out := rand(67) xor rand(58);
elsif(rand'length = 69) then --69
xor_out := rand(68) xor rand(66) xor rand(41) xor rand(39);
elsif(rand'length = 70) then --70
xor_out := rand(69) xor rand(68) xor rand(54) xor rand(53);
elsif(rand'length = 71) then --71
xor_out := rand(70) xor rand(64);
elsif(rand'length = 72) then --72
xor_out := rand(71) xor rand(65) xor rand(24) xor rand(18);
elsif(rand'length = 73) then --73
xor_out := rand(72) xor rand(47);
elsif(rand'length = 74) then --74
xor_out := rand(73) xor rand(72) xor rand(58) xor rand(57);
elsif(rand'length = 75) then --75
xor_out := rand(74) xor rand(73) xor rand(64) xor rand(63);
elsif(rand'length = 76) then --76
xor_out := rand(75) xor rand(74) xor rand(40) xor rand(39);
elsif(rand'length = 77) then --77
xor_out := rand(76) xor rand(75) xor rand(46) xor rand(45);
elsif(rand'length = 78) then --78
xor_out := rand(77) xor rand(76) xor rand(58) xor rand(57);
elsif(rand'length = 79) then --79
xor_out := rand(78) xor rand(69);
elsif(rand'length = 80) then --80
xor_out := rand(79) xor rand(78) xor rand(42) xor rand(41);
elsif(rand'length = 81) then --81
xor_out := rand(80) xor rand(76);
elsif(rand'length = 82) then --82
xor_out := rand(81) xor rand(78) xor rand(46) xor rand(43);
elsif(rand'length = 83) then --83
xor_out := rand(82) xor rand(81) xor rand(37) xor rand(36);
elsif(rand'length = 84) then --84
xor_out := rand(83) xor rand(70);
elsif(rand'length = 85) then --85
xor_out := rand(84) xor rand(83) xor rand(57) xor rand(56);
elsif(rand'length = 86) then --86
xor_out := rand(85) xor rand(84) xor rand(73) xor rand(72);
elsif(rand'length = 87) then --87
xor_out := rand(86) xor rand(73);
elsif(rand'length = 88) then --88
xor_out := rand(87) xor rand(86) xor rand(16) xor rand(15);
elsif(rand'length = 89) then --89
xor_out := rand(88) xor rand(50);
elsif(rand'length = 90) then --90
xor_out := rand(89) xor rand(88) xor rand(71) xor rand(70);
elsif(rand'length = 91) then --91
xor_out := rand(90) xor rand(89) xor rand(7) xor rand(6);
elsif(rand'length = 92) then --92
xor_out := rand(91) xor rand(90) xor rand(79) xor rand(78);
elsif(rand'length = 93) then --93
xor_out := rand(92) xor rand(90);
elsif(rand'length = 94) then --94
xor_out := rand(93) xor rand(72);
elsif(rand'length = 95) then --95
xor_out := rand(94) xor rand(83);
elsif(rand'length = 96) then --96
xor_out := rand(95) xor rand(93) xor rand(48) xor rand(46);
elsif(rand'length = 97) then --97
xor_out := rand(96) xor rand(90);
elsif(rand'length = 98) then --98
xor_out := rand(97) xor rand(86);
elsif(rand'length = 99) then --99
xor_out := rand(98) xor rand(96) xor rand(53) xor rand(51);
elsif(rand'length = 100) then --100
xor_out := rand(99) xor rand(62);
elsif(rand'length = 101) then --101
xor_out := rand(100) xor rand(99) xor rand(94) xor rand(93);
elsif(rand'length = 102) then --102
xor_out := rand(101) xor rand(100) xor rand(35) xor rand(34);
elsif(rand'length = 103) then --103
xor_out := rand(102) xor rand(93);
elsif(rand'length = 104) then --104
xor_out := rand(103) xor rand(102) xor rand(93) xor rand(92);
elsif(rand'length = 105) then --105
xor_out := rand(104) xor rand(88);
elsif(rand'length = 106) then --106
xor_out := rand(105) xor rand(90);
elsif(rand'length = 107) then --107
xor_out := rand(106) xor rand(104) xor rand(43) xor rand(41);
elsif(rand'length = 108) then --108
xor_out := rand(107) xor rand(76);
elsif(rand'length = 109) then --109
xor_out := rand(108) xor rand(107) xor rand(102) xor rand(101);
elsif(rand'length = 110)then --110
xor_out := rand(109) xor rand(108) xor rand(97) xor rand(96);
elsif(rand'length = 111) then --111
xor_out := rand(110) xor rand(100);
elsif(rand'length = 112) then --112
xor_out := rand(111) xor rand(109) xor rand(68) xor rand(66);
elsif(rand'length = 113) then --113
xor_out := rand(112) xor rand(103);
elsif(rand'length = 114) then --114
xor_out := rand(113) xor rand(112) xor rand(32) xor rand(31);
elsif(rand'length = 115) then --115
xor_out := rand(114) xor rand(113) xor rand(100) xor rand(99);
elsif(rand'length = 116) then --116
xor_out := rand(115) xor rand(114) xor rand(45) xor rand(44);
elsif(rand'length = 117) then --117
xor_out := rand(116) xor rand(114) xor rand(98) xor rand(96);
elsif(rand'length = 118) then --118
xor_out := rand(117) xor rand(84);
elsif(rand'length = 119) then --119
xor_out := rand(118) xor rand(110);
elsif(rand'length = 120) then --120
xor_out := rand(119) xor rand(112) xor rand(8) xor rand(1);
elsif(rand'length = 121) then --121
xor_out := rand(120) xor rand(102);
elsif(rand'length = 122) then --122
xor_out := rand(121) xor rand(120) xor rand(62) xor rand(61);
elsif(rand'length = 123) then --123
xor_out := rand(122) xor rand(120);
elsif(rand'length = 124) then --124
xor_out := rand(123) xor rand(86);
elsif(rand'length = 125) then --125
xor_out := rand(124) xor rand(123) xor rand(17) xor rand(16);
elsif(rand'length = 126) then --126
xor_out := rand(125) xor rand(124) xor rand(89) xor rand(88);
elsif(rand'length = 127) then --127
xor_out := rand(126) xor rand(125);
elsif(rand'length = 128) then --128
xor_out := rand(127) xor rand(125) xor rand(100) xor rand(98);
elsif(rand'length = 129) then --129
xor_out := rand(128) xor rand(123);
elsif(rand'length = 130) then --130
xor_out := rand(129) xor rand(126);
elsif(rand'length = 131) then --131
xor_out := rand(130) xor rand(129) xor rand(83) xor rand(82);
elsif(rand'length = 132) then --132
xor_out := rand(131) xor rand(102);
elsif(rand'length = 133) then --133
xor_out := rand(132) xor rand(131) xor rand(81) xor rand(80);
elsif(rand'length = 134) then --134
xor_out := rand(133) xor rand(76);
elsif(rand'length = 135) then --135
xor_out := rand(134) xor rand(123);
elsif(rand'length = 136) then --136
xor_out := rand(135) xor rand(134) xor rand(10) xor rand(9);
elsif(rand'length = 137) then --137
xor_out := rand(136) xor rand(115);
elsif(rand'length = 138) then --138
xor_out := rand(137) xor rand(136) xor rand(130) xor rand(129);
elsif(rand'length = 139) then --139
xor_out := rand(138) xor rand(135) xor rand(133) xor rand(130);
elsif(rand'length = 140) then --140
xor_out := rand(139) xor rand(110);
elsif(rand'length = 141) then --141
xor_out := rand(140) xor rand(139) xor rand(109) xor rand(108);
elsif(rand'length = 142) then --142
xor_out := rand(141) xor rand(120);
elsif(rand'length = 143) then --143
xor_out := rand(142) xor rand(141) xor rand(122) xor rand(121);
elsif(rand'length = 144) then --144
xor_out := rand(143) xor rand(142) xor rand(74) xor rand(73);
elsif(rand'length = 145) then --145
xor_out := rand(144) xor rand(92);
elsif(rand'length = 146) then --146
xor_out := rand(145) xor rand(144) xor rand(86) xor rand(85);
elsif(rand'length = 147) then --147
xor_out := rand(146) xor rand(145) xor rand(109) xor rand(108);
elsif(rand'length = 148) then --148
xor_out := rand(147) xor rand(120);
elsif(rand'length = 149) then --149
xor_out := rand(148) xor rand(147) xor rand(39) xor rand(38);
elsif(rand'length = 150) then --150
xor_out := rand(149) xor rand(96);
elsif(rand'length = 151) then --151
xor_out := rand(150) xor rand(147);
elsif(rand'length = 152) then --152
xor_out := rand(151) xor rand(150) xor rand(86) xor rand(85);
elsif(rand'length = 153) then --153
xor_out := rand(152) xor rand(151);
elsif(rand'length = 154) then --154
xor_out := rand(153) xor rand(151) xor rand(26) xor rand(24);
elsif(rand'length = 155) then --155
xor_out := rand(154) xor rand(153) xor rand(123) xor rand(122);
elsif(rand'length = 156) then --156
xor_out := rand(155) xor rand(154) xor rand(40) xor rand(39);
elsif(rand'length = 157) then --157
xor_out := rand(156) xor rand(155) xor rand(130) xor rand(129);
elsif(rand'length = 158) then --158
xor_out := rand(157) xor rand(156) xor rand(131) xor rand(130);
elsif(rand'length = 159) then --159
xor_out := rand(158) xor rand(127);
elsif(rand'length = 160) then --160
xor_out := rand(159) xor rand(158) xor rand(141) xor rand(140);
elsif(rand'length = 161) then --161
xor_out := rand(160) xor rand(142);
elsif(rand'length = 162) then --162
xor_out := rand(161) xor rand(160) xor rand(74) xor rand(73);
elsif(rand'length = 163) then --163
xor_out := rand(162) xor rand(161) xor rand(103) xor rand(102);
elsif(rand'length = 164) then --164
xor_out := rand(163) xor rand(162) xor rand(150) xor rand(149);
elsif(rand'length = 165) then --165
xor_out := rand(164) xor rand(163) xor rand(134) xor rand(133);
elsif(rand'length = 166) then --166
xor_out := rand(165) xor rand(164) xor rand(127) xor rand(126);
elsif(rand'length = 167) then --167
xor_out := rand(166) xor rand(160);
elsif(rand'length = 168) then --168
xor_out := rand(167) xor rand(165) xor rand(152) xor rand(150);
end if;
return xor_out;
end xor_gates;
--END function for XORing using tap values.
end lfsr_pkg;
--End of the package.
|
----------------------------------------------------------------------------
---- Create Date: 14:30:08 07/28/2010 ----
---- Design Name: lfsr_pkg ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- This is the package file used in the lfsr_randgen project.The ----
---- package contain the function for XORing bits from various tap ----
---- locations depending on the generic parameter(width of lfsr ) ----
---- ----
----------------------------------------------------------------------------
---- ----
---- This file is a part of the lfsr_randgen project at ----
---- http://www.opencores.org/ ----
---- ----
---- Author(s): ----
---- Vipin Lal, [email protected] ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2010 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lfsr_pkg is
function xor_gates( random : std_logic_vector) return std_logic;
end lfsr_pkg;
--Package body starts from here.
package body lfsr_pkg is
--function for XORing from tap values.
function xor_gates( random : std_logic_vector ) return std_logic is
variable xor_out : std_logic:='0';
variable rand : std_logic_vector(random'length-1 downto 0):=random;
begin
if(rand'length = 3) then --3
xor_out := rand(2) xor rand(1);
elsif(rand'length = 2) then --2
xor_out := rand(1) xor rand(0);
elsif(rand'length = 4) then --4
xor_out := rand(3) xor rand(2);
elsif(rand'length = 5) then --5
xor_out := rand(4) xor rand(2);
elsif(rand'length = 6) then --6
xor_out := rand(5) xor rand(4);
elsif(rand'length = 7) then --7
xor_out := rand(6) xor rand(5);
elsif(rand'length = 8) then --8
xor_out := rand(7) xor rand(5) xor rand(4) xor rand(3);
elsif(rand'length = 9) then --9
xor_out := rand(8) xor rand(4);
elsif(rand'length = 10)then --10
xor_out := rand(9) xor rand(6);
elsif(rand'length =11) then --11
xor_out := rand(10) xor rand(8);
elsif(rand'length = 12) then --12
xor_out := rand(11) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 13) then --13
xor_out := rand(12) xor rand(3) xor rand(2) xor rand(0);
elsif(rand'length = 14) then --14
xor_out := rand(13) xor rand(4) xor rand(2) xor rand(0);
elsif(rand'length = 15) then --15
xor_out := rand(14) xor rand(13);
elsif(rand'length = 16) then --16
xor_out := rand(15) xor rand(14) xor rand(12) xor rand(3);
elsif(rand'length = 17) then --17
xor_out := rand(16) xor rand(13);
elsif(rand'length = 18) then --18
xor_out := rand(17) xor rand(10);
elsif(rand'length = 19) then --19
xor_out := rand(18) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 20) then --20
xor_out := rand(19) xor rand(16);
elsif(rand'length = 21) then --21
xor_out := rand(20) xor rand(18);
elsif(rand'length = 22) then --22
xor_out := rand(21) xor rand(20);
elsif(rand'length = 23) then --23
xor_out := rand(22) xor rand(17);
elsif(rand'length = 24) then --24
xor_out := rand(23) xor rand(22) xor rand(21) xor rand(16);
elsif(rand'length = 25) then --25
xor_out := rand(24) xor rand(21);
elsif(rand'length = 26) then --26
xor_out := rand(25) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 27) then --27
xor_out := rand(26) xor rand(4) xor rand(1) xor rand(0);
elsif(rand'length = 28) then --28
xor_out := rand(27) xor rand(24);
elsif(rand'length = 29) then --29
xor_out := rand(28) xor rand(26);
elsif(rand'length = 30) then --30
xor_out := rand(29) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 31) then --31
xor_out := rand(30) xor rand(27);
elsif(rand'length = 32) then --32
xor_out := rand(31) xor rand(21) xor rand(1) xor rand(0);
elsif(rand'length = 33) then --33
xor_out := rand(32) xor rand(19);
elsif(rand'length = 34) then --34
xor_out := rand(33) xor rand(26) xor rand(1) xor rand(0);
elsif(rand'length = 35) then --35
xor_out := rand(34) xor rand(32);
elsif(rand'length = 36) then --36
xor_out := rand(35) xor rand(24);
elsif(rand'length = 37) then --37
xor_out := rand(36) xor rand(4) xor rand(3) xor rand(2) xor rand(1) xor rand(0);
elsif(rand'length = 38) then --38
xor_out := rand(37) xor rand(5) xor rand(4) xor rand(0);
elsif(rand'length = 39) then --39
xor_out := rand(38) xor rand(34);
elsif(rand'length = 40) then --40
xor_out := rand(39) xor rand(37) xor rand(20) xor rand(18);
elsif(rand'length = 41) then --41
xor_out := rand(40) xor rand(37);
elsif(rand'length = 42) then --42
xor_out := rand(41) xor rand(40) xor rand(19) xor rand(18);
elsif(rand'length = 43) then --43
xor_out := rand(42) xor rand(41) xor rand(37) xor rand(36);
elsif(rand'length = 44) then --44
xor_out := rand(43) xor rand(42) xor rand(17) xor rand(16);
elsif(rand'length = 45) then --45
xor_out := rand(44) xor rand(43) xor rand(41) xor rand(40);
elsif(rand'length = 46) then --46
xor_out := rand(45) xor rand(44) xor rand(25) xor rand(24);
elsif(rand'length = 47) then --47
xor_out := rand(46) xor rand(41);
elsif(rand'length = 48) then --48
xor_out := rand(47) xor rand(46) xor rand(20) xor rand(19);
elsif(rand'length = 49) then --49
xor_out := rand(48) xor rand(39);
elsif(rand'length = 50) then --50
xor_out := rand(49) xor rand(48) xor rand(23) xor rand(22);
elsif(rand'length = 51) then --51
xor_out := rand(50) xor rand(49) xor rand(35) xor rand(34);
elsif(rand'length = 52) then --52
xor_out := rand(51) xor rand(48);
elsif(rand'length = 53) then --53
xor_out := rand(52) xor rand(51) xor rand(37) xor rand(36);
elsif(rand'length = 54) then --54
xor_out := rand(53) xor rand(52) xor rand(17) xor rand(16);
elsif(rand'length = 55) then --55
xor_out := rand(54) xor rand(30);
elsif(rand'length = 56) then --56
xor_out := rand(55) xor rand(54) xor rand(34) xor rand(33);
elsif(rand'length = 57) then --57
xor_out := rand(56) xor rand(49);
elsif(rand'length = 58) then --58
xor_out := rand(57) xor rand(38);
elsif(rand'length = 59) then --59
xor_out := rand(58) xor rand(57) xor rand(37) xor rand(36);
elsif(rand'length = 60) then --60
xor_out := rand(59) xor rand(58);
elsif(rand'length = 61) then --61
xor_out := rand(60) xor rand(59) xor rand(45) xor rand(44);
elsif(rand'length = 62) then --62
xor_out := rand(61) xor rand(60) xor rand(5) xor rand(4);
elsif(rand'length = 63) then --63
xor_out := rand(62) xor rand(61);
elsif(rand'length = 64) then --64
xor_out := rand(63) xor rand(62) xor rand(60) xor rand(59);
elsif(rand'length = 65) then --65
xor_out := rand(64) xor rand(46);
elsif(rand'length = 66) then --66
xor_out := rand(65) xor rand(64) xor rand(56) xor rand(55);
elsif(rand'length = 67) then --67
xor_out := rand(66) xor rand(65) xor rand(57) xor rand(56);
elsif(rand'length = 68) then --68
xor_out := rand(67) xor rand(58);
elsif(rand'length = 69) then --69
xor_out := rand(68) xor rand(66) xor rand(41) xor rand(39);
elsif(rand'length = 70) then --70
xor_out := rand(69) xor rand(68) xor rand(54) xor rand(53);
elsif(rand'length = 71) then --71
xor_out := rand(70) xor rand(64);
elsif(rand'length = 72) then --72
xor_out := rand(71) xor rand(65) xor rand(24) xor rand(18);
elsif(rand'length = 73) then --73
xor_out := rand(72) xor rand(47);
elsif(rand'length = 74) then --74
xor_out := rand(73) xor rand(72) xor rand(58) xor rand(57);
elsif(rand'length = 75) then --75
xor_out := rand(74) xor rand(73) xor rand(64) xor rand(63);
elsif(rand'length = 76) then --76
xor_out := rand(75) xor rand(74) xor rand(40) xor rand(39);
elsif(rand'length = 77) then --77
xor_out := rand(76) xor rand(75) xor rand(46) xor rand(45);
elsif(rand'length = 78) then --78
xor_out := rand(77) xor rand(76) xor rand(58) xor rand(57);
elsif(rand'length = 79) then --79
xor_out := rand(78) xor rand(69);
elsif(rand'length = 80) then --80
xor_out := rand(79) xor rand(78) xor rand(42) xor rand(41);
elsif(rand'length = 81) then --81
xor_out := rand(80) xor rand(76);
elsif(rand'length = 82) then --82
xor_out := rand(81) xor rand(78) xor rand(46) xor rand(43);
elsif(rand'length = 83) then --83
xor_out := rand(82) xor rand(81) xor rand(37) xor rand(36);
elsif(rand'length = 84) then --84
xor_out := rand(83) xor rand(70);
elsif(rand'length = 85) then --85
xor_out := rand(84) xor rand(83) xor rand(57) xor rand(56);
elsif(rand'length = 86) then --86
xor_out := rand(85) xor rand(84) xor rand(73) xor rand(72);
elsif(rand'length = 87) then --87
xor_out := rand(86) xor rand(73);
elsif(rand'length = 88) then --88
xor_out := rand(87) xor rand(86) xor rand(16) xor rand(15);
elsif(rand'length = 89) then --89
xor_out := rand(88) xor rand(50);
elsif(rand'length = 90) then --90
xor_out := rand(89) xor rand(88) xor rand(71) xor rand(70);
elsif(rand'length = 91) then --91
xor_out := rand(90) xor rand(89) xor rand(7) xor rand(6);
elsif(rand'length = 92) then --92
xor_out := rand(91) xor rand(90) xor rand(79) xor rand(78);
elsif(rand'length = 93) then --93
xor_out := rand(92) xor rand(90);
elsif(rand'length = 94) then --94
xor_out := rand(93) xor rand(72);
elsif(rand'length = 95) then --95
xor_out := rand(94) xor rand(83);
elsif(rand'length = 96) then --96
xor_out := rand(95) xor rand(93) xor rand(48) xor rand(46);
elsif(rand'length = 97) then --97
xor_out := rand(96) xor rand(90);
elsif(rand'length = 98) then --98
xor_out := rand(97) xor rand(86);
elsif(rand'length = 99) then --99
xor_out := rand(98) xor rand(96) xor rand(53) xor rand(51);
elsif(rand'length = 100) then --100
xor_out := rand(99) xor rand(62);
elsif(rand'length = 101) then --101
xor_out := rand(100) xor rand(99) xor rand(94) xor rand(93);
elsif(rand'length = 102) then --102
xor_out := rand(101) xor rand(100) xor rand(35) xor rand(34);
elsif(rand'length = 103) then --103
xor_out := rand(102) xor rand(93);
elsif(rand'length = 104) then --104
xor_out := rand(103) xor rand(102) xor rand(93) xor rand(92);
elsif(rand'length = 105) then --105
xor_out := rand(104) xor rand(88);
elsif(rand'length = 106) then --106
xor_out := rand(105) xor rand(90);
elsif(rand'length = 107) then --107
xor_out := rand(106) xor rand(104) xor rand(43) xor rand(41);
elsif(rand'length = 108) then --108
xor_out := rand(107) xor rand(76);
elsif(rand'length = 109) then --109
xor_out := rand(108) xor rand(107) xor rand(102) xor rand(101);
elsif(rand'length = 110)then --110
xor_out := rand(109) xor rand(108) xor rand(97) xor rand(96);
elsif(rand'length = 111) then --111
xor_out := rand(110) xor rand(100);
elsif(rand'length = 112) then --112
xor_out := rand(111) xor rand(109) xor rand(68) xor rand(66);
elsif(rand'length = 113) then --113
xor_out := rand(112) xor rand(103);
elsif(rand'length = 114) then --114
xor_out := rand(113) xor rand(112) xor rand(32) xor rand(31);
elsif(rand'length = 115) then --115
xor_out := rand(114) xor rand(113) xor rand(100) xor rand(99);
elsif(rand'length = 116) then --116
xor_out := rand(115) xor rand(114) xor rand(45) xor rand(44);
elsif(rand'length = 117) then --117
xor_out := rand(116) xor rand(114) xor rand(98) xor rand(96);
elsif(rand'length = 118) then --118
xor_out := rand(117) xor rand(84);
elsif(rand'length = 119) then --119
xor_out := rand(118) xor rand(110);
elsif(rand'length = 120) then --120
xor_out := rand(119) xor rand(112) xor rand(8) xor rand(1);
elsif(rand'length = 121) then --121
xor_out := rand(120) xor rand(102);
elsif(rand'length = 122) then --122
xor_out := rand(121) xor rand(120) xor rand(62) xor rand(61);
elsif(rand'length = 123) then --123
xor_out := rand(122) xor rand(120);
elsif(rand'length = 124) then --124
xor_out := rand(123) xor rand(86);
elsif(rand'length = 125) then --125
xor_out := rand(124) xor rand(123) xor rand(17) xor rand(16);
elsif(rand'length = 126) then --126
xor_out := rand(125) xor rand(124) xor rand(89) xor rand(88);
elsif(rand'length = 127) then --127
xor_out := rand(126) xor rand(125);
elsif(rand'length = 128) then --128
xor_out := rand(127) xor rand(125) xor rand(100) xor rand(98);
elsif(rand'length = 129) then --129
xor_out := rand(128) xor rand(123);
elsif(rand'length = 130) then --130
xor_out := rand(129) xor rand(126);
elsif(rand'length = 131) then --131
xor_out := rand(130) xor rand(129) xor rand(83) xor rand(82);
elsif(rand'length = 132) then --132
xor_out := rand(131) xor rand(102);
elsif(rand'length = 133) then --133
xor_out := rand(132) xor rand(131) xor rand(81) xor rand(80);
elsif(rand'length = 134) then --134
xor_out := rand(133) xor rand(76);
elsif(rand'length = 135) then --135
xor_out := rand(134) xor rand(123);
elsif(rand'length = 136) then --136
xor_out := rand(135) xor rand(134) xor rand(10) xor rand(9);
elsif(rand'length = 137) then --137
xor_out := rand(136) xor rand(115);
elsif(rand'length = 138) then --138
xor_out := rand(137) xor rand(136) xor rand(130) xor rand(129);
elsif(rand'length = 139) then --139
xor_out := rand(138) xor rand(135) xor rand(133) xor rand(130);
elsif(rand'length = 140) then --140
xor_out := rand(139) xor rand(110);
elsif(rand'length = 141) then --141
xor_out := rand(140) xor rand(139) xor rand(109) xor rand(108);
elsif(rand'length = 142) then --142
xor_out := rand(141) xor rand(120);
elsif(rand'length = 143) then --143
xor_out := rand(142) xor rand(141) xor rand(122) xor rand(121);
elsif(rand'length = 144) then --144
xor_out := rand(143) xor rand(142) xor rand(74) xor rand(73);
elsif(rand'length = 145) then --145
xor_out := rand(144) xor rand(92);
elsif(rand'length = 146) then --146
xor_out := rand(145) xor rand(144) xor rand(86) xor rand(85);
elsif(rand'length = 147) then --147
xor_out := rand(146) xor rand(145) xor rand(109) xor rand(108);
elsif(rand'length = 148) then --148
xor_out := rand(147) xor rand(120);
elsif(rand'length = 149) then --149
xor_out := rand(148) xor rand(147) xor rand(39) xor rand(38);
elsif(rand'length = 150) then --150
xor_out := rand(149) xor rand(96);
elsif(rand'length = 151) then --151
xor_out := rand(150) xor rand(147);
elsif(rand'length = 152) then --152
xor_out := rand(151) xor rand(150) xor rand(86) xor rand(85);
elsif(rand'length = 153) then --153
xor_out := rand(152) xor rand(151);
elsif(rand'length = 154) then --154
xor_out := rand(153) xor rand(151) xor rand(26) xor rand(24);
elsif(rand'length = 155) then --155
xor_out := rand(154) xor rand(153) xor rand(123) xor rand(122);
elsif(rand'length = 156) then --156
xor_out := rand(155) xor rand(154) xor rand(40) xor rand(39);
elsif(rand'length = 157) then --157
xor_out := rand(156) xor rand(155) xor rand(130) xor rand(129);
elsif(rand'length = 158) then --158
xor_out := rand(157) xor rand(156) xor rand(131) xor rand(130);
elsif(rand'length = 159) then --159
xor_out := rand(158) xor rand(127);
elsif(rand'length = 160) then --160
xor_out := rand(159) xor rand(158) xor rand(141) xor rand(140);
elsif(rand'length = 161) then --161
xor_out := rand(160) xor rand(142);
elsif(rand'length = 162) then --162
xor_out := rand(161) xor rand(160) xor rand(74) xor rand(73);
elsif(rand'length = 163) then --163
xor_out := rand(162) xor rand(161) xor rand(103) xor rand(102);
elsif(rand'length = 164) then --164
xor_out := rand(163) xor rand(162) xor rand(150) xor rand(149);
elsif(rand'length = 165) then --165
xor_out := rand(164) xor rand(163) xor rand(134) xor rand(133);
elsif(rand'length = 166) then --166
xor_out := rand(165) xor rand(164) xor rand(127) xor rand(126);
elsif(rand'length = 167) then --167
xor_out := rand(166) xor rand(160);
elsif(rand'length = 168) then --168
xor_out := rand(167) xor rand(165) xor rand(152) xor rand(150);
end if;
return xor_out;
end xor_gates;
--END function for XORing using tap values.
end lfsr_pkg;
--End of the package.
|
----------------------------------------------------------------------------
---- Create Date: 14:30:08 07/28/2010 ----
---- Design Name: lfsr_pkg ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- This is the package file used in the lfsr_randgen project.The ----
---- package contain the function for XORing bits from various tap ----
---- locations depending on the generic parameter(width of lfsr ) ----
---- ----
----------------------------------------------------------------------------
---- ----
---- This file is a part of the lfsr_randgen project at ----
---- http://www.opencores.org/ ----
---- ----
---- Author(s): ----
---- Vipin Lal, [email protected] ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2010 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lfsr_pkg is
function xor_gates( random : std_logic_vector) return std_logic;
end lfsr_pkg;
--Package body starts from here.
package body lfsr_pkg is
--function for XORing from tap values.
function xor_gates( random : std_logic_vector ) return std_logic is
variable xor_out : std_logic:='0';
variable rand : std_logic_vector(random'length-1 downto 0):=random;
begin
if(rand'length = 3) then --3
xor_out := rand(2) xor rand(1);
elsif(rand'length = 2) then --2
xor_out := rand(1) xor rand(0);
elsif(rand'length = 4) then --4
xor_out := rand(3) xor rand(2);
elsif(rand'length = 5) then --5
xor_out := rand(4) xor rand(2);
elsif(rand'length = 6) then --6
xor_out := rand(5) xor rand(4);
elsif(rand'length = 7) then --7
xor_out := rand(6) xor rand(5);
elsif(rand'length = 8) then --8
xor_out := rand(7) xor rand(5) xor rand(4) xor rand(3);
elsif(rand'length = 9) then --9
xor_out := rand(8) xor rand(4);
elsif(rand'length = 10)then --10
xor_out := rand(9) xor rand(6);
elsif(rand'length =11) then --11
xor_out := rand(10) xor rand(8);
elsif(rand'length = 12) then --12
xor_out := rand(11) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 13) then --13
xor_out := rand(12) xor rand(3) xor rand(2) xor rand(0);
elsif(rand'length = 14) then --14
xor_out := rand(13) xor rand(4) xor rand(2) xor rand(0);
elsif(rand'length = 15) then --15
xor_out := rand(14) xor rand(13);
elsif(rand'length = 16) then --16
xor_out := rand(15) xor rand(14) xor rand(12) xor rand(3);
elsif(rand'length = 17) then --17
xor_out := rand(16) xor rand(13);
elsif(rand'length = 18) then --18
xor_out := rand(17) xor rand(10);
elsif(rand'length = 19) then --19
xor_out := rand(18) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 20) then --20
xor_out := rand(19) xor rand(16);
elsif(rand'length = 21) then --21
xor_out := rand(20) xor rand(18);
elsif(rand'length = 22) then --22
xor_out := rand(21) xor rand(20);
elsif(rand'length = 23) then --23
xor_out := rand(22) xor rand(17);
elsif(rand'length = 24) then --24
xor_out := rand(23) xor rand(22) xor rand(21) xor rand(16);
elsif(rand'length = 25) then --25
xor_out := rand(24) xor rand(21);
elsif(rand'length = 26) then --26
xor_out := rand(25) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 27) then --27
xor_out := rand(26) xor rand(4) xor rand(1) xor rand(0);
elsif(rand'length = 28) then --28
xor_out := rand(27) xor rand(24);
elsif(rand'length = 29) then --29
xor_out := rand(28) xor rand(26);
elsif(rand'length = 30) then --30
xor_out := rand(29) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 31) then --31
xor_out := rand(30) xor rand(27);
elsif(rand'length = 32) then --32
xor_out := rand(31) xor rand(21) xor rand(1) xor rand(0);
elsif(rand'length = 33) then --33
xor_out := rand(32) xor rand(19);
elsif(rand'length = 34) then --34
xor_out := rand(33) xor rand(26) xor rand(1) xor rand(0);
elsif(rand'length = 35) then --35
xor_out := rand(34) xor rand(32);
elsif(rand'length = 36) then --36
xor_out := rand(35) xor rand(24);
elsif(rand'length = 37) then --37
xor_out := rand(36) xor rand(4) xor rand(3) xor rand(2) xor rand(1) xor rand(0);
elsif(rand'length = 38) then --38
xor_out := rand(37) xor rand(5) xor rand(4) xor rand(0);
elsif(rand'length = 39) then --39
xor_out := rand(38) xor rand(34);
elsif(rand'length = 40) then --40
xor_out := rand(39) xor rand(37) xor rand(20) xor rand(18);
elsif(rand'length = 41) then --41
xor_out := rand(40) xor rand(37);
elsif(rand'length = 42) then --42
xor_out := rand(41) xor rand(40) xor rand(19) xor rand(18);
elsif(rand'length = 43) then --43
xor_out := rand(42) xor rand(41) xor rand(37) xor rand(36);
elsif(rand'length = 44) then --44
xor_out := rand(43) xor rand(42) xor rand(17) xor rand(16);
elsif(rand'length = 45) then --45
xor_out := rand(44) xor rand(43) xor rand(41) xor rand(40);
elsif(rand'length = 46) then --46
xor_out := rand(45) xor rand(44) xor rand(25) xor rand(24);
elsif(rand'length = 47) then --47
xor_out := rand(46) xor rand(41);
elsif(rand'length = 48) then --48
xor_out := rand(47) xor rand(46) xor rand(20) xor rand(19);
elsif(rand'length = 49) then --49
xor_out := rand(48) xor rand(39);
elsif(rand'length = 50) then --50
xor_out := rand(49) xor rand(48) xor rand(23) xor rand(22);
elsif(rand'length = 51) then --51
xor_out := rand(50) xor rand(49) xor rand(35) xor rand(34);
elsif(rand'length = 52) then --52
xor_out := rand(51) xor rand(48);
elsif(rand'length = 53) then --53
xor_out := rand(52) xor rand(51) xor rand(37) xor rand(36);
elsif(rand'length = 54) then --54
xor_out := rand(53) xor rand(52) xor rand(17) xor rand(16);
elsif(rand'length = 55) then --55
xor_out := rand(54) xor rand(30);
elsif(rand'length = 56) then --56
xor_out := rand(55) xor rand(54) xor rand(34) xor rand(33);
elsif(rand'length = 57) then --57
xor_out := rand(56) xor rand(49);
elsif(rand'length = 58) then --58
xor_out := rand(57) xor rand(38);
elsif(rand'length = 59) then --59
xor_out := rand(58) xor rand(57) xor rand(37) xor rand(36);
elsif(rand'length = 60) then --60
xor_out := rand(59) xor rand(58);
elsif(rand'length = 61) then --61
xor_out := rand(60) xor rand(59) xor rand(45) xor rand(44);
elsif(rand'length = 62) then --62
xor_out := rand(61) xor rand(60) xor rand(5) xor rand(4);
elsif(rand'length = 63) then --63
xor_out := rand(62) xor rand(61);
elsif(rand'length = 64) then --64
xor_out := rand(63) xor rand(62) xor rand(60) xor rand(59);
elsif(rand'length = 65) then --65
xor_out := rand(64) xor rand(46);
elsif(rand'length = 66) then --66
xor_out := rand(65) xor rand(64) xor rand(56) xor rand(55);
elsif(rand'length = 67) then --67
xor_out := rand(66) xor rand(65) xor rand(57) xor rand(56);
elsif(rand'length = 68) then --68
xor_out := rand(67) xor rand(58);
elsif(rand'length = 69) then --69
xor_out := rand(68) xor rand(66) xor rand(41) xor rand(39);
elsif(rand'length = 70) then --70
xor_out := rand(69) xor rand(68) xor rand(54) xor rand(53);
elsif(rand'length = 71) then --71
xor_out := rand(70) xor rand(64);
elsif(rand'length = 72) then --72
xor_out := rand(71) xor rand(65) xor rand(24) xor rand(18);
elsif(rand'length = 73) then --73
xor_out := rand(72) xor rand(47);
elsif(rand'length = 74) then --74
xor_out := rand(73) xor rand(72) xor rand(58) xor rand(57);
elsif(rand'length = 75) then --75
xor_out := rand(74) xor rand(73) xor rand(64) xor rand(63);
elsif(rand'length = 76) then --76
xor_out := rand(75) xor rand(74) xor rand(40) xor rand(39);
elsif(rand'length = 77) then --77
xor_out := rand(76) xor rand(75) xor rand(46) xor rand(45);
elsif(rand'length = 78) then --78
xor_out := rand(77) xor rand(76) xor rand(58) xor rand(57);
elsif(rand'length = 79) then --79
xor_out := rand(78) xor rand(69);
elsif(rand'length = 80) then --80
xor_out := rand(79) xor rand(78) xor rand(42) xor rand(41);
elsif(rand'length = 81) then --81
xor_out := rand(80) xor rand(76);
elsif(rand'length = 82) then --82
xor_out := rand(81) xor rand(78) xor rand(46) xor rand(43);
elsif(rand'length = 83) then --83
xor_out := rand(82) xor rand(81) xor rand(37) xor rand(36);
elsif(rand'length = 84) then --84
xor_out := rand(83) xor rand(70);
elsif(rand'length = 85) then --85
xor_out := rand(84) xor rand(83) xor rand(57) xor rand(56);
elsif(rand'length = 86) then --86
xor_out := rand(85) xor rand(84) xor rand(73) xor rand(72);
elsif(rand'length = 87) then --87
xor_out := rand(86) xor rand(73);
elsif(rand'length = 88) then --88
xor_out := rand(87) xor rand(86) xor rand(16) xor rand(15);
elsif(rand'length = 89) then --89
xor_out := rand(88) xor rand(50);
elsif(rand'length = 90) then --90
xor_out := rand(89) xor rand(88) xor rand(71) xor rand(70);
elsif(rand'length = 91) then --91
xor_out := rand(90) xor rand(89) xor rand(7) xor rand(6);
elsif(rand'length = 92) then --92
xor_out := rand(91) xor rand(90) xor rand(79) xor rand(78);
elsif(rand'length = 93) then --93
xor_out := rand(92) xor rand(90);
elsif(rand'length = 94) then --94
xor_out := rand(93) xor rand(72);
elsif(rand'length = 95) then --95
xor_out := rand(94) xor rand(83);
elsif(rand'length = 96) then --96
xor_out := rand(95) xor rand(93) xor rand(48) xor rand(46);
elsif(rand'length = 97) then --97
xor_out := rand(96) xor rand(90);
elsif(rand'length = 98) then --98
xor_out := rand(97) xor rand(86);
elsif(rand'length = 99) then --99
xor_out := rand(98) xor rand(96) xor rand(53) xor rand(51);
elsif(rand'length = 100) then --100
xor_out := rand(99) xor rand(62);
elsif(rand'length = 101) then --101
xor_out := rand(100) xor rand(99) xor rand(94) xor rand(93);
elsif(rand'length = 102) then --102
xor_out := rand(101) xor rand(100) xor rand(35) xor rand(34);
elsif(rand'length = 103) then --103
xor_out := rand(102) xor rand(93);
elsif(rand'length = 104) then --104
xor_out := rand(103) xor rand(102) xor rand(93) xor rand(92);
elsif(rand'length = 105) then --105
xor_out := rand(104) xor rand(88);
elsif(rand'length = 106) then --106
xor_out := rand(105) xor rand(90);
elsif(rand'length = 107) then --107
xor_out := rand(106) xor rand(104) xor rand(43) xor rand(41);
elsif(rand'length = 108) then --108
xor_out := rand(107) xor rand(76);
elsif(rand'length = 109) then --109
xor_out := rand(108) xor rand(107) xor rand(102) xor rand(101);
elsif(rand'length = 110)then --110
xor_out := rand(109) xor rand(108) xor rand(97) xor rand(96);
elsif(rand'length = 111) then --111
xor_out := rand(110) xor rand(100);
elsif(rand'length = 112) then --112
xor_out := rand(111) xor rand(109) xor rand(68) xor rand(66);
elsif(rand'length = 113) then --113
xor_out := rand(112) xor rand(103);
elsif(rand'length = 114) then --114
xor_out := rand(113) xor rand(112) xor rand(32) xor rand(31);
elsif(rand'length = 115) then --115
xor_out := rand(114) xor rand(113) xor rand(100) xor rand(99);
elsif(rand'length = 116) then --116
xor_out := rand(115) xor rand(114) xor rand(45) xor rand(44);
elsif(rand'length = 117) then --117
xor_out := rand(116) xor rand(114) xor rand(98) xor rand(96);
elsif(rand'length = 118) then --118
xor_out := rand(117) xor rand(84);
elsif(rand'length = 119) then --119
xor_out := rand(118) xor rand(110);
elsif(rand'length = 120) then --120
xor_out := rand(119) xor rand(112) xor rand(8) xor rand(1);
elsif(rand'length = 121) then --121
xor_out := rand(120) xor rand(102);
elsif(rand'length = 122) then --122
xor_out := rand(121) xor rand(120) xor rand(62) xor rand(61);
elsif(rand'length = 123) then --123
xor_out := rand(122) xor rand(120);
elsif(rand'length = 124) then --124
xor_out := rand(123) xor rand(86);
elsif(rand'length = 125) then --125
xor_out := rand(124) xor rand(123) xor rand(17) xor rand(16);
elsif(rand'length = 126) then --126
xor_out := rand(125) xor rand(124) xor rand(89) xor rand(88);
elsif(rand'length = 127) then --127
xor_out := rand(126) xor rand(125);
elsif(rand'length = 128) then --128
xor_out := rand(127) xor rand(125) xor rand(100) xor rand(98);
elsif(rand'length = 129) then --129
xor_out := rand(128) xor rand(123);
elsif(rand'length = 130) then --130
xor_out := rand(129) xor rand(126);
elsif(rand'length = 131) then --131
xor_out := rand(130) xor rand(129) xor rand(83) xor rand(82);
elsif(rand'length = 132) then --132
xor_out := rand(131) xor rand(102);
elsif(rand'length = 133) then --133
xor_out := rand(132) xor rand(131) xor rand(81) xor rand(80);
elsif(rand'length = 134) then --134
xor_out := rand(133) xor rand(76);
elsif(rand'length = 135) then --135
xor_out := rand(134) xor rand(123);
elsif(rand'length = 136) then --136
xor_out := rand(135) xor rand(134) xor rand(10) xor rand(9);
elsif(rand'length = 137) then --137
xor_out := rand(136) xor rand(115);
elsif(rand'length = 138) then --138
xor_out := rand(137) xor rand(136) xor rand(130) xor rand(129);
elsif(rand'length = 139) then --139
xor_out := rand(138) xor rand(135) xor rand(133) xor rand(130);
elsif(rand'length = 140) then --140
xor_out := rand(139) xor rand(110);
elsif(rand'length = 141) then --141
xor_out := rand(140) xor rand(139) xor rand(109) xor rand(108);
elsif(rand'length = 142) then --142
xor_out := rand(141) xor rand(120);
elsif(rand'length = 143) then --143
xor_out := rand(142) xor rand(141) xor rand(122) xor rand(121);
elsif(rand'length = 144) then --144
xor_out := rand(143) xor rand(142) xor rand(74) xor rand(73);
elsif(rand'length = 145) then --145
xor_out := rand(144) xor rand(92);
elsif(rand'length = 146) then --146
xor_out := rand(145) xor rand(144) xor rand(86) xor rand(85);
elsif(rand'length = 147) then --147
xor_out := rand(146) xor rand(145) xor rand(109) xor rand(108);
elsif(rand'length = 148) then --148
xor_out := rand(147) xor rand(120);
elsif(rand'length = 149) then --149
xor_out := rand(148) xor rand(147) xor rand(39) xor rand(38);
elsif(rand'length = 150) then --150
xor_out := rand(149) xor rand(96);
elsif(rand'length = 151) then --151
xor_out := rand(150) xor rand(147);
elsif(rand'length = 152) then --152
xor_out := rand(151) xor rand(150) xor rand(86) xor rand(85);
elsif(rand'length = 153) then --153
xor_out := rand(152) xor rand(151);
elsif(rand'length = 154) then --154
xor_out := rand(153) xor rand(151) xor rand(26) xor rand(24);
elsif(rand'length = 155) then --155
xor_out := rand(154) xor rand(153) xor rand(123) xor rand(122);
elsif(rand'length = 156) then --156
xor_out := rand(155) xor rand(154) xor rand(40) xor rand(39);
elsif(rand'length = 157) then --157
xor_out := rand(156) xor rand(155) xor rand(130) xor rand(129);
elsif(rand'length = 158) then --158
xor_out := rand(157) xor rand(156) xor rand(131) xor rand(130);
elsif(rand'length = 159) then --159
xor_out := rand(158) xor rand(127);
elsif(rand'length = 160) then --160
xor_out := rand(159) xor rand(158) xor rand(141) xor rand(140);
elsif(rand'length = 161) then --161
xor_out := rand(160) xor rand(142);
elsif(rand'length = 162) then --162
xor_out := rand(161) xor rand(160) xor rand(74) xor rand(73);
elsif(rand'length = 163) then --163
xor_out := rand(162) xor rand(161) xor rand(103) xor rand(102);
elsif(rand'length = 164) then --164
xor_out := rand(163) xor rand(162) xor rand(150) xor rand(149);
elsif(rand'length = 165) then --165
xor_out := rand(164) xor rand(163) xor rand(134) xor rand(133);
elsif(rand'length = 166) then --166
xor_out := rand(165) xor rand(164) xor rand(127) xor rand(126);
elsif(rand'length = 167) then --167
xor_out := rand(166) xor rand(160);
elsif(rand'length = 168) then --168
xor_out := rand(167) xor rand(165) xor rand(152) xor rand(150);
end if;
return xor_out;
end xor_gates;
--END function for XORing using tap values.
end lfsr_pkg;
--End of the package.
|
----------------------------------------------------------------------------
---- Create Date: 14:30:08 07/28/2010 ----
---- Design Name: lfsr_pkg ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- This is the package file used in the lfsr_randgen project.The ----
---- package contain the function for XORing bits from various tap ----
---- locations depending on the generic parameter(width of lfsr ) ----
---- ----
----------------------------------------------------------------------------
---- ----
---- This file is a part of the lfsr_randgen project at ----
---- http://www.opencores.org/ ----
---- ----
---- Author(s): ----
---- Vipin Lal, [email protected] ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2010 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lfsr_pkg is
function xor_gates( random : std_logic_vector) return std_logic;
end lfsr_pkg;
--Package body starts from here.
package body lfsr_pkg is
--function for XORing from tap values.
function xor_gates( random : std_logic_vector ) return std_logic is
variable xor_out : std_logic:='0';
variable rand : std_logic_vector(random'length-1 downto 0):=random;
begin
if(rand'length = 3) then --3
xor_out := rand(2) xor rand(1);
elsif(rand'length = 2) then --2
xor_out := rand(1) xor rand(0);
elsif(rand'length = 4) then --4
xor_out := rand(3) xor rand(2);
elsif(rand'length = 5) then --5
xor_out := rand(4) xor rand(2);
elsif(rand'length = 6) then --6
xor_out := rand(5) xor rand(4);
elsif(rand'length = 7) then --7
xor_out := rand(6) xor rand(5);
elsif(rand'length = 8) then --8
xor_out := rand(7) xor rand(5) xor rand(4) xor rand(3);
elsif(rand'length = 9) then --9
xor_out := rand(8) xor rand(4);
elsif(rand'length = 10)then --10
xor_out := rand(9) xor rand(6);
elsif(rand'length =11) then --11
xor_out := rand(10) xor rand(8);
elsif(rand'length = 12) then --12
xor_out := rand(11) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 13) then --13
xor_out := rand(12) xor rand(3) xor rand(2) xor rand(0);
elsif(rand'length = 14) then --14
xor_out := rand(13) xor rand(4) xor rand(2) xor rand(0);
elsif(rand'length = 15) then --15
xor_out := rand(14) xor rand(13);
elsif(rand'length = 16) then --16
xor_out := rand(15) xor rand(14) xor rand(12) xor rand(3);
elsif(rand'length = 17) then --17
xor_out := rand(16) xor rand(13);
elsif(rand'length = 18) then --18
xor_out := rand(17) xor rand(10);
elsif(rand'length = 19) then --19
xor_out := rand(18) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 20) then --20
xor_out := rand(19) xor rand(16);
elsif(rand'length = 21) then --21
xor_out := rand(20) xor rand(18);
elsif(rand'length = 22) then --22
xor_out := rand(21) xor rand(20);
elsif(rand'length = 23) then --23
xor_out := rand(22) xor rand(17);
elsif(rand'length = 24) then --24
xor_out := rand(23) xor rand(22) xor rand(21) xor rand(16);
elsif(rand'length = 25) then --25
xor_out := rand(24) xor rand(21);
elsif(rand'length = 26) then --26
xor_out := rand(25) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 27) then --27
xor_out := rand(26) xor rand(4) xor rand(1) xor rand(0);
elsif(rand'length = 28) then --28
xor_out := rand(27) xor rand(24);
elsif(rand'length = 29) then --29
xor_out := rand(28) xor rand(26);
elsif(rand'length = 30) then --30
xor_out := rand(29) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 31) then --31
xor_out := rand(30) xor rand(27);
elsif(rand'length = 32) then --32
xor_out := rand(31) xor rand(21) xor rand(1) xor rand(0);
elsif(rand'length = 33) then --33
xor_out := rand(32) xor rand(19);
elsif(rand'length = 34) then --34
xor_out := rand(33) xor rand(26) xor rand(1) xor rand(0);
elsif(rand'length = 35) then --35
xor_out := rand(34) xor rand(32);
elsif(rand'length = 36) then --36
xor_out := rand(35) xor rand(24);
elsif(rand'length = 37) then --37
xor_out := rand(36) xor rand(4) xor rand(3) xor rand(2) xor rand(1) xor rand(0);
elsif(rand'length = 38) then --38
xor_out := rand(37) xor rand(5) xor rand(4) xor rand(0);
elsif(rand'length = 39) then --39
xor_out := rand(38) xor rand(34);
elsif(rand'length = 40) then --40
xor_out := rand(39) xor rand(37) xor rand(20) xor rand(18);
elsif(rand'length = 41) then --41
xor_out := rand(40) xor rand(37);
elsif(rand'length = 42) then --42
xor_out := rand(41) xor rand(40) xor rand(19) xor rand(18);
elsif(rand'length = 43) then --43
xor_out := rand(42) xor rand(41) xor rand(37) xor rand(36);
elsif(rand'length = 44) then --44
xor_out := rand(43) xor rand(42) xor rand(17) xor rand(16);
elsif(rand'length = 45) then --45
xor_out := rand(44) xor rand(43) xor rand(41) xor rand(40);
elsif(rand'length = 46) then --46
xor_out := rand(45) xor rand(44) xor rand(25) xor rand(24);
elsif(rand'length = 47) then --47
xor_out := rand(46) xor rand(41);
elsif(rand'length = 48) then --48
xor_out := rand(47) xor rand(46) xor rand(20) xor rand(19);
elsif(rand'length = 49) then --49
xor_out := rand(48) xor rand(39);
elsif(rand'length = 50) then --50
xor_out := rand(49) xor rand(48) xor rand(23) xor rand(22);
elsif(rand'length = 51) then --51
xor_out := rand(50) xor rand(49) xor rand(35) xor rand(34);
elsif(rand'length = 52) then --52
xor_out := rand(51) xor rand(48);
elsif(rand'length = 53) then --53
xor_out := rand(52) xor rand(51) xor rand(37) xor rand(36);
elsif(rand'length = 54) then --54
xor_out := rand(53) xor rand(52) xor rand(17) xor rand(16);
elsif(rand'length = 55) then --55
xor_out := rand(54) xor rand(30);
elsif(rand'length = 56) then --56
xor_out := rand(55) xor rand(54) xor rand(34) xor rand(33);
elsif(rand'length = 57) then --57
xor_out := rand(56) xor rand(49);
elsif(rand'length = 58) then --58
xor_out := rand(57) xor rand(38);
elsif(rand'length = 59) then --59
xor_out := rand(58) xor rand(57) xor rand(37) xor rand(36);
elsif(rand'length = 60) then --60
xor_out := rand(59) xor rand(58);
elsif(rand'length = 61) then --61
xor_out := rand(60) xor rand(59) xor rand(45) xor rand(44);
elsif(rand'length = 62) then --62
xor_out := rand(61) xor rand(60) xor rand(5) xor rand(4);
elsif(rand'length = 63) then --63
xor_out := rand(62) xor rand(61);
elsif(rand'length = 64) then --64
xor_out := rand(63) xor rand(62) xor rand(60) xor rand(59);
elsif(rand'length = 65) then --65
xor_out := rand(64) xor rand(46);
elsif(rand'length = 66) then --66
xor_out := rand(65) xor rand(64) xor rand(56) xor rand(55);
elsif(rand'length = 67) then --67
xor_out := rand(66) xor rand(65) xor rand(57) xor rand(56);
elsif(rand'length = 68) then --68
xor_out := rand(67) xor rand(58);
elsif(rand'length = 69) then --69
xor_out := rand(68) xor rand(66) xor rand(41) xor rand(39);
elsif(rand'length = 70) then --70
xor_out := rand(69) xor rand(68) xor rand(54) xor rand(53);
elsif(rand'length = 71) then --71
xor_out := rand(70) xor rand(64);
elsif(rand'length = 72) then --72
xor_out := rand(71) xor rand(65) xor rand(24) xor rand(18);
elsif(rand'length = 73) then --73
xor_out := rand(72) xor rand(47);
elsif(rand'length = 74) then --74
xor_out := rand(73) xor rand(72) xor rand(58) xor rand(57);
elsif(rand'length = 75) then --75
xor_out := rand(74) xor rand(73) xor rand(64) xor rand(63);
elsif(rand'length = 76) then --76
xor_out := rand(75) xor rand(74) xor rand(40) xor rand(39);
elsif(rand'length = 77) then --77
xor_out := rand(76) xor rand(75) xor rand(46) xor rand(45);
elsif(rand'length = 78) then --78
xor_out := rand(77) xor rand(76) xor rand(58) xor rand(57);
elsif(rand'length = 79) then --79
xor_out := rand(78) xor rand(69);
elsif(rand'length = 80) then --80
xor_out := rand(79) xor rand(78) xor rand(42) xor rand(41);
elsif(rand'length = 81) then --81
xor_out := rand(80) xor rand(76);
elsif(rand'length = 82) then --82
xor_out := rand(81) xor rand(78) xor rand(46) xor rand(43);
elsif(rand'length = 83) then --83
xor_out := rand(82) xor rand(81) xor rand(37) xor rand(36);
elsif(rand'length = 84) then --84
xor_out := rand(83) xor rand(70);
elsif(rand'length = 85) then --85
xor_out := rand(84) xor rand(83) xor rand(57) xor rand(56);
elsif(rand'length = 86) then --86
xor_out := rand(85) xor rand(84) xor rand(73) xor rand(72);
elsif(rand'length = 87) then --87
xor_out := rand(86) xor rand(73);
elsif(rand'length = 88) then --88
xor_out := rand(87) xor rand(86) xor rand(16) xor rand(15);
elsif(rand'length = 89) then --89
xor_out := rand(88) xor rand(50);
elsif(rand'length = 90) then --90
xor_out := rand(89) xor rand(88) xor rand(71) xor rand(70);
elsif(rand'length = 91) then --91
xor_out := rand(90) xor rand(89) xor rand(7) xor rand(6);
elsif(rand'length = 92) then --92
xor_out := rand(91) xor rand(90) xor rand(79) xor rand(78);
elsif(rand'length = 93) then --93
xor_out := rand(92) xor rand(90);
elsif(rand'length = 94) then --94
xor_out := rand(93) xor rand(72);
elsif(rand'length = 95) then --95
xor_out := rand(94) xor rand(83);
elsif(rand'length = 96) then --96
xor_out := rand(95) xor rand(93) xor rand(48) xor rand(46);
elsif(rand'length = 97) then --97
xor_out := rand(96) xor rand(90);
elsif(rand'length = 98) then --98
xor_out := rand(97) xor rand(86);
elsif(rand'length = 99) then --99
xor_out := rand(98) xor rand(96) xor rand(53) xor rand(51);
elsif(rand'length = 100) then --100
xor_out := rand(99) xor rand(62);
elsif(rand'length = 101) then --101
xor_out := rand(100) xor rand(99) xor rand(94) xor rand(93);
elsif(rand'length = 102) then --102
xor_out := rand(101) xor rand(100) xor rand(35) xor rand(34);
elsif(rand'length = 103) then --103
xor_out := rand(102) xor rand(93);
elsif(rand'length = 104) then --104
xor_out := rand(103) xor rand(102) xor rand(93) xor rand(92);
elsif(rand'length = 105) then --105
xor_out := rand(104) xor rand(88);
elsif(rand'length = 106) then --106
xor_out := rand(105) xor rand(90);
elsif(rand'length = 107) then --107
xor_out := rand(106) xor rand(104) xor rand(43) xor rand(41);
elsif(rand'length = 108) then --108
xor_out := rand(107) xor rand(76);
elsif(rand'length = 109) then --109
xor_out := rand(108) xor rand(107) xor rand(102) xor rand(101);
elsif(rand'length = 110)then --110
xor_out := rand(109) xor rand(108) xor rand(97) xor rand(96);
elsif(rand'length = 111) then --111
xor_out := rand(110) xor rand(100);
elsif(rand'length = 112) then --112
xor_out := rand(111) xor rand(109) xor rand(68) xor rand(66);
elsif(rand'length = 113) then --113
xor_out := rand(112) xor rand(103);
elsif(rand'length = 114) then --114
xor_out := rand(113) xor rand(112) xor rand(32) xor rand(31);
elsif(rand'length = 115) then --115
xor_out := rand(114) xor rand(113) xor rand(100) xor rand(99);
elsif(rand'length = 116) then --116
xor_out := rand(115) xor rand(114) xor rand(45) xor rand(44);
elsif(rand'length = 117) then --117
xor_out := rand(116) xor rand(114) xor rand(98) xor rand(96);
elsif(rand'length = 118) then --118
xor_out := rand(117) xor rand(84);
elsif(rand'length = 119) then --119
xor_out := rand(118) xor rand(110);
elsif(rand'length = 120) then --120
xor_out := rand(119) xor rand(112) xor rand(8) xor rand(1);
elsif(rand'length = 121) then --121
xor_out := rand(120) xor rand(102);
elsif(rand'length = 122) then --122
xor_out := rand(121) xor rand(120) xor rand(62) xor rand(61);
elsif(rand'length = 123) then --123
xor_out := rand(122) xor rand(120);
elsif(rand'length = 124) then --124
xor_out := rand(123) xor rand(86);
elsif(rand'length = 125) then --125
xor_out := rand(124) xor rand(123) xor rand(17) xor rand(16);
elsif(rand'length = 126) then --126
xor_out := rand(125) xor rand(124) xor rand(89) xor rand(88);
elsif(rand'length = 127) then --127
xor_out := rand(126) xor rand(125);
elsif(rand'length = 128) then --128
xor_out := rand(127) xor rand(125) xor rand(100) xor rand(98);
elsif(rand'length = 129) then --129
xor_out := rand(128) xor rand(123);
elsif(rand'length = 130) then --130
xor_out := rand(129) xor rand(126);
elsif(rand'length = 131) then --131
xor_out := rand(130) xor rand(129) xor rand(83) xor rand(82);
elsif(rand'length = 132) then --132
xor_out := rand(131) xor rand(102);
elsif(rand'length = 133) then --133
xor_out := rand(132) xor rand(131) xor rand(81) xor rand(80);
elsif(rand'length = 134) then --134
xor_out := rand(133) xor rand(76);
elsif(rand'length = 135) then --135
xor_out := rand(134) xor rand(123);
elsif(rand'length = 136) then --136
xor_out := rand(135) xor rand(134) xor rand(10) xor rand(9);
elsif(rand'length = 137) then --137
xor_out := rand(136) xor rand(115);
elsif(rand'length = 138) then --138
xor_out := rand(137) xor rand(136) xor rand(130) xor rand(129);
elsif(rand'length = 139) then --139
xor_out := rand(138) xor rand(135) xor rand(133) xor rand(130);
elsif(rand'length = 140) then --140
xor_out := rand(139) xor rand(110);
elsif(rand'length = 141) then --141
xor_out := rand(140) xor rand(139) xor rand(109) xor rand(108);
elsif(rand'length = 142) then --142
xor_out := rand(141) xor rand(120);
elsif(rand'length = 143) then --143
xor_out := rand(142) xor rand(141) xor rand(122) xor rand(121);
elsif(rand'length = 144) then --144
xor_out := rand(143) xor rand(142) xor rand(74) xor rand(73);
elsif(rand'length = 145) then --145
xor_out := rand(144) xor rand(92);
elsif(rand'length = 146) then --146
xor_out := rand(145) xor rand(144) xor rand(86) xor rand(85);
elsif(rand'length = 147) then --147
xor_out := rand(146) xor rand(145) xor rand(109) xor rand(108);
elsif(rand'length = 148) then --148
xor_out := rand(147) xor rand(120);
elsif(rand'length = 149) then --149
xor_out := rand(148) xor rand(147) xor rand(39) xor rand(38);
elsif(rand'length = 150) then --150
xor_out := rand(149) xor rand(96);
elsif(rand'length = 151) then --151
xor_out := rand(150) xor rand(147);
elsif(rand'length = 152) then --152
xor_out := rand(151) xor rand(150) xor rand(86) xor rand(85);
elsif(rand'length = 153) then --153
xor_out := rand(152) xor rand(151);
elsif(rand'length = 154) then --154
xor_out := rand(153) xor rand(151) xor rand(26) xor rand(24);
elsif(rand'length = 155) then --155
xor_out := rand(154) xor rand(153) xor rand(123) xor rand(122);
elsif(rand'length = 156) then --156
xor_out := rand(155) xor rand(154) xor rand(40) xor rand(39);
elsif(rand'length = 157) then --157
xor_out := rand(156) xor rand(155) xor rand(130) xor rand(129);
elsif(rand'length = 158) then --158
xor_out := rand(157) xor rand(156) xor rand(131) xor rand(130);
elsif(rand'length = 159) then --159
xor_out := rand(158) xor rand(127);
elsif(rand'length = 160) then --160
xor_out := rand(159) xor rand(158) xor rand(141) xor rand(140);
elsif(rand'length = 161) then --161
xor_out := rand(160) xor rand(142);
elsif(rand'length = 162) then --162
xor_out := rand(161) xor rand(160) xor rand(74) xor rand(73);
elsif(rand'length = 163) then --163
xor_out := rand(162) xor rand(161) xor rand(103) xor rand(102);
elsif(rand'length = 164) then --164
xor_out := rand(163) xor rand(162) xor rand(150) xor rand(149);
elsif(rand'length = 165) then --165
xor_out := rand(164) xor rand(163) xor rand(134) xor rand(133);
elsif(rand'length = 166) then --166
xor_out := rand(165) xor rand(164) xor rand(127) xor rand(126);
elsif(rand'length = 167) then --167
xor_out := rand(166) xor rand(160);
elsif(rand'length = 168) then --168
xor_out := rand(167) xor rand(165) xor rand(152) xor rand(150);
end if;
return xor_out;
end xor_gates;
--END function for XORing using tap values.
end lfsr_pkg;
--End of the package.
|
----------------------------------------------------------------------------
---- Create Date: 14:30:08 07/28/2010 ----
---- Design Name: lfsr_pkg ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- This is the package file used in the lfsr_randgen project.The ----
---- package contain the function for XORing bits from various tap ----
---- locations depending on the generic parameter(width of lfsr ) ----
---- ----
----------------------------------------------------------------------------
---- ----
---- This file is a part of the lfsr_randgen project at ----
---- http://www.opencores.org/ ----
---- ----
---- Author(s): ----
---- Vipin Lal, [email protected] ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2010 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lfsr_pkg is
function xor_gates( random : std_logic_vector) return std_logic;
end lfsr_pkg;
--Package body starts from here.
package body lfsr_pkg is
--function for XORing from tap values.
function xor_gates( random : std_logic_vector ) return std_logic is
variable xor_out : std_logic:='0';
variable rand : std_logic_vector(random'length-1 downto 0):=random;
begin
if(rand'length = 3) then --3
xor_out := rand(2) xor rand(1);
elsif(rand'length = 2) then --2
xor_out := rand(1) xor rand(0);
elsif(rand'length = 4) then --4
xor_out := rand(3) xor rand(2);
elsif(rand'length = 5) then --5
xor_out := rand(4) xor rand(2);
elsif(rand'length = 6) then --6
xor_out := rand(5) xor rand(4);
elsif(rand'length = 7) then --7
xor_out := rand(6) xor rand(5);
elsif(rand'length = 8) then --8
xor_out := rand(7) xor rand(5) xor rand(4) xor rand(3);
elsif(rand'length = 9) then --9
xor_out := rand(8) xor rand(4);
elsif(rand'length = 10)then --10
xor_out := rand(9) xor rand(6);
elsif(rand'length =11) then --11
xor_out := rand(10) xor rand(8);
elsif(rand'length = 12) then --12
xor_out := rand(11) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 13) then --13
xor_out := rand(12) xor rand(3) xor rand(2) xor rand(0);
elsif(rand'length = 14) then --14
xor_out := rand(13) xor rand(4) xor rand(2) xor rand(0);
elsif(rand'length = 15) then --15
xor_out := rand(14) xor rand(13);
elsif(rand'length = 16) then --16
xor_out := rand(15) xor rand(14) xor rand(12) xor rand(3);
elsif(rand'length = 17) then --17
xor_out := rand(16) xor rand(13);
elsif(rand'length = 18) then --18
xor_out := rand(17) xor rand(10);
elsif(rand'length = 19) then --19
xor_out := rand(18) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 20) then --20
xor_out := rand(19) xor rand(16);
elsif(rand'length = 21) then --21
xor_out := rand(20) xor rand(18);
elsif(rand'length = 22) then --22
xor_out := rand(21) xor rand(20);
elsif(rand'length = 23) then --23
xor_out := rand(22) xor rand(17);
elsif(rand'length = 24) then --24
xor_out := rand(23) xor rand(22) xor rand(21) xor rand(16);
elsif(rand'length = 25) then --25
xor_out := rand(24) xor rand(21);
elsif(rand'length = 26) then --26
xor_out := rand(25) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 27) then --27
xor_out := rand(26) xor rand(4) xor rand(1) xor rand(0);
elsif(rand'length = 28) then --28
xor_out := rand(27) xor rand(24);
elsif(rand'length = 29) then --29
xor_out := rand(28) xor rand(26);
elsif(rand'length = 30) then --30
xor_out := rand(29) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 31) then --31
xor_out := rand(30) xor rand(27);
elsif(rand'length = 32) then --32
xor_out := rand(31) xor rand(21) xor rand(1) xor rand(0);
elsif(rand'length = 33) then --33
xor_out := rand(32) xor rand(19);
elsif(rand'length = 34) then --34
xor_out := rand(33) xor rand(26) xor rand(1) xor rand(0);
elsif(rand'length = 35) then --35
xor_out := rand(34) xor rand(32);
elsif(rand'length = 36) then --36
xor_out := rand(35) xor rand(24);
elsif(rand'length = 37) then --37
xor_out := rand(36) xor rand(4) xor rand(3) xor rand(2) xor rand(1) xor rand(0);
elsif(rand'length = 38) then --38
xor_out := rand(37) xor rand(5) xor rand(4) xor rand(0);
elsif(rand'length = 39) then --39
xor_out := rand(38) xor rand(34);
elsif(rand'length = 40) then --40
xor_out := rand(39) xor rand(37) xor rand(20) xor rand(18);
elsif(rand'length = 41) then --41
xor_out := rand(40) xor rand(37);
elsif(rand'length = 42) then --42
xor_out := rand(41) xor rand(40) xor rand(19) xor rand(18);
elsif(rand'length = 43) then --43
xor_out := rand(42) xor rand(41) xor rand(37) xor rand(36);
elsif(rand'length = 44) then --44
xor_out := rand(43) xor rand(42) xor rand(17) xor rand(16);
elsif(rand'length = 45) then --45
xor_out := rand(44) xor rand(43) xor rand(41) xor rand(40);
elsif(rand'length = 46) then --46
xor_out := rand(45) xor rand(44) xor rand(25) xor rand(24);
elsif(rand'length = 47) then --47
xor_out := rand(46) xor rand(41);
elsif(rand'length = 48) then --48
xor_out := rand(47) xor rand(46) xor rand(20) xor rand(19);
elsif(rand'length = 49) then --49
xor_out := rand(48) xor rand(39);
elsif(rand'length = 50) then --50
xor_out := rand(49) xor rand(48) xor rand(23) xor rand(22);
elsif(rand'length = 51) then --51
xor_out := rand(50) xor rand(49) xor rand(35) xor rand(34);
elsif(rand'length = 52) then --52
xor_out := rand(51) xor rand(48);
elsif(rand'length = 53) then --53
xor_out := rand(52) xor rand(51) xor rand(37) xor rand(36);
elsif(rand'length = 54) then --54
xor_out := rand(53) xor rand(52) xor rand(17) xor rand(16);
elsif(rand'length = 55) then --55
xor_out := rand(54) xor rand(30);
elsif(rand'length = 56) then --56
xor_out := rand(55) xor rand(54) xor rand(34) xor rand(33);
elsif(rand'length = 57) then --57
xor_out := rand(56) xor rand(49);
elsif(rand'length = 58) then --58
xor_out := rand(57) xor rand(38);
elsif(rand'length = 59) then --59
xor_out := rand(58) xor rand(57) xor rand(37) xor rand(36);
elsif(rand'length = 60) then --60
xor_out := rand(59) xor rand(58);
elsif(rand'length = 61) then --61
xor_out := rand(60) xor rand(59) xor rand(45) xor rand(44);
elsif(rand'length = 62) then --62
xor_out := rand(61) xor rand(60) xor rand(5) xor rand(4);
elsif(rand'length = 63) then --63
xor_out := rand(62) xor rand(61);
elsif(rand'length = 64) then --64
xor_out := rand(63) xor rand(62) xor rand(60) xor rand(59);
elsif(rand'length = 65) then --65
xor_out := rand(64) xor rand(46);
elsif(rand'length = 66) then --66
xor_out := rand(65) xor rand(64) xor rand(56) xor rand(55);
elsif(rand'length = 67) then --67
xor_out := rand(66) xor rand(65) xor rand(57) xor rand(56);
elsif(rand'length = 68) then --68
xor_out := rand(67) xor rand(58);
elsif(rand'length = 69) then --69
xor_out := rand(68) xor rand(66) xor rand(41) xor rand(39);
elsif(rand'length = 70) then --70
xor_out := rand(69) xor rand(68) xor rand(54) xor rand(53);
elsif(rand'length = 71) then --71
xor_out := rand(70) xor rand(64);
elsif(rand'length = 72) then --72
xor_out := rand(71) xor rand(65) xor rand(24) xor rand(18);
elsif(rand'length = 73) then --73
xor_out := rand(72) xor rand(47);
elsif(rand'length = 74) then --74
xor_out := rand(73) xor rand(72) xor rand(58) xor rand(57);
elsif(rand'length = 75) then --75
xor_out := rand(74) xor rand(73) xor rand(64) xor rand(63);
elsif(rand'length = 76) then --76
xor_out := rand(75) xor rand(74) xor rand(40) xor rand(39);
elsif(rand'length = 77) then --77
xor_out := rand(76) xor rand(75) xor rand(46) xor rand(45);
elsif(rand'length = 78) then --78
xor_out := rand(77) xor rand(76) xor rand(58) xor rand(57);
elsif(rand'length = 79) then --79
xor_out := rand(78) xor rand(69);
elsif(rand'length = 80) then --80
xor_out := rand(79) xor rand(78) xor rand(42) xor rand(41);
elsif(rand'length = 81) then --81
xor_out := rand(80) xor rand(76);
elsif(rand'length = 82) then --82
xor_out := rand(81) xor rand(78) xor rand(46) xor rand(43);
elsif(rand'length = 83) then --83
xor_out := rand(82) xor rand(81) xor rand(37) xor rand(36);
elsif(rand'length = 84) then --84
xor_out := rand(83) xor rand(70);
elsif(rand'length = 85) then --85
xor_out := rand(84) xor rand(83) xor rand(57) xor rand(56);
elsif(rand'length = 86) then --86
xor_out := rand(85) xor rand(84) xor rand(73) xor rand(72);
elsif(rand'length = 87) then --87
xor_out := rand(86) xor rand(73);
elsif(rand'length = 88) then --88
xor_out := rand(87) xor rand(86) xor rand(16) xor rand(15);
elsif(rand'length = 89) then --89
xor_out := rand(88) xor rand(50);
elsif(rand'length = 90) then --90
xor_out := rand(89) xor rand(88) xor rand(71) xor rand(70);
elsif(rand'length = 91) then --91
xor_out := rand(90) xor rand(89) xor rand(7) xor rand(6);
elsif(rand'length = 92) then --92
xor_out := rand(91) xor rand(90) xor rand(79) xor rand(78);
elsif(rand'length = 93) then --93
xor_out := rand(92) xor rand(90);
elsif(rand'length = 94) then --94
xor_out := rand(93) xor rand(72);
elsif(rand'length = 95) then --95
xor_out := rand(94) xor rand(83);
elsif(rand'length = 96) then --96
xor_out := rand(95) xor rand(93) xor rand(48) xor rand(46);
elsif(rand'length = 97) then --97
xor_out := rand(96) xor rand(90);
elsif(rand'length = 98) then --98
xor_out := rand(97) xor rand(86);
elsif(rand'length = 99) then --99
xor_out := rand(98) xor rand(96) xor rand(53) xor rand(51);
elsif(rand'length = 100) then --100
xor_out := rand(99) xor rand(62);
elsif(rand'length = 101) then --101
xor_out := rand(100) xor rand(99) xor rand(94) xor rand(93);
elsif(rand'length = 102) then --102
xor_out := rand(101) xor rand(100) xor rand(35) xor rand(34);
elsif(rand'length = 103) then --103
xor_out := rand(102) xor rand(93);
elsif(rand'length = 104) then --104
xor_out := rand(103) xor rand(102) xor rand(93) xor rand(92);
elsif(rand'length = 105) then --105
xor_out := rand(104) xor rand(88);
elsif(rand'length = 106) then --106
xor_out := rand(105) xor rand(90);
elsif(rand'length = 107) then --107
xor_out := rand(106) xor rand(104) xor rand(43) xor rand(41);
elsif(rand'length = 108) then --108
xor_out := rand(107) xor rand(76);
elsif(rand'length = 109) then --109
xor_out := rand(108) xor rand(107) xor rand(102) xor rand(101);
elsif(rand'length = 110)then --110
xor_out := rand(109) xor rand(108) xor rand(97) xor rand(96);
elsif(rand'length = 111) then --111
xor_out := rand(110) xor rand(100);
elsif(rand'length = 112) then --112
xor_out := rand(111) xor rand(109) xor rand(68) xor rand(66);
elsif(rand'length = 113) then --113
xor_out := rand(112) xor rand(103);
elsif(rand'length = 114) then --114
xor_out := rand(113) xor rand(112) xor rand(32) xor rand(31);
elsif(rand'length = 115) then --115
xor_out := rand(114) xor rand(113) xor rand(100) xor rand(99);
elsif(rand'length = 116) then --116
xor_out := rand(115) xor rand(114) xor rand(45) xor rand(44);
elsif(rand'length = 117) then --117
xor_out := rand(116) xor rand(114) xor rand(98) xor rand(96);
elsif(rand'length = 118) then --118
xor_out := rand(117) xor rand(84);
elsif(rand'length = 119) then --119
xor_out := rand(118) xor rand(110);
elsif(rand'length = 120) then --120
xor_out := rand(119) xor rand(112) xor rand(8) xor rand(1);
elsif(rand'length = 121) then --121
xor_out := rand(120) xor rand(102);
elsif(rand'length = 122) then --122
xor_out := rand(121) xor rand(120) xor rand(62) xor rand(61);
elsif(rand'length = 123) then --123
xor_out := rand(122) xor rand(120);
elsif(rand'length = 124) then --124
xor_out := rand(123) xor rand(86);
elsif(rand'length = 125) then --125
xor_out := rand(124) xor rand(123) xor rand(17) xor rand(16);
elsif(rand'length = 126) then --126
xor_out := rand(125) xor rand(124) xor rand(89) xor rand(88);
elsif(rand'length = 127) then --127
xor_out := rand(126) xor rand(125);
elsif(rand'length = 128) then --128
xor_out := rand(127) xor rand(125) xor rand(100) xor rand(98);
elsif(rand'length = 129) then --129
xor_out := rand(128) xor rand(123);
elsif(rand'length = 130) then --130
xor_out := rand(129) xor rand(126);
elsif(rand'length = 131) then --131
xor_out := rand(130) xor rand(129) xor rand(83) xor rand(82);
elsif(rand'length = 132) then --132
xor_out := rand(131) xor rand(102);
elsif(rand'length = 133) then --133
xor_out := rand(132) xor rand(131) xor rand(81) xor rand(80);
elsif(rand'length = 134) then --134
xor_out := rand(133) xor rand(76);
elsif(rand'length = 135) then --135
xor_out := rand(134) xor rand(123);
elsif(rand'length = 136) then --136
xor_out := rand(135) xor rand(134) xor rand(10) xor rand(9);
elsif(rand'length = 137) then --137
xor_out := rand(136) xor rand(115);
elsif(rand'length = 138) then --138
xor_out := rand(137) xor rand(136) xor rand(130) xor rand(129);
elsif(rand'length = 139) then --139
xor_out := rand(138) xor rand(135) xor rand(133) xor rand(130);
elsif(rand'length = 140) then --140
xor_out := rand(139) xor rand(110);
elsif(rand'length = 141) then --141
xor_out := rand(140) xor rand(139) xor rand(109) xor rand(108);
elsif(rand'length = 142) then --142
xor_out := rand(141) xor rand(120);
elsif(rand'length = 143) then --143
xor_out := rand(142) xor rand(141) xor rand(122) xor rand(121);
elsif(rand'length = 144) then --144
xor_out := rand(143) xor rand(142) xor rand(74) xor rand(73);
elsif(rand'length = 145) then --145
xor_out := rand(144) xor rand(92);
elsif(rand'length = 146) then --146
xor_out := rand(145) xor rand(144) xor rand(86) xor rand(85);
elsif(rand'length = 147) then --147
xor_out := rand(146) xor rand(145) xor rand(109) xor rand(108);
elsif(rand'length = 148) then --148
xor_out := rand(147) xor rand(120);
elsif(rand'length = 149) then --149
xor_out := rand(148) xor rand(147) xor rand(39) xor rand(38);
elsif(rand'length = 150) then --150
xor_out := rand(149) xor rand(96);
elsif(rand'length = 151) then --151
xor_out := rand(150) xor rand(147);
elsif(rand'length = 152) then --152
xor_out := rand(151) xor rand(150) xor rand(86) xor rand(85);
elsif(rand'length = 153) then --153
xor_out := rand(152) xor rand(151);
elsif(rand'length = 154) then --154
xor_out := rand(153) xor rand(151) xor rand(26) xor rand(24);
elsif(rand'length = 155) then --155
xor_out := rand(154) xor rand(153) xor rand(123) xor rand(122);
elsif(rand'length = 156) then --156
xor_out := rand(155) xor rand(154) xor rand(40) xor rand(39);
elsif(rand'length = 157) then --157
xor_out := rand(156) xor rand(155) xor rand(130) xor rand(129);
elsif(rand'length = 158) then --158
xor_out := rand(157) xor rand(156) xor rand(131) xor rand(130);
elsif(rand'length = 159) then --159
xor_out := rand(158) xor rand(127);
elsif(rand'length = 160) then --160
xor_out := rand(159) xor rand(158) xor rand(141) xor rand(140);
elsif(rand'length = 161) then --161
xor_out := rand(160) xor rand(142);
elsif(rand'length = 162) then --162
xor_out := rand(161) xor rand(160) xor rand(74) xor rand(73);
elsif(rand'length = 163) then --163
xor_out := rand(162) xor rand(161) xor rand(103) xor rand(102);
elsif(rand'length = 164) then --164
xor_out := rand(163) xor rand(162) xor rand(150) xor rand(149);
elsif(rand'length = 165) then --165
xor_out := rand(164) xor rand(163) xor rand(134) xor rand(133);
elsif(rand'length = 166) then --166
xor_out := rand(165) xor rand(164) xor rand(127) xor rand(126);
elsif(rand'length = 167) then --167
xor_out := rand(166) xor rand(160);
elsif(rand'length = 168) then --168
xor_out := rand(167) xor rand(165) xor rand(152) xor rand(150);
end if;
return xor_out;
end xor_gates;
--END function for XORing using tap values.
end lfsr_pkg;
--End of the package.
|
----------------------------------------------------------------------------
---- Create Date: 14:30:08 07/28/2010 ----
---- Design Name: lfsr_pkg ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- This is the package file used in the lfsr_randgen project.The ----
---- package contain the function for XORing bits from various tap ----
---- locations depending on the generic parameter(width of lfsr ) ----
---- ----
----------------------------------------------------------------------------
---- ----
---- This file is a part of the lfsr_randgen project at ----
---- http://www.opencores.org/ ----
---- ----
---- Author(s): ----
---- Vipin Lal, [email protected] ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2010 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lfsr_pkg is
function xor_gates( random : std_logic_vector) return std_logic;
end lfsr_pkg;
--Package body starts from here.
package body lfsr_pkg is
--function for XORing from tap values.
function xor_gates( random : std_logic_vector ) return std_logic is
variable xor_out : std_logic:='0';
variable rand : std_logic_vector(random'length-1 downto 0):=random;
begin
if(rand'length = 3) then --3
xor_out := rand(2) xor rand(1);
elsif(rand'length = 2) then --2
xor_out := rand(1) xor rand(0);
elsif(rand'length = 4) then --4
xor_out := rand(3) xor rand(2);
elsif(rand'length = 5) then --5
xor_out := rand(4) xor rand(2);
elsif(rand'length = 6) then --6
xor_out := rand(5) xor rand(4);
elsif(rand'length = 7) then --7
xor_out := rand(6) xor rand(5);
elsif(rand'length = 8) then --8
xor_out := rand(7) xor rand(5) xor rand(4) xor rand(3);
elsif(rand'length = 9) then --9
xor_out := rand(8) xor rand(4);
elsif(rand'length = 10)then --10
xor_out := rand(9) xor rand(6);
elsif(rand'length =11) then --11
xor_out := rand(10) xor rand(8);
elsif(rand'length = 12) then --12
xor_out := rand(11) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 13) then --13
xor_out := rand(12) xor rand(3) xor rand(2) xor rand(0);
elsif(rand'length = 14) then --14
xor_out := rand(13) xor rand(4) xor rand(2) xor rand(0);
elsif(rand'length = 15) then --15
xor_out := rand(14) xor rand(13);
elsif(rand'length = 16) then --16
xor_out := rand(15) xor rand(14) xor rand(12) xor rand(3);
elsif(rand'length = 17) then --17
xor_out := rand(16) xor rand(13);
elsif(rand'length = 18) then --18
xor_out := rand(17) xor rand(10);
elsif(rand'length = 19) then --19
xor_out := rand(18) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 20) then --20
xor_out := rand(19) xor rand(16);
elsif(rand'length = 21) then --21
xor_out := rand(20) xor rand(18);
elsif(rand'length = 22) then --22
xor_out := rand(21) xor rand(20);
elsif(rand'length = 23) then --23
xor_out := rand(22) xor rand(17);
elsif(rand'length = 24) then --24
xor_out := rand(23) xor rand(22) xor rand(21) xor rand(16);
elsif(rand'length = 25) then --25
xor_out := rand(24) xor rand(21);
elsif(rand'length = 26) then --26
xor_out := rand(25) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 27) then --27
xor_out := rand(26) xor rand(4) xor rand(1) xor rand(0);
elsif(rand'length = 28) then --28
xor_out := rand(27) xor rand(24);
elsif(rand'length = 29) then --29
xor_out := rand(28) xor rand(26);
elsif(rand'length = 30) then --30
xor_out := rand(29) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 31) then --31
xor_out := rand(30) xor rand(27);
elsif(rand'length = 32) then --32
xor_out := rand(31) xor rand(21) xor rand(1) xor rand(0);
elsif(rand'length = 33) then --33
xor_out := rand(32) xor rand(19);
elsif(rand'length = 34) then --34
xor_out := rand(33) xor rand(26) xor rand(1) xor rand(0);
elsif(rand'length = 35) then --35
xor_out := rand(34) xor rand(32);
elsif(rand'length = 36) then --36
xor_out := rand(35) xor rand(24);
elsif(rand'length = 37) then --37
xor_out := rand(36) xor rand(4) xor rand(3) xor rand(2) xor rand(1) xor rand(0);
elsif(rand'length = 38) then --38
xor_out := rand(37) xor rand(5) xor rand(4) xor rand(0);
elsif(rand'length = 39) then --39
xor_out := rand(38) xor rand(34);
elsif(rand'length = 40) then --40
xor_out := rand(39) xor rand(37) xor rand(20) xor rand(18);
elsif(rand'length = 41) then --41
xor_out := rand(40) xor rand(37);
elsif(rand'length = 42) then --42
xor_out := rand(41) xor rand(40) xor rand(19) xor rand(18);
elsif(rand'length = 43) then --43
xor_out := rand(42) xor rand(41) xor rand(37) xor rand(36);
elsif(rand'length = 44) then --44
xor_out := rand(43) xor rand(42) xor rand(17) xor rand(16);
elsif(rand'length = 45) then --45
xor_out := rand(44) xor rand(43) xor rand(41) xor rand(40);
elsif(rand'length = 46) then --46
xor_out := rand(45) xor rand(44) xor rand(25) xor rand(24);
elsif(rand'length = 47) then --47
xor_out := rand(46) xor rand(41);
elsif(rand'length = 48) then --48
xor_out := rand(47) xor rand(46) xor rand(20) xor rand(19);
elsif(rand'length = 49) then --49
xor_out := rand(48) xor rand(39);
elsif(rand'length = 50) then --50
xor_out := rand(49) xor rand(48) xor rand(23) xor rand(22);
elsif(rand'length = 51) then --51
xor_out := rand(50) xor rand(49) xor rand(35) xor rand(34);
elsif(rand'length = 52) then --52
xor_out := rand(51) xor rand(48);
elsif(rand'length = 53) then --53
xor_out := rand(52) xor rand(51) xor rand(37) xor rand(36);
elsif(rand'length = 54) then --54
xor_out := rand(53) xor rand(52) xor rand(17) xor rand(16);
elsif(rand'length = 55) then --55
xor_out := rand(54) xor rand(30);
elsif(rand'length = 56) then --56
xor_out := rand(55) xor rand(54) xor rand(34) xor rand(33);
elsif(rand'length = 57) then --57
xor_out := rand(56) xor rand(49);
elsif(rand'length = 58) then --58
xor_out := rand(57) xor rand(38);
elsif(rand'length = 59) then --59
xor_out := rand(58) xor rand(57) xor rand(37) xor rand(36);
elsif(rand'length = 60) then --60
xor_out := rand(59) xor rand(58);
elsif(rand'length = 61) then --61
xor_out := rand(60) xor rand(59) xor rand(45) xor rand(44);
elsif(rand'length = 62) then --62
xor_out := rand(61) xor rand(60) xor rand(5) xor rand(4);
elsif(rand'length = 63) then --63
xor_out := rand(62) xor rand(61);
elsif(rand'length = 64) then --64
xor_out := rand(63) xor rand(62) xor rand(60) xor rand(59);
elsif(rand'length = 65) then --65
xor_out := rand(64) xor rand(46);
elsif(rand'length = 66) then --66
xor_out := rand(65) xor rand(64) xor rand(56) xor rand(55);
elsif(rand'length = 67) then --67
xor_out := rand(66) xor rand(65) xor rand(57) xor rand(56);
elsif(rand'length = 68) then --68
xor_out := rand(67) xor rand(58);
elsif(rand'length = 69) then --69
xor_out := rand(68) xor rand(66) xor rand(41) xor rand(39);
elsif(rand'length = 70) then --70
xor_out := rand(69) xor rand(68) xor rand(54) xor rand(53);
elsif(rand'length = 71) then --71
xor_out := rand(70) xor rand(64);
elsif(rand'length = 72) then --72
xor_out := rand(71) xor rand(65) xor rand(24) xor rand(18);
elsif(rand'length = 73) then --73
xor_out := rand(72) xor rand(47);
elsif(rand'length = 74) then --74
xor_out := rand(73) xor rand(72) xor rand(58) xor rand(57);
elsif(rand'length = 75) then --75
xor_out := rand(74) xor rand(73) xor rand(64) xor rand(63);
elsif(rand'length = 76) then --76
xor_out := rand(75) xor rand(74) xor rand(40) xor rand(39);
elsif(rand'length = 77) then --77
xor_out := rand(76) xor rand(75) xor rand(46) xor rand(45);
elsif(rand'length = 78) then --78
xor_out := rand(77) xor rand(76) xor rand(58) xor rand(57);
elsif(rand'length = 79) then --79
xor_out := rand(78) xor rand(69);
elsif(rand'length = 80) then --80
xor_out := rand(79) xor rand(78) xor rand(42) xor rand(41);
elsif(rand'length = 81) then --81
xor_out := rand(80) xor rand(76);
elsif(rand'length = 82) then --82
xor_out := rand(81) xor rand(78) xor rand(46) xor rand(43);
elsif(rand'length = 83) then --83
xor_out := rand(82) xor rand(81) xor rand(37) xor rand(36);
elsif(rand'length = 84) then --84
xor_out := rand(83) xor rand(70);
elsif(rand'length = 85) then --85
xor_out := rand(84) xor rand(83) xor rand(57) xor rand(56);
elsif(rand'length = 86) then --86
xor_out := rand(85) xor rand(84) xor rand(73) xor rand(72);
elsif(rand'length = 87) then --87
xor_out := rand(86) xor rand(73);
elsif(rand'length = 88) then --88
xor_out := rand(87) xor rand(86) xor rand(16) xor rand(15);
elsif(rand'length = 89) then --89
xor_out := rand(88) xor rand(50);
elsif(rand'length = 90) then --90
xor_out := rand(89) xor rand(88) xor rand(71) xor rand(70);
elsif(rand'length = 91) then --91
xor_out := rand(90) xor rand(89) xor rand(7) xor rand(6);
elsif(rand'length = 92) then --92
xor_out := rand(91) xor rand(90) xor rand(79) xor rand(78);
elsif(rand'length = 93) then --93
xor_out := rand(92) xor rand(90);
elsif(rand'length = 94) then --94
xor_out := rand(93) xor rand(72);
elsif(rand'length = 95) then --95
xor_out := rand(94) xor rand(83);
elsif(rand'length = 96) then --96
xor_out := rand(95) xor rand(93) xor rand(48) xor rand(46);
elsif(rand'length = 97) then --97
xor_out := rand(96) xor rand(90);
elsif(rand'length = 98) then --98
xor_out := rand(97) xor rand(86);
elsif(rand'length = 99) then --99
xor_out := rand(98) xor rand(96) xor rand(53) xor rand(51);
elsif(rand'length = 100) then --100
xor_out := rand(99) xor rand(62);
elsif(rand'length = 101) then --101
xor_out := rand(100) xor rand(99) xor rand(94) xor rand(93);
elsif(rand'length = 102) then --102
xor_out := rand(101) xor rand(100) xor rand(35) xor rand(34);
elsif(rand'length = 103) then --103
xor_out := rand(102) xor rand(93);
elsif(rand'length = 104) then --104
xor_out := rand(103) xor rand(102) xor rand(93) xor rand(92);
elsif(rand'length = 105) then --105
xor_out := rand(104) xor rand(88);
elsif(rand'length = 106) then --106
xor_out := rand(105) xor rand(90);
elsif(rand'length = 107) then --107
xor_out := rand(106) xor rand(104) xor rand(43) xor rand(41);
elsif(rand'length = 108) then --108
xor_out := rand(107) xor rand(76);
elsif(rand'length = 109) then --109
xor_out := rand(108) xor rand(107) xor rand(102) xor rand(101);
elsif(rand'length = 110)then --110
xor_out := rand(109) xor rand(108) xor rand(97) xor rand(96);
elsif(rand'length = 111) then --111
xor_out := rand(110) xor rand(100);
elsif(rand'length = 112) then --112
xor_out := rand(111) xor rand(109) xor rand(68) xor rand(66);
elsif(rand'length = 113) then --113
xor_out := rand(112) xor rand(103);
elsif(rand'length = 114) then --114
xor_out := rand(113) xor rand(112) xor rand(32) xor rand(31);
elsif(rand'length = 115) then --115
xor_out := rand(114) xor rand(113) xor rand(100) xor rand(99);
elsif(rand'length = 116) then --116
xor_out := rand(115) xor rand(114) xor rand(45) xor rand(44);
elsif(rand'length = 117) then --117
xor_out := rand(116) xor rand(114) xor rand(98) xor rand(96);
elsif(rand'length = 118) then --118
xor_out := rand(117) xor rand(84);
elsif(rand'length = 119) then --119
xor_out := rand(118) xor rand(110);
elsif(rand'length = 120) then --120
xor_out := rand(119) xor rand(112) xor rand(8) xor rand(1);
elsif(rand'length = 121) then --121
xor_out := rand(120) xor rand(102);
elsif(rand'length = 122) then --122
xor_out := rand(121) xor rand(120) xor rand(62) xor rand(61);
elsif(rand'length = 123) then --123
xor_out := rand(122) xor rand(120);
elsif(rand'length = 124) then --124
xor_out := rand(123) xor rand(86);
elsif(rand'length = 125) then --125
xor_out := rand(124) xor rand(123) xor rand(17) xor rand(16);
elsif(rand'length = 126) then --126
xor_out := rand(125) xor rand(124) xor rand(89) xor rand(88);
elsif(rand'length = 127) then --127
xor_out := rand(126) xor rand(125);
elsif(rand'length = 128) then --128
xor_out := rand(127) xor rand(125) xor rand(100) xor rand(98);
elsif(rand'length = 129) then --129
xor_out := rand(128) xor rand(123);
elsif(rand'length = 130) then --130
xor_out := rand(129) xor rand(126);
elsif(rand'length = 131) then --131
xor_out := rand(130) xor rand(129) xor rand(83) xor rand(82);
elsif(rand'length = 132) then --132
xor_out := rand(131) xor rand(102);
elsif(rand'length = 133) then --133
xor_out := rand(132) xor rand(131) xor rand(81) xor rand(80);
elsif(rand'length = 134) then --134
xor_out := rand(133) xor rand(76);
elsif(rand'length = 135) then --135
xor_out := rand(134) xor rand(123);
elsif(rand'length = 136) then --136
xor_out := rand(135) xor rand(134) xor rand(10) xor rand(9);
elsif(rand'length = 137) then --137
xor_out := rand(136) xor rand(115);
elsif(rand'length = 138) then --138
xor_out := rand(137) xor rand(136) xor rand(130) xor rand(129);
elsif(rand'length = 139) then --139
xor_out := rand(138) xor rand(135) xor rand(133) xor rand(130);
elsif(rand'length = 140) then --140
xor_out := rand(139) xor rand(110);
elsif(rand'length = 141) then --141
xor_out := rand(140) xor rand(139) xor rand(109) xor rand(108);
elsif(rand'length = 142) then --142
xor_out := rand(141) xor rand(120);
elsif(rand'length = 143) then --143
xor_out := rand(142) xor rand(141) xor rand(122) xor rand(121);
elsif(rand'length = 144) then --144
xor_out := rand(143) xor rand(142) xor rand(74) xor rand(73);
elsif(rand'length = 145) then --145
xor_out := rand(144) xor rand(92);
elsif(rand'length = 146) then --146
xor_out := rand(145) xor rand(144) xor rand(86) xor rand(85);
elsif(rand'length = 147) then --147
xor_out := rand(146) xor rand(145) xor rand(109) xor rand(108);
elsif(rand'length = 148) then --148
xor_out := rand(147) xor rand(120);
elsif(rand'length = 149) then --149
xor_out := rand(148) xor rand(147) xor rand(39) xor rand(38);
elsif(rand'length = 150) then --150
xor_out := rand(149) xor rand(96);
elsif(rand'length = 151) then --151
xor_out := rand(150) xor rand(147);
elsif(rand'length = 152) then --152
xor_out := rand(151) xor rand(150) xor rand(86) xor rand(85);
elsif(rand'length = 153) then --153
xor_out := rand(152) xor rand(151);
elsif(rand'length = 154) then --154
xor_out := rand(153) xor rand(151) xor rand(26) xor rand(24);
elsif(rand'length = 155) then --155
xor_out := rand(154) xor rand(153) xor rand(123) xor rand(122);
elsif(rand'length = 156) then --156
xor_out := rand(155) xor rand(154) xor rand(40) xor rand(39);
elsif(rand'length = 157) then --157
xor_out := rand(156) xor rand(155) xor rand(130) xor rand(129);
elsif(rand'length = 158) then --158
xor_out := rand(157) xor rand(156) xor rand(131) xor rand(130);
elsif(rand'length = 159) then --159
xor_out := rand(158) xor rand(127);
elsif(rand'length = 160) then --160
xor_out := rand(159) xor rand(158) xor rand(141) xor rand(140);
elsif(rand'length = 161) then --161
xor_out := rand(160) xor rand(142);
elsif(rand'length = 162) then --162
xor_out := rand(161) xor rand(160) xor rand(74) xor rand(73);
elsif(rand'length = 163) then --163
xor_out := rand(162) xor rand(161) xor rand(103) xor rand(102);
elsif(rand'length = 164) then --164
xor_out := rand(163) xor rand(162) xor rand(150) xor rand(149);
elsif(rand'length = 165) then --165
xor_out := rand(164) xor rand(163) xor rand(134) xor rand(133);
elsif(rand'length = 166) then --166
xor_out := rand(165) xor rand(164) xor rand(127) xor rand(126);
elsif(rand'length = 167) then --167
xor_out := rand(166) xor rand(160);
elsif(rand'length = 168) then --168
xor_out := rand(167) xor rand(165) xor rand(152) xor rand(150);
end if;
return xor_out;
end xor_gates;
--END function for XORing using tap values.
end lfsr_pkg;
--End of the package.
|
----------------------------------------------------------------------------
---- Create Date: 14:30:08 07/28/2010 ----
---- Design Name: lfsr_pkg ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- This is the package file used in the lfsr_randgen project.The ----
---- package contain the function for XORing bits from various tap ----
---- locations depending on the generic parameter(width of lfsr ) ----
---- ----
----------------------------------------------------------------------------
---- ----
---- This file is a part of the lfsr_randgen project at ----
---- http://www.opencores.org/ ----
---- ----
---- Author(s): ----
---- Vipin Lal, [email protected] ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2010 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lfsr_pkg is
function xor_gates( random : std_logic_vector) return std_logic;
end lfsr_pkg;
--Package body starts from here.
package body lfsr_pkg is
--function for XORing from tap values.
function xor_gates( random : std_logic_vector ) return std_logic is
variable xor_out : std_logic:='0';
variable rand : std_logic_vector(random'length-1 downto 0):=random;
begin
if(rand'length = 3) then --3
xor_out := rand(2) xor rand(1);
elsif(rand'length = 2) then --2
xor_out := rand(1) xor rand(0);
elsif(rand'length = 4) then --4
xor_out := rand(3) xor rand(2);
elsif(rand'length = 5) then --5
xor_out := rand(4) xor rand(2);
elsif(rand'length = 6) then --6
xor_out := rand(5) xor rand(4);
elsif(rand'length = 7) then --7
xor_out := rand(6) xor rand(5);
elsif(rand'length = 8) then --8
xor_out := rand(7) xor rand(5) xor rand(4) xor rand(3);
elsif(rand'length = 9) then --9
xor_out := rand(8) xor rand(4);
elsif(rand'length = 10)then --10
xor_out := rand(9) xor rand(6);
elsif(rand'length =11) then --11
xor_out := rand(10) xor rand(8);
elsif(rand'length = 12) then --12
xor_out := rand(11) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 13) then --13
xor_out := rand(12) xor rand(3) xor rand(2) xor rand(0);
elsif(rand'length = 14) then --14
xor_out := rand(13) xor rand(4) xor rand(2) xor rand(0);
elsif(rand'length = 15) then --15
xor_out := rand(14) xor rand(13);
elsif(rand'length = 16) then --16
xor_out := rand(15) xor rand(14) xor rand(12) xor rand(3);
elsif(rand'length = 17) then --17
xor_out := rand(16) xor rand(13);
elsif(rand'length = 18) then --18
xor_out := rand(17) xor rand(10);
elsif(rand'length = 19) then --19
xor_out := rand(18) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 20) then --20
xor_out := rand(19) xor rand(16);
elsif(rand'length = 21) then --21
xor_out := rand(20) xor rand(18);
elsif(rand'length = 22) then --22
xor_out := rand(21) xor rand(20);
elsif(rand'length = 23) then --23
xor_out := rand(22) xor rand(17);
elsif(rand'length = 24) then --24
xor_out := rand(23) xor rand(22) xor rand(21) xor rand(16);
elsif(rand'length = 25) then --25
xor_out := rand(24) xor rand(21);
elsif(rand'length = 26) then --26
xor_out := rand(25) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 27) then --27
xor_out := rand(26) xor rand(4) xor rand(1) xor rand(0);
elsif(rand'length = 28) then --28
xor_out := rand(27) xor rand(24);
elsif(rand'length = 29) then --29
xor_out := rand(28) xor rand(26);
elsif(rand'length = 30) then --30
xor_out := rand(29) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 31) then --31
xor_out := rand(30) xor rand(27);
elsif(rand'length = 32) then --32
xor_out := rand(31) xor rand(21) xor rand(1) xor rand(0);
elsif(rand'length = 33) then --33
xor_out := rand(32) xor rand(19);
elsif(rand'length = 34) then --34
xor_out := rand(33) xor rand(26) xor rand(1) xor rand(0);
elsif(rand'length = 35) then --35
xor_out := rand(34) xor rand(32);
elsif(rand'length = 36) then --36
xor_out := rand(35) xor rand(24);
elsif(rand'length = 37) then --37
xor_out := rand(36) xor rand(4) xor rand(3) xor rand(2) xor rand(1) xor rand(0);
elsif(rand'length = 38) then --38
xor_out := rand(37) xor rand(5) xor rand(4) xor rand(0);
elsif(rand'length = 39) then --39
xor_out := rand(38) xor rand(34);
elsif(rand'length = 40) then --40
xor_out := rand(39) xor rand(37) xor rand(20) xor rand(18);
elsif(rand'length = 41) then --41
xor_out := rand(40) xor rand(37);
elsif(rand'length = 42) then --42
xor_out := rand(41) xor rand(40) xor rand(19) xor rand(18);
elsif(rand'length = 43) then --43
xor_out := rand(42) xor rand(41) xor rand(37) xor rand(36);
elsif(rand'length = 44) then --44
xor_out := rand(43) xor rand(42) xor rand(17) xor rand(16);
elsif(rand'length = 45) then --45
xor_out := rand(44) xor rand(43) xor rand(41) xor rand(40);
elsif(rand'length = 46) then --46
xor_out := rand(45) xor rand(44) xor rand(25) xor rand(24);
elsif(rand'length = 47) then --47
xor_out := rand(46) xor rand(41);
elsif(rand'length = 48) then --48
xor_out := rand(47) xor rand(46) xor rand(20) xor rand(19);
elsif(rand'length = 49) then --49
xor_out := rand(48) xor rand(39);
elsif(rand'length = 50) then --50
xor_out := rand(49) xor rand(48) xor rand(23) xor rand(22);
elsif(rand'length = 51) then --51
xor_out := rand(50) xor rand(49) xor rand(35) xor rand(34);
elsif(rand'length = 52) then --52
xor_out := rand(51) xor rand(48);
elsif(rand'length = 53) then --53
xor_out := rand(52) xor rand(51) xor rand(37) xor rand(36);
elsif(rand'length = 54) then --54
xor_out := rand(53) xor rand(52) xor rand(17) xor rand(16);
elsif(rand'length = 55) then --55
xor_out := rand(54) xor rand(30);
elsif(rand'length = 56) then --56
xor_out := rand(55) xor rand(54) xor rand(34) xor rand(33);
elsif(rand'length = 57) then --57
xor_out := rand(56) xor rand(49);
elsif(rand'length = 58) then --58
xor_out := rand(57) xor rand(38);
elsif(rand'length = 59) then --59
xor_out := rand(58) xor rand(57) xor rand(37) xor rand(36);
elsif(rand'length = 60) then --60
xor_out := rand(59) xor rand(58);
elsif(rand'length = 61) then --61
xor_out := rand(60) xor rand(59) xor rand(45) xor rand(44);
elsif(rand'length = 62) then --62
xor_out := rand(61) xor rand(60) xor rand(5) xor rand(4);
elsif(rand'length = 63) then --63
xor_out := rand(62) xor rand(61);
elsif(rand'length = 64) then --64
xor_out := rand(63) xor rand(62) xor rand(60) xor rand(59);
elsif(rand'length = 65) then --65
xor_out := rand(64) xor rand(46);
elsif(rand'length = 66) then --66
xor_out := rand(65) xor rand(64) xor rand(56) xor rand(55);
elsif(rand'length = 67) then --67
xor_out := rand(66) xor rand(65) xor rand(57) xor rand(56);
elsif(rand'length = 68) then --68
xor_out := rand(67) xor rand(58);
elsif(rand'length = 69) then --69
xor_out := rand(68) xor rand(66) xor rand(41) xor rand(39);
elsif(rand'length = 70) then --70
xor_out := rand(69) xor rand(68) xor rand(54) xor rand(53);
elsif(rand'length = 71) then --71
xor_out := rand(70) xor rand(64);
elsif(rand'length = 72) then --72
xor_out := rand(71) xor rand(65) xor rand(24) xor rand(18);
elsif(rand'length = 73) then --73
xor_out := rand(72) xor rand(47);
elsif(rand'length = 74) then --74
xor_out := rand(73) xor rand(72) xor rand(58) xor rand(57);
elsif(rand'length = 75) then --75
xor_out := rand(74) xor rand(73) xor rand(64) xor rand(63);
elsif(rand'length = 76) then --76
xor_out := rand(75) xor rand(74) xor rand(40) xor rand(39);
elsif(rand'length = 77) then --77
xor_out := rand(76) xor rand(75) xor rand(46) xor rand(45);
elsif(rand'length = 78) then --78
xor_out := rand(77) xor rand(76) xor rand(58) xor rand(57);
elsif(rand'length = 79) then --79
xor_out := rand(78) xor rand(69);
elsif(rand'length = 80) then --80
xor_out := rand(79) xor rand(78) xor rand(42) xor rand(41);
elsif(rand'length = 81) then --81
xor_out := rand(80) xor rand(76);
elsif(rand'length = 82) then --82
xor_out := rand(81) xor rand(78) xor rand(46) xor rand(43);
elsif(rand'length = 83) then --83
xor_out := rand(82) xor rand(81) xor rand(37) xor rand(36);
elsif(rand'length = 84) then --84
xor_out := rand(83) xor rand(70);
elsif(rand'length = 85) then --85
xor_out := rand(84) xor rand(83) xor rand(57) xor rand(56);
elsif(rand'length = 86) then --86
xor_out := rand(85) xor rand(84) xor rand(73) xor rand(72);
elsif(rand'length = 87) then --87
xor_out := rand(86) xor rand(73);
elsif(rand'length = 88) then --88
xor_out := rand(87) xor rand(86) xor rand(16) xor rand(15);
elsif(rand'length = 89) then --89
xor_out := rand(88) xor rand(50);
elsif(rand'length = 90) then --90
xor_out := rand(89) xor rand(88) xor rand(71) xor rand(70);
elsif(rand'length = 91) then --91
xor_out := rand(90) xor rand(89) xor rand(7) xor rand(6);
elsif(rand'length = 92) then --92
xor_out := rand(91) xor rand(90) xor rand(79) xor rand(78);
elsif(rand'length = 93) then --93
xor_out := rand(92) xor rand(90);
elsif(rand'length = 94) then --94
xor_out := rand(93) xor rand(72);
elsif(rand'length = 95) then --95
xor_out := rand(94) xor rand(83);
elsif(rand'length = 96) then --96
xor_out := rand(95) xor rand(93) xor rand(48) xor rand(46);
elsif(rand'length = 97) then --97
xor_out := rand(96) xor rand(90);
elsif(rand'length = 98) then --98
xor_out := rand(97) xor rand(86);
elsif(rand'length = 99) then --99
xor_out := rand(98) xor rand(96) xor rand(53) xor rand(51);
elsif(rand'length = 100) then --100
xor_out := rand(99) xor rand(62);
elsif(rand'length = 101) then --101
xor_out := rand(100) xor rand(99) xor rand(94) xor rand(93);
elsif(rand'length = 102) then --102
xor_out := rand(101) xor rand(100) xor rand(35) xor rand(34);
elsif(rand'length = 103) then --103
xor_out := rand(102) xor rand(93);
elsif(rand'length = 104) then --104
xor_out := rand(103) xor rand(102) xor rand(93) xor rand(92);
elsif(rand'length = 105) then --105
xor_out := rand(104) xor rand(88);
elsif(rand'length = 106) then --106
xor_out := rand(105) xor rand(90);
elsif(rand'length = 107) then --107
xor_out := rand(106) xor rand(104) xor rand(43) xor rand(41);
elsif(rand'length = 108) then --108
xor_out := rand(107) xor rand(76);
elsif(rand'length = 109) then --109
xor_out := rand(108) xor rand(107) xor rand(102) xor rand(101);
elsif(rand'length = 110)then --110
xor_out := rand(109) xor rand(108) xor rand(97) xor rand(96);
elsif(rand'length = 111) then --111
xor_out := rand(110) xor rand(100);
elsif(rand'length = 112) then --112
xor_out := rand(111) xor rand(109) xor rand(68) xor rand(66);
elsif(rand'length = 113) then --113
xor_out := rand(112) xor rand(103);
elsif(rand'length = 114) then --114
xor_out := rand(113) xor rand(112) xor rand(32) xor rand(31);
elsif(rand'length = 115) then --115
xor_out := rand(114) xor rand(113) xor rand(100) xor rand(99);
elsif(rand'length = 116) then --116
xor_out := rand(115) xor rand(114) xor rand(45) xor rand(44);
elsif(rand'length = 117) then --117
xor_out := rand(116) xor rand(114) xor rand(98) xor rand(96);
elsif(rand'length = 118) then --118
xor_out := rand(117) xor rand(84);
elsif(rand'length = 119) then --119
xor_out := rand(118) xor rand(110);
elsif(rand'length = 120) then --120
xor_out := rand(119) xor rand(112) xor rand(8) xor rand(1);
elsif(rand'length = 121) then --121
xor_out := rand(120) xor rand(102);
elsif(rand'length = 122) then --122
xor_out := rand(121) xor rand(120) xor rand(62) xor rand(61);
elsif(rand'length = 123) then --123
xor_out := rand(122) xor rand(120);
elsif(rand'length = 124) then --124
xor_out := rand(123) xor rand(86);
elsif(rand'length = 125) then --125
xor_out := rand(124) xor rand(123) xor rand(17) xor rand(16);
elsif(rand'length = 126) then --126
xor_out := rand(125) xor rand(124) xor rand(89) xor rand(88);
elsif(rand'length = 127) then --127
xor_out := rand(126) xor rand(125);
elsif(rand'length = 128) then --128
xor_out := rand(127) xor rand(125) xor rand(100) xor rand(98);
elsif(rand'length = 129) then --129
xor_out := rand(128) xor rand(123);
elsif(rand'length = 130) then --130
xor_out := rand(129) xor rand(126);
elsif(rand'length = 131) then --131
xor_out := rand(130) xor rand(129) xor rand(83) xor rand(82);
elsif(rand'length = 132) then --132
xor_out := rand(131) xor rand(102);
elsif(rand'length = 133) then --133
xor_out := rand(132) xor rand(131) xor rand(81) xor rand(80);
elsif(rand'length = 134) then --134
xor_out := rand(133) xor rand(76);
elsif(rand'length = 135) then --135
xor_out := rand(134) xor rand(123);
elsif(rand'length = 136) then --136
xor_out := rand(135) xor rand(134) xor rand(10) xor rand(9);
elsif(rand'length = 137) then --137
xor_out := rand(136) xor rand(115);
elsif(rand'length = 138) then --138
xor_out := rand(137) xor rand(136) xor rand(130) xor rand(129);
elsif(rand'length = 139) then --139
xor_out := rand(138) xor rand(135) xor rand(133) xor rand(130);
elsif(rand'length = 140) then --140
xor_out := rand(139) xor rand(110);
elsif(rand'length = 141) then --141
xor_out := rand(140) xor rand(139) xor rand(109) xor rand(108);
elsif(rand'length = 142) then --142
xor_out := rand(141) xor rand(120);
elsif(rand'length = 143) then --143
xor_out := rand(142) xor rand(141) xor rand(122) xor rand(121);
elsif(rand'length = 144) then --144
xor_out := rand(143) xor rand(142) xor rand(74) xor rand(73);
elsif(rand'length = 145) then --145
xor_out := rand(144) xor rand(92);
elsif(rand'length = 146) then --146
xor_out := rand(145) xor rand(144) xor rand(86) xor rand(85);
elsif(rand'length = 147) then --147
xor_out := rand(146) xor rand(145) xor rand(109) xor rand(108);
elsif(rand'length = 148) then --148
xor_out := rand(147) xor rand(120);
elsif(rand'length = 149) then --149
xor_out := rand(148) xor rand(147) xor rand(39) xor rand(38);
elsif(rand'length = 150) then --150
xor_out := rand(149) xor rand(96);
elsif(rand'length = 151) then --151
xor_out := rand(150) xor rand(147);
elsif(rand'length = 152) then --152
xor_out := rand(151) xor rand(150) xor rand(86) xor rand(85);
elsif(rand'length = 153) then --153
xor_out := rand(152) xor rand(151);
elsif(rand'length = 154) then --154
xor_out := rand(153) xor rand(151) xor rand(26) xor rand(24);
elsif(rand'length = 155) then --155
xor_out := rand(154) xor rand(153) xor rand(123) xor rand(122);
elsif(rand'length = 156) then --156
xor_out := rand(155) xor rand(154) xor rand(40) xor rand(39);
elsif(rand'length = 157) then --157
xor_out := rand(156) xor rand(155) xor rand(130) xor rand(129);
elsif(rand'length = 158) then --158
xor_out := rand(157) xor rand(156) xor rand(131) xor rand(130);
elsif(rand'length = 159) then --159
xor_out := rand(158) xor rand(127);
elsif(rand'length = 160) then --160
xor_out := rand(159) xor rand(158) xor rand(141) xor rand(140);
elsif(rand'length = 161) then --161
xor_out := rand(160) xor rand(142);
elsif(rand'length = 162) then --162
xor_out := rand(161) xor rand(160) xor rand(74) xor rand(73);
elsif(rand'length = 163) then --163
xor_out := rand(162) xor rand(161) xor rand(103) xor rand(102);
elsif(rand'length = 164) then --164
xor_out := rand(163) xor rand(162) xor rand(150) xor rand(149);
elsif(rand'length = 165) then --165
xor_out := rand(164) xor rand(163) xor rand(134) xor rand(133);
elsif(rand'length = 166) then --166
xor_out := rand(165) xor rand(164) xor rand(127) xor rand(126);
elsif(rand'length = 167) then --167
xor_out := rand(166) xor rand(160);
elsif(rand'length = 168) then --168
xor_out := rand(167) xor rand(165) xor rand(152) xor rand(150);
end if;
return xor_out;
end xor_gates;
--END function for XORing using tap values.
end lfsr_pkg;
--End of the package.
|
----------------------------------------------------------------------------
---- Create Date: 14:30:08 07/28/2010 ----
---- Design Name: lfsr_pkg ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- This is the package file used in the lfsr_randgen project.The ----
---- package contain the function for XORing bits from various tap ----
---- locations depending on the generic parameter(width of lfsr ) ----
---- ----
----------------------------------------------------------------------------
---- ----
---- This file is a part of the lfsr_randgen project at ----
---- http://www.opencores.org/ ----
---- ----
---- Author(s): ----
---- Vipin Lal, [email protected] ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2010 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lfsr_pkg is
function xor_gates( random : std_logic_vector) return std_logic;
end lfsr_pkg;
--Package body starts from here.
package body lfsr_pkg is
--function for XORing from tap values.
function xor_gates( random : std_logic_vector ) return std_logic is
variable xor_out : std_logic:='0';
variable rand : std_logic_vector(random'length-1 downto 0):=random;
begin
if(rand'length = 3) then --3
xor_out := rand(2) xor rand(1);
elsif(rand'length = 2) then --2
xor_out := rand(1) xor rand(0);
elsif(rand'length = 4) then --4
xor_out := rand(3) xor rand(2);
elsif(rand'length = 5) then --5
xor_out := rand(4) xor rand(2);
elsif(rand'length = 6) then --6
xor_out := rand(5) xor rand(4);
elsif(rand'length = 7) then --7
xor_out := rand(6) xor rand(5);
elsif(rand'length = 8) then --8
xor_out := rand(7) xor rand(5) xor rand(4) xor rand(3);
elsif(rand'length = 9) then --9
xor_out := rand(8) xor rand(4);
elsif(rand'length = 10)then --10
xor_out := rand(9) xor rand(6);
elsif(rand'length =11) then --11
xor_out := rand(10) xor rand(8);
elsif(rand'length = 12) then --12
xor_out := rand(11) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 13) then --13
xor_out := rand(12) xor rand(3) xor rand(2) xor rand(0);
elsif(rand'length = 14) then --14
xor_out := rand(13) xor rand(4) xor rand(2) xor rand(0);
elsif(rand'length = 15) then --15
xor_out := rand(14) xor rand(13);
elsif(rand'length = 16) then --16
xor_out := rand(15) xor rand(14) xor rand(12) xor rand(3);
elsif(rand'length = 17) then --17
xor_out := rand(16) xor rand(13);
elsif(rand'length = 18) then --18
xor_out := rand(17) xor rand(10);
elsif(rand'length = 19) then --19
xor_out := rand(18) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 20) then --20
xor_out := rand(19) xor rand(16);
elsif(rand'length = 21) then --21
xor_out := rand(20) xor rand(18);
elsif(rand'length = 22) then --22
xor_out := rand(21) xor rand(20);
elsif(rand'length = 23) then --23
xor_out := rand(22) xor rand(17);
elsif(rand'length = 24) then --24
xor_out := rand(23) xor rand(22) xor rand(21) xor rand(16);
elsif(rand'length = 25) then --25
xor_out := rand(24) xor rand(21);
elsif(rand'length = 26) then --26
xor_out := rand(25) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 27) then --27
xor_out := rand(26) xor rand(4) xor rand(1) xor rand(0);
elsif(rand'length = 28) then --28
xor_out := rand(27) xor rand(24);
elsif(rand'length = 29) then --29
xor_out := rand(28) xor rand(26);
elsif(rand'length = 30) then --30
xor_out := rand(29) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 31) then --31
xor_out := rand(30) xor rand(27);
elsif(rand'length = 32) then --32
xor_out := rand(31) xor rand(21) xor rand(1) xor rand(0);
elsif(rand'length = 33) then --33
xor_out := rand(32) xor rand(19);
elsif(rand'length = 34) then --34
xor_out := rand(33) xor rand(26) xor rand(1) xor rand(0);
elsif(rand'length = 35) then --35
xor_out := rand(34) xor rand(32);
elsif(rand'length = 36) then --36
xor_out := rand(35) xor rand(24);
elsif(rand'length = 37) then --37
xor_out := rand(36) xor rand(4) xor rand(3) xor rand(2) xor rand(1) xor rand(0);
elsif(rand'length = 38) then --38
xor_out := rand(37) xor rand(5) xor rand(4) xor rand(0);
elsif(rand'length = 39) then --39
xor_out := rand(38) xor rand(34);
elsif(rand'length = 40) then --40
xor_out := rand(39) xor rand(37) xor rand(20) xor rand(18);
elsif(rand'length = 41) then --41
xor_out := rand(40) xor rand(37);
elsif(rand'length = 42) then --42
xor_out := rand(41) xor rand(40) xor rand(19) xor rand(18);
elsif(rand'length = 43) then --43
xor_out := rand(42) xor rand(41) xor rand(37) xor rand(36);
elsif(rand'length = 44) then --44
xor_out := rand(43) xor rand(42) xor rand(17) xor rand(16);
elsif(rand'length = 45) then --45
xor_out := rand(44) xor rand(43) xor rand(41) xor rand(40);
elsif(rand'length = 46) then --46
xor_out := rand(45) xor rand(44) xor rand(25) xor rand(24);
elsif(rand'length = 47) then --47
xor_out := rand(46) xor rand(41);
elsif(rand'length = 48) then --48
xor_out := rand(47) xor rand(46) xor rand(20) xor rand(19);
elsif(rand'length = 49) then --49
xor_out := rand(48) xor rand(39);
elsif(rand'length = 50) then --50
xor_out := rand(49) xor rand(48) xor rand(23) xor rand(22);
elsif(rand'length = 51) then --51
xor_out := rand(50) xor rand(49) xor rand(35) xor rand(34);
elsif(rand'length = 52) then --52
xor_out := rand(51) xor rand(48);
elsif(rand'length = 53) then --53
xor_out := rand(52) xor rand(51) xor rand(37) xor rand(36);
elsif(rand'length = 54) then --54
xor_out := rand(53) xor rand(52) xor rand(17) xor rand(16);
elsif(rand'length = 55) then --55
xor_out := rand(54) xor rand(30);
elsif(rand'length = 56) then --56
xor_out := rand(55) xor rand(54) xor rand(34) xor rand(33);
elsif(rand'length = 57) then --57
xor_out := rand(56) xor rand(49);
elsif(rand'length = 58) then --58
xor_out := rand(57) xor rand(38);
elsif(rand'length = 59) then --59
xor_out := rand(58) xor rand(57) xor rand(37) xor rand(36);
elsif(rand'length = 60) then --60
xor_out := rand(59) xor rand(58);
elsif(rand'length = 61) then --61
xor_out := rand(60) xor rand(59) xor rand(45) xor rand(44);
elsif(rand'length = 62) then --62
xor_out := rand(61) xor rand(60) xor rand(5) xor rand(4);
elsif(rand'length = 63) then --63
xor_out := rand(62) xor rand(61);
elsif(rand'length = 64) then --64
xor_out := rand(63) xor rand(62) xor rand(60) xor rand(59);
elsif(rand'length = 65) then --65
xor_out := rand(64) xor rand(46);
elsif(rand'length = 66) then --66
xor_out := rand(65) xor rand(64) xor rand(56) xor rand(55);
elsif(rand'length = 67) then --67
xor_out := rand(66) xor rand(65) xor rand(57) xor rand(56);
elsif(rand'length = 68) then --68
xor_out := rand(67) xor rand(58);
elsif(rand'length = 69) then --69
xor_out := rand(68) xor rand(66) xor rand(41) xor rand(39);
elsif(rand'length = 70) then --70
xor_out := rand(69) xor rand(68) xor rand(54) xor rand(53);
elsif(rand'length = 71) then --71
xor_out := rand(70) xor rand(64);
elsif(rand'length = 72) then --72
xor_out := rand(71) xor rand(65) xor rand(24) xor rand(18);
elsif(rand'length = 73) then --73
xor_out := rand(72) xor rand(47);
elsif(rand'length = 74) then --74
xor_out := rand(73) xor rand(72) xor rand(58) xor rand(57);
elsif(rand'length = 75) then --75
xor_out := rand(74) xor rand(73) xor rand(64) xor rand(63);
elsif(rand'length = 76) then --76
xor_out := rand(75) xor rand(74) xor rand(40) xor rand(39);
elsif(rand'length = 77) then --77
xor_out := rand(76) xor rand(75) xor rand(46) xor rand(45);
elsif(rand'length = 78) then --78
xor_out := rand(77) xor rand(76) xor rand(58) xor rand(57);
elsif(rand'length = 79) then --79
xor_out := rand(78) xor rand(69);
elsif(rand'length = 80) then --80
xor_out := rand(79) xor rand(78) xor rand(42) xor rand(41);
elsif(rand'length = 81) then --81
xor_out := rand(80) xor rand(76);
elsif(rand'length = 82) then --82
xor_out := rand(81) xor rand(78) xor rand(46) xor rand(43);
elsif(rand'length = 83) then --83
xor_out := rand(82) xor rand(81) xor rand(37) xor rand(36);
elsif(rand'length = 84) then --84
xor_out := rand(83) xor rand(70);
elsif(rand'length = 85) then --85
xor_out := rand(84) xor rand(83) xor rand(57) xor rand(56);
elsif(rand'length = 86) then --86
xor_out := rand(85) xor rand(84) xor rand(73) xor rand(72);
elsif(rand'length = 87) then --87
xor_out := rand(86) xor rand(73);
elsif(rand'length = 88) then --88
xor_out := rand(87) xor rand(86) xor rand(16) xor rand(15);
elsif(rand'length = 89) then --89
xor_out := rand(88) xor rand(50);
elsif(rand'length = 90) then --90
xor_out := rand(89) xor rand(88) xor rand(71) xor rand(70);
elsif(rand'length = 91) then --91
xor_out := rand(90) xor rand(89) xor rand(7) xor rand(6);
elsif(rand'length = 92) then --92
xor_out := rand(91) xor rand(90) xor rand(79) xor rand(78);
elsif(rand'length = 93) then --93
xor_out := rand(92) xor rand(90);
elsif(rand'length = 94) then --94
xor_out := rand(93) xor rand(72);
elsif(rand'length = 95) then --95
xor_out := rand(94) xor rand(83);
elsif(rand'length = 96) then --96
xor_out := rand(95) xor rand(93) xor rand(48) xor rand(46);
elsif(rand'length = 97) then --97
xor_out := rand(96) xor rand(90);
elsif(rand'length = 98) then --98
xor_out := rand(97) xor rand(86);
elsif(rand'length = 99) then --99
xor_out := rand(98) xor rand(96) xor rand(53) xor rand(51);
elsif(rand'length = 100) then --100
xor_out := rand(99) xor rand(62);
elsif(rand'length = 101) then --101
xor_out := rand(100) xor rand(99) xor rand(94) xor rand(93);
elsif(rand'length = 102) then --102
xor_out := rand(101) xor rand(100) xor rand(35) xor rand(34);
elsif(rand'length = 103) then --103
xor_out := rand(102) xor rand(93);
elsif(rand'length = 104) then --104
xor_out := rand(103) xor rand(102) xor rand(93) xor rand(92);
elsif(rand'length = 105) then --105
xor_out := rand(104) xor rand(88);
elsif(rand'length = 106) then --106
xor_out := rand(105) xor rand(90);
elsif(rand'length = 107) then --107
xor_out := rand(106) xor rand(104) xor rand(43) xor rand(41);
elsif(rand'length = 108) then --108
xor_out := rand(107) xor rand(76);
elsif(rand'length = 109) then --109
xor_out := rand(108) xor rand(107) xor rand(102) xor rand(101);
elsif(rand'length = 110)then --110
xor_out := rand(109) xor rand(108) xor rand(97) xor rand(96);
elsif(rand'length = 111) then --111
xor_out := rand(110) xor rand(100);
elsif(rand'length = 112) then --112
xor_out := rand(111) xor rand(109) xor rand(68) xor rand(66);
elsif(rand'length = 113) then --113
xor_out := rand(112) xor rand(103);
elsif(rand'length = 114) then --114
xor_out := rand(113) xor rand(112) xor rand(32) xor rand(31);
elsif(rand'length = 115) then --115
xor_out := rand(114) xor rand(113) xor rand(100) xor rand(99);
elsif(rand'length = 116) then --116
xor_out := rand(115) xor rand(114) xor rand(45) xor rand(44);
elsif(rand'length = 117) then --117
xor_out := rand(116) xor rand(114) xor rand(98) xor rand(96);
elsif(rand'length = 118) then --118
xor_out := rand(117) xor rand(84);
elsif(rand'length = 119) then --119
xor_out := rand(118) xor rand(110);
elsif(rand'length = 120) then --120
xor_out := rand(119) xor rand(112) xor rand(8) xor rand(1);
elsif(rand'length = 121) then --121
xor_out := rand(120) xor rand(102);
elsif(rand'length = 122) then --122
xor_out := rand(121) xor rand(120) xor rand(62) xor rand(61);
elsif(rand'length = 123) then --123
xor_out := rand(122) xor rand(120);
elsif(rand'length = 124) then --124
xor_out := rand(123) xor rand(86);
elsif(rand'length = 125) then --125
xor_out := rand(124) xor rand(123) xor rand(17) xor rand(16);
elsif(rand'length = 126) then --126
xor_out := rand(125) xor rand(124) xor rand(89) xor rand(88);
elsif(rand'length = 127) then --127
xor_out := rand(126) xor rand(125);
elsif(rand'length = 128) then --128
xor_out := rand(127) xor rand(125) xor rand(100) xor rand(98);
elsif(rand'length = 129) then --129
xor_out := rand(128) xor rand(123);
elsif(rand'length = 130) then --130
xor_out := rand(129) xor rand(126);
elsif(rand'length = 131) then --131
xor_out := rand(130) xor rand(129) xor rand(83) xor rand(82);
elsif(rand'length = 132) then --132
xor_out := rand(131) xor rand(102);
elsif(rand'length = 133) then --133
xor_out := rand(132) xor rand(131) xor rand(81) xor rand(80);
elsif(rand'length = 134) then --134
xor_out := rand(133) xor rand(76);
elsif(rand'length = 135) then --135
xor_out := rand(134) xor rand(123);
elsif(rand'length = 136) then --136
xor_out := rand(135) xor rand(134) xor rand(10) xor rand(9);
elsif(rand'length = 137) then --137
xor_out := rand(136) xor rand(115);
elsif(rand'length = 138) then --138
xor_out := rand(137) xor rand(136) xor rand(130) xor rand(129);
elsif(rand'length = 139) then --139
xor_out := rand(138) xor rand(135) xor rand(133) xor rand(130);
elsif(rand'length = 140) then --140
xor_out := rand(139) xor rand(110);
elsif(rand'length = 141) then --141
xor_out := rand(140) xor rand(139) xor rand(109) xor rand(108);
elsif(rand'length = 142) then --142
xor_out := rand(141) xor rand(120);
elsif(rand'length = 143) then --143
xor_out := rand(142) xor rand(141) xor rand(122) xor rand(121);
elsif(rand'length = 144) then --144
xor_out := rand(143) xor rand(142) xor rand(74) xor rand(73);
elsif(rand'length = 145) then --145
xor_out := rand(144) xor rand(92);
elsif(rand'length = 146) then --146
xor_out := rand(145) xor rand(144) xor rand(86) xor rand(85);
elsif(rand'length = 147) then --147
xor_out := rand(146) xor rand(145) xor rand(109) xor rand(108);
elsif(rand'length = 148) then --148
xor_out := rand(147) xor rand(120);
elsif(rand'length = 149) then --149
xor_out := rand(148) xor rand(147) xor rand(39) xor rand(38);
elsif(rand'length = 150) then --150
xor_out := rand(149) xor rand(96);
elsif(rand'length = 151) then --151
xor_out := rand(150) xor rand(147);
elsif(rand'length = 152) then --152
xor_out := rand(151) xor rand(150) xor rand(86) xor rand(85);
elsif(rand'length = 153) then --153
xor_out := rand(152) xor rand(151);
elsif(rand'length = 154) then --154
xor_out := rand(153) xor rand(151) xor rand(26) xor rand(24);
elsif(rand'length = 155) then --155
xor_out := rand(154) xor rand(153) xor rand(123) xor rand(122);
elsif(rand'length = 156) then --156
xor_out := rand(155) xor rand(154) xor rand(40) xor rand(39);
elsif(rand'length = 157) then --157
xor_out := rand(156) xor rand(155) xor rand(130) xor rand(129);
elsif(rand'length = 158) then --158
xor_out := rand(157) xor rand(156) xor rand(131) xor rand(130);
elsif(rand'length = 159) then --159
xor_out := rand(158) xor rand(127);
elsif(rand'length = 160) then --160
xor_out := rand(159) xor rand(158) xor rand(141) xor rand(140);
elsif(rand'length = 161) then --161
xor_out := rand(160) xor rand(142);
elsif(rand'length = 162) then --162
xor_out := rand(161) xor rand(160) xor rand(74) xor rand(73);
elsif(rand'length = 163) then --163
xor_out := rand(162) xor rand(161) xor rand(103) xor rand(102);
elsif(rand'length = 164) then --164
xor_out := rand(163) xor rand(162) xor rand(150) xor rand(149);
elsif(rand'length = 165) then --165
xor_out := rand(164) xor rand(163) xor rand(134) xor rand(133);
elsif(rand'length = 166) then --166
xor_out := rand(165) xor rand(164) xor rand(127) xor rand(126);
elsif(rand'length = 167) then --167
xor_out := rand(166) xor rand(160);
elsif(rand'length = 168) then --168
xor_out := rand(167) xor rand(165) xor rand(152) xor rand(150);
end if;
return xor_out;
end xor_gates;
--END function for XORing using tap values.
end lfsr_pkg;
--End of the package.
|
----------------------------------------------------------------------------
---- Create Date: 14:30:08 07/28/2010 ----
---- Design Name: lfsr_pkg ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- This is the package file used in the lfsr_randgen project.The ----
---- package contain the function for XORing bits from various tap ----
---- locations depending on the generic parameter(width of lfsr ) ----
---- ----
----------------------------------------------------------------------------
---- ----
---- This file is a part of the lfsr_randgen project at ----
---- http://www.opencores.org/ ----
---- ----
---- Author(s): ----
---- Vipin Lal, [email protected] ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2010 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lfsr_pkg is
function xor_gates( random : std_logic_vector) return std_logic;
end lfsr_pkg;
--Package body starts from here.
package body lfsr_pkg is
--function for XORing from tap values.
function xor_gates( random : std_logic_vector ) return std_logic is
variable xor_out : std_logic:='0';
variable rand : std_logic_vector(random'length-1 downto 0):=random;
begin
if(rand'length = 3) then --3
xor_out := rand(2) xor rand(1);
elsif(rand'length = 2) then --2
xor_out := rand(1) xor rand(0);
elsif(rand'length = 4) then --4
xor_out := rand(3) xor rand(2);
elsif(rand'length = 5) then --5
xor_out := rand(4) xor rand(2);
elsif(rand'length = 6) then --6
xor_out := rand(5) xor rand(4);
elsif(rand'length = 7) then --7
xor_out := rand(6) xor rand(5);
elsif(rand'length = 8) then --8
xor_out := rand(7) xor rand(5) xor rand(4) xor rand(3);
elsif(rand'length = 9) then --9
xor_out := rand(8) xor rand(4);
elsif(rand'length = 10)then --10
xor_out := rand(9) xor rand(6);
elsif(rand'length =11) then --11
xor_out := rand(10) xor rand(8);
elsif(rand'length = 12) then --12
xor_out := rand(11) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 13) then --13
xor_out := rand(12) xor rand(3) xor rand(2) xor rand(0);
elsif(rand'length = 14) then --14
xor_out := rand(13) xor rand(4) xor rand(2) xor rand(0);
elsif(rand'length = 15) then --15
xor_out := rand(14) xor rand(13);
elsif(rand'length = 16) then --16
xor_out := rand(15) xor rand(14) xor rand(12) xor rand(3);
elsif(rand'length = 17) then --17
xor_out := rand(16) xor rand(13);
elsif(rand'length = 18) then --18
xor_out := rand(17) xor rand(10);
elsif(rand'length = 19) then --19
xor_out := rand(18) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 20) then --20
xor_out := rand(19) xor rand(16);
elsif(rand'length = 21) then --21
xor_out := rand(20) xor rand(18);
elsif(rand'length = 22) then --22
xor_out := rand(21) xor rand(20);
elsif(rand'length = 23) then --23
xor_out := rand(22) xor rand(17);
elsif(rand'length = 24) then --24
xor_out := rand(23) xor rand(22) xor rand(21) xor rand(16);
elsif(rand'length = 25) then --25
xor_out := rand(24) xor rand(21);
elsif(rand'length = 26) then --26
xor_out := rand(25) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 27) then --27
xor_out := rand(26) xor rand(4) xor rand(1) xor rand(0);
elsif(rand'length = 28) then --28
xor_out := rand(27) xor rand(24);
elsif(rand'length = 29) then --29
xor_out := rand(28) xor rand(26);
elsif(rand'length = 30) then --30
xor_out := rand(29) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 31) then --31
xor_out := rand(30) xor rand(27);
elsif(rand'length = 32) then --32
xor_out := rand(31) xor rand(21) xor rand(1) xor rand(0);
elsif(rand'length = 33) then --33
xor_out := rand(32) xor rand(19);
elsif(rand'length = 34) then --34
xor_out := rand(33) xor rand(26) xor rand(1) xor rand(0);
elsif(rand'length = 35) then --35
xor_out := rand(34) xor rand(32);
elsif(rand'length = 36) then --36
xor_out := rand(35) xor rand(24);
elsif(rand'length = 37) then --37
xor_out := rand(36) xor rand(4) xor rand(3) xor rand(2) xor rand(1) xor rand(0);
elsif(rand'length = 38) then --38
xor_out := rand(37) xor rand(5) xor rand(4) xor rand(0);
elsif(rand'length = 39) then --39
xor_out := rand(38) xor rand(34);
elsif(rand'length = 40) then --40
xor_out := rand(39) xor rand(37) xor rand(20) xor rand(18);
elsif(rand'length = 41) then --41
xor_out := rand(40) xor rand(37);
elsif(rand'length = 42) then --42
xor_out := rand(41) xor rand(40) xor rand(19) xor rand(18);
elsif(rand'length = 43) then --43
xor_out := rand(42) xor rand(41) xor rand(37) xor rand(36);
elsif(rand'length = 44) then --44
xor_out := rand(43) xor rand(42) xor rand(17) xor rand(16);
elsif(rand'length = 45) then --45
xor_out := rand(44) xor rand(43) xor rand(41) xor rand(40);
elsif(rand'length = 46) then --46
xor_out := rand(45) xor rand(44) xor rand(25) xor rand(24);
elsif(rand'length = 47) then --47
xor_out := rand(46) xor rand(41);
elsif(rand'length = 48) then --48
xor_out := rand(47) xor rand(46) xor rand(20) xor rand(19);
elsif(rand'length = 49) then --49
xor_out := rand(48) xor rand(39);
elsif(rand'length = 50) then --50
xor_out := rand(49) xor rand(48) xor rand(23) xor rand(22);
elsif(rand'length = 51) then --51
xor_out := rand(50) xor rand(49) xor rand(35) xor rand(34);
elsif(rand'length = 52) then --52
xor_out := rand(51) xor rand(48);
elsif(rand'length = 53) then --53
xor_out := rand(52) xor rand(51) xor rand(37) xor rand(36);
elsif(rand'length = 54) then --54
xor_out := rand(53) xor rand(52) xor rand(17) xor rand(16);
elsif(rand'length = 55) then --55
xor_out := rand(54) xor rand(30);
elsif(rand'length = 56) then --56
xor_out := rand(55) xor rand(54) xor rand(34) xor rand(33);
elsif(rand'length = 57) then --57
xor_out := rand(56) xor rand(49);
elsif(rand'length = 58) then --58
xor_out := rand(57) xor rand(38);
elsif(rand'length = 59) then --59
xor_out := rand(58) xor rand(57) xor rand(37) xor rand(36);
elsif(rand'length = 60) then --60
xor_out := rand(59) xor rand(58);
elsif(rand'length = 61) then --61
xor_out := rand(60) xor rand(59) xor rand(45) xor rand(44);
elsif(rand'length = 62) then --62
xor_out := rand(61) xor rand(60) xor rand(5) xor rand(4);
elsif(rand'length = 63) then --63
xor_out := rand(62) xor rand(61);
elsif(rand'length = 64) then --64
xor_out := rand(63) xor rand(62) xor rand(60) xor rand(59);
elsif(rand'length = 65) then --65
xor_out := rand(64) xor rand(46);
elsif(rand'length = 66) then --66
xor_out := rand(65) xor rand(64) xor rand(56) xor rand(55);
elsif(rand'length = 67) then --67
xor_out := rand(66) xor rand(65) xor rand(57) xor rand(56);
elsif(rand'length = 68) then --68
xor_out := rand(67) xor rand(58);
elsif(rand'length = 69) then --69
xor_out := rand(68) xor rand(66) xor rand(41) xor rand(39);
elsif(rand'length = 70) then --70
xor_out := rand(69) xor rand(68) xor rand(54) xor rand(53);
elsif(rand'length = 71) then --71
xor_out := rand(70) xor rand(64);
elsif(rand'length = 72) then --72
xor_out := rand(71) xor rand(65) xor rand(24) xor rand(18);
elsif(rand'length = 73) then --73
xor_out := rand(72) xor rand(47);
elsif(rand'length = 74) then --74
xor_out := rand(73) xor rand(72) xor rand(58) xor rand(57);
elsif(rand'length = 75) then --75
xor_out := rand(74) xor rand(73) xor rand(64) xor rand(63);
elsif(rand'length = 76) then --76
xor_out := rand(75) xor rand(74) xor rand(40) xor rand(39);
elsif(rand'length = 77) then --77
xor_out := rand(76) xor rand(75) xor rand(46) xor rand(45);
elsif(rand'length = 78) then --78
xor_out := rand(77) xor rand(76) xor rand(58) xor rand(57);
elsif(rand'length = 79) then --79
xor_out := rand(78) xor rand(69);
elsif(rand'length = 80) then --80
xor_out := rand(79) xor rand(78) xor rand(42) xor rand(41);
elsif(rand'length = 81) then --81
xor_out := rand(80) xor rand(76);
elsif(rand'length = 82) then --82
xor_out := rand(81) xor rand(78) xor rand(46) xor rand(43);
elsif(rand'length = 83) then --83
xor_out := rand(82) xor rand(81) xor rand(37) xor rand(36);
elsif(rand'length = 84) then --84
xor_out := rand(83) xor rand(70);
elsif(rand'length = 85) then --85
xor_out := rand(84) xor rand(83) xor rand(57) xor rand(56);
elsif(rand'length = 86) then --86
xor_out := rand(85) xor rand(84) xor rand(73) xor rand(72);
elsif(rand'length = 87) then --87
xor_out := rand(86) xor rand(73);
elsif(rand'length = 88) then --88
xor_out := rand(87) xor rand(86) xor rand(16) xor rand(15);
elsif(rand'length = 89) then --89
xor_out := rand(88) xor rand(50);
elsif(rand'length = 90) then --90
xor_out := rand(89) xor rand(88) xor rand(71) xor rand(70);
elsif(rand'length = 91) then --91
xor_out := rand(90) xor rand(89) xor rand(7) xor rand(6);
elsif(rand'length = 92) then --92
xor_out := rand(91) xor rand(90) xor rand(79) xor rand(78);
elsif(rand'length = 93) then --93
xor_out := rand(92) xor rand(90);
elsif(rand'length = 94) then --94
xor_out := rand(93) xor rand(72);
elsif(rand'length = 95) then --95
xor_out := rand(94) xor rand(83);
elsif(rand'length = 96) then --96
xor_out := rand(95) xor rand(93) xor rand(48) xor rand(46);
elsif(rand'length = 97) then --97
xor_out := rand(96) xor rand(90);
elsif(rand'length = 98) then --98
xor_out := rand(97) xor rand(86);
elsif(rand'length = 99) then --99
xor_out := rand(98) xor rand(96) xor rand(53) xor rand(51);
elsif(rand'length = 100) then --100
xor_out := rand(99) xor rand(62);
elsif(rand'length = 101) then --101
xor_out := rand(100) xor rand(99) xor rand(94) xor rand(93);
elsif(rand'length = 102) then --102
xor_out := rand(101) xor rand(100) xor rand(35) xor rand(34);
elsif(rand'length = 103) then --103
xor_out := rand(102) xor rand(93);
elsif(rand'length = 104) then --104
xor_out := rand(103) xor rand(102) xor rand(93) xor rand(92);
elsif(rand'length = 105) then --105
xor_out := rand(104) xor rand(88);
elsif(rand'length = 106) then --106
xor_out := rand(105) xor rand(90);
elsif(rand'length = 107) then --107
xor_out := rand(106) xor rand(104) xor rand(43) xor rand(41);
elsif(rand'length = 108) then --108
xor_out := rand(107) xor rand(76);
elsif(rand'length = 109) then --109
xor_out := rand(108) xor rand(107) xor rand(102) xor rand(101);
elsif(rand'length = 110)then --110
xor_out := rand(109) xor rand(108) xor rand(97) xor rand(96);
elsif(rand'length = 111) then --111
xor_out := rand(110) xor rand(100);
elsif(rand'length = 112) then --112
xor_out := rand(111) xor rand(109) xor rand(68) xor rand(66);
elsif(rand'length = 113) then --113
xor_out := rand(112) xor rand(103);
elsif(rand'length = 114) then --114
xor_out := rand(113) xor rand(112) xor rand(32) xor rand(31);
elsif(rand'length = 115) then --115
xor_out := rand(114) xor rand(113) xor rand(100) xor rand(99);
elsif(rand'length = 116) then --116
xor_out := rand(115) xor rand(114) xor rand(45) xor rand(44);
elsif(rand'length = 117) then --117
xor_out := rand(116) xor rand(114) xor rand(98) xor rand(96);
elsif(rand'length = 118) then --118
xor_out := rand(117) xor rand(84);
elsif(rand'length = 119) then --119
xor_out := rand(118) xor rand(110);
elsif(rand'length = 120) then --120
xor_out := rand(119) xor rand(112) xor rand(8) xor rand(1);
elsif(rand'length = 121) then --121
xor_out := rand(120) xor rand(102);
elsif(rand'length = 122) then --122
xor_out := rand(121) xor rand(120) xor rand(62) xor rand(61);
elsif(rand'length = 123) then --123
xor_out := rand(122) xor rand(120);
elsif(rand'length = 124) then --124
xor_out := rand(123) xor rand(86);
elsif(rand'length = 125) then --125
xor_out := rand(124) xor rand(123) xor rand(17) xor rand(16);
elsif(rand'length = 126) then --126
xor_out := rand(125) xor rand(124) xor rand(89) xor rand(88);
elsif(rand'length = 127) then --127
xor_out := rand(126) xor rand(125);
elsif(rand'length = 128) then --128
xor_out := rand(127) xor rand(125) xor rand(100) xor rand(98);
elsif(rand'length = 129) then --129
xor_out := rand(128) xor rand(123);
elsif(rand'length = 130) then --130
xor_out := rand(129) xor rand(126);
elsif(rand'length = 131) then --131
xor_out := rand(130) xor rand(129) xor rand(83) xor rand(82);
elsif(rand'length = 132) then --132
xor_out := rand(131) xor rand(102);
elsif(rand'length = 133) then --133
xor_out := rand(132) xor rand(131) xor rand(81) xor rand(80);
elsif(rand'length = 134) then --134
xor_out := rand(133) xor rand(76);
elsif(rand'length = 135) then --135
xor_out := rand(134) xor rand(123);
elsif(rand'length = 136) then --136
xor_out := rand(135) xor rand(134) xor rand(10) xor rand(9);
elsif(rand'length = 137) then --137
xor_out := rand(136) xor rand(115);
elsif(rand'length = 138) then --138
xor_out := rand(137) xor rand(136) xor rand(130) xor rand(129);
elsif(rand'length = 139) then --139
xor_out := rand(138) xor rand(135) xor rand(133) xor rand(130);
elsif(rand'length = 140) then --140
xor_out := rand(139) xor rand(110);
elsif(rand'length = 141) then --141
xor_out := rand(140) xor rand(139) xor rand(109) xor rand(108);
elsif(rand'length = 142) then --142
xor_out := rand(141) xor rand(120);
elsif(rand'length = 143) then --143
xor_out := rand(142) xor rand(141) xor rand(122) xor rand(121);
elsif(rand'length = 144) then --144
xor_out := rand(143) xor rand(142) xor rand(74) xor rand(73);
elsif(rand'length = 145) then --145
xor_out := rand(144) xor rand(92);
elsif(rand'length = 146) then --146
xor_out := rand(145) xor rand(144) xor rand(86) xor rand(85);
elsif(rand'length = 147) then --147
xor_out := rand(146) xor rand(145) xor rand(109) xor rand(108);
elsif(rand'length = 148) then --148
xor_out := rand(147) xor rand(120);
elsif(rand'length = 149) then --149
xor_out := rand(148) xor rand(147) xor rand(39) xor rand(38);
elsif(rand'length = 150) then --150
xor_out := rand(149) xor rand(96);
elsif(rand'length = 151) then --151
xor_out := rand(150) xor rand(147);
elsif(rand'length = 152) then --152
xor_out := rand(151) xor rand(150) xor rand(86) xor rand(85);
elsif(rand'length = 153) then --153
xor_out := rand(152) xor rand(151);
elsif(rand'length = 154) then --154
xor_out := rand(153) xor rand(151) xor rand(26) xor rand(24);
elsif(rand'length = 155) then --155
xor_out := rand(154) xor rand(153) xor rand(123) xor rand(122);
elsif(rand'length = 156) then --156
xor_out := rand(155) xor rand(154) xor rand(40) xor rand(39);
elsif(rand'length = 157) then --157
xor_out := rand(156) xor rand(155) xor rand(130) xor rand(129);
elsif(rand'length = 158) then --158
xor_out := rand(157) xor rand(156) xor rand(131) xor rand(130);
elsif(rand'length = 159) then --159
xor_out := rand(158) xor rand(127);
elsif(rand'length = 160) then --160
xor_out := rand(159) xor rand(158) xor rand(141) xor rand(140);
elsif(rand'length = 161) then --161
xor_out := rand(160) xor rand(142);
elsif(rand'length = 162) then --162
xor_out := rand(161) xor rand(160) xor rand(74) xor rand(73);
elsif(rand'length = 163) then --163
xor_out := rand(162) xor rand(161) xor rand(103) xor rand(102);
elsif(rand'length = 164) then --164
xor_out := rand(163) xor rand(162) xor rand(150) xor rand(149);
elsif(rand'length = 165) then --165
xor_out := rand(164) xor rand(163) xor rand(134) xor rand(133);
elsif(rand'length = 166) then --166
xor_out := rand(165) xor rand(164) xor rand(127) xor rand(126);
elsif(rand'length = 167) then --167
xor_out := rand(166) xor rand(160);
elsif(rand'length = 168) then --168
xor_out := rand(167) xor rand(165) xor rand(152) xor rand(150);
end if;
return xor_out;
end xor_gates;
--END function for XORing using tap values.
end lfsr_pkg;
--End of the package.
|
----------------------------------------------------------------------------
---- Create Date: 14:30:08 07/28/2010 ----
---- Design Name: lfsr_pkg ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- This is the package file used in the lfsr_randgen project.The ----
---- package contain the function for XORing bits from various tap ----
---- locations depending on the generic parameter(width of lfsr ) ----
---- ----
----------------------------------------------------------------------------
---- ----
---- This file is a part of the lfsr_randgen project at ----
---- http://www.opencores.org/ ----
---- ----
---- Author(s): ----
---- Vipin Lal, [email protected] ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2010 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lfsr_pkg is
function xor_gates( random : std_logic_vector) return std_logic;
end lfsr_pkg;
--Package body starts from here.
package body lfsr_pkg is
--function for XORing from tap values.
function xor_gates( random : std_logic_vector ) return std_logic is
variable xor_out : std_logic:='0';
variable rand : std_logic_vector(random'length-1 downto 0):=random;
begin
if(rand'length = 3) then --3
xor_out := rand(2) xor rand(1);
elsif(rand'length = 2) then --2
xor_out := rand(1) xor rand(0);
elsif(rand'length = 4) then --4
xor_out := rand(3) xor rand(2);
elsif(rand'length = 5) then --5
xor_out := rand(4) xor rand(2);
elsif(rand'length = 6) then --6
xor_out := rand(5) xor rand(4);
elsif(rand'length = 7) then --7
xor_out := rand(6) xor rand(5);
elsif(rand'length = 8) then --8
xor_out := rand(7) xor rand(5) xor rand(4) xor rand(3);
elsif(rand'length = 9) then --9
xor_out := rand(8) xor rand(4);
elsif(rand'length = 10)then --10
xor_out := rand(9) xor rand(6);
elsif(rand'length =11) then --11
xor_out := rand(10) xor rand(8);
elsif(rand'length = 12) then --12
xor_out := rand(11) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 13) then --13
xor_out := rand(12) xor rand(3) xor rand(2) xor rand(0);
elsif(rand'length = 14) then --14
xor_out := rand(13) xor rand(4) xor rand(2) xor rand(0);
elsif(rand'length = 15) then --15
xor_out := rand(14) xor rand(13);
elsif(rand'length = 16) then --16
xor_out := rand(15) xor rand(14) xor rand(12) xor rand(3);
elsif(rand'length = 17) then --17
xor_out := rand(16) xor rand(13);
elsif(rand'length = 18) then --18
xor_out := rand(17) xor rand(10);
elsif(rand'length = 19) then --19
xor_out := rand(18) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 20) then --20
xor_out := rand(19) xor rand(16);
elsif(rand'length = 21) then --21
xor_out := rand(20) xor rand(18);
elsif(rand'length = 22) then --22
xor_out := rand(21) xor rand(20);
elsif(rand'length = 23) then --23
xor_out := rand(22) xor rand(17);
elsif(rand'length = 24) then --24
xor_out := rand(23) xor rand(22) xor rand(21) xor rand(16);
elsif(rand'length = 25) then --25
xor_out := rand(24) xor rand(21);
elsif(rand'length = 26) then --26
xor_out := rand(25) xor rand(5) xor rand(1) xor rand(0);
elsif(rand'length = 27) then --27
xor_out := rand(26) xor rand(4) xor rand(1) xor rand(0);
elsif(rand'length = 28) then --28
xor_out := rand(27) xor rand(24);
elsif(rand'length = 29) then --29
xor_out := rand(28) xor rand(26);
elsif(rand'length = 30) then --30
xor_out := rand(29) xor rand(5) xor rand(3) xor rand(0);
elsif(rand'length = 31) then --31
xor_out := rand(30) xor rand(27);
elsif(rand'length = 32) then --32
xor_out := rand(31) xor rand(21) xor rand(1) xor rand(0);
elsif(rand'length = 33) then --33
xor_out := rand(32) xor rand(19);
elsif(rand'length = 34) then --34
xor_out := rand(33) xor rand(26) xor rand(1) xor rand(0);
elsif(rand'length = 35) then --35
xor_out := rand(34) xor rand(32);
elsif(rand'length = 36) then --36
xor_out := rand(35) xor rand(24);
elsif(rand'length = 37) then --37
xor_out := rand(36) xor rand(4) xor rand(3) xor rand(2) xor rand(1) xor rand(0);
elsif(rand'length = 38) then --38
xor_out := rand(37) xor rand(5) xor rand(4) xor rand(0);
elsif(rand'length = 39) then --39
xor_out := rand(38) xor rand(34);
elsif(rand'length = 40) then --40
xor_out := rand(39) xor rand(37) xor rand(20) xor rand(18);
elsif(rand'length = 41) then --41
xor_out := rand(40) xor rand(37);
elsif(rand'length = 42) then --42
xor_out := rand(41) xor rand(40) xor rand(19) xor rand(18);
elsif(rand'length = 43) then --43
xor_out := rand(42) xor rand(41) xor rand(37) xor rand(36);
elsif(rand'length = 44) then --44
xor_out := rand(43) xor rand(42) xor rand(17) xor rand(16);
elsif(rand'length = 45) then --45
xor_out := rand(44) xor rand(43) xor rand(41) xor rand(40);
elsif(rand'length = 46) then --46
xor_out := rand(45) xor rand(44) xor rand(25) xor rand(24);
elsif(rand'length = 47) then --47
xor_out := rand(46) xor rand(41);
elsif(rand'length = 48) then --48
xor_out := rand(47) xor rand(46) xor rand(20) xor rand(19);
elsif(rand'length = 49) then --49
xor_out := rand(48) xor rand(39);
elsif(rand'length = 50) then --50
xor_out := rand(49) xor rand(48) xor rand(23) xor rand(22);
elsif(rand'length = 51) then --51
xor_out := rand(50) xor rand(49) xor rand(35) xor rand(34);
elsif(rand'length = 52) then --52
xor_out := rand(51) xor rand(48);
elsif(rand'length = 53) then --53
xor_out := rand(52) xor rand(51) xor rand(37) xor rand(36);
elsif(rand'length = 54) then --54
xor_out := rand(53) xor rand(52) xor rand(17) xor rand(16);
elsif(rand'length = 55) then --55
xor_out := rand(54) xor rand(30);
elsif(rand'length = 56) then --56
xor_out := rand(55) xor rand(54) xor rand(34) xor rand(33);
elsif(rand'length = 57) then --57
xor_out := rand(56) xor rand(49);
elsif(rand'length = 58) then --58
xor_out := rand(57) xor rand(38);
elsif(rand'length = 59) then --59
xor_out := rand(58) xor rand(57) xor rand(37) xor rand(36);
elsif(rand'length = 60) then --60
xor_out := rand(59) xor rand(58);
elsif(rand'length = 61) then --61
xor_out := rand(60) xor rand(59) xor rand(45) xor rand(44);
elsif(rand'length = 62) then --62
xor_out := rand(61) xor rand(60) xor rand(5) xor rand(4);
elsif(rand'length = 63) then --63
xor_out := rand(62) xor rand(61);
elsif(rand'length = 64) then --64
xor_out := rand(63) xor rand(62) xor rand(60) xor rand(59);
elsif(rand'length = 65) then --65
xor_out := rand(64) xor rand(46);
elsif(rand'length = 66) then --66
xor_out := rand(65) xor rand(64) xor rand(56) xor rand(55);
elsif(rand'length = 67) then --67
xor_out := rand(66) xor rand(65) xor rand(57) xor rand(56);
elsif(rand'length = 68) then --68
xor_out := rand(67) xor rand(58);
elsif(rand'length = 69) then --69
xor_out := rand(68) xor rand(66) xor rand(41) xor rand(39);
elsif(rand'length = 70) then --70
xor_out := rand(69) xor rand(68) xor rand(54) xor rand(53);
elsif(rand'length = 71) then --71
xor_out := rand(70) xor rand(64);
elsif(rand'length = 72) then --72
xor_out := rand(71) xor rand(65) xor rand(24) xor rand(18);
elsif(rand'length = 73) then --73
xor_out := rand(72) xor rand(47);
elsif(rand'length = 74) then --74
xor_out := rand(73) xor rand(72) xor rand(58) xor rand(57);
elsif(rand'length = 75) then --75
xor_out := rand(74) xor rand(73) xor rand(64) xor rand(63);
elsif(rand'length = 76) then --76
xor_out := rand(75) xor rand(74) xor rand(40) xor rand(39);
elsif(rand'length = 77) then --77
xor_out := rand(76) xor rand(75) xor rand(46) xor rand(45);
elsif(rand'length = 78) then --78
xor_out := rand(77) xor rand(76) xor rand(58) xor rand(57);
elsif(rand'length = 79) then --79
xor_out := rand(78) xor rand(69);
elsif(rand'length = 80) then --80
xor_out := rand(79) xor rand(78) xor rand(42) xor rand(41);
elsif(rand'length = 81) then --81
xor_out := rand(80) xor rand(76);
elsif(rand'length = 82) then --82
xor_out := rand(81) xor rand(78) xor rand(46) xor rand(43);
elsif(rand'length = 83) then --83
xor_out := rand(82) xor rand(81) xor rand(37) xor rand(36);
elsif(rand'length = 84) then --84
xor_out := rand(83) xor rand(70);
elsif(rand'length = 85) then --85
xor_out := rand(84) xor rand(83) xor rand(57) xor rand(56);
elsif(rand'length = 86) then --86
xor_out := rand(85) xor rand(84) xor rand(73) xor rand(72);
elsif(rand'length = 87) then --87
xor_out := rand(86) xor rand(73);
elsif(rand'length = 88) then --88
xor_out := rand(87) xor rand(86) xor rand(16) xor rand(15);
elsif(rand'length = 89) then --89
xor_out := rand(88) xor rand(50);
elsif(rand'length = 90) then --90
xor_out := rand(89) xor rand(88) xor rand(71) xor rand(70);
elsif(rand'length = 91) then --91
xor_out := rand(90) xor rand(89) xor rand(7) xor rand(6);
elsif(rand'length = 92) then --92
xor_out := rand(91) xor rand(90) xor rand(79) xor rand(78);
elsif(rand'length = 93) then --93
xor_out := rand(92) xor rand(90);
elsif(rand'length = 94) then --94
xor_out := rand(93) xor rand(72);
elsif(rand'length = 95) then --95
xor_out := rand(94) xor rand(83);
elsif(rand'length = 96) then --96
xor_out := rand(95) xor rand(93) xor rand(48) xor rand(46);
elsif(rand'length = 97) then --97
xor_out := rand(96) xor rand(90);
elsif(rand'length = 98) then --98
xor_out := rand(97) xor rand(86);
elsif(rand'length = 99) then --99
xor_out := rand(98) xor rand(96) xor rand(53) xor rand(51);
elsif(rand'length = 100) then --100
xor_out := rand(99) xor rand(62);
elsif(rand'length = 101) then --101
xor_out := rand(100) xor rand(99) xor rand(94) xor rand(93);
elsif(rand'length = 102) then --102
xor_out := rand(101) xor rand(100) xor rand(35) xor rand(34);
elsif(rand'length = 103) then --103
xor_out := rand(102) xor rand(93);
elsif(rand'length = 104) then --104
xor_out := rand(103) xor rand(102) xor rand(93) xor rand(92);
elsif(rand'length = 105) then --105
xor_out := rand(104) xor rand(88);
elsif(rand'length = 106) then --106
xor_out := rand(105) xor rand(90);
elsif(rand'length = 107) then --107
xor_out := rand(106) xor rand(104) xor rand(43) xor rand(41);
elsif(rand'length = 108) then --108
xor_out := rand(107) xor rand(76);
elsif(rand'length = 109) then --109
xor_out := rand(108) xor rand(107) xor rand(102) xor rand(101);
elsif(rand'length = 110)then --110
xor_out := rand(109) xor rand(108) xor rand(97) xor rand(96);
elsif(rand'length = 111) then --111
xor_out := rand(110) xor rand(100);
elsif(rand'length = 112) then --112
xor_out := rand(111) xor rand(109) xor rand(68) xor rand(66);
elsif(rand'length = 113) then --113
xor_out := rand(112) xor rand(103);
elsif(rand'length = 114) then --114
xor_out := rand(113) xor rand(112) xor rand(32) xor rand(31);
elsif(rand'length = 115) then --115
xor_out := rand(114) xor rand(113) xor rand(100) xor rand(99);
elsif(rand'length = 116) then --116
xor_out := rand(115) xor rand(114) xor rand(45) xor rand(44);
elsif(rand'length = 117) then --117
xor_out := rand(116) xor rand(114) xor rand(98) xor rand(96);
elsif(rand'length = 118) then --118
xor_out := rand(117) xor rand(84);
elsif(rand'length = 119) then --119
xor_out := rand(118) xor rand(110);
elsif(rand'length = 120) then --120
xor_out := rand(119) xor rand(112) xor rand(8) xor rand(1);
elsif(rand'length = 121) then --121
xor_out := rand(120) xor rand(102);
elsif(rand'length = 122) then --122
xor_out := rand(121) xor rand(120) xor rand(62) xor rand(61);
elsif(rand'length = 123) then --123
xor_out := rand(122) xor rand(120);
elsif(rand'length = 124) then --124
xor_out := rand(123) xor rand(86);
elsif(rand'length = 125) then --125
xor_out := rand(124) xor rand(123) xor rand(17) xor rand(16);
elsif(rand'length = 126) then --126
xor_out := rand(125) xor rand(124) xor rand(89) xor rand(88);
elsif(rand'length = 127) then --127
xor_out := rand(126) xor rand(125);
elsif(rand'length = 128) then --128
xor_out := rand(127) xor rand(125) xor rand(100) xor rand(98);
elsif(rand'length = 129) then --129
xor_out := rand(128) xor rand(123);
elsif(rand'length = 130) then --130
xor_out := rand(129) xor rand(126);
elsif(rand'length = 131) then --131
xor_out := rand(130) xor rand(129) xor rand(83) xor rand(82);
elsif(rand'length = 132) then --132
xor_out := rand(131) xor rand(102);
elsif(rand'length = 133) then --133
xor_out := rand(132) xor rand(131) xor rand(81) xor rand(80);
elsif(rand'length = 134) then --134
xor_out := rand(133) xor rand(76);
elsif(rand'length = 135) then --135
xor_out := rand(134) xor rand(123);
elsif(rand'length = 136) then --136
xor_out := rand(135) xor rand(134) xor rand(10) xor rand(9);
elsif(rand'length = 137) then --137
xor_out := rand(136) xor rand(115);
elsif(rand'length = 138) then --138
xor_out := rand(137) xor rand(136) xor rand(130) xor rand(129);
elsif(rand'length = 139) then --139
xor_out := rand(138) xor rand(135) xor rand(133) xor rand(130);
elsif(rand'length = 140) then --140
xor_out := rand(139) xor rand(110);
elsif(rand'length = 141) then --141
xor_out := rand(140) xor rand(139) xor rand(109) xor rand(108);
elsif(rand'length = 142) then --142
xor_out := rand(141) xor rand(120);
elsif(rand'length = 143) then --143
xor_out := rand(142) xor rand(141) xor rand(122) xor rand(121);
elsif(rand'length = 144) then --144
xor_out := rand(143) xor rand(142) xor rand(74) xor rand(73);
elsif(rand'length = 145) then --145
xor_out := rand(144) xor rand(92);
elsif(rand'length = 146) then --146
xor_out := rand(145) xor rand(144) xor rand(86) xor rand(85);
elsif(rand'length = 147) then --147
xor_out := rand(146) xor rand(145) xor rand(109) xor rand(108);
elsif(rand'length = 148) then --148
xor_out := rand(147) xor rand(120);
elsif(rand'length = 149) then --149
xor_out := rand(148) xor rand(147) xor rand(39) xor rand(38);
elsif(rand'length = 150) then --150
xor_out := rand(149) xor rand(96);
elsif(rand'length = 151) then --151
xor_out := rand(150) xor rand(147);
elsif(rand'length = 152) then --152
xor_out := rand(151) xor rand(150) xor rand(86) xor rand(85);
elsif(rand'length = 153) then --153
xor_out := rand(152) xor rand(151);
elsif(rand'length = 154) then --154
xor_out := rand(153) xor rand(151) xor rand(26) xor rand(24);
elsif(rand'length = 155) then --155
xor_out := rand(154) xor rand(153) xor rand(123) xor rand(122);
elsif(rand'length = 156) then --156
xor_out := rand(155) xor rand(154) xor rand(40) xor rand(39);
elsif(rand'length = 157) then --157
xor_out := rand(156) xor rand(155) xor rand(130) xor rand(129);
elsif(rand'length = 158) then --158
xor_out := rand(157) xor rand(156) xor rand(131) xor rand(130);
elsif(rand'length = 159) then --159
xor_out := rand(158) xor rand(127);
elsif(rand'length = 160) then --160
xor_out := rand(159) xor rand(158) xor rand(141) xor rand(140);
elsif(rand'length = 161) then --161
xor_out := rand(160) xor rand(142);
elsif(rand'length = 162) then --162
xor_out := rand(161) xor rand(160) xor rand(74) xor rand(73);
elsif(rand'length = 163) then --163
xor_out := rand(162) xor rand(161) xor rand(103) xor rand(102);
elsif(rand'length = 164) then --164
xor_out := rand(163) xor rand(162) xor rand(150) xor rand(149);
elsif(rand'length = 165) then --165
xor_out := rand(164) xor rand(163) xor rand(134) xor rand(133);
elsif(rand'length = 166) then --166
xor_out := rand(165) xor rand(164) xor rand(127) xor rand(126);
elsif(rand'length = 167) then --167
xor_out := rand(166) xor rand(160);
elsif(rand'length = 168) then --168
xor_out := rand(167) xor rand(165) xor rand(152) xor rand(150);
end if;
return xor_out;
end xor_gates;
--END function for XORing using tap values.
end lfsr_pkg;
--End of the package.
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