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--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.axistream_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
--========================================================================================================================
--========================================================================================================================
package vvc_methods_pkg is
--========================================================================================================================
-- Types and constants for the AXISTREAM VVC
--========================================================================================================================
constant C_VVC_NAME : string := "AXISTREAM_VVC";
signal AXISTREAM_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is AXISTREAM_VVCT;
alias t_bfm_config is t_axistream_bfm_config;
-- Type found in UVVM-Util types_pkg
constant C_AXISTREAM_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => warning
);
type t_vvc_config is
record
inter_bfm_delay : t_inter_bfm_delay; -- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay.
cmd_queue_count_max : natural; -- Maximum pending number in command queue before queue is full. Adding additional commands will result in an ERROR.
cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if command queue is almost full. Will be ignored if set to 0.
cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold
result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full.
result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if result queue is almost full. Will be ignored if set to 0.
result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold
bfm_config : t_axistream_bfm_config; -- Configuration for the BFM. See BFM quick reference
msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel
end record;
type t_vvc_config_array is array (natural range <>) of t_vvc_config;
constant C_AXISTREAM_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_AXISTREAM_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX,
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_AXISTREAM_BFM_CONFIG_DEFAULT,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT
);
type t_vvc_status is
record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
type t_transaction_info is
record
operation : t_operation;
numPacketsSent : natural;
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
end record;
type t_transaction_info_array is array (natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
operation => NO_OPERATION,
numPacketsSent => 0,
msg => (others => ' ')
);
shared variable shared_axistream_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_AXISTREAM_VVC_CONFIG_DEFAULT);
shared variable shared_axistream_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_VVC_STATUS_DEFAULT);
shared variable shared_axistream_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_TRANSACTION_INFO_DEFAULT);
--========================================================================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order to queue BFM calls
-- in the VVC command queue. The VVC will store and forward these calls to the
-- AXISTREAM BFM when the command is at the from of the VVC command queue.
--========================================================================================================================
procedure axistream_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant user_array : in t_user_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_user_array
constant strb_array : in t_strb_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_strb_array
constant id_array : in t_id_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_id_array
constant dest_array : in t_dest_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_dest_array
constant msg : in string
);
procedure axistream_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant user_array : in t_user_array; -- If you need support for more bits per data byte, replace this with a wider type:
constant msg : in string
);
procedure axistream_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant msg : in string
);
procedure axistream_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string
);
procedure axistream_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string;
constant alert_level : in t_alert_level := error
);
procedure axistream_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant user_array : in t_user_array;
constant msg : in string;
constant alert_level : in t_alert_level := error
);
procedure axistream_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant msg : in string;
constant alert_level : in t_alert_level := error
);
end package vvc_methods_pkg;
package body vvc_methods_pkg is
--========================================================================================================================
-- Methods dedicated to this VVC
--========================================================================================================================
-- These procedures will be used to forward commands to the VVC executor, which will
-- call the corresponding BFM procedures.
procedure axistream_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant user_array : in t_user_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_user_array
constant strb_array : in t_strb_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_strb_array
constant id_array : in t_id_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_id_array
constant dest_array : in t_dest_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_dest_array
constant msg : in string
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(data_array'length, 5) & " bytes)";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, TRANSMIT);
-- Sanity check to avoid confusing fatal error
check_value(data_array'length > 0, TB_ERROR, proc_call & "data_array length must be > 0", "VVC");
-- Generate cmd record
shared_vvc_cmd.data_array(0 to data_array'high) := data_array;
shared_vvc_cmd.user_array(0 to user_array'high) := user_array;
shared_vvc_cmd.strb_array(0 to strb_array'high) := strb_array;
shared_vvc_cmd.id_array(0 to id_array'high) := id_array;
shared_vvc_cmd.dest_array(0 to dest_array'high) := dest_array;
shared_vvc_cmd.data_array_length := data_array'length;
shared_vvc_cmd.user_array_length := user_array'length;
shared_vvc_cmd.strb_array_length := strb_array'length;
shared_vvc_cmd.id_array_length := id_array'length;
shared_vvc_cmd.dest_array_length := dest_array'length;
-- Send command record
send_command_to_vvc(VVCT);
end procedure;
-- Overload, without the strb_array, id_array, dest_array arguments
procedure axistream_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant user_array : in t_user_array;
constant msg : in string
) is
-- Default user data : We don't know c_user_array length (how many words to send), so assume worst case: tdata = 8 bits (one data_array byte per word)
constant c_strb_array : t_strb_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1) := (others => (others => '0'));
constant c_id_array : t_id_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1) := (others => (others => '0'));
constant c_dest_array : t_dest_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1) := (others => (others => '0'));
begin
axistream_transmit(VVCT, vvc_instance_idx, data_array, user_array, c_strb_array, c_id_array, c_dest_array, msg);
end procedure;
-- Overload, without the user_array, strb_array, id_array, dest_array arguments
procedure axistream_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant msg : in string
) is
-- Default user data : We don't know c_user_array length (how many words to send), so assume tdata = 8 bits (one data_array byte per word)
constant c_user_array : t_user_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1) := (others => (others => '0'));
begin
-- Use another overload to fill in the rest
axistream_transmit(VVCT, vvc_instance_idx, data_array, c_user_array, msg);
end procedure;
procedure axistream_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "()";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, RECEIVE);
send_command_to_vvc(VVCT);
end procedure;
-- Expect, receive and compare to specified data_array, user_array, strb_array, id_array, dest_array
procedure axistream_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string;
constant alert_level : in t_alert_level := error
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(data_array'length) & "B)";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, EXPECT);
-- Generate cmd record
shared_vvc_cmd.data_array(0 to data_array'high) := data_array;
shared_vvc_cmd.user_array(0 to user_array'high) := user_array; -- user_array Length = data_array_length
shared_vvc_cmd.strb_array(0 to strb_array'high) := strb_array;
shared_vvc_cmd.id_array(0 to id_array'high) := id_array;
shared_vvc_cmd.dest_array(0 to dest_array'high) := dest_array;
shared_vvc_cmd.data_array_length := data_array'length;
shared_vvc_cmd.user_array_length := user_array'length;
shared_vvc_cmd.strb_array_length := strb_array'length;
shared_vvc_cmd.id_array_length := id_array'length;
shared_vvc_cmd.dest_array_length := dest_array'length;
-- shared_vvc_cmd.readyLowArray(0 to data_array'high) := (others => 0); -- default no ready deassertion
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVCT);
end procedure;
-- Overload for calling axiStreamExpect() without a value for strb_array, id_array, dest_array
-- (will be set to don't care)
procedure axistream_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant user_array : in t_user_array;
constant msg : in string;
constant alert_level : in t_alert_level := error
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(data_array'length) & "B)";
-- Default expected strb, id, dest
-- Don't know #bytes in AXIStream tdata, so *_array length is unknown.
-- Make the array as short as possible for best simulation time during the check performed in the BFM.
constant c_strb_array : t_strb_array(0 downto 0) := (others => (others => '-'));
constant c_id_array : t_id_array(0 downto 0) := (others => (others => '-'));
constant c_dest_array : t_dest_array(0 downto 0) := (others => (others => '-'));
begin
axistream_expect(VVCT, vvc_instance_idx, data_array, user_array, c_strb_array, c_id_array, c_dest_array, msg, alert_level);
end procedure;
-- Overload, without the user_array, strb_array, id_array, dest_array arguments
procedure axistream_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant msg : in string;
constant alert_level : in t_alert_level := error
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(data_array'length) & "B)";
-- Default user data
-- Don't know #bytes in AXIStream tdata, so user_array length is unknown.
-- Make the array as short as possible for best simulation time during the check performed in the BFM.
constant c_user_array : t_user_array(0 downto 0) := (others => (others => '-'));
begin
-- Use another overload to fill in the rest: strb_array, id_array, dest_array
axistream_expect(VVCT, vvc_instance_idx, data_array, c_user_array, msg, alert_level);
end procedure;
end package body vvc_methods_pkg;
|
--
-- FIFO
--
-- Author: Sebastian Witt
-- Date: 29.01.2008
-- Version: 1.3
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_fifo is
generic (
WIDTH : integer := 8; -- FIFO width
SIZE_E : integer := 6 -- FIFO size (2^SIZE_E)
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear FIFO
WRITE : in std_logic; -- Write to FIFO
READ : in std_logic; -- Read from FIFO
D : in std_logic_vector(WIDTH-1 downto 0); -- FIFO input
Q : out std_logic_vector(WIDTH-1 downto 0); -- FIFO output
EMPTY : out std_logic; -- FIFO is empty
FULL : out std_logic; -- FIFO is full
USAGE : out std_logic_vector(SIZE_E-1 downto 0) -- FIFO usage
);
end slib_fifo;
architecture rtl of slib_fifo is
-- Signals
signal iEMPTY : std_logic; -- Internal EMPTY
signal iFULL : std_logic; -- Internal FULL
signal iWRAddr : unsigned(SIZE_E downto 0); -- FIFO write address
signal iRDAddr : unsigned(SIZE_E downto 0); -- FIFO read address
signal iUSAGE : unsigned(SIZE_E-1 downto 0); -- FIFO usage
-- FIFO memory
type FIFO_Mem_Type is array (2**SIZE_E-1 downto 0) of std_logic_vector(WIDTH-1 downto 0);
signal iFIFOMem : FIFO_Mem_Type := (others => (others => '0'));
begin
-- Full signal (biggest difference of read and write address)
iFULL <= '1' when (iRDAddr(SIZE_E-1 downto 0) = iWRAddr(SIZE_E-1 downto 0)) and
(iRDAddr(SIZE_E) /= iWRAddr(SIZE_E)) else '0';
-- Write/read address counter and empty signal
FF_ADDR: process (RST, CLK)
begin
if (RST = '1') then
iWRAddr <= (others => '0');
iRDAddr <= (others => '0');
iEMPTY <= '1';
elsif (CLK'event and CLK='1') then
if (WRITE = '1' and iFULL = '0') then -- Write to FIFO
iWRAddr <= iWRAddr + 1;
end if;
if (READ = '1' and iEMPTY = '0') then -- Read from FIFO
iRDAddr <= iRDAddr + 1;
end if;
if (CLEAR = '1') then -- Reset FIFO
iWRAddr <= (others => '0');
iRDAddr <= (others => '0');
end if;
if (iRDAddr = iWRAddr) then -- Empty signal (read address same as write address)
iEMPTY <= '1';
else
iEMPTY <= '0';
end if;
end if;
end process;
-- FIFO memory process
FF_MEM: process (RST, CLK)
begin
if (RST = '1') then
--iFIFOMem(2**SIZE_E-1 downto 0) <= (others => (others => '0'));
elsif (CLK'event and CLK = '1') then
if (WRITE = '1' and iFULL = '0') then
iFIFOMem(to_integer(iWRAddr(SIZE_E-1 downto 0))) <= D;
end if;
Q <= iFIFOMem(to_integer(iRDAddr(SIZE_E-1 downto 0)));
end if;
end process;
-- Usage counter
FF_USAGE: process (RST, CLK)
begin
if (RST = '1') then
iUSAGE <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (CLEAR = '1') then
iUSAGE <= (others => '0');
else
if (READ = '0' and WRITE = '1' and iFULL = '0') then
iUSAGE <= iUSAGE + 1;
end if;
if (WRITE = '0' and READ = '1' and iEMPTY = '0') then
iUSAGE <= iUSAGE - 1;
end if;
end if;
end if;
end process;
-- Output signals
EMPTY <= iEMPTY;
FULL <= iFULL;
USAGE <= std_logic_vector(iUSAGE);
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1961.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01961ent IS
END c07s02b01x00p02n02i01961ent;
ARCHITECTURE c07s02b01x00p02n02i01961arch OF c07s02b01x00p02n02i01961ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := TRUE;
variable b : boolean := FALSE;
variable c : boolean;
BEGIN
c := a xor b;
assert NOT(c=TRUE)
report "***PASSED TEST: c07s02b01x00p02n02i01961"
severity NOTE;
assert ( c=TRUE )
report "***FAILED TEST: c07s02b01x00p02n02i01961 - Logical operation of 'XOR'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01961arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1961.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01961ent IS
END c07s02b01x00p02n02i01961ent;
ARCHITECTURE c07s02b01x00p02n02i01961arch OF c07s02b01x00p02n02i01961ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := TRUE;
variable b : boolean := FALSE;
variable c : boolean;
BEGIN
c := a xor b;
assert NOT(c=TRUE)
report "***PASSED TEST: c07s02b01x00p02n02i01961"
severity NOTE;
assert ( c=TRUE )
report "***FAILED TEST: c07s02b01x00p02n02i01961 - Logical operation of 'XOR'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01961arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1961.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01961ent IS
END c07s02b01x00p02n02i01961ent;
ARCHITECTURE c07s02b01x00p02n02i01961arch OF c07s02b01x00p02n02i01961ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := TRUE;
variable b : boolean := FALSE;
variable c : boolean;
BEGIN
c := a xor b;
assert NOT(c=TRUE)
report "***PASSED TEST: c07s02b01x00p02n02i01961"
severity NOTE;
assert ( c=TRUE )
report "***FAILED TEST: c07s02b01x00p02n02i01961 - Logical operation of 'XOR'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01961arch;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity ANN_mux_4to1_sel2_32_1 is
generic (
ID :integer := 0;
NUM_STAGE :integer := 1;
din1_WIDTH :integer := 32;
din2_WIDTH :integer := 32;
din3_WIDTH :integer := 32;
din4_WIDTH :integer := 32;
din5_WIDTH :integer := 32;
dout_WIDTH :integer := 32);
port (
din1 :in std_logic_vector(31 downto 0);
din2 :in std_logic_vector(31 downto 0);
din3 :in std_logic_vector(31 downto 0);
din4 :in std_logic_vector(31 downto 0);
din5 :in std_logic_vector(1 downto 0);
dout :out std_logic_vector(31 downto 0));
end entity;
architecture rtl of ANN_mux_4to1_sel2_32_1 is
-- puts internal signals
signal sel : std_logic_vector(1 downto 0);
-- level 1 signals
signal mux_1_0 : std_logic_vector(31 downto 0);
signal mux_1_1 : std_logic_vector(31 downto 0);
-- level 2 signals
signal mux_2_0 : std_logic_vector(31 downto 0);
begin
sel <= din5;
-- Generate level 1 logic
mux_1_0 <= din1 when sel(0) = '0' else din2;
mux_1_1 <= din3 when sel(0) = '0' else din4;
-- Generate level 2 logic
mux_2_0 <= mux_1_0 when sel(1) = '0' else mux_1_1;
-- output logic
dout <= mux_2_0;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity ANN_mux_4to1_sel2_32_1 is
generic (
ID :integer := 0;
NUM_STAGE :integer := 1;
din1_WIDTH :integer := 32;
din2_WIDTH :integer := 32;
din3_WIDTH :integer := 32;
din4_WIDTH :integer := 32;
din5_WIDTH :integer := 32;
dout_WIDTH :integer := 32);
port (
din1 :in std_logic_vector(31 downto 0);
din2 :in std_logic_vector(31 downto 0);
din3 :in std_logic_vector(31 downto 0);
din4 :in std_logic_vector(31 downto 0);
din5 :in std_logic_vector(1 downto 0);
dout :out std_logic_vector(31 downto 0));
end entity;
architecture rtl of ANN_mux_4to1_sel2_32_1 is
-- puts internal signals
signal sel : std_logic_vector(1 downto 0);
-- level 1 signals
signal mux_1_0 : std_logic_vector(31 downto 0);
signal mux_1_1 : std_logic_vector(31 downto 0);
-- level 2 signals
signal mux_2_0 : std_logic_vector(31 downto 0);
begin
sel <= din5;
-- Generate level 1 logic
mux_1_0 <= din1 when sel(0) = '0' else din2;
mux_1_1 <= din3 when sel(0) = '0' else din4;
-- Generate level 2 logic
mux_2_0 <= mux_1_0 when sel(1) = '0' else mux_1_1;
-- output logic
dout <= mux_2_0;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity ANN_mux_4to1_sel2_32_1 is
generic (
ID :integer := 0;
NUM_STAGE :integer := 1;
din1_WIDTH :integer := 32;
din2_WIDTH :integer := 32;
din3_WIDTH :integer := 32;
din4_WIDTH :integer := 32;
din5_WIDTH :integer := 32;
dout_WIDTH :integer := 32);
port (
din1 :in std_logic_vector(31 downto 0);
din2 :in std_logic_vector(31 downto 0);
din3 :in std_logic_vector(31 downto 0);
din4 :in std_logic_vector(31 downto 0);
din5 :in std_logic_vector(1 downto 0);
dout :out std_logic_vector(31 downto 0));
end entity;
architecture rtl of ANN_mux_4to1_sel2_32_1 is
-- puts internal signals
signal sel : std_logic_vector(1 downto 0);
-- level 1 signals
signal mux_1_0 : std_logic_vector(31 downto 0);
signal mux_1_1 : std_logic_vector(31 downto 0);
-- level 2 signals
signal mux_2_0 : std_logic_vector(31 downto 0);
begin
sel <= din5;
-- Generate level 1 logic
mux_1_0 <= din1 when sel(0) = '0' else din2;
mux_1_1 <= din3 when sel(0) = '0' else din4;
-- Generate level 2 logic
mux_2_0 <= mux_1_0 when sel(1) = '0' else mux_1_1;
-- output logic
dout <= mux_2_0;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity ANN_mux_4to1_sel2_32_1 is
generic (
ID :integer := 0;
NUM_STAGE :integer := 1;
din1_WIDTH :integer := 32;
din2_WIDTH :integer := 32;
din3_WIDTH :integer := 32;
din4_WIDTH :integer := 32;
din5_WIDTH :integer := 32;
dout_WIDTH :integer := 32);
port (
din1 :in std_logic_vector(31 downto 0);
din2 :in std_logic_vector(31 downto 0);
din3 :in std_logic_vector(31 downto 0);
din4 :in std_logic_vector(31 downto 0);
din5 :in std_logic_vector(1 downto 0);
dout :out std_logic_vector(31 downto 0));
end entity;
architecture rtl of ANN_mux_4to1_sel2_32_1 is
-- puts internal signals
signal sel : std_logic_vector(1 downto 0);
-- level 1 signals
signal mux_1_0 : std_logic_vector(31 downto 0);
signal mux_1_1 : std_logic_vector(31 downto 0);
-- level 2 signals
signal mux_2_0 : std_logic_vector(31 downto 0);
begin
sel <= din5;
-- Generate level 1 logic
mux_1_0 <= din1 when sel(0) = '0' else din2;
mux_1_1 <= din3 when sel(0) = '0' else din4;
-- Generate level 2 logic
mux_2_0 <= mux_1_0 when sel(1) = '0' else mux_1_1;
-- output logic
dout <= mux_2_0;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity ANN_mux_4to1_sel2_32_1 is
generic (
ID :integer := 0;
NUM_STAGE :integer := 1;
din1_WIDTH :integer := 32;
din2_WIDTH :integer := 32;
din3_WIDTH :integer := 32;
din4_WIDTH :integer := 32;
din5_WIDTH :integer := 32;
dout_WIDTH :integer := 32);
port (
din1 :in std_logic_vector(31 downto 0);
din2 :in std_logic_vector(31 downto 0);
din3 :in std_logic_vector(31 downto 0);
din4 :in std_logic_vector(31 downto 0);
din5 :in std_logic_vector(1 downto 0);
dout :out std_logic_vector(31 downto 0));
end entity;
architecture rtl of ANN_mux_4to1_sel2_32_1 is
-- puts internal signals
signal sel : std_logic_vector(1 downto 0);
-- level 1 signals
signal mux_1_0 : std_logic_vector(31 downto 0);
signal mux_1_1 : std_logic_vector(31 downto 0);
-- level 2 signals
signal mux_2_0 : std_logic_vector(31 downto 0);
begin
sel <= din5;
-- Generate level 1 logic
mux_1_0 <= din1 when sel(0) = '0' else din2;
mux_1_1 <= din3 when sel(0) = '0' else din4;
-- Generate level 2 logic
mux_2_0 <= mux_1_0 when sel(1) = '0' else mux_1_1;
-- output logic
dout <= mux_2_0;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity ANN_mux_4to1_sel2_32_1 is
generic (
ID :integer := 0;
NUM_STAGE :integer := 1;
din1_WIDTH :integer := 32;
din2_WIDTH :integer := 32;
din3_WIDTH :integer := 32;
din4_WIDTH :integer := 32;
din5_WIDTH :integer := 32;
dout_WIDTH :integer := 32);
port (
din1 :in std_logic_vector(31 downto 0);
din2 :in std_logic_vector(31 downto 0);
din3 :in std_logic_vector(31 downto 0);
din4 :in std_logic_vector(31 downto 0);
din5 :in std_logic_vector(1 downto 0);
dout :out std_logic_vector(31 downto 0));
end entity;
architecture rtl of ANN_mux_4to1_sel2_32_1 is
-- puts internal signals
signal sel : std_logic_vector(1 downto 0);
-- level 1 signals
signal mux_1_0 : std_logic_vector(31 downto 0);
signal mux_1_1 : std_logic_vector(31 downto 0);
-- level 2 signals
signal mux_2_0 : std_logic_vector(31 downto 0);
begin
sel <= din5;
-- Generate level 1 logic
mux_1_0 <= din1 when sel(0) = '0' else din2;
mux_1_1 <= din3 when sel(0) = '0' else din4;
-- Generate level 2 logic
mux_2_0 <= mux_1_0 when sel(1) = '0' else mux_1_1;
-- output logic
dout <= mux_2_0;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity ANN_mux_4to1_sel2_32_1 is
generic (
ID :integer := 0;
NUM_STAGE :integer := 1;
din1_WIDTH :integer := 32;
din2_WIDTH :integer := 32;
din3_WIDTH :integer := 32;
din4_WIDTH :integer := 32;
din5_WIDTH :integer := 32;
dout_WIDTH :integer := 32);
port (
din1 :in std_logic_vector(31 downto 0);
din2 :in std_logic_vector(31 downto 0);
din3 :in std_logic_vector(31 downto 0);
din4 :in std_logic_vector(31 downto 0);
din5 :in std_logic_vector(1 downto 0);
dout :out std_logic_vector(31 downto 0));
end entity;
architecture rtl of ANN_mux_4to1_sel2_32_1 is
-- puts internal signals
signal sel : std_logic_vector(1 downto 0);
-- level 1 signals
signal mux_1_0 : std_logic_vector(31 downto 0);
signal mux_1_1 : std_logic_vector(31 downto 0);
-- level 2 signals
signal mux_2_0 : std_logic_vector(31 downto 0);
begin
sel <= din5;
-- Generate level 1 logic
mux_1_0 <= din1 when sel(0) = '0' else din2;
mux_1_1 <= din3 when sel(0) = '0' else din4;
-- Generate level 2 logic
mux_2_0 <= mux_1_0 when sel(1) = '0' else mux_1_1;
-- output logic
dout <= mux_2_0;
end architecture;
|
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port(
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
|
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port(
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
|
entity tb_forgen02 is
end tb_forgen02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_forgen02 is
signal a : std_logic_vector (7 downto 0);
begin
dut: entity work.forgen02
port map (a);
process
begin
wait for 1 ns;
assert a = x"00" severity failure;
wait;
end process;
end behav;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! 8b10b encoder for EPROC_OUT2 module
entity EPROC_OUT2_ENC8b10b is
port(
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
getDataTrig : out std_logic;
edataIN : in std_logic_vector (9 downto 0);
edataINrdy : in std_logic;
EdataOUT : out std_logic_vector(1 downto 0)
);
end EPROC_OUT2_ENC8b10b;
architecture Behavioral of EPROC_OUT2_ENC8b10b is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
component enc8b10_wrap
port (
clk : in std_logic;
rst : in std_logic;
dataCode : in std_logic_vector (1 downto 0); -- 00"data, 01"eop, 10"sop, 11"comma
dataIN : in std_logic_vector (7 downto 0);
dataINrdy : in std_logic;
encDataOut : out std_logic_vector (9 downto 0);
encDataOutrdy : out std_logic
);
end component enc8b10_wrap;
----------------------------------
----------------------------------
component MUX8_Nbit
generic (N : integer := 16);
Port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
data2 : in std_logic_vector((N-1) downto 0);
data3 : in std_logic_vector((N-1) downto 0);
data4 : in std_logic_vector((N-1) downto 0);
data5 : in std_logic_vector((N-1) downto 0);
data6 : in std_logic_vector((N-1) downto 0);
data7 : in std_logic_vector((N-1) downto 0);
sel : in std_logic_vector(2 downto 0);
data_out : out std_logic_vector((N-1) downto 0)
);
end component MUX8_Nbit;
----------------------------------
----------------------------------
constant zeros2bit : std_logic_vector (1 downto 0) := (others=>'0');
signal enc10bit, enc10bit_r : std_logic_vector (9 downto 0);
signal request_cycle_cnt, send_count : std_logic_vector (2 downto 0) := (others=>'0');
signal send_out_trig : std_logic := '0';
signal inp_request_trig, inp_request_trig_out : std_logic;
begin
-------------------------------------------------------------------------------------------
-- input handshaking, request cycle 5 CLKs
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
request_cycle_cnt <= (others=>'0');
else
if inp_request_trig = '1' then
request_cycle_cnt <= (others=>'0');
else
request_cycle_cnt <= request_cycle_cnt + 1;
end if;
end if;
end if;
end process;
--
inp_request_trig <= '1' when (request_cycle_cnt = "100") else '0';
--
inp_reques1clk: pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitCLKx4, inp_request_trig, inp_request_trig_out);
getDataTrig <= inp_request_trig_out;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
send_out_trig <= inp_request_trig;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b encoding
-------------------------------------------------------------------------------------------
enc8b10bx: enc8b10_wrap
port map (
clk => bitCLKx4,
rst => rst,
dataCode => edataIN(9 downto 8), -- 00"data, 01"eop, 10"sop, 11"comma
dataIN => edataIN(7 downto 0),
dataINrdy => edataINrdy, -- one? CLKx4 after inp_request_trig_out
encDataOut => enc10bit
);
-------------------------------------------------------------------------------------------
-- sending out 2 bits @ bitCLK
-------------------------------------------------------------------------------------------
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
enc10bit_r <= (others=>'0');
elsif send_out_trig = '1' then
enc10bit_r <= enc10bit;
end if;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if send_out_trig = '1' then
send_count <= (others=>'0');
else
send_count <= send_count + 1;
end if;
end if;
end process;
--
outmux: MUX8_Nbit
generic map (N=>2)
port map (
data0 => enc10bit_r(1 downto 0),
data1 => enc10bit_r(3 downto 2),
data2 => enc10bit_r(5 downto 4),
data3 => enc10bit_r(7 downto 6),
data4 => enc10bit_r(9 downto 8),
data5 => zeros2bit,
data6 => zeros2bit,
data7 => zeros2bit,
sel => send_count,
data_out => EdataOUT
);
--
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! 8b10b encoder for EPROC_OUT2 module
entity EPROC_OUT2_ENC8b10b is
port(
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
getDataTrig : out std_logic;
edataIN : in std_logic_vector (9 downto 0);
edataINrdy : in std_logic;
EdataOUT : out std_logic_vector(1 downto 0)
);
end EPROC_OUT2_ENC8b10b;
architecture Behavioral of EPROC_OUT2_ENC8b10b is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
component enc8b10_wrap
port (
clk : in std_logic;
rst : in std_logic;
dataCode : in std_logic_vector (1 downto 0); -- 00"data, 01"eop, 10"sop, 11"comma
dataIN : in std_logic_vector (7 downto 0);
dataINrdy : in std_logic;
encDataOut : out std_logic_vector (9 downto 0);
encDataOutrdy : out std_logic
);
end component enc8b10_wrap;
----------------------------------
----------------------------------
component MUX8_Nbit
generic (N : integer := 16);
Port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
data2 : in std_logic_vector((N-1) downto 0);
data3 : in std_logic_vector((N-1) downto 0);
data4 : in std_logic_vector((N-1) downto 0);
data5 : in std_logic_vector((N-1) downto 0);
data6 : in std_logic_vector((N-1) downto 0);
data7 : in std_logic_vector((N-1) downto 0);
sel : in std_logic_vector(2 downto 0);
data_out : out std_logic_vector((N-1) downto 0)
);
end component MUX8_Nbit;
----------------------------------
----------------------------------
constant zeros2bit : std_logic_vector (1 downto 0) := (others=>'0');
signal enc10bit, enc10bit_r : std_logic_vector (9 downto 0);
signal request_cycle_cnt, send_count : std_logic_vector (2 downto 0) := (others=>'0');
signal send_out_trig : std_logic := '0';
signal inp_request_trig, inp_request_trig_out : std_logic;
begin
-------------------------------------------------------------------------------------------
-- input handshaking, request cycle 5 CLKs
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
request_cycle_cnt <= (others=>'0');
else
if inp_request_trig = '1' then
request_cycle_cnt <= (others=>'0');
else
request_cycle_cnt <= request_cycle_cnt + 1;
end if;
end if;
end if;
end process;
--
inp_request_trig <= '1' when (request_cycle_cnt = "100") else '0';
--
inp_reques1clk: pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitCLKx4, inp_request_trig, inp_request_trig_out);
getDataTrig <= inp_request_trig_out;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
send_out_trig <= inp_request_trig;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b encoding
-------------------------------------------------------------------------------------------
enc8b10bx: enc8b10_wrap
port map (
clk => bitCLKx4,
rst => rst,
dataCode => edataIN(9 downto 8), -- 00"data, 01"eop, 10"sop, 11"comma
dataIN => edataIN(7 downto 0),
dataINrdy => edataINrdy, -- one? CLKx4 after inp_request_trig_out
encDataOut => enc10bit
);
-------------------------------------------------------------------------------------------
-- sending out 2 bits @ bitCLK
-------------------------------------------------------------------------------------------
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
enc10bit_r <= (others=>'0');
elsif send_out_trig = '1' then
enc10bit_r <= enc10bit;
end if;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if send_out_trig = '1' then
send_count <= (others=>'0');
else
send_count <= send_count + 1;
end if;
end if;
end process;
--
outmux: MUX8_Nbit
generic map (N=>2)
port map (
data0 => enc10bit_r(1 downto 0),
data1 => enc10bit_r(3 downto 2),
data2 => enc10bit_r(5 downto 4),
data3 => enc10bit_r(7 downto 6),
data4 => enc10bit_r(9 downto 8),
data5 => zeros2bit,
data6 => zeros2bit,
data7 => zeros2bit,
sel => send_count,
data_out => EdataOUT
);
--
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! 8b10b encoder for EPROC_OUT2 module
entity EPROC_OUT2_ENC8b10b is
port(
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
getDataTrig : out std_logic;
edataIN : in std_logic_vector (9 downto 0);
edataINrdy : in std_logic;
EdataOUT : out std_logic_vector(1 downto 0)
);
end EPROC_OUT2_ENC8b10b;
architecture Behavioral of EPROC_OUT2_ENC8b10b is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
component enc8b10_wrap
port (
clk : in std_logic;
rst : in std_logic;
dataCode : in std_logic_vector (1 downto 0); -- 00"data, 01"eop, 10"sop, 11"comma
dataIN : in std_logic_vector (7 downto 0);
dataINrdy : in std_logic;
encDataOut : out std_logic_vector (9 downto 0);
encDataOutrdy : out std_logic
);
end component enc8b10_wrap;
----------------------------------
----------------------------------
component MUX8_Nbit
generic (N : integer := 16);
Port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
data2 : in std_logic_vector((N-1) downto 0);
data3 : in std_logic_vector((N-1) downto 0);
data4 : in std_logic_vector((N-1) downto 0);
data5 : in std_logic_vector((N-1) downto 0);
data6 : in std_logic_vector((N-1) downto 0);
data7 : in std_logic_vector((N-1) downto 0);
sel : in std_logic_vector(2 downto 0);
data_out : out std_logic_vector((N-1) downto 0)
);
end component MUX8_Nbit;
----------------------------------
----------------------------------
constant zeros2bit : std_logic_vector (1 downto 0) := (others=>'0');
signal enc10bit, enc10bit_r : std_logic_vector (9 downto 0);
signal request_cycle_cnt, send_count : std_logic_vector (2 downto 0) := (others=>'0');
signal send_out_trig : std_logic := '0';
signal inp_request_trig, inp_request_trig_out : std_logic;
begin
-------------------------------------------------------------------------------------------
-- input handshaking, request cycle 5 CLKs
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
request_cycle_cnt <= (others=>'0');
else
if inp_request_trig = '1' then
request_cycle_cnt <= (others=>'0');
else
request_cycle_cnt <= request_cycle_cnt + 1;
end if;
end if;
end if;
end process;
--
inp_request_trig <= '1' when (request_cycle_cnt = "100") else '0';
--
inp_reques1clk: pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitCLKx4, inp_request_trig, inp_request_trig_out);
getDataTrig <= inp_request_trig_out;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
send_out_trig <= inp_request_trig;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b encoding
-------------------------------------------------------------------------------------------
enc8b10bx: enc8b10_wrap
port map (
clk => bitCLKx4,
rst => rst,
dataCode => edataIN(9 downto 8), -- 00"data, 01"eop, 10"sop, 11"comma
dataIN => edataIN(7 downto 0),
dataINrdy => edataINrdy, -- one? CLKx4 after inp_request_trig_out
encDataOut => enc10bit
);
-------------------------------------------------------------------------------------------
-- sending out 2 bits @ bitCLK
-------------------------------------------------------------------------------------------
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
enc10bit_r <= (others=>'0');
elsif send_out_trig = '1' then
enc10bit_r <= enc10bit;
end if;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if send_out_trig = '1' then
send_count <= (others=>'0');
else
send_count <= send_count + 1;
end if;
end if;
end process;
--
outmux: MUX8_Nbit
generic map (N=>2)
port map (
data0 => enc10bit_r(1 downto 0),
data1 => enc10bit_r(3 downto 2),
data2 => enc10bit_r(5 downto 4),
data3 => enc10bit_r(7 downto 6),
data4 => enc10bit_r(9 downto 8),
data5 => zeros2bit,
data6 => zeros2bit,
data7 => zeros2bit,
sel => send_count,
data_out => EdataOUT
);
--
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! 8b10b encoder for EPROC_OUT2 module
entity EPROC_OUT2_ENC8b10b is
port(
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
getDataTrig : out std_logic;
edataIN : in std_logic_vector (9 downto 0);
edataINrdy : in std_logic;
EdataOUT : out std_logic_vector(1 downto 0)
);
end EPROC_OUT2_ENC8b10b;
architecture Behavioral of EPROC_OUT2_ENC8b10b is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
component enc8b10_wrap
port (
clk : in std_logic;
rst : in std_logic;
dataCode : in std_logic_vector (1 downto 0); -- 00"data, 01"eop, 10"sop, 11"comma
dataIN : in std_logic_vector (7 downto 0);
dataINrdy : in std_logic;
encDataOut : out std_logic_vector (9 downto 0);
encDataOutrdy : out std_logic
);
end component enc8b10_wrap;
----------------------------------
----------------------------------
component MUX8_Nbit
generic (N : integer := 16);
Port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
data2 : in std_logic_vector((N-1) downto 0);
data3 : in std_logic_vector((N-1) downto 0);
data4 : in std_logic_vector((N-1) downto 0);
data5 : in std_logic_vector((N-1) downto 0);
data6 : in std_logic_vector((N-1) downto 0);
data7 : in std_logic_vector((N-1) downto 0);
sel : in std_logic_vector(2 downto 0);
data_out : out std_logic_vector((N-1) downto 0)
);
end component MUX8_Nbit;
----------------------------------
----------------------------------
constant zeros2bit : std_logic_vector (1 downto 0) := (others=>'0');
signal enc10bit, enc10bit_r : std_logic_vector (9 downto 0);
signal request_cycle_cnt, send_count : std_logic_vector (2 downto 0) := (others=>'0');
signal send_out_trig : std_logic := '0';
signal inp_request_trig, inp_request_trig_out : std_logic;
begin
-------------------------------------------------------------------------------------------
-- input handshaking, request cycle 5 CLKs
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
request_cycle_cnt <= (others=>'0');
else
if inp_request_trig = '1' then
request_cycle_cnt <= (others=>'0');
else
request_cycle_cnt <= request_cycle_cnt + 1;
end if;
end if;
end if;
end process;
--
inp_request_trig <= '1' when (request_cycle_cnt = "100") else '0';
--
inp_reques1clk: pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitCLKx4, inp_request_trig, inp_request_trig_out);
getDataTrig <= inp_request_trig_out;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
send_out_trig <= inp_request_trig;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b encoding
-------------------------------------------------------------------------------------------
enc8b10bx: enc8b10_wrap
port map (
clk => bitCLKx4,
rst => rst,
dataCode => edataIN(9 downto 8), -- 00"data, 01"eop, 10"sop, 11"comma
dataIN => edataIN(7 downto 0),
dataINrdy => edataINrdy, -- one? CLKx4 after inp_request_trig_out
encDataOut => enc10bit
);
-------------------------------------------------------------------------------------------
-- sending out 2 bits @ bitCLK
-------------------------------------------------------------------------------------------
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
enc10bit_r <= (others=>'0');
elsif send_out_trig = '1' then
enc10bit_r <= enc10bit;
end if;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if send_out_trig = '1' then
send_count <= (others=>'0');
else
send_count <= send_count + 1;
end if;
end if;
end process;
--
outmux: MUX8_Nbit
generic map (N=>2)
port map (
data0 => enc10bit_r(1 downto 0),
data1 => enc10bit_r(3 downto 2),
data2 => enc10bit_r(5 downto 4),
data3 => enc10bit_r(7 downto 6),
data4 => enc10bit_r(9 downto 8),
data5 => zeros2bit,
data6 => zeros2bit,
data7 => zeros2bit,
sel => send_count,
data_out => EdataOUT
);
--
end Behavioral;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0;
USE mult_gen_v12_0.mult_gen_v12_0;
ENTITY mult_fft IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(55 DOWNTO 0)
);
END mult_fft;
ARCHITECTURE mult_fft_arch OF mult_fft IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mult_fft_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(55 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF mult_fft_arch: ARCHITECTURE IS "mult_gen_v12_0,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF mult_fft_arch : ARCHITECTURE IS "mult_fft,mult_gen_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF mult_fft_arch: ARCHITECTURE IS "mult_fft,mult_gen_v12_0,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=5,C_A_WIDTH=28,C_A_TYPE=0,C_B_WIDTH=28,C_B_TYPE=0,C_OUT_HIGH=55,C_OUT_LOW=0,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "zynq",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 5,
C_A_WIDTH => 28,
C_A_TYPE => 0,
C_B_WIDTH => 28,
C_B_TYPE => 0,
C_OUT_HIGH => 55,
C_OUT_LOW => 0,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mult_fft_arch;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0;
USE mult_gen_v12_0.mult_gen_v12_0;
ENTITY mult_fft IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(55 DOWNTO 0)
);
END mult_fft;
ARCHITECTURE mult_fft_arch OF mult_fft IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mult_fft_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(55 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF mult_fft_arch: ARCHITECTURE IS "mult_gen_v12_0,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF mult_fft_arch : ARCHITECTURE IS "mult_fft,mult_gen_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF mult_fft_arch: ARCHITECTURE IS "mult_fft,mult_gen_v12_0,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=5,C_A_WIDTH=28,C_A_TYPE=0,C_B_WIDTH=28,C_B_TYPE=0,C_OUT_HIGH=55,C_OUT_LOW=0,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "zynq",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 5,
C_A_WIDTH => 28,
C_A_TYPE => 0,
C_B_WIDTH => 28,
C_B_TYPE => 0,
C_OUT_HIGH => 55,
C_OUT_LOW => 0,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mult_fft_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1747.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY vests45 IS
function resolve_bit ( inputs : bit_vector) return bit is
VARIABLE val : bit := '0';
begin
if inputs'length = 0 then
return val;
else
for i in inputs'range LOOP
if inputs(i) = '1' then return '1'; end if;
END LOOP;
return '0';
end if;
end resolve_bit;
END vests45;
ARCHITECTURE c09s05b00x00p12n02i01747arch OF vests45 IS
signal a : resolve_bit bit BUS;
signal b : resolve_bit bit BUS;
signal grd : boolean;
BEGIN
grd <= TRUE after 10 ns,
FALSE after 20 ns;
block_label : BLOCK (grd)
begin
b <= guarded '1' after 1 ns;
end block block_label;
block_label_1 : BLOCK (grd)
begin
TESTING: PROCESS
BEGIN
if GUARD then
a <= '1' after 1 ns;
else
a <= NULL;
end if;
wait on GUARD, a;
END PROCESS TESTING;
end block block_label_1;
process(a,b)
variable f1, f2 : integer := 0;
begin
if (now = 11 ns) and (a=b) then
f1 := 1;
end if;
if (now = 20 ns) and (a=b) then
f2 := 1;
end if;
if (now = 20 ns) then
assert NOT((f1=1) and (f2=1))
report "***PASSED TEST: c09s05b00x00p12n02i01747"
severity NOTE;
assert ((f1=1) and (f2=1))
report "***FAILED TEST: c09s05b00x00p12n02i01747 - The concurrent guarded signal assignment statement has an equivalent process statement."
severity ERROR;
end if;
end process;
END c09s05b00x00p12n02i01747arch;
|
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_axi_lite_sm.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: This module is reponsible for bringing up both the MAC and the
-- attached PHY (if any) to enable basic packet transfer in both directions.
-- It is intended to be directly usable on a xilinx demo platform to demonstrate
-- simple bring up and data transfer. The mac speed is set via inputs (which
-- can be connected to dip switches) and the PHY is configured to ONLY advertise
-- the specified speed. To maximise compatibility on boards only IEEE registers
-- are used and the PHY address can be set via a parameter.
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity config_mac_phy_sm is
port (
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
phy_interrupt_n : in std_logic;
mac_interrupt : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_command : in std_logic;
serial_response : out std_logic;
debug0_sig : out std_logic;
debug1_sig : out std_logic;
debug2_sig : out std_logic;
debug3_sig : out std_logic;
s_axi_awaddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_awvalid : out std_logic := '0';
s_axi_awready : in std_logic := '0';
s_axi_wdata : out std_logic_vector(31 downto 0) := (others => '0');
s_axi_wvalid : out std_logic := '0';
s_axi_wready : in std_logic := '0';
s_axi_bresp : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_bvalid : in std_logic := '0';
s_axi_bready : out std_logic := '0';
s_axi_araddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_arvalid : out std_logic := '0';
s_axi_arready : in std_logic := '0';
s_axi_rdata : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_rresp : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_rvalid : in std_logic := '0';
s_axi_rready : out std_logic := '0'
);
end config_mac_phy_sm;
architecture rtl of config_mac_phy_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
component aeg_design_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
-- main state machine
-- Encoded main state machine states.
type state_typ is (STARTUP,
-- CHANGE_SPEED, -- not necessary, check phy first
-- MDIO_SET_INTERRUPT,
-- MDIO_READ_INTERRUPT,
MDIO_RESTART, -- restart and autoneg
MDIO_STATS, -- polling for autoneg
MDIO_STATS_POLL_CHECK, -- polling for autoneg, replace with interrupt
MDIO_READ_INTERRUPT2,
MDIO_READ_SPEED,
MDIO_READ_SPEED_POLL,
MAC_UPDATE_SPEED100,
MAC_UPDATE_SPEED1000,
CHECK_SPEED); -- waiting for a speed update
-- MDIO State machine
type mdio_state_typ is (IDLE,
SET_DATA,
INIT,
POLL);
-- AXI State Machine
type axi_state_typ is (IDLE_A,
READ,
WRITE,
DONE);
-- Management configuration register address (0x500)
constant CONFIG_MANAGEMENT_ADD : std_logic_vector(16 downto 0) := "00000" & X"500";
-- Receiver configuration register address (0x4040)
constant RECEIVER_ADD : std_logic_vector(16 downto 0) := "00000" & X"404";
-- Transmitter configuration register address (0x4080)
constant TRANSMITTER_ADD : std_logic_vector(16 downto 0) :="00000" & X"408";
-- Speed configuration register address (0x410)
constant SPEED_CONFIG_ADD : std_logic_vector(16 downto 0) :="00000" & X"410";
-- MDIO registers
constant MDIO_CONTROL : std_logic_vector(16 downto 0) := "00000" & X"504";
constant MDIO_TX_DATA : std_logic_vector(16 downto 0) := "00000" & X"508";
constant MDIO_RX_DATA : std_logic_vector(16 downto 0) := "00000" & X"50C";
constant MDIO_OP_RD : std_logic_vector(1 downto 0) := "10";
constant MDIO_OP_WR : std_logic_vector(1 downto 0) := "01";
-- PHY Registers
-- phy address is actually a 6 bit field but other bits are reserved so simpler to specify as 8 bit
--constant PHY_ADDR : std_logic_vector(7 downto 0) := X"07";
constant PHY_ADDR : std_logic_vector(7 downto 0) := X"00";
constant PHY_CONTROL_REG : std_logic_vector(7 downto 0) := X"00";
constant PHY_STATUS_REG : std_logic_vector(7 downto 0) := X"01";
constant PHY_ABILITY_REG : std_logic_vector(7 downto 0) := X"04";
constant PHY_1000BASET_CONTROL_REG : std_logic_vector(7 downto 0) := X"09";
constant PHY_1000BASET_STATUS_REG : std_logic_vector(7 downto 0) := X"0A";
constant PHY_INTERRUPT_REG : std_logic_vector(7 downto 0) := X"12";
constant PHY_CLEAR_INTERRUPT_REG : std_logic_vector(7 downto 0) := X"13";
---------------------------------------------------
-- Signal declarations
signal axi_status : std_logic_vector(4 downto 0); -- used to keep track of axi transactions
signal mdio_ready : std_logic := '0'; -- captured to acknowledge the end of mdio transactions
signal axi_rd_data : std_logic_vector(31 downto 0) := (others => '0');
signal axi_wr_data : std_logic_vector(31 downto 0);
signal mdio_wr_data : std_logic_vector(31 downto 0) := (others => '0');
signal axi_state : state_typ; -- main state machine to configure example design
signal mdio_access_sm : mdio_state_typ; -- mdio state machine to handle mdio register config
signal axi_access_sm : axi_state_typ; -- axi state machine - handles the 5 channels
signal start_access : std_logic; -- used to kick the axi acees state machine
signal start_mdio : std_logic; -- used to kick the mdio state machine
signal drive_mdio : std_logic; -- selects between mdio fields and direct sm control
signal mdio_op : std_logic_vector(1 downto 0);
signal mdio_reg_addr : std_logic_vector(7 downto 0);
signal writenread : std_logic;
signal addr : std_logic_vector(16 downto 0);
signal speed : std_logic_vector(1 downto 0);
signal update_speed_sync : std_logic;
signal update_speed_reg : std_logic;
signal count_shift : std_logic_vector(20 downto 0) := (others => '1');
-- to avoid logic being stripped a serial input is included which enables an address/data and
-- control to be setup for a user config access..
signal serial_command_shift : std_logic_vector(36 downto 0);
signal load_data : std_logic;
signal capture_data : std_logic;
signal write_access : std_logic;
signal read_access : std_logic;
signal s_axi_reset : std_logic;
signal s_axi_awvalid_int : std_logic;
signal s_axi_wvalid_int : std_logic;
signal s_axi_bready_int : std_logic;
signal s_axi_arvalid_int : std_logic;
signal s_axi_rready_int : std_logic;
--attribute mark_debug : string;
--attribute mark_debug of axi_status : signal is "true";
--attribute mark_debug of mdio_ready : signal is "true";
--attribute mark_debug of axi_rd_data : signal is "true";
--attribute mark_debug of axi_wr_data : signal is "true";
--attribute mark_debug of mdio_wr_data : signal is "true";
--attribute mark_debug of axi_state : signal is "true";
--attribute mark_debug of mdio_access_sm : signal is "true";
--attribute mark_debug of axi_access_sm : signal is "true";
--attribute mark_debug of start_access : signal is "true";
--attribute mark_debug of start_mdio : signal is "true";
--attribute mark_debug of drive_mdio : signal is "true";
--attribute mark_debug of mdio_op : signal is "true";
--attribute mark_debug of mdio_reg_addr : signal is "true";
--attribute mark_debug of writenread : signal is "true";
--attribute mark_debug of addr : signal is "true";
--attribute mark_debug of speed : signal is "true";
--attribute mark_debug of update_speed_sync : signal is "true";
--attribute mark_debug of update_speed_reg : signal is "true";
--attribute mark_debug of count_shift : signal is "true";
--attribute mark_debug of s_axi_aclk : signal is "true";
--attribute mark_debug of s_axi_resetn : signal is "true";
--attribute mark_debug of phy_interrupt_n : signal is "true";
--attribute mark_debug of mac_interrupt : signal is "true";
--attribute mark_debug of s_axi_awaddr : signal is "true";
--attribute mark_debug of s_axi_awvalid : signal is "true";
--attribute mark_debug of s_axi_awready : signal is "true";
--attribute mark_debug of s_axi_wdata : signal is "true";
--attribute mark_debug of s_axi_wvalid : signal is "true";
--attribute mark_debug of s_axi_wready : signal is "true";
--attribute mark_debug of s_axi_bresp : signal is "true";
--attribute mark_debug of s_axi_bvalid : signal is "true";
--attribute mark_debug of s_axi_bready : signal is "true";
--attribute mark_debug of s_axi_araddr : signal is "true";
--attribute mark_debug of s_axi_arvalid : signal is "true";
--attribute mark_debug of s_axi_arready : signal is "true";
--attribute mark_debug of s_axi_rdata : signal is "true";
--attribute mark_debug of s_axi_rresp : signal is "true";
--attribute mark_debug of s_axi_rvalid : signal is "true";
--attribute mark_debug of s_axi_rready : signal is "true";
begin
s_axi_awvalid <= s_axi_awvalid_int;
s_axi_wvalid <= s_axi_wvalid_int;
s_axi_bready <= s_axi_bready_int;
s_axi_arvalid <= s_axi_arvalid_int;
s_axi_rready <= s_axi_rready_int;
s_axi_reset <= not s_axi_resetn;
update_speed_sync <= update_speed;
update_reg : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
update_speed_reg <= '0';
else
update_speed_reg <= update_speed_sync;
end if;
end if;
end process update_reg;
-----------------------------------------------------------------------------
-- Management process. This process sets up the configuration by
-- turning off flow control, then checks gathered statistics at the
-- end of transmission
-----------------------------------------------------------------------------
gen_state : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
axi_state <= STARTUP;
start_access <= '0';
start_mdio <= '0';
drive_mdio <= '0';
mdio_op <= (others => '0');
mdio_reg_addr <= (others => '0');
writenread <= '0';
addr <= (others => '0');
axi_wr_data <= (others => '0');
speed <= mac_speed;
debug0_sig <= '0';
debug1_sig <= '0';
debug2_sig <= '0';
debug3_sig <= '0';
-- main state machine is kicking off multi cycle accesses in each state so has to
-- stall while they take place
elsif axi_access_sm = IDLE_A and mdio_access_sm = IDLE and start_access = '0' and start_mdio = '0' then
case axi_state is
when STARTUP =>
-- this state will be ran after reset to wait for count_shift
if (count_shift(20) = '0') then
-- set up MDC frequency. Write to Management configuration
-- register. This will enable MDIO and set MDC to 2.5MHz
speed <= mac_speed;
assert false
report "Setting MDC Frequency to 2.5MHz...." & cr
severity note;
start_mdio <= '0';
drive_mdio <= '0';
start_access <= '1';
writenread <= '1';
addr <= CONFIG_MANAGEMENT_ADD;
--axi_wr_data <= X"00000053"; -- this is 2.5 MHz
axi_wr_data <= X"00000068";
axi_state <= MDIO_RESTART;
end if;
-- when SET_PHY_SPEEDS => -- not needed, MAC and PHY support both 10M - 1G defaultly
-- when MDIO_SET_INTERRUPT =>
-- debug0_sig <= '1';
-- -- set auto-negotiation interrupt
-- assert false
-- report "Setting Auto-Negotiation-Completed interrupt" & cr
-- severity note;
-- drive_mdio <= '1';
-- start_mdio <= '1';
-- start_access <= '0';
-- writenread <= '0';
-- mdio_reg_addr <= PHY_INTERRUPT_REG;
-- mdio_op <= MDIO_OP_WR;
-- axi_wr_data <= X"00000800"; -- bit 11 for auto-negotiation completed, bit 14 for speed changed
-- axi_state <= MDIO_READ_INTERRUPT;
-- when MDIO_READ_INTERRUPT =>
-- drive_mdio <= '1';
-- start_mdio <= '1';
-- start_access <= '0';
-- writenread <= '0';
-- assert false
-- report "Read interrupt" & cr
-- severity note;
-- mdio_reg_addr <= PHY_INTERRUPT_REG;
-- mdio_op <= MDIO_OP_RD;
-- axi_state <= MDIO_RESTART;
when MDIO_RESTART =>
if axi_rd_data = X"00010800" then
debug1_sig <= '1';
end if;
-- set autoneg and reset
-- if loopback is selected then do not set autonegotiate and program the required speed directly
-- otherwise set autonegotiate
assert false
report "Applying PHY software reset" & cr
severity note;
drive_mdio <= '1';
start_mdio <= '1';
start_access <= '0';
writenread <= '0';
mdio_reg_addr <= PHY_CONTROL_REG;
mdio_op <= MDIO_OP_WR;
--axi_wr_data <= X"0000" & X"9" & X"000";
axi_wr_data <= X"00009000";
axi_state <= MDIO_STATS;
when MDIO_STATS =>
drive_mdio <= '1';
start_mdio <= '1';
start_access <= '0';
writenread <= '0';
assert false
report "Wait for Autonegotiation to complete" & cr
severity note;
mdio_reg_addr <= PHY_STATUS_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_STATS_POLL_CHECK;
when MDIO_STATS_POLL_CHECK =>
-- bit 5 is autoneg complete - assume required speed is selected
if axi_rd_data(5) = '1' then
axi_state <= MDIO_READ_INTERRUPT2;
-- axi_state <= CHECK_SPEED;
else
axi_state <= MDIO_STATS;
end if;
when MDIO_READ_INTERRUPT2 =>
drive_mdio <= '1';
start_mdio <= '1';
start_access <= '0';
writenread <= '0';
assert false
report "Read interrupt" & cr
severity note;
mdio_reg_addr <= PHY_INTERRUPT_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_READ_SPEED;
when MDIO_READ_SPEED =>
drive_mdio <= '1';
start_mdio <= '1';
start_access <= '0';
writenread <= '0';
assert false
report "Read negotiated speed" & cr
severity note;
mdio_reg_addr <= PHY_1000BASET_STATUS_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_READ_SPEED_POLL;
when MDIO_READ_SPEED_POLL =>
if axi_rd_data(11) = '1' then -- link partner 1G capable
axi_state <= MAC_UPDATE_SPEED1000;
debug2_sig <= '1';
else
axi_state <= MAC_UPDATE_SPEED100;
debug2_sig <= '0';
end if;
when MAC_UPDATE_SPEED100 =>
assert false
report "Programming MAC speed 100" & cr
severity note;
drive_mdio <= '0';
start_mdio <= '0';
start_access <= '1';
writenread <= '1';
addr <= SPEED_CONFIG_ADD;
-- bits 31:30 are used
axi_wr_data <= "01" & X"0000000" & "00";
axi_state <= CHECK_SPEED;
when MAC_UPDATE_SPEED1000 =>
assert false
report "Programming MAC speed 1000" & cr
severity note;
drive_mdio <= '0';
start_mdio <= '0';
start_access <= '1';
writenread <= '1';
addr <= SPEED_CONFIG_ADD;
-- bits 31:30 are used
axi_wr_data <= "10" & X"0000000" & "00";
axi_state <= CHECK_SPEED;
when CHECK_SPEED =>
debug3_sig <= '1';
if update_speed_reg = '1' then
--axi_state <= CHANGE_SPEED;
axi_state <= STARTUP;
else
if capture_data = '1' then
axi_wr_data <= serial_command_shift(33 downto 2);
end if;
if write_access = '1' or read_access = '1' then
addr <= "00000" & serial_command_shift (13 downto 2);
start_access <= '1';
writenread <= write_access;
end if;
end if;
when others =>
axi_state <= STARTUP;
end case;
else
start_access <= '0';
start_mdio <= '0';
end if;
end if;
end process gen_state;
--------------------------------------------------
-- MDIO setup - split from main state machine to make more manageable
gen_mdio_state : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
mdio_access_sm <= IDLE;
elsif axi_access_sm = IDLE_A or axi_access_sm = DONE then
case mdio_access_sm is
when IDLE =>
if start_mdio = '1' then
if mdio_op = MDIO_OP_WR then
mdio_access_sm <= SET_DATA;
mdio_wr_data <= axi_wr_data;
else
mdio_access_sm <= INIT;
mdio_wr_data <= PHY_ADDR & mdio_reg_addr & mdio_op & "001" & "00000000000";
end if;
end if;
when SET_DATA =>
mdio_access_sm <= INIT;
mdio_wr_data <= PHY_ADDR & mdio_reg_addr & mdio_op & "001" & "00000000000";
when INIT =>
mdio_access_sm <= POLL;
when POLL =>
if mdio_ready = '1' then
mdio_access_sm <= IDLE;
end if;
end case;
elsif mdio_access_sm = POLL and mdio_ready = '1' then
mdio_access_sm <= IDLE;
end if;
end if;
end process gen_mdio_state;
---------------------------------------------------------------------------------------------
-- processes to generate the axi transactions - only simple reads and write can be generated
gen_axi_state : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
axi_access_sm <= IDLE_A;
else
case axi_access_sm is
when IDLE_A =>
if start_access = '1' or start_mdio = '1' or mdio_access_sm /= IDLE then
if mdio_access_sm = POLL then
axi_access_sm <= READ;
elsif (start_access = '1' and writenread = '1') or
(start_mdio = '1' or mdio_access_sm = SET_DATA or mdio_access_sm = INIT) then
axi_access_sm <= WRITE;
else
axi_access_sm <= READ;
end if;
end if;
when WRITE =>
-- wait in this state until axi_status signals the write is complete
if axi_status(4 downto 2) = "111" then
axi_access_sm <= DONE;
end if;
when READ =>
-- wait in this state until axi_status signals the read is complete
if axi_status(1 downto 0) = "11" then
axi_access_sm <= DONE;
end if;
when DONE =>
axi_access_sm <= IDLE_A;
end case;
end if;
end if;
end process gen_axi_state;
-- need a process per axi interface (i.e 5)
-- in each case the interface is driven accordingly and once acknowledged a sticky
-- status bit is set and the process waits until the access_sm moves on
-- READ ADDR
read_addr_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = READ then
if axi_status(0) = '0' then
if drive_mdio = '1' then
s_axi_araddr <= MDIO_RX_DATA(11 downto 0);
else
s_axi_araddr <= addr(11 downto 0);
end if;
s_axi_arvalid_int <= '1';
if s_axi_arready = '1' and s_axi_arvalid_int = '1' then
axi_status(0) <= '1';
s_axi_araddr <= (others => '0');
s_axi_arvalid_int <= '0';
end if;
end if;
else
axi_status(0) <= '0';
s_axi_araddr <= (others => '0');
s_axi_arvalid_int <= '0';
end if;
end if;
end process read_addr_p;
-- READ DATA/RESP
read_data_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = READ then
if axi_status(1) = '0' then
s_axi_rready_int <= '1';
if s_axi_rvalid = '1' and s_axi_rready_int = '1' then
axi_status(1) <= '1';
s_axi_rready_int <= '0';
axi_rd_data <= s_axi_rdata;
if drive_mdio = '1' and s_axi_rdata(16) = '1' then
mdio_ready <= '1';
end if;
end if;
end if;
else
s_axi_rready_int <= '0';
axi_status(1) <= '0';
if axi_access_sm = IDLE_A and (start_access = '1' or start_mdio = '1') then
mdio_ready <= '0';
axi_rd_data <= (others => '0');
end if;
end if;
end if;
end process read_data_p;
-- WRITE ADDR
write_addr_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = WRITE then
if axi_status(2) = '0' then
if drive_mdio = '1' then
if mdio_access_sm = SET_DATA then
s_axi_awaddr <= MDIO_TX_DATA(11 downto 0);
else
s_axi_awaddr <= MDIO_CONTROL(11 downto 0);
end if;
else
s_axi_awaddr <= addr(11 downto 0);
end if;
s_axi_awvalid_int <= '1';
if s_axi_awready = '1' and s_axi_awvalid_int = '1' then
axi_status(2) <= '1';
s_axi_awaddr <= (others => '0');
s_axi_awvalid_int <= '0';
end if;
end if;
else
s_axi_awaddr <= (others => '0');
s_axi_awvalid_int <= '0';
axi_status(2) <= '0';
end if;
end if;
end process write_addr_p;
-- WRITE DATA
write_data_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = WRITE then
if axi_status(3) = '0' then
if drive_mdio = '1' then
s_axi_wdata <= mdio_wr_data;
else
s_axi_wdata <= axi_wr_data;
end if;
s_axi_wvalid_int <= '1';
if s_axi_wready = '1' and s_axi_wvalid_int = '1' then
axi_status(3) <= '1';
s_axi_wdata <= (others => '0');
s_axi_wvalid_int <= '0';
end if;
end if;
else
s_axi_wdata <= (others => '0');
s_axi_wvalid_int <= '0';
axi_status(3) <= '0';
end if;
end if;
end process write_data_p;
-- WRITE RESP
write_resp_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = WRITE then
if axi_status(4) = '0' then
s_axi_bready_int <= '1';
if s_axi_bvalid = '1' and s_axi_bready_int = '1' then
axi_status(4) <= '1';
s_axi_bready_int <= '0';
end if;
end if;
else
s_axi_bready_int <= '0';
axi_status(4) <= '0';
end if;
end if;
end process write_resp_p;
shift_command : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if load_data = '1' then
serial_command_shift <= serial_command_shift(35 downto 33) & axi_rd_data & serial_command_shift(0) & serial_command;
else
serial_command_shift <= serial_command_shift(35 downto 0) & serial_command;
end if;
end if;
end process shift_command;
serial_response <= serial_command_shift(34) when axi_state = CHECK_SPEED else '1';
-- the serial command is expected to have a start and stop bit - to avoid a counter -
-- and a two bit code field in the uppper two bits.
-- these decode as follows:
-- 00 - read address
-- 01 - write address
-- 10 - write data
-- 11 - read data - slightly more involved - when detected the read data is registered into the shift and passed out
-- 11 is used for read data as if the input is tied high the output will simply reflect whatever was
-- captured but will not result in any activity
-- it is expected that the write data is setup BEFORE the write address
shift_decode : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
load_data <= '0';
capture_data <= '0';
write_access <= '0';
read_access <= '0';
if serial_command_shift(36) = '0' and serial_command_shift(35) = '1' and serial_command_shift(0) = '1' then
if serial_command_shift(34) = '1' and serial_command_shift(33) = '1' then
load_data <= '1';
elsif serial_command_shift(34) = '1' and serial_command_shift(33) = '0' then
capture_data <= '1';
elsif serial_command_shift(34) = '0' and serial_command_shift(33) = '1' then
write_access <= '1';
else
read_access <= '1';
end if;
end if;
end if;
end process shift_decode;
-- don't reset this - it will always be updated before it is used..
-- it does need an init value (all ones)
-- Create fully synchronous reset in the s_axi clock domain.
gen_count : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
count_shift <= count_shift(19 downto 0) & s_axi_reset;
end if;
end process gen_count;
end rtl;
|
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_axi_lite_sm.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: This module is reponsible for bringing up both the MAC and the
-- attached PHY (if any) to enable basic packet transfer in both directions.
-- It is intended to be directly usable on a xilinx demo platform to demonstrate
-- simple bring up and data transfer. The mac speed is set via inputs (which
-- can be connected to dip switches) and the PHY is configured to ONLY advertise
-- the specified speed. To maximise compatibility on boards only IEEE registers
-- are used and the PHY address can be set via a parameter.
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity config_mac_phy_sm is
port (
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
phy_interrupt_n : in std_logic;
mac_interrupt : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_command : in std_logic;
serial_response : out std_logic;
debug0_sig : out std_logic;
debug1_sig : out std_logic;
debug2_sig : out std_logic;
debug3_sig : out std_logic;
s_axi_awaddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_awvalid : out std_logic := '0';
s_axi_awready : in std_logic := '0';
s_axi_wdata : out std_logic_vector(31 downto 0) := (others => '0');
s_axi_wvalid : out std_logic := '0';
s_axi_wready : in std_logic := '0';
s_axi_bresp : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_bvalid : in std_logic := '0';
s_axi_bready : out std_logic := '0';
s_axi_araddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_arvalid : out std_logic := '0';
s_axi_arready : in std_logic := '0';
s_axi_rdata : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_rresp : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_rvalid : in std_logic := '0';
s_axi_rready : out std_logic := '0'
);
end config_mac_phy_sm;
architecture rtl of config_mac_phy_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
component aeg_design_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
-- main state machine
-- Encoded main state machine states.
type state_typ is (STARTUP,
-- CHANGE_SPEED, -- not necessary, check phy first
-- MDIO_SET_INTERRUPT,
-- MDIO_READ_INTERRUPT,
MDIO_RESTART, -- restart and autoneg
MDIO_STATS, -- polling for autoneg
MDIO_STATS_POLL_CHECK, -- polling for autoneg, replace with interrupt
MDIO_READ_INTERRUPT2,
MDIO_READ_SPEED,
MDIO_READ_SPEED_POLL,
MAC_UPDATE_SPEED100,
MAC_UPDATE_SPEED1000,
CHECK_SPEED); -- waiting for a speed update
-- MDIO State machine
type mdio_state_typ is (IDLE,
SET_DATA,
INIT,
POLL);
-- AXI State Machine
type axi_state_typ is (IDLE_A,
READ,
WRITE,
DONE);
-- Management configuration register address (0x500)
constant CONFIG_MANAGEMENT_ADD : std_logic_vector(16 downto 0) := "00000" & X"500";
-- Receiver configuration register address (0x4040)
constant RECEIVER_ADD : std_logic_vector(16 downto 0) := "00000" & X"404";
-- Transmitter configuration register address (0x4080)
constant TRANSMITTER_ADD : std_logic_vector(16 downto 0) :="00000" & X"408";
-- Speed configuration register address (0x410)
constant SPEED_CONFIG_ADD : std_logic_vector(16 downto 0) :="00000" & X"410";
-- MDIO registers
constant MDIO_CONTROL : std_logic_vector(16 downto 0) := "00000" & X"504";
constant MDIO_TX_DATA : std_logic_vector(16 downto 0) := "00000" & X"508";
constant MDIO_RX_DATA : std_logic_vector(16 downto 0) := "00000" & X"50C";
constant MDIO_OP_RD : std_logic_vector(1 downto 0) := "10";
constant MDIO_OP_WR : std_logic_vector(1 downto 0) := "01";
-- PHY Registers
-- phy address is actually a 6 bit field but other bits are reserved so simpler to specify as 8 bit
--constant PHY_ADDR : std_logic_vector(7 downto 0) := X"07";
constant PHY_ADDR : std_logic_vector(7 downto 0) := X"00";
constant PHY_CONTROL_REG : std_logic_vector(7 downto 0) := X"00";
constant PHY_STATUS_REG : std_logic_vector(7 downto 0) := X"01";
constant PHY_ABILITY_REG : std_logic_vector(7 downto 0) := X"04";
constant PHY_1000BASET_CONTROL_REG : std_logic_vector(7 downto 0) := X"09";
constant PHY_1000BASET_STATUS_REG : std_logic_vector(7 downto 0) := X"0A";
constant PHY_INTERRUPT_REG : std_logic_vector(7 downto 0) := X"12";
constant PHY_CLEAR_INTERRUPT_REG : std_logic_vector(7 downto 0) := X"13";
---------------------------------------------------
-- Signal declarations
signal axi_status : std_logic_vector(4 downto 0); -- used to keep track of axi transactions
signal mdio_ready : std_logic := '0'; -- captured to acknowledge the end of mdio transactions
signal axi_rd_data : std_logic_vector(31 downto 0) := (others => '0');
signal axi_wr_data : std_logic_vector(31 downto 0);
signal mdio_wr_data : std_logic_vector(31 downto 0) := (others => '0');
signal axi_state : state_typ; -- main state machine to configure example design
signal mdio_access_sm : mdio_state_typ; -- mdio state machine to handle mdio register config
signal axi_access_sm : axi_state_typ; -- axi state machine - handles the 5 channels
signal start_access : std_logic; -- used to kick the axi acees state machine
signal start_mdio : std_logic; -- used to kick the mdio state machine
signal drive_mdio : std_logic; -- selects between mdio fields and direct sm control
signal mdio_op : std_logic_vector(1 downto 0);
signal mdio_reg_addr : std_logic_vector(7 downto 0);
signal writenread : std_logic;
signal addr : std_logic_vector(16 downto 0);
signal speed : std_logic_vector(1 downto 0);
signal update_speed_sync : std_logic;
signal update_speed_reg : std_logic;
signal count_shift : std_logic_vector(20 downto 0) := (others => '1');
-- to avoid logic being stripped a serial input is included which enables an address/data and
-- control to be setup for a user config access..
signal serial_command_shift : std_logic_vector(36 downto 0);
signal load_data : std_logic;
signal capture_data : std_logic;
signal write_access : std_logic;
signal read_access : std_logic;
signal s_axi_reset : std_logic;
signal s_axi_awvalid_int : std_logic;
signal s_axi_wvalid_int : std_logic;
signal s_axi_bready_int : std_logic;
signal s_axi_arvalid_int : std_logic;
signal s_axi_rready_int : std_logic;
--attribute mark_debug : string;
--attribute mark_debug of axi_status : signal is "true";
--attribute mark_debug of mdio_ready : signal is "true";
--attribute mark_debug of axi_rd_data : signal is "true";
--attribute mark_debug of axi_wr_data : signal is "true";
--attribute mark_debug of mdio_wr_data : signal is "true";
--attribute mark_debug of axi_state : signal is "true";
--attribute mark_debug of mdio_access_sm : signal is "true";
--attribute mark_debug of axi_access_sm : signal is "true";
--attribute mark_debug of start_access : signal is "true";
--attribute mark_debug of start_mdio : signal is "true";
--attribute mark_debug of drive_mdio : signal is "true";
--attribute mark_debug of mdio_op : signal is "true";
--attribute mark_debug of mdio_reg_addr : signal is "true";
--attribute mark_debug of writenread : signal is "true";
--attribute mark_debug of addr : signal is "true";
--attribute mark_debug of speed : signal is "true";
--attribute mark_debug of update_speed_sync : signal is "true";
--attribute mark_debug of update_speed_reg : signal is "true";
--attribute mark_debug of count_shift : signal is "true";
--attribute mark_debug of s_axi_aclk : signal is "true";
--attribute mark_debug of s_axi_resetn : signal is "true";
--attribute mark_debug of phy_interrupt_n : signal is "true";
--attribute mark_debug of mac_interrupt : signal is "true";
--attribute mark_debug of s_axi_awaddr : signal is "true";
--attribute mark_debug of s_axi_awvalid : signal is "true";
--attribute mark_debug of s_axi_awready : signal is "true";
--attribute mark_debug of s_axi_wdata : signal is "true";
--attribute mark_debug of s_axi_wvalid : signal is "true";
--attribute mark_debug of s_axi_wready : signal is "true";
--attribute mark_debug of s_axi_bresp : signal is "true";
--attribute mark_debug of s_axi_bvalid : signal is "true";
--attribute mark_debug of s_axi_bready : signal is "true";
--attribute mark_debug of s_axi_araddr : signal is "true";
--attribute mark_debug of s_axi_arvalid : signal is "true";
--attribute mark_debug of s_axi_arready : signal is "true";
--attribute mark_debug of s_axi_rdata : signal is "true";
--attribute mark_debug of s_axi_rresp : signal is "true";
--attribute mark_debug of s_axi_rvalid : signal is "true";
--attribute mark_debug of s_axi_rready : signal is "true";
begin
s_axi_awvalid <= s_axi_awvalid_int;
s_axi_wvalid <= s_axi_wvalid_int;
s_axi_bready <= s_axi_bready_int;
s_axi_arvalid <= s_axi_arvalid_int;
s_axi_rready <= s_axi_rready_int;
s_axi_reset <= not s_axi_resetn;
update_speed_sync <= update_speed;
update_reg : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
update_speed_reg <= '0';
else
update_speed_reg <= update_speed_sync;
end if;
end if;
end process update_reg;
-----------------------------------------------------------------------------
-- Management process. This process sets up the configuration by
-- turning off flow control, then checks gathered statistics at the
-- end of transmission
-----------------------------------------------------------------------------
gen_state : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
axi_state <= STARTUP;
start_access <= '0';
start_mdio <= '0';
drive_mdio <= '0';
mdio_op <= (others => '0');
mdio_reg_addr <= (others => '0');
writenread <= '0';
addr <= (others => '0');
axi_wr_data <= (others => '0');
speed <= mac_speed;
debug0_sig <= '0';
debug1_sig <= '0';
debug2_sig <= '0';
debug3_sig <= '0';
-- main state machine is kicking off multi cycle accesses in each state so has to
-- stall while they take place
elsif axi_access_sm = IDLE_A and mdio_access_sm = IDLE and start_access = '0' and start_mdio = '0' then
case axi_state is
when STARTUP =>
-- this state will be ran after reset to wait for count_shift
if (count_shift(20) = '0') then
-- set up MDC frequency. Write to Management configuration
-- register. This will enable MDIO and set MDC to 2.5MHz
speed <= mac_speed;
assert false
report "Setting MDC Frequency to 2.5MHz...." & cr
severity note;
start_mdio <= '0';
drive_mdio <= '0';
start_access <= '1';
writenread <= '1';
addr <= CONFIG_MANAGEMENT_ADD;
--axi_wr_data <= X"00000053"; -- this is 2.5 MHz
axi_wr_data <= X"00000068";
axi_state <= MDIO_RESTART;
end if;
-- when SET_PHY_SPEEDS => -- not needed, MAC and PHY support both 10M - 1G defaultly
-- when MDIO_SET_INTERRUPT =>
-- debug0_sig <= '1';
-- -- set auto-negotiation interrupt
-- assert false
-- report "Setting Auto-Negotiation-Completed interrupt" & cr
-- severity note;
-- drive_mdio <= '1';
-- start_mdio <= '1';
-- start_access <= '0';
-- writenread <= '0';
-- mdio_reg_addr <= PHY_INTERRUPT_REG;
-- mdio_op <= MDIO_OP_WR;
-- axi_wr_data <= X"00000800"; -- bit 11 for auto-negotiation completed, bit 14 for speed changed
-- axi_state <= MDIO_READ_INTERRUPT;
-- when MDIO_READ_INTERRUPT =>
-- drive_mdio <= '1';
-- start_mdio <= '1';
-- start_access <= '0';
-- writenread <= '0';
-- assert false
-- report "Read interrupt" & cr
-- severity note;
-- mdio_reg_addr <= PHY_INTERRUPT_REG;
-- mdio_op <= MDIO_OP_RD;
-- axi_state <= MDIO_RESTART;
when MDIO_RESTART =>
if axi_rd_data = X"00010800" then
debug1_sig <= '1';
end if;
-- set autoneg and reset
-- if loopback is selected then do not set autonegotiate and program the required speed directly
-- otherwise set autonegotiate
assert false
report "Applying PHY software reset" & cr
severity note;
drive_mdio <= '1';
start_mdio <= '1';
start_access <= '0';
writenread <= '0';
mdio_reg_addr <= PHY_CONTROL_REG;
mdio_op <= MDIO_OP_WR;
--axi_wr_data <= X"0000" & X"9" & X"000";
axi_wr_data <= X"00009000";
axi_state <= MDIO_STATS;
when MDIO_STATS =>
drive_mdio <= '1';
start_mdio <= '1';
start_access <= '0';
writenread <= '0';
assert false
report "Wait for Autonegotiation to complete" & cr
severity note;
mdio_reg_addr <= PHY_STATUS_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_STATS_POLL_CHECK;
when MDIO_STATS_POLL_CHECK =>
-- bit 5 is autoneg complete - assume required speed is selected
if axi_rd_data(5) = '1' then
axi_state <= MDIO_READ_INTERRUPT2;
-- axi_state <= CHECK_SPEED;
else
axi_state <= MDIO_STATS;
end if;
when MDIO_READ_INTERRUPT2 =>
drive_mdio <= '1';
start_mdio <= '1';
start_access <= '0';
writenread <= '0';
assert false
report "Read interrupt" & cr
severity note;
mdio_reg_addr <= PHY_INTERRUPT_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_READ_SPEED;
when MDIO_READ_SPEED =>
drive_mdio <= '1';
start_mdio <= '1';
start_access <= '0';
writenread <= '0';
assert false
report "Read negotiated speed" & cr
severity note;
mdio_reg_addr <= PHY_1000BASET_STATUS_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_READ_SPEED_POLL;
when MDIO_READ_SPEED_POLL =>
if axi_rd_data(11) = '1' then -- link partner 1G capable
axi_state <= MAC_UPDATE_SPEED1000;
debug2_sig <= '1';
else
axi_state <= MAC_UPDATE_SPEED100;
debug2_sig <= '0';
end if;
when MAC_UPDATE_SPEED100 =>
assert false
report "Programming MAC speed 100" & cr
severity note;
drive_mdio <= '0';
start_mdio <= '0';
start_access <= '1';
writenread <= '1';
addr <= SPEED_CONFIG_ADD;
-- bits 31:30 are used
axi_wr_data <= "01" & X"0000000" & "00";
axi_state <= CHECK_SPEED;
when MAC_UPDATE_SPEED1000 =>
assert false
report "Programming MAC speed 1000" & cr
severity note;
drive_mdio <= '0';
start_mdio <= '0';
start_access <= '1';
writenread <= '1';
addr <= SPEED_CONFIG_ADD;
-- bits 31:30 are used
axi_wr_data <= "10" & X"0000000" & "00";
axi_state <= CHECK_SPEED;
when CHECK_SPEED =>
debug3_sig <= '1';
if update_speed_reg = '1' then
--axi_state <= CHANGE_SPEED;
axi_state <= STARTUP;
else
if capture_data = '1' then
axi_wr_data <= serial_command_shift(33 downto 2);
end if;
if write_access = '1' or read_access = '1' then
addr <= "00000" & serial_command_shift (13 downto 2);
start_access <= '1';
writenread <= write_access;
end if;
end if;
when others =>
axi_state <= STARTUP;
end case;
else
start_access <= '0';
start_mdio <= '0';
end if;
end if;
end process gen_state;
--------------------------------------------------
-- MDIO setup - split from main state machine to make more manageable
gen_mdio_state : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
mdio_access_sm <= IDLE;
elsif axi_access_sm = IDLE_A or axi_access_sm = DONE then
case mdio_access_sm is
when IDLE =>
if start_mdio = '1' then
if mdio_op = MDIO_OP_WR then
mdio_access_sm <= SET_DATA;
mdio_wr_data <= axi_wr_data;
else
mdio_access_sm <= INIT;
mdio_wr_data <= PHY_ADDR & mdio_reg_addr & mdio_op & "001" & "00000000000";
end if;
end if;
when SET_DATA =>
mdio_access_sm <= INIT;
mdio_wr_data <= PHY_ADDR & mdio_reg_addr & mdio_op & "001" & "00000000000";
when INIT =>
mdio_access_sm <= POLL;
when POLL =>
if mdio_ready = '1' then
mdio_access_sm <= IDLE;
end if;
end case;
elsif mdio_access_sm = POLL and mdio_ready = '1' then
mdio_access_sm <= IDLE;
end if;
end if;
end process gen_mdio_state;
---------------------------------------------------------------------------------------------
-- processes to generate the axi transactions - only simple reads and write can be generated
gen_axi_state : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
axi_access_sm <= IDLE_A;
else
case axi_access_sm is
when IDLE_A =>
if start_access = '1' or start_mdio = '1' or mdio_access_sm /= IDLE then
if mdio_access_sm = POLL then
axi_access_sm <= READ;
elsif (start_access = '1' and writenread = '1') or
(start_mdio = '1' or mdio_access_sm = SET_DATA or mdio_access_sm = INIT) then
axi_access_sm <= WRITE;
else
axi_access_sm <= READ;
end if;
end if;
when WRITE =>
-- wait in this state until axi_status signals the write is complete
if axi_status(4 downto 2) = "111" then
axi_access_sm <= DONE;
end if;
when READ =>
-- wait in this state until axi_status signals the read is complete
if axi_status(1 downto 0) = "11" then
axi_access_sm <= DONE;
end if;
when DONE =>
axi_access_sm <= IDLE_A;
end case;
end if;
end if;
end process gen_axi_state;
-- need a process per axi interface (i.e 5)
-- in each case the interface is driven accordingly and once acknowledged a sticky
-- status bit is set and the process waits until the access_sm moves on
-- READ ADDR
read_addr_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = READ then
if axi_status(0) = '0' then
if drive_mdio = '1' then
s_axi_araddr <= MDIO_RX_DATA(11 downto 0);
else
s_axi_araddr <= addr(11 downto 0);
end if;
s_axi_arvalid_int <= '1';
if s_axi_arready = '1' and s_axi_arvalid_int = '1' then
axi_status(0) <= '1';
s_axi_araddr <= (others => '0');
s_axi_arvalid_int <= '0';
end if;
end if;
else
axi_status(0) <= '0';
s_axi_araddr <= (others => '0');
s_axi_arvalid_int <= '0';
end if;
end if;
end process read_addr_p;
-- READ DATA/RESP
read_data_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = READ then
if axi_status(1) = '0' then
s_axi_rready_int <= '1';
if s_axi_rvalid = '1' and s_axi_rready_int = '1' then
axi_status(1) <= '1';
s_axi_rready_int <= '0';
axi_rd_data <= s_axi_rdata;
if drive_mdio = '1' and s_axi_rdata(16) = '1' then
mdio_ready <= '1';
end if;
end if;
end if;
else
s_axi_rready_int <= '0';
axi_status(1) <= '0';
if axi_access_sm = IDLE_A and (start_access = '1' or start_mdio = '1') then
mdio_ready <= '0';
axi_rd_data <= (others => '0');
end if;
end if;
end if;
end process read_data_p;
-- WRITE ADDR
write_addr_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = WRITE then
if axi_status(2) = '0' then
if drive_mdio = '1' then
if mdio_access_sm = SET_DATA then
s_axi_awaddr <= MDIO_TX_DATA(11 downto 0);
else
s_axi_awaddr <= MDIO_CONTROL(11 downto 0);
end if;
else
s_axi_awaddr <= addr(11 downto 0);
end if;
s_axi_awvalid_int <= '1';
if s_axi_awready = '1' and s_axi_awvalid_int = '1' then
axi_status(2) <= '1';
s_axi_awaddr <= (others => '0');
s_axi_awvalid_int <= '0';
end if;
end if;
else
s_axi_awaddr <= (others => '0');
s_axi_awvalid_int <= '0';
axi_status(2) <= '0';
end if;
end if;
end process write_addr_p;
-- WRITE DATA
write_data_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = WRITE then
if axi_status(3) = '0' then
if drive_mdio = '1' then
s_axi_wdata <= mdio_wr_data;
else
s_axi_wdata <= axi_wr_data;
end if;
s_axi_wvalid_int <= '1';
if s_axi_wready = '1' and s_axi_wvalid_int = '1' then
axi_status(3) <= '1';
s_axi_wdata <= (others => '0');
s_axi_wvalid_int <= '0';
end if;
end if;
else
s_axi_wdata <= (others => '0');
s_axi_wvalid_int <= '0';
axi_status(3) <= '0';
end if;
end if;
end process write_data_p;
-- WRITE RESP
write_resp_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = WRITE then
if axi_status(4) = '0' then
s_axi_bready_int <= '1';
if s_axi_bvalid = '1' and s_axi_bready_int = '1' then
axi_status(4) <= '1';
s_axi_bready_int <= '0';
end if;
end if;
else
s_axi_bready_int <= '0';
axi_status(4) <= '0';
end if;
end if;
end process write_resp_p;
shift_command : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if load_data = '1' then
serial_command_shift <= serial_command_shift(35 downto 33) & axi_rd_data & serial_command_shift(0) & serial_command;
else
serial_command_shift <= serial_command_shift(35 downto 0) & serial_command;
end if;
end if;
end process shift_command;
serial_response <= serial_command_shift(34) when axi_state = CHECK_SPEED else '1';
-- the serial command is expected to have a start and stop bit - to avoid a counter -
-- and a two bit code field in the uppper two bits.
-- these decode as follows:
-- 00 - read address
-- 01 - write address
-- 10 - write data
-- 11 - read data - slightly more involved - when detected the read data is registered into the shift and passed out
-- 11 is used for read data as if the input is tied high the output will simply reflect whatever was
-- captured but will not result in any activity
-- it is expected that the write data is setup BEFORE the write address
shift_decode : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
load_data <= '0';
capture_data <= '0';
write_access <= '0';
read_access <= '0';
if serial_command_shift(36) = '0' and serial_command_shift(35) = '1' and serial_command_shift(0) = '1' then
if serial_command_shift(34) = '1' and serial_command_shift(33) = '1' then
load_data <= '1';
elsif serial_command_shift(34) = '1' and serial_command_shift(33) = '0' then
capture_data <= '1';
elsif serial_command_shift(34) = '0' and serial_command_shift(33) = '1' then
write_access <= '1';
else
read_access <= '1';
end if;
end if;
end if;
end process shift_decode;
-- don't reset this - it will always be updated before it is used..
-- it does need an init value (all ones)
-- Create fully synchronous reset in the s_axi clock domain.
gen_count : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
count_shift <= count_shift(19 downto 0) & s_axi_reset;
end if;
end process gen_count;
end rtl;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity array_sum is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
array_r_address0 : OUT STD_LOGIC_VECTOR (5 downto 0);
array_r_ce0 : OUT STD_LOGIC;
array_r_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
array_r_address1 : OUT STD_LOGIC_VECTOR (5 downto 0);
array_r_ce1 : OUT STD_LOGIC;
array_r_q1 : IN STD_LOGIC_VECTOR (31 downto 0);
length_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of array_sum is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"array_sum,hls_ip_2015_4,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7vx690tffg1761-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.820000,HLS_SYN_LAT=33,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=386,HLS_SYN_LUT=372}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000100000000000000000";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000001000000000000000000";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000010000000000000000000";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000100000000000000000000";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000001000000000000000000000";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000010000000000000000000000";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000100000000000000000000000";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (33 downto 0) := "0000000001000000000000000000000000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (33 downto 0) := "0000000010000000000000000000000000";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (33 downto 0) := "0000000100000000000000000000000000";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (33 downto 0) := "0000001000000000000000000000000000";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (33 downto 0) := "0000010000000000000000000000000000";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (33 downto 0) := "0000100000000000000000000000000000";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (33 downto 0) := "0001000000000000000000000000000000";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (33 downto 0) := "0010000000000000000000000000000000";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (33 downto 0) := "0100000000000000000000000000000000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (33 downto 0) := "1000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv64_2 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010";
constant ap_const_lv64_3 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000011";
constant ap_const_lv64_4 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100";
constant ap_const_lv64_5 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000101";
constant ap_const_lv64_6 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000110";
constant ap_const_lv64_7 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000111";
constant ap_const_lv64_8 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000";
constant ap_const_lv64_9 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001001";
constant ap_const_lv64_A : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001010";
constant ap_const_lv64_B : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001011";
constant ap_const_lv64_C : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001100";
constant ap_const_lv64_D : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001101";
constant ap_const_lv64_E : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001110";
constant ap_const_lv64_F : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001111";
constant ap_const_lv64_10 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000";
constant ap_const_lv64_11 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010001";
constant ap_const_lv64_12 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010010";
constant ap_const_lv64_13 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010011";
constant ap_const_lv64_14 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010100";
constant ap_const_lv64_15 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010101";
constant ap_const_lv64_16 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010110";
constant ap_const_lv64_17 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010111";
constant ap_const_lv64_18 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011000";
constant ap_const_lv64_19 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011001";
constant ap_const_lv64_1A : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011010";
constant ap_const_lv64_1B : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011011";
constant ap_const_lv64_1C : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011100";
constant ap_const_lv64_1D : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011101";
constant ap_const_lv64_1E : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011110";
constant ap_const_lv64_1F : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011111";
constant ap_const_lv64_20 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100000";
constant ap_const_lv64_21 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100001";
constant ap_const_lv64_22 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100010";
constant ap_const_lv64_23 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100011";
constant ap_const_lv64_24 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100100";
constant ap_const_lv64_25 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100101";
constant ap_const_lv64_26 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100110";
constant ap_const_lv64_27 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100111";
constant ap_const_lv64_28 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000101000";
constant ap_const_lv64_29 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000101001";
constant ap_const_lv64_2A : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000101010";
constant ap_const_lv64_2B : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000101011";
constant ap_const_lv64_2C : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000101100";
constant ap_const_lv64_2D : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000101101";
constant ap_const_lv64_2E : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000101110";
constant ap_const_lv64_2F : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000101111";
constant ap_const_lv64_30 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000110000";
constant ap_const_lv64_31 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000110001";
constant ap_const_lv64_32 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000110010";
constant ap_const_lv64_33 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000110011";
constant ap_const_lv64_34 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000110100";
constant ap_const_lv64_35 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000110101";
constant ap_const_lv64_36 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000110110";
constant ap_const_lv64_37 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000110111";
constant ap_const_lv64_38 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000111000";
constant ap_const_lv64_39 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000111001";
constant ap_const_lv64_3A : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000111010";
constant ap_const_lv64_3B : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000111011";
constant ap_const_lv64_3C : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000111100";
constant ap_const_lv64_3D : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000111101";
constant ap_const_lv64_3E : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000111110";
constant ap_const_lv64_3F : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000111111";
constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_50 : BOOLEAN;
signal reg_729 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_74 : BOOLEAN;
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_81 : BOOLEAN;
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_89 : BOOLEAN;
signal ap_sig_cseq_ST_st10_fsm_9 : STD_LOGIC;
signal ap_sig_bdd_97 : BOOLEAN;
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_105 : BOOLEAN;
signal ap_sig_cseq_ST_st16_fsm_15 : STD_LOGIC;
signal ap_sig_bdd_113 : BOOLEAN;
signal ap_sig_cseq_ST_st20_fsm_19 : STD_LOGIC;
signal ap_sig_bdd_121 : BOOLEAN;
signal ap_sig_cseq_ST_st24_fsm_23 : STD_LOGIC;
signal ap_sig_bdd_129 : BOOLEAN;
signal ap_sig_cseq_ST_st26_fsm_25 : STD_LOGIC;
signal ap_sig_bdd_137 : BOOLEAN;
signal ap_sig_cseq_ST_st28_fsm_27 : STD_LOGIC;
signal ap_sig_bdd_145 : BOOLEAN;
signal ap_sig_cseq_ST_st32_fsm_31 : STD_LOGIC;
signal ap_sig_bdd_153 : BOOLEAN;
signal reg_733 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_723_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_737 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_164 : BOOLEAN;
signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC;
signal ap_sig_bdd_171 : BOOLEAN;
signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC;
signal ap_sig_bdd_179 : BOOLEAN;
signal ap_sig_cseq_ST_st22_fsm_21 : STD_LOGIC;
signal ap_sig_bdd_187 : BOOLEAN;
signal ap_sig_cseq_ST_st30_fsm_29 : STD_LOGIC;
signal ap_sig_bdd_195 : BOOLEAN;
signal reg_741 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_204 : BOOLEAN;
signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC;
signal ap_sig_bdd_211 : BOOLEAN;
signal ap_sig_cseq_ST_st19_fsm_18 : STD_LOGIC;
signal ap_sig_bdd_219 : BOOLEAN;
signal ap_sig_cseq_ST_st23_fsm_22 : STD_LOGIC;
signal ap_sig_bdd_227 : BOOLEAN;
signal ap_sig_cseq_ST_st31_fsm_30 : STD_LOGIC;
signal ap_sig_bdd_235 : BOOLEAN;
signal grp_fu_751_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_769 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_245 : BOOLEAN;
signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC;
signal ap_sig_bdd_252 : BOOLEAN;
signal ap_sig_cseq_ST_st27_fsm_26 : STD_LOGIC;
signal ap_sig_bdd_260 : BOOLEAN;
signal reg_773 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_269 : BOOLEAN;
signal ap_sig_cseq_ST_st13_fsm_12 : STD_LOGIC;
signal ap_sig_bdd_276 : BOOLEAN;
signal ap_sig_cseq_ST_st29_fsm_28 : STD_LOGIC;
signal ap_sig_bdd_284 : BOOLEAN;
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_bdd_329 : BOOLEAN;
signal grp_fu_783_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp1_reg_898 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC;
signal ap_sig_bdd_370 : BOOLEAN;
signal tmp16_reg_983 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st21_fsm_20 : STD_LOGIC;
signal ap_sig_bdd_394 : BOOLEAN;
signal grp_fu_763_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp33_reg_1028 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st25_fsm_24 : STD_LOGIC;
signal ap_sig_bdd_419 : BOOLEAN;
signal tmp40_reg_1073 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp47_reg_1148 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st33_fsm_32 : STD_LOGIC;
signal ap_sig_bdd_458 : BOOLEAN;
signal grp_fu_745_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_757_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_777_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st34_fsm_33 : STD_LOGIC;
signal ap_sig_bdd_613 : BOOLEAN;
signal tmp32_fu_793_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp31_fu_797_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_789_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (33 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9) or (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15) or (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19) or (ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) or (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25) or (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27) or (ap_const_logic_1 = ap_sig_cseq_ST_st32_fsm_31))) then
reg_729 <= array_r_q0;
reg_733 <= array_r_q1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) or (ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21) or (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29))) then
reg_737 <= grp_fu_723_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) or (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or (ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22) or (ap_const_logic_1 = ap_sig_cseq_ST_st31_fsm_30))) then
reg_741 <= grp_fu_723_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or (ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10) or (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26))) then
reg_769 <= grp_fu_751_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) or (ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) or (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28))) then
reg_773 <= grp_fu_751_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then
tmp16_reg_983 <= grp_fu_783_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
tmp1_reg_898 <= grp_fu_783_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20)) then
tmp33_reg_1028 <= grp_fu_763_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24)) then
tmp40_reg_1073 <= grp_fu_763_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st33_fsm_32)) then
tmp47_reg_1148 <= grp_fu_783_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_sig_cseq_ST_st34_fsm_33)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st34_fsm_33)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st34_fsm_33)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st34_fsm_33)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= std_logic_vector(unsigned(tmp31_fu_797_p2) + unsigned(tmp_fu_789_p2));
-- ap_sig_bdd_105 assign process. --
ap_sig_bdd_105_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_105 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_113 assign process. --
ap_sig_bdd_113_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_113 <= (ap_const_lv1_1 = ap_CS_fsm(15 downto 15));
end process;
-- ap_sig_bdd_121 assign process. --
ap_sig_bdd_121_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_121 <= (ap_const_lv1_1 = ap_CS_fsm(19 downto 19));
end process;
-- ap_sig_bdd_129 assign process. --
ap_sig_bdd_129_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_129 <= (ap_const_lv1_1 = ap_CS_fsm(23 downto 23));
end process;
-- ap_sig_bdd_137 assign process. --
ap_sig_bdd_137_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_137 <= (ap_const_lv1_1 = ap_CS_fsm(25 downto 25));
end process;
-- ap_sig_bdd_145 assign process. --
ap_sig_bdd_145_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_145 <= (ap_const_lv1_1 = ap_CS_fsm(27 downto 27));
end process;
-- ap_sig_bdd_153 assign process. --
ap_sig_bdd_153_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_153 <= (ap_const_lv1_1 = ap_CS_fsm(31 downto 31));
end process;
-- ap_sig_bdd_164 assign process. --
ap_sig_bdd_164_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_164 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_171 assign process. --
ap_sig_bdd_171_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_171 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13));
end process;
-- ap_sig_bdd_179 assign process. --
ap_sig_bdd_179_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_179 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17));
end process;
-- ap_sig_bdd_187 assign process. --
ap_sig_bdd_187_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_187 <= (ap_const_lv1_1 = ap_CS_fsm(21 downto 21));
end process;
-- ap_sig_bdd_195 assign process. --
ap_sig_bdd_195_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_195 <= (ap_const_lv1_1 = ap_CS_fsm(29 downto 29));
end process;
-- ap_sig_bdd_204 assign process. --
ap_sig_bdd_204_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_204 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_211 assign process. --
ap_sig_bdd_211_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_211 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14));
end process;
-- ap_sig_bdd_219 assign process. --
ap_sig_bdd_219_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_219 <= (ap_const_lv1_1 = ap_CS_fsm(18 downto 18));
end process;
-- ap_sig_bdd_227 assign process. --
ap_sig_bdd_227_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_227 <= (ap_const_lv1_1 = ap_CS_fsm(22 downto 22));
end process;
-- ap_sig_bdd_235 assign process. --
ap_sig_bdd_235_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_235 <= (ap_const_lv1_1 = ap_CS_fsm(30 downto 30));
end process;
-- ap_sig_bdd_245 assign process. --
ap_sig_bdd_245_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_245 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_252 assign process. --
ap_sig_bdd_252_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_252 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
-- ap_sig_bdd_260 assign process. --
ap_sig_bdd_260_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_260 <= (ap_const_lv1_1 = ap_CS_fsm(26 downto 26));
end process;
-- ap_sig_bdd_269 assign process. --
ap_sig_bdd_269_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_269 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_276 assign process. --
ap_sig_bdd_276_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_276 <= (ap_const_lv1_1 = ap_CS_fsm(12 downto 12));
end process;
-- ap_sig_bdd_284 assign process. --
ap_sig_bdd_284_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_284 <= (ap_const_lv1_1 = ap_CS_fsm(28 downto 28));
end process;
-- ap_sig_bdd_329 assign process. --
ap_sig_bdd_329_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_329 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
-- ap_sig_bdd_370 assign process. --
ap_sig_bdd_370_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_370 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16));
end process;
-- ap_sig_bdd_394 assign process. --
ap_sig_bdd_394_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_394 <= (ap_const_lv1_1 = ap_CS_fsm(20 downto 20));
end process;
-- ap_sig_bdd_419 assign process. --
ap_sig_bdd_419_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_419 <= (ap_const_lv1_1 = ap_CS_fsm(24 downto 24));
end process;
-- ap_sig_bdd_458 assign process. --
ap_sig_bdd_458_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_458 <= (ap_const_lv1_1 = ap_CS_fsm(32 downto 32));
end process;
-- ap_sig_bdd_50 assign process. --
ap_sig_bdd_50_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_50 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_613 assign process. --
ap_sig_bdd_613_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_613 <= (ap_const_lv1_1 = ap_CS_fsm(33 downto 33));
end process;
-- ap_sig_bdd_74 assign process. --
ap_sig_bdd_74_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_74 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_81 assign process. --
ap_sig_bdd_81_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_81 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_89 assign process. --
ap_sig_bdd_89_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_89 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_97 assign process. --
ap_sig_bdd_97_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_97 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
-- ap_sig_cseq_ST_st10_fsm_9 assign process. --
ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_bdd_97)
begin
if (ap_sig_bdd_97) then
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st11_fsm_10 assign process. --
ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_bdd_252)
begin
if (ap_sig_bdd_252) then
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_105)
begin
if (ap_sig_bdd_105) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st13_fsm_12 assign process. --
ap_sig_cseq_ST_st13_fsm_12_assign_proc : process(ap_sig_bdd_276)
begin
if (ap_sig_bdd_276) then
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st14_fsm_13 assign process. --
ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_bdd_171)
begin
if (ap_sig_bdd_171) then
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st15_fsm_14 assign process. --
ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_bdd_211)
begin
if (ap_sig_bdd_211) then
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st16_fsm_15 assign process. --
ap_sig_cseq_ST_st16_fsm_15_assign_proc : process(ap_sig_bdd_113)
begin
if (ap_sig_bdd_113) then
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st17_fsm_16 assign process. --
ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_bdd_370)
begin
if (ap_sig_bdd_370) then
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st18_fsm_17 assign process. --
ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_179)
begin
if (ap_sig_bdd_179) then
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st19_fsm_18 assign process. --
ap_sig_cseq_ST_st19_fsm_18_assign_proc : process(ap_sig_bdd_219)
begin
if (ap_sig_bdd_219) then
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_50)
begin
if (ap_sig_bdd_50) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st20_fsm_19 assign process. --
ap_sig_cseq_ST_st20_fsm_19_assign_proc : process(ap_sig_bdd_121)
begin
if (ap_sig_bdd_121) then
ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st21_fsm_20 assign process. --
ap_sig_cseq_ST_st21_fsm_20_assign_proc : process(ap_sig_bdd_394)
begin
if (ap_sig_bdd_394) then
ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st22_fsm_21 assign process. --
ap_sig_cseq_ST_st22_fsm_21_assign_proc : process(ap_sig_bdd_187)
begin
if (ap_sig_bdd_187) then
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st23_fsm_22 assign process. --
ap_sig_cseq_ST_st23_fsm_22_assign_proc : process(ap_sig_bdd_227)
begin
if (ap_sig_bdd_227) then
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st24_fsm_23 assign process. --
ap_sig_cseq_ST_st24_fsm_23_assign_proc : process(ap_sig_bdd_129)
begin
if (ap_sig_bdd_129) then
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st25_fsm_24 assign process. --
ap_sig_cseq_ST_st25_fsm_24_assign_proc : process(ap_sig_bdd_419)
begin
if (ap_sig_bdd_419) then
ap_sig_cseq_ST_st25_fsm_24 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st25_fsm_24 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st26_fsm_25 assign process. --
ap_sig_cseq_ST_st26_fsm_25_assign_proc : process(ap_sig_bdd_137)
begin
if (ap_sig_bdd_137) then
ap_sig_cseq_ST_st26_fsm_25 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st26_fsm_25 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st27_fsm_26 assign process. --
ap_sig_cseq_ST_st27_fsm_26_assign_proc : process(ap_sig_bdd_260)
begin
if (ap_sig_bdd_260) then
ap_sig_cseq_ST_st27_fsm_26 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st27_fsm_26 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st28_fsm_27 assign process. --
ap_sig_cseq_ST_st28_fsm_27_assign_proc : process(ap_sig_bdd_145)
begin
if (ap_sig_bdd_145) then
ap_sig_cseq_ST_st28_fsm_27 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st28_fsm_27 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st29_fsm_28 assign process. --
ap_sig_cseq_ST_st29_fsm_28_assign_proc : process(ap_sig_bdd_284)
begin
if (ap_sig_bdd_284) then
ap_sig_cseq_ST_st29_fsm_28 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st29_fsm_28 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_74)
begin
if (ap_sig_bdd_74) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st30_fsm_29 assign process. --
ap_sig_cseq_ST_st30_fsm_29_assign_proc : process(ap_sig_bdd_195)
begin
if (ap_sig_bdd_195) then
ap_sig_cseq_ST_st30_fsm_29 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st30_fsm_29 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st31_fsm_30 assign process. --
ap_sig_cseq_ST_st31_fsm_30_assign_proc : process(ap_sig_bdd_235)
begin
if (ap_sig_bdd_235) then
ap_sig_cseq_ST_st31_fsm_30 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st31_fsm_30 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st32_fsm_31 assign process. --
ap_sig_cseq_ST_st32_fsm_31_assign_proc : process(ap_sig_bdd_153)
begin
if (ap_sig_bdd_153) then
ap_sig_cseq_ST_st32_fsm_31 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st32_fsm_31 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st33_fsm_32 assign process. --
ap_sig_cseq_ST_st33_fsm_32_assign_proc : process(ap_sig_bdd_458)
begin
if (ap_sig_bdd_458) then
ap_sig_cseq_ST_st33_fsm_32 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st33_fsm_32 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st34_fsm_33 assign process. --
ap_sig_cseq_ST_st34_fsm_33_assign_proc : process(ap_sig_bdd_613)
begin
if (ap_sig_bdd_613) then
ap_sig_cseq_ST_st34_fsm_33 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st34_fsm_33 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_245)
begin
if (ap_sig_bdd_245) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_81)
begin
if (ap_sig_bdd_81) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_269)
begin
if (ap_sig_bdd_269) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_164)
begin
if (ap_sig_bdd_164) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_204)
begin
if (ap_sig_bdd_204) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_89)
begin
if (ap_sig_bdd_89) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st9_fsm_8 assign process. --
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_329)
begin
if (ap_sig_bdd_329) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
-- array_r_address0 assign process. --
array_r_address0_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st20_fsm_19, ap_sig_cseq_ST_st24_fsm_23, ap_sig_cseq_ST_st26_fsm_25, ap_sig_cseq_ST_st28_fsm_27, ap_sig_cseq_ST_st32_fsm_31, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st22_fsm_21, ap_sig_cseq_ST_st30_fsm_29, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st23_fsm_22, ap_sig_cseq_ST_st31_fsm_30, ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st11_fsm_10, ap_sig_cseq_ST_st27_fsm_26, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st29_fsm_28, ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st17_fsm_16, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st25_fsm_24)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st32_fsm_31)) then
array_r_address0 <= ap_const_lv64_3E(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st31_fsm_30)) then
array_r_address0 <= ap_const_lv64_3C(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)) then
array_r_address0 <= ap_const_lv64_3A(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28)) then
array_r_address0 <= ap_const_lv64_38(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27)) then
array_r_address0 <= ap_const_lv64_36(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) then
array_r_address0 <= ap_const_lv64_34(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25)) then
array_r_address0 <= ap_const_lv64_32(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24)) then
array_r_address0 <= ap_const_lv64_30(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23)) then
array_r_address0 <= ap_const_lv64_2E(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22)) then
array_r_address0 <= ap_const_lv64_2C(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21)) then
array_r_address0 <= ap_const_lv64_2A(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20)) then
array_r_address0 <= ap_const_lv64_28(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19)) then
array_r_address0 <= ap_const_lv64_26(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18)) then
array_r_address0 <= ap_const_lv64_24(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) then
array_r_address0 <= ap_const_lv64_22(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then
array_r_address0 <= ap_const_lv64_20(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) then
array_r_address0 <= ap_const_lv64_1E(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
array_r_address0 <= ap_const_lv64_1C(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then
array_r_address0 <= ap_const_lv64_1A(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12)) then
array_r_address0 <= ap_const_lv64_18(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
array_r_address0 <= ap_const_lv64_16(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) then
array_r_address0 <= ap_const_lv64_14(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) then
array_r_address0 <= ap_const_lv64_12(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
array_r_address0 <= ap_const_lv64_10(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
array_r_address0 <= ap_const_lv64_E(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
array_r_address0 <= ap_const_lv64_C(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then
array_r_address0 <= ap_const_lv64_A(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
array_r_address0 <= ap_const_lv64_8(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
array_r_address0 <= ap_const_lv64_6(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
array_r_address0 <= ap_const_lv64_4(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
array_r_address0 <= ap_const_lv64_2(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) then
array_r_address0 <= ap_const_lv64_0(6 - 1 downto 0);
else
array_r_address0 <= "XXXXXX";
end if;
end process;
-- array_r_address1 assign process. --
array_r_address1_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st20_fsm_19, ap_sig_cseq_ST_st24_fsm_23, ap_sig_cseq_ST_st26_fsm_25, ap_sig_cseq_ST_st28_fsm_27, ap_sig_cseq_ST_st32_fsm_31, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st22_fsm_21, ap_sig_cseq_ST_st30_fsm_29, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st23_fsm_22, ap_sig_cseq_ST_st31_fsm_30, ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st11_fsm_10, ap_sig_cseq_ST_st27_fsm_26, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st29_fsm_28, ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st17_fsm_16, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st25_fsm_24)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st32_fsm_31)) then
array_r_address1 <= ap_const_lv64_3F(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st31_fsm_30)) then
array_r_address1 <= ap_const_lv64_3D(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)) then
array_r_address1 <= ap_const_lv64_3B(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28)) then
array_r_address1 <= ap_const_lv64_39(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27)) then
array_r_address1 <= ap_const_lv64_37(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) then
array_r_address1 <= ap_const_lv64_35(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25)) then
array_r_address1 <= ap_const_lv64_33(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24)) then
array_r_address1 <= ap_const_lv64_31(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23)) then
array_r_address1 <= ap_const_lv64_2F(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22)) then
array_r_address1 <= ap_const_lv64_2D(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21)) then
array_r_address1 <= ap_const_lv64_2B(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20)) then
array_r_address1 <= ap_const_lv64_29(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19)) then
array_r_address1 <= ap_const_lv64_27(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18)) then
array_r_address1 <= ap_const_lv64_25(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) then
array_r_address1 <= ap_const_lv64_23(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then
array_r_address1 <= ap_const_lv64_21(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) then
array_r_address1 <= ap_const_lv64_1F(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
array_r_address1 <= ap_const_lv64_1D(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then
array_r_address1 <= ap_const_lv64_1B(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12)) then
array_r_address1 <= ap_const_lv64_19(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
array_r_address1 <= ap_const_lv64_17(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) then
array_r_address1 <= ap_const_lv64_15(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) then
array_r_address1 <= ap_const_lv64_13(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
array_r_address1 <= ap_const_lv64_11(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
array_r_address1 <= ap_const_lv64_F(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
array_r_address1 <= ap_const_lv64_D(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then
array_r_address1 <= ap_const_lv64_B(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
array_r_address1 <= ap_const_lv64_9(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
array_r_address1 <= ap_const_lv64_7(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
array_r_address1 <= ap_const_lv64_5(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
array_r_address1 <= ap_const_lv64_3(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) then
array_r_address1 <= ap_const_lv64_1(6 - 1 downto 0);
else
array_r_address1 <= "XXXXXX";
end if;
end process;
-- array_r_ce0 assign process. --
array_r_ce0_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st20_fsm_19, ap_sig_cseq_ST_st24_fsm_23, ap_sig_cseq_ST_st26_fsm_25, ap_sig_cseq_ST_st28_fsm_27, ap_sig_cseq_ST_st32_fsm_31, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st22_fsm_21, ap_sig_cseq_ST_st30_fsm_29, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st23_fsm_22, ap_sig_cseq_ST_st31_fsm_30, ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st11_fsm_10, ap_sig_cseq_ST_st27_fsm_26, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st29_fsm_28, ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st17_fsm_16, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st25_fsm_24)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9) or (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15) or (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19) or (ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) or (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25) or (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27) or (ap_const_logic_1 = ap_sig_cseq_ST_st32_fsm_31) or (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) or (ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21) or (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29) or (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) or (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or (ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22) or (ap_const_logic_1 = ap_sig_cseq_ST_st31_fsm_30) or (ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or (ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10) or (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) or (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) or (ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) or (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0))) or (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) or (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16) or (ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20) or (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24))) then
array_r_ce0 <= ap_const_logic_1;
else
array_r_ce0 <= ap_const_logic_0;
end if;
end process;
-- array_r_ce1 assign process. --
array_r_ce1_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st20_fsm_19, ap_sig_cseq_ST_st24_fsm_23, ap_sig_cseq_ST_st26_fsm_25, ap_sig_cseq_ST_st28_fsm_27, ap_sig_cseq_ST_st32_fsm_31, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st22_fsm_21, ap_sig_cseq_ST_st30_fsm_29, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st23_fsm_22, ap_sig_cseq_ST_st31_fsm_30, ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st11_fsm_10, ap_sig_cseq_ST_st27_fsm_26, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st29_fsm_28, ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st17_fsm_16, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st25_fsm_24)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9) or (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15) or (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19) or (ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) or (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25) or (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27) or (ap_const_logic_1 = ap_sig_cseq_ST_st32_fsm_31) or (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) or (ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21) or (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29) or (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) or (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or (ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22) or (ap_const_logic_1 = ap_sig_cseq_ST_st31_fsm_30) or (ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or (ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10) or (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) or (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) or (ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) or (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0))) or (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) or (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16) or (ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20) or (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24))) then
array_r_ce1 <= ap_const_logic_1;
else
array_r_ce1 <= ap_const_logic_0;
end if;
end process;
grp_fu_723_p2 <= std_logic_vector(unsigned(array_r_q0) + unsigned(array_r_q1));
grp_fu_745_p2 <= std_logic_vector(unsigned(reg_729) + unsigned(reg_733));
grp_fu_751_p2 <= std_logic_vector(unsigned(grp_fu_723_p2) + unsigned(grp_fu_745_p2));
grp_fu_757_p2 <= std_logic_vector(unsigned(reg_741) + unsigned(reg_737));
grp_fu_763_p2 <= std_logic_vector(unsigned(grp_fu_751_p2) + unsigned(grp_fu_757_p2));
grp_fu_777_p2 <= std_logic_vector(unsigned(reg_773) + unsigned(reg_769));
grp_fu_783_p2 <= std_logic_vector(unsigned(grp_fu_763_p2) + unsigned(grp_fu_777_p2));
tmp31_fu_797_p2 <= std_logic_vector(unsigned(tmp47_reg_1148) + unsigned(tmp32_fu_793_p2));
tmp32_fu_793_p2 <= std_logic_vector(unsigned(tmp40_reg_1073) + unsigned(tmp33_reg_1028));
tmp_fu_789_p2 <= std_logic_vector(unsigned(tmp16_reg_983) + unsigned(tmp1_reg_898));
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uP is
port(
--inputs
clock: in std_logic;
reset: in std_logic;
--outputs
pc: out unsigned(15 downto 0); --PC value
c_flag: out std_logic; --Carry flag
z_flag: out std_logic; --Zero flag
n_flag: out std_logic; --Negative flag
lt_flag: out std_logic; --Less Than flag
r0: out unsigned(15 downto 0); --Registers values
r1: out unsigned(15 downto 0);
r2: out unsigned(15 downto 0);
r3: out unsigned(15 downto 0);
r4: out unsigned(15 downto 0);
r5: out unsigned(15 downto 0);
r6: out unsigned(15 downto 0);
r7: out unsigned(15 downto 0);
--debug
state: out unsigned(1 downto 0); --Control unit state (fetch, decode, execute)
rom_output: out unsigned (14 downto 0); --ROM out content
alu_output: out unsigned(15 downto 0); --ALU out content
regbank_output_A: out unsigned(15 downto 0); --Register bank outputs
regbank_output_B: out unsigned(15 downto 0)
);
end entity;
architecture a_uP of uP is
component ram is
port(
clk: in std_logic;
address: in unsigned(15 downto 0);
wr_en: in std_logic;
data_in: in unsigned(15 downto 0);
data_out: out unsigned(15 downto 0)
);
end component;
component condition_code_register is
port(
clk: in std_logic;
enable: in std_logic;
c_D: in std_logic;
z_D: in std_logic;
n_D: in std_logic;
lt_D: in std_logic;
c_Q: out std_logic;
z_Q: out std_logic;
n_Q: out std_logic;
lt_Q: out std_logic
);
end component;
component mux4x1 is
port(
in0: in unsigned(15 downto 0);
in1: in unsigned(15 downto 0);
in2: in unsigned(15 downto 0);
in3: in unsigned(15 downto 0);
sel: in unsigned(3 downto 0);
out0: out unsigned(15 downto 0)
);
end component;
component mux2x1 is
port(
in0: in unsigned(2 downto 0);
in1: in unsigned(2 downto 0);
sel: in unsigned(3 downto 0);
out0: out unsigned(2 downto 0)
);
end component;
component reg16bits is
port(
clk: in std_logic;
rst: in std_logic;
wr_en: in std_logic;
data_in: in unsigned(15 downto 0);
data_out: out unsigned(15 downto 0)
);
end component;
component rom is
port(
clk: in std_logic;
address: in unsigned(10 downto 0);
data: out unsigned(14 downto 0)
);
end component;
component register_bank is
port(
clock: in std_logic;
reset: in std_logic;
rd_register_A: in unsigned(2 downto 0);
rd_register_B: in unsigned(2 downto 0);
wr_data: in unsigned(15 downto 0);
wr_register: in unsigned(2 downto 0);
wr_enable: in std_logic;
rd_data_A: out unsigned(15 downto 0);
rd_data_B: out unsigned(15 downto 0);
r0: out unsigned(15 downto 0);
r1: out unsigned(15 downto 0);
r2: out unsigned(15 downto 0);
r3: out unsigned(15 downto 0);
r4: out unsigned(15 downto 0);
r5: out unsigned(15 downto 0);
r6: out unsigned(15 downto 0);
r7: out unsigned(15 downto 0)
);
end component;
component alu is
port(
operand0: in unsigned(15 downto 0);
operand1: in unsigned(15 downto 0);
operation: in unsigned(3 downto 0);
alu_out: out unsigned(15 downto 0);
c_flag: out std_logic;
z_flag: out std_logic;
n_flag: out std_logic;
lt_flag: out std_logic
);
end component;
component control is
port(
clk: in std_logic;
rst: in std_logic;
current_pc: in unsigned(15 downto 0);
current_instruction: in unsigned(14 downto 0);
c_flag: in std_logic;
z_flag: in std_logic;
n_flag: in std_logic;
lt_flag: in std_logic;
state: out unsigned(1 downto 0);
wr_en_pc: out std_logic;
wr_en_regbank: out std_logic;
wr_en_ram: out std_logic;
pc_address: out unsigned(15 downto 0);
operand_A: out unsigned(2 downto 0);
operand_B: out unsigned(2 downto 0);
opcode: out unsigned(3 downto 0);
immediate: out unsigned(15 downto 0);
wr_data_source: out unsigned(3 downto 0);
ccr_enable: out std_logic
);
end component;
--Connection signals
signal state_sig: unsigned(1 downto 0);
signal opcode_sig: unsigned(3 downto 0);
signal operand_A_sig, operand_B_sig: unsigned(2 downto 0);
signal operand_A_data_sig, operand_B_data_sig: unsigned(15 downto 0);
signal alu_out_sig: unsigned(15 downto 0);
signal wr_en_pc_sig: std_logic;
signal wr_en_regbank_sig: std_logic;
signal wr_en_ram_sig: std_logic;
signal pc_out_sig, pc_in_sig: unsigned(15 downto 0);
signal rom_out_sig: unsigned(14 downto 0);
signal wr_data_sig, immediate_sig: unsigned(15 downto 0);
signal wr_register_sig: unsigned(2 downto 0);
signal c_flag_sig,z_flag_sig,n_flag_sig,lt_flag_sig: std_logic;
signal control_c_flag_sig,control_z_flag_sig,control_n_flag_sig,control_lt_flag_sig: std_logic;
signal ram_address_sig,ram_out_sig,accumulator_sig: unsigned(15 downto 0);
signal write_data_source_sig: unsigned(3 downto 0);
signal ccr_enable_sig: std_logic;
begin
pc<=pc_out_sig;
state<=state_sig;
c_flag<=control_c_flag_sig;
z_flag<=control_z_flag_sig;
n_flag<=control_n_flag_sig;
lt_flag<=control_lt_flag_sig;
r6<=ram_address_sig;
r7<=accumulator_sig;
rom_output <= rom_out_sig;
alu_output <= alu_out_sig;
regbank_output_A <= operand_A_data_sig;
regbank_output_B <= operand_B_data_sig;
up_ram: ram port map( clk=>clock,
address=>ram_address_sig,
wr_en=>wr_en_ram_sig,
data_in=>accumulator_sig,
data_out=>ram_out_sig
);
up_ccr: condition_code_register port map( clk=>clock,
enable=>ccr_enable_sig,
c_D=>c_flag_sig,
z_D=>z_flag_sig,
n_D=>n_flag_sig,
lt_D=>lt_flag_sig,
c_Q=>control_c_flag_sig,
z_Q=>control_z_flag_sig,
n_Q=>control_n_flag_sig,
lt_Q=>control_lt_flag_sig
);
up_control: control port map( clk=>clock,
rst=>reset,
state=>state_sig,
wr_en_pc=>wr_en_pc_sig,
wr_en_regbank=>wr_en_regbank_sig,
current_instruction=>rom_out_sig,
pc_address=>pc_in_sig,
current_pc=>pc_out_sig,
operand_A=>operand_A_sig,
operand_B=>operand_B_sig,
opcode=>opcode_sig,
immediate=>immediate_sig,
wr_data_source=>write_data_source_sig,
c_flag=>control_c_flag_sig,
z_flag=>control_z_flag_sig,
n_flag=>control_n_flag_sig,
lt_flag=>control_lt_flag_sig,
ccr_enable=>ccr_enable_sig,
wr_en_ram=>wr_en_ram_sig
);
up_alu: alu port map( operand0=>operand_A_data_sig,
operand1=>operand_B_data_sig,
operation=>opcode_sig,
alu_out=>alu_out_sig,
c_flag=>c_flag_sig,
z_flag=>z_flag_sig,
n_flag=>n_flag_sig,
lt_flag=>lt_flag_sig
);
up_rom: rom port map( clk=>clock,
address=>pc_out_sig(10 downto 0),
data=>rom_out_sig
);
up_regbank: register_bank port map( clock=>clock,
reset=>reset,
rd_register_A=>operand_A_sig,
rd_register_B=>operand_B_sig,
wr_data=>wr_data_sig,
wr_register=>wr_register_sig,
wr_enable=>wr_en_regbank_sig,
rd_data_A=>operand_A_data_sig,
rd_data_B=>operand_B_data_sig,
r0=>r0,r1=>r1,r2=>r2,
r3=>r3,r4=>r4,r5=>r5,
r6=>ram_address_sig,
r7=>accumulator_sig
);
up_pc: reg16bits port map( clk=>clock,
rst=>reset,
wr_en=>wr_en_pc_sig,
data_in=>pc_in_sig,
data_out=>pc_out_sig
);
up_wr_data_mux: mux4x1 port map( in0=>alu_out_sig,
in1=>immediate_sig,
in2=>operand_B_data_sig,
in3=>ram_out_sig,
sel=>write_data_source_sig,
out0=>wr_data_sig
);
up_wr_register_mux: mux2x1 port map(in0=>"111",
in1=>operand_A_sig,
sel=>write_data_source_sig,
out0=>wr_register_sig
);
end architecture; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1920.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01920ent IS
END c07s02b01x00p01n01i01920ent;
ARCHITECTURE c07s02b01x00p01n01i01920arch OF c07s02b01x00p01n01i01920ent IS
BEGIN
TESTING: PROCESS
variable b1 : Boolean := TRUE;
BEGIN
b1 := not b1;
assert NOT(b1 = FALSE)
report "***PASSED TEST: c07s02b01x00p01n01i01920"
severity NOTE;
assert (b1 = FALSE)
report "***FAILED TEST: c07s02b01x00p01n01i01920 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01920arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1920.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01920ent IS
END c07s02b01x00p01n01i01920ent;
ARCHITECTURE c07s02b01x00p01n01i01920arch OF c07s02b01x00p01n01i01920ent IS
BEGIN
TESTING: PROCESS
variable b1 : Boolean := TRUE;
BEGIN
b1 := not b1;
assert NOT(b1 = FALSE)
report "***PASSED TEST: c07s02b01x00p01n01i01920"
severity NOTE;
assert (b1 = FALSE)
report "***FAILED TEST: c07s02b01x00p01n01i01920 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01920arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1920.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01920ent IS
END c07s02b01x00p01n01i01920ent;
ARCHITECTURE c07s02b01x00p01n01i01920arch OF c07s02b01x00p01n01i01920ent IS
BEGIN
TESTING: PROCESS
variable b1 : Boolean := TRUE;
BEGIN
b1 := not b1;
assert NOT(b1 = FALSE)
report "***PASSED TEST: c07s02b01x00p01n01i01920"
severity NOTE;
assert (b1 = FALSE)
report "***FAILED TEST: c07s02b01x00p01n01i01920 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01920arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.ddr3_ctrl_pkg.all;
entity ddr3_ctrl_wb is
generic (
g_BYTE_ADDR_WIDTH : integer := 29;
g_MASK_SIZE : integer := 8;
g_DATA_PORT_SIZE : integer := 64
);
port (
----------------------------------------------------------------------------
-- Reset input (active low)
----------------------------------------------------------------------------
rst_n_i : in std_logic;
----------------------------------------------------------------------------
-- Status
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- DDR controller port
----------------------------------------------------------------------------
ddr_addr_o : out std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
ddr_cmd_o : out std_logic_vector(2 downto 0);
ddr_cmd_en_o : out std_logic;
ddr_wdf_data_o : out std_logic_vector(511 downto 0);
ddr_wdf_end_o : out std_logic;
ddr_wdf_mask_o : out std_logic_vector(63 downto 0);
ddr_wdf_wren_o : out std_logic;
ddr_rd_data_i : in std_logic_vector(511 downto 0);
ddr_rd_data_end_i : in std_logic;
ddr_rd_data_valid_i : in std_logic;
ddr_rdy_i : in std_logic;
ddr_wdf_rdy_i : in std_logic;
ddr_sr_req_o : out std_logic;
ddr_ref_req_o : out std_logic;
ddr_zq_req_o : out std_logic;
ddr_sr_active_i : in std_logic;
ddr_ref_ack_i : in std_logic;
ddr_zq_ack_i : in std_logic;
ddr_ui_clk_i : in std_logic;
ddr_ui_clk_sync_rst_i : in std_logic;
ddr_init_calib_complete_i : in std_logic;
----------------------------------------------------------------------------
-- Wishbone bus port
----------------------------------------------------------------------------
wb_clk_i : in std_logic;
wb_sel_i : in std_logic_vector(g_MASK_SIZE - 1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_addr_i : in std_logic_vector(32 - 1 downto 0);
wb_data_i : in std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_data_o : out std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Debug ports
----------------------------------------------------------------------------
ddr_wb_rd_mask_dout_do : out std_logic_vector(7 downto 0);
ddr_wb_rd_mask_addr_dout_do : out std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
ddr_rd_mask_rd_data_count_do : out std_logic_vector(3 downto 0);
ddr_rd_data_rd_data_count_do : out std_logic_vector(3 downto 0);
ddr_rd_fifo_full_do : out std_logic_vector(1 downto 0);
ddr_rd_fifo_empty_do : out std_logic_vector(1 downto 0);
ddr_rd_fifo_rd_do : out std_logic_vector(1 downto 0)
);
end entity ddr3_ctrl_wb;
architecture behavioral of ddr3_ctrl_wb is
--------------------------------------
-- Constants
--------------------------------------
constant c_write_wait_time : unsigned(9 downto 0) := TO_UNSIGNED(15, 10);
constant c_read_wait_time : unsigned(9 downto 0) := TO_UNSIGNED(15, 10);
constant c_register_shift_size : integer := 8;
type data_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
type mask_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_MASK_SIZE - 1 downto 0);
type addr_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_BYTE_ADDR_WIDTH - 1 downto 0);
type row_array is array (0 to c_register_shift_size-1) of std_logic_vector(c_register_shift_size-1 downto 0);
--------------------------------------
-- Signals
--------------------------------------
signal rst_s : std_logic;
signal wb_wr_data_shift_a : data_array;
signal wb_wr_data_shift_next_a : data_array;
signal wb_wr_data_shift_s : std_logic_vector(511 downto 0);
signal wb_wr_mask_shift_a : mask_array;
signal wb_wr_mask_shift_next_a : mask_array;
signal wb_wr_valid_shift_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_wr_valid_shift_next_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_wr_addr_shift_a : addr_array;
signal wb_wr_addr_shift_next_a : addr_array;
signal wb_wr_shifting_s : std_logic;
signal wb_wr_match_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_wr_row_a : row_array;
signal wb_wr_global_row_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_wr_first_row_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_wr_several_row_s : std_logic;
signal wb_wr_flush_v_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_wr_shift_flush_s : std_logic;
signal wb_wr_shift_flush_1_s : std_logic;
signal fifo_wb_wr_mask_s : std_logic_vector(63 downto 0);
signal fifo_wb_wr_addr_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal fifo_wb_wr_din_s : std_logic_vector(604 downto 0);
signal fifo_wb_wr_wr_s : std_logic;
signal fifo_wb_wr_rd_s : std_logic;
signal fifo_wb_wr_rd_d : std_logic;
signal fifo_wb_wr_dout_s : std_logic_vector(604 downto 0);
signal fifo_wb_wr_full_s : std_logic;
signal fifo_wb_wr_empty_s : std_logic;
signal wb_rd_valid_shift_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_valid_shift_next_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_data_shift_a : data_array;
signal wb_rd_ack_shift_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_addr_shift_a : addr_array;
signal wb_rd_addr_shift_next_a : addr_array;
signal wb_rd_addr_ref_a : addr_array;
signal wb_rd_shifting_s : std_logic;
signal wb_rd_match_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_row_a : row_array;
signal wb_rd_global_row_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_first_row_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_several_row_s : std_logic;
signal wb_rd_flush_v_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_shift_flush_s : std_logic;
signal wb_rd_shift_flush_1_s : std_logic;
signal fifo_wb_rd_addr_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal fifo_wb_rd_addr_din_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal fifo_wb_rd_addr_wr_s : std_logic;
signal fifo_wb_rd_addr_rd_s : std_logic;
signal fifo_wb_rd_addr_dout_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal fifo_wb_rd_addr_full_s : std_logic;
signal fifo_wb_rd_addr_almost_full_s : std_logic;
signal fifo_wb_rd_addr_empty_s : std_logic;
signal fifo_wb_rd_mask_s : std_logic_vector(g_BYTE_ADDR_WIDTH + c_register_shift_size-1 downto 0);
signal fifo_wb_rd_mask_din_s : std_logic_vector(g_BYTE_ADDR_WIDTH + c_register_shift_size-1 downto 0);
signal fifo_wb_rd_mask_wr_s : std_logic;
signal fifo_wb_rd_mask_rd_s : std_logic;
signal fifo_wb_rd_mask_dout_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal fifo_wb_rd_mask_full_s : std_logic;
signal fifo_wb_rd_mask_almost_full_s : std_logic;
signal fifo_wb_rd_mask_empty_s : std_logic;
signal fifo_wb_rd_mask_rd_data_count_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
signal fifo_wb_rd_data_din_s : std_logic_vector(511 downto 0);
signal fifo_wb_rd_data_wr_s : std_logic;
signal fifo_wb_rd_data_rd_s : std_logic;
signal fifo_wb_rd_data_dout_s : std_logic_vector(511 downto 0);
signal fifo_wb_rd_data_dout_a : data_array;
signal fifo_wb_rd_data_full_s : std_logic;
signal fifo_wb_rd_data_almost_full_s : std_logic;
signal fifo_wb_rd_data_empty_s : std_logic;
signal fifo_wb_rd_data_rd_data_count_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
signal ddr_cmd_s : std_logic; -- '1' = read, '0' = write
signal ddr_rd_data_end_s : std_logic;
signal wb_stall_s : std_logic;
signal wb_stall_d : std_logic;
signal wb_stall_dd : std_logic;
signal wb_wr_ack_s : std_logic;
signal wb_rd_ack_s : std_logic;
--------------------------------------
-- debug
--------------------------------------
--------------------------------------
-- Counter
--------------------------------------
signal wb_write_wait_cnt : unsigned(9 downto 0);
signal wb_read_wait_cnt : unsigned(9 downto 0);
begin
rst_s <= not rst_n_i;
ddr_sr_req_o <= '0';
ddr_ref_req_o <= '0';
ddr_zq_req_o <= '0';
--------------------------------------
-- Read FIFOs debug
--------------------------------------
ddr_wb_rd_mask_dout_do <= fifo_wb_rd_mask_dout_s;
ddr_rd_fifo_full_do <= fifo_wb_rd_data_full_s & fifo_wb_rd_mask_full_s;
ddr_rd_fifo_empty_do <= fifo_wb_rd_data_empty_s & fifo_wb_rd_mask_empty_s;
ddr_rd_fifo_rd_do <= fifo_wb_rd_data_rd_s & fifo_wb_rd_mask_rd_s;
ddr_rd_mask_rd_data_count_do <= fifo_wb_rd_mask_rd_data_count_s(3 downto 0);
ddr_rd_data_rd_data_count_do <= fifo_wb_rd_data_rd_data_count_s(3 downto 0);
--------------------------------------
-- QWORD swap debug
--------------------------------------
--------------------------------------
-- Wishbone ack
--------------------------------------
wb_ack_o <= wb_wr_ack_s or wb_rd_ack_s;
--------------------------------------
-- Wishbone write
--------------------------------------
p_wb_write : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_write_wait_cnt <= c_write_wait_time;
wb_wr_shift_flush_1_s <= '0';
wb_wr_valid_shift_s <= (others => '0');
for i in 0 to c_register_shift_size-1 loop
wb_wr_addr_shift_a(i) <= (others => '1');
wb_wr_data_shift_a(i) <= (others => '0');
wb_wr_mask_shift_a(i) <= (others => '0');
end loop;
wb_wr_ack_s <= '0';
elsif rising_edge(wb_clk_i) then
wb_wr_shift_flush_1_s <= wb_wr_shift_flush_s;
if (wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '1') then
wb_wr_ack_s <= '1';
wb_write_wait_cnt <= c_write_wait_time;
else
wb_wr_ack_s <= '0';
if(wb_wr_valid_shift_s /= (wb_wr_valid_shift_s'range => '0')) then
if (wb_write_wait_cnt /= 0) then
wb_write_wait_cnt <= wb_write_wait_cnt - 1;
end if;
end if;
end if;
-- Erase the data sent to the FIFO
--if(wb_wr_shift_flush_1_s = '1') then
if(wb_wr_shift_flush_s = '1') then
wb_write_wait_cnt <= c_write_wait_time;
end if;
wb_wr_addr_shift_a <= wb_wr_addr_shift_next_a;
wb_wr_data_shift_a <= wb_wr_data_shift_next_a;
wb_wr_mask_shift_a <= wb_wr_mask_shift_next_a;
wb_wr_valid_shift_s <= wb_wr_valid_shift_next_s;
end if;
end process p_wb_write;
p_wb_write_rtl : process (wb_write_wait_cnt,wb_wr_addr_shift_a,wb_wr_valid_shift_s,wb_wr_shift_flush_s,wb_wr_first_row_s,wb_wr_row_a,wb_wr_match_s,wb_wr_global_row_s)
begin
fifo_wb_wr_addr_s <= (others => '0');
wb_wr_first_row_s <= (others => '0');
for i in (c_register_shift_size-1) downto 0 loop
if wb_wr_global_row_s(i) = '1' then
fifo_wb_wr_addr_s <= wb_wr_addr_shift_a(i)(g_BYTE_ADDR_WIDTH-1 downto 3) & "000" ;
wb_wr_first_row_s <= wb_wr_row_a(i);
end if;
end loop;
if((wb_wr_global_row_s /= wb_wr_first_row_s) and (wb_wr_global_row_s /= (wb_wr_global_row_s'range => '0'))) then
wb_wr_several_row_s <= '1';
else
wb_wr_several_row_s <= '0';
end if;
end process p_wb_write_rtl;
p_wb_write_shift: process (wb_wr_shifting_s,wb_wr_addr_shift_a,wb_wr_data_shift_a,wb_wr_mask_shift_a,wb_wr_valid_shift_s,wb_addr_i,wb_data_i,wb_sel_i,wb_wr_flush_v_s)
begin
if(wb_wr_shifting_s = '1') then
wb_wr_addr_shift_next_a(c_register_shift_size-1) <= wb_addr_i(g_BYTE_ADDR_WIDTH-1 downto 0);
wb_wr_data_shift_next_a(c_register_shift_size-1) <= wb_data_i;
wb_wr_mask_shift_next_a(c_register_shift_size-1) <= wb_sel_i;
wb_wr_valid_shift_next_s(c_register_shift_size-1) <= wb_cyc_i and wb_stb_i and wb_we_i;
for i in 1 to c_register_shift_size-1 loop
wb_wr_addr_shift_next_a(i-1) <= wb_wr_addr_shift_a(i);
wb_wr_data_shift_next_a(i-1) <= wb_wr_data_shift_a(i);
wb_wr_mask_shift_next_a(i-1) <= wb_wr_mask_shift_a(i);
if wb_wr_flush_v_s(i) = '0' then
wb_wr_valid_shift_next_s(i-1) <= wb_wr_valid_shift_s(i);
else
wb_wr_valid_shift_next_s(i-1) <= '0';
end if;
end loop;
else
for i in 0 to c_register_shift_size-1 loop
wb_wr_addr_shift_next_a(i) <= wb_wr_addr_shift_a(i);
wb_wr_data_shift_next_a(i) <= wb_wr_data_shift_a(i);
wb_wr_mask_shift_next_a(i) <= wb_wr_mask_shift_a(i);
if wb_wr_flush_v_s(i) = '0' then
wb_wr_valid_shift_next_s(i) <= wb_wr_valid_shift_s(i);
else
wb_wr_valid_shift_next_s(i) <= '0';
end if;
end loop;
end if;
end process p_wb_write_shift;
wb_wr_shifting_s <= --'0' when wb_wr_several_row_s = '1' else
'1' when wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '1' else
'1' when wb_write_wait_cnt = 0 else
'0';
wb_wr_global_row_s <= wb_wr_match_s and wb_wr_valid_shift_s;
wb_wr_flush_v_s <= wb_wr_first_row_s;
wb_wr_shift_flush_s <= '1' when wb_wr_flush_v_s /= (wb_wr_flush_v_s'range => '0') else
'0';
wr_mask_match_g:for i in 0 to c_register_shift_size-1 generate
wb_wr_match_s(i) <= '1' when wb_wr_addr_shift_a(i)(2 downto 0) = std_logic_vector(to_unsigned(i,3)) else
'0';
wr_row_g:for j in 0 to c_register_shift_size-1 generate
wb_wr_row_a(i)(j) <= '1' when wb_wr_addr_shift_a(i)(g_BYTE_ADDR_WIDTH-1 downto 3) = wb_wr_addr_shift_a(j)(g_BYTE_ADDR_WIDTH-1 downto 3) and wb_wr_match_s(i) = '1' and wb_wr_match_s(j) = '1' and wb_wr_valid_shift_s(i) = '1' and wb_wr_valid_shift_s(j) = '1' else
'0';
end generate;
fifo_wb_wr_mask_s((i)*8+7 downto (i)*8) <= wb_wr_mask_shift_a(i) when wb_wr_flush_v_s(i) = '1' else (others=>'0');
end generate;
-- No Little endian conversion
wb_wr_data_shift_s <= wb_wr_data_shift_a(7) &
wb_wr_data_shift_a(6) &
wb_wr_data_shift_a(5) &
wb_wr_data_shift_a(4) &
wb_wr_data_shift_a(3) &
wb_wr_data_shift_a(2) &
wb_wr_data_shift_a(1) &
wb_wr_data_shift_a(0);
fifo_wr_data_in : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fifo_wb_wr_din_s <= (others => '0');
fifo_wb_wr_wr_s <= '0';
elsif rising_edge(wb_clk_i) then
fifo_wb_wr_din_s <= fifo_wb_wr_addr_s &
fifo_wb_wr_mask_s &
wb_wr_data_shift_s;
fifo_wb_wr_wr_s <= wb_wr_shift_flush_s;
end if;
end process;
--fifo_wb_wr_din_s <= fifo_wb_wr_addr_s &
-- fifo_wb_wr_mask_s &
-- wb_wr_data_shift_s;
--fifo_wb_wr_wr_s <= wb_wr_shift_flush_s;
fifo_wb_write : fifo_315x16
PORT MAP (
rst => rst_s,
wr_clk => wb_clk_i,
rd_clk => ddr_ui_clk_i,
din => fifo_wb_wr_din_s,
wr_en => fifo_wb_wr_wr_s,
rd_en => fifo_wb_wr_rd_s,
dout => fifo_wb_wr_dout_s,
full => fifo_wb_wr_full_s,
empty => fifo_wb_wr_empty_s
);
--------------------------------------
-- Wishbone read
--------------------------------------
p_wb_read : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_rd_shift_flush_1_s <= wb_rd_shift_flush_s;
wb_read_wait_cnt <= c_read_wait_time;
wb_rd_valid_shift_s <= (others => '0');
for i in 0 to c_register_shift_size-1 loop
wb_rd_addr_shift_a(i) <= (others => '0');
end loop;
elsif rising_edge(wb_clk_i) then
wb_rd_shift_flush_1_s <= wb_rd_shift_flush_s;
-- Register Shift
if (wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '0') then
wb_read_wait_cnt <= c_read_wait_time;
else
if(wb_rd_valid_shift_s /= (wb_rd_valid_shift_s'range => '0')) then
if (wb_read_wait_cnt /= 0) then
wb_read_wait_cnt <= wb_read_wait_cnt - 1;
end if;
end if;
end if;
-- Erase the data sent to the FIFO
--if(wb_rd_shift_flush_1_s = '1') then
if(wb_rd_shift_flush_s = '1') then
wb_read_wait_cnt <= c_read_wait_time;
end if;
wb_rd_addr_shift_a <= wb_rd_addr_shift_next_a;
wb_rd_valid_shift_s <= wb_rd_valid_shift_next_s;
end if;
end process p_wb_read;
p_wb_read_rtl : process (wb_read_wait_cnt,wb_rd_addr_shift_a,wb_rd_addr_ref_a,wb_rd_valid_shift_s,wb_rd_shift_flush_s,wb_rd_global_row_s,wb_rd_addr_shift_a,wb_rd_row_a,wb_rd_first_row_s)
begin
fifo_wb_rd_addr_s <= (others => 'X');
wb_rd_first_row_s <= (others => '0');
for i in (c_register_shift_size-1) downto 0 loop
if wb_rd_global_row_s(i) = '1' then
fifo_wb_rd_addr_s <= wb_rd_addr_shift_a(i)(g_BYTE_ADDR_WIDTH-1 downto 3) & "000" ;
wb_rd_first_row_s <= wb_rd_row_a(i);
end if;
end loop;
if((wb_rd_global_row_s /= wb_rd_first_row_s) and (wb_rd_global_row_s /= (wb_rd_global_row_s'range => '0'))) then
wb_rd_several_row_s <= '1';
else
wb_rd_several_row_s <= '0';
end if;
end process p_wb_read_rtl;
wb_rd_shifting_s <= --'0' when wb_rd_several_row_s = '1' else
'1' when wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '0' else
'1' when wb_read_wait_cnt = 0 else
'0';
wb_rd_global_row_s <= wb_rd_match_s and wb_rd_valid_shift_s;
wb_rd_flush_v_s <= wb_rd_first_row_s;
rd_match_g:for i in 0 to c_register_shift_size-1 generate
wb_rd_match_s(i) <= '1' when wb_rd_addr_shift_a(i)(2 downto 0) = std_logic_vector(to_unsigned(i,3)) else
'0';
rd_row_g:for j in 0 to c_register_shift_size-1 generate
wb_rd_row_a(i)(j) <= '1' when wb_rd_addr_shift_a(i)(g_BYTE_ADDR_WIDTH-1 downto 3) = wb_rd_addr_shift_a(j)(g_BYTE_ADDR_WIDTH-1 downto 3) and wb_rd_match_s(i) = '1' and wb_rd_match_s(j) = '1' and wb_rd_valid_shift_s(i) = '1' and wb_rd_valid_shift_s(j) = '1' else
'0';
end generate;
end generate;
p_wb_read_shift: process (wb_rd_shifting_s,wb_rd_addr_shift_a,wb_rd_valid_shift_s,wb_addr_i,wb_data_i,wb_sel_i,wb_rd_flush_v_s)
begin
if(wb_rd_shifting_s = '1') then
wb_rd_addr_shift_next_a(c_register_shift_size-1) <= wb_addr_i(g_BYTE_ADDR_WIDTH-1 downto 0);
wb_rd_valid_shift_next_s(c_register_shift_size-1) <= wb_cyc_i and wb_stb_i and not wb_we_i;
for i in 1 to c_register_shift_size-1 loop
wb_rd_addr_shift_next_a(i-1) <= wb_rd_addr_shift_a(i);
if wb_rd_flush_v_s(i) = '0' then
wb_rd_valid_shift_next_s(i-1) <= wb_rd_valid_shift_s(i);
else
wb_rd_valid_shift_next_s(i-1) <= '0';
end if;
end loop;
else
for i in 0 to c_register_shift_size-1 loop
wb_rd_addr_shift_next_a(i) <= wb_rd_addr_shift_a(i);
if wb_rd_flush_v_s(i) = '0' then
wb_rd_valid_shift_next_s(i) <= wb_rd_valid_shift_s(i);
else
wb_rd_valid_shift_next_s(i) <= '0';
end if;
end loop;
end if;
end process p_wb_read_shift;
p_wb_read_data : process(wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
for i in 0 to c_register_shift_size-1 loop
wb_rd_data_shift_a(i) <= (others => '0');
wb_rd_ack_shift_s(i) <= '0';
end loop;
elsif rising_edge(wb_clk_i) then
if(fifo_wb_rd_data_rd_s = '1') then
for i in 0 to c_register_shift_size-1 loop
wb_rd_data_shift_a(i) <= fifo_wb_rd_data_dout_s(63+(i*64) downto 0+(i*64));
wb_rd_ack_shift_s(i) <= fifo_wb_rd_mask_dout_s(i); -- The data are reversed
end loop;
else
wb_rd_data_shift_a(c_register_shift_size-1) <= (others => '0');
wb_rd_ack_shift_s(c_register_shift_size-1) <= '0';
for i in 0 to c_register_shift_size-2 loop
wb_rd_data_shift_a(i) <= wb_rd_data_shift_a(i+1);
wb_rd_ack_shift_s(i) <= wb_rd_ack_shift_s(i+1);
end loop;
end if;
end if;
end process p_wb_read_data;
fifo_rd_data_in : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fifo_wb_rd_addr_din_s <= (others => '0');
fifo_wb_rd_mask_din_s <= (others => '0');
fifo_wb_rd_addr_wr_s <= '0';
fifo_wb_rd_mask_wr_s <= '0';
elsif rising_edge(wb_clk_i) then
fifo_wb_rd_addr_wr_s <= wb_rd_shift_flush_s;
fifo_wb_rd_mask_wr_s <= wb_rd_shift_flush_s;
fifo_wb_rd_addr_din_s <= fifo_wb_rd_addr_s;
fifo_wb_rd_mask_din_s <= fifo_wb_rd_addr_s & wb_rd_valid_shift_s;
end if;
end process;
--fifo_wb_rd_addr_wr_s <= wb_rd_shift_flush_s;
--fifo_wb_rd_mask_wr_s <= wb_rd_shift_flush_s;
--fifo_wb_rd_mask_din_s <= fifo_wb_rd_addr_s & wb_rd_valid_shift_s;
fifo_wb_rd_data_rd_s <= '1' when wb_rd_ack_shift_s(c_register_shift_size-1 downto 1) = "0000000" and fifo_wb_rd_mask_empty_s = '0' and fifo_wb_rd_data_empty_s = '0' else
'0';
fifo_wb_rd_mask_rd_s <= fifo_wb_rd_data_rd_s;
wb_data_o <= wb_rd_data_shift_a(0);
wb_rd_ack_s <= wb_rd_ack_shift_s(0);
wb_rd_shift_flush_s <= '1' when wb_rd_flush_v_s /= (wb_rd_flush_v_s'range => '0') else
'0';
fifo_wb_read_addr : fifo_27x16
PORT MAP (
rst => rst_s,
wr_clk => wb_clk_i,
rd_clk => ddr_ui_clk_i,
din => fifo_wb_rd_addr_din_s,
wr_en => fifo_wb_rd_addr_wr_s,
rd_en => fifo_wb_rd_addr_rd_s,
dout => fifo_wb_rd_addr_dout_s,
full => fifo_wb_rd_addr_full_s,
almost_full => fifo_wb_rd_addr_almost_full_s,
empty => fifo_wb_rd_addr_empty_s
);
fifo_wb_read_mask : fifo_4x16
PORT MAP (
rst => rst_s,
wr_clk => wb_clk_i,
rd_clk => wb_clk_i,
din => fifo_wb_rd_mask_din_s,
wr_en => fifo_wb_rd_mask_wr_s,
rd_en => fifo_wb_rd_mask_rd_s,
dout(7 downto 0) => fifo_wb_rd_mask_dout_s,
dout(36 downto 8) => ddr_wb_rd_mask_addr_dout_do,
full => fifo_wb_rd_mask_full_s,
almost_full => fifo_wb_rd_mask_almost_full_s,
empty => fifo_wb_rd_mask_empty_s,
rd_data_count => fifo_wb_rd_mask_rd_data_count_s
);
fifo_wb_read_data : fifo_256x16
PORT MAP (
rst => rst_s,
wr_clk => ddr_ui_clk_i,
rd_clk => wb_clk_i,
din => fifo_wb_rd_data_din_s,
wr_en => fifo_wb_rd_data_wr_s,
rd_en => fifo_wb_rd_data_rd_s,
dout => fifo_wb_rd_data_dout_s,
full => fifo_wb_rd_data_full_s,
almost_full => fifo_wb_rd_data_almost_full_s,
empty => fifo_wb_rd_data_empty_s,
rd_data_count => fifo_wb_rd_data_rd_data_count_s
);
--------------------------------------
-- DDR CMD
--------------------------------------
p_ddr_cmd : process (ddr_ui_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
ddr_cmd_en_o <= '0';
ddr_cmd_o <= "000";
elsif rising_edge(ddr_ui_clk_i) then
if(fifo_wb_wr_rd_s = '1') then
ddr_cmd_en_o <= '1';
ddr_cmd_o <= "000";
ddr_cmd_s <= '0';
elsif (fifo_wb_rd_addr_rd_s = '1') then
ddr_cmd_en_o <= '1';
ddr_cmd_o <= "001";
ddr_cmd_s <= '1';
elsif (ddr_rdy_i = '1') then
ddr_cmd_en_o <= '0';
end if;
end if;
end process p_ddr_cmd;
ddr_addr_o <= fifo_wb_wr_dout_s(604 downto 576) when ddr_cmd_s = '0' else
fifo_wb_rd_addr_dout_s;
--------------------------------------
-- DDR Data out
--------------------------------------
p_ddr_data_out : process (ddr_ui_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
ddr_wdf_wren_o <= '0';
ddr_wdf_end_o <= '0';
elsif rising_edge(ddr_ui_clk_i) then
if (fifo_wb_wr_rd_s = '1') then
ddr_wdf_wren_o <= '1';
ddr_wdf_end_o <= '1';
elsif (ddr_wdf_rdy_i = '1') then
ddr_wdf_wren_o <= '0';
ddr_wdf_end_o <= '0';
end if;
end if;
end process p_ddr_data_out;
ddr_wdf_data_o <= fifo_wb_wr_dout_s(511 downto 0);
ddr_wdf_mask_o <= not fifo_wb_wr_dout_s(575 downto 512);
--------------------------------------
-- DDR Data in
--------------------------------------
fifo_wb_wr_rd_s <= ddr_wdf_rdy_i and ddr_rdy_i and not fifo_wb_wr_empty_s;
fifo_wb_rd_addr_rd_s <= ddr_rdy_i and (not fifo_wb_rd_addr_empty_s) and (not fifo_wb_rd_data_almost_full_s); -- and (not fifo_wb_rd_mask_full_s);
fifo_wb_rd_data_wr_s <= ddr_rd_data_valid_i and ddr_rd_data_end_i;
fifo_wb_rd_data_din_s <= ddr_rd_data_i;
--------------------------------------
-- Stall proc
--------------------------------------
wb_stall_s <= fifo_wb_wr_full_s or fifo_wb_rd_addr_almost_full_s or fifo_wb_rd_mask_almost_full_s or wb_wr_several_row_s; --or (not ddr_wdf_rdy_i) or (not ddr_rdy_i);
wb_stall_o <= wb_stall_s;
end architecture behavioral;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_c_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_c_e-rtl-conf-c.vhd,v 1.1 2006/04/10 15:42:08 wig Exp $
-- $Date: 2006/04/10 15:42:08 $
-- $Log: inst_c_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2006/04/10 15:42:08 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_c_e_rtl_conf / inst_c_e
--
configuration inst_c_e_rtl_conf of inst_c_e is
for rtl
-- Generated Configuration
end for;
end inst_c_e_rtl_conf;
--
-- End of Generated Configuration inst_c_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
library verilog;
use verilog.vl_types.all;
entity altsquare is
generic(
data_width : integer := 1;
result_width : integer := 1;
pipeline : integer := 0;
representation : string := "UNSIGNED";
result_alignment: string := "LSB";
lpm_hint : string := "UNUSED";
lpm_type : string := "altsquare"
);
port(
data : in vl_logic_vector;
clock : in vl_logic;
ena : in vl_logic;
aclr : in vl_logic;
result : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of data_width : constant is 1;
attribute mti_svvh_generic_type of result_width : constant is 1;
attribute mti_svvh_generic_type of pipeline : constant is 1;
attribute mti_svvh_generic_type of representation : constant is 1;
attribute mti_svvh_generic_type of result_alignment : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
end altsquare;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT36.VHD ***
--*** ***
--*** Function: 36 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_lsft36;
ARCHITECTURE sft OF fp_lsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
-- shift by 0,16,32
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END sft;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT36.VHD ***
--*** ***
--*** Function: 36 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_lsft36;
ARCHITECTURE sft OF fp_lsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
-- shift by 0,16,32
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END sft;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT36.VHD ***
--*** ***
--*** Function: 36 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_lsft36;
ARCHITECTURE sft OF fp_lsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
-- shift by 0,16,32
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END sft;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT36.VHD ***
--*** ***
--*** Function: 36 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_lsft36;
ARCHITECTURE sft OF fp_lsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
-- shift by 0,16,32
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END sft;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT36.VHD ***
--*** ***
--*** Function: 36 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_lsft36;
ARCHITECTURE sft OF fp_lsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
-- shift by 0,16,32
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END sft;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT36.VHD ***
--*** ***
--*** Function: 36 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_lsft36;
ARCHITECTURE sft OF fp_lsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
-- shift by 0,16,32
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END sft;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT36.VHD ***
--*** ***
--*** Function: 36 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_lsft36;
ARCHITECTURE sft OF fp_lsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
-- shift by 0,16,32
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END sft;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT36.VHD ***
--*** ***
--*** Function: 36 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_lsft36;
ARCHITECTURE sft OF fp_lsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
-- shift by 0,16,32
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END sft;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT36.VHD ***
--*** ***
--*** Function: 36 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_lsft36;
ARCHITECTURE sft OF fp_lsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
-- shift by 0,16,32
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END sft;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT36.VHD ***
--*** ***
--*** Function: 36 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_lsft36;
ARCHITECTURE sft OF fp_lsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
-- shift by 0,16,32
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END sft;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: system_monitor
-- File: system_monitor.vhd
-- Author: Jan Andersson, Jiri Gaisler - Gaisler Research
-- Description: System monitor wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity system_monitor is
generic (
-- GRLIB generics
tech : integer := DEFFABTECH;
-- Virtex 5 SYSMON generics
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end system_monitor;
architecture struct of system_monitor is
component sysmon_virtex5
generic (
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end component;
component sysmon
generic (
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_DEVICE : string := "VIRTEX5";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end component;
begin -- struct
gen: if not ((tech = virtex5) or (tech = virtex6) or (tech = virtex7) or (tech = kintex7)) generate
alm <= (others => '0');
busy <= '0';
channel <= (others => '0');
do <= (others => '0');
drdy <= '0';
eoc <= '0';
eos <= '0';
jtagbusy <= '0';
jtaglocked <= '0';
jtagmodified <= '0';
ot <= '0';
end generate gen;
v5: if tech = virtex5 generate
v50 : sysmon_virtex5
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate v5;
v6: if tech = virtex6 generate
v60 : sysmon
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_DEVICE => "VIRTEX6",
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate v6;
v7: if tech = virtex7 generate
v70 : sysmon
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_DEVICE => "VIRTEX7",
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate v7;
k7: if tech = kintex7 generate
k70 : sysmon
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_DEVICE => "KINTEX7",
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate k7;
end struct;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-03 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_03200_bad.vhd
-- File Creation date : 2015-04-03
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Unused output ports components management: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
entity STD_03200_bad is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_03200_bad;
--CODE
architecture Behavioral of STD_03200_bad is
signal Q_n : std_logic;
begin
FlipFlop : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => i_D,
o_Q => o_Q,
o_Q_n => Q_n
);
end Behavioral;
--CODE
|
-- $Id: ibdr_dl11_buf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_dl11_buf - syn
-- Description: ibus dev(rem): DL11-A/B
--
-- Dependencies: fifo_simple_dram
-- ib_rlim_slv
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2017.2; ghdl 0.18-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-05-31 1156 1.0.1 size->fuse rename; re-organize rlim handling
-- 2019-04-26 1139 1.0 Initial version (derived from ibdr_{dl11,pc11_buf})
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_dl11_buf is -- ibus dev(rem): DL11-A/B
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#177560#,16));
AWIDTH : natural := 5); -- fifo address width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RLIM_CEV : in slv8; -- clock enable vector
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_RX : out slbit; -- interrupt request, receiver
EI_REQ_TX : out slbit; -- interrupt request, transmitter
EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
);
end ibdr_dl11_buf;
architecture syn of ibdr_dl11_buf is
constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
constant ibaddr_xcsr : slv2 := "10"; -- xcsr address offset
constant ibaddr_xbuf : slv2 := "11"; -- xbuf address offset
subtype rcsr_ibf_rrlim is integer range 14 downto 12;
subtype rcsr_ibf_type is integer range 10 downto 8;
constant rcsr_ibf_rdone : integer := 7;
constant rcsr_ibf_rie : integer := 6;
constant rcsr_ibf_rir : integer := 5;
constant rcsr_ibf_rlb : integer := 4;
constant rcsr_ibf_fclr : integer := 1;
subtype rbuf_ibf_rfuse is integer range AWIDTH-1+8 downto 8;
subtype rbuf_ibf_xfuse is integer range AWIDTH-1 downto 0;
subtype rbuf_ibf_data is integer range 7 downto 0;
subtype xcsr_ibf_xrlim is integer range 14 downto 12;
constant xcsr_ibf_xrdy : integer := 7;
constant xcsr_ibf_xie : integer := 6;
constant xcsr_ibf_xir : integer := 5;
constant xcsr_ibf_rlb : integer := 4;
constant xcsr_ibf_fclr : integer := 1;
constant xbuf_ibf_xval : integer := 15;
subtype xbuf_ibf_fuse is integer range AWIDTH-1+8 downto 8;
subtype xbuf_ibf_data is integer range 7 downto 0;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
rrlim : slv3; -- rcsr: receiver rate limit
rdone : slbit; -- rcsr: receiver done
rie : slbit; -- rcsr: receiver interrupt enable
rintreq : slbit; -- rx interrupt request
xrlim : slv3; -- xcsr: transmitter rate limit
xrdy : slbit; -- xcsr: transmitter ready
xie : slbit; -- xcsr: transmitter interrupt enable
xintreq : slbit; -- tx interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
"000", -- rrlim
'0','0','0', -- rdone,rie,rintreq
"000", -- xrlim
'1', -- xrdy !! is set !!
'0', -- xie
'0' -- xintreq
);
constant c_fuse1 : slv(AWIDTH-1 downto 0) := slv(to_unsigned(1,AWIDTH));
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal RBUF_CE : slbit := '0';
signal RBUF_WE : slbit := '0';
signal RBUF_DO : slv8 := (others=>'0');
signal RBUF_RESET : slbit := '0';
signal RBUF_EMPTY : slbit := '0';
signal RBUF_FULL : slbit := '0';
signal RBUF_FUSE : slv(AWIDTH-1 downto 0) := (others=>'0');
signal XBUF_CE : slbit := '0';
signal XBUF_WE : slbit := '0';
signal XBUF_DO : slv8 := (others=>'0');
signal XBUF_RESET : slbit := '0';
signal XBUF_EMPTY : slbit := '0';
signal XBUF_FULL : slbit := '0';
signal XBUF_FUSE : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RRLIM_START : slbit := '0';
signal RRLIM_BUSY : slbit := '0';
signal XRLIM_START : slbit := '0';
signal XRLIM_BUSY : slbit := '0';
begin
assert AWIDTH>=4 and AWIDTH<=7
report "assert(AWIDTH>=4 and AWIDTH<=7): unsupported AWIDTH"
severity failure;
RBUF : fifo_simple_dram
generic map (
AWIDTH => AWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RBUF_RESET,
CE => RBUF_CE,
WE => RBUF_WE,
DI => IB_MREQ.din(rbuf_ibf_data),
DO => RBUF_DO,
EMPTY => RBUF_EMPTY,
FULL => RBUF_FULL,
SIZE => RBUF_FUSE
);
XBUF : fifo_simple_dram
generic map (
AWIDTH => AWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => XBUF_RESET,
CE => XBUF_CE,
WE => XBUF_WE,
DI => IB_MREQ.din(xbuf_ibf_data),
DO => XBUF_DO,
EMPTY => XBUF_EMPTY,
FULL => XBUF_FULL,
SIZE => XBUF_FUSE
);
RRLIM : ib_rlim_slv
port map (
CLK => CLK,
RESET => RESET,
RLIM_CEV => RLIM_CEV,
SEL => R_REGS.rrlim,
START => RRLIM_START,
STOP => BRESET,
DONE => open,
BUSY => RRLIM_BUSY
);
XRLIM : ib_rlim_slv
port map (
CLK => CLK,
RESET => RESET,
RLIM_CEV => RLIM_CEV,
SEL => R_REGS.xrlim,
START => XRLIM_START,
STOP => BRESET,
DONE => open,
BUSY => XRLIM_BUSY
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.rrlim <= N_REGS.rrlim; -- keep RRLIM field
R_REGS.xrlim <= N_REGS.xrlim; -- keep XRLIM field
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, EI_ACK_RX, EI_ACK_TX, RESET,
RBUF_DO, RBUF_EMPTY, RBUF_FULL, RBUF_FUSE, RRLIM_BUSY,
XBUF_DO, XBUF_EMPTY, XBUF_FULL, XBUF_FUSE, XRLIM_BUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable iback : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
variable irbufce : slbit := '0';
variable irbufwe : slbit := '0';
variable irbufrst : slbit := '0';
variable irrlimsta : slbit := '0';
variable ixbufce : slbit := '0';
variable ixbufwe : slbit := '0';
variable ixbufrst : slbit := '0';
variable ixrlimsta : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
iback := r.ibsel and ibreq;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
irbufce := '0';
irbufwe := '0';
irbufrst := RESET;
irrlimsta := '0';
ixbufce := '0';
ixbufwe := '0';
ixbufrst := RESET;
ixrlimsta := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 3)=IB_ADDR(12 downto 3) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then -- ibus selected ---------------------
case IB_MREQ.addr(2 downto 1) is
when ibaddr_rcsr => -- RCSR -- receive control status ----
idout(rcsr_ibf_rdone) := r.rdone;
idout(rcsr_ibf_rie) := r.rie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then -- rcsr write
n.rie := IB_MREQ.din(rcsr_ibf_rie);
if IB_MREQ.din(rcsr_ibf_rie) = '1' then-- set IE to 1
if r.rdone='1' and r.rie='0' then -- ie 0->1 while done=1
n.rintreq := '1'; -- request interrupt
end if;
else -- set IE to 0
n.rintreq := '0'; -- cancel interrupt
end if;
end if;
else -- rri ---------------------
idout(rcsr_ibf_rrlim) := r.rrlim;
idout(rcsr_ibf_type) := slv(to_unsigned(AWIDTH,3));
idout(rcsr_ibf_rir) := r.rintreq;
idout(rcsr_ibf_rlb) := RRLIM_BUSY;
if ibw1 = '1' then
n.rrlim := IB_MREQ.din(rcsr_ibf_rrlim);
end if;
if ibw0 = '1' then
if IB_MREQ.din(rcsr_ibf_fclr) = '1' then -- 1 written to FCLR
irbufrst := '1'; -- then reset fifo
end if;
end if;
end if;
when ibaddr_rbuf => -- RBUF -- receive data buffer -------
if IB_MREQ.racc = '0' then -- cpu ---------------------
idout(rbuf_ibf_data) := RBUF_DO;
if ibrd = '1' then -- rbuf read
n.rdone := '0'; -- clear done
n.rintreq := '0'; -- cancel interrupt
if r.rdone='1' then -- data available ?
irbufce := '1'; -- read next from fifo
irbufwe := '0';
if RBUF_FUSE = c_fuse1 then -- last value (fuse=1) ?
ilam := '1'; -- rri lam
end if;
end if;
end if;
else -- rri ---------------------
idout(rbuf_ibf_rfuse) := RBUF_FUSE;
idout(rbuf_ibf_xfuse) := XBUF_FUSE;
if ibw0 = '1' then
if RBUF_FULL = '0' then -- fifo not full
irbufce := '1'; -- write to fifo
irbufwe := '1';
else -- write to full fifo
iback := '0'; -- signal nak
end if;
end if;
end if;
when ibaddr_xcsr => -- XCSR -- transmit control status ---
idout(xcsr_ibf_xrdy) := r.xrdy;
idout(xcsr_ibf_xie) := r.xie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.xie := IB_MREQ.din(xcsr_ibf_xie);
if IB_MREQ.din(xcsr_ibf_xie) = '1' then-- set IE to 1
if r.xrdy='1' and r.xie='0' then -- ie 0->1 while ready=1
n.xintreq := '1'; -- request interrupt
end if;
else -- set IE to 0
n.xintreq := '0'; -- cancel interrupts
end if;
end if;
else -- rri ---------------------
idout(xcsr_ibf_xrlim) := r.xrlim;
idout(xcsr_ibf_xir) := r.xintreq;
idout(xcsr_ibf_rlb) := XRLIM_BUSY;
if ibw1 = '1' then
n.xrlim := IB_MREQ.din(xcsr_ibf_xrlim); -- set XRLIM field
end if;
if ibw0 = '1' then
if IB_MREQ.din(xcsr_ibf_fclr) = '1' then -- 1 written to FCLR
ixbufrst := '1'; -- then reset fifo
end if;
end if;
end if;
when ibaddr_xbuf => -- XBUF -- transmit data buffer ------
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
if r.xrdy = '1' then -- ignore buf write when rdy=0
n.xrdy := '0'; -- clear ready
n.xintreq := '0'; -- cancel interrupt
if XBUF_FULL = '0' then -- fifo not full
ixbufce := '1'; -- write to fifo
ixbufwe := '1';
if XBUF_EMPTY = '1' then -- first write to empty fifo
ilam := '1'; -- request attention
end if;
end if;
end if;
end if;
else -- rri ---------------------
idout(xbuf_ibf_xval) := not XBUF_EMPTY;
idout(xbuf_ibf_fuse) := XBUF_FUSE;
idout(xbuf_ibf_data) := XBUF_DO;
if ibrd = '1' then
if XBUF_EMPTY = '0' then -- fifo not empty
ixbufce := '1'; -- read from fifo
ixbufwe := '0';
else -- read from empty fifo
iback := '0'; -- signal nak
end if;
end if;
end if;
when others => null;
end case;
else -- ibus not selected -----------------
-- handle rx done, timer and interrupt
if RBUF_EMPTY='0' and RRLIM_BUSY='0' then -- not empty and not busy ?
if r.rdone = '0' then -- done not set ?
n.rdone := '1'; -- set done
irrlimsta := '1'; -- start timer
if r.rie = '1' then -- irupts enabled ?
n.rintreq := '1'; -- request rx interrupt
end if;
end if;
end if;
-- handle tx ready, timer and interrupt
if XBUF_FULL='0' and XRLIM_BUSY='0' then -- not full and not busy ?
if r.xrdy = '0' then -- ready not set ?
n.xrdy := '1'; -- set ready
ixrlimsta := '1'; -- start timer
if r.xie = '1' then -- irupts enabled ?
n.xintreq := '1'; -- request tx interrupt
end if;
end if;
end if;
end if; -- else r.ibsel='1'
-- other state changes
if EI_ACK_RX = '1' then
n.rintreq := '0';
end if;
if EI_ACK_TX = '1' then
n.xintreq := '0';
end if;
N_REGS <= n;
RBUF_RESET <= irbufrst;
RBUF_CE <= irbufce;
RBUF_WE <= irbufwe;
RRLIM_START <= irrlimsta;
XBUF_RESET <= ixbufrst;
XBUF_CE <= ixbufce;
XBUF_WE <= ixbufwe;
XRLIM_START <= ixrlimsta;
IB_SRES.dout <= idout;
IB_SRES.ack <= iback;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ_RX <= r.rintreq;
EI_REQ_TX <= r.xintreq;
end process proc_next;
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
entity test_regfile is
end entity;
architecture behaviour of test_regfile is
component regfile
port (ra1, ra2, wa3: in std_logic_vector(4 downto 0);
wd3: in std_logic_vector(31 downto 0);
we3, clk: in std_logic;
rd1, rd2: out std_logic_vector(31 downto 0));
end component;
signal ra1, ra2, wa3: std_logic_vector(4 downto 0);
signal wd3, rd1, rd2: std_logic_vector(31 downto 0);
signal we3, clk: std_logic;
begin
prueba: regfile port map (ra1, ra2, wa3, wd3, we3, clk, rd1, rd2);
process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
process
begin
we3 <= '1';
wait for 15 ns;
we3 <= '0';
wait for 10 ns;
end process;
process
begin
wd3 <= x"ab120abb";
wait for 5 ns;
wd3 <= x"fff01bba";
wait for 5 ns;
wd3 <= x"abc99fff";
wait for 5 ns;
wd3 <= x"88888999";
wait for 10 ns;
wd3 <= x"66ff1010";
wait for 5 ns;
wd3 <= x"44ff8acc";
wait for 5 ns;
wd3 <= x"67bfaf11";
wait for 5 ns;
end process;
process
begin
wa3 <= "00001";
ra1 <= "00001";
ra2 <= "11111";
wait for 5 ns;
wa3 <= "00010";
ra1 <= "00110";
ra2 <= "00010";
wait for 5 ns;
wa3 <= "11111";
ra1 <= "00010";
ra2 <= "11111";
wait for 5 ns;
wa3 <= "10100";
ra1 <= "10100";
ra2 <= "00011";
wait for 5 ns;
wa3 <= "00011";
ra1 <= "00011";
ra2 <= "10100";
wait for 5 ns;
wa3 <= "00110";
ra1 <= "10100";
ra2 <= "00000";
wait for 5 ns;
end process;
end architecture;
|
-- Generation properties:
-- Format : hierarchical
-- Generic mappings : exclude
-- Leaf-level entities : direct binding
-- Regular libraries : use library name
-- View name : include
--
LIBRARY lab10_RegFile_lib;
CONFIGURATION RegReadWrite_Mixed_config OF RegReadWrite IS
FOR Mixed
FOR ALL : Reg
USE ENTITY lab10_RegFile_lib.Reg(Behavior);
END FOR;
END FOR;
END RegReadWrite_Mixed_config;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clock_50 : in std_logic;
sma_clkout : out std_ulogic;
errorn : out std_logic;
fl_addr : out std_logic_vector(22 downto 0);
fl_dq : inout std_logic_vector(7 downto 0);
dram_addr : out std_logic_vector(12 downto 0);
dram_ba : out std_logic_vector(1 downto 0);
dram_dq : inout std_logic_vector(31 downto 0);
dram_clk : out std_logic;
dram_cke : out std_logic;
dram_cs_n : out std_logic;
dram_we_n : out std_logic; -- sdram write enable
dram_ras_n : out std_logic; -- sdram ras
dram_cas_n : out std_logic; -- sdram cas
dram_dqm : out std_logic_vector (3 downto 0); -- sdram dqm
uart_txd : out std_logic; -- DSU tx data
uart_rxd : in std_logic; -- DSU rx data
dsubre : in std_logic;
dsuact : out std_logic;
fl_oe_n : out std_logic;
fl_we_n : out std_logic;
fl_rst_n : out std_logic;
fl_wp_n : out std_logic;
fl_ce_n : out std_logic;
-- gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
gpio : inout std_logic_vector(35 downto 0); -- I/O port
enet0_mdio : inout std_logic; -- ethernet PHY interface
enet0_gtx_clk : in std_logic;
enet0_rx_clk : in std_logic;
enet0_tx_clk : in std_logic;
enet0_rx_data: in std_logic_vector(3 downto 0);
enet0_rx_dv : in std_logic;
enet0_rx_er : in std_logic;
enet0_rx_col : in std_logic;
enet0_rx_crs : in std_logic;
enet0_int_n : in std_logic;
enet0_rst_n : out std_logic;
enet0_tx_data: out std_logic_vector(3 downto 0);
enet0_tx_en : out std_logic;
enet0_tx_er : out std_logic;
enet0_mdc : out std_logic;
can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
can_stb : out std_logic_vector(0 to CFG_CAN_NUM-1);
sw : in std_logic_vector(0 to 2) := "000"
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal spii, spislvi : spi_in_type;
signal spio, spislvo : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal stati : ahbstat_in_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal ethclk, egtx_clk_fb : std_logic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock : std_ulogic;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal dsubren : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal tck, tms, tdi, tdo : std_logic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
constant OEPOL : integer := padoen_polarity(padtech);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep : boolean;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN,
noclkfb => CFG_CLK_NOFB, freq => BOARD_FREQ, clk2xen => 1)
port map (clkin => clock_50, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => sma_clkout, sdclk => sdclkl, pciclk => open,
cgi => cgi, cgo => cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1)
port map (dram_clk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn, rstraw);
clklock <= cgo.clklock and elock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SPI2AHB+CFG_GRETH,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
leon3 : leon3x -- LEON3 processor
generic map (
hindex => i,
fabtech => fabtech,
memtech => memtech,
nwindows => CFG_NWIN,
dsu => CFG_DSU,
fpu => CFG_FPU + 32*CFG_GRFPUSH,
v8 => CFG_V8,
cp => 0,
mac => CFG_MAC,
pclow => pclow,
notag => CFG_NOTAG,
nwp => CFG_NWP,
icen => CFG_ICEN,
irepl => CFG_IREPL,
isets => CFG_ISETS,
ilinesize => CFG_ILINE,
isetsize => CFG_ISETSZ,
isetlock => CFG_ILOCK,
dcen => CFG_DCEN,
drepl => CFG_DREPL,
dsets => CFG_DSETS,
dlinesize => CFG_DLINE,
dsetsize => CFG_DSETSZ,
dsetlock => CFG_DLOCK,
dsnoop => CFG_DSNOOP,
ilram => CFG_ILRAMEN,
ilramsize => CFG_ILRAMSZ,
ilramstart => CFG_ILRAMADDR,
dlram => CFG_DLRAMEN,
dlramsize => CFG_DLRAMSZ,
dlramstart => CFG_DLRAMADDR,
mmuen => CFG_MMUEN,
itlbnum => CFG_ITLBNUM,
dtlbnum => CFG_DTLBNUM,
tlb_type => CFG_TLB_TYPE,
tlb_rep => CFG_TLB_REP,
lddel => CFG_LDDEL,
disas => disas,
tbuf => CFG_ITBSZ,
pwd => CFG_PWD,
svt => CFG_SVT,
rstaddr => CFG_RSTADDR,
smp => CFG_NCPU-1,
iuft => CFG_IUFT_EN,
fpft => CFG_FPUFT_EN,
cmft => CFG_CACHE_FT_EN,
iuinj => CFG_RF_ERRINJ,
ceinj => CFG_CACHE_ERRINJ,
cached => CFG_DFIXED,
clk2x => 0,
netlist => CFG_LEON3_NETLIST,
scantest => CFG_SCAN,
mmupgsz => CFG_MMU_PAGE,
bp => CFG_BP,
npasi => CFG_NP_ASI)
port map (
clk => clkm, gclk2 => clkm, gfclk2 => clkm, clk2 => clkm, rstn => rstn,
ahbi => ahbmi, ahbo => ahbmo(i), ahbsi => ahbsi, ahbso => ahbso,
irqi => irqi(i), irqo => irqo(i), dbgi => dbgi(i), dbgo => dbgo(i),
fpui => fpi(i), fpuo => fpo(i), clken => vcc(0));
end generate;
sh : if CFG_GRFPUSH /= 0 generate
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
nosh : if CFG_GRFPUSH = 0 generate
fpo <= (others => grfpu_out_none);
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsubren);
dsui.break <= not dsubren;
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dui.rxd <= uart_rxd when sw(0) = '0' else '1';
-- dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.edac <= '0'; memi.bwidth <= "00";
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, oepol => OEPOL, iomask => 0,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 23, tech => padtech)
port map (fl_addr, memo.address(22 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (fl_ce_n, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (fl_oe_n, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (fl_we_n, memo.writen);
fl_rst_pad : outpad generic map (tech => padtech)
port map (fl_rst_n, rstn);
fl_wp_pad : outpad generic map (tech => padtech)
port map (fl_wp_n, vcc(0));
data_pad : iopadvv generic map (tech => padtech, width => 8, oepol => OEPOL)
port map (fl_dq, memo.data(31 downto 24), memo.vbdrive(31 downto 24), memi.data(31 downto 24));
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111";
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 13)
port map (dram_addr, memo.sa(12 downto 0));
ba_pad : outpadv generic map (width => 2)
port map (dram_ba, memo.sa(14 downto 13));
sd_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (dram_dq(31 downto 0), memo.sddata(31 downto 0),
memo.svbdrive(31 downto 0), memi.sd(31 downto 0));
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (dram_we_n, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (dram_ras_n, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (dram_cas_n, sdo.casn);
sddqm_pad : outpadv generic map (width => 4, tech => padtech)
port map (dram_dqm, sdo.dqm(3 downto 0));
sdcke_pad : outpad generic map (tech => padtech)
port map (dram_cke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (dram_cs_n, sdo.sdcsn(0));
end generate;
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech)
port map (dram_cke, vcc(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (dram_cs_n, vcc(0));
end generate;
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- No PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (fl_ce_n, vcc(0));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= '1' when sw(0) = '0' else uart_rxd; u1i.ctsn <= '0'; u1i.extclk <= '0';
end generate;
uart_txd <= u1o.txd when sw(0) = '1' else duo.txd;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
-- apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
-- notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 10, paddr => 10, pmask => 16#fff#, pirq => 10,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(10), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
miso_pad : iopad generic map (tech => padtech)
port map (gpio(35), spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (gpio(34), spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (gpio(33), spio.sck, spio.sckoen, spii.sck);
slvsel_pad : iopad generic map (tech => padtech)
port map (gpio(32), slvsel(0), gnd(0), open);
end generate spic;
spibridge : if CFG_SPI2AHB /= 0 generate -- SPI to AHB bridge
withapb : if CFG_SPI2AHB_APB /= 0 generate
spi2ahb0 : spi2ahb_apb
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
ahbaddrh => CFG_SPI2AHB_ADDRH, ahbaddrl => CFG_SPI2AHB_ADDRL,
ahbmaskh => CFG_SPI2AHB_MASKH, ahbmaskl => CFG_SPI2AHB_MASKL,
resen => CFG_SPI2AHB_RESEN, pindex => 11, paddr => 11, pmask => 16#fff#,
pirq => 11, filter => CFG_SPI2AHB_FILTER, cpol => CFG_SPI2AHB_CPOL,
cpha => CFG_SPI2AHB_CPHA)
port map (rstn, clkm, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi, apbo(11), spislvi, spislvo);
end generate;
woapb : if CFG_SPI2AHB_APB = 0 generate
spi2ahb0 : spi2ahb
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
ahbaddrh => CFG_SPI2AHB_ADDRH, ahbaddrl => CFG_SPI2AHB_ADDRL,
ahbmaskh => CFG_SPI2AHB_MASKH, ahbmaskl => CFG_SPI2AHB_MASKL,
filter => CFG_SPI2AHB_FILTER,
cpol => CFG_SPI2AHB_CPOL, cpha => CFG_SPI2AHB_CPHA)
port map (rstn, clkm, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
spislvi, spislvo);
end generate;
spislv_miso_pad : iopad generic map (tech => padtech)
port map (gpio(31), spislvo.miso, spislvo.misooen, spislvi.miso);
spislvl_mosi_pad : iopad generic map (tech => padtech)
port map (gpio(30), spislvo.mosi, spislvo.mosioen, spislvi.mosi);
spislv_sck_pad : iopad generic map (tech => padtech)
port map (gpio(29), spislvo.sck, spislvo.sckoen, spislvi.sck);
spislv_slvsel_pad : iopad generic map (tech => padtech)
port map (gpio(28), gnd(0), vcc(0), spislvi.spisel);
end generate;
nospibridge : if CFG_SPI2AHB = 0 or CFG_SPI2AHB_APB = 0 generate
apbo(11) <= apb_none;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SPI2AHB,
pindex => 14, paddr => 14, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 16,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(
rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SPI2AHB),
apbi => apbi, apbo => apbo(14), ethi => ethi, etho => etho);
greth1g: if CFG_GRETH1G = 1 generate
eth_macclk_pad : clkpad
generic map (tech => padtech, arch => 3, hf => 1)
port map (enet0_gtx_clk, egtx_clk, cgo.clklock, elock);
end generate greth1g;
emdio_pad : iopad generic map (tech => padtech)
port map (enet0_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (enet0_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (enet0_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (enet0_rx_data, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (enet0_rx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (enet0_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (enet0_rx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (enet0_rx_crs, ethi.rx_crs);
emdintn_pad : inpad generic map (tech => padtech)
port map (enet0_int_n, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (enet0_tx_data, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (enet0_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (enet0_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (enet0_mdc, etho.mdc);
eth0_rst_pad : odpad generic map (tech => padtech)
port map (enet0_rst_n, rstn);
-- emdis_pad : outpad generic map (tech => padtech)
-- port map (emddis, vcc(0));
-- eepwrdwn_pad : outpad generic map (tech => padtech)
-- port map (epwrdwn, gnd(0));
-- esleep_pad : outpad generic map (tech => padtech)
-- port map (esleep, gnd(0));
-- epause_pad : outpad generic map (tech => padtech)
-- port map (epause, gnd(0));
-- ereset_pad : outpad generic map (tech => padtech)
-- port map (ereset, gnd(0));
ethi.gtx_clk <= egtx_clk;
end generate;
noeth: if CFG_GRETH = 0 or CFG_GRETH1G = 0 generate
elock <= '1';
end generate noeth;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
can_pads : for i in 0 to CFG_CAN_NUM-1 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd(i), can_ltx(i));
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd(i), can_lrx(i));
end generate;
end generate;
-- can_stb <= '0'; -- no standby
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
-- ocram : if CFG_AHBRAMEN = 1 generate
-- ahbram0 : ftahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
-- tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pindex => 6,
-- paddr => 6, edacen => CFG_AHBRAEDAC, autoscrub => CFG_AHBRASCRU,
-- errcnten => CFG_AHBRAECNT, cntbits => CFG_AHBRAEBIT)
-- port map ( rstn, clkm, ahbsi, ahbso(7), apbi, apbo(6), open);
-- end generate;
--
-- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+log2x(CFG_PCI)-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 7, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(7));
-- pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 TerAsic DE2_115 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: toutpad_tm, toutpad_tmvv
-- File: toutpad_tm.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Tech map for IO pad with built-in test mux
------------------------------------------------------------------------------
-- This is implemented recursively by passing in the test signals via the cfgi
-- input for technologies that support it, and muxing manually for others.
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allpads.all;
entity toutpad_tm is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic;
test: in std_ulogic; ti,ten : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of toutpad_tm is
signal mi,men: std_ulogic;
signal mcfgi: std_logic_vector(19 downto 0);
begin
notm: if has_tm_pads(tech)=0 generate
mi <= ti when test='1' else i;
men <= ten when test='1' else en;
mcfgi <= cfgi;
end generate;
hastm: if has_tm_pads(tech)/=0 generate
mi <= i;
men <= en;
mcfgi <= cfgi(19 downto 3) & ti & ten & test;
end generate;
p: toutpad
generic map (tech => tech, level => level, slew => slew,
voltage => voltage, strength => strength,
oepol => oepol)
port map (pad => pad, i => mi, en => men, cfgi => mcfgi);
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpad_tmvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
test: in std_ulogic;
ti : in std_logic_vector(width-1 downto 0);
ten : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of toutpad_tmvv is
begin
v : for j in width-1 downto 0 generate
x0 : toutpad_tm generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en(j), test, ti(j), ten(j), cfgi);
end generate;
end;
|
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`protect end_protected
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_1;
USE fir_compiler_v7_1.fir_compiler_v7_1;
ENTITY half_band_FIR IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END half_band_FIR;
ARCHITECTURE half_band_FIR_arch OF half_band_FIR IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF half_band_FIR_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF half_band_FIR_arch: ARCHITECTURE IS "fir_compiler_v7_1,Vivado 2014.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF half_band_FIR_arch : ARCHITECTURE IS "half_band_FIR,fir_compiler_v7_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF half_band_FIR_arch: ARCHITECTURE IS "half_band_FIR,fir_compiler_v7_1,{x_ipProduct=Vivado 2014.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fir_compiler,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_COMPONENT_NAME=half_band_FIR,C_COEF_FILE=half_band_FIR.mif,C_COEF_FILE_LINES=5,C_FILTER_TYPE=7,C_INTERP_RATE=1,C_DECIM_RATE=2,C_ZERO_PACKING_FACTOR=1,C_SYMMETRY=1,C_NUM_FILTS=1,C_NUM_TAPS=15,C_NUM_CHANNELS=1,C_CHANNEL_PATTERN=fixed,C_ROUND_MODE=1,C_COEF_RELOAD=0,C_NUM_RELOAD_SLOTS=1,C_COL_MODE=1,C_COL_PIPE_LEN=4,C_COL_CONFIG=1,C_OPTIMIZATION=0,C_DATA_PATH_WIDTHS=22,C_DATA_IP_PATH_WIDTHS=22,C_DATA_PX_PATH_WIDTHS=22,C_DATA_WIDTH=22,C_COEF_PATH_WIDTHS=15,C_COEF_WIDTH=15,C_DATA_PATH_SRC=0,C_COEF_PATH_SRC=0,C_DATA_PATH_SIGN=0,C_COEF_PATH_SIGN=0,C_ACCUM_PATH_WIDTHS=38,C_OUTPUT_WIDTH=22,C_OUTPUT_PATH_WIDTHS=22,C_ACCUM_OP_PATH_WIDTHS=38,C_EXT_MULT_CNFG=none,C_DATA_PATH_PSAMP_SRC=0,C_OP_PATH_PSAMP_SRC=0,C_NUM_MADDS=1,C_OPT_MADDS=none,C_OVERSAMPLING_RATE=5,C_INPUT_RATE=16,C_OUTPUT_RATE=32,C_DATA_MEMTYPE=0,C_COEF_MEMTYPE=2,C_IPBUFF_MEMTYPE=2,C_OPBUFF_MEMTYPE=0,C_DATAPATH_MEMTYPE=2,C_MEM_ARRANGEMENT=1,C_DATA_MEM_PACKING=0,C_COEF_MEM_PACKING=0,C_FILTS_PACKED=0,C_LATENCY=42,C_HAS_ARESETn=0,C_HAS_ACLKEN=0,C_DATA_HAS_TLAST=0,C_S_DATA_HAS_FIFO=1,C_S_DATA_HAS_TUSER=0,C_S_DATA_TDATA_WIDTH=24,C_S_DATA_TUSER_WIDTH=1,C_M_DATA_HAS_TREADY=0,C_M_DATA_HAS_TUSER=0,C_M_DATA_TDATA_WIDTH=24,C_M_DATA_TUSER_WIDTH=1,C_HAS_CONFIG_CHANNEL=0,C_CONFIG_SYNC_MODE=0,C_CONFIG_PACKET_SIZE=0,C_CONFIG_TDATA_WIDTH=1,C_RELOAD_TDATA_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_1
GENERIC MAP (
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "half_band_FIR",
C_COEF_FILE => "half_band_FIR.mif",
C_COEF_FILE_LINES => 5,
C_FILTER_TYPE => 7,
C_INTERP_RATE => 1,
C_DECIM_RATE => 2,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 15,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 1,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "1",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "22",
C_DATA_IP_PATH_WIDTHS => "22",
C_DATA_PX_PATH_WIDTHS => "22",
C_DATA_WIDTH => 22,
C_COEF_PATH_WIDTHS => "15",
C_COEF_WIDTH => 15,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "38",
C_OUTPUT_WIDTH => 22,
C_OUTPUT_PATH_WIDTHS => "22",
C_ACCUM_OP_PATH_WIDTHS => "38",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 1,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 5,
C_INPUT_RATE => 16,
C_OUTPUT_RATE => 32,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 2,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 42,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 24,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 24,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END half_band_FIR_arch;
|
--
-- Authors: Francisco Paiva Knebel
-- Gabriel Alexandre Zillmer
--
-- Universidade Federal do Rio Grande do Sul
-- Instituto de Informática
-- Sistemas Digitais
-- Prof. Fernanda Lima Kastensmidt
--
-- Create Date: 23:58:40 05/02/2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg8bits is
port (
data_in : in STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
load : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0)
);
end reg8bits;
architecture Behavioral of reg8bits is
signal reg : std_logic_vector (7 downto 0);
constant reg_delay: TIME := 2 ns;
begin
process (clk, rst)
begin
if (rst = '1') then
reg <= "00000000";
elsif (clk = '1' and clk'EVENT) then
if (load = '1') then
reg <= data_in;
end if;
end if;
end process;
data_out <= reg;
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all; -- or_reduce()
use work.trfsmparts.all;
entity InputSwitchingMatrix is
generic (
InputWidth : integer range 1 to 256;
OutputWidth : integer range 1 to 256
);
port (
Reset_n_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
-- Configuration
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic
);
end InputSwitchingMatrix;
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all; -- or_reduce()
use work.trfsmparts.all;
entity InputSwitchingMatrix is
generic (
InputWidth : integer range 1 to 256;
OutputWidth : integer range 1 to 256
);
port (
Reset_n_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
-- Configuration
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic
);
end InputSwitchingMatrix;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 06-05-2016
-- Module Name: p4-1.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity logic1 is
port (A, B, C : in std_logic;
F : out std_logic);
end logic1;
architecture behavioral of logic1 is
begin
process(A,B,C) begin
if A = '1' then
F<= '1';
elsif B = '1' and C = '1' then
F <= '0';
-- providing else clause in order to
-- preventing from transparent latch
-- creation.
else
F <= 'X';
end if;
end process;
end behavioral;
|
-----------------------------------------------------------
-- Default Libs
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
-- My libs
-- USE work.my_functions.all
-----------------------------------------------------------
ENTITY UartTransmitter IS
PORT (
clk : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
send : IN STD_LOGIC;
rdy : OUT STD_LOGIC := '1';
TXD : OUT STD_LOGIC := '1'
);
END ENTITY;
-----------------------------------------------------------
ARCHITECTURE structure OF UartTransmitter IS
SIGNAL running : STD_LOGIC := '0';
SIGNAL s_data : STD_LOGIC_VECTOR (0 TO 9);
BEGIN
PROCESS (clk)
VARIABLE outBit : INTEGER RANGE -1 to 9 := -1;
BEGIN
IF clk'EVENT AND clk='1' THEN
IF send = '1' AND running = '0' THEN
s_data(1 TO 8) <= data;
s_data(9) <= '0'; -- Start bit
s_data(0) <= '1'; -- Stop bit
outBit := 9;
rdy <= '0';
running <= '1';
ELSIF running = '1' AND outBit >= 0 THEN
TXD <= s_data(outBit);
outBit := outBit-1;
ELSE
running <= '0';
rdy <= '1';
END IF;
END IF;
END PROCESS;
END ARCHITECTURE structure; |
architecture RTL of ENT is
begin
end;
ARCHITECTURE RTL of ENT is
begin
end;
ArChItEcTuRe RTL of ENT is
begin
end;
|
architecture RTL of ENT is
begin
end;
ARCHITECTURE RTL of ENT is
begin
end;
ArChItEcTuRe RTL of ENT is
begin
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1251.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n02i01251ent IS
END c08s02b00x00p04n02i01251ent;
ARCHITECTURE c08s02b00x00p04n02i01251arch OF c08s02b00x00p04n02i01251ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "Report this Note"
severity fatal;
assert FALSE
report "***FAILED TEST: c08s02b00x00p04n02i01251 - Predefined severity_level type with non-existent value"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n02i01251arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1251.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n02i01251ent IS
END c08s02b00x00p04n02i01251ent;
ARCHITECTURE c08s02b00x00p04n02i01251arch OF c08s02b00x00p04n02i01251ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "Report this Note"
severity fatal;
assert FALSE
report "***FAILED TEST: c08s02b00x00p04n02i01251 - Predefined severity_level type with non-existent value"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n02i01251arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1251.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n02i01251ent IS
END c08s02b00x00p04n02i01251ent;
ARCHITECTURE c08s02b00x00p04n02i01251arch OF c08s02b00x00p04n02i01251ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "Report this Note"
severity fatal;
assert FALSE
report "***FAILED TEST: c08s02b00x00p04n02i01251 - Predefined severity_level type with non-existent value"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n02i01251arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlslice:1.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlslice;
ENTITY RAT_xlslice_0_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END RAT_xlslice_0_0;
ARCHITECTURE RAT_xlslice_0_0_arch OF RAT_xlslice_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_xlslice_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlslice IS
GENERIC (
DIN_WIDTH : INTEGER;
DIN_FROM : INTEGER;
DIN_TO : INTEGER
);
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT xlslice;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_xlslice_0_0_arch: ARCHITECTURE IS "xlslice,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_xlslice_0_0_arch : ARCHITECTURE IS "RAT_xlslice_0_0,xlslice,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_xlslice_0_0_arch: ARCHITECTURE IS "RAT_xlslice_0_0,xlslice,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DIN_WIDTH=18,DIN_FROM=12,DIN_TO=3}";
BEGIN
U0 : xlslice
GENERIC MAP (
DIN_WIDTH => 18,
DIN_FROM => 12,
DIN_TO => 3
)
PORT MAP (
Din => Din,
Dout => Dout
);
END RAT_xlslice_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlslice:1.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlslice;
ENTITY RAT_xlslice_0_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END RAT_xlslice_0_0;
ARCHITECTURE RAT_xlslice_0_0_arch OF RAT_xlslice_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_xlslice_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlslice IS
GENERIC (
DIN_WIDTH : INTEGER;
DIN_FROM : INTEGER;
DIN_TO : INTEGER
);
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT xlslice;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_xlslice_0_0_arch: ARCHITECTURE IS "xlslice,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_xlslice_0_0_arch : ARCHITECTURE IS "RAT_xlslice_0_0,xlslice,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_xlslice_0_0_arch: ARCHITECTURE IS "RAT_xlslice_0_0,xlslice,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DIN_WIDTH=18,DIN_FROM=12,DIN_TO=3}";
BEGIN
U0 : xlslice
GENERIC MAP (
DIN_WIDTH => 18,
DIN_FROM => 12,
DIN_TO => 3
)
PORT MAP (
Din => Din,
Dout => Dout
);
END RAT_xlslice_0_0_arch;
|
-------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : disp_lut.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-05-17
-- Last update: 2018-04-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Display controller look up table
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-17 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--library work;
--use work.util_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;
entity disp_lut is
port (
rst_n : in std_logic;
clk : in std_logic;
sram_addr : in std_logic_vector(9 downto 0);
sram_we : in std_logic;
sram_datao : in std_logic_vector(31 downto 0);
sram_datai : out std_logic_vector(31 downto 0);
lut_addr : in std_logic_vector(11 downto 0);
lut_data : out std_logic_vector(7 downto 0)
);
end disp_lut;
architecture structure of disp_lut is
SIGNAL rst : std_logic;
begin
rst <= not rst_n;
-- BRAM_TDP_MACRO: True Dual Port RAM
-- 7 Series
-- Xilinx HDL Libraries Guide, version 2014.4
-- Note - This Unimacro model assumes the port directions to be "downto".
-- Simulation of this model with "to" in the port directions could lead to erroneous results.
--------------------------------------------------------------------------
-- DATA_WIDTH_A/B | BRAM_SIZE | RAM Depth | ADDRA/B Width | WEA/B Width --
-- ===============|===========|===========|===============|=============--
-- 19-36 | "36Kb" | 1024 | 10-bit | 4-bit --
-- 10-18 | "36Kb" | 2048 | 11-bit | 2-bit --
-- 10-18 | "18Kb" | 1024 | 10-bit | 2-bit --
-- 5-9 | "36Kb" | 4096 | 12-bit | 1-bit --
-- 5-9 | "18Kb" | 2048 | 11-bit | 1-bit --
-- 3-4 | "36Kb" | 8192 | 13-bit | 1-bit --
-- 3-4 | "18Kb" | 4096 | 12-bit | 1-bit --
-- 2 | "36Kb" | 16384 | 14-bit | 1-bit --
-- 2 | "18Kb" | 8192 | 13-bit | 1-bit --
-- 1 | "36Kb" | 32768 | 15-bit | 1-bit --
-- 1 | "18Kb" | 16384 | 14-bit | 1-bit --
--------------------------------------------------------------------------
BRAM_TDP_MACRO_inst : BRAM_TDP_MACRO
generic map (
BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
DOA_REG => 0, -- Optional port A output register (0 or 1)
DOB_REG => 0, -- Optional port B output register (0 or 1)
INIT_A => X"000000000", -- Initial values on A output port
INIT_B => X"000000000", -- Initial values on B output port
INIT_FILE => "NONE",
READ_WIDTH_A => 32, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
READ_WIDTH_B => 8, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY",
-- "GENERATE_X_ONLY" or "NONE"
SRVAL_A => X"000000000", -- Set/Reset value for A port output
SRVAL_B => X"000000000", -- Set/Reset value for B port output
WRITE_MODE_A => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
WRITE_MODE_B => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
WRITE_WIDTH_A => 32, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
WRITE_WIDTH_B => 8, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
-- The following INIT_xx declarations specify the initial contents of the RAM
INIT_00 => X"000000000000000000000064006300530075006e00380038002000470050004c",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"00220023002400250026002700280029002a002b002c002d002e002f00300031",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000200021",
INIT_04 => X"003400350036003700380039003a003b003c003d003e003f0040004100420043",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000320033",
INIT_06 => X"0046004700480049004a004b004c004d004e004f005000510052005300540055",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000440045",
INIT_08 => X"00580059005a005b005c005d005e005f00600061006200630064006500660067",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000560057",
INIT_0A => X"006a006b006c006d006e006f0070007100720073007400750076007700780079",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000680069",
INIT_0C => X"007c007d007e007f002000200020002000200020002000200020002000200020",
INIT_0D => X"00000000000000000000000000000000000000000000000000000000007a007b",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0020002000200020002000880087002000860085002000840183008200810080",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000200020",
INIT_12 => X"0020002000200020008800870020008600850020008401830082008100800020",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000200020",
INIT_14 => X"0020002000200088008700200086008500200084018300820081008000200020",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000200020",
INIT_16 => X"0020002000880087002000860085002000840183008200810080002000200020",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000200020",
INIT_18 => X"0020008800870020008600850020008401830082008100800020002000200020",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000200020",
INIT_1A => X"0088008700200086008500200084018300820081008000200020002000200020",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000200020",
INIT_1C => X"0087002000860085002000840183008200810080002000200020002000200020",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000200088",
INIT_1E => X"0020008600850020008401830082008100800020002000200020002000200020",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000880087",
INIT_20 => X"0086008500200084018300820081008000200020002000200020002000200088",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000870020",
INIT_22 => X"0085002000840183008200810080002000200020002000200020002000880087",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000200086",
INIT_24 => X"0020008401830082008100800020002000200020002000200020008800870020",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000860085",
INIT_26 => X"0084018300820081008000200020002000200020002000200088008700200086",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000850020",
INIT_28 => X"0183008200810080002000200020002000200020002000880087002000860085",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000200084",
INIT_2A => X"0082008100800020002000200020002000200020008800870020008600850020",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000840183",
INIT_2C => X"0081008000200020002000200020002000200088008700200086008500200084",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000001830082",
INIT_2E => X"0080002000200020002000200020002000880087002000860085002000840183",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000820081",
INIT_30 => X"0020002000200020002000200020008800870020008600850020008401830082",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000810080",
INIT_32 => X"0020002000200020002000200088008700200086008500200084018300820081",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000800020",
INIT_34 => X"002000470050004c002000470050004c002000470050004c002000470050004c",
INIT_35 => X"002000470050004c002000470050004c002000470050004c002000470050004c",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"000000000000000000000064006300530075006e00380038002000470050004c",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0020008800870020008600850020008401830082008100800020002000200020",
INIT_3D => X"0020002000200020002000200020002000200020002000200020002000200020",
INIT_3E => X"0138013801380138013801380138013801380138013801380138013801380138",
INIT_3F => X"0138013801380138013801380138013801380138013801380138013801380138",
-- The next set of INIT_xx are valid when configured as 36Kb
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"ca0012000000f6fee0beb666f2da60fc00010200000000000400000000440000",
INIT_42 => X"1000000000da766e547c7c1eb6ccd6cefceca81cae780c6ebc8e9e7a9cfeee00",
INIT_43 => X"0080000000da766e4438381eb60ae6ce3a2a280cae30082ef68ede7a1a3efa40",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- The next set of INITP_xx are for the parity bits
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- The next set of INIT_xx are valid when configured as 36Kb
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DOA => sram_datai, -- Output port-A data, width defined by READ_WIDTH_A parameter
DOB => lut_data, -- Output port-B data, width defined by READ_WIDTH_B parameter
ADDRA => sram_addr, -- Input port-A address, width defined by Port A depth
ADDRB => lut_addr, -- Input port-B address, width defined by Port B depth
CLKA => clk, -- 1-bit input port-A clock
CLKB => clk, -- 1-bit input port-B clock
DIA => sram_datao, -- Input port-A data, width defined by WRITE_WIDTH_A parameter
DIB => x"00", -- Input port-B data, width defined by WRITE_WIDTH_B parameter
ENA => '1', -- 1-bit input port-A enable
ENB => '1', -- 1-bit input port-B enable
REGCEA => '1', -- 1-bit input port-A output register enable
REGCEB => '1', -- 1-bit input port-B output register enable
RSTA => rst, -- 1-bit input port-A reset
RSTB => rst, -- 1-bit input port-B reset
WEA(0) => sram_we, -- Input port-A write enable, width defined by Port A depth
WEA(1) => sram_we, -- Input port-A write enable, width defined by Port A depth
WEA(2) => sram_we, -- Input port-A write enable, width defined by Port A depth
WEA(3) => sram_we, -- Input port-A write enable, width defined by Port A depth
WEB => "0" -- Input port-B write enable, width defined by Port B depth
);
-- End of BRAM_TDP_MACRO_inst instantiation
end structure;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Josh Tombs
--
-- Create Date: SPRING 2015
-- Module Name: Register Bank
-- Project Name: UMD_RISC16
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Create a register bank to hold m
-- registers of size n bits.
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity register_bank is
GENERIC ( M : INTEGER := 16; --Number of registers
N : INTEGER := 16; --Size of registers
A : INTEGER := 4); --Size of Addresses
Port( CLK : in STD_LOGIC;
ADDR_A : in STD_LOGIC_VECTOR (A-1 downto 0);
ADDR_B : in STD_LOGIC_VECTOR (A-1 downto 0);
W_ADDR : in STD_LOGIC_VECTOR (A-1 downto 0);
R_W : in STD_LOGIC; -- 0 = read, 1 = write
ENB : in STD_LOGIC;
DATA_IN : in STD_LOGIC_VECTOR (N-1 downto 0);
REG_A : out STD_LOGIC_VECTOR (N-1 downto 0);
REG_B : out STD_LOGIC_VECTOR (N-1 downto 0));
end register_bank;
architecture Behavioral of register_bank is
type bank_type is array (0 to M-1) of std_logic_vector (N-1 downto 0);
signal bank: bank_type := (others=> (others=>'0')); -- initialize all registers to "0000"
begin
PROCESS(CLK, ENB, R_W)
begin
if (CLK'EVENT and CLK = '1') then --rising edge event (read)
if(ENB = '1') then --enabled and read
REG_A <= bank(to_integer(unsigned(ADDR_A)));
REG_B <= bank(to_integer(unsigned(ADDR_B)));
end if;
end if;
end PROCESS;
PROCESS(CLK, ENB, R_W)
begin
if (CLK'EVENT and CLK = '0') then --falling edge event (write)
if(ENB = '1' and R_W = '1') then --enabled and write
bank(to_integer(unsigned(W_ADDR))) <= DATA_IN;
end if;
end if;
end PROCESS;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1925.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01925ent IS
END c07s02b01x00p01n01i01925ent;
ARCHITECTURE c07s02b01x00p01n01i01925arch OF c07s02b01x00p01n01i01925ent IS
BEGIN
TESTING: PROCESS
variable b1 : Boolean := TRUE;
BEGIN
b1 := b1 nor b1;
assert NOT(b1 = FALSE)
report "***PASSED TEST: c07s02b01x00p01n01i01925"
severity NOTE;
assert (b1 = FALSE)
report "***FAILED TEST: c07s02b01x00p01n01i01925 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01925arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1925.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01925ent IS
END c07s02b01x00p01n01i01925ent;
ARCHITECTURE c07s02b01x00p01n01i01925arch OF c07s02b01x00p01n01i01925ent IS
BEGIN
TESTING: PROCESS
variable b1 : Boolean := TRUE;
BEGIN
b1 := b1 nor b1;
assert NOT(b1 = FALSE)
report "***PASSED TEST: c07s02b01x00p01n01i01925"
severity NOTE;
assert (b1 = FALSE)
report "***FAILED TEST: c07s02b01x00p01n01i01925 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01925arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1925.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01925ent IS
END c07s02b01x00p01n01i01925ent;
ARCHITECTURE c07s02b01x00p01n01i01925arch OF c07s02b01x00p01n01i01925ent IS
BEGIN
TESTING: PROCESS
variable b1 : Boolean := TRUE;
BEGIN
b1 := b1 nor b1;
assert NOT(b1 = FALSE)
report "***PASSED TEST: c07s02b01x00p01n01i01925"
severity NOTE;
assert (b1 = FALSE)
report "***FAILED TEST: c07s02b01x00p01n01i01925 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01925arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D_Latch_Param is
port (
D : in std_logic;
Q, nQ : out std_logic
);
end D_Latch_Param;
architecture Struct of D_Latch_Param is
component nor2
port (
a, b: in std_logic;
z : out std_logic);
end component;
component inv
port (
a: in std_logic;
z: out std_logic);
end component;
signal t1, t2, t3 : std_logic;
begin
U1: inv port map (a => D, z => t3);
U2: nor2 port map (a => D, b => t2, z => t1);
U3: nor2 port map (a => t3, b => t1, z => t2);
Q <= t2 after 5 ns;
nQ <= t1 after 7 ns;
end Struct;
architecture Beh of D_Latch_Param is
signal q_t: std_logic;
begin
q_t <= D when q_t /= D;
Q <= q_t after 5 ns;
nQ <= not q_t after 7 ns;
end Beh; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_gen_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Behavioural memory generators
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic
);
end;
architecture behavioral of generic_syncram is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra : std_logic_vector((abits -1) downto 0);
begin
main : process(clk)
begin
if rising_edge(clk) then
if write = '1' then
memarr(conv_integer(address)) <= datain;
end if;
ra <= address;
end if;
end process;
dataout <= memarr(conv_integer(ra));
end;
-- synchronous 2-port ram, common clock
LIBRARY ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram_2p is
generic (
abits : integer := 8;
dbits : integer := 32;
sepclk: integer := 0
);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of generic_syncram_2p is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
signal rfd : dregtype;
signal wa, ra : std_logic_vector (abits -1 downto 0);
begin
wp : process(wclk)
begin
if rising_edge(wclk) then
if wren = '1' then rfd(conv_integer(wraddress)) <= data; end if;
end if;
end process;
oneclk : if sepclk = 0 generate
rp : process(wclk) begin
if rising_edge(wclk) then ra <= rdaddress; end if;
end process;
end generate;
twoclk : if sepclk = 1 generate
rp : process(rclk) begin
if rising_edge(rclk) then ra <= rdaddress; end if;
end process;
end generate;
q <= rfd(conv_integer(ra));
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_regfile_3p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32;
wrfst : integer := 0; numregs : integer := 40);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0)
);
end;
architecture rtl of generic_regfile_3p is
type mem is array(0 to numregs-1)
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra1, ra2, wa : std_logic_vector((abits -1) downto 0);
signal din : std_logic_vector((dbits -1) downto 0);
signal wr : std_ulogic;
begin
main : process(wclk)
begin
if rising_edge(wclk) then
din <= wdata; wr <= we;
if (we = '1')
-- pragma translate_off
and (conv_integer(waddr) < numregs)
-- pragma translate_on
then wa <= waddr; end if;
if (re1 = '1')
-- pragma translate_off
and (conv_integer(raddr1) < numregs)
-- pragma translate_on
then ra1 <= raddr1; end if;
if (re2 = '1')
-- pragma translate_off
and (conv_integer(raddr2) < numregs)
-- pragma translate_on
then ra2 <= raddr2; end if;
if wr = '1' then
memarr(conv_integer(wa)) <= din;
end if;
end if;
end process;
rdata1 <= din when (wr = '1') and (wa = ra1) and (wrfst = 1)
else memarr(conv_integer(ra1));
rdata2 <= din when (wr = '1') and (wa = ra2) and (wrfst = 1)
else memarr(conv_integer(ra2));
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_gen_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Behavioural memory generators
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic
);
end;
architecture behavioral of generic_syncram is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra : std_logic_vector((abits -1) downto 0);
begin
main : process(clk)
begin
if rising_edge(clk) then
if write = '1' then
memarr(conv_integer(address)) <= datain;
end if;
ra <= address;
end if;
end process;
dataout <= memarr(conv_integer(ra));
end;
-- synchronous 2-port ram, common clock
LIBRARY ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram_2p is
generic (
abits : integer := 8;
dbits : integer := 32;
sepclk: integer := 0
);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of generic_syncram_2p is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
signal rfd : dregtype;
signal wa, ra : std_logic_vector (abits -1 downto 0);
begin
wp : process(wclk)
begin
if rising_edge(wclk) then
if wren = '1' then rfd(conv_integer(wraddress)) <= data; end if;
end if;
end process;
oneclk : if sepclk = 0 generate
rp : process(wclk) begin
if rising_edge(wclk) then ra <= rdaddress; end if;
end process;
end generate;
twoclk : if sepclk = 1 generate
rp : process(rclk) begin
if rising_edge(rclk) then ra <= rdaddress; end if;
end process;
end generate;
q <= rfd(conv_integer(ra));
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_regfile_3p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32;
wrfst : integer := 0; numregs : integer := 40);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0)
);
end;
architecture rtl of generic_regfile_3p is
type mem is array(0 to numregs-1)
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra1, ra2, wa : std_logic_vector((abits -1) downto 0);
signal din : std_logic_vector((dbits -1) downto 0);
signal wr : std_ulogic;
begin
main : process(wclk)
begin
if rising_edge(wclk) then
din <= wdata; wr <= we;
if (we = '1')
-- pragma translate_off
and (conv_integer(waddr) < numregs)
-- pragma translate_on
then wa <= waddr; end if;
if (re1 = '1')
-- pragma translate_off
and (conv_integer(raddr1) < numregs)
-- pragma translate_on
then ra1 <= raddr1; end if;
if (re2 = '1')
-- pragma translate_off
and (conv_integer(raddr2) < numregs)
-- pragma translate_on
then ra2 <= raddr2; end if;
if wr = '1' then
memarr(conv_integer(wa)) <= din;
end if;
end if;
end process;
rdata1 <= din when (wr = '1') and (wa = ra1) and (wrfst = 1)
else memarr(conv_integer(ra1));
rdata2 <= din when (wr = '1') and (wa = ra2) and (wrfst = 1)
else memarr(conv_integer(ra2));
end;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_dgen
GENERIC MAP (
C_DIN_WIDTH => 1,
C_DOUT_WIDTH => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_dverif
GENERIC MAP (
C_DOUT_WIDTH => 1,
C_DIN_WIDTH => 1,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 1,
C_DIN_WIDTH => 1,
C_WR_PNTR_WIDTH => 5,
C_RD_PNTR_WIDTH => 5,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_exdes
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
----------------------------------------------------------------------------------
-- Company: Digilent Ro
-- Engineer: Elod Gyorgy
--
-- Create Date: 14:55:31 04/22/2011
-- Design Name:
-- Module Name: SSegDisp
-- Project Name: 7-segment Display Controller
-- Target Devices:
-- Tool versions:
-- Description: This module is able to drive a common-cathode multi-digit
-- 7-segment display.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.math_real.all;
entity SSegDisp is
generic (
CLOCKFREQ : natural := 100; -- in MHz
DIGITS : natural := 4
);
port (
CLK_I: in std_logic;
DATA_I: in std_logic_vector(DIGITS*4-1 downto 0);
DOTS_I: in std_logic_vector(DIGITS-1 downto 0);
AN_O: out std_logic_vector(DIGITS-1 downto 0);
CA_O: out std_logic_vector(7 downto 0)
);
end SSegDisp;
architecture Behavioral of SSegDisp is
constant DISP_FREQ : natural := 20 * DIGITS; --in kHz
constant DISP_FREQ_CYCLES : natural :=
natural(ceil(real(CLOCKFREQ*1_000/DISP_FREQ)));
signal refreshCnt : natural range 0 to DISP_FREQ_CYCLES-1 := 0;
signal DisplayCLK: std_logic;
signal DigitNo: natural range 0 to DIGITS-1 := 0;
signal Digit: std_logic_vector(3 downto 0);
signal HexDigit: std_logic_vector(6 downto 0);
signal Dot: std_logic;
begin
with Digit select
HexDigit <= "1000000" when "0000", --0
"1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" when "0011", --3
"0011001" when "0100", --4
"0010010" when "0101", --5
"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when "1111", --F
"0001001" when others; --H ???
Digit <= DATA_I(DigitNo*4+3 downto DigitNo*4);
-- Let's use Dots as active high and not confuse the user
Dot <= not DOTS_I(DigitNo);
CA_O <= Dot & HexDigit;
DIV_CLK_EN: process(CLK_I)
begin
if Rising_Edge(CLK_I) then
if (refreshCnt = DISP_FREQ_CYCLES-1) then
refreshCnt <= 0;
else
refreshCnt <= refreshCnt + 1;
end if;
end if;
end process;
CycleDIGITS: process(CLK_I)
begin
if Rising_Edge(CLK_I) then
if (refreshCnt = DISP_FREQ_CYCLES-1) then
if (DigitNo+1 = DIGITS) then
DigitNo <= 0;
else
DigitNo <= DigitNo+1;
end if;
end if;
end if;
end process CycleDIGITS;
SetAnodes: process(DigitNo)
begin
AN_O <= (others => '1');
AN_O(DigitNo) <= '0';
end process SetAnodes;
end Behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY muxproc IS
GENERIC (N : POSITIVE := 8);
PORT(
a, b, c, d, e, f, g, h, i, j : IN std_logic_vector(N-1 DOWNTO 0);
sel : IN std_logic_vector(3 DOWNTO 0);
S : OUT std_logic_vector(N-1 DOWNTO 0)
);
END ENTITY muxproc;
ARCHITECTURE Behavior OF muxproc IS
SIGNAL Qs : STD_LOGIC_VECTOR(N-1 DOWNTO 0);
BEGIN
mux : PROCESS(sel)
BEGIN
CASE sel IS
when "0000" =>
Qs <= a;
when "0001" =>
Qs <= b;
when "0010" =>
Qs <= c;
when "0011" =>
Qs <= d;
when "0100" =>
Qs <= e;
when "0101" =>
Qs <= f;
when "0110" =>
Qs <= g;
when "0111" =>
Qs <= h;
when "1000" =>
Qs <= i;
when "1001" =>
Qs <= j;
when others =>
NULL;
END CASE;
END PROCESS mux;
S <= Qs;
END ARCHITECTURE Behavior;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2916.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02916ent IS
END c02s01b01x02p03n01i02916ent;
ARCHITECTURE c02s01b01x02p03n01i02916arch OF c02s01b01x02p03n01i02916ent IS
procedure proc1 (signal S1: out bit) is
variable V1 : boolean;
begin
-- Failure_here : attribute QUIET may not be read within a procedure
V1 := S1'QUIET;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02916 - The attribute QUIET of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02916arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2916.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02916ent IS
END c02s01b01x02p03n01i02916ent;
ARCHITECTURE c02s01b01x02p03n01i02916arch OF c02s01b01x02p03n01i02916ent IS
procedure proc1 (signal S1: out bit) is
variable V1 : boolean;
begin
-- Failure_here : attribute QUIET may not be read within a procedure
V1 := S1'QUIET;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02916 - The attribute QUIET of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02916arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2916.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02916ent IS
END c02s01b01x02p03n01i02916ent;
ARCHITECTURE c02s01b01x02p03n01i02916arch OF c02s01b01x02p03n01i02916ent IS
procedure proc1 (signal S1: out bit) is
variable V1 : boolean;
begin
-- Failure_here : attribute QUIET may not be read within a procedure
V1 := S1'QUIET;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02916 - The attribute QUIET of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02916arch;
|
-- Project generated by script.
-- Date: Dom,20/01/2013-11:15:10
-- Author: rogerio
-- Comments: Entity Description: or2.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity or2 is
port (a, b: in std_logic; c: out std_logic);
end or2;
architecture logica of or2 is
begin
-- Commands.
c <= a or b;
end logica;
|
--
-- Input synchronization
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_input_sync is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end slib_input_sync;
architecture rtl of slib_input_sync is
signal iD : std_logic_vector(1 downto 0);
begin
IS_D: process (RST, CLK)
begin
if (RST = '1') then
iD <= (others => '0');
elsif (CLK'event and CLK='1') then
iD(0) <= D;
iD(1) <= iD(0);
end if;
end process;
-- Output ports
Q <= iD(1);
end rtl;
|
--
-- Input synchronization
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_input_sync is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end slib_input_sync;
architecture rtl of slib_input_sync is
signal iD : std_logic_vector(1 downto 0);
begin
IS_D: process (RST, CLK)
begin
if (RST = '1') then
iD <= (others => '0');
elsif (CLK'event and CLK='1') then
iD(0) <= D;
iD(1) <= iD(0);
end if;
end process;
-- Output ports
Q <= iD(1);
end rtl;
|
--
-- Input synchronization
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_input_sync is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end slib_input_sync;
architecture rtl of slib_input_sync is
signal iD : std_logic_vector(1 downto 0);
begin
IS_D: process (RST, CLK)
begin
if (RST = '1') then
iD <= (others => '0');
elsif (CLK'event and CLK='1') then
iD(0) <= D;
iD(1) <= iD(0);
end if;
end process;
-- Output ports
Q <= iD(1);
end rtl;
|
--
-- Input synchronization
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_input_sync is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end slib_input_sync;
architecture rtl of slib_input_sync is
signal iD : std_logic_vector(1 downto 0);
begin
IS_D: process (RST, CLK)
begin
if (RST = '1') then
iD <= (others => '0');
elsif (CLK'event and CLK='1') then
iD(0) <= D;
iD(1) <= iD(0);
end if;
end process;
-- Output ports
Q <= iD(1);
end rtl;
|
--
-- Input synchronization
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_input_sync is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end slib_input_sync;
architecture rtl of slib_input_sync is
signal iD : std_logic_vector(1 downto 0);
begin
IS_D: process (RST, CLK)
begin
if (RST = '1') then
iD <= (others => '0');
elsif (CLK'event and CLK='1') then
iD(0) <= D;
iD(1) <= iD(0);
end if;
end process;
-- Output ports
Q <= iD(1);
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity SeqEightBitAdder is
generic(WIDTH : integer := 8);
port(
SW: IN std_logic_vector(15 downto 0);
KEY0: IN std_logic;
LEDR: OUT std_logic_vector(8 downto 0)
);
end SeqEightBitAdder;
architecture impl of SeqEightBitAdder is
component OneBitAdder is
port(
A, B, CIN: IN std_logic;
S, COUT: OUT std_logic
);
end component;
signal c: std_logic_vector(8 downto 0);
signal outBuf: std_logic_vector(7 downto 0);
begin
c(0)<= '0';
SUM: for i in WIDTH - 1 downto 0 generate
ad : OneBitAdder port map(
SW(i), SW(i + 7), c(i), outBuf(i), c(i + 1) );
end generate;
process(KEY0)
begin
if rising_edge(KEY0) then
LEDR(7 downto 0) <= outBuf(7 downto 0);
LEDR(8) <= c(8);
end if;
end process;
end;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_05_07 is
end entity fg_05_07;
architecture test of fg_05_07 is
constant T_pw : time := 10 ns;
signal clk : bit;
begin
-- code from book
clock_gen : process is
begin
clk <= '1' after T_pw, '0' after 2*T_pw;
wait until clk = '0';
end process clock_gen;
-- end code from book
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_05_07 is
end entity fg_05_07;
architecture test of fg_05_07 is
constant T_pw : time := 10 ns;
signal clk : bit;
begin
-- code from book
clock_gen : process is
begin
clk <= '1' after T_pw, '0' after 2*T_pw;
wait until clk = '0';
end process clock_gen;
-- end code from book
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_05_07 is
end entity fg_05_07;
architecture test of fg_05_07 is
constant T_pw : time := 10 ns;
signal clk : bit;
begin
-- code from book
clock_gen : process is
begin
clk <= '1' after T_pw, '0' after 2*T_pw;
wait until clk = '0';
end process clock_gen;
-- end code from book
end architecture test;
|
--
-- FIFO First word fall through adapter. Part of libstorage
--
-- Copyright (C) 2015 Olof Kindgren <[email protected]>
--
-- Permission to use, copy, modify, and/or distribute this software for any
-- purpose with or without fee is hereby granted, provided that the above
-- copyright notice and this permission notice appear in all copies.
--
-- THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-- ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-- ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-- OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
--
library ieee;
use ieee.std_logic_1164.all;
entity fifo_fwft_adapter is
generic (
type data_type);
port (
clk : in std_ulogic;
rst : in std_ulogic;
fifo_rd_en_o : out std_ulogic;
fifo_rd_data_i : in data_type;
fifo_empty_i : in std_ulogic;
rd_en_i : in std_ulogic;
rd_data_o : out data_type;
empty_o : out std_ulogic);
end entity;
architecture rtl of fifo_fwft_adapter is
signal fifo_valid : std_ulogic;
signal middle_valid : std_ulogic;
signal dout_valid : std_ulogic;
signal will_update_middle : std_ulogic;
signal will_update_dout : std_ulogic;
signal middle_dout : data_type;
begin
will_update_middle <= fifo_valid and (middle_valid ?= will_update_dout);
will_update_dout <= (middle_valid or fifo_valid) and
(rd_en_i or not dout_valid);
fifo_rd_en_o <= (not fifo_empty_i) and
not (middle_valid and dout_valid and fifo_valid);
empty_o <= not dout_valid;
p_main : process(clk)
begin
if rising_edge(clk) then
if will_update_middle then
middle_dout <= fifo_rd_data_i;
end if;
if will_update_dout then
if middle_valid = '1' then
rd_data_o <= middle_dout;
else
rd_data_o <= fifo_rd_data_i;
end if;
end if;
if fifo_rd_en_o then
fifo_valid <= '1';
elsif will_update_middle or will_update_dout then
fifo_valid <= '0';
end if;
if will_update_middle then
middle_valid <= '1';
elsif will_update_dout then
middle_valid <= '0';
end if;
if will_update_dout then
dout_valid <= '1';
elsif rd_en_i then
dout_valid <= '0';
end if;
if rst then
fifo_valid <= '0';
middle_valid <= '0';
dout_valid <= '0';
end if;
end if;
end process;
end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1849.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01849ent IS
END c07s01b00x00p08n01i01849ent;
ARCHITECTURE c07s01b00x00p08n01i01849arch OF c07s01b00x00p08n01i01849ent IS
type byte is range c07s01b00x00p08n01i01849arch to 3;
BEGIN
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01849 - Architecture body names are not permitted as primaries in a range expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01849arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1849.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01849ent IS
END c07s01b00x00p08n01i01849ent;
ARCHITECTURE c07s01b00x00p08n01i01849arch OF c07s01b00x00p08n01i01849ent IS
type byte is range c07s01b00x00p08n01i01849arch to 3;
BEGIN
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01849 - Architecture body names are not permitted as primaries in a range expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01849arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1849.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01849ent IS
END c07s01b00x00p08n01i01849ent;
ARCHITECTURE c07s01b00x00p08n01i01849arch OF c07s01b00x00p08n01i01849ent IS
type byte is range c07s01b00x00p08n01i01849arch to 3;
BEGIN
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01849 - Architecture body names are not permitted as primaries in a range expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01849arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use std.textio.all;
ENTITY INTERFACE_COMB_4 IS
PORT (
rst : IN std_ulogic;
clk : IN std_ulogic;
holdn : IN std_ulogic;
cancel : IN std_ulogic;
inp : IN custom32_in_type;
outp : OUT custom32_out_type
);
END;
ARCHITECTURE RTL OF INTERFACE_COMB_4 IS
-------------------------------------------------------------------------
-- PRAGMA BEGIN DECLARATION
COMPONENT Q16_8_V_to_C_RAM
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
COMPONENT Q16_8_C_to_V_RAM
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
COMPONENT Q16_8_ROM_iPos is
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
READ_EN : in STD_LOGIC;
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
COMPONENT Q16_8_ROM_2Pos is
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
READ_EN : in STD_LOGIC;
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
COMPONENT Q16_8_RAM_576s
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
COMPONENT Q16_8_opr_CtoV_RAM
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
COMPONENT Q16_8_opr_VtoC_RAM
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
-- PRAGMA END DECLARATION
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN SIGNAL
SIGNAL RESULT_1 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_2 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_3 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_4 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_5 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_6 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_7 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL READ_EN_1 : STD_LOGIC;
SIGNAL READ_EN_2 : STD_LOGIC;
SIGNAL READ_EN_3 : STD_LOGIC;
SIGNAL READ_EN_4 : STD_LOGIC;
SIGNAL READ_EN_5 : STD_LOGIC;
SIGNAL READ_EN_6 : STD_LOGIC;
SIGNAL READ_EN_7 : STD_LOGIC;
SIGNAL WRITE_EN_1 : STD_LOGIC;
SIGNAL WRITE_EN_2 : STD_LOGIC;
SIGNAL WRITE_EN_3 : STD_LOGIC;
SIGNAL WRITE_EN_4 : STD_LOGIC;
SIGNAL WRITE_EN_5 : STD_LOGIC;
SIGNAL sINPUT_1 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL sINPUT_2 : STD_LOGIC_VECTOR(31 downto 0);
-- PRAGMA END SIGNAL
-------------------------------------------------------------------------
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) INTERFACE_COMB_4 : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
sINPUT_1 <= inp.op1(31 downto 0);
sINPUT_2 <= inp.op2(31 downto 0);
-------------------------------------------------------------------------
-------------------------------------------------------------------------
PROCESS(inp.instr, cancel)
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable opf : std_logic_vector(8 downto 0);
BEGIN
op := inp.instr(31 downto 30);
opf := inp.instr(13 downto 5);
op3 := inp.instr(24 downto 19);
READ_EN_1 <= '0';
READ_EN_2 <= '0';
READ_EN_3 <= '0';
READ_EN_4 <= '0';
READ_EN_5 <= '0';
READ_EN_6 <= '0';
READ_EN_7 <= '0';
WRITE_EN_1 <= '0';
WRITE_EN_2 <= '0';
WRITE_EN_3 <= '0';
WRITE_EN_4 <= '0';
WRITE_EN_5 <= '0';
if( op = "10" ) AND (cancel = '0') THEN
IF ( op3 = "011101" ) THEN
if opf = "000000001" THEN
READ_EN_1 <= '1'; -- 0x01
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING READ_1 SIGNAL");
-- synthesis translate_on
ELSif opf = "000000010" THEN
WRITE_EN_1 <= '1'; -- 0x02
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING WRITE_1 SIGNAL");
-- synthesis translate_on
ELSif opf = "000000011" THEN
READ_EN_2 <= '1'; -- 0x03
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING READ_2 SIGNAL");
-- synthesis translate_on
ELSif opf = "000000100" THEN
WRITE_EN_2 <= '1'; -- 0x04
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING WRITE_2 SIGNAL");
-- synthesis translate_on
ELSif opf = "000000101" THEN
READ_EN_3 <= '1'; -- 0x05
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING READ_3 SIGNAL (ldipos)");
-- synthesis translate_on
ELSif opf = "000000110" THEN
READ_EN_4 <= '1'; -- 0x06
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING READ_4 SIGNAL");
-- synthesis translate_on
ELSif opf = "000000111" THEN
READ_EN_5 <= '1'; -- 0x07
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING READ_5 SIGNAL");
-- synthesis translate_on
ELSif opf = "000001000" THEN
WRITE_EN_3 <= '1'; -- 0x08
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING WRITE_3 SIGNAL");
-- synthesis translate_on
ELSif opf = "000001001" THEN
READ_EN_6 <= '1'; -- 0x09
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING READ_6 SIGNAL");
-- synthesis translate_on
ELSif opf = "000001010" THEN
WRITE_EN_4 <= '1'; -- 0x0A
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING WRITE_4 SIGNAL (Q16_8_opr_VtoC_RAM)");
-- synthesis translate_on
ELSif opf = "000001011" THEN
READ_EN_7 <= '1'; -- 0x0B
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING READ_7 SIGNAL");
-- synthesis translate_on
ELSif opf = "000001100" THEN
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING WRITE SIGNAL TO RESOURCE (7)");
-- synthesis translate_on
WRITE_EN_5 <= '1'; -- 0x0C
ELSE
-- synthesis translate_off
printmsg("(INTERFACE_COMB_4) ===> GENERATING AN OUPS PROBLEM");
-- synthesis translate_on
END IF;
END IF;
END IF;
END PROCESS;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN INSTANCIATION
RESOURCE_1 : Q16_8_C_to_V_RAM PORT MAP (rst, clk, holdn, WRITE_EN_1, READ_EN_1, sINPUT_1, RESULT_1);
RESOURCE_2 : Q16_8_V_to_C_RAM PORT MAP (rst, clk, holdn, WRITE_EN_2, READ_EN_2, sINPUT_1, RESULT_2);
RESOURCE_3 : Q16_8_ROM_iPos PORT MAP (rst, clk, holdn, READ_EN_3, RESULT_3);
RESOURCE_4 : Q16_8_ROM_2Pos PORT MAP (rst, clk, holdn, READ_EN_4, RESULT_4);
RESOURCE_5 : Q16_8_opr_CtoV_RAM PORT MAP (rst, clk, holdn, WRITE_EN_3, READ_EN_5, sINPUT_1, sINPUT_2, RESULT_5);
RESOURCE_6 : Q16_8_opr_VtoC_RAM PORT MAP (rst, clk, holdn, WRITE_EN_4, READ_EN_6, sINPUT_1, sINPUT_2, RESULT_6);
RESOURCE_7 : Q16_8_RAM_576s PORT MAP (rst, clk, holdn, WRITE_EN_5, READ_EN_7, sINPUT_1, RESULT_7);
-- PRAGMA END INSTANCIATION
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN RESULT SELECTION
WITH inp.instr(13 downto 5) SELECT
outp.result <=
RESULT_1 WHEN "000000001",
RESULT_1 WHEN "000000010",
RESULT_2 WHEN "000000011",
RESULT_2 WHEN "000000100",
RESULT_3 WHEN "000000101",
RESULT_4 WHEN "000000110",
RESULT_5 WHEN "000000111",
RESULT_5 WHEN "000001000",
RESULT_6 WHEN "000001001",
RESULT_6 WHEN "000001010",
RESULT_7 WHEN "000001011",
RESULT_7 WHEN "000001100",
STD_LOGIC_VECTOR( TO_SIGNED(-1, 32) ) WHEN OTHERS;
-- PRAGMA END RESULT SELECTION
-------------------------------------------------------------------------
end; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcipads
-- File: pcipads.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: PCI pads module
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use work.pci.all;
library grlib;
use grlib.stdlib.all;
entity pcipads is
generic (
padtech : integer := 0;
noreset : integer := 0;
oepol : integer := 0;
host : integer := 1;
int : integer := 0
);
port (
pci_rst : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic; -- tristate pad but never read
pci_serr : inout std_ulogic; -- open drain output
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pcii : out pci_in_type;
pcio : in pci_out_type;
pci_int : inout std_logic_vector(3 downto 0) := conv_std_logic_vector(16#F#, 4) -- Disable int by default
--pci_int : inout std_logic_vector(3 downto 0) :=
-- conv_std_logic_vector(16#F# - (16#F# * oepol), 4) -- Disable int by default
);
end;
architecture rtl of pcipads is
signal vcc : std_ulogic;
begin
vcc <= '1';
norst : if noreset = 0 generate
pad_pci_rst : inpad generic map (padtech, pci33, 0) port map (pci_rst, pcii.rst);
end generate;
dorst : if noreset = 1 generate
pcii.rst <= pci_rst;
end generate;
pad_pci_gnt : inpad generic map (padtech, pci33, 0) port map (pci_gnt, pcii.gnt);
pad_pci_idsel : inpad generic map (padtech, pci33, 0) port map (pci_idsel, pcii.idsel);
dohost : if host = 1 generate
pad_pci_host : inpad generic map (padtech, pci33, 0) port map (pci_host, pcii.host);
end generate;
nohost : if host = 0 generate
pcii.host <= '1'; -- disable pci host functionality
end generate;
pad_pci_66 : inpad generic map (padtech, pci33, 0) port map (pci_66, pcii.pci66);
pad_pci_lock : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_lock, pcio.lock, pcio.locken, pcii.lock);
pad_pci_ad : iopadvv generic map (tech => padtech, level => pci33, width => 32,
oepol => oepol)
port map (pci_ad, pcio.ad, pcio.vaden, pcii.ad);
pad_pci_cbe0 : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_cbe(0), pcio.cbe(0), pcio.cbeen(0), pcii.cbe(0));
pad_pci_cbe1 : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_cbe(1), pcio.cbe(1), pcio.cbeen(1), pcii.cbe(1));
pad_pci_cbe2 : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_cbe(2), pcio.cbe(2), pcio.cbeen(2), pcii.cbe(2));
pad_pci_cbe3 : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_cbe(3), pcio.cbe(3), pcio.cbeen(3), pcii.cbe(3));
pad_pci_frame : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_frame, pcio.frame, pcio.frameen, pcii.frame);
pad_pci_trdy : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_trdy, pcio.trdy, pcio.trdyen, pcii.trdy);
pad_pci_irdy : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_irdy, pcio.irdy, pcio.irdyen, pcii.irdy);
pad_pci_devsel: iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_devsel, pcio.devsel, pcio.devselen, pcii.devsel);
pad_pci_stop : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_stop, pcio.stop, pcio.stopen, pcii.stop);
pad_pci_perr : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_perr, pcio.perr, pcio.perren, pcii.perr);
pad_pci_par : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_par, pcio.par, pcio.paren, pcii.par);
pad_pci_req : toutpad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_req, pcio.req, pcio.reqen);
pad_pci_serr : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_serr, pcio.serr, pcio.serren, pcii.serr);
-- PCI interrupt pads
-- int = 0 => no interrupt
-- int = 1 => PCI_INT[A] = out, PCI_INT[B,C,D] = Not connected
-- int = 2 => PCI_INT[B] = out, PCI_INT[A,C,D] = Not connected
-- int = 3 => PCI_INT[C] = out, PCI_INT[A,B,D] = Not connected
-- int = 4 => PCI_INT[D] = out, PCI_INT[A,B,C] = Not connected
-- int = 10 => PCI_INT[A] = inout, PCI_INT[B,C,D] = in
-- int = 11 => PCI_INT[B] = inout, PCI_INT[A,C,D] = in
-- int = 12 => PCI_INT[C] = inout, PCI_INT[A,B,D] = in
-- int = 13 => PCI_INT[D] = inout, PCI_INT[A,B,C] = in
-- int > 13 => PCI_INT[A,B,C,D] = in
interrupt : if int /= 0 generate
x : for i in 0 to 3 generate
xo : if i = int - 1 and int < 10 generate
pad_pci_int : odpad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_int(i), pcio.inten);
end generate;
xio : if i = (int - 10) and int >= 10 generate
pad_pci_int : iodpad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_int(i), pcio.inten, pcii.int(i));
end generate;
xi : if i /= (int - 10) and int >= 10 generate
pad_pci_int : inpad generic map (tech => padtech, level => pci33)
port map (pci_int(i), pcii.int(i));
end generate;
end generate;
end generate;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcipads
-- File: pcipads.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: PCI pads module
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use work.pci.all;
library grlib;
use grlib.stdlib.all;
entity pcipads is
generic (
padtech : integer := 0;
noreset : integer := 0;
oepol : integer := 0;
host : integer := 1;
int : integer := 0
);
port (
pci_rst : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic; -- tristate pad but never read
pci_serr : inout std_ulogic; -- open drain output
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pcii : out pci_in_type;
pcio : in pci_out_type;
pci_int : inout std_logic_vector(3 downto 0) := conv_std_logic_vector(16#F#, 4) -- Disable int by default
--pci_int : inout std_logic_vector(3 downto 0) :=
-- conv_std_logic_vector(16#F# - (16#F# * oepol), 4) -- Disable int by default
);
end;
architecture rtl of pcipads is
signal vcc : std_ulogic;
begin
vcc <= '1';
norst : if noreset = 0 generate
pad_pci_rst : inpad generic map (padtech, pci33, 0) port map (pci_rst, pcii.rst);
end generate;
dorst : if noreset = 1 generate
pcii.rst <= pci_rst;
end generate;
pad_pci_gnt : inpad generic map (padtech, pci33, 0) port map (pci_gnt, pcii.gnt);
pad_pci_idsel : inpad generic map (padtech, pci33, 0) port map (pci_idsel, pcii.idsel);
dohost : if host = 1 generate
pad_pci_host : inpad generic map (padtech, pci33, 0) port map (pci_host, pcii.host);
end generate;
nohost : if host = 0 generate
pcii.host <= '1'; -- disable pci host functionality
end generate;
pad_pci_66 : inpad generic map (padtech, pci33, 0) port map (pci_66, pcii.pci66);
pad_pci_lock : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_lock, pcio.lock, pcio.locken, pcii.lock);
pad_pci_ad : iopadvv generic map (tech => padtech, level => pci33, width => 32,
oepol => oepol)
port map (pci_ad, pcio.ad, pcio.vaden, pcii.ad);
pad_pci_cbe0 : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_cbe(0), pcio.cbe(0), pcio.cbeen(0), pcii.cbe(0));
pad_pci_cbe1 : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_cbe(1), pcio.cbe(1), pcio.cbeen(1), pcii.cbe(1));
pad_pci_cbe2 : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_cbe(2), pcio.cbe(2), pcio.cbeen(2), pcii.cbe(2));
pad_pci_cbe3 : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_cbe(3), pcio.cbe(3), pcio.cbeen(3), pcii.cbe(3));
pad_pci_frame : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_frame, pcio.frame, pcio.frameen, pcii.frame);
pad_pci_trdy : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_trdy, pcio.trdy, pcio.trdyen, pcii.trdy);
pad_pci_irdy : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_irdy, pcio.irdy, pcio.irdyen, pcii.irdy);
pad_pci_devsel: iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_devsel, pcio.devsel, pcio.devselen, pcii.devsel);
pad_pci_stop : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_stop, pcio.stop, pcio.stopen, pcii.stop);
pad_pci_perr : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_perr, pcio.perr, pcio.perren, pcii.perr);
pad_pci_par : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_par, pcio.par, pcio.paren, pcii.par);
pad_pci_req : toutpad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_req, pcio.req, pcio.reqen);
pad_pci_serr : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_serr, pcio.serr, pcio.serren, pcii.serr);
-- PCI interrupt pads
-- int = 0 => no interrupt
-- int = 1 => PCI_INT[A] = out, PCI_INT[B,C,D] = Not connected
-- int = 2 => PCI_INT[B] = out, PCI_INT[A,C,D] = Not connected
-- int = 3 => PCI_INT[C] = out, PCI_INT[A,B,D] = Not connected
-- int = 4 => PCI_INT[D] = out, PCI_INT[A,B,C] = Not connected
-- int = 10 => PCI_INT[A] = inout, PCI_INT[B,C,D] = in
-- int = 11 => PCI_INT[B] = inout, PCI_INT[A,C,D] = in
-- int = 12 => PCI_INT[C] = inout, PCI_INT[A,B,D] = in
-- int = 13 => PCI_INT[D] = inout, PCI_INT[A,B,C] = in
-- int > 13 => PCI_INT[A,B,C,D] = in
interrupt : if int /= 0 generate
x : for i in 0 to 3 generate
xo : if i = int - 1 and int < 10 generate
pad_pci_int : odpad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_int(i), pcio.inten);
end generate;
xio : if i = (int - 10) and int >= 10 generate
pad_pci_int : iodpad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_int(i), pcio.inten, pcii.int(i));
end generate;
xi : if i /= (int - 10) and int >= 10 generate
pad_pci_int : inpad generic map (tech => padtech, level => pci33)
port map (pci_int(i), pcii.int(i));
end generate;
end generate;
end generate;
end;
|
------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet. Publication of this
-- design is not authorized without written consent from Avnet.
--
-- Please direct any questions to: [email protected]
--
-- Disclaimer:
-- Avnet, Inc. makes no warranty for the use of this code or design.
-- This code is provided "As Is". Avnet, Inc assumes no responsibility for
-- any errors, which may appear in this code, nor does it make a commitment
-- to update the information contained herein. Avnet, Inc specifically
-- disclaims any implied warranties of fitness for a particular purpose.
-- Copyright(c) 2010 Avnet, Inc.
-- All rights reserved.
--
------------------------------------------------------------------
--
-- Create Date: Dec 03, 2009
-- Design Name: IVK
-- Module Name: ivk_video_gen\videosyncgen.vhd
-- Project Name: IVK
-- Target Devices: Spartan-6
-- Avnet Boards: IVK
--
-- Tool versions: ISE 11.4
--
-- Description: Video Synchronization Generator
--
-- Dependencies:
--
-- Revision: Dec 03, 2009: 1.00 Initial version
-- Feb 08, 2010: 1.02 Add generation of VBLANK/HBLANK
--
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity VideoSyncGen is
generic (
HWidth_g : integer := 16;
VWidth_g : integer := 16
);
port (
-- Global Reset
i_Clk_p : in std_logic;
i_Reset_p : in std_logic;
-- Video Configuration
iv16_VidHActive_p : in std_logic_vector(15 downto 0);
iv16_VidHFPorch_p : in std_logic_vector(15 downto 0);
iv16_VidHSync_p : in std_logic_vector(15 downto 0);
iv16_VidHBPorch_p : in std_logic_vector(15 downto 0);
--
iv16_VidVActive_p : in std_logic_vector(15 downto 0);
iv16_VidVFPorch_p : in std_logic_vector(15 downto 0);
iv16_VidVSync_p : in std_logic_vector(15 downto 0);
iv16_VidVBPorch_p : in std_logic_vector(15 downto 0);
-- Video Synchronization Signals
o_HSync_p : out std_logic;
o_VSync_p : out std_logic;
o_De_p : out std_logic;
o_HBlank_p : out std_logic;
o_VBlank_p : out std_logic;
-- Data Request strobe (1 cycle in advance of synchronization signals)
ov_HCount_p : out std_logic_vector(HWidth_g-1 downto 0);
ov_VCount_p : out std_logic_vector(VWidth_g-1 downto 0);
o_PixelRequest_p : out std_logic
);
end entity VideoSyncGen;
architecture Rtl of VideoSyncGen is
--
-- Intermediate signals for output ports
--
-- Video Synchronization Signals
signal HSync_s : std_logic;
signal VSync_s : std_logic;
signal De_s : std_logic;
signal HBlank_s : std_logic;
signal VBlank_s : std_logic;
-- Data Request strobe (1 cycle in advance of synchronization signals)
signal v_HCount_s : unsigned(HWidth_g-1 downto 0);
signal v_VCount_s : unsigned(VWidth_g-1 downto 0);
signal PixelRequest_s : std_logic;
--
-- Sync State Machines
--
type SyncState_t is (
FrontPorch_c,
SyncPulse_c,
BackPorch_c,
ActiveVideo_c
);
signal HSyncState_s : SyncState_t;
signal VSyncState_s : SyncState_t;
signal VSyncStateD1_s : SyncState_t;
attribute fsm_encoding : string;
attribute fsm_encoding of HSyncState_s : signal is "sequential";
attribute fsm_encoding of VSyncState_s : signal is "sequential";
attribute safe_implementation : string;
attribute safe_implementation of HSyncState_s : signal is "yes";
attribute safe_implementation of VSyncState_s : signal is "yes";
signal v_HSyncCount_s : unsigned(HWidth_g+1 downto 0);
signal v_VSyncCount_s : unsigned(VWidth_g+1 downto 0);
signal HSyncDone_s : std_logic;
signal VSyncDone_s : std_logic;
signal HSyncA1_s : std_logic;
signal VSyncA1_s : std_logic;
signal DeA1_s : std_logic;
signal HBlankA1_s : std_logic;
signal VBlankA1_s : std_logic;
begin
--
-- Output port assignments
--
-- Video Synchronization Signals
o_VSync_p <= VSync_s;
o_HSync_p <= HSync_s;
o_De_p <= De_s;
o_HBlank_p <= HBlank_s;
o_VBlank_p <= VBlank_s;
-- Data Request strobe (1 cycle in advance of synchronization signals)
ov_HCount_p <= std_logic_vector(v_HCount_s);
ov_VCount_p <= std_logic_vector(v_VCount_s);
o_PixelRequest_p <= PixelRequest_s;
--
-- HSync State Machine
--
HSyncFsm_l : process ( i_Clk_p, i_Reset_p )
begin
if ( i_Reset_p = '1' ) then
HSyncState_s <= FrontPorch_c;
v_HSyncCount_s <= (others => '0');
HSyncA1_s <= '0';
DeA1_s <= '0';
HBlankA1_s <= '0';
HSync_s <= '0';
De_s <= '0';
HBlank_s <= '0';
v_HCount_s <= (others => '0');
HSyncDone_s <= '0';
elsif rising_edge( i_Clk_p ) then
-- Default values
HSyncDone_s <= '0';
-- HSync Counter
v_HSyncCount_s <= v_HSyncCount_s + 1;
-- HSync State Machine
case HSyncState_s is
when FrontPorch_c =>
if v_HSyncCount_s >= (unsigned(iv16_VidHFPorch_p) - 1) then
v_HSyncCount_s <= (others => '0');
HSyncDone_s <= '1';
HSyncState_s <= SyncPulse_c;
if ( iv16_VidHSync_p(15) = '1' ) then
HSyncA1_s <= '1'; -- Active High sync pulse
else
HSyncA1_s <= '0'; -- Active Low sync pulse
end if;
end if;
when SyncPulse_c =>
if v_HSyncCount_s >= (unsigned(iv16_VidHSync_p(14 downto 0)) - 1) then
v_HSyncCount_s <= (others => '0');
HSyncState_s <= BackPorch_c;
if ( iv16_VidHSync_p(15) = '1' ) then
HSyncA1_s <= '0'; -- Active High sync pulse
else
HSyncA1_s <= '1'; -- Active Low sync pulse
end if;
end if;
when BackPorch_c =>
if v_HSyncCount_s >= (unsigned(iv16_VidHBPorch_p) - 1) then
v_HSyncCount_s <= (others => '0');
HSyncState_s <= ActiveVideo_c;
v_HCount_s <= (others => '0');
--if ( VSyncState_s = ActiveVideo_c ) then
if ( VSyncStateD1_s = ActiveVideo_c ) then
DeA1_s <= '1';
end if;
HBlankA1_s <= '0';
end if;
when ActiveVideo_c =>
v_HCount_s <= v_HCount_s + 1;
if v_HSyncCount_s >= (unsigned(iv16_VidHActive_p) - 1) then
v_HSyncCount_s <= (others => '0');
HSyncState_s <= FrontPorch_c;
DeA1_s <= '0';
HBlankA1_s <= '1';
end if;
when others =>
HSyncState_s <= ActiveVideo_c;
v_HSyncCount_s <= (others => '0');
HSyncDone_s <= '0';
end case;
-- non-advanced versions of synchronization signals (ie. delayed by 1 clock cycle)
HSync_s <= HSyncA1_s;
De_s <= DeA1_s;
HBlank_s <= HBlankA1_s;
end if;
end process HSyncFsm_l;
-- Pixel Request is advanced version of DE
PixelRequest_s <= DeA1_s;
--
-- VSync State Machine
--
VSyncFsm_l : process ( i_Clk_p, i_Reset_p )
begin
if ( i_Reset_p = '1' ) then
VSyncState_s <= FrontPorch_c;
VSyncStateD1_s <= FrontPorch_c;
v_VSyncCount_s <= (others => '0');
VSyncA1_s <= '0';
VBlankA1_s <= '0';
VSync_s <= '0';
VBlank_s <= '0';
v_VCount_s <= (others => '0');
VSyncDone_s <= '0';
elsif rising_edge( i_Clk_p ) then
-- Default values
VSyncDone_s <= '0';
if ( HSyncDone_s = '1' ) then
-- VSync Counter
v_VSyncCount_s <= v_VSyncCount_s + 1;
-- VSync State Machine
case VSyncState_s is
when FrontPorch_c =>
if v_VSyncCount_s >= (unsigned(iv16_VidVFPorch_p) - 1) then
v_VSyncCount_s <= (others => '0');
VSyncState_s <= SyncPulse_c;
if ( iv16_VidVSync_p(15) = '1' ) then
VSyncA1_s <= '1'; -- Active High sync pulse
else
VSyncA1_s <= '0'; -- Active Low sync pulse
end if;
end if;
-- The following assignment is not required
-- but conveniently indicates the number of active lines during blanking intervals
v_VCount_s <= unsigned(iv16_VidVActive_p(VWidth_g-1 downto 0));
when SyncPulse_c =>
if v_VSyncCount_s >= (unsigned(iv16_VidVSync_p(14 downto 0)) - 1) then
v_VSyncCount_s <= (others => '0');
VSyncState_s <= BackPorch_c;
if ( iv16_VidVSync_p(15) = '1' ) then
VSyncA1_s <= '0'; -- Active High sync pulse
else
VSyncA1_s <= '1'; -- Active Low sync pulse
end if;
end if;
when BackPorch_c =>
if v_VSyncCount_s >= (unsigned(iv16_VidVBPorch_p) - 1) then
v_VSyncCount_s <= (others => '0');
VSyncState_s <= ActiveVideo_c;
v_VCount_s <= (others => '0');
VSyncDone_s <= '1';
VBlankA1_s <= '0';
end if;
when ActiveVideo_c =>
v_VCount_s <= v_VSyncCount_s(VWidth_g-1 downto 0);
if v_VSyncCount_s >= (unsigned(iv16_VidVActive_p) - 1) then
v_VSyncCount_s <= (others => '0');
VSyncState_s <= FrontPorch_c;
VBlankA1_s <= '1';
end if;
when others =>
VSyncState_s <= ActiveVideo_c;
v_VSyncCount_s <= (others => '0');
VSyncDone_s <= '0';
end case;
-- non-advanced versions of synchronization signals (ie. delayed by 1 line)
VSync_s <= VSyncA1_s;
VBlank_s <= VBlankA1_s;
-- delayed version of VSyncState
VSyncStateD1_s <= VSyncState_s;
end if; -- if ( HSyncDone_s = '1' )
end if;
end process VSyncFsm_l;
end architecture Rtl;
|
-------------------------------------------------------------------------------
--
-- Title : inv
-- Design : lab2
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : inv.vhd
-- Generated : Fri Oct 3 17:29:58 2014
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {inv} architecture {inv}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity inv is
port(
A : in STD_LOGIC;
Z : out STD_LOGIC
);
end inv;
--}} End of automatically maintained section
architecture inv of inv is
begin
Z <= not A;
end inv;
|
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