rtl-llm/vhdl_github · Datasets at Hugging Face

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---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 19:32:46 06/20/2014 -- Design Name: -- Module Name: channel_avg - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values USE ieee.numeric_std.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. LIBRARY UNISIM; USE UNISIM.VComponents.ALL; ENTITY channel_avg IS GENERIC ( NCH : positive := 16; OUTCH_WIDTH : positive := 16; INTERNAL_WIDTH : positive := 32; INDATA_WIDTH : positive := 256; OUTDATA_WIDTH : positive := 256 ); PORT ( RESET : IN std_logic; CLK : IN std_logic; -- high 4-bit is offset, 2*(low 4-bit) is number of points to average CONFIG : IN std_logic_vector(7 DOWNTO 0); TRIG : IN std_logic; INDATA_Q : IN std_logic_vector(INDATA_WIDTH-1 DOWNTO 0); OUTVALID : OUT std_logic; OUTDATA_Q : OUT std_logic_vector(OUTDATA_WIDTH-1 DOWNTO 0) ); END channel_avg; ARCHITECTURE Behavioral OF channel_avg IS SIGNAL trig_prev : std_logic; SIGNAL trig_prev1 : std_logic; SIGNAL trig_prev2 : std_logic; SIGNAL trig_synced : std_logic; -- SIGNAL avg_n : positive; -- TYPE INTERNALVAL IS ARRAY(NCH-1 DOWNTO 0) OF signed(INTERNAL_WIDTH-1 DOWNTO 0); SIGNAL inch_val : INTERNALVAL; SIGNAL internal_val : INTERNALVAL; BEGIN PROCESS (CLK) IS VARIABLE i : integer; BEGIN IF falling_edge(CLK) THEN -- register half-cycle earlier FOR i IN 0 TO NCH-1 LOOP inch_val(i) <= resize(signed(INDATA_Q(16(i+1)-1 DOWNTO 16i)), INTERNAL_WIDTH); END LOOP; END IF; END PROCESS; -- capture the rising edge of trigger PROCESS (CLK, RESET) IS BEGIN IF RESET = '1' THEN trig_prev <= '0'; trig_prev1 <= '0'; trig_prev2 <= '0'; ELSIF rising_edge(CLK) THEN trig_prev <= TRIG; trig_prev1 <= trig_prev; trig_prev2 <= trig_prev1; END IF; END PROCESS; trig_synced <= '1' WHEN trig_prev2 = '0' AND trig_prev1 = '1' ELSE '0'; avg_n <= to_integer(unsigned(CONFIG(3 DOWNTO 0))); PROCESS (CLK, RESET) IS VARIABLE i : integer; VARIABLE j : unsigned(15 DOWNTO 0); BEGIN IF RESET = '1' THEN FOR i IN 0 TO NCH-1 LOOP internal_val(i) <= (OTHERS => '0'); END LOOP; OUTVALID <= '0'; j := (OTHERS => '0'); ELSIF rising_edge(CLK) THEN IF trig_synced = '1' THEN j := resize(unsigned(CONFIG(7 DOWNTO 4)), j'length) + 1; END IF; FOR i IN 0 TO NCH-1 LOOP IF j = 1 THEN internal_val(i) <= inch_val(i); ELSE internal_val(i) <= internal_val(i) + inch_val(i); END IF; END LOOP; IF j(avg_n) = '1' THEN j := to_unsigned(1, j'length); OUTVALID <= '1'; ELSE j := j + 1; OUTVALID <= '0'; END IF; END IF; END PROCESS; outdata_q_inst : FOR i IN 0 TO NCH-1 GENERATE OUTDATA_Q(OUTCH_WIDTH(i+1)-1 DOWNTO OUTCH_WIDTH*i) <= std_logic_vector(internal_val(i)(OUTCH_WIDTH-1+avg_n DOWNTO avg_n)); END GENERATE; END Behavioral;
-- $Id: serport_1clock.vhd 1181 2019-07-08 17:00:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2011-2015 by Walter F.J. Mueller <[email protected]> -- ------------------------------------------------------------------------------ -- Module Name: serport_1clock - syn -- Description: serial port: serial port module, 1 clock domain -- -- Dependencies: serport_uart_rxtx_ab -- serport_xonrx -- serport_xontx -- memlib/fifo_1c_dram -- Test bench: - -- Target Devices: generic -- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri -- 2015-04-12 666 14.7 131013 xc6slx16-2 171 239 32 94 s 6.3 -- 2011-11-13 424 13.1 O40d xc3s1000-4 157 337 64 232 s 9.9 -- -- Revision History: -- Date Rev Version Comment -- 2015-04-11 666 1.1.1 add sim assertions for RXOVR and RXERR -- 2015-02-01 641 1.1 add CLKDIV_F for autobaud; -- 2011-12-10 438 1.0.2 internal reset on abact -- 2011-12-09 437 1.0.1 rename stat->moni port -- 2011-11-13 424 1.0 Initial version -- 2011-10-23 419 0.5 First draft ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; use work.serportlib.all; use work.memlib.all; entity serport_1clock is -- serial port module, 1 clock domain generic ( CDWIDTH : positive := 13; -- clk divider width CDINIT : natural := 15; -- clk divider initial/reset setting RXFAWIDTH : natural := 5; -- rx fifo address width TXFAWIDTH : natural := 5); -- tx fifo address width port ( CLK : in slbit; -- clock CE_MSEC : in slbit; -- 1 msec clock enable RESET : in slbit; -- reset ENAXON : in slbit; -- enable xon/xoff handling ENAESC : in slbit; -- enable xon/xoff escaping RXDATA : out slv8; -- receiver data out RXVAL : out slbit; -- receiver data valid RXHOLD : in slbit; -- receiver data hold TXDATA : in slv8; -- transmit data in TXENA : in slbit; -- transmit data enable TXBUSY : out slbit; -- transmit busy MONI : out serport_moni_type; -- serport monitor port RXSD : in slbit; -- receive serial data (uart view) TXSD : out slbit; -- transmit serial data (uart view) RXRTS_N : out slbit; -- receive rts (uart view, act.low) TXCTS_N : in slbit -- transmit cts (uart view, act.low) ); end serport_1clock; architecture syn of serport_1clock is signal R_RXOK : slbit := '1'; signal RESET_INT : slbit := '0'; signal UART_RXDATA : slv8 := (others=>'0'); signal UART_RXVAL : slbit := '0'; signal UART_TXDATA : slv8 := (others=>'0'); signal UART_TXENA : slbit := '0'; signal UART_TXBUSY : slbit := '0'; signal XONTX_TXENA : slbit := '0'; signal XONTX_TXBUSY : slbit := '0'; signal RXFIFO_DI : slv8 := (others=>'0'); signal RXFIFO_ENA : slbit := '0'; signal RXFIFO_BUSY : slbit := '0'; signal RXFIFO_SIZE : slv(RXFAWIDTH downto 0) := (others=>'0'); signal TXFIFO_DO : slv8 := (others=>'0'); signal TXFIFO_VAL : slbit := '0'; signal TXFIFO_HOLD : slbit := '0'; signal RXERR : slbit := '0'; signal RXOVR : slbit := '0'; signal RXACT : slbit := '0'; signal ABACT : slbit := '0'; signal ABDONE : slbit := '0'; signal ABCLKDIV : slv(CDWIDTH-1 downto 0) := (others=>'0'); signal ABCLKDIV_F : slv3 := (others=>'0'); signal TXOK : slbit := '0'; signal RXOK : slbit := '0'; begin assert CDWIDTH<=16 report "assert(CDWIDTH<=16): max width of UART clock divider" severity failure; UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo generic map ( CDWIDTH => CDWIDTH, CDINIT => CDINIT) port map ( CLK => CLK, CE_MSEC => CE_MSEC, RESET => RESET, RXSD => RXSD, RXDATA => UART_RXDATA, RXVAL => UART_RXVAL, RXERR => RXERR, RXACT => RXACT, TXSD => TXSD, TXDATA => UART_TXDATA, TXENA => UART_TXENA, TXBUSY => UART_TXBUSY, ABACT => ABACT, ABDONE => ABDONE, ABCLKDIV => ABCLKDIV, ABCLKDIV_F => ABCLKDIV_F ); RESET_INT <= RESET or ABACT; XONRX : serport_xonrx -- xon/xoff logic rx path port map ( CLK => CLK, RESET => RESET_INT, ENAXON => ENAXON, ENAESC => ENAESC, UART_RXDATA => UART_RXDATA, UART_RXVAL => UART_RXVAL, RXDATA => RXFIFO_DI, RXVAL => RXFIFO_ENA, RXHOLD => RXFIFO_BUSY, RXOVR => RXOVR, TXOK => TXOK ); XONTX : serport_xontx -- xon/xoff logic tx path port map ( CLK => CLK, RESET => RESET_INT, ENAXON => ENAXON, ENAESC => ENAESC, UART_TXDATA => UART_TXDATA, UART_TXENA => XONTX_TXENA, UART_TXBUSY => XONTX_TXBUSY, TXDATA => TXFIFO_DO, TXENA => TXFIFO_VAL, TXBUSY => TXFIFO_HOLD, RXOK => RXOK, TXOK => TXOK ); RXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based generic map ( AWIDTH => RXFAWIDTH, DWIDTH => 8) port map ( CLK => CLK, RESET => RESET_INT, DI => RXFIFO_DI, ENA => RXFIFO_ENA, BUSY => RXFIFO_BUSY, DO => RXDATA, VAL => RXVAL, HOLD => RXHOLD, SIZE => RXFIFO_SIZE ); TXFIFO : fifo_1c_dram -- output fifo, 1 clock, dram based generic map ( AWIDTH => TXFAWIDTH, DWIDTH => 8) port map ( CLK => CLK, RESET => RESET_INT, DI => TXDATA, ENA => TXENA, BUSY => TXBUSY, DO => TXFIFO_DO, VAL => TXFIFO_VAL, HOLD => TXFIFO_HOLD, SIZE => open ); -- receive back pressure -- on if fifo more than 3/4 full -- off if fifo less than 1/2 full proc_rxok: process (CLK) constant rxsize_rxok_off : slv3 := "011"; constant rxsize_rxok_on : slv3 := "010"; variable rxsize_msb : slv3 := "000"; begin if rising_edge(CLK) then if RESET_INT = '1' then R_RXOK <= '1'; else rxsize_msb := RXFIFO_SIZE(RXFAWIDTH downto RXFAWIDTH-2); if unsigned(rxsize_msb) >= unsigned(rxsize_rxok_off) then R_RXOK <= '0'; elsif unsigned(rxsize_msb) <= unsigned(rxsize_rxok_on) then R_RXOK <= '1'; end if; end if; end if; end process proc_rxok; RXOK <= R_RXOK; RXRTS_N <= not R_RXOK; proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY) begin if TXCTS_N = '0' then -- transmit cts asserted UART_TXENA <= XONTX_TXENA; XONTX_TXBUSY <= UART_TXBUSY; else -- transmit cts not asserted UART_TXENA <= '0'; XONTX_TXBUSY <= '1'; end if; end process proc_cts; MONI.rxerr <= RXERR; MONI.rxovr <= RXOVR; MONI.rxact <= RXACT; MONI.txact <= UART_TXBUSY; MONI.abact <= ABACT; MONI.abdone <= ABDONE; MONI.rxok <= RXOK; MONI.txok <= TXOK; proc_abclkdiv: process (ABCLKDIV, ABCLKDIV_F) begin MONI.abclkdiv <= (others=>'0'); MONI.abclkdiv(ABCLKDIV'range) <= ABCLKDIV; MONI.abclkdiv_f <= ABCLKDIV_F; end process proc_abclkdiv; -- synthesis translate_off proc_check: process (CLK) begin if rising_edge(CLK) then assert RXOVR = '0' report "serport_1clock-W: RXOVR = " & slbit'image(RXOVR) & "; data loss in receive fifo" severity warning; assert RXERR = '0' report "serport_1clock-W: RXERR = " & slbit'image(RXERR) & "; spurious receive error" severity warning; end if; end process proc_check; -- synthesis translate_on end syn;
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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block j568ylTKCX1ijKCu3zCEYX4KzYIJPurwijBGL11yx0O4LKHLMP8dlqw1rKJAJyrIFXxSA8VDlDyI zGGu45lCWA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Zsr0AQ+BVB+qiaA/LMGWEJP/NrZG3InNL+c379B92bObAE0efeTZpmUE1xBqjehQpvWUAwUx+nu1 ovOY8kEzNgIq2y7PBozDXLUFYCGPeG8YSvcca9nazpYZq3J1pYo73+j7dFLANXGQbyuVYrJ2fYen tlUyhv+6QbaysUJuVbI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Q2+tD8NGxa+F0Kpjcc7LfAe6tSHp2t/mfv+sRfVCSbFXzphOA7xbOWMnCZ2v11rkLOTfvtsY9E5x egpSXJPwZm/DAmzKgDWCXDHkuVgfrpxeZMNdJ1lJ9SpDF+JD/u4nORV5Q5/DeeXs2+CQ5PqkdYUD eIjqeKg1UKhzovo4tymm7vrVQtfKqVoXYUxWEXB6QJLlvWA5gOpbJ72hUPw6a0NzFAS3PM9gJRWr +V/WEj/+m/HldnM/s5CLDxqiKGoTJeipBMDXuSfUTg9agdUBzwGsFCMZJSLJ4cYWQUG6tMY3AaLS MOniFSWAyMTYTif8NQsspDwq92mtLcETXdUz5A== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block SIoa1SLEDIJ50U+1JCg5zLLYmPSw4kw2HFkGIoi2lK+mwV4W3mmmZAX326KwZQjzb9VWnIVFdT1Y UN2hFjGyLs8z+rzG4Oy9dq7L+kkKeWNXb0jGjejfJbh8K9cxmEEPP8/IjSoJaNkIJlUxmJUnjyHE IKC2aqKScbgxjZHZt9w= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block gJv7V3tQbfvvgMOdcWebzitR5f3OA0wOotRLu972K8EfTJsXxH0DQMQ8HCrhd5UEee7Tvs6urOmX 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block j568ylTKCX1ijKCu3zCEYX4KzYIJPurwijBGL11yx0O4LKHLMP8dlqw1rKJAJyrIFXxSA8VDlDyI zGGu45lCWA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Zsr0AQ+BVB+qiaA/LMGWEJP/NrZG3InNL+c379B92bObAE0efeTZpmUE1xBqjehQpvWUAwUx+nu1 ovOY8kEzNgIq2y7PBozDXLUFYCGPeG8YSvcca9nazpYZq3J1pYo73+j7dFLANXGQbyuVYrJ2fYen tlUyhv+6QbaysUJuVbI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Q2+tD8NGxa+F0Kpjcc7LfAe6tSHp2t/mfv+sRfVCSbFXzphOA7xbOWMnCZ2v11rkLOTfvtsY9E5x egpSXJPwZm/DAmzKgDWCXDHkuVgfrpxeZMNdJ1lJ9SpDF+JD/u4nORV5Q5/DeeXs2+CQ5PqkdYUD eIjqeKg1UKhzovo4tymm7vrVQtfKqVoXYUxWEXB6QJLlvWA5gOpbJ72hUPw6a0NzFAS3PM9gJRWr +V/WEj/+m/HldnM/s5CLDxqiKGoTJeipBMDXuSfUTg9agdUBzwGsFCMZJSLJ4cYWQUG6tMY3AaLS MOniFSWAyMTYTif8NQsspDwq92mtLcETXdUz5A== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block SIoa1SLEDIJ50U+1JCg5zLLYmPSw4kw2HFkGIoi2lK+mwV4W3mmmZAX326KwZQjzb9VWnIVFdT1Y UN2hFjGyLs8z+rzG4Oy9dq7L+kkKeWNXb0jGjejfJbh8K9cxmEEPP8/IjSoJaNkIJlUxmJUnjyHE IKC2aqKScbgxjZHZt9w= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block gJv7V3tQbfvvgMOdcWebzitR5f3OA0wOotRLu972K8EfTJsXxH0DQMQ8HCrhd5UEee7Tvs6urOmX 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block j568ylTKCX1ijKCu3zCEYX4KzYIJPurwijBGL11yx0O4LKHLMP8dlqw1rKJAJyrIFXxSA8VDlDyI zGGu45lCWA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Zsr0AQ+BVB+qiaA/LMGWEJP/NrZG3InNL+c379B92bObAE0efeTZpmUE1xBqjehQpvWUAwUx+nu1 ovOY8kEzNgIq2y7PBozDXLUFYCGPeG8YSvcca9nazpYZq3J1pYo73+j7dFLANXGQbyuVYrJ2fYen tlUyhv+6QbaysUJuVbI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Q2+tD8NGxa+F0Kpjcc7LfAe6tSHp2t/mfv+sRfVCSbFXzphOA7xbOWMnCZ2v11rkLOTfvtsY9E5x egpSXJPwZm/DAmzKgDWCXDHkuVgfrpxeZMNdJ1lJ9SpDF+JD/u4nORV5Q5/DeeXs2+CQ5PqkdYUD eIjqeKg1UKhzovo4tymm7vrVQtfKqVoXYUxWEXB6QJLlvWA5gOpbJ72hUPw6a0NzFAS3PM9gJRWr +V/WEj/+m/HldnM/s5CLDxqiKGoTJeipBMDXuSfUTg9agdUBzwGsFCMZJSLJ4cYWQUG6tMY3AaLS MOniFSWAyMTYTif8NQsspDwq92mtLcETXdUz5A== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block SIoa1SLEDIJ50U+1JCg5zLLYmPSw4kw2HFkGIoi2lK+mwV4W3mmmZAX326KwZQjzb9VWnIVFdT1Y UN2hFjGyLs8z+rzG4Oy9dq7L+kkKeWNXb0jGjejfJbh8K9cxmEEPP8/IjSoJaNkIJlUxmJUnjyHE IKC2aqKScbgxjZHZt9w= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block gJv7V3tQbfvvgMOdcWebzitR5f3OA0wOotRLu972K8EfTJsXxH0DQMQ8HCrhd5UEee7Tvs6urOmX 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block j568ylTKCX1ijKCu3zCEYX4KzYIJPurwijBGL11yx0O4LKHLMP8dlqw1rKJAJyrIFXxSA8VDlDyI zGGu45lCWA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Zsr0AQ+BVB+qiaA/LMGWEJP/NrZG3InNL+c379B92bObAE0efeTZpmUE1xBqjehQpvWUAwUx+nu1 ovOY8kEzNgIq2y7PBozDXLUFYCGPeG8YSvcca9nazpYZq3J1pYo73+j7dFLANXGQbyuVYrJ2fYen tlUyhv+6QbaysUJuVbI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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entity sig is end; architecture behav of sig is signal s : natural; signal last : time; begin s <= 1 after 20 ns; b: block port (q : boolean); port map (q => s'quiet(10 ns)); begin process (q) begin report "q is " & boolean'image (q); last <= now; end process; end block; process begin wait for 100 ns; assert last = 30 ns severity failure; wait; end process; end;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2094.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY vests9 IS END vests9; ARCHITECTURE c07s02b04x00p20n01i02094arch OF vests9 IS TYPE boolean_v is array (integer range <>) of boolean; SUBTYPE boolean_4 is boolean_v (1 to 4); SUBTYPE boolean_8 is boolean_v (1 to 8); FUNCTION return_array RETURN boolean_4 is constant l_operand : boolean_4 := (true,false,true,false); begin RETURN l_operand; end return_array; BEGIN l : block generic ( info : boolean_8 ); generic map ( return_array & return_array ); begin assert NOT(info = (true,false,true,false,true,false,true,false)) report "*PASSED TEST: c07s02b04x00p20n01i02094" severity NOTE; assert (info = (true,false,true,false,true,false,true,false)) report "*FAILED TEST: c07s02b04x00p20n01i02094 - Function array concatenation did not succeed." severity ERROR; end block; END c07s02b04x00p20n01i02094arch;
------------------------------------------------------------------- -- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. -- -- -- -- This file contains confidential and proprietary information -- -- of Xilinx, Inc. and is protected under U.S. and -- -- international copyright and other intellectual property -- -- laws. -- -- -- -- DISCLAIMER -- -- This disclaimer is not a license and does not grant any -- -- rights to the materials distributed herewith. Except as -- -- otherwise provided in a valid license issued to you by -- -- Xilinx, and to the maximum extent permitted by applicable -- -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- -- (2) Xilinx shall not be liable (whether in contract or tort, -- -- including negligence, or under any other theory of -- -- liability) for any loss or damage of any kind or nature -- -- related to, arising under or in connection with these -- -- materials, including for any direct, or any indirect, -- -- special, incidental, or consequential loss or damage -- -- (including loss of data, profits, goodwill, or any type of -- -- loss or damage suffered as a result of any action brought -- -- by a third party) even if such damage or loss was -- -- reasonably foreseeable or Xilinx had been advised of the -- -- possibility of the same. -- -- -- -- CRITICAL APPLICATIONS -- -- Xilinx products are not designed or intended to be fail- -- -- safe, or for use in any application requiring fail-safe -- -- performance, such as life-support or safety devices or -- -- systems, Class III medical devices, nuclear facilities, -- -- applications related to the deployment of airbags, or any -- -- other applications that could lead to death, personal -- -- injury, or severe property or environmental damage -- -- (individually and collectively, "Critical -- -- Applications"). Customer assumes the sole risk and -- -- liability of any use of Xilinx products in Critical -- -- Applications, subject only to applicable laws and -- -- regulations governing limitations on product liability. -- -- -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------- -- ************************************************************************ -- ------------------------------------------------------------------------------- -- Filename: address_decoder.vhd -- Version: v1.01.a -- Description: Address decoder utilizing unconstrained arrays for Base -- Address specification and ce number. ------------------------------------------------------------------------------- -- Structure: This section shows the hierarchical structure of axi_lite_ipif. -- -- --axi_lite_ipif.vhd -- --slave_attachment.vhd -- --address_decoder.vhd ------------------------------------------------------------------------------- -- Author: BSB -- -- History: -- -- BSB 05/20/10 -- First version -- ~~~~~~ -- - Created the first version v1.00.a -- ^^^^^^ -- ~~~~~~ -- SK 08/09/2010 -- -- - updated the core with optimziation. Closed CR 574507 -- - combined the CE generation logic to further optimize the code. -- ^^^^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; use work.common_types.all; ------------------------------------------------------------------------------- -- Definition of Generics ------------------------------------------------------------------------------- -- C_BUS_AWIDTH -- Address bus width -- C_S_AXI_MIN_SIZE -- Minimum address range of the IP -- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range -- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range -- C_FAMILY -- Target FPGA family ------------------------------------------------------------------------------- -- Definition of Ports ------------------------------------------------------------------------------- -- Bus_clk -- Clock -- Bus_rst -- Reset -- Address_In_Erly -- Adddress in -- Address_Valid_Erly -- Address is valid -- Bus_RNW -- Read or write registered -- Bus_RNW_Erly -- Read or Write -- CS_CE_ld_enable -- chip select and chip enable registered -- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear -- RW_CE_ld_enable -- Read or Write Chip Enable -- CS_for_gaps -- CS generation for the gaps between address ranges -- CS_Out -- Chip select -- RdCE_Out -- Read Chip enable -- WrCE_Out -- Write chip enable ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Entity Declaration ------------------------------------------------------------------------------- entity address_decoder is generic ( C_BUS_AWIDTH : integer := 32; C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF"; C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := ( X"0000_0000_1000_0000", -- IP user0 base address X"0000_0000_1000_01FF", -- IP user0 high address X"0000_0000_1000_0200", -- IP user1 base address X"0000_0000_1000_02FF" -- IP user1 high address ); C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 8, -- User0 CE Number 1 -- User1 CE Number ); C_FAMILY : string := "virtex6" ); port ( Bus_clk : in std_logic; Bus_rst : in std_logic; -- PLB Interface signals Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1); Address_Valid_Erly : in std_logic; Bus_RNW : in std_logic; Bus_RNW_Erly : in std_logic; -- Registering control signals CS_CE_ld_enable : in std_logic; Clear_CS_CE_Reg : in std_logic; RW_CE_ld_enable : in std_logic; CS_for_gaps : out std_logic; -- Decode output signals CS_Out : out std_logic_vector (0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1); RdCE_Out : out std_logic_vector (0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1); WrCE_Out : out std_logic_vector (0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) ); end entity address_decoder; ------------------------------------------------------------------------------- -- Architecture section ------------------------------------------------------------------------------- architecture IMP of address_decoder is -- local type declarations ---------------------------------------------------- type decode_bit_array_type is Array(natural range 0 to ( (C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of integer; type short_addr_array_type is Array(natural range 0 to C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of std_logic_vector(0 to C_BUS_AWIDTH-1); ------------------------------------------------------------------------------- -- Function Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- This function converts a 64 bit address range array to a AWIDTH bit -- address range array. ------------------------------------------------------------------------------- function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE; awidth : integer) return short_addr_array_type is variable temp_addr : std_logic_vector(0 to 63); variable slv_array : short_addr_array_type; begin for array_index in 0 to slv64_addr_array'length-1 loop temp_addr := slv64_addr_array(array_index); slv_array(array_index) := temp_addr((64-awidth) to 63); end loop; return(slv_array); end function slv64_2_slv_awidth; ------------------------------------------------------------------------------- --Function Addr_bits --function to convert an address range (base address and an upper address) --into the number of upper address bits needed for decoding a device --select signal. will handle slices and big or little endian ------------------------------------------------------------------------------- function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1)) return integer is variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1); begin addr_nor := x xor y; for i in 0 to C_BUS_AWIDTH-1 loop if addr_nor(i)='1' then return i; end if; end loop; --coverage off return(C_BUS_AWIDTH); --coverage on end function Addr_Bits; ------------------------------------------------------------------------------- --Function Get_Addr_Bits --function calculates the array which has the decode bits for the each address --range. ------------------------------------------------------------------------------- function Get_Addr_Bits (baseaddrs : short_addr_array_type) return decode_bit_array_type is variable num_bits : decode_bit_array_type; begin for i in 0 to ((baseaddrs'length)/2)-1 loop num_bits(i) := Addr_Bits (baseaddrs(i2), baseaddrs(i2+1)); end loop; return(num_bits); end function Get_Addr_Bits; ------------------------------------------------------------------------------- -- NEEDED_ADDR_BITS -- -- Function Description: -- This function calculates the number of address bits required -- to support the CE generation logic. This is determined by -- multiplying the number of CEs for an address space by the -- data width of the address space (in bytes). Each address -- space entry is processed and the biggest of the spaces is -- used to set the number of address bits required to be latched -- and used for CE decoding. A minimum value of 1 is returned by -- this function. -- ------------------------------------------------------------------------------- function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE) return integer is constant NUM_CE_ENTRIES : integer := CE_ARRAY'length; variable biggest : integer := 2; variable req_ce_addr_size : integer := 0; variable num_addr_bits : integer := 0; begin for i in 0 to NUM_CE_ENTRIES-1 loop req_ce_addr_size := ce_array(i) 4; if (req_ce_addr_size > biggest) Then biggest := req_ce_addr_size; end if; end loop; num_addr_bits := clog2(biggest); return(num_addr_bits); end function NEEDED_ADDR_BITS; ----------------------------------------------------------------------------- -- Function calc_high_address -- -- This function is used to calculate the high address of the each address -- range ----------------------------------------------------------------------------- function calc_high_address (high_address : short_addr_array_type; index : integer) return std_logic_vector is variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1); begin If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31); else calc_high_addr := high_address(index2+2); end if; return(calc_high_addr); end function calc_high_address; ---------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type := slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY, C_BUS_AWIDTH); constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2; constant DECODE_BITS : decode_bit_array_type := Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY); constant NUM_CE_SIGNALS : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY); constant NUM_S_H_ADDR_BITS : integer := needed_addr_bits(C_ARD_NUM_CE_ARRAY); ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- signal pselect_hit_i : std_logic_vector (0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1); signal cs_out_i : std_logic_vector (0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1); signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); -- signal cs_ce_clr : std_logic; signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1); signal Bus_RNW_reg : std_logic; ------------------------------------------------------------------------------- -- Begin architecture ------------------------------------------------------------------------------- begin -- architecture IMP -- Register clears cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg; addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS to C_BUS_AWIDTH-1); ------------------------------------------------------------------------------- -- MEM_DECODE_GEN: Universal Address Decode Block ------------------------------------------------------------------------------- MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate --------------- constant CE_INDEX_START : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index); constant CE_ADDR_SIZE : Integer range 0 to 15 := clog2(C_ARD_NUM_CE_ARRAY(bar_index)); constant OFFSET : integer := 2; constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1) := ARD_ADDR_RANGE_ARRAY(bar_index2+1); constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1) := calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index); --constant DECODE_BITS_0 : integer:= DECODE_BITS(0); --------- begin --------- -- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address -- ----------------- GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate -- Instantiate the basic Base Address Decoders MEM_SELECT_I: entity work.pselect_f generic map ( C_AB => DECODE_BITS(bar_index), C_AW => C_BUS_AWIDTH, C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2), C_FAMILY => C_FAMILY ) port map ( A => Address_In_Erly, -- [in] AValid => Address_Valid_Erly, -- [in] CS => pselect_hit_i(bar_index) -- [out] ); end generate GEN_FOR_MULTI_CS; -- GEN_FOR_ONE_CS: below logic decodes the CS for single address range -- --------------- GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate pselect_hit_i(bar_index) <= Address_Valid_Erly; end generate GEN_FOR_ONE_CS; -- Instantate backend registers for the Chip Selects BKEND_CS_REG : process(Bus_Clk) begin if(Bus_Clk'EVENT and Bus_Clk = '1')then if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then cs_out_i(bar_index) <= '0'; elsif(CS_CE_ld_enable='1')then cs_out_i(bar_index) <= pselect_hit_i(bar_index); end if; end if; end process BKEND_CS_REG; ------------------------------------------------------------------------- -- PER_CE_GEN: Now expand the individual CEs for each base address. ------------------------------------------------------------------------- PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate ----------- begin ----------- ---------------------------------------------------------------------- -- CE decoders for multiple CE's ---------------------------------------------------------------------- MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) := std_logic_vector(to_unsigned(j,CE_ADDR_SIZE)); begin CE_I : entity work.pselect_f generic map ( C_AB => CE_ADDR_SIZE , C_AW => CE_ADDR_SIZE , C_BAR => BAR , C_FAMILY => C_FAMILY ) port map ( A => addr_out_s_h (NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE to NUM_S_H_ADDR_BITS - OFFSET - 1) , AValid => pselect_hit_i(bar_index) , CS => ce_expnd_i(CE_INDEX_START+j) ); end generate MULTIPLE_CES_THIS_CS_GEN; -------------------------------------- ---------------------------------------------------------------------- -- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE ---------------------------------------------------------------------- SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index); end generate; ------------- end generate PER_CE_GEN; ------------------------ end generate MEM_DECODE_GEN; -- RNW_REG_P: Register the incoming RNW signal at the time of registering the -- address. This is need to generate the CE's separately. RNW_REG_P:process(Bus_Clk) begin if(Bus_Clk'EVENT and Bus_Clk = '1')then if(RW_CE_ld_enable='1')then Bus_RNW_reg <= Bus_RNW_Erly; end if; end if; end process RNW_REG_P; --------------------------------------------------------------------------- -- GEN_BKEND_CE_REGISTERS -- This ForGen implements the backend registering for -- the CE, RdCE, and WrCE output buses. --------------------------------------------------------------------------- GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); ------ begin ------ BKEND_RDCE_REG : process(Bus_Clk) begin if(Bus_Clk'EVENT and Bus_Clk = '1')then if(cs_ce_clr='1')then ce_out_i(ce_index) <= '0'; elsif(RW_CE_ld_enable='1')then ce_out_i(ce_index) <= ce_expnd_i(ce_index); end if; end if; end process BKEND_RDCE_REG; rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg; wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg; ------------------------------- end generate GEN_BKEND_CE_REGISTERS; ------------------------------------------------------------------------------- CS_for_gaps <= '0'; -- Removed the GAP adecoder logic --------------------------------- CS_Out <= cs_out_i ; RdCE_Out <= rdce_out_i ; WrCE_Out <= wrce_out_i ; end architecture IMP;
------------------------------------------------------------------- -- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. -- -- -- -- This file contains confidential and proprietary information -- -- of Xilinx, Inc. and is protected under U.S. and -- -- international copyright and other intellectual property -- -- laws. -- -- -- -- DISCLAIMER -- -- This disclaimer is not a license and does not grant any -- -- rights to the materials distributed herewith. Except as -- -- otherwise provided in a valid license issued to you by -- -- Xilinx, and to the maximum extent permitted by applicable -- -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- -- (2) Xilinx shall not be liable (whether in contract or tort, -- -- including negligence, or under any other theory of -- -- liability) for any loss or damage of any kind or nature -- -- related to, arising under or in connection with these -- -- materials, including for any direct, or any indirect, -- -- special, incidental, or consequential loss or damage -- -- (including loss of data, profits, goodwill, or any type of -- -- loss or damage suffered as a result of any action brought -- -- by a third party) even if such damage or loss was -- -- reasonably foreseeable or Xilinx had been advised of the -- -- possibility of the same. -- -- -- -- CRITICAL APPLICATIONS -- -- Xilinx products are not designed or intended to be fail- -- -- safe, or for use in any application requiring fail-safe -- -- performance, such as life-support or safety devices or -- -- systems, Class III medical devices, nuclear facilities, -- -- applications related to the deployment of airbags, or any -- -- other applications that could lead to death, personal -- -- injury, or severe property or environmental damage -- -- (individually and collectively, "Critical -- -- Applications"). Customer assumes the sole risk and -- -- liability of any use of Xilinx products in Critical -- -- Applications, subject only to applicable laws and -- -- regulations governing limitations on product liability. -- -- -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------- -- ************************************************************************ -- ------------------------------------------------------------------------------- -- Filename: address_decoder.vhd -- Version: v1.01.a -- Description: Address decoder utilizing unconstrained arrays for Base -- Address specification and ce number. ------------------------------------------------------------------------------- -- Structure: This section shows the hierarchical structure of axi_lite_ipif. -- -- --axi_lite_ipif.vhd -- --slave_attachment.vhd -- --address_decoder.vhd ------------------------------------------------------------------------------- -- Author: BSB -- -- History: -- -- BSB 05/20/10 -- First version -- ~~~~~~ -- - Created the first version v1.00.a -- ^^^^^^ -- ~~~~~~ -- SK 08/09/2010 -- -- - updated the core with optimziation. Closed CR 574507 -- - combined the CE generation logic to further optimize the code. -- ^^^^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; use work.common_types.all; ------------------------------------------------------------------------------- -- Definition of Generics ------------------------------------------------------------------------------- -- C_BUS_AWIDTH -- Address bus width -- C_S_AXI_MIN_SIZE -- Minimum address range of the IP -- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range -- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range -- C_FAMILY -- Target FPGA family ------------------------------------------------------------------------------- -- Definition of Ports ------------------------------------------------------------------------------- -- Bus_clk -- Clock -- Bus_rst -- Reset -- Address_In_Erly -- Adddress in -- Address_Valid_Erly -- Address is valid -- Bus_RNW -- Read or write registered -- Bus_RNW_Erly -- Read or Write -- CS_CE_ld_enable -- chip select and chip enable registered -- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear -- RW_CE_ld_enable -- Read or Write Chip Enable -- CS_for_gaps -- CS generation for the gaps between address ranges -- CS_Out -- Chip select -- RdCE_Out -- Read Chip enable -- WrCE_Out -- Write chip enable ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Entity Declaration ------------------------------------------------------------------------------- entity address_decoder is generic ( C_BUS_AWIDTH : integer := 32; C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF"; C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := ( X"0000_0000_1000_0000", -- IP user0 base address X"0000_0000_1000_01FF", -- IP user0 high address X"0000_0000_1000_0200", -- IP user1 base address X"0000_0000_1000_02FF" -- IP user1 high address ); C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 8, -- User0 CE Number 1 -- User1 CE Number ); C_FAMILY : string := "virtex6" ); port ( Bus_clk : in std_logic; Bus_rst : in std_logic; -- PLB Interface signals Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1); Address_Valid_Erly : in std_logic; Bus_RNW : in std_logic; Bus_RNW_Erly : in std_logic; -- Registering control signals CS_CE_ld_enable : in std_logic; Clear_CS_CE_Reg : in std_logic; RW_CE_ld_enable : in std_logic; CS_for_gaps : out std_logic; -- Decode output signals CS_Out : out std_logic_vector (0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1); RdCE_Out : out std_logic_vector (0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1); WrCE_Out : out std_logic_vector (0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) ); end entity address_decoder; ------------------------------------------------------------------------------- -- Architecture section ------------------------------------------------------------------------------- architecture IMP of address_decoder is -- local type declarations ---------------------------------------------------- type decode_bit_array_type is Array(natural range 0 to ( (C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of integer; type short_addr_array_type is Array(natural range 0 to C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of std_logic_vector(0 to C_BUS_AWIDTH-1); ------------------------------------------------------------------------------- -- Function Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- This function converts a 64 bit address range array to a AWIDTH bit -- address range array. ------------------------------------------------------------------------------- function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE; awidth : integer) return short_addr_array_type is variable temp_addr : std_logic_vector(0 to 63); variable slv_array : short_addr_array_type; begin for array_index in 0 to slv64_addr_array'length-1 loop temp_addr := slv64_addr_array(array_index); slv_array(array_index) := temp_addr((64-awidth) to 63); end loop; return(slv_array); end function slv64_2_slv_awidth; ------------------------------------------------------------------------------- --Function Addr_bits --function to convert an address range (base address and an upper address) --into the number of upper address bits needed for decoding a device --select signal. will handle slices and big or little endian ------------------------------------------------------------------------------- function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1)) return integer is variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1); begin addr_nor := x xor y; for i in 0 to C_BUS_AWIDTH-1 loop if addr_nor(i)='1' then return i; end if; end loop; --coverage off return(C_BUS_AWIDTH); --coverage on end function Addr_Bits; ------------------------------------------------------------------------------- --Function Get_Addr_Bits --function calculates the array which has the decode bits for the each address --range. ------------------------------------------------------------------------------- function Get_Addr_Bits (baseaddrs : short_addr_array_type) return decode_bit_array_type is variable num_bits : decode_bit_array_type; begin for i in 0 to ((baseaddrs'length)/2)-1 loop num_bits(i) := Addr_Bits (baseaddrs(i2), baseaddrs(i2+1)); end loop; return(num_bits); end function Get_Addr_Bits; ------------------------------------------------------------------------------- -- NEEDED_ADDR_BITS -- -- Function Description: -- This function calculates the number of address bits required -- to support the CE generation logic. This is determined by -- multiplying the number of CEs for an address space by the -- data width of the address space (in bytes). Each address -- space entry is processed and the biggest of the spaces is -- used to set the number of address bits required to be latched -- and used for CE decoding. A minimum value of 1 is returned by -- this function. -- ------------------------------------------------------------------------------- function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE) return integer is constant NUM_CE_ENTRIES : integer := CE_ARRAY'length; variable biggest : integer := 2; variable req_ce_addr_size : integer := 0; variable num_addr_bits : integer := 0; begin for i in 0 to NUM_CE_ENTRIES-1 loop req_ce_addr_size := ce_array(i) 4; if (req_ce_addr_size > biggest) Then biggest := req_ce_addr_size; end if; end loop; num_addr_bits := clog2(biggest); return(num_addr_bits); end function NEEDED_ADDR_BITS; ----------------------------------------------------------------------------- -- Function calc_high_address -- -- This function is used to calculate the high address of the each address -- range ----------------------------------------------------------------------------- function calc_high_address (high_address : short_addr_array_type; index : integer) return std_logic_vector is variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1); begin If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31); else calc_high_addr := high_address(index2+2); end if; return(calc_high_addr); end function calc_high_address; ---------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type := slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY, C_BUS_AWIDTH); constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2; constant DECODE_BITS : decode_bit_array_type := Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY); constant NUM_CE_SIGNALS : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY); constant NUM_S_H_ADDR_BITS : integer := needed_addr_bits(C_ARD_NUM_CE_ARRAY); ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- signal pselect_hit_i : std_logic_vector (0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1); signal cs_out_i : std_logic_vector (0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1); signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); -- signal cs_ce_clr : std_logic; signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1); signal Bus_RNW_reg : std_logic; ------------------------------------------------------------------------------- -- Begin architecture ------------------------------------------------------------------------------- begin -- architecture IMP -- Register clears cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg; addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS to C_BUS_AWIDTH-1); ------------------------------------------------------------------------------- -- MEM_DECODE_GEN: Universal Address Decode Block ------------------------------------------------------------------------------- MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate --------------- constant CE_INDEX_START : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index); constant CE_ADDR_SIZE : Integer range 0 to 15 := clog2(C_ARD_NUM_CE_ARRAY(bar_index)); constant OFFSET : integer := 2; constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1) := ARD_ADDR_RANGE_ARRAY(bar_index2+1); constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1) := calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index); --constant DECODE_BITS_0 : integer:= DECODE_BITS(0); --------- begin --------- -- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address -- ----------------- GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate -- Instantiate the basic Base Address Decoders MEM_SELECT_I: entity work.pselect_f generic map ( C_AB => DECODE_BITS(bar_index), C_AW => C_BUS_AWIDTH, C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2), C_FAMILY => C_FAMILY ) port map ( A => Address_In_Erly, -- [in] AValid => Address_Valid_Erly, -- [in] CS => pselect_hit_i(bar_index) -- [out] ); end generate GEN_FOR_MULTI_CS; -- GEN_FOR_ONE_CS: below logic decodes the CS for single address range -- --------------- GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate pselect_hit_i(bar_index) <= Address_Valid_Erly; end generate GEN_FOR_ONE_CS; -- Instantate backend registers for the Chip Selects BKEND_CS_REG : process(Bus_Clk) begin if(Bus_Clk'EVENT and Bus_Clk = '1')then if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then cs_out_i(bar_index) <= '0'; elsif(CS_CE_ld_enable='1')then cs_out_i(bar_index) <= pselect_hit_i(bar_index); end if; end if; end process BKEND_CS_REG; ------------------------------------------------------------------------- -- PER_CE_GEN: Now expand the individual CEs for each base address. ------------------------------------------------------------------------- PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate ----------- begin ----------- ---------------------------------------------------------------------- -- CE decoders for multiple CE's ---------------------------------------------------------------------- MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) := std_logic_vector(to_unsigned(j,CE_ADDR_SIZE)); begin CE_I : entity work.pselect_f generic map ( C_AB => CE_ADDR_SIZE , C_AW => CE_ADDR_SIZE , C_BAR => BAR , C_FAMILY => C_FAMILY ) port map ( A => addr_out_s_h (NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE to NUM_S_H_ADDR_BITS - OFFSET - 1) , AValid => pselect_hit_i(bar_index) , CS => ce_expnd_i(CE_INDEX_START+j) ); end generate MULTIPLE_CES_THIS_CS_GEN; -------------------------------------- ---------------------------------------------------------------------- -- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE ---------------------------------------------------------------------- SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index); end generate; ------------- end generate PER_CE_GEN; ------------------------ end generate MEM_DECODE_GEN; -- RNW_REG_P: Register the incoming RNW signal at the time of registering the -- address. This is need to generate the CE's separately. RNW_REG_P:process(Bus_Clk) begin if(Bus_Clk'EVENT and Bus_Clk = '1')then if(RW_CE_ld_enable='1')then Bus_RNW_reg <= Bus_RNW_Erly; end if; end if; end process RNW_REG_P; --------------------------------------------------------------------------- -- GEN_BKEND_CE_REGISTERS -- This ForGen implements the backend registering for -- the CE, RdCE, and WrCE output buses. --------------------------------------------------------------------------- GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); ------ begin ------ BKEND_RDCE_REG : process(Bus_Clk) begin if(Bus_Clk'EVENT and Bus_Clk = '1')then if(cs_ce_clr='1')then ce_out_i(ce_index) <= '0'; elsif(RW_CE_ld_enable='1')then ce_out_i(ce_index) <= ce_expnd_i(ce_index); end if; end if; end process BKEND_RDCE_REG; rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg; wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg; ------------------------------- end generate GEN_BKEND_CE_REGISTERS; ------------------------------------------------------------------------------- CS_for_gaps <= '0'; -- Removed the GAP adecoder logic --------------------------------- CS_Out <= cs_out_i ; RdCE_Out <= rdce_out_i ; WrCE_Out <= wrce_out_i ; end architecture IMP;
------------------------------------------------------------------- -- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. -- -- -- -- This file contains confidential and proprietary information -- -- of Xilinx, Inc. and is protected under U.S. and -- -- international copyright and other intellectual property -- -- laws. -- -- -- -- DISCLAIMER -- -- This disclaimer is not a license and does not grant any -- -- rights to the materials distributed herewith. Except as -- -- otherwise provided in a valid license issued to you by -- -- Xilinx, and to the maximum extent permitted by applicable -- -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- -- (2) Xilinx shall not be liable (whether in contract or tort, -- -- including negligence, or under any other theory of -- -- liability) for any loss or damage of any kind or nature -- -- related to, arising under or in connection with these -- -- materials, including for any direct, or any indirect, -- -- special, incidental, or consequential loss or damage -- -- (including loss of data, profits, goodwill, or any type of -- -- loss or damage suffered as a result of any action brought -- -- by a third party) even if such damage or loss was -- -- reasonably foreseeable or Xilinx had been advised of the -- -- possibility of the same. -- -- -- -- CRITICAL APPLICATIONS -- -- Xilinx products are not designed or intended to be fail- -- -- safe, or for use in any application requiring fail-safe -- -- performance, such as life-support or safety devices or -- -- systems, Class III medical devices, nuclear facilities, -- -- applications related to the deployment of airbags, or any -- -- other applications that could lead to death, personal -- -- injury, or severe property or environmental damage -- -- (individually and collectively, "Critical -- -- Applications"). Customer assumes the sole risk and -- -- liability of any use of Xilinx products in Critical -- -- Applications, subject only to applicable laws and -- -- regulations governing limitations on product liability. -- -- -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------- -- ************************************************************************ -- ------------------------------------------------------------------------------- -- Filename: address_decoder.vhd -- Version: v1.01.a -- Description: Address decoder utilizing unconstrained arrays for Base -- Address specification and ce number. ------------------------------------------------------------------------------- -- Structure: This section shows the hierarchical structure of axi_lite_ipif. -- -- --axi_lite_ipif.vhd -- --slave_attachment.vhd -- --address_decoder.vhd ------------------------------------------------------------------------------- -- Author: BSB -- -- History: -- -- BSB 05/20/10 -- First version -- ~~~~~~ -- - Created the first version v1.00.a -- ^^^^^^ -- ~~~~~~ -- SK 08/09/2010 -- -- - updated the core with optimziation. Closed CR 574507 -- - combined the CE generation logic to further optimize the code. -- ^^^^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; use work.common_types.all; ------------------------------------------------------------------------------- -- Definition of Generics ------------------------------------------------------------------------------- -- C_BUS_AWIDTH -- Address bus width -- C_S_AXI_MIN_SIZE -- Minimum address range of the IP -- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range -- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range -- C_FAMILY -- Target FPGA family ------------------------------------------------------------------------------- -- Definition of Ports ------------------------------------------------------------------------------- -- Bus_clk -- Clock -- Bus_rst -- Reset -- Address_In_Erly -- Adddress in -- Address_Valid_Erly -- Address is valid -- Bus_RNW -- Read or write registered -- Bus_RNW_Erly -- Read or Write -- CS_CE_ld_enable -- chip select and chip enable registered -- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear -- RW_CE_ld_enable -- Read or Write Chip Enable -- CS_for_gaps -- CS generation for the gaps between address ranges -- CS_Out -- Chip select -- RdCE_Out -- Read Chip enable -- WrCE_Out -- Write chip enable ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Entity Declaration ------------------------------------------------------------------------------- entity address_decoder is generic ( C_BUS_AWIDTH : integer := 32; C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF"; C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := ( X"0000_0000_1000_0000", -- IP user0 base address X"0000_0000_1000_01FF", -- IP user0 high address X"0000_0000_1000_0200", -- IP user1 base address X"0000_0000_1000_02FF" -- IP user1 high address ); C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 8, -- User0 CE Number 1 -- User1 CE Number ); C_FAMILY : string := "virtex6" ); port ( Bus_clk : in std_logic; Bus_rst : in std_logic; -- PLB Interface signals Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1); Address_Valid_Erly : in std_logic; Bus_RNW : in std_logic; Bus_RNW_Erly : in std_logic; -- Registering control signals CS_CE_ld_enable : in std_logic; Clear_CS_CE_Reg : in std_logic; RW_CE_ld_enable : in std_logic; CS_for_gaps : out std_logic; -- Decode output signals CS_Out : out std_logic_vector (0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1); RdCE_Out : out std_logic_vector (0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1); WrCE_Out : out std_logic_vector (0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) ); end entity address_decoder; ------------------------------------------------------------------------------- -- Architecture section ------------------------------------------------------------------------------- architecture IMP of address_decoder is -- local type declarations ---------------------------------------------------- type decode_bit_array_type is Array(natural range 0 to ( (C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of integer; type short_addr_array_type is Array(natural range 0 to C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of std_logic_vector(0 to C_BUS_AWIDTH-1); ------------------------------------------------------------------------------- -- Function Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- This function converts a 64 bit address range array to a AWIDTH bit -- address range array. ------------------------------------------------------------------------------- function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE; awidth : integer) return short_addr_array_type is variable temp_addr : std_logic_vector(0 to 63); variable slv_array : short_addr_array_type; begin for array_index in 0 to slv64_addr_array'length-1 loop temp_addr := slv64_addr_array(array_index); slv_array(array_index) := temp_addr((64-awidth) to 63); end loop; return(slv_array); end function slv64_2_slv_awidth; ------------------------------------------------------------------------------- --Function Addr_bits --function to convert an address range (base address and an upper address) --into the number of upper address bits needed for decoding a device --select signal. will handle slices and big or little endian ------------------------------------------------------------------------------- function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1)) return integer is variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1); begin addr_nor := x xor y; for i in 0 to C_BUS_AWIDTH-1 loop if addr_nor(i)='1' then return i; end if; end loop; --coverage off return(C_BUS_AWIDTH); --coverage on end function Addr_Bits; ------------------------------------------------------------------------------- --Function Get_Addr_Bits --function calculates the array which has the decode bits for the each address --range. ------------------------------------------------------------------------------- function Get_Addr_Bits (baseaddrs : short_addr_array_type) return decode_bit_array_type is variable num_bits : decode_bit_array_type; begin for i in 0 to ((baseaddrs'length)/2)-1 loop num_bits(i) := Addr_Bits (baseaddrs(i2), baseaddrs(i2+1)); end loop; return(num_bits); end function Get_Addr_Bits; ------------------------------------------------------------------------------- -- NEEDED_ADDR_BITS -- -- Function Description: -- This function calculates the number of address bits required -- to support the CE generation logic. This is determined by -- multiplying the number of CEs for an address space by the -- data width of the address space (in bytes). Each address -- space entry is processed and the biggest of the spaces is -- used to set the number of address bits required to be latched -- and used for CE decoding. A minimum value of 1 is returned by -- this function. -- ------------------------------------------------------------------------------- function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE) return integer is constant NUM_CE_ENTRIES : integer := CE_ARRAY'length; variable biggest : integer := 2; variable req_ce_addr_size : integer := 0; variable num_addr_bits : integer := 0; begin for i in 0 to NUM_CE_ENTRIES-1 loop req_ce_addr_size := ce_array(i) 4; if (req_ce_addr_size > biggest) Then biggest := req_ce_addr_size; end if; end loop; num_addr_bits := clog2(biggest); return(num_addr_bits); end function NEEDED_ADDR_BITS; ----------------------------------------------------------------------------- -- Function calc_high_address -- -- This function is used to calculate the high address of the each address -- range ----------------------------------------------------------------------------- function calc_high_address (high_address : short_addr_array_type; index : integer) return std_logic_vector is variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1); begin If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31); else calc_high_addr := high_address(index2+2); end if; return(calc_high_addr); end function calc_high_address; ---------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type := slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY, C_BUS_AWIDTH); constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2; constant DECODE_BITS : decode_bit_array_type := Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY); constant NUM_CE_SIGNALS : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY); constant NUM_S_H_ADDR_BITS : integer := needed_addr_bits(C_ARD_NUM_CE_ARRAY); ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- signal pselect_hit_i : std_logic_vector (0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1); signal cs_out_i : std_logic_vector (0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1); signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); -- signal cs_ce_clr : std_logic; signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1); signal Bus_RNW_reg : std_logic; ------------------------------------------------------------------------------- -- Begin architecture ------------------------------------------------------------------------------- begin -- architecture IMP -- Register clears cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg; addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS to C_BUS_AWIDTH-1); ------------------------------------------------------------------------------- -- MEM_DECODE_GEN: Universal Address Decode Block ------------------------------------------------------------------------------- MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate --------------- constant CE_INDEX_START : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index); constant CE_ADDR_SIZE : Integer range 0 to 15 := clog2(C_ARD_NUM_CE_ARRAY(bar_index)); constant OFFSET : integer := 2; constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1) := ARD_ADDR_RANGE_ARRAY(bar_index2+1); constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1) := calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index); --constant DECODE_BITS_0 : integer:= DECODE_BITS(0); --------- begin --------- -- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address -- ----------------- GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate -- Instantiate the basic Base Address Decoders MEM_SELECT_I: entity work.pselect_f generic map ( C_AB => DECODE_BITS(bar_index), C_AW => C_BUS_AWIDTH, C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2), C_FAMILY => C_FAMILY ) port map ( A => Address_In_Erly, -- [in] AValid => Address_Valid_Erly, -- [in] CS => pselect_hit_i(bar_index) -- [out] ); end generate GEN_FOR_MULTI_CS; -- GEN_FOR_ONE_CS: below logic decodes the CS for single address range -- --------------- GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate pselect_hit_i(bar_index) <= Address_Valid_Erly; end generate GEN_FOR_ONE_CS; -- Instantate backend registers for the Chip Selects BKEND_CS_REG : process(Bus_Clk) begin if(Bus_Clk'EVENT and Bus_Clk = '1')then if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then cs_out_i(bar_index) <= '0'; elsif(CS_CE_ld_enable='1')then cs_out_i(bar_index) <= pselect_hit_i(bar_index); end if; end if; end process BKEND_CS_REG; ------------------------------------------------------------------------- -- PER_CE_GEN: Now expand the individual CEs for each base address. ------------------------------------------------------------------------- PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate ----------- begin ----------- ---------------------------------------------------------------------- -- CE decoders for multiple CE's ---------------------------------------------------------------------- MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) := std_logic_vector(to_unsigned(j,CE_ADDR_SIZE)); begin CE_I : entity work.pselect_f generic map ( C_AB => CE_ADDR_SIZE , C_AW => CE_ADDR_SIZE , C_BAR => BAR , C_FAMILY => C_FAMILY ) port map ( A => addr_out_s_h (NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE to NUM_S_H_ADDR_BITS - OFFSET - 1) , AValid => pselect_hit_i(bar_index) , CS => ce_expnd_i(CE_INDEX_START+j) ); end generate MULTIPLE_CES_THIS_CS_GEN; -------------------------------------- ---------------------------------------------------------------------- -- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE ---------------------------------------------------------------------- SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index); end generate; ------------- end generate PER_CE_GEN; ------------------------ end generate MEM_DECODE_GEN; -- RNW_REG_P: Register the incoming RNW signal at the time of registering the -- address. This is need to generate the CE's separately. RNW_REG_P:process(Bus_Clk) begin if(Bus_Clk'EVENT and Bus_Clk = '1')then if(RW_CE_ld_enable='1')then Bus_RNW_reg <= Bus_RNW_Erly; end if; end if; end process RNW_REG_P; --------------------------------------------------------------------------- -- GEN_BKEND_CE_REGISTERS -- This ForGen implements the backend registering for -- the CE, RdCE, and WrCE output buses. --------------------------------------------------------------------------- GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); ------ begin ------ BKEND_RDCE_REG : process(Bus_Clk) begin if(Bus_Clk'EVENT and Bus_Clk = '1')then if(cs_ce_clr='1')then ce_out_i(ce_index) <= '0'; elsif(RW_CE_ld_enable='1')then ce_out_i(ce_index) <= ce_expnd_i(ce_index); end if; end if; end process BKEND_RDCE_REG; rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg; wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg; ------------------------------- end generate GEN_BKEND_CE_REGISTERS; ------------------------------------------------------------------------------- CS_for_gaps <= '0'; -- Removed the GAP adecoder logic --------------------------------- CS_Out <= cs_out_i ; RdCE_Out <= rdce_out_i ; WrCE_Out <= wrce_out_i ; end architecture IMP;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- package: uart -- File: uart.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: UART types and components ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; package uart is type uart_in_type is record rxd : std_ulogic; ctsn : std_ulogic; extclk : std_ulogic; end record; type uart_out_type is record rtsn : std_ulogic; txd : std_ulogic; scaler : std_logic_vector(31 downto 0); txen : std_ulogic; flow : std_ulogic; rxen : std_ulogic; end record; component apbuart generic ( pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff#; console : integer := 0; pirq : integer := 0; parity : integer := 1; flow : integer := 1; fifosize : integer range 1 to 32 := 1; abits : integer := 8; sbits : integer range 12 to 32 := 12); port ( rst : in std_ulogic; clk : in std_ulogic; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; uarti : in uart_in_type; uarto : out uart_out_type); end component; component ahbuart generic ( hindex : integer := 0; pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff# ); port ( rst : in std_ulogic; clk : in std_ulogic; uarti : in uart_in_type; uarto : out uart_out_type; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; ahbi : in ahb_mst_in_type; ahbo : out ahb_mst_out_type); end component; end;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc881.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c10s01b00x00p06n01i00881PKG is -- VAL1 is here a constant constant VAL1 : INTEGER := 65; type DBLINTREC is record -- VAL1 is here a record element VAL1 : INTEGER; VAL2 : INTEGER; end record; end c10s01b00x00p06n01i00881PKG; use WORK.c10s01b00x00p06n01i00881PKG.DBLINTREC; entity c10s01b00x00p06n01i00881ent_a is port ( PS1: in DBLINTREC; PS2: out DBLINTREC ); end c10s01b00x00p06n01i00881ent_a; architecture c10s01b00x00p06n01i00881arch_a of c10s01b00x00p06n01i00881ent_a is begin process begin PS2.VAL1 <= PS1.VAL1 + 1; PS2.VAL2 <= PS1.VAL2 + 2; wait; end process; end c10s01b00x00p06n01i00881arch_a; use WORK.c10s01b00x00p06n01i00881PKG.DBLINTREC; use WORK.c10s01b00x00p06n01i00881ent_a; ENTITY c10s01b00x00p06n01i00881ent IS END c10s01b00x00p06n01i00881ent; ARCHITECTURE c10s01b00x00p06n01i00881arch OF c10s01b00x00p06n01i00881ent IS component c10s01b00x00p06n01i00881ent_a port ( PS1: in DBLINTREC; PS2: out DBLINTREC ); end component; for A1: c10s01b00x00p06n01i00881ent_a use entity work.c10s01b00x00p06n01i00881ent_a ( c10s01b00x00p06n01i00881arch_a ); signal S1: DBLINTREC := (3, 9); signal S2: DBLINTREC := (0, 0); BEGIN A1: c10s01b00x00p06n01i00881ent_a port map ( S1, S2 ); TESTING: PROCESS BEGIN wait for 1 ns; -- let a time increment go by so init done assert ( S2.VAL1 = 4 ) report "didn't add to record element S2.VAL1 correctly" severity FAILURE; assert ( S2.VAL2 = 11 ) report "didn't add to record element S2.VAL2 correctly" severity FAILURE; assert NOT( S2.VAL1 = 4 and S2.VAL2 =11 ) report "*PASSED TEST: c10s01b00x00p06n01i00881" severity NOTE; assert ( S2.VAL1 = 4 and S2.VAL2 =11 ) report "*FAILED TEST: c10s01b00x00p06n01i00881 - A declaratione region is formed by a record type declaration." severity ERROR; wait; END PROCESS TESTING; END c10s01b00x00p06n01i00881arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc881.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c10s01b00x00p06n01i00881PKG is -- VAL1 is here a constant constant VAL1 : INTEGER := 65; type DBLINTREC is record -- VAL1 is here a record element VAL1 : INTEGER; VAL2 : INTEGER; end record; end c10s01b00x00p06n01i00881PKG; use WORK.c10s01b00x00p06n01i00881PKG.DBLINTREC; entity c10s01b00x00p06n01i00881ent_a is port ( PS1: in DBLINTREC; PS2: out DBLINTREC ); end c10s01b00x00p06n01i00881ent_a; architecture c10s01b00x00p06n01i00881arch_a of c10s01b00x00p06n01i00881ent_a is begin process begin PS2.VAL1 <= PS1.VAL1 + 1; PS2.VAL2 <= PS1.VAL2 + 2; wait; end process; end c10s01b00x00p06n01i00881arch_a; use WORK.c10s01b00x00p06n01i00881PKG.DBLINTREC; use WORK.c10s01b00x00p06n01i00881ent_a; ENTITY c10s01b00x00p06n01i00881ent IS END c10s01b00x00p06n01i00881ent; ARCHITECTURE c10s01b00x00p06n01i00881arch OF c10s01b00x00p06n01i00881ent IS component c10s01b00x00p06n01i00881ent_a port ( PS1: in DBLINTREC; PS2: out DBLINTREC ); end component; for A1: c10s01b00x00p06n01i00881ent_a use entity work.c10s01b00x00p06n01i00881ent_a ( c10s01b00x00p06n01i00881arch_a ); signal S1: DBLINTREC := (3, 9); signal S2: DBLINTREC := (0, 0); BEGIN A1: c10s01b00x00p06n01i00881ent_a port map ( S1, S2 ); TESTING: PROCESS BEGIN wait for 1 ns; -- let a time increment go by so init done assert ( S2.VAL1 = 4 ) report "didn't add to record element S2.VAL1 correctly" severity FAILURE; assert ( S2.VAL2 = 11 ) report "didn't add to record element S2.VAL2 correctly" severity FAILURE; assert NOT( S2.VAL1 = 4 and S2.VAL2 =11 ) report "*PASSED TEST: c10s01b00x00p06n01i00881" severity NOTE; assert ( S2.VAL1 = 4 and S2.VAL2 =11 ) report "*FAILED TEST: c10s01b00x00p06n01i00881 - A declaratione region is formed by a record type declaration." severity ERROR; wait; END PROCESS TESTING; END c10s01b00x00p06n01i00881arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc881.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c10s01b00x00p06n01i00881PKG is -- VAL1 is here a constant constant VAL1 : INTEGER := 65; type DBLINTREC is record -- VAL1 is here a record element VAL1 : INTEGER; VAL2 : INTEGER; end record; end c10s01b00x00p06n01i00881PKG; use WORK.c10s01b00x00p06n01i00881PKG.DBLINTREC; entity c10s01b00x00p06n01i00881ent_a is port ( PS1: in DBLINTREC; PS2: out DBLINTREC ); end c10s01b00x00p06n01i00881ent_a; architecture c10s01b00x00p06n01i00881arch_a of c10s01b00x00p06n01i00881ent_a is begin process begin PS2.VAL1 <= PS1.VAL1 + 1; PS2.VAL2 <= PS1.VAL2 + 2; wait; end process; end c10s01b00x00p06n01i00881arch_a; use WORK.c10s01b00x00p06n01i00881PKG.DBLINTREC; use WORK.c10s01b00x00p06n01i00881ent_a; ENTITY c10s01b00x00p06n01i00881ent IS END c10s01b00x00p06n01i00881ent; ARCHITECTURE c10s01b00x00p06n01i00881arch OF c10s01b00x00p06n01i00881ent IS component c10s01b00x00p06n01i00881ent_a port ( PS1: in DBLINTREC; PS2: out DBLINTREC ); end component; for A1: c10s01b00x00p06n01i00881ent_a use entity work.c10s01b00x00p06n01i00881ent_a ( c10s01b00x00p06n01i00881arch_a ); signal S1: DBLINTREC := (3, 9); signal S2: DBLINTREC := (0, 0); BEGIN A1: c10s01b00x00p06n01i00881ent_a port map ( S1, S2 ); TESTING: PROCESS BEGIN wait for 1 ns; -- let a time increment go by so init done assert ( S2.VAL1 = 4 ) report "didn't add to record element S2.VAL1 correctly" severity FAILURE; assert ( S2.VAL2 = 11 ) report "didn't add to record element S2.VAL2 correctly" severity FAILURE; assert NOT( S2.VAL1 = 4 and S2.VAL2 =11 ) report "*PASSED TEST: c10s01b00x00p06n01i00881" severity NOTE; assert ( S2.VAL1 = 4 and S2.VAL2 =11 ) report "*FAILED TEST: c10s01b00x00p06n01i00881 - A declaratione region is formed by a record type declaration." severity ERROR; wait; END PROCESS TESTING; END c10s01b00x00p06n01i00881arch;
-- -- A simulation model of VIC20 hardware -- Copyright (c) MikeJ - March 2003 -- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written permission. -- -- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- You are responsible for any legal issues arising from your use of this code. -- -- The latest version of this file can be found at: www.fpgaarcade.com -- -- Email [email protected] -- -- -- Revision list -- -- version 004 fixes to PB7 T1 control and Mode 0 Shift Register operation -- version 003 fix reset of T1/T2 IFR flags if T1/T2 is reload via reg5/reg9 from wolfgang (WoS) -- Ported to numeric_std and simulation fix for signal initializations from arnim laeuger -- version 002 fix from Mark McDougall, untested -- version 001 initial release -- not very sure about the shift register, documentation is a bit light. library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity M6522 is port ( I_RS : in std_logic_vector(3 downto 0); I_DATA : in std_logic_vector(7 downto 0); O_DATA : out std_logic_vector(7 downto 0); O_DATA_OE_L : out std_logic; I_RW_L : in std_logic; I_CS1 : in std_logic; I_CS2_L : in std_logic; O_IRQ_L : out std_logic; -- note, not open drain -- port a I_CA1 : in std_logic; I_CA2 : in std_logic; O_CA2 : out std_logic; O_CA2_OE_L : out std_logic; I_PA : in std_logic_vector(7 downto 0); O_PA : out std_logic_vector(7 downto 0); O_PA_OE_L : out std_logic_vector(7 downto 0); -- port b I_CB1 : in std_logic; O_CB1 : out std_logic; O_CB1_OE_L : out std_logic; I_CB2 : in std_logic; O_CB2 : out std_logic; O_CB2_OE_L : out std_logic; I_PB : in std_logic_vector(7 downto 0); O_PB : out std_logic_vector(7 downto 0); O_PB_OE_L : out std_logic_vector(7 downto 0); I_P2_H : in std_logic; -- high for phase 2 clock ____----__ RESET_L : in std_logic; ENA_4 : in std_logic; -- clk enable CLK : in std_logic ); end; architecture RTL of M6522 is signal phase : std_logic_vector(1 downto 0):="00"; signal p2_h_t1 : std_logic; signal cs : std_logic; -- registers signal r_ddra : std_logic_vector(7 downto 0); signal r_ora : std_logic_vector(7 downto 0); signal r_ira : std_logic_vector(7 downto 0); signal r_ddrb : std_logic_vector(7 downto 0); signal r_orb : std_logic_vector(7 downto 0); signal r_irb : std_logic_vector(7 downto 0); signal r_t1l_l : std_logic_vector(7 downto 0); signal r_t1l_h : std_logic_vector(7 downto 0); signal r_t2l_l : std_logic_vector(7 downto 0); signal r_t2l_h : std_logic_vector(7 downto 0); -- not in real chip signal r_sr : std_logic_vector(7 downto 0); signal r_acr : std_logic_vector(7 downto 0); signal r_pcr : std_logic_vector(7 downto 0); signal r_ifr : std_logic_vector(7 downto 0); signal r_ier : std_logic_vector(6 downto 0); signal sr_write_ena : boolean; signal sr_read_ena : boolean; signal ifr_write_ena : boolean; signal ier_write_ena : boolean; signal clear_irq : std_logic_vector(7 downto 0); signal load_data : std_logic_vector(7 downto 0); -- timer 1 signal t1c : std_logic_vector(15 downto 0) := (others => '1'); -- simulators may not catch up w/o init here... signal t1c_active : boolean; signal t1c_done : boolean; signal t1_w_reset_int : boolean; signal t1_r_reset_int : boolean; signal t1_load_counter : boolean; signal t1_reload_counter : boolean; signal t1_toggle : std_logic; signal t1_irq : std_logic := '0'; -- timer 2 signal t2c : std_logic_vector(15 downto 0) := (others => '1'); -- simulators may not catch up w/o init here... signal t2c_active : boolean; signal t2c_done : boolean; signal t2_pb6 : std_logic; signal t2_pb6_t1 : std_logic; signal t2_w_reset_int : boolean; signal t2_r_reset_int : boolean; signal t2_load_counter : boolean; signal t2_reload_counter : boolean; signal t2_irq : std_logic := '0'; signal t2_sr_ena : boolean; -- shift reg signal sr_cnt : std_logic_vector(3 downto 0); signal sr_cb1_oe_l : std_logic; signal sr_cb1_out : std_logic; signal sr_drive_cb2 : std_logic; signal sr_strobe : std_logic; signal sr_strobe_t1 : std_logic; signal sr_strobe_falling : boolean; signal sr_strobe_rising : boolean; signal sr_irq : std_logic; signal sr_out : std_logic; signal sr_off_delay : std_logic; -- io signal w_orb_hs : std_logic; signal w_ora_hs : std_logic; signal r_irb_hs : std_logic; signal r_ira_hs : std_logic; signal ca_hs_sr : std_logic; signal ca_hs_pulse : std_logic; signal cb_hs_sr : std_logic; signal cb_hs_pulse : std_logic; signal cb1_in_mux : std_logic; signal ca1_ip_reg : std_logic; signal cb1_ip_reg : std_logic; signal ca1_int : boolean; signal cb1_int : boolean; signal ca1_irq : std_logic; signal cb1_irq : std_logic; signal ca2_ip_reg : std_logic; signal cb2_ip_reg : std_logic; signal ca2_int : boolean; signal cb2_int : boolean; signal ca2_irq : std_logic; signal cb2_irq : std_logic; signal final_irq : std_logic; begin p_phase : process begin -- internal clock phase wait until rising_edge(CLK); if (ENA_4 = '1') then p2_h_t1 <= I_P2_H; if (p2_h_t1 = '0') and (I_P2_H = '1') then phase <= "11"; else phase <= phase + "1"; end if; end if; end process; p_cs : process(I_CS1, I_CS2_L, I_P2_H) begin cs <= '0'; if (I_CS1 = '1') and (I_CS2_L = '0') and (I_P2_H = '1') then cs <= '1'; end if; end process; -- peripheral control reg (pcr) -- 0 ca1 interrupt control (0 +ve edge, 1 -ve edge) -- 3..1 ca2 operation -- 000 input -ve edge -- 001 independend interrupt input -ve edge -- 010 input +ve edge -- 011 independend interrupt input +ve edge -- 100 handshake output -- 101 pulse output -- 110 low output -- 111 high output -- 7..4 as 3..0 for cb1,cb2 -- auxiliary control reg (acr) -- 0 input latch PA (0 disable, 1 enable) -- 1 input latch PB (0 disable, 1 enable) -- 4..2 shift reg control -- 000 disable -- 001 shift in using t2 -- 010 shift in using o2 -- 011 shift in using ext clk -- 100 shift out free running t2 rate -- 101 shift out using t2 -- 101 shift out using o2 -- 101 shift out using ext clk -- 5 t2 timer control (0 timed interrupt, 1 count down with pulses on pb6) -- 7..6 t1 timer control -- 00 timed interrupt each time t1 is loaded pb7 disable -- 01 continuous interrupts pb7 disable -- 00 timed interrupt each time t1 is loaded pb7 one shot output -- 01 continuous interrupts pb7 square wave output -- p_write_reg_reset : process(RESET_L, CLK) begin if (RESET_L = '0') then r_ora <= x"00"; r_orb <= x"00"; r_ddra <= x"00"; r_ddrb <= x"00"; r_acr <= x"00"; r_pcr <= x"00"; w_orb_hs <= '0'; w_ora_hs <= '0'; elsif rising_edge(CLK) then if (ENA_4 = '1') then w_orb_hs <= '0'; w_ora_hs <= '0'; if (cs = '1') and (I_RW_L = '0') then case I_RS is when x"0" => r_orb <= I_DATA; w_orb_hs <= '1'; when x"1" => r_ora <= I_DATA; w_ora_hs <= '1'; when x"2" => r_ddrb <= I_DATA; when x"3" => r_ddra <= I_DATA; when x"B" => r_acr <= I_DATA; when x"C" => r_pcr <= I_DATA; when x"F" => r_ora <= I_DATA; when others => null; end case; end if; if r_acr(7) = '1' then -- DMB: Forgetting to clear B7 broke Acornsoft Planetoid if t1_load_counter then r_orb(7) <= '0'; -- writing T1C-H resets bit 7 elsif t1_toggle = '1' then r_orb(7) <= not r_orb(7); -- toggle end if; end if; end if; end if; end process; p_write_reg : process (RESET_L, CLK) is begin if (RESET_L = '0') then -- The spec says, this is not reset. -- Fact is that the 1541 VIA1 timer won't work, -- as the firmware ONLY sets the r_t1l_h latch!!!! r_t1l_l <= (others => '0'); r_t1l_h <= (others => '0'); r_t2l_l <= (others => '0'); r_t2l_h <= (others => '0'); elsif rising_edge(CLK) then if (ENA_4 = '1') then t1_w_reset_int <= false; t1_load_counter <= false; t2_w_reset_int <= false; t2_load_counter <= false; load_data <= x"00"; sr_write_ena <= false; ifr_write_ena <= false; ier_write_ena <= false; if (cs = '1') and (I_RW_L = '0') then load_data <= I_DATA; case I_RS is when x"4" => r_t1l_l <= I_DATA; when x"5" => r_t1l_h <= I_DATA; t1_w_reset_int <= true; t1_load_counter <= true; when x"6" => r_t1l_l <= I_DATA; when x"7" => r_t1l_h <= I_DATA; t1_w_reset_int <= true; when x"8" => r_t2l_l <= I_DATA; when x"9" => r_t2l_h <= I_DATA; t2_w_reset_int <= true; t2_load_counter <= true; when x"A" => sr_write_ena <= true; when x"D" => ifr_write_ena <= true; when x"E" => ier_write_ena <= true; when others => null; end case; end if; end if; end if; end process; p_oe : process(cs, I_RW_L) begin O_DATA_OE_L <= '1'; if (cs = '1') and (I_RW_L = '1') then O_DATA_OE_L <= '0'; end if; end process; p_read : process(cs, I_RW_L, I_RS, r_irb, r_ira, r_ddrb, r_ddra, t1c, r_t1l_l, r_t1l_h, t2c, r_sr, r_acr, r_pcr, r_ifr, r_ier, r_orb) begin t1_r_reset_int <= false; t2_r_reset_int <= false; sr_read_ena <= false; r_irb_hs <= '0'; r_ira_hs <= '0'; O_DATA <= x"00"; -- default if (cs = '1') and (I_RW_L = '1') then case I_RS is --when x"0" => O_DATA <= r_irb; r_irb_hs <= '1'; -- fix from Mark McDougall, untested when x"0" => O_DATA <= (r_irb and not r_ddrb) or (r_orb and r_ddrb); r_irb_hs <= '1'; when x"1" => O_DATA <= r_ira; r_ira_hs <= '1'; when x"2" => O_DATA <= r_ddrb; when x"3" => O_DATA <= r_ddra; when x"4" => O_DATA <= t1c( 7 downto 0); t1_r_reset_int <= true; when x"5" => O_DATA <= t1c(15 downto 8); when x"6" => O_DATA <= r_t1l_l; when x"7" => O_DATA <= r_t1l_h; when x"8" => O_DATA <= t2c( 7 downto 0); t2_r_reset_int <= true; when x"9" => O_DATA <= t2c(15 downto 8); when x"A" => O_DATA <= r_sr; sr_read_ena <= true; when x"B" => O_DATA <= r_acr; when x"C" => O_DATA <= r_pcr; when x"D" => O_DATA <= r_ifr; when x"E" => O_DATA <= ('0' & r_ier); when x"F" => O_DATA <= r_ira; when others => null; end case; end if; end process; -- -- IO -- p_ca1_cb1_sel : process(sr_cb1_oe_l, sr_cb1_out, I_CB1) begin -- if the shift register is enabled, cb1 may be an output -- in this case, we should listen to the CB1_OUT for the interrupt if (sr_cb1_oe_l = '1') then cb1_in_mux <= I_CB1; else cb1_in_mux <= sr_cb1_out; end if; end process; p_ca1_cb1_int : process(r_pcr, ca1_ip_reg, I_CA1, cb1_ip_reg, cb1_in_mux) begin if (r_pcr(0) = '0') then -- ca1 control -- negative edge ca1_int <= (ca1_ip_reg = '1') and (I_CA1 = '0'); else -- positive edge ca1_int <= (ca1_ip_reg = '0') and (I_CA1 = '1'); end if; if (r_pcr(4) = '0') then -- cb1 control -- negative edge cb1_int <= (cb1_ip_reg = '1') and (cb1_in_mux = '0'); else -- positive edge cb1_int <= (cb1_ip_reg = '0') and (cb1_in_mux = '1'); end if; end process; p_ca2_cb2_int : process(r_pcr, ca2_ip_reg, I_CA2, cb2_ip_reg, I_CB2) begin ca2_int <= false; if (r_pcr(3) = '0') then -- ca2 input if (r_pcr(2) = '0') then -- ca2 edge -- negative edge ca2_int <= (ca2_ip_reg = '1') and (I_CA2 = '0'); else -- positive edge ca2_int <= (ca2_ip_reg = '0') and (I_CA2 = '1'); end if; end if; cb2_int <= false; if (r_pcr(7) = '0') then -- cb2 input if (r_pcr(6) = '0') then -- cb2 edge -- negative edge cb2_int <= (cb2_ip_reg = '1') and (I_CB2 = '0'); else -- positive edge cb2_int <= (cb2_ip_reg = '0') and (I_CB2 = '1'); end if; end if; end process; p_ca2_cb2 : process(RESET_L, CLK) begin if (RESET_L = '0') then O_CA2 <= '0'; O_CA2_OE_L <= '1'; O_CB2 <= '0'; O_CB2_OE_L <= '1'; ca_hs_sr <= '0'; ca_hs_pulse <= '0'; cb_hs_sr <= '0'; cb_hs_pulse <= '0'; elsif rising_edge(CLK) then if (ENA_4 = '1') then -- ca if (phase = "00") and ((w_ora_hs = '1') or (r_ira_hs = '1')) then ca_hs_sr <= '1'; elsif ca1_int then ca_hs_sr <= '0'; end if; if (phase = "00") then ca_hs_pulse <= w_ora_hs or r_ira_hs; end if; O_CA2_OE_L <= not r_pcr(3); -- ca2 output case r_pcr(3 downto 1) is when "000" => O_CA2 <= '0'; -- input when "001" => O_CA2 <= '0'; -- input when "010" => O_CA2 <= '0'; -- input when "011" => O_CA2 <= '0'; -- input when "100" => O_CA2 <= not (ca_hs_sr); -- handshake when "101" => O_CA2 <= not (ca_hs_pulse); -- pulse when "110" => O_CA2 <= '0'; -- low when "111" => O_CA2 <= '1'; -- high when others => null; end case; -- cb if (phase = "00") and (w_orb_hs = '1') then cb_hs_sr <= '1'; elsif cb1_int then cb_hs_sr <= '0'; end if; if (phase = "00") then cb_hs_pulse <= w_orb_hs; end if; O_CB2_OE_L <= not (r_pcr(7) or sr_drive_cb2); -- cb2 output or serial if (sr_drive_cb2 = '1') then -- serial output O_CB2 <= sr_out; else case r_pcr(7 downto 5) is when "000" => O_CB2 <= '0'; -- input when "001" => O_CB2 <= '0'; -- input when "010" => O_CB2 <= '0'; -- input when "011" => O_CB2 <= '0'; -- input when "100" => O_CB2 <= not (cb_hs_sr); -- handshake when "101" => O_CB2 <= not (cb_hs_pulse); -- pulse when "110" => O_CB2 <= '0'; -- low when "111" => O_CB2 <= '1'; -- high when others => null; end case; end if; end if; end if; end process; O_CB1 <= sr_cb1_out; O_CB1_OE_L <= sr_cb1_oe_l; p_ca_cb_irq : process(RESET_L, CLK) begin if (RESET_L = '0') then ca1_irq <= '0'; ca2_irq <= '0'; cb1_irq <= '0'; cb2_irq <= '0'; elsif rising_edge(CLK) then if (ENA_4 = '1') then -- not pretty if ca1_int then ca1_irq <= '1'; elsif (r_ira_hs = '1') or (w_ora_hs = '1') or (clear_irq(1) = '1') then ca1_irq <= '0'; end if; if ca2_int then ca2_irq <= '1'; else if (((r_ira_hs = '1') or (w_ora_hs = '1')) and (r_pcr(1) = '0')) or (clear_irq(0) = '1') then ca2_irq <= '0'; end if; end if; if cb1_int then cb1_irq <= '1'; elsif (r_irb_hs = '1') or (w_orb_hs = '1') or (clear_irq(4) = '1') then cb1_irq <= '0'; end if; if cb2_int then cb2_irq <= '1'; else if (((r_irb_hs = '1') or (w_orb_hs = '1')) and (r_pcr(5) = '0')) or (clear_irq(3) = '1') then cb2_irq <= '0'; end if; end if; end if; end if; end process; p_input_reg : process(RESET_L, CLK) begin if (RESET_L = '0') then ca1_ip_reg <= '0'; cb1_ip_reg <= '0'; ca2_ip_reg <= '0'; cb2_ip_reg <= '0'; r_ira <= x"00"; r_irb <= x"00"; elsif rising_edge(CLK) then if (ENA_4 = '1') then -- we have a fast clock, so we can have input registers ca1_ip_reg <= I_CA1; cb1_ip_reg <= cb1_in_mux; ca2_ip_reg <= I_CA2; cb2_ip_reg <= I_CB2; if (r_acr(0) = '0') then r_ira <= I_PA; else -- enable latching if ca1_int then r_ira <= I_PA; end if; end if; if (r_acr(1) = '0') then r_irb <= I_PB; else -- enable latching if cb1_int then r_irb <= I_PB; end if; end if; end if; end if; end process; p_buffers : process(r_ddra, r_ora, r_ddrb, r_acr, r_orb) begin -- data direction reg (ddr) 0 = input, 1 = output O_PA <= r_ora; O_PA_OE_L <= not r_ddra; if (r_acr(7) = '1') then -- not clear if r_ddrb(7) must be 1 as well O_PB_OE_L(7) <= '0'; -- an output if under t1 control else O_PB_OE_L(7) <= not (r_ddrb(7)); end if; O_PB_OE_L(6 downto 0) <= not r_ddrb(6 downto 0); O_PB(7 downto 0) <= r_orb(7 downto 0); end process; -- -- Timer 1 -- p_timer1_done : process variable done : boolean; begin wait until rising_edge(CLK); if (ENA_4 = '1') then done := (t1c = x"0000"); t1c_done <= done and (phase = "11"); if (phase = "11") then t1_reload_counter <= done and (r_acr(6) = '1'); end if; if t1_load_counter then -- done reset on load! t1c_done <= false; end if; end if; end process; p_timer1 : process begin wait until rising_edge(CLK); if (ENA_4 = '1') then if t1_load_counter or (t1_reload_counter and phase = "11") then t1c( 7 downto 0) <= r_t1l_l; t1c(15 downto 8) <= r_t1l_h; elsif (phase="11") then t1c <= t1c - "1"; end if; if t1_load_counter or t1_reload_counter then t1c_active <= true; elsif t1c_done then t1c_active <= false; end if; t1_toggle <= '0'; if t1c_active and t1c_done then t1_toggle <= '1'; t1_irq <= '1'; elsif t1_w_reset_int or t1_r_reset_int or (clear_irq(6) = '1') then t1_irq <= '0'; end if; if t1_load_counter then -- irq reset on load! t1_irq <= '0'; end if; end if; end process; -- -- Timer2 -- p_timer2_pb6_input : process begin wait until rising_edge(CLK); if (ENA_4 = '1') then if (phase = "01") then -- leading edge p2_h t2_pb6 <= I_PB(6); t2_pb6_t1 <= t2_pb6; end if; end if; end process; p_timer2_done : process variable done : boolean; begin wait until rising_edge(CLK); if (ENA_4 = '1') then done := (t2c = x"0000"); t2c_done <= done and (phase = "11"); if (phase = "11") then t2_reload_counter <= done; end if; if t2_load_counter then -- done reset on load! t2c_done <= false; end if; end if; end process; p_timer2 : process variable ena : boolean; begin wait until rising_edge(CLK); if (ENA_4 = '1') then if (r_acr(5) = '0') then ena := true; else ena := (t2_pb6_t1 = '1') and (t2_pb6 = '0'); -- falling edge end if; if t2_load_counter or (t2_reload_counter and phase = "11") then -- not sure if t2c_reload should be here. Does timer2 just continue to -- count down, or is it reloaded ? Reloaded makes more sense if using -- it to generate a clock for the shift register. t2c( 7 downto 0) <= r_t2l_l; t2c(15 downto 8) <= r_t2l_h; else if (phase="11") and ena then -- or count mode t2c <= t2c - "1"; end if; end if; t2_sr_ena <= (t2c(7 downto 0) = x"00") and (phase = "11"); if t2_load_counter then t2c_active <= true; elsif t2c_done then t2c_active <= false; end if; if t2c_active and t2c_done then t2_irq <= '1'; elsif t2_w_reset_int or t2_r_reset_int or (clear_irq(5) = '1') then t2_irq <= '0'; end if; if t2_load_counter then -- irq reset on load! t2_irq <= '0'; end if; end if; end process; -- -- Shift Register -- p_sr : process(RESET_L, CLK) variable dir_out : std_logic; variable ena : std_logic; variable cb1_op : std_logic; variable cb1_ip : std_logic; variable use_t2 : std_logic; variable free_run : std_logic; variable sr_count_ena : boolean; begin if (RESET_L = '0') then r_sr <= x"00"; sr_drive_cb2 <= '0'; sr_cb1_oe_l <= '1'; sr_cb1_out <= '0'; sr_strobe <= '1'; sr_cnt <= "0000"; sr_irq <= '0'; sr_out <= '1'; sr_off_delay <= '0'; elsif rising_edge(CLK) then if (ENA_4 = '1') then -- decode mode dir_out := r_acr(4); -- output on cb2 cb1_op := '0'; cb1_ip := '0'; use_t2 := '0'; free_run := '0'; -- DMB: SR still runs even in disabled mode (on rising edge of CB1). -- It just doesn't generate any interrupts. -- Ref BBC micro advanced user guide p409 case r_acr(4 downto 2) is -- DMB: in disabled mode, configure cb1 as an input when "000" => ena := '0'; cb1_ip := '1'; when "001" => ena := '1'; cb1_op := '1'; use_t2 := '1'; when "010" => ena := '1'; cb1_op := '1'; when "011" => ena := '1'; cb1_ip := '1'; when "100" => ena := '1'; use_t2 := '1'; free_run := '1'; when "101" => ena := '1'; cb1_op := '1'; use_t2 := '1'; when "110" => ena := '1'; when "111" => ena := '1'; cb1_ip := '1'; when others => null; end case; -- clock select -- DMB: in disabled mode, strobe from cb1 if (cb1_ip = '1') then sr_strobe <= I_CB1; else if (sr_cnt(3) = '0') and (free_run = '0') then sr_strobe <= '1'; else if ((use_t2 = '1') and t2_sr_ena) or ((use_t2 = '0') and (phase = "00")) then sr_strobe <= not sr_strobe; end if; end if; end if; -- latch on rising edge, shift on falling edge if sr_write_ena then r_sr <= load_data; else -- DMB: allow shifting in all modes if (dir_out = '0') then -- input if (sr_cnt(3) = '1') or (cb1_ip = '1') then if sr_strobe_rising then r_sr(0) <= I_CB2; elsif sr_strobe_falling then r_sr(7 downto 1) <= r_sr(6 downto 0); end if; end if; sr_out <= '1'; else -- output if (sr_cnt(3) = '1') or (sr_off_delay = '1') or (cb1_ip = '1') or (free_run = '1') then if sr_strobe_falling then r_sr(7 downto 1) <= r_sr(6 downto 0); r_sr(0) <= r_sr(7); sr_out <= r_sr(7); end if; else sr_out <= '1'; end if; end if; end if; sr_count_ena := sr_strobe_rising; -- DMB: reseting sr_count when not enabled cause the sr to -- start running immediately it was enabled, which is incorrect -- and broke the latest SmartSPI ROM on the BBC Micro if ena = '1' and (sr_write_ena or sr_read_ena) then -- some documentation says sr bit in IFR must be set as well ? sr_cnt <= "1000"; elsif sr_count_ena and (sr_cnt(3) = '1') then sr_cnt <= sr_cnt + "1"; end if; if (phase = "00") then sr_off_delay <= sr_cnt(3); -- give some hold time when shifting out end if; if sr_count_ena and (sr_cnt = "1111") and (ena = '1') and (free_run = '0') then sr_irq <= '1'; elsif sr_write_ena or sr_read_ena or (clear_irq(2) = '1') then sr_irq <= '0'; end if; -- assign ops sr_drive_cb2 <= dir_out; sr_cb1_oe_l <= not cb1_op; sr_cb1_out <= sr_strobe; end if; end if; end process; p_sr_strobe_rise_fall : process begin wait until rising_edge(CLK); if (ENA_4 = '1') then sr_strobe_t1 <= sr_strobe; sr_strobe_rising <= (sr_strobe_t1 = '0') and (sr_strobe = '1'); sr_strobe_falling <= (sr_strobe_t1 = '1') and (sr_strobe = '0'); end if; end process; -- -- Interrupts -- p_ier : process(RESET_L, CLK) begin if (RESET_L = '0') then r_ier <= "0000000"; elsif rising_edge(CLK) then if (ENA_4 = '1') then if ier_write_ena then if (load_data(7) = '1') then -- set r_ier <= r_ier or load_data(6 downto 0); else -- clear r_ier <= r_ier and not load_data(6 downto 0); end if; end if; end if; end if; end process; p_ifr : process(t1_irq, t2_irq, final_irq, ca1_irq, ca2_irq, sr_irq, cb1_irq, cb2_irq) begin r_ifr(7) <= final_irq; r_ifr(6) <= t1_irq; r_ifr(5) <= t2_irq; r_ifr(4) <= cb1_irq; r_ifr(3) <= cb2_irq; r_ifr(2) <= sr_irq; r_ifr(1) <= ca1_irq; r_ifr(0) <= ca2_irq; O_IRQ_L <= not final_irq; end process; p_irq : process(RESET_L, CLK) begin if (RESET_L = '0') then final_irq <= '0'; elsif rising_edge(CLK) then if (ENA_4 = '1') then if ((r_ifr(6 downto 0) and r_ier(6 downto 0)) = "0000000") then final_irq <= '0'; -- no interrupts else final_irq <= '1'; end if; end if; end if; end process; p_clear_irq : process(ifr_write_ena, load_data) begin clear_irq <= x"00"; if ifr_write_ena then clear_irq <= load_data; end if; end process; end architecture RTL;
------------------------------------------------------------------------------- -- Title : test_order -- Project : ------------------------------------------------------------------------------- -- File : test_order.vhd -- Author : <kristoffer.nordstrom@HELVNB0100> -- Company : -- Created : 2015-04-27 -- Last update: 2015-05-20 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2015 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2015-04-27 1.0 kn Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.test_order_pkg.all; ------------------------------------------------------------------------------- entity test_order is port ( Clk : in std_logic; Clr : in std_logic; Order_A : in std_logic_vector(3 downto 0); Order_B : in std_logic_vector(3 downto 0); Order_AB : out std_logic_vector(4 downto 0) ); end entity test_order; ------------------------------------------------------------------------------- architecture str of test_order is ----------------------------------------------------------------------------- -- Internal signal declarations ----------------------------------------------------------------------------- signal AB : unsigned(Order_AB'range); begin -- architecture str ----------------------------------------------------------------------------- -- Output assignments ----------------------------------------------------------------------------- Order_AB <= std_logic_vector(AB); ----------------------------------------------------------------------------- -- Component instantiations ----------------------------------------------------------------------------- p_addAandB: process (Clk) is begin -- process p_addAandB if Clk'event and Clk = '1' then -- rising clock edge if Clr = '1' then AB <= to_unsigned(0, AB'length); else AB <= resize(unsigned(Order_A), AB'length) + resize(unsigned(Order_B), AB'length); end if; end if; end process p_addAandB; assert THE_TRUTH = 42 report "No answer to the question." severity error; end architecture str; -------------------------------------------------------------------------------
-------------------------------------------------------------------------------- -- -- FIFO Generator Core - core top file for implementation -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_1_exdes.vhd -- -- Description: -- This is the FIFO core wrapper with BUFG instances for clock connections. -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; -------------------------------------------------------------------------------- -- Entity Declaration -------------------------------------------------------------------------------- entity system_axi_dma_0_wrapper_fifo_generator_v9_3_1_exdes is PORT ( CLK : IN std_logic; DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0); WR_ACK : OUT std_logic; VALID : OUT std_logic; ALMOST_EMPTY : OUT std_logic; SRST : IN std_logic; WR_EN : IN std_logic; RD_EN : IN std_logic; DIN : IN std_logic_vector(39-1 DOWNTO 0); DOUT : OUT std_logic_vector(39-1 DOWNTO 0); FULL : OUT std_logic; EMPTY : OUT std_logic); end system_axi_dma_0_wrapper_fifo_generator_v9_3_1_exdes; architecture xilinx of system_axi_dma_0_wrapper_fifo_generator_v9_3_1_exdes is signal clk_i : std_logic; component system_axi_dma_0_wrapper_fifo_generator_v9_3_1 is PORT ( CLK : IN std_logic; DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0); WR_ACK : OUT std_logic; VALID : OUT std_logic; ALMOST_EMPTY : OUT std_logic; SRST : IN std_logic; WR_EN : IN std_logic; RD_EN : IN std_logic; DIN : IN std_logic_vector(39-1 DOWNTO 0); DOUT : OUT std_logic_vector(39-1 DOWNTO 0); FULL : OUT std_logic; EMPTY : OUT std_logic); end component; begin clk_buf: bufg PORT map( i => CLK, o => clk_i ); exdes_inst : system_axi_dma_0_wrapper_fifo_generator_v9_3_1 PORT MAP ( CLK => clk_i, DATA_COUNT => data_count, WR_ACK => wr_ack, VALID => valid, ALMOST_EMPTY => almost_empty, SRST => srst, WR_EN => wr_en, RD_EN => rd_en, DIN => din, DOUT => dout, FULL => full, EMPTY => empty); end xilinx;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block SaIWyjva/co9bRUSmYAfIKCgxws6MT8pkOO2swHirc0i27P//C3pVBhhDY8IBidnDbsGJrlXitZs FIvI0trB/Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Q+zCnGWE4oZnejyJVZdj9qCiFfpjvlN7gx8X0h+Q7Cp4afTQVc1xpgGbJC8fOc0qxSYo5wvBUW+i Zg1eCjLz28P/80PjXFU1eLuHWz0lGzaSlpmtfGPrc4+1t6rP85mTal3hLPhuiyNpmgsU8wS+4Oj7 X48Fl5q3jElUyRdqElM= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block SaIWyjva/co9bRUSmYAfIKCgxws6MT8pkOO2swHirc0i27P//C3pVBhhDY8IBidnDbsGJrlXitZs FIvI0trB/Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Q+zCnGWE4oZnejyJVZdj9qCiFfpjvlN7gx8X0h+Q7Cp4afTQVc1xpgGbJC8fOc0qxSYo5wvBUW+i Zg1eCjLz28P/80PjXFU1eLuHWz0lGzaSlpmtfGPrc4+1t6rP85mTal3hLPhuiyNpmgsU8wS+4Oj7 X48Fl5q3jElUyRdqElM= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_decoder_GNBT6YIKS3 is generic ( decode : string := "011"; pipeline : natural := 1; width : natural := 3); port( aclr : in std_logic; clock : in std_logic; data : in std_logic_vector((width)-1 downto 0); dec : out std_logic; ena : in std_logic; sclr : in std_logic); end entity; architecture rtl of alt_dspbuilder_decoder_GNBT6YIKS3 is Begin -- DSP Builder Block - Simulink Block "Decoder" Decoderi : alt_dspbuilder_sdecoderaltr Generic map ( width => 3, decode => "011", pipeline => 1) port map ( aclr => aclr, user_aclr => '0', sclr => sclr, clock => clock, data => data, dec => dec); end architecture;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_decoder_GNBT6YIKS3 is generic ( decode : string := "011"; pipeline : natural := 1; width : natural := 3); port( aclr : in std_logic; clock : in std_logic; data : in std_logic_vector((width)-1 downto 0); dec : out std_logic; ena : in std_logic; sclr : in std_logic); end entity; architecture rtl of alt_dspbuilder_decoder_GNBT6YIKS3 is Begin -- DSP Builder Block - Simulink Block "Decoder" Decoderi : alt_dspbuilder_sdecoderaltr Generic map ( width => 3, decode => "011", pipeline => 1) port map ( aclr => aclr, user_aclr => '0', sclr => sclr, clock => clock, data => data, dec => dec); end architecture;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_decoder_GNBT6YIKS3 is generic ( decode : string := "011"; pipeline : natural := 1; width : natural := 3); port( aclr : in std_logic; clock : in std_logic; data : in std_logic_vector((width)-1 downto 0); dec : out std_logic; ena : in std_logic; sclr : in std_logic); end entity; architecture rtl of alt_dspbuilder_decoder_GNBT6YIKS3 is Begin -- DSP Builder Block - Simulink Block "Decoder" Decoderi : alt_dspbuilder_sdecoderaltr Generic map ( width => 3, decode => "011", pipeline => 1) port map ( aclr => aclr, user_aclr => '0', sclr => sclr, clock => clock, data => data, dec => dec); end architecture;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_decoder_GNBT6YIKS3 is generic ( decode : string := "011"; pipeline : natural := 1; width : natural := 3); port( aclr : in std_logic; clock : in std_logic; data : in std_logic_vector((width)-1 downto 0); dec : out std_logic; ena : in std_logic; sclr : in std_logic); end entity; architecture rtl of alt_dspbuilder_decoder_GNBT6YIKS3 is Begin -- DSP Builder Block - Simulink Block "Decoder" Decoderi : alt_dspbuilder_sdecoderaltr Generic map ( width => 3, decode => "011", pipeline => 1) port map ( aclr => aclr, user_aclr => '0', sclr => sclr, clock => clock, data => data, dec => dec); end architecture;
-------------------------------------------------------------------------------- -- -- Distributed Memory Generator v6.3 Core - Top-level core wrapper -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -------------------------------------------------------------------------------- -- -- -- Description: -- This is the actual DMG core wrapper. -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; -------------------------------------------------------------------------------- -- Entity Declaration -------------------------------------------------------------------------------- entity ROM_GAUSS_COE_exdes is PORT ( A : IN STD_LOGIC_VECTOR(4-1-(40boolean'pos(4>4)) downto 0) := (OTHERS => '0'); D : IN STD_LOGIC_VECTOR(135-1 downto 0) := (OTHERS => '0'); DPRA : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS => '0'); SPRA : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS => '0'); CLK : IN STD_LOGIC := '0'; WE : IN STD_LOGIC := '0'; I_CE : IN STD_LOGIC := '1'; QSPO_CE : IN STD_LOGIC := '1'; QDPO_CE : IN STD_LOGIC := '1'; QDPO_CLK : IN STD_LOGIC := '0'; QSPO_RST : IN STD_LOGIC := '0'; QDPO_RST : IN STD_LOGIC := '0'; QSPO_SRST : IN STD_LOGIC := '0'; QDPO_SRST : IN STD_LOGIC := '0'; SPO : OUT STD_LOGIC_VECTOR(135-1 downto 0); DPO : OUT STD_LOGIC_VECTOR(135-1 downto 0); QSPO : OUT STD_LOGIC_VECTOR(135-1 downto 0); QDPO : OUT STD_LOGIC_VECTOR(135-1 downto 0) ); end ROM_GAUSS_COE_exdes; architecture xilinx of ROM_GAUSS_COE_exdes is SIGNAL CLK_i : std_logic; component ROM_GAUSS_COE is PORT ( CLK : IN STD_LOGIC; WE : IN STD_LOGIC; SPO : OUT STD_LOGIC_VECTOR(135-1 downto 0); A : IN STD_LOGIC_VECTOR(4-1-(40boolean'pos(4>4)) downto 0) := (OTHERS => '0'); D : IN STD_LOGIC_VECTOR(135-1 downto 0) := (OTHERS => '0') ); end component; begin dmg0 : ROM_GAUSS_COE port map ( CLK => CLK_i, WE => WE, SPO => SPO, A => A, D => D ); clk_buf: bufg PORT map( i => CLK, o => CLK_i ); end xilinx;
--Part of Mano Basic Computer --Behzad Mokhtari; [email protected] --Sahand University of Technology; sut.ac.ir --Licensed under GPLv3 --ALU Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all; Library manoBasic; use manoBasic.defines.all, manoBasic.devices.all; entity tb_ALU is end tb_ALU; architecture tb of tb_ALU is signal cmd: instALU; signal Ei: std_logic := '0'; signal Eo: std_logic; signal IP: std_logic_vector(15 downto 0); signal AC: std_logic_vector(15 downto 0); signal DR: std_logic_vector(15 downto 0); signal Q,qq: std_logic_vector(15 downto 0); signal Check: std_logic := '1'; begin A0: ALU generic map(width =>16) port map( cmd => cmd, Ei => Ei, Eo => Eo, IP => IP, AC => AC, DR => DR, Q => Q ); test: process begin IP <= "0000111100001111"; cmd <= aluINPR; wait for 1 ns; if(IP = Q) then Check <= '1'; else Check <= '0'; end if; AC <= IP; DR <= not IP; cmd <= aluAND; wait for 1 ns; if(Q = (AC and DR)) then Check <= '1'; else Check <= '0'; end if; wait for 1 ns; cmd <= aluADD; wait for 1 ns; if(to_integer(unsigned(Q)) = (to_integer(unsigned(AC)) + to_integer(unsigned(DR)))) then Check <= '1'; else Check <= '0'; end if; wait for 1 ns; cmd <= aluDR; wait for 1 ns; if(Q = DR) then Check <= '1'; else Check <= '0'; end if; wait for 1 ns; cmd <= aluCOM; wait for 1 ns; if(Q = not AC) then Check <= '1'; else Check <= '0'; end if; wait for 1 ns; cmd <= aluSHR; qq <= '0' & AC(15 downto 1); wait for 1 ns; if(Q = qq) then Check <= '1'; else Check <= '0'; end if; wait for 1 ns; cmd <= aluSHL; qq <= AC(14 downto 0) & '0'; wait for 1 ns; if(Q = qq) then Check <= '1'; else Check <= '0'; end if; wait; end process test; end architecture tb;
library verilog; use verilog.vl_types.all; entity sum is port( a : in vl_logic_vector(9 downto 0); b : in vl_logic_vector(9 downto 0); y : out vl_logic_vector(9 downto 0) ); end sum;
-- $Id: tb_w11a_n2.vhd 314 2010-07-09 17:38:41Z mueller $ -- -- Copyright 2010- by Walter F.J. Mueller <[email protected]> -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free -- Software Foundation, either version 2, or at your option any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY -- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for complete details. -- ------------------------------------------------------------------------------ -- Module Name: tb_w11a_n2 -- Description: Configuration for tb_w11a_n2 for tb_nexys2_fusp -- -- Dependencies: sys_w11a_n2 -- -- To test: sys_w11a_n2 -- -- Verified (with (#1) ../../tb/tb_rritba_pdp11core_stim.dat -- (#2) ../../tb/tb_pdp11_core_stim.dat): -- Date Rev Code ghdl ise Target Comment -- 2010-05-28 295 - -.-- - - -:-- -- -- Revision History: -- Date Rev Version Comment -- 2010-05-26 295 1.0 Initial version (cloned from _s3) ------------------------------------------------------------------------------ configuration tb_w11a_n2 of tb_nexys2_fusp is for sim for all : nexys2_fusp_aif use entity work.sys_w11a_n2; end for; end for; end tb_w11a_n2;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2013, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: grethc -- File: grethc.vhd -- Author: Marko Isomaki -- Description: Ethernet Media Access Controller with Ethernet Debug -- Communication Link ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library grlib; use grlib.stdlib.all; library eth; use eth.grethpkg.all; entity grethc is generic( ifg_gap : integer := 24; attempt_limit : integer := 16; backoff_limit : integer := 10; mdcscaler : integer range 0 to 255 := 25; enable_mdio : integer range 0 to 1 := 0; fifosize : integer range 4 to 512 := 8; nsync : integer range 1 to 2 := 2; edcl : integer range 0 to 3 := 0; edclbufsz : integer range 1 to 64 := 1; macaddrh : integer := 16#00005E#; macaddrl : integer := 16#000000#; ipaddrh : integer := 16#c0a8#; ipaddrl : integer := 16#0035#; phyrstadr : integer range 0 to 32 := 0; rmii : integer range 0 to 1 := 0; oepol : integer range 0 to 1 := 0; scanen : integer range 0 to 1 := 0; mdint_pol : integer range 0 to 1 := 0; enable_mdint : integer range 0 to 1 := 0; multicast : integer range 0 to 1 := 0; edclsepahbg : integer range 0 to 1 := 0; ramdebug : integer range 0 to 2 := 0; mdiohold : integer := 1; maxsize : integer := 1500); port( rst : in std_ulogic; clk : in std_ulogic; --ahb mst in hgrant : in std_ulogic; hready : in std_ulogic; hresp : in std_logic_vector(1 downto 0); hrdata : in std_logic_vector(31 downto 0); --ahb mst out hbusreq : out std_ulogic; hlock : out std_ulogic; htrans : out std_logic_vector(1 downto 0); haddr : out std_logic_vector(31 downto 0); hwrite : out std_ulogic; hsize : out std_logic_vector(2 downto 0); hburst : out std_logic_vector(2 downto 0); hprot : out std_logic_vector(3 downto 0); hwdata : out std_logic_vector(31 downto 0); --edcl ahb mst in ehgrant : in std_ulogic; ehready : in std_ulogic; ehresp : in std_logic_vector(1 downto 0); ehrdata : in std_logic_vector(31 downto 0); --edcl ahb mst out ehbusreq : out std_ulogic; ehlock : out std_ulogic; ehtrans : out std_logic_vector(1 downto 0); ehaddr : out std_logic_vector(31 downto 0); ehwrite : out std_ulogic; ehsize : out std_logic_vector(2 downto 0); ehburst : out std_logic_vector(2 downto 0); ehprot : out std_logic_vector(3 downto 0); ehwdata : out std_logic_vector(31 downto 0); --apb slv in psel : in std_ulogic; penable : in std_ulogic; paddr : in std_logic_vector(31 downto 0); pwrite : in std_ulogic; pwdata : in std_logic_vector(31 downto 0); --apb slv out prdata : out std_logic_vector(31 downto 0); --irq irq : out std_logic; --rx ahb fifo rxrenable : out std_ulogic; rxraddress : out std_logic_vector(10 downto 0); rxwrite : out std_ulogic; rxwdata : out std_logic_vector(31 downto 0); rxwaddress : out std_logic_vector(10 downto 0); rxrdata : in std_logic_vector(31 downto 0); --tx ahb fifo txrenable : out std_ulogic; txraddress : out std_logic_vector(10 downto 0); txwrite : out std_ulogic; txwdata : out std_logic_vector(31 downto 0); txwaddress : out std_logic_vector(10 downto 0); txrdata : in std_logic_vector(31 downto 0); --edcl buf erenable : out std_ulogic; eraddress : out std_logic_vector(15 downto 0); ewritem : out std_ulogic; ewritel : out std_ulogic; ewaddressm : out std_logic_vector(15 downto 0); ewaddressl : out std_logic_vector(15 downto 0); ewdata : out std_logic_vector(31 downto 0); erdata : in std_logic_vector(31 downto 0); --ethernet input signals rmii_clk : in std_ulogic; tx_clk : in std_ulogic; rx_clk : in std_ulogic; rxd : in std_logic_vector(3 downto 0); rx_dv : in std_ulogic; rx_er : in std_ulogic; rx_col : in std_ulogic; rx_crs : in std_ulogic; mdio_i : in std_ulogic; phyrstaddr : in std_logic_vector(4 downto 0); mdint : in std_ulogic; --ethernet output signals reset : out std_ulogic; txd : out std_logic_vector(3 downto 0); tx_en : out std_ulogic; tx_er : out std_ulogic; mdc : out std_ulogic; mdio_o : out std_ulogic; mdio_oe : out std_ulogic; --scantest testrst : in std_ulogic; testen : in std_ulogic; testoen : in std_ulogic; edcladdr : in std_logic_vector(3 downto 0) := "0000"; edclsepahb : in std_ulogic; edcldisable : in std_ulogic; speed : out std_ulogic ); attribute sync_set_reset of rst : signal is "true"; end entity; architecture rtl of grethc is procedure sel_op_mode( capbil : in std_logic_vector(4 downto 0); speed : out std_ulogic; duplex : out std_ulogic) is variable vspeed : std_ulogic; variable vduplex : std_ulogic; begin vspeed := '0'; vduplex := '0'; vspeed := orv(capbil(4 downto 2)); vduplex := (vspeed and capbil(3)) or ((not vspeed) and capbil(1)); speed := vspeed; duplex := vduplex; end procedure; --host constants constant fabits : integer := log2(fifosize); constant burstlength : integer := setburstlength(fifosize); constant burstbits : integer := log2(burstlength); constant ctrlopcode : std_logic_vector(15 downto 0) := X"8808"; constant broadcast : std_logic_vector(47 downto 0) := X"FFFFFFFFFFFF"; -- constant maxsizetx : integer := 1514; constant index : integer := log2(edclbufsz); constant receiveOK : std_logic_vector(3 downto 0) := "0000"; constant frameCheckError : std_logic_vector(3 downto 0) := "0100"; constant alignmentError : std_logic_vector(3 downto 0) := "0001"; constant frameTooLong : std_logic_vector(3 downto 0) := "0010"; constant overrun : std_logic_vector(3 downto 0) := "1000"; constant minpload : std_logic_vector(10 downto 0) := conv_std_logic_vector(60, 11); --mdio constants constant divisor : std_logic_vector(7 downto 0) := conv_std_logic_vector(mdcscaler, 8); --receiver constants constant maxsizerx : unsigned(15 downto 0) := to_unsigned(maxsize + 18 - 4, 16); --tranceiver constants constant maxsizetx : unsigned(15 downto 0) := to_unsigned(maxsize + 18 - 4, 16); --edcl constants type szvct is array (0 to 6) of integer; constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256); constant blbits : szvct := (6, 7, 7, 8, 8, 8, 8); constant winsz : szvct := (4, 4, 8, 8, 16, 32, 64); constant macaddrt : std_logic_vector(47 downto 0) := conv_std_logic_vector(macaddrh, 24) & conv_std_logic_vector(macaddrl, 24); constant bpbits : integer := blbits(log2(edclbufsz)); constant wsz : integer := winsz(log2(edclbufsz)); constant bselbits : integer := log2(wsz); constant eabits: integer := log2(edclbufsz) + 8; constant ebufmax : std_logic_vector(bpbits-1 downto 0) := (others => '1'); constant bufsize : std_logic_vector(2 downto 0) := conv_std_logic_vector(log2(edclbufsz), 3); constant ebufsize : integer := ebuf(log2(edclbufsz)); constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize); constant txfabits : integer := log2(txfifosize); constant txfifosizev : std_logic_vector(txfabits downto 0) := conv_std_logic_vector(txfifosize, txfabits+1); constant rxburstlen : std_logic_vector(fabits downto 0) := conv_std_logic_vector(burstlength, fabits+1); constant txburstlen : std_logic_vector(txfabits downto 0) := conv_std_logic_vector(burstlength, txfabits+1); type edclrstate_type is (idle, wrda, wrdsa, wrsa, wrtype, ip, ipdata, oplength, arp, iplength, ipcrc, arpop, udp, spill); type duplexstate_type is (start, waitop, nextop, selmode, done); --host types type txd_state_type is (idle, read_desc, check_desc, req, fill_fifo, check_result, write_result, readhdr, start, wrbus1, etdone, getlen, ahberror, fill_fifo2, wrbus2); type rxd_state_type is (idle, read_desc, check_desc, read_req, read_fifo, discard, write_status, write_status2); --mdio types type mdio_state_type is (idle, preamble, startst, op, op2, phyadr, regadr, ta, ta2, ta3, data, dataend); type ctrl_reg_type is record txen : std_ulogic; rxen : std_ulogic; tx_irqen : std_ulogic; rx_irqen : std_ulogic; full_duplex : std_ulogic; prom : std_ulogic; reset : std_ulogic; speed : std_ulogic; pstatirqen : std_ulogic; mcasten : std_ulogic; ramdebugen : std_ulogic; edcldis : std_ulogic; end record; type status_reg_type is record tx_int : std_ulogic; rx_int : std_ulogic; rx_err : std_ulogic; tx_err : std_ulogic; txahberr : std_ulogic; rxahberr : std_ulogic; toosmall : std_ulogic; invaddr : std_ulogic; phystat : std_ulogic; end record; type mdio_ctrl_reg_type is record phyadr : std_logic_vector(4 downto 0); regadr : std_logic_vector(4 downto 0); write : std_ulogic; read : std_ulogic; data : std_logic_vector(15 downto 0); busy : std_ulogic; linkfail : std_ulogic; end record; subtype mac_addr_reg_type is std_logic_vector(47 downto 0); type fifo_access_in_type is record renable : std_ulogic; raddress : std_logic_vector(fabits-1 downto 0); write : std_ulogic; waddress : std_logic_vector(fabits-1 downto 0); datain : std_logic_vector(31 downto 0); end record; type fifo_access_out_type is record data : std_logic_vector(31 downto 0); end record; type tx_fifo_access_in_type is record renable : std_ulogic; raddress : std_logic_vector(txfabits-1 downto 0); write : std_ulogic; waddress : std_logic_vector(txfabits-1 downto 0); datain : std_logic_vector(31 downto 0); end record; type tx_fifo_access_out_type is record data : std_logic_vector(31 downto 0); end record; type edcl_ram_in_type is record renable : std_ulogic; raddress : std_logic_vector(eabits-1 downto 0); writem : std_ulogic; writel : std_ulogic; waddressm : std_logic_vector(eabits-1 downto 0); waddressl : std_logic_vector(eabits-1 downto 0); datain : std_logic_vector(31 downto 0); end record; type edcl_ram_out_type is record data : std_logic_vector(31 downto 0); end record; type reg_type is record --user registers ctrl : ctrl_reg_type; status : status_reg_type; mdio_ctrl : mdio_ctrl_reg_type; mac_addr : mac_addr_reg_type; hash : std_logic_vector(63 downto 0); txdesc : std_logic_vector(31 downto 10); rxdesc : std_logic_vector(31 downto 10); edclip : std_logic_vector(31 downto 0); --master tx interface txdsel : std_logic_vector(9 downto 3); tmsto : eth_tx_ahb_in_type; tmsto2 : eth_tx_ahb_in_type; txdstate : txd_state_type; txwrap : std_ulogic; txden : std_ulogic; txirq : std_ulogic; txaddr : std_logic_vector(31 downto 2); txlength : std_logic_vector(10 downto 0); txburstcnt : std_logic_vector(burstbits downto 0); tfwpnt : std_logic_vector(txfabits-1 downto 0); tfrpnt : std_logic_vector(txfabits-1 downto 0); tfcnt : std_logic_vector(txfabits downto 0); txcnt : std_logic_vector(10 downto 0); txstart : std_ulogic; txirqgen : std_ulogic; txstatus : std_logic_vector(1 downto 0); txvalid : std_ulogic; txdata : std_logic_vector(31 downto 0); writeok : std_ulogic; txread : std_logic_vector(nsync-1 downto 0); txrestart : std_logic_vector(nsync downto 0); txdone : std_logic_vector(nsync downto 0); txstart_sync : std_ulogic; txreadack : std_ulogic; txdataav : std_ulogic; txburstav : std_ulogic; --master rx interface rxrenable : std_ulogic; rxdsel : std_logic_vector(9 downto 3); rmsto : eth_rx_ahb_in_type; rxdstate : rxd_state_type; rxstatus : std_logic_vector(4 downto 0); rxaddr : std_logic_vector(31 downto 2); rxlength : std_logic_vector(10 downto 0); rxbytecount : std_logic_vector(10 downto 0); rxwrap : std_ulogic; rxirq : std_ulogic; rfwpnt : std_logic_vector(fabits-1 downto 0); rfrpnt : std_logic_vector(fabits-1 downto 0); rfcnt : std_logic_vector(fabits downto 0); rxcnt : std_logic_vector(10 downto 0); rxdoneold : std_ulogic; rxdoneack : std_ulogic; rxdone : std_logic_vector(nsync-1 downto 0); rxstart : std_logic_vector(nsync downto 0); rxwrite : std_logic_vector(nsync-1 downto 0); rxwriteack : std_ulogic; rxburstcnt : std_logic_vector(burstbits downto 0); addrok : std_ulogic; addrdone : std_ulogic; ctrlpkt : std_ulogic; check : std_ulogic; checkdata : std_logic_vector(31 downto 0); usesizefield : std_ulogic; rxden : std_ulogic; gotframe : std_ulogic; bcast : std_ulogic; msbgood : std_ulogic; rxburstav : std_ulogic; hashlookup : std_ulogic; mcast : std_ulogic; mcastacc : std_ulogic; --mdio mdccnt : std_logic_vector(7 downto 0); mdioclk : std_ulogic; mdioclkold : std_logic_vector(mdiohold-1 downto 0); mdio_state : mdio_state_type; mdioo : std_ulogic; mdioi : std_ulogic; mdioen : std_ulogic; cnt : std_logic_vector(4 downto 0); duplexstate : duplexstate_type; disableduplex : std_ulogic; init_busy : std_ulogic; ext : std_ulogic; extcap : std_ulogic; regaddr : std_logic_vector(4 downto 0); phywr : std_ulogic; rstphy : std_ulogic; capbil : std_logic_vector(4 downto 0); rstaneg : std_ulogic; mdint_sync : std_logic_vector(2 downto 0); --edcl erenable : std_ulogic; edclrstate : edclrstate_type; edclactive : std_ulogic; nak : std_ulogic; ewr : std_ulogic; write : std_logic_vector(wsz-1 downto 0); seq : std_logic_vector(13 downto 0); abufs : std_logic_vector(bselbits downto 0); tpnt : std_logic_vector(bselbits-1 downto 0); rpnt : std_logic_vector(bselbits-1 downto 0); tcnt : std_logic_vector(bpbits-1 downto 0); rcntm : std_logic_vector(bpbits-1 downto 0); rcntl : std_logic_vector(bpbits-1 downto 0); ipcrc : std_logic_vector(17 downto 0); applength : std_logic_vector(15 downto 0); oplen : std_logic_vector(9 downto 0); udpsrc : std_logic_vector(15 downto 0); ecnt : std_logic_vector(3 downto 0); tarp : std_ulogic; tnak : std_ulogic; tedcl : std_ulogic; edclbcast : std_ulogic; etxidle : std_ulogic; erxidle : std_ulogic; emacaddr : std_logic_vector(47 downto 0); edclsepahb : std_ulogic; end record; --host signals signal arst : std_ulogic; signal irst : std_ulogic; signal vcc : std_ulogic; signal tmsto : eth_tx_ahb_in_type; signal tmsti : eth_tx_ahb_out_type; signal tmsto2 : eth_tx_ahb_in_type; signal tmsti2 : eth_tx_ahb_out_type; signal rmsto : eth_rx_ahb_in_type; signal rmsti : eth_rx_ahb_out_type; signal ahbmi : ahbc_mst_in_type; signal ahbmo : ahbc_mst_out_type; signal ahbmi2 : ahbc_mst_in_type; signal ahbmo2 : ahbc_mst_out_type; signal txi : host_tx_type; signal txo : tx_host_type; signal rxi : host_rx_type; signal rxo : rx_host_type; signal r, rin : reg_type; attribute sync_set_reset of irst : signal is "true"; attribute async_set_reset of arst : signal is "true"; begin --reset generators for transmitter and receiver vcc <= '1'; arst <= testrst when (scanen = 1) and (testen = '1') else rst and not r.ctrl.reset; irst <= rst and not r.ctrl.reset; comb : process(rst, irst, r, rmsti, tmsti, txo, rxo, psel, paddr, penable, erdata, pwrite, pwdata, rxrdata, txrdata, mdio_i, phyrstaddr, testen, testrst, edcladdr, mdint, tmsti2, edcldisable, edclsepahb) is variable v : reg_type; variable vpirq : std_ulogic; variable vprdata : std_logic_vector(31 downto 0); variable txvalid : std_ulogic; variable vtxfi : tx_fifo_access_in_type; variable vrxfi : fifo_access_in_type; variable lengthav : std_ulogic; variable txdone : std_ulogic; variable txread : std_ulogic; variable txrestart : std_ulogic; variable rxstart : std_ulogic; variable rxdone : std_ulogic; variable vrxwrite : std_ulogic; variable ovrunstop : std_ulogic; variable edcldbgread : std_ulogic; --mdio variable mdioindex : integer range 0 to 31; variable mclk : std_ulogic; --rising mdio clk edge variable nmclk : std_ulogic; --falling mdio clk edge variable mclkvec : std_logic_vector(mdiohold downto 0); --edcl variable veri : edcl_ram_in_type; variable swap : std_ulogic; variable setmz : std_ulogic; variable ipcrctmp : std_logic_vector(15 downto 0); variable ipcrctmp2 : std_logic_vector(17 downto 0); variable vrxenable : std_ulogic; variable crctmp : std_ulogic; variable vecnt : integer; begin v := r; vprdata := (others => '0'); vpirq := '0'; v.check := '0'; lengthav := r.rxdoneold;-- or r.usesizefield; ovrunstop := '0'; vrxfi.raddress := v.rfrpnt; if edcl /= 0 then veri.renable := r.erenable; veri.datain := rxo.dataout; veri.writem := '0'; veri.writel := '0'; veri.waddressm := r.rpnt & r.rcntm; veri.waddressl := r.rpnt & r.rcntl; end if; vtxfi.renable := '0'; vtxfi.datain := tmsti.data; vtxfi.raddress := r.tfrpnt; vtxfi.write := '0'; vtxfi.waddress := r.tfwpnt; vrxfi.datain := rxo.dataout; vrxfi.write := '0'; vrxfi.waddress := r.rfwpnt; vrxfi.renable := r.rxrenable; vrxenable := r.ctrl.rxen; --synchronization v.txdone(0) := txo.done; v.txread(0) := txo.read; v.txrestart(0) := txo.restart; v.rxstart(0) := rxo.start; v.rxdone(0) := rxo.done; v.rxwrite(0) := rxo.write; if nsync = 2 then v.txdone(1) := r.txdone(0); v.txread(1) := r.txread(0); v.txrestart(1) := r.txrestart(0); v.rxstart(1) := r.rxstart(0); v.rxdone(1) := r.rxdone(0); v.rxwrite(1) := r.rxwrite(0); end if; if enable_mdint = 1 then v.mdint_sync(0) := mdint; v.mdint_sync(1) := r.mdint_sync(0); v.mdint_sync(2) := r.mdint_sync(1); end if; txdone := r.txdone(nsync) xor r.txdone(nsync-1); txread := r.txreadack xor r.txread(nsync-1); txrestart := r.txrestart(nsync) xor r.txrestart(nsync-1); rxstart := r.rxstart(nsync) xor r.rxstart(nsync-1); rxdone := r.rxdoneack xor r.rxdone(nsync-1); vrxwrite := r.rxwriteack xor r.rxwrite(nsync-1); if txdone = '1' then v.txstatus := txo.status; end if; ------------------------------------------------------------------------------- -- HOST INTERFACE ------------------------------------------------------------- ------------------------------------------------------------------------------- --SLAVE INTERFACE if ramdebug = 2 then edcldbgread := '0'; end if; --write if (psel and penable and pwrite) = '1' then if (ramdebug = 0) or (paddr(17 downto 16) = "00") then case paddr(5 downto 2) is when "0000" => --ctrl reg if ramdebug /= 0 then v.ctrl.ramdebugen := pwdata(13); end if; if edcl /= 0 then v.ctrl.edcldis := pwdata(14); v.disableduplex := pwdata(12); end if; if multicast = 1 then v.ctrl.mcasten := pwdata(11); end if; if enable_mdint = 1 then v.ctrl.pstatirqen := pwdata(10); end if; if rmii = 1 then v.ctrl.speed := pwdata(7); end if; v.ctrl.reset := pwdata(6); v.ctrl.prom := pwdata(5); v.ctrl.full_duplex := pwdata(4); v.ctrl.rx_irqen := pwdata(3); v.ctrl.tx_irqen := pwdata(2); v.ctrl.rxen := pwdata(1); v.ctrl.txen := pwdata(0); when "0001" => --status/int source reg if enable_mdint = 1 then if pwdata(8) = '1' then v.status.phystat := '0'; end if; end if; if pwdata(7) = '1' then v.status.invaddr := '0'; end if; if pwdata(6) = '1' then v.status.toosmall := '0'; end if; if pwdata(5) = '1' then v.status.txahberr := '0'; end if; if pwdata(4) = '1' then v.status.rxahberr := '0'; end if; if pwdata(3) = '1' then v.status.tx_int := '0'; end if; if pwdata(2) = '1' then v.status.rx_int := '0'; end if; if pwdata(1) = '1' then v.status.tx_err := '0'; end if; if pwdata(0) = '1' then v.status.rx_err := '0'; end if; when "0010" => --mac addr msb v.mac_addr(47 downto 32) := pwdata(15 downto 0); when "0011" => --mac addr lsb v.mac_addr(31 downto 0) := pwdata(31 downto 0); when "0100" => --mdio ctrl/status if enable_mdio = 1 then if r.mdio_ctrl.busy = '0' then v.mdio_ctrl.data := pwdata(31 downto 16); v.mdio_ctrl.phyadr := pwdata(15 downto 11); v.mdio_ctrl.regadr := pwdata(10 downto 6); v.mdio_ctrl.read := pwdata(1); v.mdio_ctrl.write := pwdata(0); v.mdio_ctrl.busy := pwdata(1) or pwdata(0); end if; end if; when "0101" => --tx descriptor v.txdesc := pwdata(31 downto 10); v.txdsel := pwdata(9 downto 3); when "0110" => --rx descriptor v.rxdesc := pwdata(31 downto 10); v.rxdsel := pwdata(9 downto 3); when "0111" => --edcl ip if (edcl /= 0) then v.edclip := pwdata; end if; when "1000" => --hash msb if multicast = 1 then v.hash(63 downto 32) := pwdata; end if; when "1001" => --hash lsb if multicast = 1 then v.hash(31 downto 0) := pwdata; end if; when "1010" => if edcl /= 0 then v.emacaddr(47 downto 32) := pwdata(15 downto 0); end if; when "1011" => if edcl /= 0 then v.emacaddr(31 downto 0) := pwdata; end if; when others => null; end case; elsif ((ramdebug /= 0) and (paddr(17 downto 16) = "01")) then if r.ctrl.ramdebugen = '1' then vtxfi.write := '1'; vtxfi.waddress := paddr(txfabits+1 downto 2); vtxfi.datain := pwdata; end if; elsif ((ramdebug /= 0) and (paddr(17 downto 16) = "10")) then if r.ctrl.ramdebugen = '1' then vrxfi.write := '1'; vrxfi.waddress := paddr(fabits+1 downto 2); vrxfi.datain := pwdata; end if; elsif ((ramdebug = 2) and (edcl /= 0) and (paddr(17 downto 16) = "11")) then if r.ctrl.ramdebugen = '1' then veri.datain := pwdata; veri.waddressm := paddr(eabits+1 downto 2); veri.waddressl := paddr(eabits+1 downto 2); veri.writem := '1'; veri.writel := '1'; end if; end if; end if; --read if (ramdebug = 0) or (paddr(17 downto 16) = "00") then case paddr(5 downto 2) is when "0000" => --ctrl reg if ramdebug /= 0 then vprdata(13) := r.ctrl.ramdebugen; end if; if (edcl /= 0) then vprdata(31) := '1'; vprdata(30 downto 28) := bufsize; vprdata(14) := r.ctrl.edcldis; vprdata(12) := r.disableduplex; end if; if enable_mdint = 1 then vprdata(26) := '1'; vprdata(10) := r.ctrl.pstatirqen; end if; if multicast = 1 then vprdata(25) := '1'; vprdata(11) := r.ctrl.mcasten; end if; if rmii = 1 then vprdata(7) := r.ctrl.speed; end if; vprdata(6) := r.ctrl.reset; vprdata(5) := r.ctrl.prom; vprdata(4) := r.ctrl.full_duplex; vprdata(3) := r.ctrl.rx_irqen; vprdata(2) := r.ctrl.tx_irqen; vprdata(1) := r.ctrl.rxen; vprdata(0) := r.ctrl.txen; when "0001" => --status/int source reg vprdata(9) := not (r.etxidle or r.erxidle); if enable_mdint = 1 then vprdata(8) := r.status.phystat; end if; vprdata(7) := r.status.invaddr; vprdata(6) := r.status.toosmall; vprdata(5) := r.status.txahberr; vprdata(4) := r.status.rxahberr; vprdata(3) := r.status.tx_int; vprdata(2) := r.status.rx_int; vprdata(1) := r.status.tx_err; vprdata(0) := r.status.rx_err; when "0010" => --mac addr msb/mdio address vprdata(15 downto 0) := r.mac_addr(47 downto 32); when "0011" => --mac addr lsb vprdata := r.mac_addr(31 downto 0); when "0100" => --mdio ctrl/status vprdata(31 downto 16) := r.mdio_ctrl.data; vprdata(15 downto 11) := r.mdio_ctrl.phyadr; vprdata(10 downto 6) := r.mdio_ctrl.regadr; vprdata(3) := r.mdio_ctrl.busy; vprdata(2) := r.mdio_ctrl.linkfail; vprdata(1) := r.mdio_ctrl.read; vprdata(0) := r.mdio_ctrl.write; when "0101" => --tx descriptor vprdata(31 downto 10) := r.txdesc; vprdata(9 downto 3) := r.txdsel; when "0110" => --rx descriptor vprdata(31 downto 10) := r.rxdesc; vprdata(9 downto 3) := r.rxdsel; when "0111" => --edcl ip if (edcl /= 0) then vprdata := r.edclip; end if; when "1000" => if multicast = 1 then vprdata := r.hash(63 downto 32); end if; when "1001" => if multicast = 1 then vprdata := r.hash(31 downto 0); end if; when "1010" => if edcl /= 0 then vprdata(15 downto 0) := r.emacaddr(47 downto 32); end if; when "1011" => if edcl /= 0 then vprdata := r.emacaddr(31 downto 0); end if; when others => null; end case; elsif ((ramdebug /= 0) and (paddr(17 downto 16) = "01")) then if r.ctrl.ramdebugen = '1' then vtxfi.renable := '1'; vtxfi.raddress := paddr(txfabits+1 downto 2); vprdata := txrdata; end if; elsif ((ramdebug /= 0) and (paddr(17 downto 16) = "10")) then if r.ctrl.ramdebugen = '1' then vrxfi.renable := '1'; vrxfi.raddress := paddr(fabits+1 downto 2); vprdata := rxrdata; end if; elsif ((ramdebug = 2) and (edcl /= 0) and (paddr(17 downto 16) = "11")) then if r.ctrl.ramdebugen = '1' then edcldbgread := '1'; veri.renable := '1'; veri.raddress := paddr(eabits+1 downto 2); vprdata := erdata; end if; end if; --PHY STATUS DETECTION if enable_mdint = 1 then if mdint_pol = 0 then if (r.mdint_sync(2) and not r.mdint_sync(1)) = '1' then v.status.phystat := '1'; if r.ctrl.pstatirqen = '1' then vpirq := '1'; end if; end if; else if (r.mdint_sync(1) and not r.mdint_sync(2)) = '1' then v.status.phystat := '1'; if r.ctrl.pstatirqen = '1' then vpirq := '1'; end if; end if; end if; end if; --MASTER INTERFACE v.txburstav := '0'; if (txfifosizev - r.tfcnt) >= txburstlen then v.txburstav := '1'; end if; if (conv_integer(r.abufs) /= 0) then v.etxidle := '0'; else v.etxidle := '1'; end if; --tx dma fsm case r.txdstate is when idle => v.txcnt := (others => '0'); v.txburstcnt := (others => '0'); if (edcl /= 0) then v.tedcl := '0'; v.erenable := '0'; end if; if (edcl /= 0) and (conv_integer(r.abufs) /= 0) and (r.ctrl.edcldis = '0') then v.erenable := '1'; v.etxidle := '0'; if r.erenable = '1' then v.txdstate := getlen; end if; v.tcnt := conv_std_logic_vector(10, bpbits); elsif r.ctrl.txen = '1' then v.txdstate := read_desc; v.tmsto.write := '0'; v.tmsto.addr := r.txdesc & r.txdsel & "000"; v.tmsto.req := '1'; end if; if r.txirqgen = '1' then vpirq := '1'; v.txirqgen := '0'; end if; if txrestart = '1' then v.txrestart(nsync) := r.txrestart(nsync-1); v.tfcnt := (others => '0'); v.tfrpnt := (others => '0'); v.tfwpnt := (others => '0'); end if; when read_desc => v.tmsto.write := '0'; v.txstatus := (others => '0'); v.tfwpnt := (others => '0'); v.tfrpnt := (others => '0'); v.tfcnt := (others => '0'); if tmsti.grant = '1' then v.txburstcnt := r.txburstcnt + 1; v.tmsto.addr := r.tmsto.addr + 4; if r.txburstcnt(0) = '1' then v.tmsto.req := '0'; end if; end if; if tmsti.ready = '1' then v.txcnt := r.txcnt + 1; case r.txcnt(1 downto 0) is when "00" => v.txlength := tmsti.data(10 downto 0); v.txden := tmsti.data(11); v.txwrap := tmsti.data(12); v.txirq := tmsti.data(13); v.ctrl.txen := tmsti.data(11); when "01" => v.txaddr := tmsti.data(31 downto 2); v.txdstate := check_desc; when others => null; end case; end if; when check_desc => v.txstart := '0'; v.txburstcnt := (others => '0'); if r.txden = '1' then if (unsigned(r.txlength) > unsigned(maxsizetx)) or (conv_integer(r.txlength) = 0) then v.txdstate := write_result; v.tmsto.req := '1'; v.tmsto.write := '1'; v.tmsto.addr := r.txdesc & r.txdsel & "000"; v.tmsto.data := (others => '0'); else v.txdstate := req; v.tmsto.addr := r.txaddr & "00"; v.txcnt(10 downto 0) := r.txlength; end if; else v.txdstate := idle; end if; when req => if txrestart = '1' then v.txdstate := idle; v.txstart := '0'; if (edcl /= 0) and (r.tedcl = '1') then v.txdstate := idle; end if; elsif txdone = '1' then v.txdstate := check_result; v.tfcnt := (others => '0'); v.tfrpnt := (others => '0'); v.tfwpnt := (others => '0'); if (edcl /= 0) and (r.tedcl = '1') then v.txdstate := etdone; end if; elsif conv_integer(r.txcnt) = 0 then v.txdstate := check_result; if (edcl /= 0) and (r.tedcl = '1') then v.txdstate := etdone; v.txstart_sync := not r.txstart_sync; end if; elsif (r.txburstav = '1') or (r.tedcl = '1') then if (edclsepahbg = 0) or (edcl = 0) or (r.edclsepahb = '0') or (r.tedcl = '0') then v.tmsto.req := '1'; v.txdstate := fill_fifo; else v.tmsto2.req := '1'; v.txdstate := fill_fifo2; end if; end if; v.txburstcnt := (others => '0'); when fill_fifo => v.txburstav := '0'; if tmsti.grant = '1' then v.tmsto.addr := r.tmsto.addr + 4; if ((conv_integer(r.txcnt) <= 8) and (tmsti.ready = '1')) or ((conv_integer(r.txcnt) <= 4) and (tmsti.ready = '0')) then v.tmsto.req := '0'; end if; v.txburstcnt := r.txburstcnt + 1; if (conv_integer(r.txburstcnt) = burstlength-1) then v.tmsto.req := '0'; end if; end if; if (tmsti.ready = '1') or ((edcl /= 0) and (r.tedcl and tmsti.error) = '1') then v.tfwpnt := r.tfwpnt + 1; v.tfcnt := r.tfcnt + 1; vtxfi.write := '1'; if r.tmsto.req = '0' then v.txdstate := req; if (r.txstart = '0') and not ((edcl /= 0) and (r.tedcl = '1')) then v.txstart := '1'; v.txstart_sync := not r.txstart_sync; end if; end if; if conv_integer(r.txcnt) > 3 then v.txcnt := r.txcnt - 4; else v.txcnt := (others => '0'); end if; end if; when fill_fifo2 => if edclsepahbg = 1 then v.txburstav := '0'; vtxfi.datain := tmsti2.data; if tmsti2.grant = '1' then v.tmsto2.addr := r.tmsto2.addr + 4; if ((conv_integer(r.txcnt) <= 8) and (tmsti2.ready = '1')) or ((conv_integer(r.txcnt) <= 4) and (tmsti2.ready = '0')) then v.tmsto2.req := '0'; end if; v.txburstcnt := r.txburstcnt + 1; if (conv_integer(r.txburstcnt) = burstlength-1) then v.tmsto2.req := '0'; end if; end if; if (tmsti2.ready = '1') or ((edcl /= 0) and (r.tedcl and tmsti2.error) = '1') then v.tfwpnt := r.tfwpnt + 1; v.tfcnt := r.tfcnt + 1; vtxfi.write := '1'; if r.tmsto2.req = '0' then v.txdstate := req; if (r.txstart = '0') and not ((edcl /= 0) and (r.tedcl = '1')) then v.txstart := '1'; v.txstart_sync := not r.txstart_sync; end if; end if; if conv_integer(r.txcnt) > 3 then v.txcnt := r.txcnt - 4; else v.txcnt := (others => '0'); end if; end if; end if; when check_result => if txdone = '1' then v.txdstate := write_result; v.tmsto.req := '1'; v.txstart := '0'; v.tmsto.write := '1'; v.tmsto.addr := r.txdesc & r.txdsel & "000"; v.tmsto.data(31 downto 16) := (others => '0'); v.tmsto.data(15 downto 14) := v.txstatus; v.tmsto.data(13 downto 0) := (others => '0'); v.txdone(nsync) := r.txdone(nsync-1); elsif txrestart = '1' then v.txdstate := idle; v.txstart := '0'; end if; when write_result => if tmsti.grant = '1' then v.tmsto.req := '0'; v.tmsto.addr := r.tmsto.addr + 4; end if; if tmsti.ready = '1' then v.txdstate := idle; v.txirqgen := r.ctrl.tx_irqen and r.txirq; if r.txwrap = '0' then v.txdsel := r.txdsel + 1; else v.txdsel := (others => '0'); end if; if conv_integer(r.txstatus) = 0 then v.status.tx_int := '1'; else v.status.tx_err := '1'; end if; end if; when ahberror => v.tfcnt := (others => '0'); v.tfwpnt := (others => '0'); v.tfrpnt := (others => '0'); v.status.txahberr := '1'; v.ctrl.txen := '0'; if not ((edcl /= 0) and (r.tedcl = '1')) then if r.txstart = '1' then if txdone = '1' then v.txdstate := idle; v.txdone(nsync) := r.txdone(nsync-1); end if; else v.txdstate := idle; end if; else v.txdstate := idle; v.abufs := r.abufs - 1; v.tpnt := r.tpnt + 1; end if; when others => null; end case; --tx fifo read v.txdataav := '0'; if conv_integer(r.tfcnt) /= 0 then v.txdataav := '1'; end if; if txread = '1' then v.txreadack := not r.txreadack; if r.txdataav = '1' then if conv_integer(r.tfcnt) < 2 then v.txdataav := '0'; end if; v.txvalid := '1'; v.tfcnt := v.tfcnt - 1; v.tfrpnt := r.tfrpnt + 1; else v.txvalid := '0'; end if; v.txdata := txrdata; end if; v.rxburstav := '0'; if r.rfcnt >= rxburstlen then v.rxburstav := '1'; end if; if ramdebug = 0 then vtxfi.renable := v.txdataav; else vtxfi.renable := vtxfi.renable or v.txdataav; end if; --rx dma fsm case r.rxdstate is when idle => v.rmsto.req := '0'; v.rmsto.write := '0'; v.addrok := '0'; v.rxburstcnt := (others => '0'); v.addrdone := '0'; v.rxcnt := (others => '0'); v.rxdoneold := '0'; v.ctrlpkt := '0'; v.bcast := '0'; v.edclactive := '0'; v.msbgood := '0'; v.rxrenable := '0'; if multicast = 1 then v.mcast := '0'; v.mcastacc := '0'; end if; if r.ctrl.rxen = '1' then v.rxdstate := read_desc; v.rmsto.req := '1'; v.rmsto.addr := r.rxdesc & r.rxdsel & "000"; elsif rxstart = '1' then v.rxstart(nsync) := r.rxstart(nsync-1); v.rxdstate := discard; end if; when read_desc => v.rxstatus := (others => '0'); if rmsti.grant = '1' then v.rxburstcnt := r.rxburstcnt + 1; v.rmsto.addr := r.rmsto.addr + 4; if r.rxburstcnt(0) = '1' then v.rmsto.req := '0'; end if; end if; if rmsti.ready = '1' then v.rxcnt := r.rxcnt + 1; case r.rxcnt(1 downto 0) is when "00" => v.ctrl.rxen := rmsti.data(11); v.rxden := rmsti.data(11); v.rxwrap := rmsti.data(12); v.rxirq := rmsti.data(13); when "01" => v.rxaddr := rmsti.data(31 downto 2); v.rxdstate := check_desc; v.rxrenable := '1'; when others => null; end case; end if; if rmsti.error = '1' then v.rmsto.req := '0'; v.rxdstate := idle; v.status.rxahberr := '1'; v.ctrl.rxen := '0'; end if; when check_desc => v.rxcnt := (others => '0'); v.usesizefield := '0'; v.rmsto.write := '1'; if r.rxden = '1' then if rxstart = '1' then v.rxdstate := read_req; v.rxstart(nsync) := r.rxstart(nsync-1); end if; else v.rxdstate := idle; end if; v.rmsto.addr := r.rxaddr & "00"; when read_req => if r.edclactive = '1' then v.rxdstate := discard; elsif (r.rxdoneold and r.rxstatus(3)) = '1' then v.rxdstate := write_status; v.rfcnt := (others => '0'); v.rfwpnt := (others => '0'); v.rfrpnt := (others => '0'); v.writeok := '1'; v.rxbytecount := (others => '0'); v.rxlength := (others => '0'); elsif ((r.addrdone and not r.addrok) or r.ctrlpkt) = '1' then v.rxdstate := discard; v.status.invaddr := '1'; elsif ((r.rxdoneold = '1') and r.rxcnt >= r.rxlength) then if r.gotframe = '1' then v.rxdstate := write_status; else v.rxdstate := discard; v.status.toosmall := '1'; end if; elsif (r.rxburstav or r.rxdoneold) = '1' then v.rmsto.req := '1'; v.rxdstate := read_fifo; v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1; end if; v.rxburstcnt := (others => '0'); v.rmsto.data := rxrdata; when read_fifo => v.rxburstav := '0'; if rmsti.grant = '1' then v.rmsto.addr := r.rmsto.addr + 4; if (lengthav = '1') then if ((conv_integer(r.rxcnt) >= (conv_integer(r.rxlength) - 8)) and (rmsti.ready = '1')) or ((conv_integer(r.rxcnt) >= (conv_integer(r.rxlength) - 4)) and (rmsti.ready = '0')) then v.rmsto.req := '0'; end if; end if; v.rxburstcnt := r.rxburstcnt + 1; if (conv_integer(r.rxburstcnt) = burstlength-1) then v.rmsto.req := '0'; end if; end if; if rmsti.ready = '1' then v.rmsto.data := rxrdata; v.rxcnt := r.rxcnt + 4; if r.rmsto.req = '0' then v.rxdstate := read_req; else v.rfcnt := r.rfcnt - 1; v.rfrpnt := r.rfrpnt + 1; end if; v.check := '1'; v.checkdata := r.rmsto.data; end if; if rmsti.error = '1' then v.rmsto.req := '0'; v.rxdstate := discard; v.rxcnt := r.rxcnt + 4; v.status.rxahberr := '1'; v.ctrl.rxen := '0'; end if; when write_status => v.rmsto.req := '1'; v.rmsto.addr := r.rxdesc & r.rxdsel & "000"; v.rxdstate := write_status2; if multicast = 1 then v.rmsto.data := "00000" & r.mcastacc & "0000000" & r.rxstatus & "000" & r.rxlength; else v.rmsto.data := "0000000000000" & r.rxstatus & "000" & r.rxlength; end if; when write_status2 => if rmsti.grant = '1' then v.rmsto.req := '0'; v.rmsto.addr := r.rmsto.addr + 4; end if; if rmsti.ready = '1' then if (r.rxstatus(4) or not r.rxstatus(3)) = '1' then v.rxdstate := discard; else v.rxdstate := idle; end if; if (r.ctrl.rx_irqen and r.rxirq) = '1' then vpirq := '1'; end if; if conv_integer(r.rxstatus) = 0 then v.status.rx_int := '1'; else v.status.rx_err := '1'; end if; if r.rxwrap = '1' then v.rxdsel := (others => '0'); else v.rxdsel := r.rxdsel + 1; end if; end if; if rmsti.error = '1' then v.rmsto.req := '0'; v.rxdstate := idle; v.status.rxahberr := '1'; v.ctrl.rxen := '0'; end if; when discard => if (r.rxdoneold = '0') then if conv_integer(r.rfcnt) /= 0 then v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1; v.rxcnt := r.rxcnt + 4; end if; else if r.rxstatus(3) = '1' then v.rfcnt := (others => '0'); v.rfwpnt := (others => '0'); v.rfrpnt := (others => '0'); v.writeok := '1'; v.rxbytecount := (others => '0'); v.rxlength := (others => '0'); v.rxdstate := idle; elsif (conv_integer(r.rxcnt) < conv_integer(r.rxbytecount)) then if conv_integer(r.rfcnt) /= 0 then v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1; v.rxcnt := r.rxcnt + 4; end if; else v.rxdstate := idle; v.ctrlpkt := '0'; end if; end if; when others => null; end case; --rx address/type check if r.check = '1' and r.rxcnt(10 downto 5) = "000000" then case r.rxcnt(4 downto 2) is when "001" => if r.ctrl.prom = '1' then v.addrok := '1'; end if; v.mcast := r.checkdata(24); if r.checkdata = broadcast(47 downto 16) then v.bcast := '1'; end if; if r.checkdata = r.mac_addr(47 downto 16) then v.msbgood := '1'; end if; when "010" => if r.checkdata(31 downto 16) = broadcast(15 downto 0) then if r.bcast = '1' then v.addrok := '1'; end if; else v.bcast := '0'; end if; if r.checkdata(31 downto 16) = r.mac_addr(15 downto 0) then if r.msbgood = '1' then v.addrok := '1'; end if; end if; if multicast = 1 then v.hashlookup := r.hash(conv_integer(rxo.mcasthash)); end if; when "011" => if multicast = 1 then if (r.hashlookup and r.ctrl.mcasten and r.mcast) = '1' then v.addrok := '1'; if r.bcast = '0' then v.mcastacc := '1'; end if; end if; end if; when "100" => if r.checkdata(31 downto 16) = ctrlopcode then v.ctrlpkt := '1'; end if; v.addrdone := '1'; when others => null; end case; end if; --rx packet done if (rxdone and not rxstart) = '1' then v.gotframe := rxo.gotframe; v.rxbytecount := rxo.byte_count; v.rxstatus(3 downto 0) := rxo.status; if (unsigned(rxo.lentype) > maxsizerx) or (rxo.status /= "0000") then v.rxlength := rxo.byte_count; else v.rxlength := rxo.lentype(10 downto 0); if (rxo.lentype(10 downto 0) > minpload) and (rxo.lentype(10 downto 0) /= rxo.byte_count) then if rxo.status(2 downto 0) = "000" then v.rxstatus(4) := '1'; v.rxlength := rxo.byte_count; v.usesizefield := '0'; end if; elsif (rxo.lentype(10 downto 0) <= minpload) and (rxo.byte_count /= minpload) then if rxo.status(2 downto 0) = "000" then v.rxstatus(4) := '1'; v.rxlength := rxo.byte_count; v.usesizefield := '0'; end if; end if; end if; v.rxdoneold := '1'; v.rxdoneack := not r.rxdoneack; end if; --rx fifo write if vrxwrite = '1' then v.rxwriteack := not r.rxwriteack; if (not r.rfcnt(fabits)) = '1' then v.rfwpnt := r.rfwpnt + 1; v.rfcnt := v.rfcnt + 1; v.writeok := '1'; vrxfi.write := '1'; else v.writeok := '0'; end if; end if; --must be placed here because it uses variable if (ramdebug = 0) or (r.ctrl.ramdebugen = '0') then vrxfi.raddress := v.rfrpnt; end if; ------------------------------------------------------------------------------- -- MDIO INTERFACE ------------------------------------------------------------- ------------------------------------------------------------------------------- --mdio commands if enable_mdio = 1 then mclkvec := r.mdioclkold & r.mdioclk; mclk := mclkvec(mdiohold-1) and not mclkvec(mdiohold); nmclk := mclkvec(1) and not mclkvec(0); v.mdioclkold := mclkvec(mdiohold-1 downto 0); if r.mdccnt = "00000000" then v.mdccnt := divisor; v.mdioclk := not r.mdioclk; else v.mdccnt := r.mdccnt - 1; end if; mdioindex := conv_integer(r.cnt); v.mdioi := mdio_i; case r.mdio_state is when idle => if (enable_mdio = 1) and (edcl = 0) and (r.ctrl.reset = '1') then v.mdio_state := idle; v.mdio_ctrl.read := '0'; v.mdio_ctrl.write := '0'; v.mdio_ctrl.busy := '0'; v.mdio_ctrl.data := (others => '0'); v.mdio_ctrl.regadr := (others => '0'); v.ctrl.reset := '0'; if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if; end if; if mclk = '1' then v.cnt := (others => '0'); if r.mdio_ctrl.busy = '1' then v.mdio_ctrl.linkfail := '0'; if r.mdio_ctrl.read = '1' then v.mdio_ctrl.write := '0'; end if; v.mdio_state := preamble; v.mdioo := '1'; if OEPOL = 0 then v.mdioen := '0'; else v.mdioen := '1'; end if; end if; end if; when preamble => if mclk = '1' then v.cnt := r.cnt + 1; if r.cnt = "11111" then v.mdioo := '0'; v.mdio_state := startst; end if; end if; when startst => if mclk = '1' then v.mdioo := '1'; v.mdio_state := op; v.cnt := (others => '0'); end if; when op => if mclk = '1' then v.mdio_state := op2; if r.mdio_ctrl.read = '1' then v.mdioo := '1'; else v.mdioo := '0'; end if; end if; when op2 => if mclk = '1' then v.mdioo := not r.mdioo; v.mdio_state := phyadr; v.cnt := (others => '0'); end if; when phyadr => if mclk = '1' then v.cnt := r.cnt + 1; case mdioindex is when 0 => v.mdioo := r.mdio_ctrl.phyadr(4); when 1 => v.mdioo := r.mdio_ctrl.phyadr(3); when 2 => v.mdioo := r.mdio_ctrl.phyadr(2); when 3 => v.mdioo := r.mdio_ctrl.phyadr(1); when 4 => v.mdioo := r.mdio_ctrl.phyadr(0); v.mdio_state := regadr; v.cnt := (others => '0'); when others => null; end case; end if; when regadr => if mclk = '1' then v.cnt := r.cnt + 1; case mdioindex is when 0 => v.mdioo := r.mdio_ctrl.regadr(4); when 1 => v.mdioo := r.mdio_ctrl.regadr(3); when 2 => v.mdioo := r.mdio_ctrl.regadr(2); when 3 => v.mdioo := r.mdio_ctrl.regadr(1); when 4 => v.mdioo := r.mdio_ctrl.regadr(0); v.mdio_state := ta; v.cnt := (others => '0'); when others => null; end case; end if; when ta => if mclk = '1' then v.mdio_state := ta2; if r.mdio_ctrl.read = '1' then if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if; else v.mdioo := '1'; end if; end if; when ta2 => if mclk = '1' then v.cnt := "01111"; v.mdio_state := ta3; if r.mdio_ctrl.write = '1' then v.mdioo := '0'; v.mdio_state := data; end if; end if; when ta3 => if mclk = '1' then v.mdio_state := data; end if; if nmclk = '1' then if r.mdioi /= '0' then v.mdio_ctrl.linkfail := '1'; end if; end if; when data => if mclk = '1' then v.cnt := r.cnt - 1; if r.cnt = "00000" then v.mdio_state := dataend; end if; if r.mdio_ctrl.read = '0' then v.mdioo := r.mdio_ctrl.data(mdioindex); end if; end if; if nmclk = '1' then if r.mdio_ctrl.read = '1' then v.mdio_ctrl.data(mdioindex) := r.mdioi; end if; end if; when dataend => if mclk = '1' then if (rmii = 1) or (edcl /= 0) then v.init_busy := '0'; if r.duplexstate = done then v.mdio_ctrl.busy := '0'; end if; else v.mdio_ctrl.busy := '0'; end if; v.mdio_ctrl.read := '0'; v.mdio_ctrl.write := '0'; v.mdio_state := idle; if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if; end if; when others => null; end case; end if; ------------------------------------------------------------------------------- -- EDCL ----------------------------------------------------------------------- ------------------------------------------------------------------------------- if (edcl /= 0) then if (ramdebug /= 2) or (r.ctrl.ramdebugen = '0') then veri.renable := r.erenable; veri.writem := '0'; veri.writel := '0'; veri.waddressm := r.rpnt & r.rcntm; veri.waddressl := r.rpnt & r.rcntl; vrxenable := '1'; end if; swap := '0'; vecnt := conv_integer(r.ecnt); setmz := '0'; if vrxwrite = '1' then if r.ctrl.edcldis = '0' then v.rxwriteack := not r.rxwriteack; end if; end if; --edcl receiver case r.edclrstate is when idle => v.edclbcast := '0'; v.erxidle := '1'; if (ramdebug /= 2) or (r.ctrl.ramdebugen = '0') then if (rxstart and not r.ctrl.edcldis) = '1' then v.edclrstate := wrda; v.edclactive := '0'; v.erxidle := '0'; v.rcntm := conv_std_logic_vector(2, bpbits); v.rcntl := conv_std_logic_vector(1, bpbits); end if; end if; when wrda => if vrxwrite = '1' then v.edclrstate := wrdsa; veri.writem := '1'; veri.writel := '1'; swap := '1'; v.rcntm := r.rcntm - 2; v.rcntl := r.rcntl + 1; if (r.emacaddr(47 downto 16) /= rxo.dataout) and (X"FFFFFFFF" /= rxo.dataout) then v.edclrstate := spill; elsif (X"FFFFFFFF" = rxo.dataout) then v.edclbcast := '1'; end if; if conv_integer(r.abufs) = wsz then v.edclrstate := spill; end if; end if; if (rxdone and not rxstart) = '1' then v.edclrstate := idle; end if; when wrdsa => if vrxwrite = '1' then v.edclrstate := wrsa; swap := '1'; veri.writem := '1'; veri.writel := '1'; v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl - 2; if (r.emacaddr(15 downto 0) /= rxo.dataout(31 downto 16)) and (X"FFFF" /= rxo.dataout(31 downto 16)) then v.edclrstate := spill; elsif (X"FFFF" = rxo.dataout(31 downto 16)) then v.edclbcast := r.edclbcast; end if; end if; if (rxdone and not rxstart) = '1' then v.edclrstate := idle; end if; when wrsa => if vrxwrite = '1' then veri.writem := '1'; veri.writel := '1'; v.edclrstate := wrtype; swap := '1'; v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl + 3; end if; if (rxdone and not rxstart) = '1' then v.edclrstate := idle; end if; when wrtype => if vrxwrite = '1' then veri.writem := '1'; veri.writel := '1'; v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1; if X"0800" = rxo.dataout(31 downto 16) and (r.edclbcast = '0') then v.edclrstate := ip; elsif X"0806" = rxo.dataout(31 downto 16) and (r.edclbcast = '1') then v.edclrstate := arp; else v.edclrstate := spill; end if; end if; v.ecnt := (others => '0'); v.ipcrc := (others => '0'); if (rxdone and not rxstart) = '1' then v.edclrstate := idle; end if; when ip => if vrxwrite = '1' then v.ecnt := r.ecnt + 1; veri.writem := '1'; veri.writel := '1'; case vecnt is when 0 => v.ipcrc := crcadder(not rxo.dataout(31 downto 16), r.ipcrc); v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1; when 1 => v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 2; when 2 => v.ipcrc := crcadder(not rxo.dataout(31 downto 16), r.ipcrc); v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl - 1; when 3 => v.rcntm := r.rcntm - 1; v.rcntl := r.rcntl + 2; when 4 => v.udpsrc := rxo.dataout(15 downto 0); v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl + 1; when 5 => setmz := '1'; v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1; when 6 => v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1; when 7 => v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1; if (rxo.dataout(31 downto 18) = r.seq) then v.nak := '0'; else v.nak := '1'; veri.datain(31 downto 18) := r.seq; end if; veri.datain(17) := v.nak; v.ewr := rxo.dataout(17); if (rxo.dataout(17) or v.nak) = '1' then veri.datain(16 downto 7) := (others => '0'); end if; v.oplen := rxo.dataout(16 downto 7); v.applength := "000000" & veri.datain(16 downto 7); v.ipcrc := crcadder(v.applength + 38, r.ipcrc); v.write(conv_integer(r.rpnt)) := rxo.dataout(17); when 8 => ipcrctmp := (others => '0'); ipcrctmp(1 downto 0) := r.ipcrc(17 downto 16); ipcrctmp2 := "00" & r.ipcrc(15 downto 0); v.ipcrc := crcadder(ipcrctmp, ipcrctmp2); v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1; v.edclrstate := ipdata; when others => null; end case; end if; if (rxdone and not rxstart) = '1' then v.edclrstate := idle; end if; when ipdata => if (vrxwrite and r.ewr and not r.nak) = '1' and (r.rcntm /= ebufmax) then veri.writem := '1'; veri.writel := '1'; v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1; end if; if rxdone = '1' then v.edclrstate := ipcrc; v.rcntm := conv_std_logic_vector(6, bpbits); ipcrctmp := (others => '0'); ipcrctmp(1 downto 0) := r.ipcrc(17 downto 16); ipcrctmp2 := "00" & r.ipcrc(15 downto 0); v.ipcrc := crcadder(ipcrctmp, ipcrctmp2); if conv_integer(v.rxstatus(3 downto 0)) /= 0 then v.edclrstate := idle; end if; end if; when ipcrc => veri.writem := '1'; veri.datain(31 downto 16) := not r.ipcrc(15 downto 0); v.edclrstate := udp; v.rcntm := conv_std_logic_vector(9, bpbits); v.rcntl := conv_std_logic_vector(9, bpbits); when udp => veri.writem := '1'; veri.writel := '1'; v.edclrstate := iplength; veri.datain(31 downto 16) := r.udpsrc; veri.datain(15 downto 0) := r.applength + 18; v.rcntm := conv_std_logic_vector(4, bpbits); when iplength => veri.writem := '1'; veri.datain(31 downto 16) := r.applength + 38; v.edclrstate := oplength; v.rcntm := conv_std_logic_vector(10, bpbits); v.rcntl := conv_std_logic_vector(10, bpbits); when oplength => if rxstart = '0' then v.abufs := r.abufs + 1; v.rpnt := r.rpnt + 1; veri.writel := '1'; veri.writem := '1'; end if; if r.nak = '0' then v.seq := r.seq + 1; end if; v.edclrstate := idle; veri.datain(31 downto 0) := (others => '0'); veri.datain(15 downto 0) := "00000" & r.nak & r.oplen; when arp => if vrxwrite = '1' then v.ecnt := r.ecnt + 1; veri.writem := '1'; veri.writel := '1'; case vecnt is when 0 => v.rcntm := r.rcntm + 4; when 1 => swap := '1'; veri.writel := '0'; v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 4; when 2 => swap := '1'; v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1; when 3 => swap := '1'; v.rcntm := r.rcntm - 4; v.rcntl := r.rcntl - 4; when 4 => veri.datain := r.emacaddr(31 downto 16) & r.emacaddr(47 downto 32); v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1; when 5 => v.rcntl := r.rcntl + 1; veri.datain(31 downto 16) := rxo.dataout(15 downto 0); veri.datain(15 downto 0) := r.emacaddr(15 downto 0); if rxo.dataout(15 downto 0) /= r.edclip(31 downto 16) then v.edclrstate := spill; end if; when 6 => swap := '1'; veri.writem := '0'; v.rcntm := conv_std_logic_vector(5, bpbits); v.rcntl := conv_std_logic_vector(1, bpbits); if rxo.dataout(31 downto 16) /= r.edclip(15 downto 0) then v.edclrstate := spill; else v.edclactive := '1'; end if; when 7 => veri.writem := '0'; veri.datain(15 downto 0) := r.emacaddr(47 downto 32); v.rcntl := r.rcntl + 1; v.rcntm := conv_std_logic_vector(2, bpbits); when 8 => v.edclrstate := arpop; veri.datain := r.emacaddr(31 downto 0); v.rcntm := conv_std_logic_vector(5, bpbits); when others => null; end case; end if; if (rxdone and not rxstart) = '1' then v.edclrstate := idle; end if; when arpop => veri.writem := '1'; veri.datain(31 downto 16) := X"0002"; if (rxdone and not rxstart) = '1' then v.edclrstate := idle; if conv_integer(v.rxstatus) = 0 and (rxo.gotframe = '1') then v.abufs := r.abufs + 1; v.rpnt := r.rpnt + 1; end if; end if; when spill => if (rxdone and not rxstart) = '1' then v.edclrstate := idle; end if; end case; --edcl transmitter case r.txdstate is when getlen => v.tcnt := r.tcnt + 1; if conv_integer(r.tcnt) = 10 then v.txlength := '0' & erdata(9 downto 0); v.tnak := erdata(10); v.txcnt := v.txlength; if (r.write(conv_integer(r.tpnt)) or v.tnak) = '1' then v.txlength := (others => '0'); end if; end if; if conv_integer(r.tcnt) = 11 then v.txdstate := readhdr; v.tcnt := (others => '0'); end if; when readhdr => v.tcnt := r.tcnt + 1; vtxfi.write := '1'; v.tfwpnt := r.tfwpnt + 1; v.tfcnt := v.tfcnt + 1; vtxfi.datain := erdata; if conv_integer(r.tcnt) = 12 then v.txaddr := erdata(31 downto 2); end if; if conv_integer(r.tcnt) = 3 then if erdata(31 downto 16) = X"0806" then v.tarp := '1'; v.txlength := conv_std_logic_vector(42, 11); else v.tarp := '0'; v.txlength := r.txlength + 52; end if; end if; if r.tarp = '0' then if conv_integer(r.tcnt) = 12 then v.txdstate := start; end if; else if conv_integer(r.tcnt) = 10 then v.txdstate := start; end if; end if; if (txrestart or txdone) = '1' then v.txdstate := etdone; end if; when start => v.tmsto.addr := r.txaddr & "00"; v.tmsto.write := r.write(conv_integer(r.tpnt)); if (edclsepahbg /= 0) and (edcl /= 0) then v.tmsto2.addr := r.txaddr & "00"; v.tmsto2.write := r.write(conv_integer(r.tpnt)); end if; if (conv_integer(r.txcnt) = 0) or (r.tarp or r.tnak) = '1' then v.txdstate := etdone; v.txstart_sync := not r.txstart_sync; v.tmsto.req := '0'; if (edclsepahbg /= 0) and (edcl /= 0) then v.tmsto2.req := '0'; end if; elsif r.write(conv_integer(r.tpnt)) = '0' then v.txdstate := req; v.tedcl := '1'; else v.txstart_sync := not r.txstart_sync; v.tedcl := '1'; v.tcnt := r.tcnt + 1; if (edclsepahbg = 0) or (edcl = 0) or (r.edclsepahb = '0') then v.tmsto.req := '1'; v.tmsto.data := erdata; v.txdstate := wrbus1; else v.tmsto2.req := '1'; v.tmsto2.data := erdata; v.txdstate := wrbus2; end if; end if; if (txrestart or txdone) = '1' then v.txdstate := etdone; end if; when wrbus1 => if tmsti.grant = '1' then v.tmsto.addr := r.tmsto.addr + 4; if ((conv_integer(r.txcnt) <= 4) and (tmsti.ready = '0')) or ((conv_integer(r.txcnt) <= 8) and (tmsti.ready = '1')) then v.tmsto.req := '0'; end if; end if; if (tmsti.ready or tmsti.error) = '1' then v.tmsto.data := erdata; v.tcnt := r.tcnt + 1; v.txcnt := r.txcnt - 4; if r.tmsto.req = '0' then v.txdstate := etdone; end if; end if; if tmsti.retry = '1' then v.tmsto.addr := r.tmsto.addr - 4; v.tmsto.req := '1'; end if; when wrbus2 => if tmsti2.grant = '1' then v.tmsto2.addr := r.tmsto2.addr + 4; if ((conv_integer(r.txcnt) <= 4) and (tmsti2.ready = '0')) or ((conv_integer(r.txcnt) <= 8) and (tmsti2.ready = '1')) then v.tmsto2.req := '0'; end if; end if; if (tmsti2.ready or tmsti2.error) = '1' then v.tmsto2.data := erdata; v.tcnt := r.tcnt + 1; v.txcnt := r.txcnt - 4; if r.tmsto2.req = '0' then v.txdstate := etdone; end if; end if; if tmsti2.retry = '1' then v.tmsto2.addr := r.tmsto2.addr - 4; v.tmsto2.req := '1'; end if; when etdone => if txdone = '1' then v.txdstate := idle; v.txdone(nsync) := r.txdone(nsync-1); v.abufs := v.abufs - 1; v.tpnt := r.tpnt + 1; v.tfcnt := (others => '0'); v.tfrpnt := (others => '0'); v.tfwpnt := (others => '0'); elsif txrestart = '1' then v.txdstate := idle; end if; when others => null; end case; if swap = '1' then veri.datain(31 downto 16) := rxo.dataout(15 downto 0); veri.datain(15 downto 0) := rxo.dataout(31 downto 16); end if; if setmz = '1' then veri.datain(31 downto 16) := (others => '0'); end if; if (ramdebug /= 2) or (edcl = 0) or (edcldbgread = '0') then veri.raddress := r.tpnt & v.tcnt; end if; end if; --edcl duplex mode read if (rmii = 1) or (edcl /= 0) then --edcl, gbit link mode check case r.duplexstate is when start => v.mdio_ctrl.regadr := r.regaddr; v.init_busy := '1'; v.mdio_ctrl.busy := '1'; v.duplexstate := waitop; if (r.phywr or r.rstphy) = '1' then v.mdio_ctrl.write := '1'; else v.mdio_ctrl.read := '1'; end if; if r.rstphy = '1' then v.mdio_ctrl.data := X"9000"; end if; when waitop => if r.init_busy = '0' then if r.mdio_ctrl.linkfail = '1' then v.duplexstate := start; elsif r.rstphy = '1' then v.duplexstate := start; v.rstphy := '0'; else v.duplexstate := nextop; end if; end if; when nextop => case r.regaddr is when "00000" => if r.mdio_ctrl.data(15) = '1' then --rst not finished v.duplexstate := start; elsif (r.phywr and not r.rstaneg) = '1' then --forced to 10 Mbit HD v.duplexstate := selmode; elsif r.mdio_ctrl.data(12) = '0' then --no auto neg v.duplexstate := start; v.phywr := '1'; v.mdio_ctrl.data := (others => '0'); else v.duplexstate := start; v.regaddr := "00001"; end if; if r.rstaneg = '1' then v.phywr := '0'; end if; when "00001" => v.ext := r.mdio_ctrl.data(8); --extended status register v.extcap := r.mdio_ctrl.data(1); --extended register capabilities v.duplexstate := start; if r.mdio_ctrl.data(0) = '0' then --no extended register capabilites, unable to read aneg config --forcing 10 Mbit v.duplexstate := start; v.phywr := '1'; v.mdio_ctrl.data := (others => '0'); v.regaddr := (others => '0'); elsif (r.mdio_ctrl.data(8) and not r.rstaneg) = '1' then --phy gbit capable, disable gbit v.regaddr := "01001"; elsif r.mdio_ctrl.data(5) = '1' then --auto neg completed v.regaddr := "00100"; elsif r.disableduplex = '1' then v.duplexstate := done; v.mdio_ctrl.busy := '0'; end if; when "00100" => v.duplexstate := start; v.regaddr := "00101"; v.capbil(4 downto 0) := r.mdio_ctrl.data(9 downto 5); when "00101" => v.duplexstate := selmode; v.capbil(4 downto 0) := r.capbil(4 downto 0) and r.mdio_ctrl.data(9 downto 5); when "01001" => if r.phywr = '0' then v.duplexstate := start; v.phywr := '1'; v.mdio_ctrl.data(9 downto 8) := (others => '0'); else v.regaddr := "00000"; v.duplexstate := start; v.phywr := '1'; v.mdio_ctrl.data := X"3300"; v.rstaneg := '1'; end if; when others => null; end case; when selmode => v.duplexstate := done; v.mdio_ctrl.busy := '0'; if r.phywr = '1' then v.ctrl.full_duplex := '0'; v.ctrl.speed := '0'; else sel_op_mode(r.capbil, v.ctrl.speed, v.ctrl.full_duplex); end if; when done => null; end case; end if; --transmitter retry if tmsti.retry = '1' then v.tmsto.req := '1'; v.tmsto.addr := r.tmsto.addr - 4; v.txburstcnt := r.txburstcnt - 1; end if; --transmitter AHB error if tmsti.error = '1' and (not ((edcl /= 0) and (r.tedcl = '1'))) then v.tmsto.req := '0'; v.txdstate := ahberror; end if; if (edclsepahbg /= 0) and (edcl /= 0) then --transmitter retry if tmsti2.retry = '1' then v.tmsto2.req := '1'; v.tmsto2.addr := r.tmsto2.addr - 4; v.txburstcnt := r.txburstcnt - 1; end if; --transmitter AHB error if tmsti2.error = '1' and (not ((edcl /= 0) and (r.tedcl = '1'))) then v.tmsto2.req := '0'; v.txdstate := ahberror; end if; end if; --receiver retry if rmsti.retry = '1' then v.rmsto.req := '1'; v.rmsto.addr := r.rmsto.addr - 4; v.rxburstcnt := r.rxburstcnt - 1; end if; ------------------------------------------------------------------------------ -- RESET ---------------------------------------------------------------------- ------------------------------------------------------------------------------- if irst = '0' then v.txdstate := idle; v.rxdstate := idle; v.rfrpnt := (others => '0'); v.tmsto.req := '0'; v.tmsto2.req := '0'; v.rfwpnt := (others => '0'); v.rfcnt := (others => '0'); v.ctrl.txen := '0'; v.txirqgen := '0'; v.ctrl.rxen := '0'; v.txdsel := (others => '0'); v.txstart_sync := '0'; v.txread := (others => '0'); v.txrestart := (others => '0'); v.txdone := (others => '0'); v.txreadack := '0'; v.rxdsel := (others => '0'); v.rxdone := (others => '0'); v.rxdoneold := '0'; v.rxdoneack := '0'; v.rxwriteack := '0'; v.rxstart := (others => '0'); v.rxwrite := (others => '0'); v.status.invaddr := '0'; v.status.toosmall := '0'; v.ctrl.full_duplex := '0'; v.writeok := '1'; if (enable_mdio = 0) or (edcl /= 0) then v.ctrl.reset := '0'; end if; if enable_mdint = 1 then v.status.phystat := '0'; v.ctrl.pstatirqen := '0'; end if; if (edcl /= 0) then v.tpnt := (others => '0'); v.rpnt := (others => '0'); v.tcnt := (others => '0'); v.edclactive := '0'; v.tarp := '0'; v.abufs := (others => '0'); v.edclrstate := idle; v.emacaddr := macaddrt; end if; if (rmii = 1) then v.ctrl.speed := '1'; end if; v.ctrl.tx_irqen := '0'; v.ctrl.rx_irqen := '0'; v.ctrl.prom := '0'; if multicast = 1 then v.ctrl.mcasten := '0'; end if; if ramdebug /= 0 then v.ctrl.ramdebugen := '0'; end if; end if; if edcl = 0 then v.edclrstate := idle; v.edclactive := '0'; v.nak := '0'; v.ewr := '0'; v.write := (others => '0'); v.seq := (others => '0'); v.abufs := (others => '0'); v.tpnt := (others => '0'); v.rpnt := (others => '0'); v.tcnt := (others => '0'); v.rcntm := (others => '0'); v.rcntl := (others => '0'); v.ipcrc := (others => '0'); v.applength := (others => '0'); v.oplen := (others => '0'); v.udpsrc := (others => '0'); v.ecnt := (others => '0'); v.tarp := '0'; v.tnak := '0'; v.tedcl := '0'; v.edclbcast := '0'; end if; --some parts of edcl are only affected by hw reset if rst = '0' then v.edclip := conv_std_logic_vector(ipaddrh, 16) & conv_std_logic_vector(ipaddrl, 16); if edcl > 1 then v.edclip(3 downto 0) := edcladdr; v.emacaddr(3 downto 0) := edcladdr; end if; v.duplexstate := start; v.regaddr := (others => '0'); v.phywr := '0'; v.rstphy := '1'; v.rstaneg := '0'; if phyrstadr /= 32 then v.mdio_ctrl.phyadr := conv_std_logic_vector(phyrstadr, 5); else v.mdio_ctrl.phyadr := phyrstaddr; end if; v.seq := (others => '0'); if (enable_mdio = 1) then v.mdccnt := divisor; v.mdioclk := '0'; end if; if edcl /= 0 then v.disableduplex := '0'; end if; if edcl = 3 then v.ctrl.edcldis := edcldisable; elsif edcl /= 0 then v.ctrl.edcldis := '0'; end if; v.ctrl.reset := '0'; if (enable_mdio = 1) then v.mdio_state := idle; v.mdio_ctrl.read := '0'; v.mdio_ctrl.write := '0'; v.mdio_ctrl.busy := '0'; v.mdio_ctrl.data := (others => '0'); v.mdio_ctrl.regadr := (others => '0'); v.ctrl.reset := '0'; v.mdio_ctrl.linkfail := '1'; if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if; v.cnt := (others => '0'); end if; if edclsepahbg /= 0 then v.edclsepahb := edclsepahb; end if; v.txcnt := (others => '0'); v.txburstcnt := (others => '0'); v.tedcl := '0'; v.erenable := '0'; v.rmsto.req := '0'; v.rmsto.write := '0'; v.addrok := '0'; v.rxburstcnt := (others => '0'); v.addrdone := '0'; v.rxcnt := (others => '0'); v.rxdoneold := '0'; v.ctrlpkt := '0'; v.bcast := '0'; v.edclactive := '0'; v.msbgood := '0'; v.rxrenable := '0'; if multicast = 1 then v.mcast := '0'; v.mcastacc := '0'; end if; v.tnak := '0'; v.tedcl := '0'; v.edclbcast := '0'; v.gotframe := '0'; v.rxbytecount := (others => '0'); v.rxlength := (others => '0'); v.txburstav := '0'; v.txdataav := '0'; v.txstatus := (others => '0'); v.txstart := '0'; v.tfcnt := (others => '0'); v.tfrpnt := (others => '0'); v.tfwpnt := (others => '0'); v.txaddr := (others => '0'); v.cnt := (others => '0'); v.rxaddr := (others => '0'); v.rxstatus := (others => '0'); v.rxwrap := '0'; v.rxden := '0'; v.rmsto.addr := (others => '0'); v.tmsto.addr := (others => '0'); v.nak := '0'; v.ewr := '0'; v.write := (others => '0'); v.applength := (others => '0'); v.oplen := (others => '0'); v.udpsrc := (others => '0'); v.ecnt := (others => '0'); v.rcntm := (others => '0'); v.rcntl := (others => '0'); end if; ------------------------------------------------------------------------------- -- SIGNAL ASSIGNMENTS --------------------------------------------------------- ------------------------------------------------------------------------------- rin <= v; prdata <= vprdata; irq <= vpirq; --rx ahb fifo rxrenable <= vrxfi.renable; rxraddress(10 downto fabits) <= (others => '0'); rxraddress(fabits-1 downto 0) <= vrxfi.raddress; rxwrite <= vrxfi.write; rxwdata <= vrxfi.datain; rxwaddress(10 downto fabits) <= (others => '0'); rxwaddress(fabits-1 downto 0) <= vrxfi.waddress; --tx ahb fifo txrenable <= vtxfi.renable; txraddress(10 downto txfabits) <= (others => '0'); txraddress(txfabits-1 downto 0) <= vtxfi.raddress; txwrite <= vtxfi.write; txwdata <= vtxfi.datain; txwaddress(10 downto txfabits) <= (others => '0'); txwaddress(txfabits-1 downto 0) <= vtxfi.waddress; --edcl buf erenable <= veri.renable; eraddress(15 downto eabits) <= (others => '0'); eraddress(eabits-1 downto 0) <= veri.raddress; ewritem <= veri.writem; ewritel <= veri.writel; ewaddressm(15 downto eabits) <= (others => '0'); ewaddressm(eabits-1 downto 0) <= veri.waddressm(eabits-1 downto 0); ewaddressl(15 downto eabits) <= (others => '0'); ewaddressl(eabits-1 downto 0) <= veri.waddressl(eabits-1 downto 0); ewdata <= veri.datain; rxi.enable <= vrxenable; end process; rxi.writeack <= r.rxwriteack; rxi.doneack <= r.rxdoneack; rxi.speed <= r.ctrl.speed; rxi.writeok <= r.writeok; rxi.rxd <= rxd; rxi.rx_dv <= rx_dv; rxi.rx_crs <= rx_crs; rxi.rx_er <= rx_er; txi.rx_col <= rx_col; txi.rx_crs <= rx_crs; txi.full_duplex <= r.ctrl.full_duplex; txi.start <= r.txstart_sync; txi.readack <= r.txreadack; txi.speed <= r.ctrl.speed; txi.data <= r.txdata; txi.valid <= r.txvalid; txi.len <= r.txlength; mdc <= r.mdioclk; mdio_o <= r.mdioo; mdio_oe <= testoen when (scanen/=0 and testen/='0') else r.mdioen; tmsto <= r.tmsto; rmsto <= r.rmsto; tmsto2 <= r.tmsto2; txd <= txo.txd; tx_en <= txo.tx_en; tx_er <= txo.tx_er; ahbmi.hgrant <= hgrant; ahbmi.hready <= hready; ahbmi.hresp <= hresp; ahbmi.hrdata <= hrdata; hbusreq <= ahbmo.hbusreq; hlock <= ahbmo.hlock; htrans <= ahbmo.htrans; haddr <= ahbmo.haddr; hwrite <= ahbmo.hwrite; hsize <= ahbmo.hsize; hburst <= ahbmo.hburst; hprot <= ahbmo.hprot; hwdata <= ahbmo.hwdata; ahbmi2.hgrant <= ehgrant; ahbmi2.hready <= ehready; ahbmi2.hresp <= ehresp; ahbmi2.hrdata <= ehrdata; ehbusreq <= ahbmo2.hbusreq; ehlock <= ahbmo2.hlock; ehtrans <= ahbmo2.htrans; ehaddr <= ahbmo2.haddr; ehwrite <= ahbmo2.hwrite; ehsize <= ahbmo2.hsize; ehburst <= ahbmo2.hburst; ehprot <= ahbmo2.hprot; ehwdata <= ahbmo2.hwdata; speed <= r.ctrl.speed; reset <= irst; regs : process(clk) is begin if rising_edge(clk) then r <= rin; end if; end process; ------------------------------------------------------------------------------- -- TRANSMITTER----------------------------------------------------------------- ------------------------------------------------------------------------------- tx_rmii0 : if rmii = 0 generate tx0: greth_tx generic map( ifg_gap => ifg_gap, attempt_limit => attempt_limit, backoff_limit => backoff_limit, nsync => nsync, rmii => rmii) port map( rst => arst, clk => tx_clk, txi => txi, txo => txo); end generate; tx_rmii1 : if rmii = 1 generate tx0: greth_tx generic map( ifg_gap => ifg_gap, attempt_limit => attempt_limit, backoff_limit => backoff_limit, nsync => nsync, rmii => rmii) port map( rst => arst, clk => rmii_clk, txi => txi, txo => txo); end generate; ------------------------------------------------------------------------------- -- RECEIVER ------------------------------------------------------------------- ------------------------------------------------------------------------------- rx_rmii0 : if rmii = 0 generate rx0 : greth_rx generic map( nsync => nsync, rmii => rmii, multicast => multicast, maxsize => maxsize) port map( rst => arst, clk => rx_clk, rxi => rxi, rxo => rxo); end generate; rx_rmii1 : if rmii = 1 generate rx0 : greth_rx generic map( nsync => nsync, rmii => rmii, multicast => multicast, maxsize => maxsize) port map( rst => arst, clk => rmii_clk, rxi => rxi, rxo => rxo); end generate; ------------------------------------------------------------------------------- -- AHB MST INTERFACE ---------------------------------------------------------- ------------------------------------------------------------------------------- ahb0 : eth_ahb_mst port map(rst, clk, ahbmi, ahbmo, tmsto, tmsti, rmsto, rmsti); edclmst : if edclsepahbg = 1 generate ahb1 : eth_edcl_ahb_mst port map(rst, clk, ahbmi2, ahbmo2, tmsto2, tmsti2); end generate; end architecture;
-- ------------------------------------------------------------- -- -- Entity Declaration for inst_eda_e -- -- Generated -- by: wig -- on: Mon Mar 22 13:27:43 2004 -- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_eda_e-e.vhd,v 1.1 2004/04/06 10:50:07 wig Exp $ -- $Date: 2004/04/06 10:50:07 $ -- $Log: inst_eda_e-e.vhd,v $ -- Revision 1.1 2004/04/06 10:50:07 wig -- Adding result/mde_tests -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp -- -- Generator: mix_0.pl Version: Revision: 1.26 , [email protected] -- (C) 2003 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity inst_eda_e -- entity inst_eda_e is -- Generics: -- No Generated Generics for Entity inst_eda_e -- Generated Port Declaration: port( -- Generated Port for Entity inst_eda_e cgs_ramclk : out std_ulogic; nreset : out std_ulogic; nreset_s : out std_ulogic; vclkl27 : out std_ulogic -- End of Generated Port for Entity inst_eda_e ); end inst_eda_e; -- -- End of Generated Entity inst_eda_e -- -- --!End of Entity/ies -- --------------------------------------------------------------
-- Automatically generated VHDL-93 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.MATH_REAL.ALL; use std.textio.all; use work.all; use work.packetprocessor_types.all; entity packetprocessor_blockram is port(rd : in unsigned(10 downto 0); wrm : in std_logic_vector(19 downto 0); -- clock system1000 : in std_logic; result : out unsigned(7 downto 0)); end; architecture structural of packetprocessor_blockram is signal x2 : unsigned(10 downto 0); signal wild2_app_arg : signed(63 downto 0); signal y : unsigned(7 downto 0); signal wild2 : signed(63 downto 0); signal x1 : packetprocessor_types.tup2_0; signal result_0 : signed(63 downto 0); signal wild_app_arg : signed(63 downto 0); signal case_alt : unsigned(7 downto 0); signal case_alt_0 : signed(63 downto 0); signal wild : signed(63 downto 0); signal app_arg : unsigned(7 downto 0); signal app_arg_0 : signed(63 downto 0); signal app_arg_1 : boolean; signal result_1 : signed(63 downto 0); begin -- blockRam begin packetprocessor_blockram_blockram : block signal ram : packetprocessor_types.array_of_unsigned_8(0 to 2047) := (packetprocessor_types.array_of_unsigned_8'(0 to 2048-1 => to_unsigned(0,8) )); signal dout : unsigned(7 downto 0); signal rd_0 : integer range 0 to 2048 - 1; signal wr : integer range 0 to 2048 - 1; begin rd_0 <= to_integer(result_1) -- pragma translate_off mod 2048 -- pragma translate_on ; wr <= to_integer(app_arg_0) -- pragma translate_off mod 2048 -- pragma translate_on ; blockram_sync : process(system1000) begin if rising_edge(system1000) then if app_arg_1 then ram(wr) <= app_arg; end if; dout <= ram(rd_0); end if; end process; result <= dout; end block; -- blockRam end x2 <= x1.tup2_0_sel0; wild2_app_arg <= signed(std_logic_vector(resize(x2,64))); y <= x1.tup2_0_sel1; wild2 <= wild2_app_arg; x1 <= (tup2_0_sel0 => unsigned(wrm(18 downto 8)) ,tup2_0_sel1 => unsigned(wrm(7 downto 0))); result_0 <= wild2; wild_app_arg <= signed(std_logic_vector(resize(rd,64))); case_alt <= y; case_alt_0 <= result_0; wild <= wild_app_arg; with (wrm(19 downto 19)) select app_arg <= unsigned'(0 to 7 => 'X') when "0", case_alt when others; with (wrm(19 downto 19)) select app_arg_0 <= signed'(0 to 63 => 'X') when "0", case_alt_0 when others; with (wrm(19 downto 19)) select app_arg_1 <= false when "0", true when others; result_1 <= wild; end;
-- Automatically generated VHDL-93 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.MATH_REAL.ALL; use std.textio.all; use work.all; use work.packetprocessor_types.all; entity packetprocessor_blockram is port(rd : in unsigned(10 downto 0); wrm : in std_logic_vector(19 downto 0); -- clock system1000 : in std_logic; result : out unsigned(7 downto 0)); end; architecture structural of packetprocessor_blockram is signal x2 : unsigned(10 downto 0); signal wild2_app_arg : signed(63 downto 0); signal y : unsigned(7 downto 0); signal wild2 : signed(63 downto 0); signal x1 : packetprocessor_types.tup2_0; signal result_0 : signed(63 downto 0); signal wild_app_arg : signed(63 downto 0); signal case_alt : unsigned(7 downto 0); signal case_alt_0 : signed(63 downto 0); signal wild : signed(63 downto 0); signal app_arg : unsigned(7 downto 0); signal app_arg_0 : signed(63 downto 0); signal app_arg_1 : boolean; signal result_1 : signed(63 downto 0); begin -- blockRam begin packetprocessor_blockram_blockram : block signal ram : packetprocessor_types.array_of_unsigned_8(0 to 2047) := (packetprocessor_types.array_of_unsigned_8'(0 to 2048-1 => to_unsigned(0,8) )); signal dout : unsigned(7 downto 0); signal rd_0 : integer range 0 to 2048 - 1; signal wr : integer range 0 to 2048 - 1; begin rd_0 <= to_integer(result_1) -- pragma translate_off mod 2048 -- pragma translate_on ; wr <= to_integer(app_arg_0) -- pragma translate_off mod 2048 -- pragma translate_on ; blockram_sync : process(system1000) begin if rising_edge(system1000) then if app_arg_1 then ram(wr) <= app_arg; end if; dout <= ram(rd_0); end if; end process; result <= dout; end block; -- blockRam end x2 <= x1.tup2_0_sel0; wild2_app_arg <= signed(std_logic_vector(resize(x2,64))); y <= x1.tup2_0_sel1; wild2 <= wild2_app_arg; x1 <= (tup2_0_sel0 => unsigned(wrm(18 downto 8)) ,tup2_0_sel1 => unsigned(wrm(7 downto 0))); result_0 <= wild2; wild_app_arg <= signed(std_logic_vector(resize(rd,64))); case_alt <= y; case_alt_0 <= result_0; wild <= wild_app_arg; with (wrm(19 downto 19)) select app_arg <= unsigned'(0 to 7 => 'X') when "0", case_alt when others; with (wrm(19 downto 19)) select app_arg_0 <= signed'(0 to 63 => 'X') when "0", case_alt_0 when others; with (wrm(19 downto 19)) select app_arg_1 <= false when "0", true when others; result_1 <= wild; end;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v6_3 Core - Synthesizable Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: bmg_tb_synth.vhd -- -- Description: -- Synthesizable Testbench -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_MISC.ALL; LIBRARY STD; USE STD.TEXTIO.ALL; LIBRARY unisim; USE unisim.vcomponents.ALL; LIBRARY work; USE work.ALL; USE work.BMG_TB_PKG.ALL; ENTITY BMG_TB IS PORT( CLK_IN : IN STD_LOGIC; CLKB_IN : IN STD_LOGIC; RESET_IN : IN STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA ); END ENTITY; ARCHITECTURE BMG_TB_ARCH OF BMG_TB IS COMPONENT RAM_WRITE_top PORT ( --Inputs - Port A WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(255 DOWNTO 0); DOUTA : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); CLKA : IN STD_LOGIC; --Inputs - Port B WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0); DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); CLKB : IN STD_LOGIC ); END COMPONENT; SIGNAL CLKA: STD_LOGIC := '0'; SIGNAL RSTA: STD_LOGIC := '0'; SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA: STD_LOGIC_VECTOR(255 DOWNTO 0) := (OTHERS => '0'); SIGNAL DOUTA: STD_LOGIC_VECTOR(255 DOWNTO 0); SIGNAL CLKB: STD_LOGIC := '0'; SIGNAL RSTB: STD_LOGIC := '0'; SIGNAL WEB: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRB: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINB: STD_LOGIC_VECTOR( 7 DOWNTO 0) := (OTHERS => '0'); SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL CHECKER_EN : STD_LOGIC:='0'; SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); SIGNAL clk_in_i: STD_LOGIC; SIGNAL RESET_SYNC_R1 : STD_LOGIC; SIGNAL RESET_SYNC_R2 : STD_LOGIC; SIGNAL RESET_SYNC_R3 : STD_LOGIC; SIGNAL clkb_in_i: STD_LOGIC; SIGNAL RESETB_SYNC_R1 : STD_LOGIC; SIGNAL RESETB_SYNC_R2 : STD_LOGIC; SIGNAL RESETB_SYNC_R3 : STD_LOGIC; SIGNAL ITER_R0 : STD_LOGIC := '0'; SIGNAL ITER_R1 : STD_LOGIC := '0'; SIGNAL ITER_R2 : STD_LOGIC := '0'; SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); BEGIN clk_buf: bufg PORT map( i => CLK_IN, o => clk_in_i ); CLKA <= clk_in_i; clkb_buf: bufg PORT map( i => CLKB_IN, o => clkb_in_i ); CLKB <= clkb_in_i; RSTA <= RESET_IN; PROCESS(clk_in_i) BEGIN IF(RISING_EDGE(clk_in_i)) THEN RESET_SYNC_R1 <= RESET_IN; RESET_SYNC_R2 <= RESET_SYNC_R1; RESET_SYNC_R3 <= RESET_SYNC_R2; END IF; END PROCESS; RSTB <= RESET_IN; PROCESS(clkb_in_i) BEGIN IF(RISING_EDGE(clkb_in_i)) THEN RESETB_SYNC_R1 <= RESET_IN; RESETB_SYNC_R2 <= RESETB_SYNC_R1; RESETB_SYNC_R3 <= RESETB_SYNC_R2; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ISSUE_FLAG_STATUS<= (OTHERS => '0'); ELSE ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; END IF; END IF; END PROCESS; STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; BMG_DATA_CHECKER_INST_A: ENTITY work.CHECKER GENERIC MAP ( WRITE_WIDTH => 256, READ_WIDTH => 256 ) PORT MAP ( CLK => CLKA, RST => RSTA, EN => CHECK_DATA_TDP(0), DATA_IN => DOUTA, STATUS => ISSUE_FLAG(0) ); BMG_DATA_CHECKER_INST_B: ENTITY work.CHECKER GENERIC MAP ( WRITE_WIDTH => 8, READ_WIDTH => 8 ) PORT MAP ( CLK => CLKB, RST => RSTB, EN => CHECK_DATA_TDP(1), DATA_IN => DOUTB, STATUS => ISSUE_FLAG(1) ); BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN PORT MAP( CLKA => CLKA, CLKB => CLKB, TB_RST => RSTA, ADDRA => ADDRA, DINA => DINA, WEA => WEA, WEB => WEB, ADDRB => ADDRB, DINB => DINB, CHECK_DATA => CHECK_DATA_TDP ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STATUS(8) <= '0'; iter_r2 <= '0'; iter_r1 <= '0'; iter_r0 <= '0'; ELSE STATUS(8) <= iter_r2; iter_r2 <= iter_r1; iter_r1 <= iter_r0; iter_r0 <= STIMULUS_FLOW(8); END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STIMULUS_FLOW <= (OTHERS => '0'); ELSIF(WEA(0)='1') THEN STIMULUS_FLOW <= STIMULUS_FLOW+1; END IF; END IF; END PROCESS; BMG_PORT: RAM_WRITE_top PORT MAP ( --Port A WEA => WEA, ADDRA => ADDRA, DINA => DINA, DOUTA => DOUTA, CLKA => CLKA, --Port B WEB => WEB, ADDRB => ADDRB, DINB => DINB, DOUTB => DOUTB, CLKB => CLKB ); END ARCHITECTURE;
------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package caph_processing_component is component dy_net port ( i_f: out std_logic; i: in std_logic_vector(9 downto 0); i_wr: in std_logic; o_e: out std_logic; o: out std_logic_vector(9 downto 0); o_rd: in std_logic; clock: in std_logic; reset: in std_logic ); end component; component conv33_port_net is port ( i_f: out std_logic; i: in std_logic_vector(9 downto 0); i_wr: in std_logic; k0_f: out std_logic; k0: in std_logic_vector(15 downto 0); k0_wr: in std_logic; k1_f: out std_logic; k1: in std_logic_vector(15 downto 0); k1_wr: in std_logic; k2_f: out std_logic; k2: in std_logic_vector(15 downto 0); k2_wr: in std_logic; k3_f: out std_logic; k3: in std_logic_vector(15 downto 0); k3_wr: in std_logic; k4_f: out std_logic; k4: in std_logic_vector(15 downto 0); k4_wr: in std_logic; k5_f: out std_logic; k5: in std_logic_vector(15 downto 0); k5_wr: in std_logic; k6_f: out std_logic; k6: in std_logic_vector(15 downto 0); k6_wr: in std_logic; k7_f: out std_logic; k7: in std_logic_vector(15 downto 0); k7_wr: in std_logic; k8_f: out std_logic; k8: in std_logic_vector(15 downto 0); k8_wr: in std_logic; n_f: out std_logic; n: in std_logic_vector(7 downto 0); n_wr: in std_logic; o_e: out std_logic; o: out std_logic_vector(9 downto 0); o_rd: in std_logic; clock: in std_logic; reset: in std_logic ); end component; component dx_net port ( w3_f: out std_logic; w3: in std_logic_vector(9 downto 0); w3_wr: in std_logic; w6_e: out std_logic; w6: out std_logic_vector(9 downto 0); w6_rd: in std_logic; clock: in std_logic; reset: in std_logic ); end component; component inv_net is port ( w3_f: out std_logic; w3: in std_logic_vector(9 downto 0); w3_wr: in std_logic; w6_e: out std_logic; w6: out std_logic_vector(9 downto 0); w6_rd: in std_logic; clock: in std_logic; reset: in std_logic ); end component; component conv_net is port ( w8_f: out std_logic; w8: in std_logic_vector(9 downto 0); w8_wr: in std_logic; w15_e: out std_logic; w15: out std_logic_vector(9 downto 0); w15_rd: in std_logic; clock: in std_logic; reset: in std_logic ); end component; component port_test_net port ( w4_f: out std_logic; w4: in std_logic_vector(9 downto 0); w4_wr: in std_logic; w6_f: out std_logic; w6: in std_logic_vector(7 downto 0); w6_wr: in std_logic; w9_e: out std_logic; w9: out std_logic_vector(9 downto 0); w9_rd: in std_logic; clock: in std_logic; reset: in std_logic ); end component; end caph_processing_component;
package STRSYN is attribute SigDir : string; attribute SigType : string; attribute SigBias : string; end STRSYN; entity op is port ( terminal in1: electrical; terminal in2: electrical; terminal out1: electrical; terminal vbias4: electrical; terminal gnd: electrical; terminal vdd: electrical; terminal vbias2: electrical; terminal vbias1: electrical; terminal vbias3: electrical); end op; architecture simple of op is -- Attributes for Ports attribute SigDir of in1:terminal is "input"; attribute SigType of in1:terminal is "voltage"; attribute SigDir of in2:terminal is "input"; attribute SigType of in2:terminal is "voltage"; attribute SigDir of out1:terminal is "output"; attribute SigType of out1:terminal is "voltage"; attribute SigDir of vbias4:terminal is "reference"; attribute SigType of vbias4:terminal is "voltage"; attribute SigDir of gnd:terminal is "reference"; attribute SigType of gnd:terminal is "current"; attribute SigBias of gnd:terminal is "negative"; attribute SigDir of vdd:terminal is "reference"; attribute SigType of vdd:terminal is "current"; attribute SigBias of vdd:terminal is "positive"; attribute SigDir of vbias2:terminal is "reference"; attribute SigType of vbias2:terminal is "voltage"; attribute SigDir of vbias1:terminal is "reference"; attribute SigType of vbias1:terminal is "voltage"; attribute SigDir of vbias3:terminal is "reference"; attribute SigType of vbias3:terminal is "voltage"; terminal net1: electrical; terminal net2: electrical; terminal net3: electrical; terminal net4: electrical; terminal net5: electrical; terminal net6: electrical; terminal net7: electrical; terminal net8: electrical; begin subnet0_subnet0_m1 : entity nmos(behave) generic map( L => Ldiff_0, W => Wdiff_0, scope => private ) port map( D => net2, G => in1, S => net4 ); subnet0_subnet0_m2 : entity nmos(behave) generic map( L => Ldiff_0, W => Wdiff_0, scope => private ) port map( D => net1, G => in2, S => net4 ); subnet0_subnet0_m3 : entity nmos(behave) generic map( L => LBias, W => W_0 ) port map( D => net4, G => vbias4, S => gnd ); subnet0_subnet0_m4 : entity nmos(behave) generic map( L => Ldiff_0, W => Wdiff_0, scope => private ) port map( D => net5, G => in1, S => net4 ); subnet0_subnet0_m5 : entity nmos(behave) generic map( L => Ldiff_0, W => Wdiff_0, scope => private ) port map( D => net5, G => in2, S => net4 ); subnet0_subnet0_m6 : entity pmos(behave) generic map( L => Lcmdiffp_0, W => Wcmdiffp_0, scope => private ) port map( D => net5, G => net5, S => vdd ); subnet0_subnet0_m7 : entity pmos(behave) generic map( L => Lcmdiffp_0, W => Wcmdiffp_0, scope => private ) port map( D => net5, G => net5, S => vdd ); subnet0_subnet0_m8 : entity pmos(behave) generic map( L => Lcmdiffp_0, W => Wcmdiffp_0, scope => private ) port map( D => net1, G => net5, S => vdd ); subnet0_subnet0_m9 : entity pmos(behave) generic map( L => Lcmdiffp_0, W => Wcmdiffp_0, scope => private ) port map( D => net2, G => net5, S => vdd ); subnet0_subnet1_m1 : entity nmos(behave) generic map( L => Lsrc, W => Wsrc_2, scope => Wprivate, symmetry_scope => sym_7 ) port map( D => net3, G => net1, S => gnd ); subnet0_subnet2_m1 : entity nmos(behave) generic map( L => Lsrc, W => Wsrc_2, scope => Wprivate, symmetry_scope => sym_7 ) port map( D => out1, G => net2, S => gnd ); subnet0_subnet3_m1 : entity pmos(behave) generic map( L => LBias, W => Wcmcasc_1, scope => Wprivate ) port map( D => net3, G => vbias2, S => net6 ); subnet0_subnet3_m2 : entity pmos(behave) generic map( L => Lcm_1, W => Wcm_1, scope => private ) port map( D => net6, G => net3, S => vdd ); subnet0_subnet3_m3 : entity pmos(behave) generic map( L => Lcm_1, W => Wcmout_1, scope => private ) port map( D => net7, G => net3, S => vdd ); subnet0_subnet3_m4 : entity pmos(behave) generic map( L => LBias, W => Wcmcasc_1, scope => Wprivate ) port map( D => out1, G => vbias2, S => net7 ); subnet1_subnet0_m1 : entity pmos(behave) generic map( L => LBias, W => (pfak)(WBias) ) port map( D => vbias1, G => vbias1, S => vdd ); subnet1_subnet0_m2 : entity pmos(behave) generic map( L => (pfak)(LBias), W => (pfak)(WBias) ) port map( D => vbias2, G => vbias2, S => vbias1 ); subnet1_subnet0_i1 : entity idc(behave) generic map( dc => 1.145e-05 ) port map( P => vdd, N => vbias3 ); subnet1_subnet0_m3 : entity nmos(behave) generic map( L => (pfak)(LBias), W => WBias ) port map( D => vbias3, G => vbias3, S => vbias4 ); subnet1_subnet0_m4 : entity nmos(behave) generic map( L => LBias, W => WBias ) port map( D => vbias2, G => vbias3, S => net8 ); subnet1_subnet0_m5 : entity nmos(behave) generic map( L => LBias, W => WBias ) port map( D => vbias4, G => vbias4, S => gnd ); subnet1_subnet0_m6 : entity nmos(behave) generic map( L => LBias, W => WBias ) port map( D => net8, G => vbias4, S => gnd ); end simple;
library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity shiftreg_nov is port( clock: in std_logic; input: in std_logic_vector(0 downto 0); output: out std_logic_vector(0 downto 0) ); end shiftreg_nov; architecture behaviour of shiftreg_nov is constant st0: std_logic_vector(2 downto 0) := "000"; constant st1: std_logic_vector(2 downto 0) := "100"; constant st2: std_logic_vector(2 downto 0) := "011"; constant st3: std_logic_vector(2 downto 0) := "111"; constant st4: std_logic_vector(2 downto 0) := "010"; constant st5: std_logic_vector(2 downto 0) := "110"; constant st6: std_logic_vector(2 downto 0) := "001"; constant st7: std_logic_vector(2 downto 0) := "101"; signal current_state, next_state: std_logic_vector(2 downto 0); begin process(clock) begin if rising_edge(clock) then current_state <= next_state; end if; end process; process(input, current_state) begin next_state <= "---"; output <= "-"; case current_state is when st0 => if std_match(input, "0") then next_state <= st0; output <= "0"; elsif std_match(input, "1") then next_state <= st4; output <= "0"; end if; when st1 => if std_match(input, "0") then next_state <= st0; output <= "1"; elsif std_match(input, "1") then next_state <= st4; output <= "1"; end if; when st2 => if std_match(input, "0") then next_state <= st1; output <= "0"; elsif std_match(input, "1") then next_state <= st5; output <= "0"; end if; when st3 => if std_match(input, "0") then next_state <= st1; output <= "1"; elsif std_match(input, "1") then next_state <= st5; output <= "1"; end if; when st4 => if std_match(input, "0") then next_state <= st2; output <= "0"; elsif std_match(input, "1") then next_state <= st6; output <= "0"; end if; when st5 => if std_match(input, "0") then next_state <= st2; output <= "1"; elsif std_match(input, "1") then next_state <= st6; output <= "1"; end if; when st6 => if std_match(input, "0") then next_state <= st3; output <= "0"; elsif std_match(input, "1") then next_state <= st7; output <= "0"; end if; when st7 => if std_match(input, "0") then next_state <= st3; output <= "1"; elsif std_match(input, "1") then next_state <= st7; output <= "1"; end if; when others => next_state <= "---"; output <= "-"; end case; end process; end behaviour;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.tl_flat_memory_model_pkg.all; use work.mem_bus_pkg.all; use work.cart_slot_pkg.all; use work.io_bus_pkg.all; use work.io_bus_bfm_pkg.all; use work.command_if_pkg.all; entity harness_v5 is end harness_v5; architecture tb of harness_v5 is constant c_uart_divisor : natural := 434; signal PHI2 : std_logic := '0'; signal RSTn : std_logic := 'H'; signal DOTCLK : std_logic := '1'; signal BUFFER_ENn : std_logic := '1'; signal BA : std_logic := '0'; signal DMAn : std_logic := '1'; signal EXROMn : std_logic; signal GAMEn : std_logic; signal ROMHn : std_logic := '1'; signal ROMLn : std_logic := '1'; signal IO1n : std_logic := '1'; signal IO2n : std_logic := '1'; signal IRQn : std_logic := '1'; signal NMIn : std_logic := '1'; signal SDRAM_CSn : std_logic; signal SDRAM_RASn : std_logic; signal SDRAM_CASn : std_logic; signal SDRAM_WEn : std_logic; signal SDRAM_CKE : std_logic; signal SDRAM_CLK : std_logic; signal SDRAM_DQM : std_logic; signal LB_ADDR : std_logic_vector(14 downto 0); signal LB_DATA : std_logic_vector(7 downto 0) := X"00"; signal logic_SDRAM_CSn : std_logic; signal logic_SDRAM_RASn : std_logic; signal logic_SDRAM_CASn : std_logic; signal logic_SDRAM_WEn : std_logic; signal logic_SDRAM_CKE : std_logic; signal logic_SDRAM_CLK : std_logic; signal logic_SDRAM_DQM : std_logic; signal logic_LB_ADDR : std_logic_vector(14 downto 0); signal PWM_OUT : std_logic_vector(1 downto 0); signal IEC_ATN : std_logic := '1'; signal IEC_DATA : std_logic := '1'; signal IEC_CLOCK : std_logic := '1'; signal IEC_RESET : std_logic := '1'; signal IEC_SRQ_IN : std_logic := '1'; signal DISK_ACTn : std_logic; -- activity LED signal CART_LEDn : std_logic; signal SDACT_LEDn : std_logic; signal MOTOR_LEDn : std_logic; signal UART_TXD : std_logic; signal UART_RXD : std_logic := '1'; signal SD_SSn : std_logic; signal SD_CLK : std_logic; signal SD_MOSI : std_logic; signal SD_MISO : std_logic := '1'; signal SD_WP : std_logic := '1'; signal SD_CARDDETn : std_logic := '1'; signal BUTTON : std_logic_vector(2 downto 0) := "000"; signal SLOT_ADDR : std_logic_vector(15 downto 0); signal SLOT_DATA : std_logic_vector(7 downto 0); signal RWn : std_logic := '1'; signal CAS_MOTOR : std_logic := '1'; signal CAS_SENSE : std_logic := '0'; signal CAS_READ : std_logic := '0'; signal CAS_WRITE : std_logic := '0'; signal RTC_CS : std_logic; signal RTC_SCK : std_logic; signal RTC_MOSI : std_logic; signal RTC_MISO : std_logic := '1'; signal FLASH_CSn : std_logic; signal FLASH_SCK : std_logic; signal FLASH_MOSI : std_logic; signal FLASH_MISO : std_logic := '1'; signal ULPI_CLOCK : std_logic := '0'; signal ULPI_RESET : std_logic := '0'; signal ULPI_NXT : std_logic := '0'; signal ULPI_STP : std_logic; signal ULPI_DIR : std_logic := '0'; signal ULPI_DATA : std_logic_vector(7 downto 0) := (others => 'H'); signal sys_clock : std_logic := '0'; signal sys_reset : std_logic := '0'; signal sys_shifted : std_logic := '0'; signal rx_char : std_logic_vector(7 downto 0); signal rx_char_d : std_logic_vector(7 downto 0); signal rx_ack : std_logic; signal tx_char : std_logic_vector(7 downto 0) := X"00"; signal tx_done : std_logic; signal do_tx : std_logic := '0'; shared variable dram : h_mem_object; shared variable ram : h_mem_object; -- shared variable rom : h_mem_object; -- shared variable bram : h_mem_object; -- memory controller interconnect signal memctrl_inhibit : std_logic := '0'; signal mem_req : t_mem_req; signal mem_resp : t_mem_resp; signal mem_req_cached : t_mem_burst_req; signal mem_resp_cached : t_mem_burst_resp; signal io_req : t_io_req; signal io_resp : t_io_resp; -- cache monitoring signal hit_count : unsigned(31 downto 0); signal miss_count : unsigned(31 downto 0); signal hit_ratio : real := 0.0; begin mut: entity work.ultimate_logic generic map ( g_simulation => true, g_uart => true, g_drive_1541 => true, g_drive_1541_2 => true, g_hardware_gcr => true, g_cartridge => true, g_command_intf => true, g_stereo_sid => true, g_ram_expansion => true, g_extended_reu => true, g_hardware_iec => true, g_c2n_streamer => true, g_c2n_recorder => true, g_drive_sound => true, g_rtc_chip => true, g_rtc_timer => true, g_usb_host => true, g_spi_flash => true ) port map ( sys_clock => sys_clock, sys_reset => sys_reset, PHI2 => PHI2, DOTCLK => DOTCLK, RSTn => RSTn, BUFFER_ENn => BUFFER_ENn, SLOT_ADDR => SLOT_ADDR, SLOT_DATA => SLOT_DATA, RWn => RWn, BA => BA, DMAn => DMAn, EXROMn => EXROMn, GAMEn => GAMEn, ROMHn => ROMHn, ROMLn => ROMLn, IO1n => IO1n, IO2n => IO2n, IRQn => IRQn, NMIn => NMIn, -- local bus side mem_inhibit => memctrl_inhibit, --memctrl_idle => memctrl_idle, mem_req => mem_req, mem_resp => mem_resp, -- io bus for simulation sim_io_req => io_req, sim_io_resp => io_resp, -- PWM outputs (for audio) PWM_OUT => PWM_OUT, -- IEC bus IEC_ATN => IEC_ATN, IEC_DATA => IEC_DATA, IEC_CLOCK => IEC_CLOCK, IEC_RESET => IEC_RESET, IEC_SRQ_IN => IEC_SRQ_IN, DISK_ACTn => DISK_ACTn, -- activity LED CART_LEDn => CART_LEDn, SDACT_LEDn => SDACT_LEDn, MOTOR_LEDn => MOTOR_LEDn, -- Debug UART UART_TXD => UART_TXD, UART_RXD => UART_RXD, -- SD Card Interface SD_SSn => SD_SSn, SD_CLK => SD_CLK, SD_MOSI => SD_MOSI, SD_MISO => SD_MISO, SD_CARDDETn => SD_CARDDETn, -- Cassette Interface CAS_MOTOR => CAS_MOTOR, CAS_SENSE => CAS_SENSE, CAS_READ => CAS_READ, CAS_WRITE => CAS_WRITE, -- RTC Interface RTC_CS => RTC_CS, RTC_SCK => RTC_SCK, RTC_MOSI => RTC_MOSI, RTC_MISO => RTC_MISO, -- Flash Interface FLASH_CSn => FLASH_CSn, FLASH_SCK => FLASH_SCK, FLASH_MOSI => FLASH_MOSI, FLASH_MISO => FLASH_MISO, -- USB Interface (ULPI) ULPI_CLOCK => ULPI_CLOCK, ULPI_RESET => ULPI_RESET, ULPI_NXT => ULPI_NXT, ULPI_STP => ULPI_STP, ULPI_DIR => ULPI_DIR, ULPI_DATA => ULPI_DATA, -- Buttons BUTTON => BUTTON ); i_cache: entity work.dm_cache port map ( clock => sys_clock, reset => sys_reset, client_req => mem_req, client_resp => mem_resp, mem_req => mem_req_cached, mem_resp => mem_resp_cached, hit_count => hit_count, miss_count => miss_count ); hit_ratio <= real(to_integer(hit_count)) / real(to_integer(miss_count) + to_integer(hit_count) + 1); i_memctrl: entity work.ext_mem_ctrl_v5_sdr generic map ( g_simulation => true, A_Width => 15 ) port map ( clock => sys_clock, clk_shifted => sys_shifted, reset => sys_reset, inhibit => '0', --memctrl_inhibit, is_idle => open, --memctrl_idle, req => mem_req_cached, resp => mem_resp_cached, SDRAM_CSn => logic_SDRAM_CSn, SDRAM_RASn => logic_SDRAM_RASn, SDRAM_CASn => logic_SDRAM_CASn, SDRAM_WEn => logic_SDRAM_WEn, SDRAM_CKE => logic_SDRAM_CKE, SDRAM_CLK => logic_SDRAM_CLK, MEM_A => logic_LB_ADDR, MEM_D => LB_DATA ); -- clock to out.. for data it is inside of the memory controller, because it's bidirectional SDRAM_CSn <= transport logic_SDRAM_CSn after 4.9 ns; SDRAM_RASn <= transport logic_SDRAM_RASn after 4.9 ns; SDRAM_CASn <= transport logic_SDRAM_CASn after 4.9 ns; SDRAM_WEn <= transport logic_SDRAM_WEn after 4.9 ns; SDRAM_CKE <= transport logic_SDRAM_CKE after 4.9 ns; SDRAM_CLK <= transport logic_SDRAM_CLK after 4.9 ns; LB_ADDR <= transport logic_LB_ADDR after 4.9 ns; sys_clock <= not sys_clock after 10 ns; -- 50 MHz sys_reset <= '1', '0' after 100 ns; sys_shifted <= transport sys_clock after 15 ns; -- 270 degrees ULPI_CLOCK <= not ULPI_CLOCK after 8.333 ns; -- 60 MHz ULPI_RESET <= '1', '0' after 100 ns; PHI2 <= not PHI2 after 507.5 ns; -- 0.98525 MHz RSTn <= '0', 'H' after 6 us, '0' after 100 us, 'H' after 105 us; i_ulpi_phy: entity work.ulpi_phy_bfm generic map ( g_rx_interval => 100000 ) port map ( clock => ULPI_CLOCK, reset => ULPI_RESET, ULPI_DATA => ULPI_DATA, ULPI_DIR => ULPI_DIR, ULPI_NXT => ULPI_NXT, ULPI_STP => ULPI_STP ); i_io_bfm: entity work.io_bus_bfm generic map ( g_name => "io_bfm" ) port map ( clock => sys_clock, req => io_req, resp => io_resp ); process begin bind_mem_model("intram", ram); bind_mem_model("dram", dram); load_memory("../../software/1st_boot/result/1st_boot.bin", ram, X"00000000"); -- 1st boot will try to load the 2nd bootloader and application from flash. In simulation this is a cumbersome -- process. It would work with a good model of the serial spi flash, but since it is not included in the public -- archive, you need to create a special boot image that just jumps to 0x20000 and load the application here to dram: load_memory("../../software/ultimate/result/ultimate.bin", dram, X"00020000"); wait; end process; SLOT_DATA <= (others => 'H'); ROMHn <= '1'; ROMLn <= not PHI2 after 50 ns; IO1n <= '1'; IO2n <= '1'; process begin SLOT_ADDR <= X"D400"; RWn <= '1'; while true loop wait until PHI2 = '0'; --SLOT_ADDR(8 downto 0) <= std_logic_vector(unsigned(SLOT_ADDR(8 downto 0)) + 1); SLOT_ADDR <= std_logic_vector(unsigned(SLOT_ADDR) + 1); RWn <= '1'; wait until PHI2 = '0'; RWn <= '0'; end loop; end process; process begin BA <= '1'; for i in 0 to 100 loop wait until PHI2='0'; end loop; BA <= '0'; for i in 0 to 10 loop wait until PHI2='0'; end loop; end process; dram_bfm: entity work.dram_model_8 generic map( g_given_name => "dram", g_cas_latency => 2, g_burst_len_r => 4, g_burst_len_w => 4, g_column_bits => 10, g_row_bits => 13, g_bank_bits => 2 ) port map ( CLK => SDRAM_CLK, CKE => SDRAM_CKE, A => LB_ADDR(12 downto 0), BA => LB_ADDR(14 downto 13), CSn => SDRAM_CSn, RASn => SDRAM_RASn, CASn => SDRAM_CASn, WEn => SDRAM_WEn, DQM => SDRAM_DQM, DQ => LB_DATA); i_rx: entity work.rx generic map (c_uart_divisor) port map ( clk => sys_clock, reset => sys_reset, rxd => UART_TXD, rxchar => rx_char, rx_ack => rx_ack ); i_tx: entity work.tx generic map (c_uart_divisor) port map ( clk => sys_clock, reset => sys_reset, dotx => do_tx, txchar => tx_char, done => tx_done, txd => UART_RXD ); process(sys_clock) begin if rising_edge(sys_clock) then if rx_ack='1' then rx_char_d <= rx_char; end if; end if; end process; -- procedure register_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object); -- procedure bind_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object); -- procedure io_read(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0)); -- procedure io_write(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0)); -- constant c_cart_c64_mode : unsigned(3 downto 0) := X"0"; -- constant c_cart_c64_stop : unsigned(3 downto 0) := X"1"; -- constant c_cart_c64_stop_mode : unsigned(3 downto 0) := X"2"; -- constant c_cart_c64_clock_detect : unsigned(3 downto 0) := X"3"; -- constant c_cart_cartridge_rom_base : unsigned(3 downto 0) := X"4"; -- constant c_cart_cartridge_type : unsigned(3 downto 0) := X"5"; -- constant c_cart_cartridge_kill : unsigned(3 downto 0) := X"6"; -- constant c_cart_reu_enable : unsigned(3 downto 0) := X"8"; -- constant c_cart_reu_size : unsigned(3 downto 0) := X"9"; -- constant c_cart_swap_buttons : unsigned(3 downto 0) := X"A"; -- constant c_cart_ethernet_enable : unsigned(3 downto 0) := X"F"; process variable io : p_io_bus_bfm_object; begin wait until sys_reset='0'; wait until sys_clock='1'; bind_io_bus_bfm("io_bfm", io); io_write(io, X"40000" + c_cart_c64_mode, X"04"); -- reset io_write(io, X"40000" + c_cart_cartridge_type, X"06"); -- retro io_write(io, X"40000" + c_cart_c64_mode, X"08"); -- unreset io_write(io, X"44000" + c_cif_io_slot_base, X"7E"); io_write(io, X"44000" + c_cif_io_slot_enable, X"01"); wait for 6 us; wait until sys_clock='1'; io_write(io, X"42002", X"42"); wait; end process; process procedure send_char(i: std_logic_vector(7 downto 0)) is begin if tx_done /= '1' then wait until tx_done = '1'; end if; wait until sys_clock='1'; tx_char <= i; do_tx <= '1'; wait until tx_done = '0'; wait until sys_clock='1'; do_tx <= '0'; end procedure; procedure send_string(i : string) is variable b : std_logic_vector(7 downto 0); begin for n in i'range loop b := std_logic_vector(to_unsigned(character'pos(i(n)), 8)); send_char(b); end loop; send_char(X"0d"); send_char(X"0a"); end procedure; begin wait for 2 ms; --send_string("wd 4005000 12345678"); send_string("run"); -- send_string("m 100000"); -- send_string("w 400000F 4"); wait; end process; -- check timing data process(PHI2) begin if falling_edge(PHI2) then assert SLOT_DATA'last_event >= 189 ns report "Timing error on C64 bus." severity error; end if; end process; end tb;
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity D6_C1 is port( rst : in STD_LOGIC; sel : in STD_LOGIC; clk : in STD_LOGIC; seg1 : out STD_LOGIC_VECTOR(7 downto 0);--hang don vi seg2 : out STD_LOGIC_VECTOR(7 downto 0)--hang chuc ); end D6_C1; architecture D6_C1 of D6_C1 is begin process(rst,clk,sel) variable temp1:integer range 0 to 10; variable temp2:integer range 0 to 10; begin if (rst='1') then temp1:=0; temp2:=0; elsif (rising_edge(clk)) then if (sel='1') then if (temp1=10) then temp1:=0; temp2:=temp2+1; if (temp2=10) then temp2:=0; end if; else temp1:=temp1+1; end if; elsif (sel='0') then if(temp1=0) then temp1:=9; temp2:=temp2-1; if (temp2=0) then temp2:=9; end if; else temp1:=temp1-1; end if; end if; end if; case temp1 is when 0 => seg1<= x"C0"; when 1 => seg1<= x"F9"; when 2 => seg1<= x"A4"; when 3 => seg1<= x"B0"; when 4 => seg1<= x"99"; when 5 => seg1<= x"92"; when 6 => seg1<= x"82"; when 7 => seg1<= x"F8"; when 8 => seg1<= x"80"; when 9 => seg1<= x"90"; when others =>NULL; end case; case temp2 is when 0 => seg2<= x"C0"; when 1 => seg2<= x"F9"; when 2 => seg2<= x"A4"; when 3 => seg2<= x"B0"; when 4 => seg2<= x"99"; when 5 => seg2<= x"92"; when 6 => seg2<= x"82"; when 7 => seg2<= x"F8"; when 8 => seg2<= x"80"; when 9 => seg2<= x"90"; when others =>NULL; end case; end process; end D6_C1; -- rst= 10kHz; sel=50Khz; clk=20Mhz;
------------------------------------------------------------------------------- -- Title : Commutation control via Hall sensors ------------------------------------------------------------------------------- -- Author : Fabian Greif <[email protected]> -- Company : Roboterclub Aachen e.V. -- Platform : Spartan 3 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.motor_control_pkg.all; package commutation_pkg is component commutation is port ( driver_stage_p : out bldc_driver_stage_type; hall_p : in hall_sensor_type; pwm_p : in half_bridge_type; dir_p : in std_logic; sd_p : in std_logic; clk : in std_logic); end component commutation; end commutation_pkg; ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.commutation_pkg.all; use work.motor_control_pkg.all; entity commutation is port ( driver_stage_p : out bldc_driver_stage_type; -- Driver Stage of 3 half bridges hall_p : in hall_sensor_type; -- Hall Sensors pwm_p : in half_bridge_type; dir_p : in std_logic; -- Direction sd_p : in std_logic; -- Shutdown clk : in std_logic ); end commutation; architecture behavioral of commutation is type commutation_type is record hall_1r : std_logic_vector(2 downto 0); hall_2r : std_logic_vector(2 downto 0); driver : bldc_driver_stage_type; end record; signal r, rin : commutation_type; begin seq_proc : process(clk) begin if rising_edge(clk) then r <= rin; end if; end process seq_proc; comb_proc : process(dir_p, hall_p.a, hall_p.b, hall_p.c, pwm_p.high, pwm_p.low, r, r.hall_1r, r.hall_2r, r.driver.a.high, r.driver.a.low, r.driver.b.high, r.driver.b.low, r.driver.c.high, r.driver.c.low, sd_p) variable v : commutation_type; variable index : integer range 0 to 6; begin v := r; -- synchronise Hall sensors inputs v.hall_1r := hall_p.a & hall_p.b & hall_p.c; v.hall_2r := r.hall_1r; if dir_p = '0' then case r.hall_2r is when "101" => index := 1; when "100" => index := 2; when "110" => index := 3; when "010" => index := 4; when "011" => index := 5; when "001" => index := 6; when others => index := 0; end case; else case r.hall_2r is when "101" => index := 4; when "100" => index := 5; when "110" => index := 6; when "010" => index := 1; when "011" => index := 2; when "001" => index := 3; when others => index := 0; end case; end if; case index is when 1 => v.driver := (a => (pwm_p.high, pwm_p.low), b => ('0', '1'), c => ('0', '0')); when 2 => v.driver := (a => (pwm_p.high, pwm_p.low), b => ('0', '0'), c => ('0', '1')); when 3 => v.driver := (a => ('0', '0'), b => (pwm_p.high, pwm_p.low), c => ('0', '1')); when 4 => v.driver := (a => ('0', '1'), b => (pwm_p.high, pwm_p.low), c => ('0', '0')); when 5 => v.driver := (a => ('0', '1'), b => ('0', '0'), c => (pwm_p.high, pwm_p.low)); when 6 => v.driver := (a => ('0', '0'), b => ('0', '1'), c => (pwm_p.high, pwm_p.low)); when others => -- Error in the readings of the Hall-Sensors => Disable PWM v.driver := (a => ('0', '0'), b => ('0', '0'), c => ('0', '0')); end case; if sd_p = '1' then v.driver := (a => ('0', '0'), b => ('0', '0'), c => ('0', '0')); end if; rin <= v; end process comb_proc; driver_stage_p <= r.driver; end behavioral;
------------------------------------------------------------------------------- -- Title : Commutation control via Hall sensors ------------------------------------------------------------------------------- -- Author : Fabian Greif <[email protected]> -- Company : Roboterclub Aachen e.V. -- Platform : Spartan 3 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.motor_control_pkg.all; package commutation_pkg is component commutation is port ( driver_stage_p : out bldc_driver_stage_type; hall_p : in hall_sensor_type; pwm_p : in half_bridge_type; dir_p : in std_logic; sd_p : in std_logic; clk : in std_logic); end component commutation; end commutation_pkg; ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.commutation_pkg.all; use work.motor_control_pkg.all; entity commutation is port ( driver_stage_p : out bldc_driver_stage_type; -- Driver Stage of 3 half bridges hall_p : in hall_sensor_type; -- Hall Sensors pwm_p : in half_bridge_type; dir_p : in std_logic; -- Direction sd_p : in std_logic; -- Shutdown clk : in std_logic ); end commutation; architecture behavioral of commutation is type commutation_type is record hall_1r : std_logic_vector(2 downto 0); hall_2r : std_logic_vector(2 downto 0); driver : bldc_driver_stage_type; end record; signal r, rin : commutation_type; begin seq_proc : process(clk) begin if rising_edge(clk) then r <= rin; end if; end process seq_proc; comb_proc : process(dir_p, hall_p.a, hall_p.b, hall_p.c, pwm_p.high, pwm_p.low, r, r.hall_1r, r.hall_2r, r.driver.a.high, r.driver.a.low, r.driver.b.high, r.driver.b.low, r.driver.c.high, r.driver.c.low, sd_p) variable v : commutation_type; variable index : integer range 0 to 6; begin v := r; -- synchronise Hall sensors inputs v.hall_1r := hall_p.a & hall_p.b & hall_p.c; v.hall_2r := r.hall_1r; if dir_p = '0' then case r.hall_2r is when "101" => index := 1; when "100" => index := 2; when "110" => index := 3; when "010" => index := 4; when "011" => index := 5; when "001" => index := 6; when others => index := 0; end case; else case r.hall_2r is when "101" => index := 4; when "100" => index := 5; when "110" => index := 6; when "010" => index := 1; when "011" => index := 2; when "001" => index := 3; when others => index := 0; end case; end if; case index is when 1 => v.driver := (a => (pwm_p.high, pwm_p.low), b => ('0', '1'), c => ('0', '0')); when 2 => v.driver := (a => (pwm_p.high, pwm_p.low), b => ('0', '0'), c => ('0', '1')); when 3 => v.driver := (a => ('0', '0'), b => (pwm_p.high, pwm_p.low), c => ('0', '1')); when 4 => v.driver := (a => ('0', '1'), b => (pwm_p.high, pwm_p.low), c => ('0', '0')); when 5 => v.driver := (a => ('0', '1'), b => ('0', '0'), c => (pwm_p.high, pwm_p.low)); when 6 => v.driver := (a => ('0', '0'), b => ('0', '1'), c => (pwm_p.high, pwm_p.low)); when others => -- Error in the readings of the Hall-Sensors => Disable PWM v.driver := (a => ('0', '0'), b => ('0', '0'), c => ('0', '0')); end case; if sd_p = '1' then v.driver := (a => ('0', '0'), b => ('0', '0'), c => ('0', '0')); end if; rin <= v; end process comb_proc; driver_stage_p <= r.driver; end behavioral;
------------------------------------------------------------------------------- --! @file ab.vhd --! @author Johannes Walter <[email protected]> --! @copyright CERN TE-EPC-CCE --! @date 2014-07-08 --! @brief Analogue board control and filters. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.ab_pkg.all; use work.nf_pkg.all; use work.ads1281_filter_pkg.all; --! @brief Entity declaration of ab --! @details --! This component controls the analogue board switches, DAC and ADCs. It --! also provides FIR filter implementations for the ADCs and has an internal --! pattern generator for test purposes. entity ab is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Analogue board interface --! @{ --! Inputs ab_i : in ab_in_t; --! Outputs ab_o : out ab_out_t; --! @} --! @name Internal interface --! @{ --! Millisecond strobe ms_strobe_i : in std_ulogic; --! Millisecond strobe indicating start of cycle ms_0_strobe_i : in std_ulogic; --! Commands command_i : in nf_command_t; --! SEFI detector sefi_o : out std_ulogic_vector(5 downto 0); --! Voltage reference when ramping down pf_vref_i : in std_ulogic_vector(15 downto 0); --! Voltage reference enable pf_vref_en_i : in std_ulogic; --! Voltage reference override pf_vref_ovr_i : in std_ulogic; --! @} --! @name ADC results --! @{ --! ADC VS result adc_vs_o : out std_ulogic_vector(23 downto 0); --! ADC VS result enable adc_vs_en_o : out std_ulogic; --! ADC IA result adc_ia_o : out std_ulogic_vector(23 downto 0); --! ADC IA result enable adc_ia_en_o : out std_ulogic; --! ADC IB result adc_ib_o : out std_ulogic_vector(23 downto 0); --! ADC IB result enable adc_ib_en_o : out std_ulogic; --! @} --! @name Accumulator results --! @{ --! Accumulator VS result acc_vs_o : out std_ulogic_vector(31 downto 0); --! Accumulator VS result enable acc_vs_en_o : out std_ulogic; --! Accumulator IA result acc_ia_o : out std_ulogic_vector(31 downto 0); --! Accumulator IA result enable acc_ia_en_o : out std_ulogic; --! Accumulator IB result acc_ib_o : out std_ulogic_vector(31 downto 0); --! Accumulator IB result enable acc_ib_en_o : out std_ulogic); --! @} end entity ab; --! RTL implementation of ab architecture rtl of ab is --------------------------------------------------------------------------- --! @name Types and Constants --------------------------------------------------------------------------- --! @{ type acc_result_t is array (0 to 2) of std_ulogic_vector(27 downto 0); type sefi_mode_t is array (0 to 5) of std_ulogic_vector(1 downto 0); --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal adc_m0 : std_ulogic_vector(2 downto 0); signal adc_m1 : std_ulogic_vector(2 downto 0); signal adc_result : ads1281_filter_result_t; signal adc_result_en : std_ulogic_vector(2 downto 0); signal acc_result : acc_result_t; signal acc_result_en : std_ulogic_vector(2 downto 0); signal ab : ab_out_t; signal sample_strb : std_ulogic; signal adc_m : std_ulogic_vector(5 downto 0); signal sefi_in : std_ulogic_vector(5 downto 0); signal sefi_mode : sefi_mode_t; signal vref : std_ulogic_vector(15 downto 0); signal vref_en : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- -- Power up analogue board ab_o.pwr_on_n <= '0'; -- Start temperature control on analogue board ab_o.temp_stop <= '0'; ab_o.cal_dac <= ab.cal_dac; ab_o.cal_offset <= ab.cal_offset; ab_o.cal_vref_p <= ab.cal_vref_p; ab_o.cal_vref_n <= ab.cal_vref_n; ab_o.adc_vs_rst_n <= ab.adc_vs_rst_n; ab_o.sw_in_vs <= ab.sw_in_vs; ab_o.adc_a_rst_n <= ab.adc_a_rst_n; ab_o.sw_in_a <= ab.sw_in_a; ab_o.adc_b_rst_n <= ab.adc_b_rst_n; ab_o.sw_in_b <= ab.sw_in_b; adc_vs_o <= adc_result(0); adc_vs_en_o <= adc_result_en(0); adc_ia_o <= adc_result(1); adc_ia_en_o <= adc_result_en(1); adc_ib_o <= adc_result(2); adc_ib_en_o <= adc_result_en(2); acc_vs_o(31 downto 28) <= (31 downto 28 => acc_result(0)(acc_result(0)'high)); acc_vs_o(27 downto 0) <= acc_result(0); acc_vs_en_o <= acc_result_en(0); acc_ia_o(31 downto 28) <= (31 downto 28 => acc_result(1)(acc_result(1)'high)); acc_ia_o(27 downto 0) <= acc_result(1); acc_ia_en_o <= acc_result_en(1); acc_ib_o(31 downto 28) <= (31 downto 28 => acc_result(2)(acc_result(2)'high)); acc_ib_o(27 downto 0) <= acc_result(2); acc_ib_en_o <= acc_result_en(2); --------------------------------------------------------------------------- -- Signal Assignments --------------------------------------------------------------------------- adc_m0 <= ab_i.adc_vs(0) & ab_i.adc_a(0) & ab_i.adc_b(0); adc_m1 <= ab_i.adc_vs(1) & ab_i.adc_a(1) & ab_i.adc_b(1); adc_m <= ab_i.adc_b & ab_i.adc_a & ab_i.adc_vs; sefi_mode(0) <= command_i.sefi_test_vs_m0; sefi_mode(1) <= command_i.sefi_test_vs_m1; sefi_mode(2) <= command_i.sefi_test_ia_m0; sefi_mode(3) <= command_i.sefi_test_ia_m1; sefi_mode(4) <= command_i.sefi_test_ib_m0; sefi_mode(5) <= command_i.sefi_test_ib_m1; vref <= pf_vref_i when pf_vref_ovr_i = '1' else command_i.v_ref; vref_en <= pf_vref_en_i when pf_vref_ovr_i = '1' else ms_0_strobe_i; --------------------------------------------------------------------------- -- Instances --------------------------------------------------------------------------- --! SEFI detector test sefi_test_gen : for i in 0 to 5 generate sefi_test_inst : entity work.sefi_detector_test port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, ms_0_strobe_i => ms_0_strobe_i, en_i => command_i.vs_cmd(0), mode_i => sefi_mode(i), strb_i => sample_strb, adc_i => adc_m(i), test_o => sefi_in(i)); end generate sefi_test_gen; --! SEFI detectors sefi_detector_gen : for i in 0 to 5 generate sefi_detector_inst : entity work.sefi_detector generic map ( num_g => 30) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => ms_0_strobe_i, en_i => sample_strb, sig_i => sefi_in(i), sefi_o => sefi_o(i)); end generate sefi_detector_gen; --! Analogue board DAC interface max5541_interface_inst : entity work.max5541_interface port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, data_i => vref, data_en_i => vref_en, busy_o => open, done_o => open, cs_o => ab_o.dac_cs, sclk_o => ab_o.dac_sclk, din_o => ab_o.dac_din); --! ADS1281 filter ads1281_filter_inst : entity work.ads1281_filter port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, strb_ms_i => ms_strobe_i, strb_sample_o => sample_strb, adc_m0_i => adc_m0, adc_m1_i => adc_m1, result_o => adc_result, result_en_o => adc_result_en); --! ADS1281 result accumulator ads1281_result_accumulator_gen : for i in 0 to 2 generate ads1281_result_accumulator_inst : entity work.ads1281_result_accumulator generic map ( num_results_g => 10) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => ms_0_strobe_i, result_i => adc_result(i), result_en_i => adc_result_en(i), result_o => acc_result(i), result_en_o => acc_result_en(i)); end generate ads1281_result_accumulator_gen; --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin ab.cal_dac <= '0'; ab.cal_offset <= '0'; ab.cal_vref_p <= '0'; ab.cal_vref_n <= '0'; ab.adc_vs_rst_n <= '1'; ab.sw_in_vs <= '0'; ab.adc_a_rst_n <= '1'; ab.sw_in_a <= '0'; ab.adc_b_rst_n <= '1'; ab.sw_in_b <= '0'; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; elsif ms_0_strobe_i = '1' then case command_i.cal_source is when "00" => ab.cal_dac <= '0'; ab.cal_offset <= '1'; ab.cal_vref_n <= '0'; ab.cal_vref_p <= '0'; when "01" => ab.cal_dac <= '0'; ab.cal_offset <= '0'; ab.cal_vref_n <= '0'; ab.cal_vref_p <= '1'; when "10" => ab.cal_dac <= '0'; ab.cal_offset <= '0'; ab.cal_vref_n <= '1'; ab.cal_vref_p <= '0'; when "11" => ab.cal_dac <= '1'; ab.cal_offset <= '0'; ab.cal_vref_n <= '0'; ab.cal_vref_p <= '0'; when others => null; end case; ab.adc_vs_rst_n <= command_i.adc_vs_reset_n; ab.adc_a_rst_n <= command_i.adc_ia_reset_n; ab.adc_b_rst_n <= command_i.adc_ib_reset_n; if command_i.vs_cmd(0) = '0' then ab.sw_in_vs <= command_i.cal_vs_en; ab.sw_in_a <= command_i.cal_ia_en; ab.sw_in_b <= command_i.cal_ib_en; else ab.sw_in_vs <= '0'; ab.sw_in_a <= '0'; ab.sw_in_b <= '0'; end if; end if; end if; end process regs; end architecture rtl;
architecture RTL of FIFO is begin process begin -- Comment loop end loop; -- Comment LOOP_LABEL : loop end loop; -- Comment while condition loop end loop; -- Comment for x in (31 downto 0) loop end loop; loop end loop; LOOP_LABEL : loop end loop; while condition loop end loop; for x in (31 downto 0) loop end loop; -- Violations below a <= b; loop end loop; a <= b; LOOP_LABEL : loop end loop; a <= b; while condition loop end loop; a <= b; for x in (31 downto 0) loop end loop; end process; end;
------------------------------------------------------------------------------ -- mgt_fifo1.vhd - entity/architecture pair ------------------------------------------------------------------------------ -- IMPORTANT: -- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS. -- -- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED. -- -- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW -- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION -- OF THE USER_LOGIC ENTITY. ------------------------------------------------------------------------------ -- -- ************************************************************************* -- Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. -- -- Xilinx, Inc. -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE. -- -- YOU MAY COPY AND MODIFY THESE FILES FOR YOUR OWN INTERNAL USE SOLELY -- WITH XILINX PROGRAMMABLE LOGIC DEVICES AND XILINX EDK SYSTEM OR -- CREATE IP MODULES SOLELY FOR XILINX PROGRAMMABLE LOGIC DEVICES AND -- XILINX EDK SYSTEM. NO RIGHTS ARE GRANTED TO DISTRIBUTE ANY FILES -- UNLESS THEY ARE DISTRIBUTED IN XILINX PROGRAMMABLE LOGIC DEVICES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------ -- Filename: mgt_fifo1.vhd -- Version: 1.00.a -- Description: Top level design, instantiates IPIF and user logic. -- Date: Tue Jul 05 10:18:46 2005 (by Create and Import Peripheral Wizard) -- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port: "_i" -- device pins: "_pin" -- ports: "- Names begin with Uppercase" -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC>" ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v2_00_a; use proc_common_v2_00_a.proc_common_pkg.all; use proc_common_v2_00_a.ipif_pkg.all; library opb_ipif_v3_01_a; use opb_ipif_v3_01_a.all; library mgt_fifo1_v1_00_a; use mgt_fifo1_v1_00_a.all; ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_BASEADDR -- User logic base address -- C_HIGHADDR -- User logic high address -- C_OPB_AWIDTH -- OPB address bus width -- C_OPB_DWIDTH -- OPB data bus width -- C_FAMILY -- Target FPGA architecture -- -- Definition of Ports: -- OPB_Clk -- OPB Clock -- OPB_Rst -- OPB Reset -- Sl_DBus -- Slave data bus -- Sl_errAck -- Slave error acknowledge -- Sl_retry -- Slave retry -- Sl_toutSup -- Slave timeout suppress -- Sl_xferAck -- Slave transfer acknowledge -- OPB_ABus -- OPB address bus -- OPB_BE -- OPB byte enable -- OPB_DBus -- OPB data bus -- OPB_RNW -- OPB read/not write -- OPB_select -- OPB select -- OPB_seqAddr -- OPB sequential address ------------------------------------------------------------------------------ entity mgt_fifo1 is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_BASEADDR : std_logic_vector := X"00000000"; C_HIGHADDR : std_logic_vector := X"0000FFFF"; C_OPB_AWIDTH : integer := 32; C_OPB_DWIDTH : integer := 32; C_FAMILY : string := "virtex2p" -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here iTOP_REF_CLK : in std_logic; iRXN : in std_logic; iRXP : in std_logic; iTXN : out std_logic; iTXP : out std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete OPB_Clk : in std_logic; OPB_Rst : in std_logic; Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); Sl_errAck : out std_logic; Sl_retry : out std_logic; Sl_toutSup : out std_logic; Sl_xferAck : out std_logic; OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); OPB_RNW : in std_logic; OPB_select : in std_logic; OPB_seqAddr : in std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute SIGIS : string; attribute SIGIS of OPB_Clk : signal is "Clk"; attribute SIGIS of OPB_Rst : signal is "Rst"; end entity mgt_fifo1; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of mgt_fifo1 is ------------------------------------------ -- Constant: array of address range identifiers ------------------------------------------ constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => USER_00, -- user logic S/W register address space 1 => IPIF_RDFIFO_REG, -- include read FIFO register service 2 => IPIF_RDFIFO_DATA, -- include read FIFO service 3 => IPIF_WRFIFO_REG, -- include write FIFO register service 4 => IPIF_WRFIFO_DATA -- include write FIFO service ); ------------------------------------------ -- Constant: array of address pairs for each address range ------------------------------------------ constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0'); constant USER_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000"; constant USER_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF"; constant RDFIFO_REG_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100"; constant RDFIFO_REG_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF"; constant RDFIFO_DATA_BASEADDR : std_logic_vector := C_BASEADDR or X"00000200"; constant RDFIFO_DATA_HIGHADDR : std_logic_vector := C_BASEADDR or X"000002FF"; constant WRFIFO_REG_BASEADDR : std_logic_vector := C_BASEADDR or X"00000300"; constant WRFIFO_REG_HIGHADDR : std_logic_vector := C_BASEADDR or X"000003FF"; constant WRFIFO_DATA_BASEADDR : std_logic_vector := C_BASEADDR or X"00000400"; constant WRFIFO_DATA_HIGHADDR : std_logic_vector := C_BASEADDR or X"000004FF"; constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address ZERO_ADDR_PAD & USER_HIGHADDR, -- user logic high address ZERO_ADDR_PAD & RDFIFO_REG_BASEADDR, -- read FIFO register base address ZERO_ADDR_PAD & RDFIFO_REG_HIGHADDR, -- read FIFO register high address ZERO_ADDR_PAD & RDFIFO_DATA_BASEADDR, -- read FIFO data base address ZERO_ADDR_PAD & RDFIFO_DATA_HIGHADDR, -- read FIFO data high address ZERO_ADDR_PAD & WRFIFO_REG_BASEADDR, -- write FIFO register base address ZERO_ADDR_PAD & WRFIFO_REG_HIGHADDR, -- write FIFO register high address ZERO_ADDR_PAD & WRFIFO_DATA_BASEADDR, -- write FIFO data base address ZERO_ADDR_PAD & WRFIFO_DATA_HIGHADDR -- write FIFO data high address ); ------------------------------------------ -- Constant: array of data widths for each target address range ------------------------------------------ constant USER_DWIDTH : integer := 32; constant USER_RDFIFO_DWIDTH : integer := 32; constant USER_WRFIFO_DWIDTH : integer := 32; constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => USER_DWIDTH, -- user logic data width 1 => C_OPB_DWIDTH, -- read FIFO register data width 2 => USER_RDFIFO_DWIDTH, -- read FIFO data width 3 => C_OPB_DWIDTH, -- write FIFO register data width 4 => USER_WRFIFO_DWIDTH -- write FIFO data width ); ------------------------------------------ -- Constant: array of desired number of chip enables for each address range ------------------------------------------ constant USER_NUM_CE : integer := 2; constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => pad_power2(USER_NUM_CE), -- user logic number of CEs 1 => 2, -- read FIFO register - 2 CEs 2 => 1, -- read FIFO data - 1 CE 3 => 2, -- write FIFO register - 2 CEs 4 => 1 -- write FIFO data - 1 CE ); ------------------------------------------ -- Constant: array of unique properties for each address range ------------------------------------------ constant USER_RDFIFO_DEPTH : integer := 512; constant USER_RDFIFO_INCLUDE_PACKET_MODE : boolean := false; constant USER_RDFIFO_INCLUDE_VACANCY : boolean := true; constant USER_WRFIFO_DEPTH : integer := 512; constant USER_WRFIFO_INCLUDE_PACKET_MODE : boolean := false; constant USER_WRFIFO_INCLUDE_VACANCY : boolean := true; constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE := ( 0 => (others => 0), -- user logic slave space dependent properties (none defined) 1 => (others => 0), -- IPIF read pfifo register dependent properties (none defined) 2 => ( -- IPIF read pfifo data dependent properties FIFO_CAPACITY_BITS => USER_RDFIFO_DEPTHUSER_RDFIFO_DWIDTH, WR_WIDTH_BITS => USER_RDFIFO_DWIDTH, RD_WIDTH_BITS => USER_RDFIFO_DWIDTH, EXCLUDE_PACKET_MODE => 1-boolean'pos(USER_RDFIFO_INCLUDE_PACKET_MODE), EXCLUDE_VACANCY => 1-boolean'pos(USER_RDFIFO_INCLUDE_VACANCY), others => 0), 3 => (others => 0), -- IPIF write pfifo register dependent properties (none defined) 4 => ( -- IPIF write pfifo data dependent properties FIFO_CAPACITY_BITS => USER_WRFIFO_DEPTH*USER_WRFIFO_DWIDTH, WR_WIDTH_BITS => USER_WRFIFO_DWIDTH, RD_WIDTH_BITS => USER_WRFIFO_DWIDTH, EXCLUDE_PACKET_MODE => 1-boolean'pos(USER_WRFIFO_INCLUDE_PACKET_MODE), EXCLUDE_VACANCY => 1-boolean'pos(USER_WRFIFO_INCLUDE_VACANCY), others => 0) ); ------------------------------------------ -- Constant: pipeline mode -- 1 = include OPB-In pipeline registers -- 2 = include IP pipeline registers -- 3 = include OPB-In and IP pipeline registers -- 4 = include OPB-Out pipeline registers -- 5 = include OPB-In and OPB-Out pipeline registers -- 6 = include IP and OPB-Out pipeline registers -- 7 = include OPB-In, IP, and OPB-Out pipeline registers -- Note: -- only mode 4, 5, 7 are supported for this release ------------------------------------------ constant PIPELINE_MODEL : integer := 5; ------------------------------------------ -- Constant: user core ID code ------------------------------------------ constant DEV_BLK_ID : integer := 0; ------------------------------------------ -- Constant: enable MIR/Reset register ------------------------------------------ constant DEV_MIR_ENABLE : integer := 0; ------------------------------------------ -- Constant: array of IP interrupt mode -- 1 = Active-high interrupt condition -- 2 = Active-low interrupt condition -- 3 = Active-high pulse interrupt event -- 4 = Active-low pulse interrupt event -- 5 = Positive-edge interrupt event -- 6 = Negative-edge interrupt event ------------------------------------------ constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => 0 -- not used ); ------------------------------------------ -- Constant: enable device burst ------------------------------------------ constant DEV_BURST_ENABLE : integer := 0; ------------------------------------------ -- Constant: include address counter for burst transfers ------------------------------------------ constant INCLUDE_ADDR_CNTR : integer := 0; ------------------------------------------ -- Constant: include write buffer that decouples OPB and IPIC write transactions ------------------------------------------ constant INCLUDE_WR_BUF : integer := 0; ------------------------------------------ -- Constant: index for CS/CE ------------------------------------------ constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00); constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX); ------------------------------------------ -- IP Interconnect (IPIC) signal declarations -- do not delete -- prefix 'i' stands for IPIF while prefix 'u' stands for user logic -- typically user logic will be hooked up to IPIF directly via i<sig> -- unless signal slicing and muxing are needed via u<sig> ------------------------------------------ signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1); signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1); signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0'); signal iIP2Bus_Ack : std_logic := '0'; signal iIP2Bus_Error : std_logic := '0'; signal iIP2Bus_Retry : std_logic := '0'; signal iIP2Bus_ToutSup : std_logic := '0'; signal ZERO_IP2Bus_PostedWrInh : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping signal iIP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0'); signal iIP2RFIFO_WrReq : std_logic := '0'; signal iRFIFO2IP_AlmostFull : std_logic; signal iRFIFO2IP_Full : std_logic; signal iRFIFO2IP_Vacancy : std_logic_vector(0 to bits_needed_for_vac(find_ard_id(ARD_ID_ARRAY, IPIF_RDFIFO_DATA), ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA)))-1); signal iRFIFO2IP_WrAck : std_logic; signal iIP2WFIFO_RdReq : std_logic := '0'; signal iWFIFO2IP_AlmostEmpty : std_logic; signal iWFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0'); signal iWFIFO2IP_Empty : std_logic; signal iWFIFO2IP_Occupancy : std_logic_vector(0 to bits_needed_for_vac(find_ard_id(ARD_ID_ARRAY, IPIF_WRFIFO_DATA), ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA)))-1); signal iWFIFO2IP_RdAck : std_logic; signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping signal iBus2IP_Clk : std_logic; signal iBus2IP_Reset : std_logic; signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1); signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1); signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1); signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1); signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1); ------------------------------------------ -- Component declaration for verilog user logic ------------------------------------------ component user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_DWIDTH : integer := 32; C_NUM_CE : integer := 2; C_RDFIFO_DWIDTH : integer := 32; C_RDFIFO_DEPTH : integer := 512; C_WRFIFO_DWIDTH : integer := 32; C_WRFIFO_DEPTH : integer := 512 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here TOP_REF_CLK : in std_logic; RXP : in std_logic; RXN : in std_logic; TXP : out std_logic; TXN : out std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Reset : in std_logic; Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1); Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1); Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1); Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1); IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1); IP2Bus_Ack : out std_logic; IP2Bus_Retry : out std_logic; IP2Bus_Error : out std_logic; IP2Bus_ToutSup : out std_logic; IP2RFIFO_WrReq : out std_logic; IP2RFIFO_Data : out std_logic_vector(0 to C_RDFIFO_DWIDTH-1); RFIFO2IP_WrAck : in std_logic; RFIFO2IP_AlmostFull : in std_logic; RFIFO2IP_Full : in std_logic; RFIFO2IP_Vacancy : in std_logic_vector(0 to log2(C_RDFIFO_DEPTH)); IP2WFIFO_RdReq : out std_logic; WFIFO2IP_Data : in std_logic_vector(0 to C_WRFIFO_DWIDTH-1); WFIFO2IP_RdAck : in std_logic; WFIFO2IP_AlmostEmpty : in std_logic; WFIFO2IP_Empty : in std_logic; WFIFO2IP_Occupancy : in std_logic_vector(0 to log2(C_WRFIFO_DEPTH)) -- DO NOT EDIT ABOVE THIS LINE --------------------- ); end component user_logic; begin ------------------------------------------ -- instantiate the OPB IPIF ------------------------------------------ OPB_IPIF_I : entity opb_ipif_v3_01_a.opb_ipif generic map ( C_ARD_ID_ARRAY => ARD_ID_ARRAY, C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY, C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY, C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY, C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY, C_PIPELINE_MODEL => PIPELINE_MODEL, C_DEV_BLK_ID => DEV_BLK_ID, C_DEV_MIR_ENABLE => DEV_MIR_ENABLE, C_OPB_AWIDTH => C_OPB_AWIDTH, C_OPB_DWIDTH => C_OPB_DWIDTH, C_FAMILY => C_FAMILY, C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY, C_DEV_BURST_ENABLE => DEV_BURST_ENABLE, C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR, C_INCLUDE_WR_BUF => INCLUDE_WR_BUF ) port map ( OPB_select => OPB_select, OPB_DBus => OPB_DBus, OPB_ABus => OPB_ABus, OPB_BE => OPB_BE, OPB_RNW => OPB_RNW, OPB_seqAddr => OPB_seqAddr, Sln_DBus => Sl_DBus, Sln_xferAck => Sl_xferAck, Sln_errAck => Sl_errAck, Sln_retry => Sl_retry, Sln_toutSup => Sl_toutSup, Bus2IP_CS => open, Bus2IP_CE => open, Bus2IP_RdCE => iBus2IP_RdCE, Bus2IP_WrCE => iBus2IP_WrCE, Bus2IP_Data => iBus2IP_Data, Bus2IP_Addr => open, Bus2IP_AddrValid => open, Bus2IP_BE => iBus2IP_BE, Bus2IP_RNW => open, Bus2IP_Burst => open, IP2Bus_Data => iIP2Bus_Data, IP2Bus_Ack => iIP2Bus_Ack, IP2Bus_AddrAck => '0', IP2Bus_Error => iIP2Bus_Error, IP2Bus_Retry => iIP2Bus_Retry, IP2Bus_ToutSup => iIP2Bus_ToutSup, IP2Bus_PostedWrInh => ZERO_IP2Bus_PostedWrInh, IP2RFIFO_Data => iIP2RFIFO_Data, IP2RFIFO_WrMark => '0', IP2RFIFO_WrRelease => '0', IP2RFIFO_WrReq => iIP2RFIFO_WrReq, IP2RFIFO_WrRestore => '0', RFIFO2IP_AlmostFull => iRFIFO2IP_AlmostFull, RFIFO2IP_Full => iRFIFO2IP_Full, RFIFO2IP_Vacancy => iRFIFO2IP_Vacancy, RFIFO2IP_WrAck => iRFIFO2IP_WrAck, IP2WFIFO_RdMark => '0', IP2WFIFO_RdRelease => '0', IP2WFIFO_RdReq => iIP2WFIFO_RdReq, IP2WFIFO_RdRestore => '0', WFIFO2IP_AlmostEmpty => iWFIFO2IP_AlmostEmpty, WFIFO2IP_Data => iWFIFO2IP_Data, WFIFO2IP_Empty => iWFIFO2IP_Empty, WFIFO2IP_Occupancy => iWFIFO2IP_Occupancy, WFIFO2IP_RdAck => iWFIFO2IP_RdAck, IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent, IP2INTC_Irpt => open, Freeze => '0', Bus2IP_Freeze => open, OPB_Clk => OPB_Clk, Bus2IP_Clk => iBus2IP_Clk, IP2Bus_Clk => '0', Reset => OPB_Rst, Bus2IP_Reset => iBus2IP_Reset ); ------------------------------------------ -- instantiate the User Logic ------------------------------------------ USER_LOGIC_I : component user_logic generic map ( -- MAP USER GENERICS BELOW THIS LINE --------------- --USER generics mapped here -- MAP USER GENERICS ABOVE THIS LINE --------------- C_DWIDTH => USER_DWIDTH, C_NUM_CE => USER_NUM_CE, C_RDFIFO_DWIDTH => USER_RDFIFO_DWIDTH, C_RDFIFO_DEPTH => USER_RDFIFO_DEPTH, C_WRFIFO_DWIDTH => USER_WRFIFO_DWIDTH, C_WRFIFO_DEPTH => USER_WRFIFO_DEPTH ) port map ( -- MAP USER PORTS BELOW THIS LINE ------------------ --USER ports mapped here TOP_REF_CLK => iTOP_REF_CLK, RXP => iRXP, RXN => iRXN, TXP => iTXP, TXN => iTXN, -- MAP USER PORTS ABOVE THIS LINE ------------------ Bus2IP_Clk => iBus2IP_Clk, Bus2IP_Reset => iBus2IP_Reset, Bus2IP_Data => uBus2IP_Data, Bus2IP_BE => uBus2IP_BE, Bus2IP_RdCE => uBus2IP_RdCE, Bus2IP_WrCE => uBus2IP_WrCE, IP2Bus_Data => uIP2Bus_Data, IP2Bus_Ack => iIP2Bus_Ack, IP2Bus_Retry => iIP2Bus_Retry, IP2Bus_Error => iIP2Bus_Error, IP2Bus_ToutSup => iIP2Bus_ToutSup, IP2RFIFO_WrReq => iIP2RFIFO_WrReq, IP2RFIFO_Data => iIP2RFIFO_Data, RFIFO2IP_WrAck => iRFIFO2IP_WrAck, RFIFO2IP_AlmostFull => iRFIFO2IP_AlmostFull, RFIFO2IP_Full => iRFIFO2IP_Full, RFIFO2IP_Vacancy => iRFIFO2IP_Vacancy, IP2WFIFO_RdReq => iIP2WFIFO_RdReq, WFIFO2IP_Data => iWFIFO2IP_Data, WFIFO2IP_RdAck => iWFIFO2IP_RdAck, WFIFO2IP_AlmostEmpty => iWFIFO2IP_AlmostEmpty, WFIFO2IP_Empty => iWFIFO2IP_Empty, WFIFO2IP_Occupancy => iWFIFO2IP_Occupancy ); ------------------------------------------ -- hooking up signal slicing ------------------------------------------ uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1); uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1); uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1); uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1); iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data; end IMP;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_cast_GNMYKU6OLE is generic ( round : natural := 0; saturate : natural := 0); port( input : in std_logic_vector(15 downto 0); output : out std_logic_vector(3 downto 0)); end entity; architecture rtl of alt_dspbuilder_cast_GNMYKU6OLE is Begin -- Output - I/O assignment from Simulink Block "Output" Outputi : alt_dspbuilder_SBF generic map( width_inl=> 4 + 1 , width_inr=> 12, width_outl=> 4, width_outr=> 0, lpm_signed=> BusIsUnsigned , round=> round, satur=> saturate) port map ( xin(15 downto 0) => input, xin(16) => '0', yout => output ); end architecture;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_cast_GNMYKU6OLE is generic ( round : natural := 0; saturate : natural := 0); port( input : in std_logic_vector(15 downto 0); output : out std_logic_vector(3 downto 0)); end entity; architecture rtl of alt_dspbuilder_cast_GNMYKU6OLE is Begin -- Output - I/O assignment from Simulink Block "Output" Outputi : alt_dspbuilder_SBF generic map( width_inl=> 4 + 1 , width_inr=> 12, width_outl=> 4, width_outr=> 0, lpm_signed=> BusIsUnsigned , round=> round, satur=> saturate) port map ( xin(15 downto 0) => input, xin(16) => '0', yout => output ); end architecture;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_cast_GNMYKU6OLE is generic ( round : natural := 0; saturate : natural := 0); port( input : in std_logic_vector(15 downto 0); output : out std_logic_vector(3 downto 0)); end entity; architecture rtl of alt_dspbuilder_cast_GNMYKU6OLE is Begin -- Output - I/O assignment from Simulink Block "Output" Outputi : alt_dspbuilder_SBF generic map( width_inl=> 4 + 1 , width_inr=> 12, width_outl=> 4, width_outr=> 0, lpm_signed=> BusIsUnsigned , round=> round, satur=> saturate) port map ( xin(15 downto 0) => input, xin(16) => '0', yout => output ); end architecture;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_cast_GNMYKU6OLE is generic ( round : natural := 0; saturate : natural := 0); port( input : in std_logic_vector(15 downto 0); output : out std_logic_vector(3 downto 0)); end entity; architecture rtl of alt_dspbuilder_cast_GNMYKU6OLE is Begin -- Output - I/O assignment from Simulink Block "Output" Outputi : alt_dspbuilder_SBF generic map( width_inl=> 4 + 1 , width_inr=> 12, width_outl=> 4, width_outr=> 0, lpm_signed=> BusIsUnsigned , round=> round, satur=> saturate) port map ( xin(15 downto 0) => input, xin(16) => '0', yout => output ); end architecture;
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ORGATE IS PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END ORGATE; ARCHITECTURE OR1 OF ORGATE IS BEGIN C <= A OR B; END OR1;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity logical is Port ( A : in STD_LOGIC_VECTOR (3 downto 0); B : in STD_LOGIC_VECTOR (3 downto 0); op : in STD_LOGIC_VECTOR (1 downto 0); R : out STD_LOGIC_VECTOR (3 downto 0) ); end logical; architecture Behavioral of logical is --output signals signal and_R : std_logic_vector (3 downto 0); signal or_R : std_logic_vector (3 downto 0); signal nor_R : std_logic_vector (3 downto 0); signal xor_R : std_logic_vector (3 downto 0); begin --crunch all possible values and_R <= A AND B; or_R <= A OR B; nor_R <= A NOR B; xor_R <= A XOR B; --select output based on opcode output: entity work.mux4 port map (nor_R, and_R, or_R, xor_R, op, R); end Behavioral;
-- -------------------------------------------------------------------- -- -- Copyright © 2008 by IEEE. All rights reserved. -- -- This source file is an essential part of IEEE Std 1076-2008, -- IEEE Standard VHDL Language Reference Manual. This source file may not be -- copied, sold, or included with software that is sold without written -- permission from the IEEE Standards Department. This source file may be -- copied for individual use between licensed users. This source file is -- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR -- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE -- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify -- and hold IEEE harmless from any damages or liability arising out of the -- use thereof. -- -- Title : Floating-point package (Generic package body) -- : -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: Accellera VHDL-TC and IEEE P1076 Working Group -- : -- Purpose : This packages defines basic binary floating point -- : arithmetic functions -- : -- Note : This package may be modified to include additional data -- : required by tools, but it must in no way change the -- : external interfaces or simulation behavior of the -- : description. It is permissible to add comments and/or -- : attributes to the package declarations, but not to change -- : or delete any original lines of the package declaration. -- : The package body may be changed only in accordance with -- : the terms of Clause 16 of this standard. -- : -- -------------------------------------------------------------------- -- $Revision: 1220 $ -- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ -- -------------------------------------------------------------------- package body float_generic_pkg is -- Author David Bishop ([email protected]) ----------------------------------------------------------------------------- -- type declarations ----------------------------------------------------------------------------- -- This deferred constant will tell you if the package body is synthesizable -- or implemented as real numbers, set to "true" if synthesizable. constant fphdlsynth_or_real : BOOLEAN := true; -- deferred constant -- types of boundary conditions type boundary_type is (normal, infinity, zero, denormal); -- null range array constant constant NAFP : UNRESOLVED_float (0 downto 1) := (others => '0'); constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0'); -- Special version of "minimum" to do some boundary checking function mine (L, R : INTEGER) return INTEGER is begin -- function minimum if (L = INTEGER'low or R = INTEGER'low) then report float_generic_pkg'instance_name & " Unbounded number passed, was a literal used?" severity error; return 0; end if; return minimum (L, R); end function mine; -- Generates the base number for the exponent normalization offset. function gen_expon_base ( constant exponent_width : NATURAL) return SIGNED is variable result : SIGNED (exponent_width-1 downto 0); begin result := (others => '1'); result (exponent_width-1) := '0'; return result; end function gen_expon_base; -- Integer version of the "log2" command (contributed by Peter Ashenden) function log2 (A : NATURAL) return NATURAL is variable quotient : NATURAL; variable result : NATURAL := 0; begin quotient := A / 2; while quotient > 0 loop quotient := quotient / 2; result := result + 1; end loop; return result; end function log2; -- Function similar to the ILOGB function in MATH_REAL function log2 (A : REAL) return INTEGER is variable Y : REAL; variable N : INTEGER := 0; begin if (A = 1.0 or A = 0.0) then return 0; end if; Y := A; if(A > 1.0) then while Y >= 2.0 loop Y := Y / 2.0; N := N + 1; end loop; return N; end if; -- O < Y < 1 while Y < 1.0 loop Y := Y * 2.0; N := N - 1; end loop; return N; end function log2; -- purpose: Test the boundary conditions of a Real number procedure test_boundary ( arg : in REAL; -- Input, converted to real constant fraction_width : in NATURAL; -- length of FP output fraction constant exponent_width : in NATURAL; -- length of FP exponent constant denormalize : in BOOLEAN := true; -- Use IEEE extended FP variable btype : out boundary_type; variable log2i : out INTEGER ) is constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset constant exp_min : SIGNED (12 downto 0) := -(resize(expon_base, 13)) + 1; -- Minimum normal exponent constant exp_ext_min : SIGNED (12 downto 0) := exp_min - fraction_width; -- Minimum for denormal exponent variable log2arg : INTEGER; -- log2 of argument begin -- function test_boundary -- Check to see if the exponent is big enough -- Note that the argument is always an absolute value at this point. log2arg := log2(arg); if arg = 0.0 then btype := zero; elsif exponent_width > 11 then -- Exponent for Real is 11 (64 bit) btype := normal; else if log2arg < to_integer(exp_min) then if denormalize then if log2arg < to_integer(exp_ext_min) then btype := zero; else btype := denormal; end if; else if log2arg < to_integer(exp_min)-1 then btype := zero; else btype := normal; -- Can still represent this number end if; end if; elsif exponent_width < 11 then if log2arg > to_integer(expon_base)+1 then btype := infinity; else btype := normal; end if; else btype := normal; end if; end if; log2i := log2arg; end procedure test_boundary; -- purpose: Rounds depending on the state of the "round_style" -- Logic taken from -- "What Every Computer Scientist Should Know About Floating Point Arithmetic" -- by David Goldberg (1991) function check_round ( fract_in : STD_ULOGIC; -- input fraction sign : STD_ULOGIC; -- sign bit remainder : UNSIGNED; -- remainder to round from sticky : STD_ULOGIC := '0'; -- Sticky bit constant round_style : round_type) -- rounding type return BOOLEAN is variable result : BOOLEAN; variable or_reduced : STD_ULOGIC; begin -- function check_round result := false; if (remainder'length > 0) then -- if remainder in a null array or_reduced := or (remainder & sticky); rounding_case : case round_style is when round_nearest => -- Round Nearest, default mode if remainder(remainder'high) = '1' then -- round if (remainder'length > 1) then if ((or (remainder(remainder'high-1 downto remainder'low)) = '1' or sticky = '1') or fract_in = '1') then -- Make the bottom bit zero if possible if we are at 1/2 result := true; end if; else result := (fract_in = '1' or sticky = '1'); end if; end if; when round_inf => -- round up if positive, else truncate. if or_reduced = '1' and sign = '0' then result := true; end if; when round_neginf => -- round down if negative, else truncate. if or_reduced = '1' and sign = '1' then result := true; end if; when round_zero => -- round toward 0 Truncate null; end case rounding_case; end if; return result; end function check_round; -- purpose: Rounds depending on the state of the "round_style" -- unsigned version procedure fp_round ( fract_in : in UNSIGNED; -- input fraction expon_in : in SIGNED; -- input exponent fract_out : out UNSIGNED; -- output fraction expon_out : out SIGNED) is -- output exponent begin -- procedure fp_round if and (fract_in) = '1' then -- Fraction is all "1" expon_out := expon_in + 1; fract_out := to_unsigned(0, fract_out'high+1); else expon_out := expon_in; fract_out := fract_in + 1; end if; end procedure fp_round; -- This version of break_number doesn't call "classfp" procedure break_number ( -- internal version arg : in UNRESOLVED_float; fptyp : in valid_fpstate; denormalize : in BOOLEAN := true; fract : out UNSIGNED; expon : out SIGNED) is constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction constant exponent_width : NATURAL := arg'high; -- length of FP output exponent constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable exp : SIGNED (expon'range); begin fract (fraction_width-1 downto 0) := UNSIGNED (to_slv(arg(-1 downto -fraction_width))); breakcase : case fptyp is when pos_zero \| neg_zero => fract (fraction_width) := '0'; exp := -expon_base; when pos_denormal \| neg_denormal => if denormalize then exp := -expon_base; fract (fraction_width) := '0'; else exp := -expon_base - 1; fract (fraction_width) := '1'; end if; when pos_normal \| neg_normal \| pos_inf \| neg_inf => fract (fraction_width) := '1'; exp := SIGNED(arg(exponent_width-1 downto 0)); exp (exponent_width-1) := not exp(exponent_width-1); when others => assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "BREAK_NUMBER: " & "Meta state detected in fp_break_number process" severity warning; -- complete the case, if a NAN goes in, a NAN comes out. exp := (others => '1'); fract (fraction_width) := '1'; end case breakcase; expon := exp; end procedure break_number; -- purpose: floating point to UNSIGNED -- Used by to_integer, to_unsigned, and to_signed functions procedure float_to_unsigned ( arg : in UNRESOLVED_float; -- floating point input variable sign : out STD_ULOGIC; -- sign of output variable frac : out UNSIGNED; -- unsigned biased output constant denormalize : in BOOLEAN; -- turn on denormalization constant bias : in NATURAL; -- bias for fixed point constant round_style : in round_type) is -- rounding method constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent variable fract : UNSIGNED (frac'range); -- internal version of frac variable isign : STD_ULOGIC; -- internal version of sign variable exp : INTEGER; -- Exponent variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp -- Base to divide fraction by variable frac_shift : UNSIGNED (frac'high+3 downto 0); -- Fraction shifted variable shift : INTEGER; variable remainder : UNSIGNED (2 downto 0); variable round : STD_ULOGIC; -- round BIT begin isign := to_x01(arg(arg'high)); -- exponent /= '0', normal floating point expon := to_01(SIGNED(arg (exponent_width-1 downto 0)), 'X'); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (expon); -- Figure out the fraction fract := (others => '0'); -- fill with zero fract (fract'high) := '1'; -- Add the "1.0". shift := (fract'high-1) - exp; if fraction_width > fract'high then -- Can only use size-2 bits fract (fract'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto -fract'high))); else -- can use all bits fract (fract'high-1 downto fract'high-fraction_width) := UNSIGNED (to_slv (arg(-1 downto -fraction_width))); end if; frac_shift := fract & "000"; if shift < 0 then -- Overflow fract := (others => '1'); else frac_shift := shift_right (frac_shift, shift); fract := frac_shift (frac_shift'high downto 3); remainder := frac_shift (2 downto 0); -- round (round_zero will bypass this and truncate) case round_style is when round_nearest => round := remainder(2) and (fract (0) or (or (remainder (1 downto 0)))); when round_inf => round := remainder(2) and not isign; when round_neginf => round := remainder(2) and isign; when others => round := '0'; end case; if round = '1' then fract := fract + 1; end if; end if; frac := fract; sign := isign; end procedure float_to_unsigned; -- purpose: returns a part of a vector, this function is here because -- or (fractr (to_integer(shiftx) downto 0)); -- can't be synthesized in some synthesis tools. function smallfract ( arg : UNSIGNED; shift : NATURAL) return STD_ULOGIC is variable orx : STD_ULOGIC; begin orx := arg(shift); for i in arg'range loop if i < shift then orx := arg(i) or orx; end if; end loop; return orx; end function smallfract; --------------------------------------------------------------------------- -- Visible functions --------------------------------------------------------------------------- -- purpose: converts the negative index to a positive one -- negative indices are illegal in 1164 and 1076.3 function to_sulv ( arg : UNRESOLVED_float) -- fp vector return STD_ULOGIC_VECTOR is subtype result_subtype is STD_ULOGIC_VECTOR (arg'length-1 downto 0); variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0); begin -- function to_std_ulogic_vector if arg'length < 1 then return NSLV; end if; result := result_subtype (arg); return result; end function to_sulv; -- Converts an fp into an SULV function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR is begin return to_sulv (arg); end function to_slv; -- purpose: normalizes a floating point number -- This version assumes an "unsigned" input with function normalize ( fract : UNRESOLVED_UNSIGNED; -- fraction, unnormalized expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1 sign : STD_ULOGIC; -- sign BIT sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is variable sfract : UNSIGNED (fract'high downto 0); -- shifted fraction variable rfract : UNSIGNED (fraction_width-1 downto 0); -- fraction variable exp : SIGNED (exponent_width+1 downto 0); -- exponent variable rexp : SIGNED (exponent_width+1 downto 0); -- result exponent variable rexpon : UNSIGNED (exponent_width-1 downto 0); -- exponent variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result variable shiftr : INTEGER; -- shift amount variable stickyx : STD_ULOGIC; -- version of sticky constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable round, zerores, infres : BOOLEAN; begin -- function normalize zerores := false; infres := false; round := false; shiftr := find_leftmost (to_01(fract), '1') -- Find the first "1" - fraction_width - nguard; -- subtract the length we want exp := resize (expon, exp'length) + shiftr; if (or (fract) = '0') then -- Zero zerores := true; elsif ((exp <= -resize(expon_base, exp'length)-1) and denormalize) or ((exp < -resize(expon_base, exp'length)-1) and not denormalize) then if (exp >= -resize(expon_base, exp'length)-fraction_width-1) and denormalize then exp := -resize(expon_base, exp'length)-1; shiftr := -to_integer (expon + expon_base); -- new shift else -- return zero zerores := true; end if; elsif (exp > expon_base-1) then -- infinity infres := true; end if; if zerores then result := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); elsif infres then result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else sfract := fract srl shiftr; -- shift if shiftr > 0 then -- stickyx := sticky or (or (fract (shiftr-1 downto 0))); stickyx := sticky or smallfract (fract, shiftr-1); else stickyx := sticky; end if; if nguard > 0 then round := check_round ( fract_in => sfract (nguard), sign => sign, remainder => sfract(nguard-1 downto 0), sticky => stickyx, round_style => round_style); end if; if round then fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard), expon_in => exp(rexp'range), fract_out => rfract, expon_out => rexp); else rfract := sfract (fraction_width-1+nguard downto nguard); rexp := exp(rexp'range); end if; -- result rexpon := UNSIGNED (rexp(exponent_width-1 downto 0)); rexpon (exponent_width-1) := not rexpon(exponent_width-1); result (rexpon'range) := UNRESOLVED_float(rexpon); result (-1 downto -fraction_width) := UNRESOLVED_float(rfract); end if; result (exponent_width) := sign; -- sign BIT return result; end function normalize; -- purpose: normalizes a floating point number -- This version assumes a "ufixed" input function normalize ( fract : UNRESOLVED_ufixed; -- unsigned fixed point expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1 sign : STD_ULOGIC; -- sign bit sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arguns : UNSIGNED (fract'high + fraction_width + nguard downto 0) := (others => '0'); begin -- function normalize arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) := UNSIGNED (to_slv (fract)); result := normalize (fract => arguns, expon => expon, sign => sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => nguard); return result; end function normalize; -- purpose: normalizes a floating point number -- This version assumes a "ufixed" input with a "size_res" input function normalize ( fract : UNRESOLVED_ufixed; -- unsigned fixed point expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1 sign : STD_ULOGIC; -- sign bit sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) size_res : UNRESOLVED_float; -- used for sizing only constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is constant fraction_width : NATURAL := -size_res'low; constant exponent_width : NATURAL := size_res'high; variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arguns : UNSIGNED (fract'high + fraction_width + nguard downto 0) := (others => '0'); begin -- function normalize arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) := UNSIGNED (to_slv (fract)); result := normalize (fract => arguns, expon => expon, sign => sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => nguard); return result; end function normalize; -- Regular "normalize" function with a "size_res" input. function normalize ( fract : UNRESOLVED_UNSIGNED; -- unsigned expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized sign : STD_ULOGIC; -- sign bit sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) size_res : UNRESOLVED_float; -- used for sizing only constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is begin return normalize (fract => fract, expon => expon, sign => sign, sticky => sticky, fraction_width => -size_res'low, exponent_width => size_res'high, round_style => round_style, denormalize => denormalize, nguard => nguard); end function normalize; -- Returns the class which X falls into function Classfp ( x : UNRESOLVED_float; -- floating point input check_error : BOOLEAN := float_check_error) -- check for errors return valid_fpstate is constant fraction_width : INTEGER := -mine(x'low, x'low); -- length of FP output fraction constant exponent_width : INTEGER := x'high; -- length of FP output exponent variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- classfp if (arg'length < 1 or fraction_width < 3 or exponent_width < 3 or x'left < x'right) then report FLOAT_GENERIC_PKG'instance_name & "CLASSFP: " & "Floating point number detected with a bad range" severity error; return isx; end if; -- Check for "X". arg := to_01 (x, 'X'); if (arg(0) = 'X') then return isx; -- If there is an X in the number -- Special cases, check for illegal number elsif check_error and (and (STD_ULOGIC_VECTOR (arg (exponent_width-1 downto 0))) = '1') then -- Exponent is all "1". if or (to_slv (arg (-1 downto -fraction_width))) /= '0' then -- Fraction must be all "0" or this is not a number. if (arg(-1) = '1') then -- From "W. Khan - IEEE standard return nan; -- 754 binary FP Signaling nan (Not a number) else return quiet_nan; end if; -- Check for infinity elsif arg(exponent_width) = '0' then return pos_inf; -- Positive infinity else return neg_inf; -- Negative infinity end if; -- check for "0" elsif or (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0))) = '0' then -- Exponent is all "0" if or (to_slv (arg (-1 downto -fraction_width))) = '0' then -- Fraction is all "0" if arg(exponent_width) = '0' then return pos_zero; -- Zero else return neg_zero; end if; else if arg(exponent_width) = '0' then return pos_denormal; -- Denormal number (ieee extended fp) else return neg_denormal; end if; end if; else if arg(exponent_width) = '0' then return pos_normal; -- Normal FP number else return neg_normal; end if; end if; end function Classfp; procedure break_number ( arg : in UNRESOLVED_float; denormalize : in BOOLEAN := float_denormalize; check_error : in BOOLEAN := float_check_error; fract : out UNRESOLVED_UNSIGNED; expon : out UNRESOLVED_SIGNED; sign : out STD_ULOGIC) is constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction variable fptyp : valid_fpstate; begin fptyp := Classfp (arg, check_error); sign := to_x01(arg(arg'high)); break_number ( arg => arg, fptyp => fptyp, denormalize => denormalize, fract => fract, expon => expon); end procedure break_number; procedure break_number ( arg : in UNRESOLVED_float; denormalize : in BOOLEAN := float_denormalize; check_error : in BOOLEAN := float_check_error; fract : out UNRESOLVED_ufixed; -- 1 downto -fraction_width expon : out UNRESOLVED_SIGNED; -- exponent_width-1 downto 0 sign : out STD_ULOGIC) is constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction variable fptyp : valid_fpstate; variable ufract : UNSIGNED (fraction_width downto 0); -- unsigned fraction begin fptyp := Classfp (arg, check_error); sign := to_x01(arg(arg'high)); break_number ( arg => arg, fptyp => fptyp, denormalize => denormalize, fract => ufract, expon => expon); fract (0 downto -fraction_width) := ufixed (ufract); end procedure break_number; -- Arithmetic functions function "abs" ( arg : UNRESOLVED_float) -- floating point input return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); -- result begin if (arg'length > 0) then result := to_01 (arg, 'X'); result (arg'high) := '0'; -- set the sign bit to positive return result; else return NAFP; end if; end function "abs"; -- IEEE 754 "negative" function function "-" ( arg : UNRESOLVED_float) -- floating point input return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); -- result begin if (arg'length > 0) then result := to_01 (arg, 'X'); result (arg'high) := not result (arg'high); -- invert sign bit return result; else return NAFP; end if; end function "-"; -- Addition, adds two floating point numbers function add ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant addguard : NATURAL := guard; -- add one guard bit variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable fractl, fractr : UNSIGNED (fraction_width+1+addguard downto 0); -- fractions variable fractc, fracts : UNSIGNED (fractl'range); -- constant and shifted variables variable urfract, ulfract : UNSIGNED (fraction_width downto 0); variable ufract : UNSIGNED (fraction_width+1+addguard downto 0); variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width downto 0); -- result exponent variable shiftx : SIGNED (exponent_width downto 0); -- shift fractions variable sign : STD_ULOGIC; -- sign of the output variable leftright : BOOLEAN; -- left or right used variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); variable sticky : STD_ULOGIC; -- Holds precision for rounding begin -- addition if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan) -- Return quiet NAN, IEEE754-1985-7.1,1 or (lfptype = pos_inf and rfptype = neg_inf) or (lfptype = neg_inf and rfptype = pos_inf) then -- Return quiet NAN, IEEE754-1985-7.1,2 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = pos_inf or rfptype = pos_inf) then -- x + inf = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = neg_inf or rfptype = neg_inf) then -- x - inf = -inf fpresult := neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = neg_zero and rfptype = neg_zero) then -- -0 + -0 = -0 fpresult := neg_zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); fractl := (others => '0'); fractl (fraction_width+addguard downto addguard) := ulfract; break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); fractr := (others => '0'); fractr (fraction_width+addguard downto addguard) := urfract; shiftx := (exponl(exponent_width-1) & exponl) - exponr; if shiftx < -fractl'high then rexpon := exponr(exponent_width-1) & exponr; fractc := fractr; fracts := (others => '0'); -- add zero leftright := false; sticky := or (fractl); elsif shiftx < 0 then shiftx := - shiftx; fracts := shift_right (fractl, to_integer(shiftx)); fractc := fractr; rexpon := exponr(exponent_width-1) & exponr; leftright := false; -- sticky := or (fractl (to_integer(shiftx) downto 0)); sticky := smallfract (fractl, to_integer(shiftx)); elsif shiftx = 0 then rexpon := exponl(exponent_width-1) & exponl; sticky := '0'; if fractr > fractl then fractc := fractr; fracts := fractl; leftright := false; else fractc := fractl; fracts := fractr; leftright := true; end if; elsif shiftx > fractr'high then rexpon := exponl(exponent_width-1) & exponl; fracts := (others => '0'); -- add zero fractc := fractl; leftright := true; sticky := or (fractr); elsif shiftx > 0 then fracts := shift_right (fractr, to_integer(shiftx)); fractc := fractl; rexpon := exponl(exponent_width-1) & exponl; leftright := true; -- sticky := or (fractr (to_integer(shiftx) downto 0)); sticky := smallfract (fractr, to_integer(shiftx)); end if; -- add fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB if l(l'high) = r(r'high) then ufract := fractc + fracts; sign := l(l'high); else -- signs are different ufract := fractc - fracts; -- always positive result if leftright then -- Figure out which sign to use sign := l(l'high); else sign := r(r'high); end if; end if; if or (ufract) = '0' then sign := '0'; -- IEEE 854, 6.3, paragraph 2. end if; -- normalize fpresult := normalize (fract => ufract, expon => rexpon, sign => sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => addguard); end if; return fpresult; end function add; -- Subtraction, Calls "add". function subtract ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable negr : UNRESOLVED_float (r'range); -- negative version of r begin negr := -r; -- r := -r return add (l => l, r => negr, round_style => round_style, guard => guard, check_error => check_error, denormalize => denormalize); end function subtract; -- Floating point multiply function multiply ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant multguard : NATURAL := guard; -- guard bits variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions variable rfract : UNSIGNED ((2(fraction_width))+1 downto 0); -- result fraction variable sfract : UNSIGNED (fraction_width+1+multguard downto 0); -- result fraction variable shifty : INTEGER; -- denormal shift variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent variable fp_sign : STD_ULOGIC; -- sign of result variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); variable sticky : STD_ULOGIC; -- Holds precision for rounding begin -- multiply if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif ((lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan)) then -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (((lfptype = pos_inf or lfptype = neg_inf) and (rfptype = pos_zero or rfptype = neg_zero)) or ((rfptype = pos_inf or rfptype = neg_inf) and (lfptype = pos_zero or lfptype = neg_zero))) then -- 0 inf -- Return quiet NAN, IEEE754-1985-7.1,3 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = pos_inf or rfptype = pos_inf or lfptype = neg_inf or rfptype = neg_inf) then -- x * inf = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); -- figure out the sign fp_sign := l(l'high) xor r(r'high); -- figure out the sign fpresult (exponent_width) := fp_sign; else fp_sign := l(l'high) xor r(r'high); -- figure out the sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => fractl, expon => exponl); break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => fractr, expon => exponr); if (rfptype = pos_denormal or rfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractr, '1'); fractr := shift_left (fractr, shifty); elsif (lfptype = pos_denormal or lfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractl, '1'); fractl := shift_left (fractl, shifty); else shifty := 0; -- Note that a denormal number * a denormal number is always zero. end if; -- multiply -- add the exponents rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1; rfract := fractl * fractr; -- Multiply the fraction sfract := rfract (rfract'high downto rfract'high - (fraction_width+1+multguard)); sticky := or (rfract (rfract'high-(fraction_width+1+multguard) downto 0)); -- normalize fpresult := normalize (fract => sfract, expon => rexpon, sign => fp_sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => multguard); end if; return fpresult; end function multiply; function short_divide ( lx, rx : UNSIGNED) return UNSIGNED is -- This is a special divider for the floating point routines. -- For a true unsigned divider, "stages" needs to = lx'high constant stages : INTEGER := lx'high - rx'high; -- number of stages variable partial : UNSIGNED (lx'range); variable q : UNSIGNED (stages downto 0); variable partial_argl : SIGNED (rx'high + 2 downto 0); variable partial_arg : SIGNED (rx'high + 2 downto 0); begin partial := lx; for i in stages downto 0 loop partial_argl := resize ("0" & SIGNED (partial(lx'high downto i)), partial_argl'length); partial_arg := partial_argl - SIGNED ("0" & rx); if (partial_arg (partial_arg'high) = '1') then -- negative q(i) := '0'; else q(i) := '1'; partial (lx'high+i-stages downto lx'high+i-stages-rx'high) := UNSIGNED (partial_arg(rx'range)); end if; end loop; -- to make the output look like that of the unsigned IEEE divide. return resize (q, lx'length); end function short_divide; -- 1/X function. Needed for algorithm development. function reciprocal ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : NATURAL := arg'high; -- length of FP output exponent constant divguard : NATURAL := guard; -- guard bits function onedivy ( arg : UNSIGNED) return UNSIGNED is variable q : UNSIGNED((2arg'high)+1 downto 0); variable one : UNSIGNED (q'range); begin one := (others => '0'); one(one'high) := '1'; q := short_divide (one, arg); -- Unsigned divide return resize (q, arg'length+1); end function onedivy; variable fptype : valid_fpstate; variable expon : SIGNED (exponent_width-1 downto 0); -- exponents variable denorm_offset : NATURAL range 0 to 2; variable fract : UNSIGNED (fraction_width downto 0); variable fractg : UNSIGNED (fraction_width+divguard downto 0); variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- reciprocal fptype := classfp(arg, check_error); classcase : case fptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => -- 1/inf, return 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); when neg_zero \| pos_zero => -- 1/0 report FLOAT_GENERIC_PKG'instance_name & "RECIPROCAL: Floating Point divide by zero" severity error; fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); when others => if (fptype = pos_denormal or fptype = neg_denormal) and ((arg (-1) or arg(-2)) /= '1') then -- 1/denormal = infinity, with the exception of 2-expon_base fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fpresult (exponent_width) := to_x01 (arg (exponent_width)); else break_number ( arg => arg, fptyp => fptype, denormalize => denormalize, fract => fract, expon => expon); fractg := (others => '0'); if (fptype = pos_denormal or fptype = neg_denormal) then -- The reciprocal of a denormal number is typically zero, -- except for two special cases which are trapped here. if (to_x01(arg (-1)) = '1') then fractg (fractg'high downto divguard+1) := fract (fract'high-1 downto 0); -- Shift to not denormal denorm_offset := 1; -- add 1 to exponent compensate else -- arg(-2) = '1' fractg (fractg'high downto divguard+2) := fract (fract'high-2 downto 0); -- Shift to not denormal denorm_offset := 2; -- add 2 to exponent compensate end if; else fractg (fractg'high downto divguard) := fract; denorm_offset := 0; end if; expon := - expon - 3 + denorm_offset; sfract := onedivy (fractg); -- normalize fpresult := normalize (fract => sfract, expon => expon, sign => arg(exponent_width), sticky => '1', fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => divguard); end if; end case classcase; return fpresult; end function reciprocal; -- floating point division function divide ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant divguard : NATURAL := guard; -- division guard bits variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable ulfract, urfract : UNSIGNED (fraction_width downto 0); variable fractl : UNSIGNED ((2(fraction_width+divguard)+1) downto 0); -- left variable fractr : UNSIGNED (fraction_width+divguard downto 0); -- right variable rfract : UNSIGNED (fractl'range); -- result fraction variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent variable fp_sign, sticky : STD_ULOGIC; -- sign of result variable shifty, shiftx : INTEGER; -- denormal number shift variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- divide if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; classcase : case rfptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => if lfptype = pos_inf or lfptype = neg_inf -- inf / inf or lfptype = quiet_nan or lfptype = nan then -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else -- x / inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when pos_zero \| neg_zero => if lfptype = pos_zero or lfptype = neg_zero -- 0 / 0 or lfptype = quiet_nan or lfptype = nan then -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else report float_generic_pkg'instance_name & "DIVIDE: Floating Point divide by zero" severity error; -- Infinity, define in 754-1985-7.2 fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when others => classcase2 : case lfptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => -- inf / x = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult(exponent_width) := fp_sign; when pos_zero \| neg_zero => -- 0 / X = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult(exponent_width) := fp_sign; when others => fp_sign := l(l'high) xor r(r'high); -- sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); -- right side break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); -- Compute the exponent rexpon := resize (exponl, rexpon'length) - exponr - 2; if (rfptype = pos_denormal or rfptype = neg_denormal) then -- Do the shifting here not after. That way we have a smaller -- shifter, and need a smaller divider, because the top -- bit in the divisor will always be a "1". shifty := fraction_width - find_leftmost(urfract, '1'); urfract := shift_left (urfract, shifty); rexpon := rexpon + shifty; end if; fractr := (others => '0'); fractr (fraction_width+divguard downto divguard) := urfract; if (lfptype = pos_denormal or lfptype = neg_denormal) then shiftx := fraction_width - find_leftmost(ulfract, '1'); ulfract := shift_left (ulfract, shiftx); rexpon := rexpon - shiftx; end if; fractl := (others => '0'); fractl (fractl'high downto fractl'high-fraction_width) := ulfract; -- divide rfract := short_divide (fractl, fractr); -- unsigned divide sfract := rfract (sfract'range); -- lower bits sticky := '1'; -- normalize fpresult := normalize (fract => sfract, expon => rexpon, sign => fp_sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => divguard); end case classcase2; end case classcase; return fpresult; end function divide; -- division by a power of 2 function dividebyp2 ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable ulfract, urfract : UNSIGNED (fraction_width downto 0); variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED(exponent_width downto 0); -- result exponent variable fp_sign : STD_ULOGIC; -- sign of result variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- divisionbyp2 if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; classcase : case rfptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => if lfptype = pos_inf or lfptype = neg_inf then -- inf / inf -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else -- x / inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when pos_zero \| neg_zero => if lfptype = pos_zero or lfptype = neg_zero then -- 0 / 0 -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else report FLOAT_GENERIC_PKG'instance_name & "DIVIDEBYP2: Floating Point divide by zero" severity error; -- Infinity, define in 754-1985-7.2 fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when others => classcase2 : case lfptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => -- inf / x = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (exponent_width) := fp_sign; -- sign when pos_zero \| neg_zero => -- 0 / X = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (exponent_width) := fp_sign; -- sign when others => fp_sign := l(l'high) xor r(r'high); -- sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); -- right side break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); assert (or (urfract (fraction_width-1 downto 0)) = '0') report FLOAT_GENERIC_PKG'instance_name & "DIVIDEBYP2: " & "Dividebyp2 called with a non power of two divisor" severity error; rexpon := (exponl(exponl'high)&exponl) - (exponr(exponr'high)&exponr) - 1; -- normalize fpresult := normalize (fract => ulfract, expon => rexpon, sign => fp_sign, sticky => '1', fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => 0); end case classcase2; end case classcase; return fpresult; end function dividebyp2; -- Multiply accumulate result = lr + c function mac ( l, r, c : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine (mine(l'low, r'low), c'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum (maximum(l'high, r'high), c'high); -- length of FP output exponent variable lfptype, rfptype, cfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions variable fractx : UNSIGNED (fraction_width+guard downto 0); variable fractc, fracts : UNSIGNED (fraction_width+1+guard downto 0); variable rfract : UNSIGNED ((2(fraction_width))+1 downto 0); -- result fraction variable sfract, ufract : UNSIGNED (fraction_width+1+guard downto 0); -- result fraction variable exponl, exponr, exponc : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon, rexpon2 : SIGNED (exponent_width+1 downto 0); -- result exponent variable shifty : INTEGER; -- denormal shift variable shiftx : SIGNED (rexpon'range); -- shift fractions variable fp_sign : STD_ULOGIC; -- sign of result variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); variable cresize : UNRESOLVED_float (exponent_width downto -fraction_width - guard); variable leftright : BOOLEAN; -- left or right used variable sticky : STD_ULOGIC; -- Holds precision for rounding begin -- multiply if (fraction_width = 0 or l'length < 7 or r'length < 7 or c'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); cfptype := classfp (c, check_error); end if; if (lfptype = isx or rfptype = isx or cfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan or cfptype = nan or cfptype = quiet_nan) then -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (((lfptype = pos_inf or lfptype = neg_inf) and (rfptype = pos_zero or rfptype = neg_zero)) or ((rfptype = pos_inf or rfptype = neg_inf) and (lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf -- Return quiet NAN, IEEE754-1985-7.1,3 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = pos_inf or rfptype = pos_inf or lfptype = neg_inf or rfptype = neg_inf -- x * inf = inf or cfptype = neg_inf or cfptype = pos_inf) then -- x + inf = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); -- figure out the sign fpresult (exponent_width) := l(l'high) xor r(r'high); else fp_sign := l(l'high) xor r(r'high); -- figure out the sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked cresize := resize (arg => to_x01(c), exponent_width => exponent_width, fraction_width => -cresize'low, denormalize_in => denormalize, denormalize => denormalize); cfptype := classfp (cresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => fractl, expon => exponl); break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => fractr, expon => exponr); break_number ( arg => cresize, fptyp => cfptype, denormalize => denormalize, fract => fractx, expon => exponc); if (rfptype = pos_denormal or rfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractr, '1'); fractr := shift_left (fractr, shifty); elsif (lfptype = pos_denormal or lfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractl, '1'); fractl := shift_left (fractl, shifty); else shifty := 0; -- Note that a denormal number * a denormal number is always zero. end if; -- multiply rfract := fractl * fractr; -- Multiply the fraction -- add the exponents rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1; shiftx := rexpon - exponc; if shiftx < -fractl'high then rexpon2 := resize (exponc, rexpon2'length); fractc := "0" & fractx; fracts := (others => '0'); sticky := or (rfract); elsif shiftx < 0 then shiftx := - shiftx; fracts := shift_right (rfract (rfract'high downto rfract'high - fracts'length+1), to_integer(shiftx)); fractc := "0" & fractx; rexpon2 := resize (exponc, rexpon2'length); leftright := false; sticky := or (rfract (to_integer(shiftx)+rfract'high - fracts'length downto 0)); elsif shiftx = 0 then rexpon2 := resize (exponc, rexpon2'length); sticky := or (rfract (rfract'high - fractc'length downto 0)); if rfract (rfract'high downto rfract'high - fractc'length+1) > fractx then fractc := "0" & fractx; fracts := rfract (rfract'high downto rfract'high - fracts'length+1); leftright := false; else fractc := rfract (rfract'high downto rfract'high - fractc'length+1); fracts := "0" & fractx; leftright := true; end if; elsif shiftx > fractx'high then rexpon2 := rexpon; fracts := (others => '0'); fractc := rfract (rfract'high downto rfract'high - fractc'length+1); leftright := true; sticky := or (fractx & rfract (rfract'high - fractc'length downto 0)); else -- fractx'high > shiftx > 0 rexpon2 := rexpon; fracts := "0" & shift_right (fractx, to_integer (shiftx)); fractc := rfract (rfract'high downto rfract'high - fractc'length+1); leftright := true; sticky := or (fractx (to_integer (shiftx) downto 0) & rfract (rfract'high - fractc'length downto 0)); end if; fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB if fp_sign = to_X01(c(c'high)) then ufract := fractc + fracts; fp_sign := fp_sign; else -- signs are different ufract := fractc - fracts; -- always positive result if leftright then -- Figure out which sign to use fp_sign := fp_sign; else fp_sign := c(c'high); end if; end if; -- normalize fpresult := normalize (fract => ufract, expon => rexpon2, sign => fp_sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => guard); end if; return fpresult; end function mac; -- "rem" function function remainder ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant divguard : NATURAL := guard; -- division guard bits variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable ulfract, urfract : UNSIGNED (fraction_width downto 0); variable fractr, fractl : UNSIGNED (fraction_width+divguard downto 0); -- right variable rfract : UNSIGNED (fractr'range); -- result fraction variable sfract : UNSIGNED (fraction_width+divguard downto 0); -- result fraction variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width downto 0); -- result exponent variable fp_sign : STD_ULOGIC; -- sign of result variable shifty : INTEGER; -- denormal number shift variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- remainder if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan) or (rfptype = nan or rfptype = quiet_nan) -- Return quiet NAN, IEEE754-1985-7.1,1 or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x -- Return quiet NAN, IEEE754-1985-7.1,5 or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0 -- Return quiet NAN, IEEE754-1985-7.1,5 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (abs(l) < abs(r)) then fpresult := l; else fp_sign := to_X01(l(l'high)); -- sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked fractl := (others => '0'); break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); fractl (fraction_width+divguard downto divguard) := ulfract; -- right side fractr := (others => '0'); break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); fractr (fraction_width+divguard downto divguard) := urfract; rexpon := (exponr(exponr'high)&exponr); shifty := to_integer(exponl - rexpon); if (shifty > 0) then fractr := shift_right (fractr, shifty); rexpon := rexpon + shifty; end if; if (fractr /= 0) then -- rem rfract := fractl rem fractr; -- unsigned rem sfract := rfract (sfract'range); -- lower bits -- normalize fpresult := normalize (fract => sfract, expon => rexpon, sign => fp_sign, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => divguard); else -- If we shift "fractr" so far that it becomes zero, return zero. fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); end if; end if; return fpresult; end function remainder; -- "mod" function function modulo ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := - mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable remres : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- remainder if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan) or (rfptype = nan or rfptype = quiet_nan) -- Return quiet NAN, IEEE754-1985-7.1,1 or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x -- Return quiet NAN, IEEE754-1985-7.1,5 or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0 -- Return quiet NAN, IEEE754-1985-7.1,5 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else remres := remainder (l => abs(l), r => abs(r), round_style => round_style, guard => guard, check_error => false, denormalize => denormalize); -- MOD is the same as REM, but you do something different with -- negative values if (is_negative (l)) then remres := - remres; end if; if (is_negative (l) = is_negative (r) or remres = 0) then fpresult := remres; else fpresult := add (l => remres, r => r, round_style => round_style, guard => guard, check_error => false, denormalize => denormalize); end if; end if; return fpresult; end function modulo; -- Square root of a floating point number. Done using Newton's Iteration. function sqrt ( arg : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; constant guard : NATURAL := float_guard_bits; constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_float is constant fraction_width : NATURAL := guard-arg'low; -- length of FP output fraction constant exponent_width : NATURAL := arg'high; -- length of FP output exponent variable sign : STD_ULOGIC; variable fpresult : float (arg'range); variable fptype : valid_fpstate; variable iexpon : SIGNED(exponent_width-1 downto 0); -- exponents variable expon : SIGNED(exponent_width downto 0); -- exponents variable ufact : ufixed (0 downto arg'low); variable fact : ufixed (2 downto -fraction_width); -- fraction variable resb : ufixed (fact'high+1 downto fact'low); begin -- square root fptype := Classfp (arg, check_error); classcase : case fptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan \| -- Return quiet NAN, IEEE754-1985-7.1,1 neg_normal \| neg_denormal \| neg_inf => -- sqrt (neg) -- Return quiet NAN, IEEE754-1985-7.1.6 fpresult := qnanfp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when pos_inf => -- Sqrt (inf), return infinity fpresult := pos_inffp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when pos_zero => -- return 0 fpresult := zerofp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when neg_zero => -- IEEE754-1985-6.3 return -0 fpresult := neg_zerofp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when others => break_number (arg => arg, denormalize => denormalize, check_error => false, fract => ufact, expon => iexpon, sign => sign); expon := resize (iexpon+1, expon'length); -- get exponent fact := resize (ufact, fact'high, fact'low); if (expon(0) = '1') then fact := fact sla 1; -- * 2.0 end if; expon := shift_right (expon, 1); -- exponent/2 -- Newton's iteration - root := (1 + arg) / 2 resb := (fact + 1) sra 1; for j in 0 to fraction_width/4 loop -- root := (root + (arg/root))/2 resb := resize (arg => (resb + (fact/resb)) sra 1, left_index => resb'high, right_index => resb'low, round_style => fixed_truncate, overflow_style => fixed_wrap); end loop; fpresult := normalize (fract => resb, expon => expon-1, sign => '0', exponent_width => arg'high, fraction_width => -arg'low, round_style => round_style, denormalize => denormalize, nguard => guard); end case classcase; return fpresult; end function sqrt; function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN is -- Technically -0 should return "false", but I'm leaving that case out. begin return (to_x01(arg(arg'high)) = '1'); end function Is_Negative; -- compare functions -- =, /=, >=, <=, <, > function eq ( -- equal = l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable lfptype, rfptype : valid_fpstate; variable is_equal, is_unordered : BOOLEAN; constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- equal if (fraction_width = 0 or l'length < 7 or r'length < 7) then return false; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = neg_zero or lfptype = pos_zero) and (rfptype = neg_zero or rfptype = pos_zero) then is_equal := true; else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); is_equal := (to_slv(lresize) = to_slv(rresize)); end if; if (check_error) then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return is_equal and not is_unordered; end function eq; function lt ( -- less than < l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable expl, expr : UNSIGNED (exponent_width-1 downto 0); variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0); variable is_less_than, is_unordered : BOOLEAN; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then is_less_than := false; else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits expl := UNSIGNED(lresize(exponent_width-1 downto 0)); expr := UNSIGNED(rresize(exponent_width-1 downto 0)); if expl = expr then fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width))); fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width))); if to_x01(l(l'high)) = '0' then -- positive number is_less_than := (fractl < fractr); else is_less_than := (fractl > fractr); -- negative end if; else if to_x01(l(l'high)) = '0' then -- positive number is_less_than := (expl < expr); else is_less_than := (expl > expr); -- negative end if; end if; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); if (lfptype = neg_zero and rfptype = pos_zero) then is_less_than := false; -- -0 < 0 returns false. else is_less_than := (to_x01(l(l'high)) > to_x01(r(r'high))); end if; end if; end if; if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return is_less_than and not is_unordered; end function lt; function gt ( -- greater than > l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable expl, expr : UNSIGNED (exponent_width-1 downto 0); variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0); variable is_greater_than : BOOLEAN; variable is_unordered : BOOLEAN; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- greater_than if (fraction_width = 0 or l'length < 7 or r'length < 7) then is_greater_than := false; else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits expl := UNSIGNED(lresize(exponent_width-1 downto 0)); expr := UNSIGNED(rresize(exponent_width-1 downto 0)); if expl = expr then fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width))); fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width))); if to_x01(l(l'high)) = '0' then -- positive number is_greater_than := fractl > fractr; else is_greater_than := fractl < fractr; -- negative end if; else if to_x01(l(l'high)) = '0' then -- positive number is_greater_than := expl > expr; else is_greater_than := expl < expr; -- negative end if; end if; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); if (lfptype = pos_zero and rfptype = neg_zero) then is_greater_than := false; -- 0 > -0 returns false. else is_greater_than := to_x01(l(l'high)) < to_x01(r(r'high)); end if; end if; end if; if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return is_greater_than and not is_unordered; end function gt; -- purpose: /= function function ne ( -- not equal /= l, r : UNRESOLVED_float; constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable is_equal, is_unordered : BOOLEAN; begin is_equal := eq (l => l, r => r, check_error => false, denormalize => denormalize); if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return not (is_equal and not is_unordered); end function ne; function le ( -- less than or equal to <= l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable is_greater_than, is_unordered : BOOLEAN; begin is_greater_than := gt (l => l, r => r, check_error => false, denormalize => denormalize); if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return not is_greater_than and not is_unordered; end function le; function ge ( -- greater than or equal to >= l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable is_less_than, is_unordered : BOOLEAN; begin is_less_than := lt (l => l, r => r, check_error => false, denormalize => denormalize); if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return not is_less_than and not is_unordered; end function ge; function "?=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable is_equal, is_unordered : STD_ULOGIC; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- ?= if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else lfptype := classfp (l, float_check_error); rfptype := classfp (r, float_check_error); end if; if (lfptype = neg_zero or lfptype = pos_zero) and (rfptype = neg_zero or rfptype = pos_zero) then is_equal := '1'; else lresize := resize (arg => l, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); rresize := resize (arg => r, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); is_equal := to_sulv(lresize) ?= to_sulv(rresize); end if; if (float_check_error) then if (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan) then is_unordered := '1'; else is_unordered := '0'; end if; else is_unordered := '0'; end if; return is_equal and not is_unordered; end function "?="; function "?/=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable is_equal, is_unordered : STD_ULOGIC; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- ?/= if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else lfptype := classfp (l, float_check_error); rfptype := classfp (r, float_check_error); end if; if (lfptype = neg_zero or lfptype = pos_zero) and (rfptype = neg_zero or rfptype = pos_zero) then is_equal := '1'; else lresize := resize (arg => l, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); rresize := resize (arg => r, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); is_equal := to_sulv(lresize) ?= to_sulv(rresize); end if; if (float_check_error) then if (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan) then is_unordered := '1'; else is_unordered := '0'; end if; else is_unordered := '0'; end if; return not (is_equal and not is_unordered); end function "?/="; function "?>" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?>"": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l > r then return '1'; else return '0'; end if; end if; end function "?>"; function "?>=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?>="": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l >= r then return '1'; else return '0'; end if; end if; end function "?>="; function "?<" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?<"": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l < r then return '1'; else return '0'; end if; end if; end function "?<"; function "?<=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?<="": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l <= r then return '1'; else return '0'; end if; end if; end function "?<="; function std_match (L, R : UNRESOLVED_float) return BOOLEAN is begin if (L'high = R'high and L'low = R'low) then return std_match(to_sulv(L), to_sulv(R)); else report float_generic_pkg'instance_name & "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE" severity warning; return false; end if; end function std_match; function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is begin for_loop : for i in arg'reverse_range loop if arg(i) ?= y then return i; end if; end loop; return arg'high+1; -- return out of bounds 'high end function find_rightmost; function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is begin for_loop : for i in arg'range loop if arg(i) ?= y then return i; end if; end loop; return arg'low-1; -- return out of bounds 'low end function find_leftmost; -- These override the defaults for the compare operators. function "=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return eq(l, r); end function "="; function "/=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return ne(l, r); end function "/="; function ">=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return ge(l, r); end function ">="; function "<=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return le(l, r); end function "<="; function ">" (l, r : UNRESOLVED_float) return BOOLEAN is begin return gt(l, r); end function ">"; function "<" (l, r : UNRESOLVED_float) return BOOLEAN is begin return lt(l, r); end function "<"; -- purpose: maximum of two numbers (overrides default) function maximum ( L, R : UNRESOLVED_float) return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin if ((L'length < 1) or (R'length < 1)) then return NAFP; end if; lresize := resize (l, exponent_width, fraction_width); rresize := resize (r, exponent_width, fraction_width); if lresize > rresize then return lresize; else return rresize; end if; end function maximum; function minimum ( L, R : UNRESOLVED_float) return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin if ((L'length < 1) or (R'length < 1)) then return NAFP; end if; lresize := resize (l, exponent_width, fraction_width); rresize := resize (r, exponent_width, fraction_width); if lresize > rresize then return rresize; else return lresize; end if; end function minimum; ----------------------------------------------------------------------------- -- conversion functions ----------------------------------------------------------------------------- -- Converts a floating point number of one format into another format function resize ( arg : UNRESOLVED_float; -- Floating point input constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant in_fraction_width : NATURAL := -arg'low; -- length of FP output fraction constant in_exponent_width : NATURAL := arg'high; -- length of FP output exponent variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result value variable fptype : valid_fpstate; variable expon_in : SIGNED (in_exponent_width-1 downto 0); variable fract_in : UNSIGNED (in_fraction_width downto 0); variable round : BOOLEAN; variable expon_out : SIGNED (exponent_width-1 downto 0); -- output fract variable fract_out : UNSIGNED (fraction_width downto 0); -- output fract variable passguard : NATURAL; begin fptype := classfp(arg, check_error); if ((fptype = pos_denormal or fptype = neg_denormal) and denormalize_in and (in_exponent_width < exponent_width or in_fraction_width < fraction_width)) or in_exponent_width > exponent_width or in_fraction_width > fraction_width then -- size reduction classcase : case fptype is when isx => result := (others => 'X'); when nan \| quiet_nan => result := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf => result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); when neg_inf => result := neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_zero \| neg_zero => result := zerofp (fraction_width => fraction_width, -- hate -0 exponent_width => exponent_width); when others => break_number ( arg => arg, fptyp => fptype, denormalize => denormalize_in, fract => fract_in, expon => expon_in); if fraction_width > in_fraction_width and denormalize_in then -- You only get here if you have a denormal input fract_out := (others => '0'); -- pad with zeros fract_out (fraction_width downto fraction_width - in_fraction_width) := fract_in; result := normalize ( fract => fract_out, expon => expon_in, sign => arg(arg'high), fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => 0); else result := normalize ( fract => fract_in, expon => expon_in, sign => arg(arg'high), fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => in_fraction_width - fraction_width); end if; end case classcase; else -- size increase or the same size if exponent_width > in_exponent_width then expon_in := SIGNED(arg (in_exponent_width-1 downto 0)); if fptype = pos_zero or fptype = neg_zero then result (exponent_width-1 downto 0) := (others => '0'); elsif expon_in = -1 then -- inf or nan (shorts out check_error) result (exponent_width-1 downto 0) := (others => '1'); else -- invert top BIT expon_in(expon_in'high) := not expon_in(expon_in'high); expon_out := resize (expon_in, expon_out'length); -- signed expand -- Flip it back. expon_out(expon_out'high) := not expon_out(expon_out'high); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon_out); end if; result (exponent_width) := arg (in_exponent_width); -- sign else -- exponent_width = in_exponent_width result (exponent_width downto 0) := arg (in_exponent_width downto 0); end if; if fraction_width > in_fraction_width then result (-1 downto -fraction_width) := (others => '0'); -- zeros result (-1 downto -in_fraction_width) := arg (-1 downto -in_fraction_width); else -- fraction_width = in_fraciton_width result (-1 downto -fraction_width) := arg (-1 downto -in_fraction_width); end if; end if; return result; end function resize; function resize ( arg : UNRESOLVED_float; -- floating point input size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := resize (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); return result; end if; end function resize; function to_float32 ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float32 is begin return resize (arg => arg, exponent_width => float32'high, fraction_width => -float32'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); end function to_float32; function to_float64 ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float64 is begin return resize (arg => arg, exponent_width => float64'high, fraction_width => -float64'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); end function to_float64; function to_float128 ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float128 is begin return resize (arg => arg, exponent_width => float128'high, fraction_width => -float128'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); end function to_float128; -- to_float (Real) -- typically not Synthesizable unless the input is a constant. function to_float ( arg : REAL; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arg_real : REAL; -- Real version of argument variable validfp : boundary_type; -- Check for valid results variable exp : INTEGER; -- Integer version of exponent variable expon : UNSIGNED (exponent_width - 1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fract : UNSIGNED (fraction_width-1 downto 0); variable frac : REAL; -- Real version of fraction constant roundfrac : REAL := 2.0 ** (-2 - fract'high); -- used for rounding variable round : BOOLEAN; -- to round or not to round begin result := (others => '0'); arg_real := arg; if arg_real < 0.0 then result (exponent_width) := '1'; arg_real := - arg_real; -- Make it positive. else result (exponent_width) := '0'; end if; test_boundary (arg => arg_real, fraction_width => fraction_width, exponent_width => exponent_width, denormalize => denormalize, btype => validfp, log2i => exp); if validfp = zero then return result; -- Result initialized to "0". elsif validfp = infinity then result (exponent_width - 1 downto 0) := (others => '1'); -- Exponent all "1" -- return infinity. return result; else if validfp = denormal then -- Exponent will default to "0". expon := (others => '0'); frac := arg_real * (2.0 (to_integer(expon_base)-1)); else -- Number less than 1. "normal" number expon := UNSIGNED (to_signed (exp-1, exponent_width)); expon(exponent_width-1) := not expon(exponent_width-1); frac := (arg_real / 2.0 exp) - 1.0; -- Number less than 1. end if; for i in 0 to fract'high loop if frac >= 2.0 (-1 - i) then fract (fract'high - i) := '1'; frac := frac - 2.0 (-1 - i); else fract (fract'high - i) := '0'; end if; end loop; round := false; case round_style is when round_nearest => if frac > roundfrac or ((frac = roundfrac) and fract(0) = '1') then round := true; end if; when round_inf => if frac /= 0.0 and result(exponent_width) = '0' then round := true; end if; when round_neginf => if frac /= 0.0 and result(exponent_width) = '1' then round := true; end if; when others => null; -- don't round end case; if (round) then if and(fract) = '1' then -- fraction is all "1" expon := expon + 1; fract := (others => '0'); else fract := fract + 1; end if; end if; result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(fract); return result; end if; end function to_float; -- to_float (Integer) function to_float ( arg : INTEGER; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arg_int : NATURAL; -- Natural version of argument variable expon : SIGNED (exponent_width-1 downto 0); variable exptmp : SIGNED (exponent_width-1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fract : UNSIGNED (fraction_width-1 downto 0) := (others => '0'); variable fracttmp : UNSIGNED (fraction_width-1 downto 0); variable round : BOOLEAN; variable shift : NATURAL; variable shiftr : NATURAL; variable roundfrac : NATURAL; -- used in rounding begin if arg < 0 then result (exponent_width) := '1'; arg_int := -arg; -- Make it positive. else result (exponent_width) := '0'; arg_int := arg; end if; if arg_int = 0 then result := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else -- If the number is larger than we can represent in this number system -- we need to return infinity. shift := log2(arg_int); if shift > to_integer(expon_base) then -- worry about infinity if result (exponent_width) = '0' then result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else -- return negative infinity. result := neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); end if; else -- Normal number (can't be denormal) -- Compute Exponent expon := to_signed (shift-1, expon'length); -- positive fraction. -- Compute Fraction arg_int := arg_int - 2shift; -- Subtract off the 1.0 shiftr := shift; for I in fract'high downto maximum (fract'high - shift + 1, 0) loop shiftr := shiftr - 1; if (arg_int >= 2shiftr) then arg_int := arg_int - 2shiftr; fract(I) := '1'; else fract(I) := '0'; end if; end loop; -- Rounding routine round := false; if arg_int > 0 then roundfrac := 2(shiftr-1); case round_style is when round_nearest => if arg_int > roundfrac or ((arg_int = roundfrac) and fract(0) = '1') then round := true; end if; when round_inf => if arg_int /= 0 and result (exponent_width) = '0' then round := true; end if; when round_neginf => if arg_int /= 0 and result (exponent_width) = '1' then round := true; end if; when others => null; end case; end if; if round then fp_round(fract_in => fract, expon_in => expon, fract_out => fracttmp, expon_out => exptmp); fract := fracttmp; expon := exptmp; end if; -- Put the number together and return expon(exponent_width-1) := not expon(exponent_width-1); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(fract); end if; end if; return result; end function to_float; -- to_float (unsigned) function to_float ( arg : UNRESOLVED_UNSIGNED; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG; variable sarg : SIGNED (ARG_LEFT+1 downto 0); -- signed version of arg begin if arg'length < 1 then return NAFP; end if; sarg (XARG'range) := SIGNED (XARG); sarg (sarg'high) := '0'; result := to_float (arg => sarg, exponent_width => exponent_width, fraction_width => fraction_width, round_style => round_style); return result; end function to_float; -- to_float (signed) function to_float ( arg : UNRESOLVED_SIGNED; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : SIGNED(ARG_LEFT downto 0) is ARG; variable arg_int : UNSIGNED(xarg'range); -- Real version of argument variable argb2 : UNSIGNED(xarg'high/2 downto 0); -- log2 of input variable rexp : SIGNED (exponent_width - 1 downto 0); variable exp : SIGNED (exponent_width - 1 downto 0); -- signed version of exp. variable expon : UNSIGNED (exponent_width - 1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable round : BOOLEAN; variable fract : UNSIGNED (fraction_width-1 downto 0); variable rfract : UNSIGNED (fraction_width-1 downto 0); variable sign : STD_ULOGIC; -- sign bit begin if arg'length < 1 then return NAFP; end if; if Is_X (xarg) then result := (others => 'X'); elsif (xarg = 0) then result := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else -- Normal number (can't be denormal) sign := to_X01(xarg (xarg'high)); arg_int := UNSIGNED(abs (to_01(xarg))); -- Compute Exponent argb2 := to_unsigned(find_leftmost(arg_int, '1'), argb2'length); -- Log2 if argb2 > UNSIGNED(expon_base) then result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); result (exponent_width) := sign; else exp := SIGNED(resize(argb2, exp'length)); arg_int := shift_left (arg_int, arg_int'high-to_integer(exp)); if (arg_int'high > fraction_width) then fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)); round := check_round ( fract_in => fract (0), sign => sign, remainder => arg_int((arg_int'high-fraction_width-1) downto 0), round_style => round_style); if round then fp_round(fract_in => fract, expon_in => exp, fract_out => rfract, expon_out => rexp); else rfract := fract; rexp := exp; end if; else rexp := exp; rfract := (others => '0'); rfract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) := arg_int (arg_int'high-1 downto 0); end if; result (exponent_width) := sign; expon := UNSIGNED (rexp-1); expon(exponent_width-1) := not expon(exponent_width-1); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(rfract); end if; end if; return result; end function to_float; -- std_logic_vector to float function to_float ( arg : STD_ULOGIC_VECTOR; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction return UNRESOLVED_float is variable fpvar : UNRESOLVED_float (exponent_width downto -fraction_width); begin if arg'length < 1 then return NAFP; end if; fpvar := UNRESOLVED_float(arg); return fpvar; end function to_float; -- purpose: converts a ufixed to a floating point function to_float ( arg : UNRESOLVED_ufixed; -- unsigned fixed point input constant exponent_width : NATURAL := float_exponent_width; -- width of exponent constant fraction_width : NATURAL := float_fraction_width; -- width of fraction constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions return UNRESOLVED_float is variable sarg : sfixed (arg'high+1 downto arg'low); -- Signed version of arg variable result : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- function to_float if (arg'length < 1) then return NAFP; end if; sarg (arg'range) := sfixed (arg); sarg (sarg'high) := '0'; result := to_float (arg => sarg, exponent_width => exponent_width, fraction_width => fraction_width, round_style => round_style, denormalize => denormalize); return result; end function to_float; function to_float ( arg : UNRESOLVED_sfixed; -- signed fixed point constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- rounding option return UNRESOLVED_float is constant integer_width : INTEGER := arg'high; constant in_fraction_width : INTEGER := arg'low; variable xresult : sfixed (integer_width downto in_fraction_width); variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arg_int : UNSIGNED(integer_width - in_fraction_width - 1 downto 0); -- signed version of argument variable argx : SIGNED (integer_width - in_fraction_width downto 0); variable exp, exptmp : SIGNED (exponent_width downto 0); variable expon : UNSIGNED (exponent_width - 1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) := (others => '0'); variable round : BOOLEAN := false; begin if (arg'length < 1) then return NAFP; end if; xresult := to_01(arg, 'X'); argx := SIGNED(to_slv(xresult)); if (Is_X (arg)) then result := (others => 'X'); elsif (argx = 0) then result := (others => '0'); else result := (others => '0'); -- zero out the result if argx(argx'left) = '1' then -- toss the sign bit result (exponent_width) := '1'; -- Negative number argx := -argx; -- Make it positive. else result (exponent_width) := '0'; end if; arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (argx(arg_int'range)))); -- Compute Exponent exp := to_signed(find_leftmost(arg_int, '1'), exp'length); -- Log2 if exp + in_fraction_width > expon_base then -- return infinity result (-1 downto -fraction_width) := (others => '0'); result (exponent_width -1 downto 0) := (others => '1'); return result; elsif (denormalize and (exp + in_fraction_width <= -resize(expon_base, exp'length))) then exp := -resize(expon_base, exp'length); -- shift by a constant arg_int := shift_left (arg_int, (arg_int'high + to_integer(expon_base) + in_fraction_width - 1)); if (arg_int'high > fraction_width) then fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)); round := check_round ( fract_in => arg_int(arg_int'high-fraction_width), sign => result(result'high), remainder => arg_int((arg_int'high-fraction_width-1) downto 0), round_style => round_style); if (round) then fp_round (fract_in => arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)), expon_in => exp, fract_out => fract, expon_out => exptmp); exp := exptmp; end if; else fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) := arg_int (arg_int'high-1 downto 0); end if; else arg_int := shift_left (arg_int, arg_int'high-to_integer(exp)); exp := exp + in_fraction_width; if (arg_int'high > fraction_width) then fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)); round := check_round ( fract_in => fract(0), sign => result(result'high), remainder => arg_int((arg_int'high-fraction_width-1) downto 0), round_style => round_style); if (round) then fp_round (fract_in => fract, expon_in => exp, fract_out => fracttmp, expon_out => exptmp); fract := fracttmp; exp := exptmp; end if; else fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) := arg_int (arg_int'high-1 downto 0); end if; end if; expon := UNSIGNED (resize(exp-1, exponent_width)); expon(exponent_width-1) := not expon(exponent_width-1); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(fract); end if; return result; end function to_float; -- size_res functions -- Integer to float function to_float ( arg : INTEGER; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style); return result; end if; end function to_float; -- real to float function to_float ( arg : REAL; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, denormalize => denormalize); return result; end if; end function to_float; -- unsigned to float function to_float ( arg : UNRESOLVED_UNSIGNED; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style); return result; end if; end function to_float; -- signed to float function to_float ( arg : UNRESOLVED_SIGNED; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style) -- rounding return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style); return result; end if; end function to_float; -- std_ulogic_vector to float function to_float ( arg : STD_ULOGIC_VECTOR; size_res : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low); return result; end if; end function to_float; -- unsigned fixed point to float function to_float ( arg : UNRESOLVED_ufixed; -- unsigned fixed point input size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, denormalize => denormalize); return result; end if; end function to_float; -- signed fixed point to float function to_float ( arg : UNRESOLVED_sfixed; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, denormalize => denormalize); return result; end if; end function to_float; -- to_integer (float) function to_integer ( arg : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return INTEGER is variable validfp : valid_fpstate; -- Valid FP state variable frac : UNSIGNED (-arg'low downto 0); -- Fraction variable fract : UNSIGNED (1-arg'low downto 0); -- Fraction variable expon : SIGNED (arg'high-1 downto 0); variable isign : STD_ULOGIC; -- internal version of sign variable round : STD_ULOGIC; -- is rounding needed? variable result : INTEGER; variable base : INTEGER; -- Integer exponent begin validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan \| pos_zero \| neg_zero \| pos_denormal \| neg_denormal => result := 0; -- return 0 when pos_inf => result := INTEGER'high; when neg_inf => result := INTEGER'low; when others => break_number ( arg => arg, fptyp => validfp, denormalize => false, fract => frac, expon => expon); fract (fract'high) := '0'; -- Add extra bit for 0.6 case fract (fract'high-1 downto 0) := frac; isign := to_x01 (arg (arg'high)); base := to_integer (expon) + 1; if base < -1 then result := 0; elsif base >= frac'high then result := to_integer (fract) * 2(base - frac'high); else -- We need to round if base = -1 then -- trap for 0.6 case. result := 0; else result := to_integer (fract (frac'high downto frac'high-base)); end if; -- rounding routine case round_style is when round_nearest => if frac'high - base > 1 then round := fract (frac'high - base - 1) and (fract (frac'high - base) or (or (fract (frac'high - base - 2 downto 0)))); else round := fract (frac'high - base - 1) and fract (frac'high - base); end if; when round_inf => round := fract(frac'high - base - 1) and not isign; when round_neginf => round := fract(frac'high - base - 1) and isign; when others => round := '0'; end case; if round = '1' then result := result + 1; end if; end if; if isign = '1' then result := - result; end if; end case classcase; return result; end function to_integer; -- to_unsigned (float) function to_unsigned ( arg : UNRESOLVED_float; -- floating point input constant size : NATURAL; -- length of output constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_UNSIGNED is variable validfp : valid_fpstate; -- Valid FP state variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction variable sign : STD_ULOGIC; -- not used begin validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan => frac := (others => 'X'); when pos_zero \| neg_inf \| neg_zero \| neg_normal \| pos_denormal \| neg_denormal => frac := (others => '0'); -- return 0 when pos_inf => frac := (others => '1'); when others => float_to_unsigned ( arg => arg, frac => frac, sign => sign, denormalize => false, bias => 0, round_style => round_style); end case classcase; return (frac); end function to_unsigned; -- to_signed (float) function to_signed ( arg : UNRESOLVED_float; -- floating point input constant size : NATURAL; -- length of output constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_SIGNED is variable sign : STD_ULOGIC; -- true if negative variable validfp : valid_fpstate; -- Valid FP state variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction variable result : UNRESOLVED_SIGNED (size-1 downto 0); begin validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan => result := (others => 'X'); when pos_zero \| neg_zero \| pos_denormal \| neg_denormal => result := (others => '0'); -- return 0 when pos_inf => result := (others => '1'); result (result'high) := '0'; when neg_inf => result := (others => '0'); result (result'high) := '1'; when others => float_to_unsigned ( arg => arg, sign => sign, frac => frac, denormalize => false, bias => 0, round_style => round_style); result (size-1) := '0'; result (size-2 downto 0) := UNRESOLVED_SIGNED(frac (size-2 downto 0)); if sign = '1' then -- Because the most negative signed number is 1 less than the most -- positive signed number, we need this code. if frac(frac'high) = '1' then -- return most negative number result := (others => '0'); result (result'high) := '1'; else result := -result; end if; else if frac(frac'high) = '1' then -- return most positive number result := (others => '1'); result (result'high) := '0'; end if; end if; end case classcase; return result; end function to_signed; -- purpose: Converts a float to ufixed function to_ufixed ( arg : UNRESOLVED_float; -- fp input constant left_index : INTEGER; -- integer part constant right_index : INTEGER; -- fraction part constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_ufixed is constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent constant size : INTEGER := left_index - right_index + 4; -- unsigned size variable expon_base : INTEGER; -- exponent offset variable validfp : valid_fpstate; -- Valid FP state variable exp : INTEGER; -- Exponent variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent -- Base to divide fraction by variable frac : UNSIGNED (size-1 downto 0) := (others => '0'); -- Fraction variable frac_shift : UNSIGNED (size-1 downto 0); -- Fraction shifted variable shift : INTEGER; variable result_big : UNRESOLVED_ufixed (left_index downto right_index-3); variable result : UNRESOLVED_ufixed (left_index downto right_index); -- result begin -- function to_ufixed validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan => frac := (others => 'X'); when pos_zero \| neg_inf \| neg_zero \| neg_normal \| neg_denormal => frac := (others => '0'); -- return 0 when pos_inf => frac := (others => '1'); -- always saturate when others => expon_base := 2(exponent_width-1) -1; -- exponent offset -- Figure out the fraction if (validfp = pos_denormal) and denormalize then exp := -expon_base +1; frac (frac'high) := '0'; -- Remove the "1.0". else -- exponent /= '0', normal floating point expon := UNSIGNED(arg (exponent_width-1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (SIGNED(expon)) +1; frac (frac'high) := '1'; -- Add the "1.0". end if; shift := (frac'high - 3 + right_index) - exp; if fraction_width > frac'high then -- Can only use size-2 bits frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto -frac'high))); else -- can use all bits frac (frac'high-1 downto frac'high-fraction_width) := UNSIGNED (to_slv (arg(-1 downto -fraction_width))); end if; frac_shift := frac srl shift; if shift < 0 then -- Overflow frac := (others => '1'); else frac := frac_shift; end if; end case classcase; result_big := to_ufixed ( arg => STD_ULOGIC_VECTOR(frac), left_index => left_index, right_index => (right_index-3)); result := resize (arg => result_big, left_index => left_index, right_index => right_index, round_style => round_style, overflow_style => overflow_style); return result; end function to_ufixed; -- purpose: Converts a float to sfixed function to_sfixed ( arg : UNRESOLVED_float; -- fp input constant left_index : INTEGER; -- integer part constant right_index : INTEGER; -- fraction part constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_sfixed is constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent constant size : INTEGER := left_index - right_index + 4; -- unsigned size variable expon_base : INTEGER; -- exponent offset variable validfp : valid_fpstate; -- Valid FP state variable exp : INTEGER; -- Exponent variable sign : BOOLEAN; -- true if negative variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent -- Base to divide fraction by variable frac : UNSIGNED (size-2 downto 0) := (others => '0'); -- Fraction variable frac_shift : UNSIGNED (size-2 downto 0); -- Fraction shifted variable shift : INTEGER; variable rsigned : SIGNED (size-1 downto 0); -- signed version of result variable result_big : UNRESOLVED_sfixed (left_index downto right_index-3); variable result : UNRESOLVED_sfixed (left_index downto right_index) := (others => '0'); -- result begin -- function to_sfixed validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan => result := (others => 'X'); when pos_zero \| neg_zero => result := (others => '0'); -- return 0 when neg_inf => result (left_index) := '1'; -- return smallest negative number when pos_inf => result := (others => '1'); -- return largest number result (left_index) := '0'; when others => expon_base := 2(exponent_width-1) -1; -- exponent offset if arg(exponent_width) = '0' then sign := false; else sign := true; end if; -- Figure out the fraction if (validfp = pos_denormal or validfp = neg_denormal) and denormalize then exp := -expon_base +1; frac (frac'high) := '0'; -- Add the "1.0". else -- exponent /= '0', normal floating point expon := UNSIGNED(arg (exponent_width-1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (SIGNED(expon)) +1; frac (frac'high) := '1'; -- Add the "1.0". end if; shift := (frac'high - 3 + right_index) - exp; if fraction_width > frac'high then -- Can only use size-2 bits frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto -frac'high))); else -- can use all bits frac (frac'high-1 downto frac'high-fraction_width) := UNSIGNED (to_slv (arg(-1 downto -fraction_width))); end if; frac_shift := frac srl shift; if shift < 0 then -- Overflow frac := (others => '1'); else frac := frac_shift; end if; if not sign then rsigned := SIGNED("0" & frac); else rsigned := -(SIGNED("0" & frac)); end if; result_big := to_sfixed ( arg => STD_LOGIC_VECTOR(rsigned), left_index => left_index, right_index => (right_index-3)); result := resize (arg => result_big, left_index => left_index, right_index => right_index, round_style => round_style, overflow_style => overflow_style); end case classcase; return result; end function to_sfixed; -- size_res versions -- float to unsigned function to_unsigned ( arg : UNRESOLVED_float; -- floating point input size_res : UNRESOLVED_UNSIGNED; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_UNSIGNED is variable result : UNRESOLVED_UNSIGNED (size_res'range); begin if (SIZE_RES'length = 0) then return result; else result := to_unsigned ( arg => arg, size => size_res'length, round_style => round_style, check_error => check_error); return result; end if; end function to_unsigned; -- float to signed function to_signed ( arg : UNRESOLVED_float; -- floating point input size_res : UNRESOLVED_SIGNED; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_SIGNED is variable result : UNRESOLVED_SIGNED (size_res'range); begin if (SIZE_RES'length = 0) then return result; else result := to_signed ( arg => arg, size => size_res'length, round_style => round_style, check_error => check_error); return result; end if; end function to_signed; -- purpose: Converts a float to unsigned fixed point function to_ufixed ( arg : UNRESOLVED_float; -- fp input size_res : UNRESOLVED_ufixed; constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_ufixed is variable result : UNRESOLVED_ufixed (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_ufixed ( arg => arg, left_index => size_res'high, right_index => size_res'low, overflow_style => overflow_style, round_style => round_style, check_error => check_error, denormalize => denormalize); return result; end if; end function to_ufixed; -- float to signed fixed point function to_sfixed ( arg : UNRESOLVED_float; -- fp input size_res : UNRESOLVED_sfixed; constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_sfixed is variable result : UNRESOLVED_sfixed (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_sfixed ( arg => arg, left_index => size_res'high, right_index => size_res'low, overflow_style => overflow_style, round_style => round_style, check_error => check_error, denormalize => denormalize); return result; end if; end function to_sfixed; -- to_real (float) -- typically not Synthesizable unless the input is a constant. function to_real ( arg : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return REAL is constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent variable sign : REAL; -- Sign, + or - 1 variable exp : INTEGER; -- Exponent variable expon_base : INTEGER; -- exponent offset variable frac : REAL := 0.0; -- Fraction variable validfp : valid_fpstate; -- Valid FP state variable expon : UNSIGNED (exponent_width - 1 downto 0) := (others => '1'); -- Vectorized exponent begin validfp := classfp (arg, check_error); classcase : case validfp is when isx \| pos_zero \| neg_zero \| nan \| quiet_nan => return 0.0; when neg_inf => return REAL'low; -- Negative infinity. when pos_inf => return REAL'high; -- Positive infinity when others => expon_base := 2(exponent_width-1) -1; if to_X01(arg(exponent_width)) = '0' then sign := 1.0; else sign := -1.0; end if; -- Figure out the fraction for i in 0 to fraction_width-1 loop if to_X01(arg (-1 - i)) = '1' then frac := frac + (2.0 *(-1 - i)); end if; end loop; -- i if validfp = pos_normal or validfp = neg_normal or not denormalize then -- exponent /= '0', normal floating point expon := UNSIGNED(arg (exponent_width-1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (SIGNED(expon)) +1; sign := sign (2.0 ** exp) * (1.0 + frac); else -- exponent = '0', IEEE extended floating point exp := 1 - expon_base; sign := sign * (2.0 ** exp) * frac; end if; return sign; end case classcase; end function to_real; -- For Verilog compatability function realtobits (arg : REAL) return STD_ULOGIC_VECTOR is variable result : float64; -- 64 bit floating point begin result := to_float (arg => arg, exponent_width => float64'high, fraction_width => -float64'low); return to_sulv (result); end function realtobits; function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL is variable arg64 : float64; -- arg converted to float begin arg64 := to_float (arg => arg, exponent_width => float64'high, fraction_width => -float64'low); return to_real (arg64); end function bitstoreal; -- purpose: Removes meta-logical values from FP string function to_01 ( arg : UNRESOLVED_float; -- floating point input XMAP : STD_LOGIC := '0') return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin -- function to_01 if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_01: null detected, returning NULL" severity warning; return NAFP; end if; result := UNRESOLVED_float (STD_LOGIC_VECTOR(to_01(UNSIGNED(to_slv(arg)), XMAP))); return result; end function to_01; function Is_X (arg : UNRESOLVED_float) return BOOLEAN is begin return Is_X (to_slv(arg)); end function Is_X; function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_X01: null detected, returning NULL" severity warning; return NAFP; else result := UNRESOLVED_float (to_X01(to_slv(arg))); return result; end if; end function to_X01; function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_X01Z: null detected, returning NULL" severity warning; return NAFP; else result := UNRESOLVED_float (to_X01Z(to_slv(arg))); return result; end if; end function to_X01Z; function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_UX01: null detected, returning NULL" severity warning; return NAFP; else result := UNRESOLVED_float (to_UX01(to_slv(arg))); return result; end if; end function to_UX01; -- These allows the base math functions to use the default values -- of their parameters. Thus they do full IEEE floating point. function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return add (l, r); end function "+"; function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return subtract (l, r); end function "-"; function "" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return multiply (l, r); end function ""; function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return divide (l, r); end function "/"; function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return remainder (l, r); end function "rem"; function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return modulo (l, r); end function "mod"; -- overloaded versions function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return add (l, r_float); end function "+"; function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return add (l_float, r); end function "+"; function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return add (l, r_float); end function "+"; function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return add (l_float, r); end function "+"; function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return subtract (l, r_float); end function "-"; function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return subtract (l_float, r); end function "-"; function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return subtract (l, r_float); end function "-"; function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return subtract (l_float, r); end function "-"; function "" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return multiply (l, r_float); end function ""; function "" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return multiply (l_float, r); end function ""; function "" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return multiply (l, r_float); end function ""; function "" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return multiply (l_float, r); end function ""; function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return divide (l, r_float); end function "/"; function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return divide (l_float, r); end function "/"; function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return divide (l, r_float); end function "/"; function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return divide (l_float, r); end function "/"; function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return remainder (l, r_float); end function "rem"; function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return remainder (l_float, r); end function "rem"; function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return remainder (l, r_float); end function "rem"; function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return remainder (l_float, r); end function "rem"; function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return modulo (l, r_float); end function "mod"; function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return modulo (l_float, r); end function "mod"; function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return modulo (l, r_float); end function "mod"; function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return modulo (l_float, r); end function "mod"; function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return eq (l, r_float); end function "="; function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ne (l, r_float); end function "/="; function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ge (l, r_float); end function ">="; function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return le (l, r_float); end function "<="; function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return gt (l, r_float); end function ">"; function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return lt (l, r_float); end function "<"; function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return eq (l_float, r); end function "="; function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ne (l_float, r); end function "/="; function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ge (l_float, r); end function ">="; function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return le (l_float, r); end function "<="; function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return gt (l_float, r); end function ">"; function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return lt (l_float, r); end function "<"; function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return eq (l, r_float); end function "="; function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ne (l, r_float); end function "/="; function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ge (l, r_float); end function ">="; function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return le (l, r_float); end function "<="; function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return gt (l, r_float); end function ">"; function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return lt (l, r_float); end function "<"; function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return eq (l_float, r); end function "="; function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ne (l_float, r); end function "/="; function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ge (l_float, r); end function ">="; function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return le (l_float, r); end function "<="; function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return gt (l_float, r); end function ">"; function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return lt (l_float, r); end function "<"; -- ?= overloads function "?=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?= r_float; end function "?="; function "?/=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?/= r_float; end function "?/="; function "?>" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?> r_float; end function "?>"; function "?>=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?>= r_float; end function "?>="; function "?<" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?< r_float; end function "?<"; function "?<=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?<= r_float; end function "?<="; -- real and float function "?=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?= r; end function "?="; function "?/=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?/= r; end function "?/="; function "?>" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?> r; end function "?>"; function "?>=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?>= r; end function "?>="; function "?<" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?< r; end function "?<"; function "?<=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?<= r; end function "?<="; -- ?= overloads function "?=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?= r_float; end function "?="; function "?/=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?/= r_float; end function "?/="; function "?>" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?> r_float; end function "?>"; function "?>=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?>= r_float; end function "?>="; function "?<" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?< r_float; end function "?<"; function "?<=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?<= r_float; end function "?<="; -- integer and float function "?=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?= r; end function "?="; function "?/=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?/= r; end function "?/="; function "?>" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?> r; end function "?>"; function "?>=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?>= r; end function "?>="; function "?<" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?< r; end function "?<"; function "?<=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?<= r; end function "?<="; -- minimum and maximum overloads function minimum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return minimum (l, r_float); end function minimum; function maximum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return maximum (l, r_float); end function maximum; function minimum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return minimum (l_float, r); end function minimum; function maximum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return maximum (l_float, r); end function maximum; function minimum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return minimum (l, r_float); end function minimum; function maximum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return maximum (l, r_float); end function maximum; function minimum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return minimum (l_float, r); end function minimum; function maximum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return maximum (l_float, r); end function maximum; ---------------------------------------------------------------------------- -- logical functions ---------------------------------------------------------------------------- function "not" (L : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin RESULT := not to_sulv(L); return to_float (RESULT, L'high, -L'low); end function "not"; function "and" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) and to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """and"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "and"; function "or" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) or to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """or"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "or"; function "nand" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) nand to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """nand"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "nand"; function "nor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) nor to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """nor"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "nor"; function "xor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) xor to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """xor"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "xor"; function "xnor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) xnor to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """xnor"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "xnor"; -- Vector and std_ulogic functions, same as functions in numeric_std function "and" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L and to_sulv(R)); return result; end function "and"; function "and" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) and R); return result; end function "and"; function "or" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L or to_sulv(R)); return result; end function "or"; function "or" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) or R); return result; end function "or"; function "nand" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L nand to_sulv(R)); return result; end function "nand"; function "nand" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) nand R); return result; end function "nand"; function "nor" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L nor to_sulv(R)); return result; end function "nor"; function "nor" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) nor R); return result; end function "nor"; function "xor" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L xor to_sulv(R)); return result; end function "xor"; function "xor" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) xor R); return result; end function "xor"; function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L xnor to_sulv(R)); return result; end function "xnor"; function "xnor" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) xnor R); return result; end function "xnor"; -- Reduction operators, same as numeric_std functions function "and" (l : UNRESOLVED_float) return STD_ULOGIC is begin return and to_sulv(l); end function "and"; function "nand" (l : UNRESOLVED_float) return STD_ULOGIC is begin return nand to_sulv(l); end function "nand"; function "or" (l : UNRESOLVED_float) return STD_ULOGIC is begin return or to_sulv(l); end function "or"; function "nor" (l : UNRESOLVED_float) return STD_ULOGIC is begin return nor to_sulv(l); end function "nor"; function "xor" (l : UNRESOLVED_float) return STD_ULOGIC is begin return xor to_sulv(l); end function "xor"; function "xnor" (l : UNRESOLVED_float) return STD_ULOGIC is begin return xnor to_sulv(l); end function "xnor"; ----------------------------------------------------------------------------- -- Recommended Functions from the IEEE 754 Appendix ----------------------------------------------------------------------------- -- returns x with the sign of y. function Copysign ( x, y : UNRESOLVED_float) -- floating point input return UNRESOLVED_float is begin return y(y'high) & x (x'high-1 downto x'low); end function Copysign; -- Returns y * 2n for integral values of N without computing 2n function Scalb ( y : UNRESOLVED_float; -- floating point input N : INTEGER; -- exponent to add constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(y'low, y'low); -- length of FP output fraction constant exponent_width : NATURAL := y'high; -- length of FP output exponent variable arg, result : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp variable exp : SIGNED (exponent_width downto 0); variable ufract : UNSIGNED (fraction_width downto 0); constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fptype : valid_fpstate; begin -- This can be done by simply adding N to the exponent. arg := to_01 (y, 'X'); fptype := classfp(arg, check_error); classcase : case fptype is when isx => result := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 result := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when others => break_number ( arg => arg, fptyp => fptype, denormalize => denormalize, fract => ufract, expon => expon); exp := resize (expon, exp'length) + N; result := normalize ( fract => ufract, expon => exp, sign => to_x01 (arg (arg'high)), fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => 0); end case classcase; return result; end function Scalb; -- Returns y * 2n for integral values of N without computing 2n function Scalb ( y : UNRESOLVED_float; -- floating point input N : UNRESOLVED_SIGNED; -- exponent to add constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable n_int : INTEGER; begin n_int := to_integer(N); return Scalb (y => y, N => n_int, round_style => round_style, check_error => check_error, denormalize => denormalize); end function Scalb; -- returns the unbiased exponent of x function Logb ( x : UNRESOLVED_float) -- floating point input return INTEGER is constant fraction_width : NATURAL := -mine (x'low, x'low); -- length of FP output fraction constant exponent_width : NATURAL := x'high; -- length of FP output exponent variable result : INTEGER; -- result variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument variable expon : SIGNED (exponent_width - 1 downto 0); variable fract : UNSIGNED (fraction_width downto 0); constant expon_base : INTEGER := 2*(exponent_width-1) -1; -- exponent -- offset +1 variable fptype : valid_fpstate; begin -- Just return the exponent. arg := to_01 (x, 'X'); fptype := classfp(arg); classcase : case fptype is when isx \| nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 result := 0; when pos_denormal \| neg_denormal => fract (fraction_width) := '0'; fract (fraction_width-1 downto 0) := UNSIGNED (to_slv(arg(-1 downto -fraction_width))); result := find_leftmost (fract, '1') -- Find the first "1" - fraction_width; -- subtract the length we want result := -expon_base + 1 + result; when others => expon := SIGNED(arg (exponent_width - 1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); expon := expon + 1; result := to_integer (expon); end case classcase; return result; end function Logb; -- returns the unbiased exponent of x function Logb ( x : UNRESOLVED_float) -- floating point input return UNRESOLVED_SIGNED is constant exponent_width : NATURAL := x'high; -- length of FP output exponent variable result : SIGNED (exponent_width - 1 downto 0); -- result begin -- Just return the exponent. result := to_signed (Logb (x), exponent_width); return result; end function Logb; -- returns the next representable neighbor of x in the direction toward y function Nextafter ( x, y : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(x'low, x'low); -- length of FP output fraction constant exponent_width : NATURAL := x'high; -- length of FP output exponent function "=" ( l, r : UNRESOLVED_float) -- inputs return BOOLEAN is begin -- function "=" return eq (l => l, r => r, check_error => false); end function "="; function ">" ( l, r : UNRESOLVED_float) -- inputs return BOOLEAN is begin -- function ">" return gt (l => l, r => r, check_error => false); end function ">"; variable fract : UNSIGNED (fraction_width-1 downto 0); variable expon : UNSIGNED (exponent_width-1 downto 0); variable sign : STD_ULOGIC; variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable validfpx, validfpy : valid_fpstate; -- Valid FP state begin -- fp_Nextafter -- If Y > X, add one to the fraction, otherwise subtract. validfpx := classfp (x, check_error); validfpy := classfp (y, check_error); if validfpx = isx or validfpy = isx then result := (others => 'X'); return result; elsif (validfpx = nan or validfpy = nan) then return nanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (validfpx = quiet_nan or validfpy = quiet_nan) then return qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif x = y then -- Return X return x; else fract := UNSIGNED (to_slv (x (-1 downto -fraction_width))); -- Fraction expon := UNSIGNED (x (exponent_width - 1 downto 0)); -- exponent sign := x(exponent_width); -- sign bit if (y > x) then -- Increase the number given if validfpx = neg_inf then -- return most negative number expon := (others => '1'); expon (0) := '0'; fract := (others => '1'); elsif validfpx = pos_zero or validfpx = neg_zero then -- return smallest denormal number sign := '0'; expon := (others => '0'); fract := (others => '0'); fract(0) := '1'; elsif validfpx = pos_normal then if and (fract) = '1' then -- fraction is all "1". if and (expon (exponent_width-1 downto 1)) = '1' and expon (0) = '0' then -- Exponent is one away from infinity. assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "FP_NEXTAFTER: NextAfter overflow" severity warning; return pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else expon := expon + 1; fract := (others => '0'); end if; else fract := fract + 1; end if; elsif validfpx = pos_denormal then if and (fract) = '1' then -- fraction is all "1". -- return smallest possible normal number expon := (others => '0'); expon(0) := '1'; fract := (others => '0'); else fract := fract + 1; end if; elsif validfpx = neg_normal then if or (fract) = '0' then -- fraction is all "0". if or (expon (exponent_width-1 downto 1)) = '0' and expon (0) = '1' then -- Smallest exponent -- return the largest negative denormal number expon := (others => '0'); fract := (others => '1'); else expon := expon - 1; fract := (others => '1'); end if; else fract := fract - 1; end if; elsif validfpx = neg_denormal then if or (fract(fract'high downto 1)) = '0' and fract (0) = '1' then -- Smallest possible fraction return zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else fract := fract - 1; end if; end if; else -- Decrease the number if validfpx = pos_inf then -- return most positive number expon := (others => '1'); expon (0) := '0'; fract := (others => '1'); elsif validfpx = pos_zero or classfp (x) = neg_zero then -- return smallest negative denormal number sign := '1'; expon := (others => '0'); fract := (others => '0'); fract(0) := '1'; elsif validfpx = neg_normal then if and (fract) = '1' then -- fraction is all "1". if and (expon (exponent_width-1 downto 1)) = '1' and expon (0) = '0' then -- Exponent is one away from infinity. assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "FP_NEXTAFTER: NextAfter overflow" severity warning; return neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else expon := expon + 1; -- Fraction overflow fract := (others => '0'); end if; else fract := fract + 1; end if; elsif validfpx = neg_denormal then if and (fract) = '1' then -- fraction is all "1". -- return smallest possible normal number expon := (others => '0'); expon(0) := '1'; fract := (others => '0'); else fract := fract + 1; end if; elsif validfpx = pos_normal then if or (fract) = '0' then -- fraction is all "0". if or (expon (exponent_width-1 downto 1)) = '0' and expon (0) = '1' then -- Smallest exponent -- return the largest positive denormal number expon := (others => '0'); fract := (others => '1'); else expon := expon - 1; fract := (others => '1'); end if; else fract := fract - 1; end if; elsif validfpx = pos_denormal then if or (fract(fract'high downto 1)) = '0' and fract (0) = '1' then -- Smallest possible fraction return zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else fract := fract - 1; end if; end if; end if; result (-1 downto -fraction_width) := UNRESOLVED_float(fract); result (exponent_width -1 downto 0) := UNRESOLVED_float(expon); result (exponent_width) := sign; return result; end if; end function Nextafter; -- Returns True if X is unordered with Y. function Unordered ( x, y : UNRESOLVED_float) -- floating point input return BOOLEAN is variable lfptype, rfptype : valid_fpstate; begin lfptype := classfp (x); rfptype := classfp (y); if (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan or lfptype = isx or rfptype = isx) then return true; else return false; end if; end function Unordered; function Finite ( x : UNRESOLVED_float) return BOOLEAN is variable fp_state : valid_fpstate; -- fp state begin fp_state := Classfp (x); if (fp_state = pos_inf) or (fp_state = neg_inf) then return true; else return false; end if; end function Finite; function Isnan ( x : UNRESOLVED_float) return BOOLEAN is variable fp_state : valid_fpstate; -- fp state begin fp_state := Classfp (x); if (fp_state = nan) or (fp_state = quiet_nan) then return true; else return false; end if; end function Isnan; -- Function to return constants. function zerofp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is constant result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin return result; end function zerofp; function nanfp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1" result (-1) := '1'; -- MSB of Fraction "1" -- Note: From W. Khan "IEEE Standard 754 for Binary Floating Point" -- The difference between a signaling NAN and a quiet NAN is that -- the MSB of the Fraction is a "1" in a Signaling NAN, and is a -- "0" in a quiet NAN. return result; end function nanfp; function qnanfp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1" result (-fraction_width) := '1'; -- LSB of Fraction "1" -- (Could have been any bit) return result; end function qnanfp; function pos_inffp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1" return result; end function pos_inffp; function neg_inffp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width downto 0) := (others => '1'); -- top bits all "1" return result; end function neg_inffp; function neg_zerofp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width) := '1'; return result; end function neg_zerofp; -- size_res versions function zerofp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return zerofp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function zerofp; function nanfp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return nanfp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function nanfp; function qnanfp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return qnanfp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function qnanfp; function pos_inffp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return pos_inffp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function pos_inffp; function neg_inffp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return neg_inffp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function neg_inffp; function neg_zerofp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return neg_zerofp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function neg_zerofp; -- Textio functions -- purpose: writes float into a line (NOTE changed basetype) type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error); type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER; type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC; type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus; constant NBSP : CHARACTER := CHARACTER'val(160); -- space character constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-"; constant char_to_MVL9 : MVL9_indexed_by_char := ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U'); constant char_to_MVL9plus : MVL9plus_indexed_by_char := ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error); -- purpose: Skips white space procedure skip_whitespace ( L : inout LINE) is variable readOk : BOOLEAN; variable c : CHARACTER; begin while L /= null and L.all'length /= 0 loop c := l (l'left); if (c = ' ' or c = NBSP or c = HT) then read (l, c, readOk); else exit; end if; end loop; end procedure skip_whitespace; -- purpose: Checks the punctuation in a line procedure check_punctuation ( arg : in STRING; colon : out BOOLEAN; -- There was a colon in the line dot : out BOOLEAN; -- There was a dot in the line good : out BOOLEAN; -- True if enough characters found chars : in INTEGER) is -- Examples. Legal inputs are "0000000", "0000.000", "0:000:000" alias xarg : STRING (1 to arg'length) is arg; -- make it downto range variable icolon, idot : BOOLEAN; -- internal variable j : INTEGER := 0; -- charters read begin good := false; icolon := false; idot := false; for i in 1 to arg'length loop if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j = chars then exit; elsif xarg(i) = ':' then icolon := true; elsif xarg(i) = '.' then idot := true; elsif xarg (i) /= '_' then j := j + 1; end if; end loop; if j = chars then good := true; -- There are enough charactes to read end if; colon := icolon; if idot and icolon then dot := false; else dot := idot; end if; end procedure check_punctuation; -- purpose: Searches a line for a ":" and replaces it with a ".". procedure fix_colon ( arg : inout STRING; chars : in integer) is alias xarg : STRING (1 to arg'length) is arg; -- make it downto range variable j : INTEGER := 0; -- charters read begin for i in 1 to arg'length loop if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j > chars then exit; elsif xarg(i) = ':' then xarg (i) := '.'; elsif xarg (i) /= '_' then j := j + 1; end if; end loop; end procedure fix_colon; procedure WRITE ( L : inout LINE; -- input line VALUE : in UNRESOLVED_float; -- floating point input JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable s : STRING(1 to value'high - value'low +3); variable sindx : INTEGER; begin -- function write s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high))); s(2) := ':'; sindx := 3; for i in VALUE'high-1 downto 0 loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; s(sindx) := ':'; sindx := sindx + 1; for i in -1 downto VALUE'low loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; WRITE (L, s, JUSTIFIED, FIELD); end procedure WRITE; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float) is -- Possible data: 0:0000:0000000 -- 000000000000 variable c : CHARACTER; variable mv : UNRESOLVED_float (VALUE'range); variable readOk : BOOLEAN; variable lastu : BOOLEAN := false; -- last character was an "_" variable i : INTEGER; -- index variable begin -- READ VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); READ (l, c, readOk); if VALUE'length > 0 then i := value'high; readloop : loop if readOk = false then -- Bail out if there was a bad read report float_generic_pkg'instance_name & "READ(float): " & "Error end of file encountered." severity error; return; elsif c = ' ' or c = CR or c = HT then -- reading done. if (i /= value'low) then report float_generic_pkg'instance_name & "READ(float): " & "Warning: Value truncated." severity warning; return; end if; elsif c = '_' then if i = value'high then -- Begins with an "_" report float_generic_pkg'instance_name & "READ(float): " & "String begins with an ""_""" severity error; return; elsif lastu then -- "__" detected report float_generic_pkg'instance_name & "READ(float): " & "Two underscores detected in input string ""__""" severity error; return; else lastu := true; end if; elsif c = ':' or c = '.' then -- separator, ignore if not (i = -1 or i = value'high-1) then report float_generic_pkg'instance_name & "READ(float): " & "Warning: Separator point does not match number format: '" & c & "' encountered at location " & INTEGER'image(i) & "." severity warning; end if; lastu := false; elsif (char_to_MVL9plus(c) = error) then report float_generic_pkg'instance_name & "READ(float): " & "Error: Character '" & c & "' read, expected STD_ULOGIC literal." severity error; return; else mv (i) := char_to_MVL9(c); i := i - 1; if i < value'low then VALUE := mv; return; end if; lastu := false; end if; READ (l, c, readOk); end loop readloop; end if; end procedure READ; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is -- Possible data: 0:0000:0000000 -- 000000000000 variable c : CHARACTER; variable mv : UNRESOLVED_float (VALUE'range); variable lastu : BOOLEAN := false; -- last character was an "_" variable i : INTEGER; -- index variable variable readOk : BOOLEAN; begin -- READ VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); READ (l, c, readOk); if VALUE'length > 0 then i := value'high; good := false; readloop : loop if readOk = false then -- Bail out if there was a bad read return; elsif c = ' ' or c = CR or c = HT then -- reading done return; elsif c = '_' then if i = 0 then -- Begins with an "_" return; elsif lastu then -- "__" detected return; else lastu := true; end if; elsif c = ':' or c = '.' then -- separator, ignore -- good := (i = -1 or i = value'high-1); lastu := false; elsif (char_to_MVL9plus(c) = error) then return; else mv (i) := char_to_MVL9(c); i := i - 1; if i < value'low then good := true; VALUE := mv; return; end if; lastu := false; end if; READ (l, c, readOk); end loop readloop; else good := true; -- read into a null array end if; end procedure READ; procedure OWRITE ( L : inout LINE; -- access type (pointer) VALUE : in UNRESOLVED_float; -- value to write JUSTIFIED : in SIDE := right; -- which side to justify text FIELD : in WIDTH := 0) is -- width of field begin WRITE (L => L, VALUE => to_ostring(VALUE), JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure OWRITE; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is constant ne : INTEGER := ((value'length+2)/3) 3; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/3); if not ok then report float_generic_pkg'instance_name & "OREAD: " & "short string encounted: " & L.all & " needs to have " & integer'image (ne/3) & " valid octal characters." severity error; return; elsif dot then OREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "OREAD: " & "error encounted reading STRING " & L.all severity error; return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then OREAD (L, nybble, ok); -- read the sign bit if not ok then report float_generic_pkg'instance_name & "OREAD: " & "End of string encountered" severity error; return; elsif nybble (2 downto 1) /= "00" then report float_generic_pkg'instance_name & "OREAD: " & "Illegal sign bit STRING encounted " severity error; return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/3); -- replaces the colon with a ".". OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "OREAD: " & "error encounted reading STRING " & L.all severity error; return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else OREAD (L, slv, ok); if not ok then report float_generic_pkg'instance_name & "OREAD: " & "Error encounted during read" severity error; return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then report float_generic_pkg'instance_name & "OREAD: " & "Vector truncated." severity error; return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; end if; end procedure OREAD; procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" GOOD := false; Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/3); if not ok then return; elsif dot then OREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then OREAD (L, nybble, ok); -- read the sign bit if not ok then return; elsif nybble (2 downto 1) /= "00" then return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/3); -- replaces the colon with a ".". OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else OREAD (L, slv, ok); if not ok then return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; GOOD := true; end if; end procedure OREAD; procedure HWRITE ( L : inout LINE; -- access type (pointer) VALUE : in UNRESOLVED_float; -- value to write JUSTIFIED : in SIDE := right; -- which side to justify text FIELD : in WIDTH := 0) is -- width of field begin WRITE (L => L, VALUE => to_hstring(VALUE), JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure HWRITE; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/4); if not ok then report float_generic_pkg'instance_name & "HREAD: " & "short string encounted: " & L.all & " needs to have " & integer'image (ne/4) & " valid hex characters." severity error; return; elsif dot then HREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "HREAD: " & "error encounted reading STRING " & L.all severity error; return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then HREAD (L, nybble, ok); -- read the sign bit if not ok then report float_generic_pkg'instance_name & "HREAD: " & "End of string encountered" severity error; return; elsif nybble (3 downto 1) /= "000" then report float_generic_pkg'instance_name & "HREAD: " & "Illegal sign bit STRING encounted " severity error; return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/4); -- replaces the colon with a ".". HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "HREAD: " & "error encounted reading STRING " & L.all severity error; return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else HREAD (L, slv, ok); if not ok then report float_generic_pkg'instance_name & "HREAD: " & "Error encounted during read" severity error; return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then report float_generic_pkg'instance_name & "HREAD: " & "Vector truncated." severity error; return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; end if; end procedure HREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" GOOD := false; Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/4); if not ok then return; elsif dot then HREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then HREAD (L, nybble, ok); -- read the sign bit if not ok then return; elsif nybble (3 downto 1) /= "000" then return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/4); -- replaces the colon with a ".". HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else HREAD (L, slv, ok); if not ok then return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; GOOD := true; end if; end procedure HREAD; function to_string (value : UNRESOLVED_float) return STRING is variable s : STRING(1 to value'high - value'low +3); variable sindx : INTEGER; begin -- function write s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high))); s(2) := ':'; sindx := 3; for i in VALUE'high-1 downto 0 loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; s(sindx) := ':'; sindx := sindx + 1; for i in -1 downto VALUE'low loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; return s; end function to_string; function to_hstring (value : UNRESOLVED_float) return STRING is variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0); begin floop : for i in slv'range loop slv(i) := to_X01Z (value(i + value'low)); end loop floop; return to_hstring (slv); end function to_hstring; function to_ostring (value : UNRESOLVED_float) return STRING is variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0); begin floop : for i in slv'range loop slv(i) := to_X01Z (value(i + value'low)); end loop floop; return to_ostring (slv); end function to_ostring; function from_string ( bstring : STRING; -- binary string constant exponent_width : NATURAL := float_exponent_width; constant fraction_width : NATURAL := float_fraction_width) return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable L : LINE; variable good : BOOLEAN; begin L := new STRING'(bstring); READ (L, result, good); deallocate (L); assert (good) report FLOAT_GENERIC_PKG'instance_name & "from_string: Bad string " & bstring severity error; return result; end function from_string; function from_ostring ( ostring : STRING; -- Octal string constant exponent_width : NATURAL := float_exponent_width; constant fraction_width : NATURAL := float_fraction_width) return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable L : LINE; variable good : BOOLEAN; begin L := new STRING'(ostring); OREAD (L, result, good); deallocate (L); assert (good) report FLOAT_GENERIC_PKG'instance_name & "from_ostring: Bad string " & ostring severity error; return result; end function from_ostring; function from_hstring ( hstring : STRING; -- hex string constant exponent_width : NATURAL := float_exponent_width; constant fraction_width : NATURAL := float_fraction_width) return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable L : LINE; variable good : BOOLEAN; begin L := new STRING'(hstring); HREAD (L, result, good); deallocate (L); assert (good) report FLOAT_GENERIC_PKG'instance_name & "from_hstring: Bad string " & hstring severity error; return result; end function from_hstring; function from_string ( bstring : STRING; -- binary string size_res : UNRESOLVED_float) -- used for sizing only return UNRESOLVED_float is begin return from_string (bstring => bstring, exponent_width => size_res'high, fraction_width => -size_res'low); end function from_string; function from_ostring ( ostring : STRING; -- Octal string size_res : UNRESOLVED_float) -- used for sizing only return UNRESOLVED_float is begin return from_ostring (ostring => ostring, exponent_width => size_res'high, fraction_width => -size_res'low); end function from_ostring; function from_hstring ( hstring : STRING; -- hex string size_res : UNRESOLVED_float) -- used for sizing only return UNRESOLVED_float is begin return from_hstring (hstring => hstring, exponent_width => size_res'high, fraction_width => -size_res'low); end function from_hstring; end package body float_generic_pkg;
-- -------------------------------------------------------------------- -- -- Copyright © 2008 by IEEE. All rights reserved. -- -- This source file is an essential part of IEEE Std 1076-2008, -- IEEE Standard VHDL Language Reference Manual. This source file may not be -- copied, sold, or included with software that is sold without written -- permission from the IEEE Standards Department. This source file may be -- copied for individual use between licensed users. This source file is -- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR -- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE -- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify -- and hold IEEE harmless from any damages or liability arising out of the -- use thereof. -- -- Title : Floating-point package (Generic package body) -- : -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: Accellera VHDL-TC and IEEE P1076 Working Group -- : -- Purpose : This packages defines basic binary floating point -- : arithmetic functions -- : -- Note : This package may be modified to include additional data -- : required by tools, but it must in no way change the -- : external interfaces or simulation behavior of the -- : description. It is permissible to add comments and/or -- : attributes to the package declarations, but not to change -- : or delete any original lines of the package declaration. -- : The package body may be changed only in accordance with -- : the terms of Clause 16 of this standard. -- : -- -------------------------------------------------------------------- -- $Revision: 1220 $ -- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ -- -------------------------------------------------------------------- package body float_generic_pkg is -- Author David Bishop ([email protected]) ----------------------------------------------------------------------------- -- type declarations ----------------------------------------------------------------------------- -- This deferred constant will tell you if the package body is synthesizable -- or implemented as real numbers, set to "true" if synthesizable. constant fphdlsynth_or_real : BOOLEAN := true; -- deferred constant -- types of boundary conditions type boundary_type is (normal, infinity, zero, denormal); -- null range array constant constant NAFP : UNRESOLVED_float (0 downto 1) := (others => '0'); constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0'); -- Special version of "minimum" to do some boundary checking function mine (L, R : INTEGER) return INTEGER is begin -- function minimum if (L = INTEGER'low or R = INTEGER'low) then report float_generic_pkg'instance_name & " Unbounded number passed, was a literal used?" severity error; return 0; end if; return minimum (L, R); end function mine; -- Generates the base number for the exponent normalization offset. function gen_expon_base ( constant exponent_width : NATURAL) return SIGNED is variable result : SIGNED (exponent_width-1 downto 0); begin result := (others => '1'); result (exponent_width-1) := '0'; return result; end function gen_expon_base; -- Integer version of the "log2" command (contributed by Peter Ashenden) function log2 (A : NATURAL) return NATURAL is variable quotient : NATURAL; variable result : NATURAL := 0; begin quotient := A / 2; while quotient > 0 loop quotient := quotient / 2; result := result + 1; end loop; return result; end function log2; -- Function similar to the ILOGB function in MATH_REAL function log2 (A : REAL) return INTEGER is variable Y : REAL; variable N : INTEGER := 0; begin if (A = 1.0 or A = 0.0) then return 0; end if; Y := A; if(A > 1.0) then while Y >= 2.0 loop Y := Y / 2.0; N := N + 1; end loop; return N; end if; -- O < Y < 1 while Y < 1.0 loop Y := Y * 2.0; N := N - 1; end loop; return N; end function log2; -- purpose: Test the boundary conditions of a Real number procedure test_boundary ( arg : in REAL; -- Input, converted to real constant fraction_width : in NATURAL; -- length of FP output fraction constant exponent_width : in NATURAL; -- length of FP exponent constant denormalize : in BOOLEAN := true; -- Use IEEE extended FP variable btype : out boundary_type; variable log2i : out INTEGER ) is constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset constant exp_min : SIGNED (12 downto 0) := -(resize(expon_base, 13)) + 1; -- Minimum normal exponent constant exp_ext_min : SIGNED (12 downto 0) := exp_min - fraction_width; -- Minimum for denormal exponent variable log2arg : INTEGER; -- log2 of argument begin -- function test_boundary -- Check to see if the exponent is big enough -- Note that the argument is always an absolute value at this point. log2arg := log2(arg); if arg = 0.0 then btype := zero; elsif exponent_width > 11 then -- Exponent for Real is 11 (64 bit) btype := normal; else if log2arg < to_integer(exp_min) then if denormalize then if log2arg < to_integer(exp_ext_min) then btype := zero; else btype := denormal; end if; else if log2arg < to_integer(exp_min)-1 then btype := zero; else btype := normal; -- Can still represent this number end if; end if; elsif exponent_width < 11 then if log2arg > to_integer(expon_base)+1 then btype := infinity; else btype := normal; end if; else btype := normal; end if; end if; log2i := log2arg; end procedure test_boundary; -- purpose: Rounds depending on the state of the "round_style" -- Logic taken from -- "What Every Computer Scientist Should Know About Floating Point Arithmetic" -- by David Goldberg (1991) function check_round ( fract_in : STD_ULOGIC; -- input fraction sign : STD_ULOGIC; -- sign bit remainder : UNSIGNED; -- remainder to round from sticky : STD_ULOGIC := '0'; -- Sticky bit constant round_style : round_type) -- rounding type return BOOLEAN is variable result : BOOLEAN; variable or_reduced : STD_ULOGIC; begin -- function check_round result := false; if (remainder'length > 0) then -- if remainder in a null array or_reduced := or (remainder & sticky); rounding_case : case round_style is when round_nearest => -- Round Nearest, default mode if remainder(remainder'high) = '1' then -- round if (remainder'length > 1) then if ((or (remainder(remainder'high-1 downto remainder'low)) = '1' or sticky = '1') or fract_in = '1') then -- Make the bottom bit zero if possible if we are at 1/2 result := true; end if; else result := (fract_in = '1' or sticky = '1'); end if; end if; when round_inf => -- round up if positive, else truncate. if or_reduced = '1' and sign = '0' then result := true; end if; when round_neginf => -- round down if negative, else truncate. if or_reduced = '1' and sign = '1' then result := true; end if; when round_zero => -- round toward 0 Truncate null; end case rounding_case; end if; return result; end function check_round; -- purpose: Rounds depending on the state of the "round_style" -- unsigned version procedure fp_round ( fract_in : in UNSIGNED; -- input fraction expon_in : in SIGNED; -- input exponent fract_out : out UNSIGNED; -- output fraction expon_out : out SIGNED) is -- output exponent begin -- procedure fp_round if and (fract_in) = '1' then -- Fraction is all "1" expon_out := expon_in + 1; fract_out := to_unsigned(0, fract_out'high+1); else expon_out := expon_in; fract_out := fract_in + 1; end if; end procedure fp_round; -- This version of break_number doesn't call "classfp" procedure break_number ( -- internal version arg : in UNRESOLVED_float; fptyp : in valid_fpstate; denormalize : in BOOLEAN := true; fract : out UNSIGNED; expon : out SIGNED) is constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction constant exponent_width : NATURAL := arg'high; -- length of FP output exponent constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable exp : SIGNED (expon'range); begin fract (fraction_width-1 downto 0) := UNSIGNED (to_slv(arg(-1 downto -fraction_width))); breakcase : case fptyp is when pos_zero \| neg_zero => fract (fraction_width) := '0'; exp := -expon_base; when pos_denormal \| neg_denormal => if denormalize then exp := -expon_base; fract (fraction_width) := '0'; else exp := -expon_base - 1; fract (fraction_width) := '1'; end if; when pos_normal \| neg_normal \| pos_inf \| neg_inf => fract (fraction_width) := '1'; exp := SIGNED(arg(exponent_width-1 downto 0)); exp (exponent_width-1) := not exp(exponent_width-1); when others => assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "BREAK_NUMBER: " & "Meta state detected in fp_break_number process" severity warning; -- complete the case, if a NAN goes in, a NAN comes out. exp := (others => '1'); fract (fraction_width) := '1'; end case breakcase; expon := exp; end procedure break_number; -- purpose: floating point to UNSIGNED -- Used by to_integer, to_unsigned, and to_signed functions procedure float_to_unsigned ( arg : in UNRESOLVED_float; -- floating point input variable sign : out STD_ULOGIC; -- sign of output variable frac : out UNSIGNED; -- unsigned biased output constant denormalize : in BOOLEAN; -- turn on denormalization constant bias : in NATURAL; -- bias for fixed point constant round_style : in round_type) is -- rounding method constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent variable fract : UNSIGNED (frac'range); -- internal version of frac variable isign : STD_ULOGIC; -- internal version of sign variable exp : INTEGER; -- Exponent variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp -- Base to divide fraction by variable frac_shift : UNSIGNED (frac'high+3 downto 0); -- Fraction shifted variable shift : INTEGER; variable remainder : UNSIGNED (2 downto 0); variable round : STD_ULOGIC; -- round BIT begin isign := to_x01(arg(arg'high)); -- exponent /= '0', normal floating point expon := to_01(SIGNED(arg (exponent_width-1 downto 0)), 'X'); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (expon); -- Figure out the fraction fract := (others => '0'); -- fill with zero fract (fract'high) := '1'; -- Add the "1.0". shift := (fract'high-1) - exp; if fraction_width > fract'high then -- Can only use size-2 bits fract (fract'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto -fract'high))); else -- can use all bits fract (fract'high-1 downto fract'high-fraction_width) := UNSIGNED (to_slv (arg(-1 downto -fraction_width))); end if; frac_shift := fract & "000"; if shift < 0 then -- Overflow fract := (others => '1'); else frac_shift := shift_right (frac_shift, shift); fract := frac_shift (frac_shift'high downto 3); remainder := frac_shift (2 downto 0); -- round (round_zero will bypass this and truncate) case round_style is when round_nearest => round := remainder(2) and (fract (0) or (or (remainder (1 downto 0)))); when round_inf => round := remainder(2) and not isign; when round_neginf => round := remainder(2) and isign; when others => round := '0'; end case; if round = '1' then fract := fract + 1; end if; end if; frac := fract; sign := isign; end procedure float_to_unsigned; -- purpose: returns a part of a vector, this function is here because -- or (fractr (to_integer(shiftx) downto 0)); -- can't be synthesized in some synthesis tools. function smallfract ( arg : UNSIGNED; shift : NATURAL) return STD_ULOGIC is variable orx : STD_ULOGIC; begin orx := arg(shift); for i in arg'range loop if i < shift then orx := arg(i) or orx; end if; end loop; return orx; end function smallfract; --------------------------------------------------------------------------- -- Visible functions --------------------------------------------------------------------------- -- purpose: converts the negative index to a positive one -- negative indices are illegal in 1164 and 1076.3 function to_sulv ( arg : UNRESOLVED_float) -- fp vector return STD_ULOGIC_VECTOR is subtype result_subtype is STD_ULOGIC_VECTOR (arg'length-1 downto 0); variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0); begin -- function to_std_ulogic_vector if arg'length < 1 then return NSLV; end if; result := result_subtype (arg); return result; end function to_sulv; -- Converts an fp into an SULV function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR is begin return to_sulv (arg); end function to_slv; -- purpose: normalizes a floating point number -- This version assumes an "unsigned" input with function normalize ( fract : UNRESOLVED_UNSIGNED; -- fraction, unnormalized expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1 sign : STD_ULOGIC; -- sign BIT sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is variable sfract : UNSIGNED (fract'high downto 0); -- shifted fraction variable rfract : UNSIGNED (fraction_width-1 downto 0); -- fraction variable exp : SIGNED (exponent_width+1 downto 0); -- exponent variable rexp : SIGNED (exponent_width+1 downto 0); -- result exponent variable rexpon : UNSIGNED (exponent_width-1 downto 0); -- exponent variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result variable shiftr : INTEGER; -- shift amount variable stickyx : STD_ULOGIC; -- version of sticky constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable round, zerores, infres : BOOLEAN; begin -- function normalize zerores := false; infres := false; round := false; shiftr := find_leftmost (to_01(fract), '1') -- Find the first "1" - fraction_width - nguard; -- subtract the length we want exp := resize (expon, exp'length) + shiftr; if (or (fract) = '0') then -- Zero zerores := true; elsif ((exp <= -resize(expon_base, exp'length)-1) and denormalize) or ((exp < -resize(expon_base, exp'length)-1) and not denormalize) then if (exp >= -resize(expon_base, exp'length)-fraction_width-1) and denormalize then exp := -resize(expon_base, exp'length)-1; shiftr := -to_integer (expon + expon_base); -- new shift else -- return zero zerores := true; end if; elsif (exp > expon_base-1) then -- infinity infres := true; end if; if zerores then result := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); elsif infres then result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else sfract := fract srl shiftr; -- shift if shiftr > 0 then -- stickyx := sticky or (or (fract (shiftr-1 downto 0))); stickyx := sticky or smallfract (fract, shiftr-1); else stickyx := sticky; end if; if nguard > 0 then round := check_round ( fract_in => sfract (nguard), sign => sign, remainder => sfract(nguard-1 downto 0), sticky => stickyx, round_style => round_style); end if; if round then fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard), expon_in => exp(rexp'range), fract_out => rfract, expon_out => rexp); else rfract := sfract (fraction_width-1+nguard downto nguard); rexp := exp(rexp'range); end if; -- result rexpon := UNSIGNED (rexp(exponent_width-1 downto 0)); rexpon (exponent_width-1) := not rexpon(exponent_width-1); result (rexpon'range) := UNRESOLVED_float(rexpon); result (-1 downto -fraction_width) := UNRESOLVED_float(rfract); end if; result (exponent_width) := sign; -- sign BIT return result; end function normalize; -- purpose: normalizes a floating point number -- This version assumes a "ufixed" input function normalize ( fract : UNRESOLVED_ufixed; -- unsigned fixed point expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1 sign : STD_ULOGIC; -- sign bit sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arguns : UNSIGNED (fract'high + fraction_width + nguard downto 0) := (others => '0'); begin -- function normalize arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) := UNSIGNED (to_slv (fract)); result := normalize (fract => arguns, expon => expon, sign => sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => nguard); return result; end function normalize; -- purpose: normalizes a floating point number -- This version assumes a "ufixed" input with a "size_res" input function normalize ( fract : UNRESOLVED_ufixed; -- unsigned fixed point expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1 sign : STD_ULOGIC; -- sign bit sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) size_res : UNRESOLVED_float; -- used for sizing only constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is constant fraction_width : NATURAL := -size_res'low; constant exponent_width : NATURAL := size_res'high; variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arguns : UNSIGNED (fract'high + fraction_width + nguard downto 0) := (others => '0'); begin -- function normalize arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) := UNSIGNED (to_slv (fract)); result := normalize (fract => arguns, expon => expon, sign => sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => nguard); return result; end function normalize; -- Regular "normalize" function with a "size_res" input. function normalize ( fract : UNRESOLVED_UNSIGNED; -- unsigned expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized sign : STD_ULOGIC; -- sign bit sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) size_res : UNRESOLVED_float; -- used for sizing only constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is begin return normalize (fract => fract, expon => expon, sign => sign, sticky => sticky, fraction_width => -size_res'low, exponent_width => size_res'high, round_style => round_style, denormalize => denormalize, nguard => nguard); end function normalize; -- Returns the class which X falls into function Classfp ( x : UNRESOLVED_float; -- floating point input check_error : BOOLEAN := float_check_error) -- check for errors return valid_fpstate is constant fraction_width : INTEGER := -mine(x'low, x'low); -- length of FP output fraction constant exponent_width : INTEGER := x'high; -- length of FP output exponent variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- classfp if (arg'length < 1 or fraction_width < 3 or exponent_width < 3 or x'left < x'right) then report FLOAT_GENERIC_PKG'instance_name & "CLASSFP: " & "Floating point number detected with a bad range" severity error; return isx; end if; -- Check for "X". arg := to_01 (x, 'X'); if (arg(0) = 'X') then return isx; -- If there is an X in the number -- Special cases, check for illegal number elsif check_error and (and (STD_ULOGIC_VECTOR (arg (exponent_width-1 downto 0))) = '1') then -- Exponent is all "1". if or (to_slv (arg (-1 downto -fraction_width))) /= '0' then -- Fraction must be all "0" or this is not a number. if (arg(-1) = '1') then -- From "W. Khan - IEEE standard return nan; -- 754 binary FP Signaling nan (Not a number) else return quiet_nan; end if; -- Check for infinity elsif arg(exponent_width) = '0' then return pos_inf; -- Positive infinity else return neg_inf; -- Negative infinity end if; -- check for "0" elsif or (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0))) = '0' then -- Exponent is all "0" if or (to_slv (arg (-1 downto -fraction_width))) = '0' then -- Fraction is all "0" if arg(exponent_width) = '0' then return pos_zero; -- Zero else return neg_zero; end if; else if arg(exponent_width) = '0' then return pos_denormal; -- Denormal number (ieee extended fp) else return neg_denormal; end if; end if; else if arg(exponent_width) = '0' then return pos_normal; -- Normal FP number else return neg_normal; end if; end if; end function Classfp; procedure break_number ( arg : in UNRESOLVED_float; denormalize : in BOOLEAN := float_denormalize; check_error : in BOOLEAN := float_check_error; fract : out UNRESOLVED_UNSIGNED; expon : out UNRESOLVED_SIGNED; sign : out STD_ULOGIC) is constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction variable fptyp : valid_fpstate; begin fptyp := Classfp (arg, check_error); sign := to_x01(arg(arg'high)); break_number ( arg => arg, fptyp => fptyp, denormalize => denormalize, fract => fract, expon => expon); end procedure break_number; procedure break_number ( arg : in UNRESOLVED_float; denormalize : in BOOLEAN := float_denormalize; check_error : in BOOLEAN := float_check_error; fract : out UNRESOLVED_ufixed; -- 1 downto -fraction_width expon : out UNRESOLVED_SIGNED; -- exponent_width-1 downto 0 sign : out STD_ULOGIC) is constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction variable fptyp : valid_fpstate; variable ufract : UNSIGNED (fraction_width downto 0); -- unsigned fraction begin fptyp := Classfp (arg, check_error); sign := to_x01(arg(arg'high)); break_number ( arg => arg, fptyp => fptyp, denormalize => denormalize, fract => ufract, expon => expon); fract (0 downto -fraction_width) := ufixed (ufract); end procedure break_number; -- Arithmetic functions function "abs" ( arg : UNRESOLVED_float) -- floating point input return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); -- result begin if (arg'length > 0) then result := to_01 (arg, 'X'); result (arg'high) := '0'; -- set the sign bit to positive return result; else return NAFP; end if; end function "abs"; -- IEEE 754 "negative" function function "-" ( arg : UNRESOLVED_float) -- floating point input return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); -- result begin if (arg'length > 0) then result := to_01 (arg, 'X'); result (arg'high) := not result (arg'high); -- invert sign bit return result; else return NAFP; end if; end function "-"; -- Addition, adds two floating point numbers function add ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant addguard : NATURAL := guard; -- add one guard bit variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable fractl, fractr : UNSIGNED (fraction_width+1+addguard downto 0); -- fractions variable fractc, fracts : UNSIGNED (fractl'range); -- constant and shifted variables variable urfract, ulfract : UNSIGNED (fraction_width downto 0); variable ufract : UNSIGNED (fraction_width+1+addguard downto 0); variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width downto 0); -- result exponent variable shiftx : SIGNED (exponent_width downto 0); -- shift fractions variable sign : STD_ULOGIC; -- sign of the output variable leftright : BOOLEAN; -- left or right used variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); variable sticky : STD_ULOGIC; -- Holds precision for rounding begin -- addition if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan) -- Return quiet NAN, IEEE754-1985-7.1,1 or (lfptype = pos_inf and rfptype = neg_inf) or (lfptype = neg_inf and rfptype = pos_inf) then -- Return quiet NAN, IEEE754-1985-7.1,2 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = pos_inf or rfptype = pos_inf) then -- x + inf = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = neg_inf or rfptype = neg_inf) then -- x - inf = -inf fpresult := neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = neg_zero and rfptype = neg_zero) then -- -0 + -0 = -0 fpresult := neg_zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); fractl := (others => '0'); fractl (fraction_width+addguard downto addguard) := ulfract; break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); fractr := (others => '0'); fractr (fraction_width+addguard downto addguard) := urfract; shiftx := (exponl(exponent_width-1) & exponl) - exponr; if shiftx < -fractl'high then rexpon := exponr(exponent_width-1) & exponr; fractc := fractr; fracts := (others => '0'); -- add zero leftright := false; sticky := or (fractl); elsif shiftx < 0 then shiftx := - shiftx; fracts := shift_right (fractl, to_integer(shiftx)); fractc := fractr; rexpon := exponr(exponent_width-1) & exponr; leftright := false; -- sticky := or (fractl (to_integer(shiftx) downto 0)); sticky := smallfract (fractl, to_integer(shiftx)); elsif shiftx = 0 then rexpon := exponl(exponent_width-1) & exponl; sticky := '0'; if fractr > fractl then fractc := fractr; fracts := fractl; leftright := false; else fractc := fractl; fracts := fractr; leftright := true; end if; elsif shiftx > fractr'high then rexpon := exponl(exponent_width-1) & exponl; fracts := (others => '0'); -- add zero fractc := fractl; leftright := true; sticky := or (fractr); elsif shiftx > 0 then fracts := shift_right (fractr, to_integer(shiftx)); fractc := fractl; rexpon := exponl(exponent_width-1) & exponl; leftright := true; -- sticky := or (fractr (to_integer(shiftx) downto 0)); sticky := smallfract (fractr, to_integer(shiftx)); end if; -- add fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB if l(l'high) = r(r'high) then ufract := fractc + fracts; sign := l(l'high); else -- signs are different ufract := fractc - fracts; -- always positive result if leftright then -- Figure out which sign to use sign := l(l'high); else sign := r(r'high); end if; end if; if or (ufract) = '0' then sign := '0'; -- IEEE 854, 6.3, paragraph 2. end if; -- normalize fpresult := normalize (fract => ufract, expon => rexpon, sign => sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => addguard); end if; return fpresult; end function add; -- Subtraction, Calls "add". function subtract ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable negr : UNRESOLVED_float (r'range); -- negative version of r begin negr := -r; -- r := -r return add (l => l, r => negr, round_style => round_style, guard => guard, check_error => check_error, denormalize => denormalize); end function subtract; -- Floating point multiply function multiply ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant multguard : NATURAL := guard; -- guard bits variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions variable rfract : UNSIGNED ((2(fraction_width))+1 downto 0); -- result fraction variable sfract : UNSIGNED (fraction_width+1+multguard downto 0); -- result fraction variable shifty : INTEGER; -- denormal shift variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent variable fp_sign : STD_ULOGIC; -- sign of result variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); variable sticky : STD_ULOGIC; -- Holds precision for rounding begin -- multiply if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif ((lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan)) then -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (((lfptype = pos_inf or lfptype = neg_inf) and (rfptype = pos_zero or rfptype = neg_zero)) or ((rfptype = pos_inf or rfptype = neg_inf) and (lfptype = pos_zero or lfptype = neg_zero))) then -- 0 inf -- Return quiet NAN, IEEE754-1985-7.1,3 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = pos_inf or rfptype = pos_inf or lfptype = neg_inf or rfptype = neg_inf) then -- x * inf = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); -- figure out the sign fp_sign := l(l'high) xor r(r'high); -- figure out the sign fpresult (exponent_width) := fp_sign; else fp_sign := l(l'high) xor r(r'high); -- figure out the sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => fractl, expon => exponl); break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => fractr, expon => exponr); if (rfptype = pos_denormal or rfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractr, '1'); fractr := shift_left (fractr, shifty); elsif (lfptype = pos_denormal or lfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractl, '1'); fractl := shift_left (fractl, shifty); else shifty := 0; -- Note that a denormal number * a denormal number is always zero. end if; -- multiply -- add the exponents rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1; rfract := fractl * fractr; -- Multiply the fraction sfract := rfract (rfract'high downto rfract'high - (fraction_width+1+multguard)); sticky := or (rfract (rfract'high-(fraction_width+1+multguard) downto 0)); -- normalize fpresult := normalize (fract => sfract, expon => rexpon, sign => fp_sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => multguard); end if; return fpresult; end function multiply; function short_divide ( lx, rx : UNSIGNED) return UNSIGNED is -- This is a special divider for the floating point routines. -- For a true unsigned divider, "stages" needs to = lx'high constant stages : INTEGER := lx'high - rx'high; -- number of stages variable partial : UNSIGNED (lx'range); variable q : UNSIGNED (stages downto 0); variable partial_argl : SIGNED (rx'high + 2 downto 0); variable partial_arg : SIGNED (rx'high + 2 downto 0); begin partial := lx; for i in stages downto 0 loop partial_argl := resize ("0" & SIGNED (partial(lx'high downto i)), partial_argl'length); partial_arg := partial_argl - SIGNED ("0" & rx); if (partial_arg (partial_arg'high) = '1') then -- negative q(i) := '0'; else q(i) := '1'; partial (lx'high+i-stages downto lx'high+i-stages-rx'high) := UNSIGNED (partial_arg(rx'range)); end if; end loop; -- to make the output look like that of the unsigned IEEE divide. return resize (q, lx'length); end function short_divide; -- 1/X function. Needed for algorithm development. function reciprocal ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : NATURAL := arg'high; -- length of FP output exponent constant divguard : NATURAL := guard; -- guard bits function onedivy ( arg : UNSIGNED) return UNSIGNED is variable q : UNSIGNED((2arg'high)+1 downto 0); variable one : UNSIGNED (q'range); begin one := (others => '0'); one(one'high) := '1'; q := short_divide (one, arg); -- Unsigned divide return resize (q, arg'length+1); end function onedivy; variable fptype : valid_fpstate; variable expon : SIGNED (exponent_width-1 downto 0); -- exponents variable denorm_offset : NATURAL range 0 to 2; variable fract : UNSIGNED (fraction_width downto 0); variable fractg : UNSIGNED (fraction_width+divguard downto 0); variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- reciprocal fptype := classfp(arg, check_error); classcase : case fptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => -- 1/inf, return 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); when neg_zero \| pos_zero => -- 1/0 report FLOAT_GENERIC_PKG'instance_name & "RECIPROCAL: Floating Point divide by zero" severity error; fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); when others => if (fptype = pos_denormal or fptype = neg_denormal) and ((arg (-1) or arg(-2)) /= '1') then -- 1/denormal = infinity, with the exception of 2-expon_base fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fpresult (exponent_width) := to_x01 (arg (exponent_width)); else break_number ( arg => arg, fptyp => fptype, denormalize => denormalize, fract => fract, expon => expon); fractg := (others => '0'); if (fptype = pos_denormal or fptype = neg_denormal) then -- The reciprocal of a denormal number is typically zero, -- except for two special cases which are trapped here. if (to_x01(arg (-1)) = '1') then fractg (fractg'high downto divguard+1) := fract (fract'high-1 downto 0); -- Shift to not denormal denorm_offset := 1; -- add 1 to exponent compensate else -- arg(-2) = '1' fractg (fractg'high downto divguard+2) := fract (fract'high-2 downto 0); -- Shift to not denormal denorm_offset := 2; -- add 2 to exponent compensate end if; else fractg (fractg'high downto divguard) := fract; denorm_offset := 0; end if; expon := - expon - 3 + denorm_offset; sfract := onedivy (fractg); -- normalize fpresult := normalize (fract => sfract, expon => expon, sign => arg(exponent_width), sticky => '1', fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => divguard); end if; end case classcase; return fpresult; end function reciprocal; -- floating point division function divide ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant divguard : NATURAL := guard; -- division guard bits variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable ulfract, urfract : UNSIGNED (fraction_width downto 0); variable fractl : UNSIGNED ((2(fraction_width+divguard)+1) downto 0); -- left variable fractr : UNSIGNED (fraction_width+divguard downto 0); -- right variable rfract : UNSIGNED (fractl'range); -- result fraction variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent variable fp_sign, sticky : STD_ULOGIC; -- sign of result variable shifty, shiftx : INTEGER; -- denormal number shift variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- divide if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; classcase : case rfptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => if lfptype = pos_inf or lfptype = neg_inf -- inf / inf or lfptype = quiet_nan or lfptype = nan then -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else -- x / inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when pos_zero \| neg_zero => if lfptype = pos_zero or lfptype = neg_zero -- 0 / 0 or lfptype = quiet_nan or lfptype = nan then -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else report float_generic_pkg'instance_name & "DIVIDE: Floating Point divide by zero" severity error; -- Infinity, define in 754-1985-7.2 fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when others => classcase2 : case lfptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => -- inf / x = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult(exponent_width) := fp_sign; when pos_zero \| neg_zero => -- 0 / X = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult(exponent_width) := fp_sign; when others => fp_sign := l(l'high) xor r(r'high); -- sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); -- right side break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); -- Compute the exponent rexpon := resize (exponl, rexpon'length) - exponr - 2; if (rfptype = pos_denormal or rfptype = neg_denormal) then -- Do the shifting here not after. That way we have a smaller -- shifter, and need a smaller divider, because the top -- bit in the divisor will always be a "1". shifty := fraction_width - find_leftmost(urfract, '1'); urfract := shift_left (urfract, shifty); rexpon := rexpon + shifty; end if; fractr := (others => '0'); fractr (fraction_width+divguard downto divguard) := urfract; if (lfptype = pos_denormal or lfptype = neg_denormal) then shiftx := fraction_width - find_leftmost(ulfract, '1'); ulfract := shift_left (ulfract, shiftx); rexpon := rexpon - shiftx; end if; fractl := (others => '0'); fractl (fractl'high downto fractl'high-fraction_width) := ulfract; -- divide rfract := short_divide (fractl, fractr); -- unsigned divide sfract := rfract (sfract'range); -- lower bits sticky := '1'; -- normalize fpresult := normalize (fract => sfract, expon => rexpon, sign => fp_sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => divguard); end case classcase2; end case classcase; return fpresult; end function divide; -- division by a power of 2 function dividebyp2 ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable ulfract, urfract : UNSIGNED (fraction_width downto 0); variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED(exponent_width downto 0); -- result exponent variable fp_sign : STD_ULOGIC; -- sign of result variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- divisionbyp2 if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; classcase : case rfptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => if lfptype = pos_inf or lfptype = neg_inf then -- inf / inf -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else -- x / inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when pos_zero \| neg_zero => if lfptype = pos_zero or lfptype = neg_zero then -- 0 / 0 -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else report FLOAT_GENERIC_PKG'instance_name & "DIVIDEBYP2: Floating Point divide by zero" severity error; -- Infinity, define in 754-1985-7.2 fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when others => classcase2 : case lfptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => -- inf / x = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (exponent_width) := fp_sign; -- sign when pos_zero \| neg_zero => -- 0 / X = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (exponent_width) := fp_sign; -- sign when others => fp_sign := l(l'high) xor r(r'high); -- sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); -- right side break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); assert (or (urfract (fraction_width-1 downto 0)) = '0') report FLOAT_GENERIC_PKG'instance_name & "DIVIDEBYP2: " & "Dividebyp2 called with a non power of two divisor" severity error; rexpon := (exponl(exponl'high)&exponl) - (exponr(exponr'high)&exponr) - 1; -- normalize fpresult := normalize (fract => ulfract, expon => rexpon, sign => fp_sign, sticky => '1', fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => 0); end case classcase2; end case classcase; return fpresult; end function dividebyp2; -- Multiply accumulate result = lr + c function mac ( l, r, c : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine (mine(l'low, r'low), c'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum (maximum(l'high, r'high), c'high); -- length of FP output exponent variable lfptype, rfptype, cfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions variable fractx : UNSIGNED (fraction_width+guard downto 0); variable fractc, fracts : UNSIGNED (fraction_width+1+guard downto 0); variable rfract : UNSIGNED ((2(fraction_width))+1 downto 0); -- result fraction variable sfract, ufract : UNSIGNED (fraction_width+1+guard downto 0); -- result fraction variable exponl, exponr, exponc : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon, rexpon2 : SIGNED (exponent_width+1 downto 0); -- result exponent variable shifty : INTEGER; -- denormal shift variable shiftx : SIGNED (rexpon'range); -- shift fractions variable fp_sign : STD_ULOGIC; -- sign of result variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); variable cresize : UNRESOLVED_float (exponent_width downto -fraction_width - guard); variable leftright : BOOLEAN; -- left or right used variable sticky : STD_ULOGIC; -- Holds precision for rounding begin -- multiply if (fraction_width = 0 or l'length < 7 or r'length < 7 or c'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); cfptype := classfp (c, check_error); end if; if (lfptype = isx or rfptype = isx or cfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan or cfptype = nan or cfptype = quiet_nan) then -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (((lfptype = pos_inf or lfptype = neg_inf) and (rfptype = pos_zero or rfptype = neg_zero)) or ((rfptype = pos_inf or rfptype = neg_inf) and (lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf -- Return quiet NAN, IEEE754-1985-7.1,3 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = pos_inf or rfptype = pos_inf or lfptype = neg_inf or rfptype = neg_inf -- x * inf = inf or cfptype = neg_inf or cfptype = pos_inf) then -- x + inf = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); -- figure out the sign fpresult (exponent_width) := l(l'high) xor r(r'high); else fp_sign := l(l'high) xor r(r'high); -- figure out the sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked cresize := resize (arg => to_x01(c), exponent_width => exponent_width, fraction_width => -cresize'low, denormalize_in => denormalize, denormalize => denormalize); cfptype := classfp (cresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => fractl, expon => exponl); break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => fractr, expon => exponr); break_number ( arg => cresize, fptyp => cfptype, denormalize => denormalize, fract => fractx, expon => exponc); if (rfptype = pos_denormal or rfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractr, '1'); fractr := shift_left (fractr, shifty); elsif (lfptype = pos_denormal or lfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractl, '1'); fractl := shift_left (fractl, shifty); else shifty := 0; -- Note that a denormal number * a denormal number is always zero. end if; -- multiply rfract := fractl * fractr; -- Multiply the fraction -- add the exponents rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1; shiftx := rexpon - exponc; if shiftx < -fractl'high then rexpon2 := resize (exponc, rexpon2'length); fractc := "0" & fractx; fracts := (others => '0'); sticky := or (rfract); elsif shiftx < 0 then shiftx := - shiftx; fracts := shift_right (rfract (rfract'high downto rfract'high - fracts'length+1), to_integer(shiftx)); fractc := "0" & fractx; rexpon2 := resize (exponc, rexpon2'length); leftright := false; sticky := or (rfract (to_integer(shiftx)+rfract'high - fracts'length downto 0)); elsif shiftx = 0 then rexpon2 := resize (exponc, rexpon2'length); sticky := or (rfract (rfract'high - fractc'length downto 0)); if rfract (rfract'high downto rfract'high - fractc'length+1) > fractx then fractc := "0" & fractx; fracts := rfract (rfract'high downto rfract'high - fracts'length+1); leftright := false; else fractc := rfract (rfract'high downto rfract'high - fractc'length+1); fracts := "0" & fractx; leftright := true; end if; elsif shiftx > fractx'high then rexpon2 := rexpon; fracts := (others => '0'); fractc := rfract (rfract'high downto rfract'high - fractc'length+1); leftright := true; sticky := or (fractx & rfract (rfract'high - fractc'length downto 0)); else -- fractx'high > shiftx > 0 rexpon2 := rexpon; fracts := "0" & shift_right (fractx, to_integer (shiftx)); fractc := rfract (rfract'high downto rfract'high - fractc'length+1); leftright := true; sticky := or (fractx (to_integer (shiftx) downto 0) & rfract (rfract'high - fractc'length downto 0)); end if; fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB if fp_sign = to_X01(c(c'high)) then ufract := fractc + fracts; fp_sign := fp_sign; else -- signs are different ufract := fractc - fracts; -- always positive result if leftright then -- Figure out which sign to use fp_sign := fp_sign; else fp_sign := c(c'high); end if; end if; -- normalize fpresult := normalize (fract => ufract, expon => rexpon2, sign => fp_sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => guard); end if; return fpresult; end function mac; -- "rem" function function remainder ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant divguard : NATURAL := guard; -- division guard bits variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable ulfract, urfract : UNSIGNED (fraction_width downto 0); variable fractr, fractl : UNSIGNED (fraction_width+divguard downto 0); -- right variable rfract : UNSIGNED (fractr'range); -- result fraction variable sfract : UNSIGNED (fraction_width+divguard downto 0); -- result fraction variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width downto 0); -- result exponent variable fp_sign : STD_ULOGIC; -- sign of result variable shifty : INTEGER; -- denormal number shift variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- remainder if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan) or (rfptype = nan or rfptype = quiet_nan) -- Return quiet NAN, IEEE754-1985-7.1,1 or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x -- Return quiet NAN, IEEE754-1985-7.1,5 or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0 -- Return quiet NAN, IEEE754-1985-7.1,5 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (abs(l) < abs(r)) then fpresult := l; else fp_sign := to_X01(l(l'high)); -- sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked fractl := (others => '0'); break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); fractl (fraction_width+divguard downto divguard) := ulfract; -- right side fractr := (others => '0'); break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); fractr (fraction_width+divguard downto divguard) := urfract; rexpon := (exponr(exponr'high)&exponr); shifty := to_integer(exponl - rexpon); if (shifty > 0) then fractr := shift_right (fractr, shifty); rexpon := rexpon + shifty; end if; if (fractr /= 0) then -- rem rfract := fractl rem fractr; -- unsigned rem sfract := rfract (sfract'range); -- lower bits -- normalize fpresult := normalize (fract => sfract, expon => rexpon, sign => fp_sign, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => divguard); else -- If we shift "fractr" so far that it becomes zero, return zero. fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); end if; end if; return fpresult; end function remainder; -- "mod" function function modulo ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := - mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable remres : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- remainder if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan) or (rfptype = nan or rfptype = quiet_nan) -- Return quiet NAN, IEEE754-1985-7.1,1 or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x -- Return quiet NAN, IEEE754-1985-7.1,5 or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0 -- Return quiet NAN, IEEE754-1985-7.1,5 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else remres := remainder (l => abs(l), r => abs(r), round_style => round_style, guard => guard, check_error => false, denormalize => denormalize); -- MOD is the same as REM, but you do something different with -- negative values if (is_negative (l)) then remres := - remres; end if; if (is_negative (l) = is_negative (r) or remres = 0) then fpresult := remres; else fpresult := add (l => remres, r => r, round_style => round_style, guard => guard, check_error => false, denormalize => denormalize); end if; end if; return fpresult; end function modulo; -- Square root of a floating point number. Done using Newton's Iteration. function sqrt ( arg : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; constant guard : NATURAL := float_guard_bits; constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_float is constant fraction_width : NATURAL := guard-arg'low; -- length of FP output fraction constant exponent_width : NATURAL := arg'high; -- length of FP output exponent variable sign : STD_ULOGIC; variable fpresult : float (arg'range); variable fptype : valid_fpstate; variable iexpon : SIGNED(exponent_width-1 downto 0); -- exponents variable expon : SIGNED(exponent_width downto 0); -- exponents variable ufact : ufixed (0 downto arg'low); variable fact : ufixed (2 downto -fraction_width); -- fraction variable resb : ufixed (fact'high+1 downto fact'low); begin -- square root fptype := Classfp (arg, check_error); classcase : case fptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan \| -- Return quiet NAN, IEEE754-1985-7.1,1 neg_normal \| neg_denormal \| neg_inf => -- sqrt (neg) -- Return quiet NAN, IEEE754-1985-7.1.6 fpresult := qnanfp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when pos_inf => -- Sqrt (inf), return infinity fpresult := pos_inffp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when pos_zero => -- return 0 fpresult := zerofp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when neg_zero => -- IEEE754-1985-6.3 return -0 fpresult := neg_zerofp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when others => break_number (arg => arg, denormalize => denormalize, check_error => false, fract => ufact, expon => iexpon, sign => sign); expon := resize (iexpon+1, expon'length); -- get exponent fact := resize (ufact, fact'high, fact'low); if (expon(0) = '1') then fact := fact sla 1; -- * 2.0 end if; expon := shift_right (expon, 1); -- exponent/2 -- Newton's iteration - root := (1 + arg) / 2 resb := (fact + 1) sra 1; for j in 0 to fraction_width/4 loop -- root := (root + (arg/root))/2 resb := resize (arg => (resb + (fact/resb)) sra 1, left_index => resb'high, right_index => resb'low, round_style => fixed_truncate, overflow_style => fixed_wrap); end loop; fpresult := normalize (fract => resb, expon => expon-1, sign => '0', exponent_width => arg'high, fraction_width => -arg'low, round_style => round_style, denormalize => denormalize, nguard => guard); end case classcase; return fpresult; end function sqrt; function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN is -- Technically -0 should return "false", but I'm leaving that case out. begin return (to_x01(arg(arg'high)) = '1'); end function Is_Negative; -- compare functions -- =, /=, >=, <=, <, > function eq ( -- equal = l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable lfptype, rfptype : valid_fpstate; variable is_equal, is_unordered : BOOLEAN; constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- equal if (fraction_width = 0 or l'length < 7 or r'length < 7) then return false; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = neg_zero or lfptype = pos_zero) and (rfptype = neg_zero or rfptype = pos_zero) then is_equal := true; else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); is_equal := (to_slv(lresize) = to_slv(rresize)); end if; if (check_error) then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return is_equal and not is_unordered; end function eq; function lt ( -- less than < l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable expl, expr : UNSIGNED (exponent_width-1 downto 0); variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0); variable is_less_than, is_unordered : BOOLEAN; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then is_less_than := false; else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits expl := UNSIGNED(lresize(exponent_width-1 downto 0)); expr := UNSIGNED(rresize(exponent_width-1 downto 0)); if expl = expr then fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width))); fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width))); if to_x01(l(l'high)) = '0' then -- positive number is_less_than := (fractl < fractr); else is_less_than := (fractl > fractr); -- negative end if; else if to_x01(l(l'high)) = '0' then -- positive number is_less_than := (expl < expr); else is_less_than := (expl > expr); -- negative end if; end if; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); if (lfptype = neg_zero and rfptype = pos_zero) then is_less_than := false; -- -0 < 0 returns false. else is_less_than := (to_x01(l(l'high)) > to_x01(r(r'high))); end if; end if; end if; if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return is_less_than and not is_unordered; end function lt; function gt ( -- greater than > l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable expl, expr : UNSIGNED (exponent_width-1 downto 0); variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0); variable is_greater_than : BOOLEAN; variable is_unordered : BOOLEAN; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- greater_than if (fraction_width = 0 or l'length < 7 or r'length < 7) then is_greater_than := false; else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits expl := UNSIGNED(lresize(exponent_width-1 downto 0)); expr := UNSIGNED(rresize(exponent_width-1 downto 0)); if expl = expr then fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width))); fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width))); if to_x01(l(l'high)) = '0' then -- positive number is_greater_than := fractl > fractr; else is_greater_than := fractl < fractr; -- negative end if; else if to_x01(l(l'high)) = '0' then -- positive number is_greater_than := expl > expr; else is_greater_than := expl < expr; -- negative end if; end if; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); if (lfptype = pos_zero and rfptype = neg_zero) then is_greater_than := false; -- 0 > -0 returns false. else is_greater_than := to_x01(l(l'high)) < to_x01(r(r'high)); end if; end if; end if; if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return is_greater_than and not is_unordered; end function gt; -- purpose: /= function function ne ( -- not equal /= l, r : UNRESOLVED_float; constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable is_equal, is_unordered : BOOLEAN; begin is_equal := eq (l => l, r => r, check_error => false, denormalize => denormalize); if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return not (is_equal and not is_unordered); end function ne; function le ( -- less than or equal to <= l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable is_greater_than, is_unordered : BOOLEAN; begin is_greater_than := gt (l => l, r => r, check_error => false, denormalize => denormalize); if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return not is_greater_than and not is_unordered; end function le; function ge ( -- greater than or equal to >= l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable is_less_than, is_unordered : BOOLEAN; begin is_less_than := lt (l => l, r => r, check_error => false, denormalize => denormalize); if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return not is_less_than and not is_unordered; end function ge; function "?=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable is_equal, is_unordered : STD_ULOGIC; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- ?= if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else lfptype := classfp (l, float_check_error); rfptype := classfp (r, float_check_error); end if; if (lfptype = neg_zero or lfptype = pos_zero) and (rfptype = neg_zero or rfptype = pos_zero) then is_equal := '1'; else lresize := resize (arg => l, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); rresize := resize (arg => r, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); is_equal := to_sulv(lresize) ?= to_sulv(rresize); end if; if (float_check_error) then if (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan) then is_unordered := '1'; else is_unordered := '0'; end if; else is_unordered := '0'; end if; return is_equal and not is_unordered; end function "?="; function "?/=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable is_equal, is_unordered : STD_ULOGIC; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- ?/= if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else lfptype := classfp (l, float_check_error); rfptype := classfp (r, float_check_error); end if; if (lfptype = neg_zero or lfptype = pos_zero) and (rfptype = neg_zero or rfptype = pos_zero) then is_equal := '1'; else lresize := resize (arg => l, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); rresize := resize (arg => r, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); is_equal := to_sulv(lresize) ?= to_sulv(rresize); end if; if (float_check_error) then if (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan) then is_unordered := '1'; else is_unordered := '0'; end if; else is_unordered := '0'; end if; return not (is_equal and not is_unordered); end function "?/="; function "?>" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?>"": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l > r then return '1'; else return '0'; end if; end if; end function "?>"; function "?>=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?>="": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l >= r then return '1'; else return '0'; end if; end if; end function "?>="; function "?<" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?<"": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l < r then return '1'; else return '0'; end if; end if; end function "?<"; function "?<=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?<="": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l <= r then return '1'; else return '0'; end if; end if; end function "?<="; function std_match (L, R : UNRESOLVED_float) return BOOLEAN is begin if (L'high = R'high and L'low = R'low) then return std_match(to_sulv(L), to_sulv(R)); else report float_generic_pkg'instance_name & "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE" severity warning; return false; end if; end function std_match; function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is begin for_loop : for i in arg'reverse_range loop if arg(i) ?= y then return i; end if; end loop; return arg'high+1; -- return out of bounds 'high end function find_rightmost; function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is begin for_loop : for i in arg'range loop if arg(i) ?= y then return i; end if; end loop; return arg'low-1; -- return out of bounds 'low end function find_leftmost; -- These override the defaults for the compare operators. function "=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return eq(l, r); end function "="; function "/=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return ne(l, r); end function "/="; function ">=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return ge(l, r); end function ">="; function "<=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return le(l, r); end function "<="; function ">" (l, r : UNRESOLVED_float) return BOOLEAN is begin return gt(l, r); end function ">"; function "<" (l, r : UNRESOLVED_float) return BOOLEAN is begin return lt(l, r); end function "<"; -- purpose: maximum of two numbers (overrides default) function maximum ( L, R : UNRESOLVED_float) return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin if ((L'length < 1) or (R'length < 1)) then return NAFP; end if; lresize := resize (l, exponent_width, fraction_width); rresize := resize (r, exponent_width, fraction_width); if lresize > rresize then return lresize; else return rresize; end if; end function maximum; function minimum ( L, R : UNRESOLVED_float) return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin if ((L'length < 1) or (R'length < 1)) then return NAFP; end if; lresize := resize (l, exponent_width, fraction_width); rresize := resize (r, exponent_width, fraction_width); if lresize > rresize then return rresize; else return lresize; end if; end function minimum; ----------------------------------------------------------------------------- -- conversion functions ----------------------------------------------------------------------------- -- Converts a floating point number of one format into another format function resize ( arg : UNRESOLVED_float; -- Floating point input constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant in_fraction_width : NATURAL := -arg'low; -- length of FP output fraction constant in_exponent_width : NATURAL := arg'high; -- length of FP output exponent variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result value variable fptype : valid_fpstate; variable expon_in : SIGNED (in_exponent_width-1 downto 0); variable fract_in : UNSIGNED (in_fraction_width downto 0); variable round : BOOLEAN; variable expon_out : SIGNED (exponent_width-1 downto 0); -- output fract variable fract_out : UNSIGNED (fraction_width downto 0); -- output fract variable passguard : NATURAL; begin fptype := classfp(arg, check_error); if ((fptype = pos_denormal or fptype = neg_denormal) and denormalize_in and (in_exponent_width < exponent_width or in_fraction_width < fraction_width)) or in_exponent_width > exponent_width or in_fraction_width > fraction_width then -- size reduction classcase : case fptype is when isx => result := (others => 'X'); when nan \| quiet_nan => result := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf => result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); when neg_inf => result := neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_zero \| neg_zero => result := zerofp (fraction_width => fraction_width, -- hate -0 exponent_width => exponent_width); when others => break_number ( arg => arg, fptyp => fptype, denormalize => denormalize_in, fract => fract_in, expon => expon_in); if fraction_width > in_fraction_width and denormalize_in then -- You only get here if you have a denormal input fract_out := (others => '0'); -- pad with zeros fract_out (fraction_width downto fraction_width - in_fraction_width) := fract_in; result := normalize ( fract => fract_out, expon => expon_in, sign => arg(arg'high), fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => 0); else result := normalize ( fract => fract_in, expon => expon_in, sign => arg(arg'high), fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => in_fraction_width - fraction_width); end if; end case classcase; else -- size increase or the same size if exponent_width > in_exponent_width then expon_in := SIGNED(arg (in_exponent_width-1 downto 0)); if fptype = pos_zero or fptype = neg_zero then result (exponent_width-1 downto 0) := (others => '0'); elsif expon_in = -1 then -- inf or nan (shorts out check_error) result (exponent_width-1 downto 0) := (others => '1'); else -- invert top BIT expon_in(expon_in'high) := not expon_in(expon_in'high); expon_out := resize (expon_in, expon_out'length); -- signed expand -- Flip it back. expon_out(expon_out'high) := not expon_out(expon_out'high); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon_out); end if; result (exponent_width) := arg (in_exponent_width); -- sign else -- exponent_width = in_exponent_width result (exponent_width downto 0) := arg (in_exponent_width downto 0); end if; if fraction_width > in_fraction_width then result (-1 downto -fraction_width) := (others => '0'); -- zeros result (-1 downto -in_fraction_width) := arg (-1 downto -in_fraction_width); else -- fraction_width = in_fraciton_width result (-1 downto -fraction_width) := arg (-1 downto -in_fraction_width); end if; end if; return result; end function resize; function resize ( arg : UNRESOLVED_float; -- floating point input size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := resize (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); return result; end if; end function resize; function to_float32 ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float32 is begin return resize (arg => arg, exponent_width => float32'high, fraction_width => -float32'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); end function to_float32; function to_float64 ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float64 is begin return resize (arg => arg, exponent_width => float64'high, fraction_width => -float64'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); end function to_float64; function to_float128 ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float128 is begin return resize (arg => arg, exponent_width => float128'high, fraction_width => -float128'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); end function to_float128; -- to_float (Real) -- typically not Synthesizable unless the input is a constant. function to_float ( arg : REAL; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arg_real : REAL; -- Real version of argument variable validfp : boundary_type; -- Check for valid results variable exp : INTEGER; -- Integer version of exponent variable expon : UNSIGNED (exponent_width - 1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fract : UNSIGNED (fraction_width-1 downto 0); variable frac : REAL; -- Real version of fraction constant roundfrac : REAL := 2.0 ** (-2 - fract'high); -- used for rounding variable round : BOOLEAN; -- to round or not to round begin result := (others => '0'); arg_real := arg; if arg_real < 0.0 then result (exponent_width) := '1'; arg_real := - arg_real; -- Make it positive. else result (exponent_width) := '0'; end if; test_boundary (arg => arg_real, fraction_width => fraction_width, exponent_width => exponent_width, denormalize => denormalize, btype => validfp, log2i => exp); if validfp = zero then return result; -- Result initialized to "0". elsif validfp = infinity then result (exponent_width - 1 downto 0) := (others => '1'); -- Exponent all "1" -- return infinity. return result; else if validfp = denormal then -- Exponent will default to "0". expon := (others => '0'); frac := arg_real * (2.0 (to_integer(expon_base)-1)); else -- Number less than 1. "normal" number expon := UNSIGNED (to_signed (exp-1, exponent_width)); expon(exponent_width-1) := not expon(exponent_width-1); frac := (arg_real / 2.0 exp) - 1.0; -- Number less than 1. end if; for i in 0 to fract'high loop if frac >= 2.0 (-1 - i) then fract (fract'high - i) := '1'; frac := frac - 2.0 (-1 - i); else fract (fract'high - i) := '0'; end if; end loop; round := false; case round_style is when round_nearest => if frac > roundfrac or ((frac = roundfrac) and fract(0) = '1') then round := true; end if; when round_inf => if frac /= 0.0 and result(exponent_width) = '0' then round := true; end if; when round_neginf => if frac /= 0.0 and result(exponent_width) = '1' then round := true; end if; when others => null; -- don't round end case; if (round) then if and(fract) = '1' then -- fraction is all "1" expon := expon + 1; fract := (others => '0'); else fract := fract + 1; end if; end if; result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(fract); return result; end if; end function to_float; -- to_float (Integer) function to_float ( arg : INTEGER; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arg_int : NATURAL; -- Natural version of argument variable expon : SIGNED (exponent_width-1 downto 0); variable exptmp : SIGNED (exponent_width-1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fract : UNSIGNED (fraction_width-1 downto 0) := (others => '0'); variable fracttmp : UNSIGNED (fraction_width-1 downto 0); variable round : BOOLEAN; variable shift : NATURAL; variable shiftr : NATURAL; variable roundfrac : NATURAL; -- used in rounding begin if arg < 0 then result (exponent_width) := '1'; arg_int := -arg; -- Make it positive. else result (exponent_width) := '0'; arg_int := arg; end if; if arg_int = 0 then result := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else -- If the number is larger than we can represent in this number system -- we need to return infinity. shift := log2(arg_int); if shift > to_integer(expon_base) then -- worry about infinity if result (exponent_width) = '0' then result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else -- return negative infinity. result := neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); end if; else -- Normal number (can't be denormal) -- Compute Exponent expon := to_signed (shift-1, expon'length); -- positive fraction. -- Compute Fraction arg_int := arg_int - 2shift; -- Subtract off the 1.0 shiftr := shift; for I in fract'high downto maximum (fract'high - shift + 1, 0) loop shiftr := shiftr - 1; if (arg_int >= 2shiftr) then arg_int := arg_int - 2shiftr; fract(I) := '1'; else fract(I) := '0'; end if; end loop; -- Rounding routine round := false; if arg_int > 0 then roundfrac := 2(shiftr-1); case round_style is when round_nearest => if arg_int > roundfrac or ((arg_int = roundfrac) and fract(0) = '1') then round := true; end if; when round_inf => if arg_int /= 0 and result (exponent_width) = '0' then round := true; end if; when round_neginf => if arg_int /= 0 and result (exponent_width) = '1' then round := true; end if; when others => null; end case; end if; if round then fp_round(fract_in => fract, expon_in => expon, fract_out => fracttmp, expon_out => exptmp); fract := fracttmp; expon := exptmp; end if; -- Put the number together and return expon(exponent_width-1) := not expon(exponent_width-1); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(fract); end if; end if; return result; end function to_float; -- to_float (unsigned) function to_float ( arg : UNRESOLVED_UNSIGNED; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG; variable sarg : SIGNED (ARG_LEFT+1 downto 0); -- signed version of arg begin if arg'length < 1 then return NAFP; end if; sarg (XARG'range) := SIGNED (XARG); sarg (sarg'high) := '0'; result := to_float (arg => sarg, exponent_width => exponent_width, fraction_width => fraction_width, round_style => round_style); return result; end function to_float; -- to_float (signed) function to_float ( arg : UNRESOLVED_SIGNED; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : SIGNED(ARG_LEFT downto 0) is ARG; variable arg_int : UNSIGNED(xarg'range); -- Real version of argument variable argb2 : UNSIGNED(xarg'high/2 downto 0); -- log2 of input variable rexp : SIGNED (exponent_width - 1 downto 0); variable exp : SIGNED (exponent_width - 1 downto 0); -- signed version of exp. variable expon : UNSIGNED (exponent_width - 1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable round : BOOLEAN; variable fract : UNSIGNED (fraction_width-1 downto 0); variable rfract : UNSIGNED (fraction_width-1 downto 0); variable sign : STD_ULOGIC; -- sign bit begin if arg'length < 1 then return NAFP; end if; if Is_X (xarg) then result := (others => 'X'); elsif (xarg = 0) then result := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else -- Normal number (can't be denormal) sign := to_X01(xarg (xarg'high)); arg_int := UNSIGNED(abs (to_01(xarg))); -- Compute Exponent argb2 := to_unsigned(find_leftmost(arg_int, '1'), argb2'length); -- Log2 if argb2 > UNSIGNED(expon_base) then result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); result (exponent_width) := sign; else exp := SIGNED(resize(argb2, exp'length)); arg_int := shift_left (arg_int, arg_int'high-to_integer(exp)); if (arg_int'high > fraction_width) then fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)); round := check_round ( fract_in => fract (0), sign => sign, remainder => arg_int((arg_int'high-fraction_width-1) downto 0), round_style => round_style); if round then fp_round(fract_in => fract, expon_in => exp, fract_out => rfract, expon_out => rexp); else rfract := fract; rexp := exp; end if; else rexp := exp; rfract := (others => '0'); rfract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) := arg_int (arg_int'high-1 downto 0); end if; result (exponent_width) := sign; expon := UNSIGNED (rexp-1); expon(exponent_width-1) := not expon(exponent_width-1); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(rfract); end if; end if; return result; end function to_float; -- std_logic_vector to float function to_float ( arg : STD_ULOGIC_VECTOR; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction return UNRESOLVED_float is variable fpvar : UNRESOLVED_float (exponent_width downto -fraction_width); begin if arg'length < 1 then return NAFP; end if; fpvar := UNRESOLVED_float(arg); return fpvar; end function to_float; -- purpose: converts a ufixed to a floating point function to_float ( arg : UNRESOLVED_ufixed; -- unsigned fixed point input constant exponent_width : NATURAL := float_exponent_width; -- width of exponent constant fraction_width : NATURAL := float_fraction_width; -- width of fraction constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions return UNRESOLVED_float is variable sarg : sfixed (arg'high+1 downto arg'low); -- Signed version of arg variable result : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- function to_float if (arg'length < 1) then return NAFP; end if; sarg (arg'range) := sfixed (arg); sarg (sarg'high) := '0'; result := to_float (arg => sarg, exponent_width => exponent_width, fraction_width => fraction_width, round_style => round_style, denormalize => denormalize); return result; end function to_float; function to_float ( arg : UNRESOLVED_sfixed; -- signed fixed point constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- rounding option return UNRESOLVED_float is constant integer_width : INTEGER := arg'high; constant in_fraction_width : INTEGER := arg'low; variable xresult : sfixed (integer_width downto in_fraction_width); variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arg_int : UNSIGNED(integer_width - in_fraction_width - 1 downto 0); -- signed version of argument variable argx : SIGNED (integer_width - in_fraction_width downto 0); variable exp, exptmp : SIGNED (exponent_width downto 0); variable expon : UNSIGNED (exponent_width - 1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) := (others => '0'); variable round : BOOLEAN := false; begin if (arg'length < 1) then return NAFP; end if; xresult := to_01(arg, 'X'); argx := SIGNED(to_slv(xresult)); if (Is_X (arg)) then result := (others => 'X'); elsif (argx = 0) then result := (others => '0'); else result := (others => '0'); -- zero out the result if argx(argx'left) = '1' then -- toss the sign bit result (exponent_width) := '1'; -- Negative number argx := -argx; -- Make it positive. else result (exponent_width) := '0'; end if; arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (argx(arg_int'range)))); -- Compute Exponent exp := to_signed(find_leftmost(arg_int, '1'), exp'length); -- Log2 if exp + in_fraction_width > expon_base then -- return infinity result (-1 downto -fraction_width) := (others => '0'); result (exponent_width -1 downto 0) := (others => '1'); return result; elsif (denormalize and (exp + in_fraction_width <= -resize(expon_base, exp'length))) then exp := -resize(expon_base, exp'length); -- shift by a constant arg_int := shift_left (arg_int, (arg_int'high + to_integer(expon_base) + in_fraction_width - 1)); if (arg_int'high > fraction_width) then fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)); round := check_round ( fract_in => arg_int(arg_int'high-fraction_width), sign => result(result'high), remainder => arg_int((arg_int'high-fraction_width-1) downto 0), round_style => round_style); if (round) then fp_round (fract_in => arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)), expon_in => exp, fract_out => fract, expon_out => exptmp); exp := exptmp; end if; else fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) := arg_int (arg_int'high-1 downto 0); end if; else arg_int := shift_left (arg_int, arg_int'high-to_integer(exp)); exp := exp + in_fraction_width; if (arg_int'high > fraction_width) then fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)); round := check_round ( fract_in => fract(0), sign => result(result'high), remainder => arg_int((arg_int'high-fraction_width-1) downto 0), round_style => round_style); if (round) then fp_round (fract_in => fract, expon_in => exp, fract_out => fracttmp, expon_out => exptmp); fract := fracttmp; exp := exptmp; end if; else fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) := arg_int (arg_int'high-1 downto 0); end if; end if; expon := UNSIGNED (resize(exp-1, exponent_width)); expon(exponent_width-1) := not expon(exponent_width-1); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(fract); end if; return result; end function to_float; -- size_res functions -- Integer to float function to_float ( arg : INTEGER; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style); return result; end if; end function to_float; -- real to float function to_float ( arg : REAL; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, denormalize => denormalize); return result; end if; end function to_float; -- unsigned to float function to_float ( arg : UNRESOLVED_UNSIGNED; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style); return result; end if; end function to_float; -- signed to float function to_float ( arg : UNRESOLVED_SIGNED; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style) -- rounding return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style); return result; end if; end function to_float; -- std_ulogic_vector to float function to_float ( arg : STD_ULOGIC_VECTOR; size_res : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low); return result; end if; end function to_float; -- unsigned fixed point to float function to_float ( arg : UNRESOLVED_ufixed; -- unsigned fixed point input size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, denormalize => denormalize); return result; end if; end function to_float; -- signed fixed point to float function to_float ( arg : UNRESOLVED_sfixed; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, denormalize => denormalize); return result; end if; end function to_float; -- to_integer (float) function to_integer ( arg : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return INTEGER is variable validfp : valid_fpstate; -- Valid FP state variable frac : UNSIGNED (-arg'low downto 0); -- Fraction variable fract : UNSIGNED (1-arg'low downto 0); -- Fraction variable expon : SIGNED (arg'high-1 downto 0); variable isign : STD_ULOGIC; -- internal version of sign variable round : STD_ULOGIC; -- is rounding needed? variable result : INTEGER; variable base : INTEGER; -- Integer exponent begin validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan \| pos_zero \| neg_zero \| pos_denormal \| neg_denormal => result := 0; -- return 0 when pos_inf => result := INTEGER'high; when neg_inf => result := INTEGER'low; when others => break_number ( arg => arg, fptyp => validfp, denormalize => false, fract => frac, expon => expon); fract (fract'high) := '0'; -- Add extra bit for 0.6 case fract (fract'high-1 downto 0) := frac; isign := to_x01 (arg (arg'high)); base := to_integer (expon) + 1; if base < -1 then result := 0; elsif base >= frac'high then result := to_integer (fract) * 2(base - frac'high); else -- We need to round if base = -1 then -- trap for 0.6 case. result := 0; else result := to_integer (fract (frac'high downto frac'high-base)); end if; -- rounding routine case round_style is when round_nearest => if frac'high - base > 1 then round := fract (frac'high - base - 1) and (fract (frac'high - base) or (or (fract (frac'high - base - 2 downto 0)))); else round := fract (frac'high - base - 1) and fract (frac'high - base); end if; when round_inf => round := fract(frac'high - base - 1) and not isign; when round_neginf => round := fract(frac'high - base - 1) and isign; when others => round := '0'; end case; if round = '1' then result := result + 1; end if; end if; if isign = '1' then result := - result; end if; end case classcase; return result; end function to_integer; -- to_unsigned (float) function to_unsigned ( arg : UNRESOLVED_float; -- floating point input constant size : NATURAL; -- length of output constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_UNSIGNED is variable validfp : valid_fpstate; -- Valid FP state variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction variable sign : STD_ULOGIC; -- not used begin validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan => frac := (others => 'X'); when pos_zero \| neg_inf \| neg_zero \| neg_normal \| pos_denormal \| neg_denormal => frac := (others => '0'); -- return 0 when pos_inf => frac := (others => '1'); when others => float_to_unsigned ( arg => arg, frac => frac, sign => sign, denormalize => false, bias => 0, round_style => round_style); end case classcase; return (frac); end function to_unsigned; -- to_signed (float) function to_signed ( arg : UNRESOLVED_float; -- floating point input constant size : NATURAL; -- length of output constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_SIGNED is variable sign : STD_ULOGIC; -- true if negative variable validfp : valid_fpstate; -- Valid FP state variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction variable result : UNRESOLVED_SIGNED (size-1 downto 0); begin validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan => result := (others => 'X'); when pos_zero \| neg_zero \| pos_denormal \| neg_denormal => result := (others => '0'); -- return 0 when pos_inf => result := (others => '1'); result (result'high) := '0'; when neg_inf => result := (others => '0'); result (result'high) := '1'; when others => float_to_unsigned ( arg => arg, sign => sign, frac => frac, denormalize => false, bias => 0, round_style => round_style); result (size-1) := '0'; result (size-2 downto 0) := UNRESOLVED_SIGNED(frac (size-2 downto 0)); if sign = '1' then -- Because the most negative signed number is 1 less than the most -- positive signed number, we need this code. if frac(frac'high) = '1' then -- return most negative number result := (others => '0'); result (result'high) := '1'; else result := -result; end if; else if frac(frac'high) = '1' then -- return most positive number result := (others => '1'); result (result'high) := '0'; end if; end if; end case classcase; return result; end function to_signed; -- purpose: Converts a float to ufixed function to_ufixed ( arg : UNRESOLVED_float; -- fp input constant left_index : INTEGER; -- integer part constant right_index : INTEGER; -- fraction part constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_ufixed is constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent constant size : INTEGER := left_index - right_index + 4; -- unsigned size variable expon_base : INTEGER; -- exponent offset variable validfp : valid_fpstate; -- Valid FP state variable exp : INTEGER; -- Exponent variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent -- Base to divide fraction by variable frac : UNSIGNED (size-1 downto 0) := (others => '0'); -- Fraction variable frac_shift : UNSIGNED (size-1 downto 0); -- Fraction shifted variable shift : INTEGER; variable result_big : UNRESOLVED_ufixed (left_index downto right_index-3); variable result : UNRESOLVED_ufixed (left_index downto right_index); -- result begin -- function to_ufixed validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan => frac := (others => 'X'); when pos_zero \| neg_inf \| neg_zero \| neg_normal \| neg_denormal => frac := (others => '0'); -- return 0 when pos_inf => frac := (others => '1'); -- always saturate when others => expon_base := 2(exponent_width-1) -1; -- exponent offset -- Figure out the fraction if (validfp = pos_denormal) and denormalize then exp := -expon_base +1; frac (frac'high) := '0'; -- Remove the "1.0". else -- exponent /= '0', normal floating point expon := UNSIGNED(arg (exponent_width-1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (SIGNED(expon)) +1; frac (frac'high) := '1'; -- Add the "1.0". end if; shift := (frac'high - 3 + right_index) - exp; if fraction_width > frac'high then -- Can only use size-2 bits frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto -frac'high))); else -- can use all bits frac (frac'high-1 downto frac'high-fraction_width) := UNSIGNED (to_slv (arg(-1 downto -fraction_width))); end if; frac_shift := frac srl shift; if shift < 0 then -- Overflow frac := (others => '1'); else frac := frac_shift; end if; end case classcase; result_big := to_ufixed ( arg => STD_ULOGIC_VECTOR(frac), left_index => left_index, right_index => (right_index-3)); result := resize (arg => result_big, left_index => left_index, right_index => right_index, round_style => round_style, overflow_style => overflow_style); return result; end function to_ufixed; -- purpose: Converts a float to sfixed function to_sfixed ( arg : UNRESOLVED_float; -- fp input constant left_index : INTEGER; -- integer part constant right_index : INTEGER; -- fraction part constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_sfixed is constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent constant size : INTEGER := left_index - right_index + 4; -- unsigned size variable expon_base : INTEGER; -- exponent offset variable validfp : valid_fpstate; -- Valid FP state variable exp : INTEGER; -- Exponent variable sign : BOOLEAN; -- true if negative variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent -- Base to divide fraction by variable frac : UNSIGNED (size-2 downto 0) := (others => '0'); -- Fraction variable frac_shift : UNSIGNED (size-2 downto 0); -- Fraction shifted variable shift : INTEGER; variable rsigned : SIGNED (size-1 downto 0); -- signed version of result variable result_big : UNRESOLVED_sfixed (left_index downto right_index-3); variable result : UNRESOLVED_sfixed (left_index downto right_index) := (others => '0'); -- result begin -- function to_sfixed validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan => result := (others => 'X'); when pos_zero \| neg_zero => result := (others => '0'); -- return 0 when neg_inf => result (left_index) := '1'; -- return smallest negative number when pos_inf => result := (others => '1'); -- return largest number result (left_index) := '0'; when others => expon_base := 2(exponent_width-1) -1; -- exponent offset if arg(exponent_width) = '0' then sign := false; else sign := true; end if; -- Figure out the fraction if (validfp = pos_denormal or validfp = neg_denormal) and denormalize then exp := -expon_base +1; frac (frac'high) := '0'; -- Add the "1.0". else -- exponent /= '0', normal floating point expon := UNSIGNED(arg (exponent_width-1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (SIGNED(expon)) +1; frac (frac'high) := '1'; -- Add the "1.0". end if; shift := (frac'high - 3 + right_index) - exp; if fraction_width > frac'high then -- Can only use size-2 bits frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto -frac'high))); else -- can use all bits frac (frac'high-1 downto frac'high-fraction_width) := UNSIGNED (to_slv (arg(-1 downto -fraction_width))); end if; frac_shift := frac srl shift; if shift < 0 then -- Overflow frac := (others => '1'); else frac := frac_shift; end if; if not sign then rsigned := SIGNED("0" & frac); else rsigned := -(SIGNED("0" & frac)); end if; result_big := to_sfixed ( arg => STD_LOGIC_VECTOR(rsigned), left_index => left_index, right_index => (right_index-3)); result := resize (arg => result_big, left_index => left_index, right_index => right_index, round_style => round_style, overflow_style => overflow_style); end case classcase; return result; end function to_sfixed; -- size_res versions -- float to unsigned function to_unsigned ( arg : UNRESOLVED_float; -- floating point input size_res : UNRESOLVED_UNSIGNED; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_UNSIGNED is variable result : UNRESOLVED_UNSIGNED (size_res'range); begin if (SIZE_RES'length = 0) then return result; else result := to_unsigned ( arg => arg, size => size_res'length, round_style => round_style, check_error => check_error); return result; end if; end function to_unsigned; -- float to signed function to_signed ( arg : UNRESOLVED_float; -- floating point input size_res : UNRESOLVED_SIGNED; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_SIGNED is variable result : UNRESOLVED_SIGNED (size_res'range); begin if (SIZE_RES'length = 0) then return result; else result := to_signed ( arg => arg, size => size_res'length, round_style => round_style, check_error => check_error); return result; end if; end function to_signed; -- purpose: Converts a float to unsigned fixed point function to_ufixed ( arg : UNRESOLVED_float; -- fp input size_res : UNRESOLVED_ufixed; constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_ufixed is variable result : UNRESOLVED_ufixed (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_ufixed ( arg => arg, left_index => size_res'high, right_index => size_res'low, overflow_style => overflow_style, round_style => round_style, check_error => check_error, denormalize => denormalize); return result; end if; end function to_ufixed; -- float to signed fixed point function to_sfixed ( arg : UNRESOLVED_float; -- fp input size_res : UNRESOLVED_sfixed; constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_sfixed is variable result : UNRESOLVED_sfixed (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_sfixed ( arg => arg, left_index => size_res'high, right_index => size_res'low, overflow_style => overflow_style, round_style => round_style, check_error => check_error, denormalize => denormalize); return result; end if; end function to_sfixed; -- to_real (float) -- typically not Synthesizable unless the input is a constant. function to_real ( arg : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return REAL is constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent variable sign : REAL; -- Sign, + or - 1 variable exp : INTEGER; -- Exponent variable expon_base : INTEGER; -- exponent offset variable frac : REAL := 0.0; -- Fraction variable validfp : valid_fpstate; -- Valid FP state variable expon : UNSIGNED (exponent_width - 1 downto 0) := (others => '1'); -- Vectorized exponent begin validfp := classfp (arg, check_error); classcase : case validfp is when isx \| pos_zero \| neg_zero \| nan \| quiet_nan => return 0.0; when neg_inf => return REAL'low; -- Negative infinity. when pos_inf => return REAL'high; -- Positive infinity when others => expon_base := 2(exponent_width-1) -1; if to_X01(arg(exponent_width)) = '0' then sign := 1.0; else sign := -1.0; end if; -- Figure out the fraction for i in 0 to fraction_width-1 loop if to_X01(arg (-1 - i)) = '1' then frac := frac + (2.0 *(-1 - i)); end if; end loop; -- i if validfp = pos_normal or validfp = neg_normal or not denormalize then -- exponent /= '0', normal floating point expon := UNSIGNED(arg (exponent_width-1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (SIGNED(expon)) +1; sign := sign (2.0 ** exp) * (1.0 + frac); else -- exponent = '0', IEEE extended floating point exp := 1 - expon_base; sign := sign * (2.0 ** exp) * frac; end if; return sign; end case classcase; end function to_real; -- For Verilog compatability function realtobits (arg : REAL) return STD_ULOGIC_VECTOR is variable result : float64; -- 64 bit floating point begin result := to_float (arg => arg, exponent_width => float64'high, fraction_width => -float64'low); return to_sulv (result); end function realtobits; function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL is variable arg64 : float64; -- arg converted to float begin arg64 := to_float (arg => arg, exponent_width => float64'high, fraction_width => -float64'low); return to_real (arg64); end function bitstoreal; -- purpose: Removes meta-logical values from FP string function to_01 ( arg : UNRESOLVED_float; -- floating point input XMAP : STD_LOGIC := '0') return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin -- function to_01 if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_01: null detected, returning NULL" severity warning; return NAFP; end if; result := UNRESOLVED_float (STD_LOGIC_VECTOR(to_01(UNSIGNED(to_slv(arg)), XMAP))); return result; end function to_01; function Is_X (arg : UNRESOLVED_float) return BOOLEAN is begin return Is_X (to_slv(arg)); end function Is_X; function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_X01: null detected, returning NULL" severity warning; return NAFP; else result := UNRESOLVED_float (to_X01(to_slv(arg))); return result; end if; end function to_X01; function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_X01Z: null detected, returning NULL" severity warning; return NAFP; else result := UNRESOLVED_float (to_X01Z(to_slv(arg))); return result; end if; end function to_X01Z; function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_UX01: null detected, returning NULL" severity warning; return NAFP; else result := UNRESOLVED_float (to_UX01(to_slv(arg))); return result; end if; end function to_UX01; -- These allows the base math functions to use the default values -- of their parameters. Thus they do full IEEE floating point. function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return add (l, r); end function "+"; function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return subtract (l, r); end function "-"; function "" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return multiply (l, r); end function ""; function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return divide (l, r); end function "/"; function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return remainder (l, r); end function "rem"; function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return modulo (l, r); end function "mod"; -- overloaded versions function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return add (l, r_float); end function "+"; function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return add (l_float, r); end function "+"; function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return add (l, r_float); end function "+"; function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return add (l_float, r); end function "+"; function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return subtract (l, r_float); end function "-"; function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return subtract (l_float, r); end function "-"; function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return subtract (l, r_float); end function "-"; function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return subtract (l_float, r); end function "-"; function "" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return multiply (l, r_float); end function ""; function "" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return multiply (l_float, r); end function ""; function "" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return multiply (l, r_float); end function ""; function "" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return multiply (l_float, r); end function ""; function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return divide (l, r_float); end function "/"; function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return divide (l_float, r); end function "/"; function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return divide (l, r_float); end function "/"; function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return divide (l_float, r); end function "/"; function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return remainder (l, r_float); end function "rem"; function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return remainder (l_float, r); end function "rem"; function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return remainder (l, r_float); end function "rem"; function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return remainder (l_float, r); end function "rem"; function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return modulo (l, r_float); end function "mod"; function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return modulo (l_float, r); end function "mod"; function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return modulo (l, r_float); end function "mod"; function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return modulo (l_float, r); end function "mod"; function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return eq (l, r_float); end function "="; function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ne (l, r_float); end function "/="; function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ge (l, r_float); end function ">="; function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return le (l, r_float); end function "<="; function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return gt (l, r_float); end function ">"; function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return lt (l, r_float); end function "<"; function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return eq (l_float, r); end function "="; function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ne (l_float, r); end function "/="; function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ge (l_float, r); end function ">="; function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return le (l_float, r); end function "<="; function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return gt (l_float, r); end function ">"; function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return lt (l_float, r); end function "<"; function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return eq (l, r_float); end function "="; function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ne (l, r_float); end function "/="; function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ge (l, r_float); end function ">="; function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return le (l, r_float); end function "<="; function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return gt (l, r_float); end function ">"; function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return lt (l, r_float); end function "<"; function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return eq (l_float, r); end function "="; function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ne (l_float, r); end function "/="; function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ge (l_float, r); end function ">="; function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return le (l_float, r); end function "<="; function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return gt (l_float, r); end function ">"; function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return lt (l_float, r); end function "<"; -- ?= overloads function "?=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?= r_float; end function "?="; function "?/=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?/= r_float; end function "?/="; function "?>" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?> r_float; end function "?>"; function "?>=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?>= r_float; end function "?>="; function "?<" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?< r_float; end function "?<"; function "?<=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?<= r_float; end function "?<="; -- real and float function "?=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?= r; end function "?="; function "?/=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?/= r; end function "?/="; function "?>" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?> r; end function "?>"; function "?>=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?>= r; end function "?>="; function "?<" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?< r; end function "?<"; function "?<=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?<= r; end function "?<="; -- ?= overloads function "?=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?= r_float; end function "?="; function "?/=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?/= r_float; end function "?/="; function "?>" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?> r_float; end function "?>"; function "?>=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?>= r_float; end function "?>="; function "?<" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?< r_float; end function "?<"; function "?<=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?<= r_float; end function "?<="; -- integer and float function "?=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?= r; end function "?="; function "?/=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?/= r; end function "?/="; function "?>" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?> r; end function "?>"; function "?>=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?>= r; end function "?>="; function "?<" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?< r; end function "?<"; function "?<=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?<= r; end function "?<="; -- minimum and maximum overloads function minimum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return minimum (l, r_float); end function minimum; function maximum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return maximum (l, r_float); end function maximum; function minimum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return minimum (l_float, r); end function minimum; function maximum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return maximum (l_float, r); end function maximum; function minimum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return minimum (l, r_float); end function minimum; function maximum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return maximum (l, r_float); end function maximum; function minimum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return minimum (l_float, r); end function minimum; function maximum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return maximum (l_float, r); end function maximum; ---------------------------------------------------------------------------- -- logical functions ---------------------------------------------------------------------------- function "not" (L : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin RESULT := not to_sulv(L); return to_float (RESULT, L'high, -L'low); end function "not"; function "and" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) and to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """and"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "and"; function "or" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) or to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """or"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "or"; function "nand" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) nand to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """nand"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "nand"; function "nor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) nor to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """nor"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "nor"; function "xor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) xor to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """xor"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "xor"; function "xnor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) xnor to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """xnor"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "xnor"; -- Vector and std_ulogic functions, same as functions in numeric_std function "and" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L and to_sulv(R)); return result; end function "and"; function "and" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) and R); return result; end function "and"; function "or" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L or to_sulv(R)); return result; end function "or"; function "or" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) or R); return result; end function "or"; function "nand" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L nand to_sulv(R)); return result; end function "nand"; function "nand" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) nand R); return result; end function "nand"; function "nor" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L nor to_sulv(R)); return result; end function "nor"; function "nor" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) nor R); return result; end function "nor"; function "xor" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L xor to_sulv(R)); return result; end function "xor"; function "xor" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) xor R); return result; end function "xor"; function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L xnor to_sulv(R)); return result; end function "xnor"; function "xnor" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) xnor R); return result; end function "xnor"; -- Reduction operators, same as numeric_std functions function "and" (l : UNRESOLVED_float) return STD_ULOGIC is begin return and to_sulv(l); end function "and"; function "nand" (l : UNRESOLVED_float) return STD_ULOGIC is begin return nand to_sulv(l); end function "nand"; function "or" (l : UNRESOLVED_float) return STD_ULOGIC is begin return or to_sulv(l); end function "or"; function "nor" (l : UNRESOLVED_float) return STD_ULOGIC is begin return nor to_sulv(l); end function "nor"; function "xor" (l : UNRESOLVED_float) return STD_ULOGIC is begin return xor to_sulv(l); end function "xor"; function "xnor" (l : UNRESOLVED_float) return STD_ULOGIC is begin return xnor to_sulv(l); end function "xnor"; ----------------------------------------------------------------------------- -- Recommended Functions from the IEEE 754 Appendix ----------------------------------------------------------------------------- -- returns x with the sign of y. function Copysign ( x, y : UNRESOLVED_float) -- floating point input return UNRESOLVED_float is begin return y(y'high) & x (x'high-1 downto x'low); end function Copysign; -- Returns y * 2n for integral values of N without computing 2n function Scalb ( y : UNRESOLVED_float; -- floating point input N : INTEGER; -- exponent to add constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(y'low, y'low); -- length of FP output fraction constant exponent_width : NATURAL := y'high; -- length of FP output exponent variable arg, result : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp variable exp : SIGNED (exponent_width downto 0); variable ufract : UNSIGNED (fraction_width downto 0); constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fptype : valid_fpstate; begin -- This can be done by simply adding N to the exponent. arg := to_01 (y, 'X'); fptype := classfp(arg, check_error); classcase : case fptype is when isx => result := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 result := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when others => break_number ( arg => arg, fptyp => fptype, denormalize => denormalize, fract => ufract, expon => expon); exp := resize (expon, exp'length) + N; result := normalize ( fract => ufract, expon => exp, sign => to_x01 (arg (arg'high)), fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => 0); end case classcase; return result; end function Scalb; -- Returns y * 2n for integral values of N without computing 2n function Scalb ( y : UNRESOLVED_float; -- floating point input N : UNRESOLVED_SIGNED; -- exponent to add constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable n_int : INTEGER; begin n_int := to_integer(N); return Scalb (y => y, N => n_int, round_style => round_style, check_error => check_error, denormalize => denormalize); end function Scalb; -- returns the unbiased exponent of x function Logb ( x : UNRESOLVED_float) -- floating point input return INTEGER is constant fraction_width : NATURAL := -mine (x'low, x'low); -- length of FP output fraction constant exponent_width : NATURAL := x'high; -- length of FP output exponent variable result : INTEGER; -- result variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument variable expon : SIGNED (exponent_width - 1 downto 0); variable fract : UNSIGNED (fraction_width downto 0); constant expon_base : INTEGER := 2*(exponent_width-1) -1; -- exponent -- offset +1 variable fptype : valid_fpstate; begin -- Just return the exponent. arg := to_01 (x, 'X'); fptype := classfp(arg); classcase : case fptype is when isx \| nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 result := 0; when pos_denormal \| neg_denormal => fract (fraction_width) := '0'; fract (fraction_width-1 downto 0) := UNSIGNED (to_slv(arg(-1 downto -fraction_width))); result := find_leftmost (fract, '1') -- Find the first "1" - fraction_width; -- subtract the length we want result := -expon_base + 1 + result; when others => expon := SIGNED(arg (exponent_width - 1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); expon := expon + 1; result := to_integer (expon); end case classcase; return result; end function Logb; -- returns the unbiased exponent of x function Logb ( x : UNRESOLVED_float) -- floating point input return UNRESOLVED_SIGNED is constant exponent_width : NATURAL := x'high; -- length of FP output exponent variable result : SIGNED (exponent_width - 1 downto 0); -- result begin -- Just return the exponent. result := to_signed (Logb (x), exponent_width); return result; end function Logb; -- returns the next representable neighbor of x in the direction toward y function Nextafter ( x, y : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(x'low, x'low); -- length of FP output fraction constant exponent_width : NATURAL := x'high; -- length of FP output exponent function "=" ( l, r : UNRESOLVED_float) -- inputs return BOOLEAN is begin -- function "=" return eq (l => l, r => r, check_error => false); end function "="; function ">" ( l, r : UNRESOLVED_float) -- inputs return BOOLEAN is begin -- function ">" return gt (l => l, r => r, check_error => false); end function ">"; variable fract : UNSIGNED (fraction_width-1 downto 0); variable expon : UNSIGNED (exponent_width-1 downto 0); variable sign : STD_ULOGIC; variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable validfpx, validfpy : valid_fpstate; -- Valid FP state begin -- fp_Nextafter -- If Y > X, add one to the fraction, otherwise subtract. validfpx := classfp (x, check_error); validfpy := classfp (y, check_error); if validfpx = isx or validfpy = isx then result := (others => 'X'); return result; elsif (validfpx = nan or validfpy = nan) then return nanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (validfpx = quiet_nan or validfpy = quiet_nan) then return qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif x = y then -- Return X return x; else fract := UNSIGNED (to_slv (x (-1 downto -fraction_width))); -- Fraction expon := UNSIGNED (x (exponent_width - 1 downto 0)); -- exponent sign := x(exponent_width); -- sign bit if (y > x) then -- Increase the number given if validfpx = neg_inf then -- return most negative number expon := (others => '1'); expon (0) := '0'; fract := (others => '1'); elsif validfpx = pos_zero or validfpx = neg_zero then -- return smallest denormal number sign := '0'; expon := (others => '0'); fract := (others => '0'); fract(0) := '1'; elsif validfpx = pos_normal then if and (fract) = '1' then -- fraction is all "1". if and (expon (exponent_width-1 downto 1)) = '1' and expon (0) = '0' then -- Exponent is one away from infinity. assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "FP_NEXTAFTER: NextAfter overflow" severity warning; return pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else expon := expon + 1; fract := (others => '0'); end if; else fract := fract + 1; end if; elsif validfpx = pos_denormal then if and (fract) = '1' then -- fraction is all "1". -- return smallest possible normal number expon := (others => '0'); expon(0) := '1'; fract := (others => '0'); else fract := fract + 1; end if; elsif validfpx = neg_normal then if or (fract) = '0' then -- fraction is all "0". if or (expon (exponent_width-1 downto 1)) = '0' and expon (0) = '1' then -- Smallest exponent -- return the largest negative denormal number expon := (others => '0'); fract := (others => '1'); else expon := expon - 1; fract := (others => '1'); end if; else fract := fract - 1; end if; elsif validfpx = neg_denormal then if or (fract(fract'high downto 1)) = '0' and fract (0) = '1' then -- Smallest possible fraction return zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else fract := fract - 1; end if; end if; else -- Decrease the number if validfpx = pos_inf then -- return most positive number expon := (others => '1'); expon (0) := '0'; fract := (others => '1'); elsif validfpx = pos_zero or classfp (x) = neg_zero then -- return smallest negative denormal number sign := '1'; expon := (others => '0'); fract := (others => '0'); fract(0) := '1'; elsif validfpx = neg_normal then if and (fract) = '1' then -- fraction is all "1". if and (expon (exponent_width-1 downto 1)) = '1' and expon (0) = '0' then -- Exponent is one away from infinity. assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "FP_NEXTAFTER: NextAfter overflow" severity warning; return neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else expon := expon + 1; -- Fraction overflow fract := (others => '0'); end if; else fract := fract + 1; end if; elsif validfpx = neg_denormal then if and (fract) = '1' then -- fraction is all "1". -- return smallest possible normal number expon := (others => '0'); expon(0) := '1'; fract := (others => '0'); else fract := fract + 1; end if; elsif validfpx = pos_normal then if or (fract) = '0' then -- fraction is all "0". if or (expon (exponent_width-1 downto 1)) = '0' and expon (0) = '1' then -- Smallest exponent -- return the largest positive denormal number expon := (others => '0'); fract := (others => '1'); else expon := expon - 1; fract := (others => '1'); end if; else fract := fract - 1; end if; elsif validfpx = pos_denormal then if or (fract(fract'high downto 1)) = '0' and fract (0) = '1' then -- Smallest possible fraction return zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else fract := fract - 1; end if; end if; end if; result (-1 downto -fraction_width) := UNRESOLVED_float(fract); result (exponent_width -1 downto 0) := UNRESOLVED_float(expon); result (exponent_width) := sign; return result; end if; end function Nextafter; -- Returns True if X is unordered with Y. function Unordered ( x, y : UNRESOLVED_float) -- floating point input return BOOLEAN is variable lfptype, rfptype : valid_fpstate; begin lfptype := classfp (x); rfptype := classfp (y); if (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan or lfptype = isx or rfptype = isx) then return true; else return false; end if; end function Unordered; function Finite ( x : UNRESOLVED_float) return BOOLEAN is variable fp_state : valid_fpstate; -- fp state begin fp_state := Classfp (x); if (fp_state = pos_inf) or (fp_state = neg_inf) then return true; else return false; end if; end function Finite; function Isnan ( x : UNRESOLVED_float) return BOOLEAN is variable fp_state : valid_fpstate; -- fp state begin fp_state := Classfp (x); if (fp_state = nan) or (fp_state = quiet_nan) then return true; else return false; end if; end function Isnan; -- Function to return constants. function zerofp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is constant result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin return result; end function zerofp; function nanfp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1" result (-1) := '1'; -- MSB of Fraction "1" -- Note: From W. Khan "IEEE Standard 754 for Binary Floating Point" -- The difference between a signaling NAN and a quiet NAN is that -- the MSB of the Fraction is a "1" in a Signaling NAN, and is a -- "0" in a quiet NAN. return result; end function nanfp; function qnanfp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1" result (-fraction_width) := '1'; -- LSB of Fraction "1" -- (Could have been any bit) return result; end function qnanfp; function pos_inffp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1" return result; end function pos_inffp; function neg_inffp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width downto 0) := (others => '1'); -- top bits all "1" return result; end function neg_inffp; function neg_zerofp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width) := '1'; return result; end function neg_zerofp; -- size_res versions function zerofp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return zerofp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function zerofp; function nanfp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return nanfp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function nanfp; function qnanfp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return qnanfp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function qnanfp; function pos_inffp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return pos_inffp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function pos_inffp; function neg_inffp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return neg_inffp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function neg_inffp; function neg_zerofp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return neg_zerofp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function neg_zerofp; -- Textio functions -- purpose: writes float into a line (NOTE changed basetype) type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error); type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER; type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC; type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus; constant NBSP : CHARACTER := CHARACTER'val(160); -- space character constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-"; constant char_to_MVL9 : MVL9_indexed_by_char := ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U'); constant char_to_MVL9plus : MVL9plus_indexed_by_char := ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error); -- purpose: Skips white space procedure skip_whitespace ( L : inout LINE) is variable readOk : BOOLEAN; variable c : CHARACTER; begin while L /= null and L.all'length /= 0 loop c := l (l'left); if (c = ' ' or c = NBSP or c = HT) then read (l, c, readOk); else exit; end if; end loop; end procedure skip_whitespace; -- purpose: Checks the punctuation in a line procedure check_punctuation ( arg : in STRING; colon : out BOOLEAN; -- There was a colon in the line dot : out BOOLEAN; -- There was a dot in the line good : out BOOLEAN; -- True if enough characters found chars : in INTEGER) is -- Examples. Legal inputs are "0000000", "0000.000", "0:000:000" alias xarg : STRING (1 to arg'length) is arg; -- make it downto range variable icolon, idot : BOOLEAN; -- internal variable j : INTEGER := 0; -- charters read begin good := false; icolon := false; idot := false; for i in 1 to arg'length loop if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j = chars then exit; elsif xarg(i) = ':' then icolon := true; elsif xarg(i) = '.' then idot := true; elsif xarg (i) /= '_' then j := j + 1; end if; end loop; if j = chars then good := true; -- There are enough charactes to read end if; colon := icolon; if idot and icolon then dot := false; else dot := idot; end if; end procedure check_punctuation; -- purpose: Searches a line for a ":" and replaces it with a ".". procedure fix_colon ( arg : inout STRING; chars : in integer) is alias xarg : STRING (1 to arg'length) is arg; -- make it downto range variable j : INTEGER := 0; -- charters read begin for i in 1 to arg'length loop if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j > chars then exit; elsif xarg(i) = ':' then xarg (i) := '.'; elsif xarg (i) /= '_' then j := j + 1; end if; end loop; end procedure fix_colon; procedure WRITE ( L : inout LINE; -- input line VALUE : in UNRESOLVED_float; -- floating point input JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable s : STRING(1 to value'high - value'low +3); variable sindx : INTEGER; begin -- function write s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high))); s(2) := ':'; sindx := 3; for i in VALUE'high-1 downto 0 loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; s(sindx) := ':'; sindx := sindx + 1; for i in -1 downto VALUE'low loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; WRITE (L, s, JUSTIFIED, FIELD); end procedure WRITE; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float) is -- Possible data: 0:0000:0000000 -- 000000000000 variable c : CHARACTER; variable mv : UNRESOLVED_float (VALUE'range); variable readOk : BOOLEAN; variable lastu : BOOLEAN := false; -- last character was an "_" variable i : INTEGER; -- index variable begin -- READ VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); READ (l, c, readOk); if VALUE'length > 0 then i := value'high; readloop : loop if readOk = false then -- Bail out if there was a bad read report float_generic_pkg'instance_name & "READ(float): " & "Error end of file encountered." severity error; return; elsif c = ' ' or c = CR or c = HT then -- reading done. if (i /= value'low) then report float_generic_pkg'instance_name & "READ(float): " & "Warning: Value truncated." severity warning; return; end if; elsif c = '_' then if i = value'high then -- Begins with an "_" report float_generic_pkg'instance_name & "READ(float): " & "String begins with an ""_""" severity error; return; elsif lastu then -- "__" detected report float_generic_pkg'instance_name & "READ(float): " & "Two underscores detected in input string ""__""" severity error; return; else lastu := true; end if; elsif c = ':' or c = '.' then -- separator, ignore if not (i = -1 or i = value'high-1) then report float_generic_pkg'instance_name & "READ(float): " & "Warning: Separator point does not match number format: '" & c & "' encountered at location " & INTEGER'image(i) & "." severity warning; end if; lastu := false; elsif (char_to_MVL9plus(c) = error) then report float_generic_pkg'instance_name & "READ(float): " & "Error: Character '" & c & "' read, expected STD_ULOGIC literal." severity error; return; else mv (i) := char_to_MVL9(c); i := i - 1; if i < value'low then VALUE := mv; return; end if; lastu := false; end if; READ (l, c, readOk); end loop readloop; end if; end procedure READ; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is -- Possible data: 0:0000:0000000 -- 000000000000 variable c : CHARACTER; variable mv : UNRESOLVED_float (VALUE'range); variable lastu : BOOLEAN := false; -- last character was an "_" variable i : INTEGER; -- index variable variable readOk : BOOLEAN; begin -- READ VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); READ (l, c, readOk); if VALUE'length > 0 then i := value'high; good := false; readloop : loop if readOk = false then -- Bail out if there was a bad read return; elsif c = ' ' or c = CR or c = HT then -- reading done return; elsif c = '_' then if i = 0 then -- Begins with an "_" return; elsif lastu then -- "__" detected return; else lastu := true; end if; elsif c = ':' or c = '.' then -- separator, ignore -- good := (i = -1 or i = value'high-1); lastu := false; elsif (char_to_MVL9plus(c) = error) then return; else mv (i) := char_to_MVL9(c); i := i - 1; if i < value'low then good := true; VALUE := mv; return; end if; lastu := false; end if; READ (l, c, readOk); end loop readloop; else good := true; -- read into a null array end if; end procedure READ; procedure OWRITE ( L : inout LINE; -- access type (pointer) VALUE : in UNRESOLVED_float; -- value to write JUSTIFIED : in SIDE := right; -- which side to justify text FIELD : in WIDTH := 0) is -- width of field begin WRITE (L => L, VALUE => to_ostring(VALUE), JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure OWRITE; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is constant ne : INTEGER := ((value'length+2)/3) 3; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/3); if not ok then report float_generic_pkg'instance_name & "OREAD: " & "short string encounted: " & L.all & " needs to have " & integer'image (ne/3) & " valid octal characters." severity error; return; elsif dot then OREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "OREAD: " & "error encounted reading STRING " & L.all severity error; return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then OREAD (L, nybble, ok); -- read the sign bit if not ok then report float_generic_pkg'instance_name & "OREAD: " & "End of string encountered" severity error; return; elsif nybble (2 downto 1) /= "00" then report float_generic_pkg'instance_name & "OREAD: " & "Illegal sign bit STRING encounted " severity error; return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/3); -- replaces the colon with a ".". OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "OREAD: " & "error encounted reading STRING " & L.all severity error; return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else OREAD (L, slv, ok); if not ok then report float_generic_pkg'instance_name & "OREAD: " & "Error encounted during read" severity error; return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then report float_generic_pkg'instance_name & "OREAD: " & "Vector truncated." severity error; return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; end if; end procedure OREAD; procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" GOOD := false; Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/3); if not ok then return; elsif dot then OREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then OREAD (L, nybble, ok); -- read the sign bit if not ok then return; elsif nybble (2 downto 1) /= "00" then return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/3); -- replaces the colon with a ".". OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else OREAD (L, slv, ok); if not ok then return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; GOOD := true; end if; end procedure OREAD; procedure HWRITE ( L : inout LINE; -- access type (pointer) VALUE : in UNRESOLVED_float; -- value to write JUSTIFIED : in SIDE := right; -- which side to justify text FIELD : in WIDTH := 0) is -- width of field begin WRITE (L => L, VALUE => to_hstring(VALUE), JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure HWRITE; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/4); if not ok then report float_generic_pkg'instance_name & "HREAD: " & "short string encounted: " & L.all & " needs to have " & integer'image (ne/4) & " valid hex characters." severity error; return; elsif dot then HREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "HREAD: " & "error encounted reading STRING " & L.all severity error; return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then HREAD (L, nybble, ok); -- read the sign bit if not ok then report float_generic_pkg'instance_name & "HREAD: " & "End of string encountered" severity error; return; elsif nybble (3 downto 1) /= "000" then report float_generic_pkg'instance_name & "HREAD: " & "Illegal sign bit STRING encounted " severity error; return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/4); -- replaces the colon with a ".". HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "HREAD: " & "error encounted reading STRING " & L.all severity error; return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else HREAD (L, slv, ok); if not ok then report float_generic_pkg'instance_name & "HREAD: " & "Error encounted during read" severity error; return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then report float_generic_pkg'instance_name & "HREAD: " & "Vector truncated." severity error; return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; end if; end procedure HREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" GOOD := false; Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/4); if not ok then return; elsif dot then HREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then HREAD (L, nybble, ok); -- read the sign bit if not ok then return; elsif nybble (3 downto 1) /= "000" then return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/4); -- replaces the colon with a ".". HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else HREAD (L, slv, ok); if not ok then return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; GOOD := true; end if; end procedure HREAD; function to_string (value : UNRESOLVED_float) return STRING is variable s : STRING(1 to value'high - value'low +3); variable sindx : INTEGER; begin -- function write s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high))); s(2) := ':'; sindx := 3; for i in VALUE'high-1 downto 0 loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; s(sindx) := ':'; sindx := sindx + 1; for i in -1 downto VALUE'low loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; return s; end function to_string; function to_hstring (value : UNRESOLVED_float) return STRING is variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0); begin floop : for i in slv'range loop slv(i) := to_X01Z (value(i + value'low)); end loop floop; return to_hstring (slv); end function to_hstring; function to_ostring (value : UNRESOLVED_float) return STRING is variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0); begin floop : for i in slv'range loop slv(i) := to_X01Z (value(i + value'low)); end loop floop; return to_ostring (slv); end function to_ostring; function from_string ( bstring : STRING; -- binary string constant exponent_width : NATURAL := float_exponent_width; constant fraction_width : NATURAL := float_fraction_width) return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable L : LINE; variable good : BOOLEAN; begin L := new STRING'(bstring); READ (L, result, good); deallocate (L); assert (good) report FLOAT_GENERIC_PKG'instance_name & "from_string: Bad string " & bstring severity error; return result; end function from_string; function from_ostring ( ostring : STRING; -- Octal string constant exponent_width : NATURAL := float_exponent_width; constant fraction_width : NATURAL := float_fraction_width) return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable L : LINE; variable good : BOOLEAN; begin L := new STRING'(ostring); OREAD (L, result, good); deallocate (L); assert (good) report FLOAT_GENERIC_PKG'instance_name & "from_ostring: Bad string " & ostring severity error; return result; end function from_ostring; function from_hstring ( hstring : STRING; -- hex string constant exponent_width : NATURAL := float_exponent_width; constant fraction_width : NATURAL := float_fraction_width) return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable L : LINE; variable good : BOOLEAN; begin L := new STRING'(hstring); HREAD (L, result, good); deallocate (L); assert (good) report FLOAT_GENERIC_PKG'instance_name & "from_hstring: Bad string " & hstring severity error; return result; end function from_hstring; function from_string ( bstring : STRING; -- binary string size_res : UNRESOLVED_float) -- used for sizing only return UNRESOLVED_float is begin return from_string (bstring => bstring, exponent_width => size_res'high, fraction_width => -size_res'low); end function from_string; function from_ostring ( ostring : STRING; -- Octal string size_res : UNRESOLVED_float) -- used for sizing only return UNRESOLVED_float is begin return from_ostring (ostring => ostring, exponent_width => size_res'high, fraction_width => -size_res'low); end function from_ostring; function from_hstring ( hstring : STRING; -- hex string size_res : UNRESOLVED_float) -- used for sizing only return UNRESOLVED_float is begin return from_hstring (hstring => hstring, exponent_width => size_res'high, fraction_width => -size_res'low); end function from_hstring; end package body float_generic_pkg;
-- -------------------------------------------------------------------- -- -- Copyright © 2008 by IEEE. All rights reserved. -- -- This source file is an essential part of IEEE Std 1076-2008, -- IEEE Standard VHDL Language Reference Manual. This source file may not be -- copied, sold, or included with software that is sold without written -- permission from the IEEE Standards Department. This source file may be -- copied for individual use between licensed users. This source file is -- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR -- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE -- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify -- and hold IEEE harmless from any damages or liability arising out of the -- use thereof. -- -- Title : Floating-point package (Generic package body) -- : -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: Accellera VHDL-TC and IEEE P1076 Working Group -- : -- Purpose : This packages defines basic binary floating point -- : arithmetic functions -- : -- Note : This package may be modified to include additional data -- : required by tools, but it must in no way change the -- : external interfaces or simulation behavior of the -- : description. It is permissible to add comments and/or -- : attributes to the package declarations, but not to change -- : or delete any original lines of the package declaration. -- : The package body may be changed only in accordance with -- : the terms of Clause 16 of this standard. -- : -- -------------------------------------------------------------------- -- $Revision: 1220 $ -- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ -- -------------------------------------------------------------------- package body float_generic_pkg is -- Author David Bishop ([email protected]) ----------------------------------------------------------------------------- -- type declarations ----------------------------------------------------------------------------- -- This deferred constant will tell you if the package body is synthesizable -- or implemented as real numbers, set to "true" if synthesizable. constant fphdlsynth_or_real : BOOLEAN := true; -- deferred constant -- types of boundary conditions type boundary_type is (normal, infinity, zero, denormal); -- null range array constant constant NAFP : UNRESOLVED_float (0 downto 1) := (others => '0'); constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0'); -- Special version of "minimum" to do some boundary checking function mine (L, R : INTEGER) return INTEGER is begin -- function minimum if (L = INTEGER'low or R = INTEGER'low) then report float_generic_pkg'instance_name & " Unbounded number passed, was a literal used?" severity error; return 0; end if; return minimum (L, R); end function mine; -- Generates the base number for the exponent normalization offset. function gen_expon_base ( constant exponent_width : NATURAL) return SIGNED is variable result : SIGNED (exponent_width-1 downto 0); begin result := (others => '1'); result (exponent_width-1) := '0'; return result; end function gen_expon_base; -- Integer version of the "log2" command (contributed by Peter Ashenden) function log2 (A : NATURAL) return NATURAL is variable quotient : NATURAL; variable result : NATURAL := 0; begin quotient := A / 2; while quotient > 0 loop quotient := quotient / 2; result := result + 1; end loop; return result; end function log2; -- Function similar to the ILOGB function in MATH_REAL function log2 (A : REAL) return INTEGER is variable Y : REAL; variable N : INTEGER := 0; begin if (A = 1.0 or A = 0.0) then return 0; end if; Y := A; if(A > 1.0) then while Y >= 2.0 loop Y := Y / 2.0; N := N + 1; end loop; return N; end if; -- O < Y < 1 while Y < 1.0 loop Y := Y * 2.0; N := N - 1; end loop; return N; end function log2; -- purpose: Test the boundary conditions of a Real number procedure test_boundary ( arg : in REAL; -- Input, converted to real constant fraction_width : in NATURAL; -- length of FP output fraction constant exponent_width : in NATURAL; -- length of FP exponent constant denormalize : in BOOLEAN := true; -- Use IEEE extended FP variable btype : out boundary_type; variable log2i : out INTEGER ) is constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset constant exp_min : SIGNED (12 downto 0) := -(resize(expon_base, 13)) + 1; -- Minimum normal exponent constant exp_ext_min : SIGNED (12 downto 0) := exp_min - fraction_width; -- Minimum for denormal exponent variable log2arg : INTEGER; -- log2 of argument begin -- function test_boundary -- Check to see if the exponent is big enough -- Note that the argument is always an absolute value at this point. log2arg := log2(arg); if arg = 0.0 then btype := zero; elsif exponent_width > 11 then -- Exponent for Real is 11 (64 bit) btype := normal; else if log2arg < to_integer(exp_min) then if denormalize then if log2arg < to_integer(exp_ext_min) then btype := zero; else btype := denormal; end if; else if log2arg < to_integer(exp_min)-1 then btype := zero; else btype := normal; -- Can still represent this number end if; end if; elsif exponent_width < 11 then if log2arg > to_integer(expon_base)+1 then btype := infinity; else btype := normal; end if; else btype := normal; end if; end if; log2i := log2arg; end procedure test_boundary; -- purpose: Rounds depending on the state of the "round_style" -- Logic taken from -- "What Every Computer Scientist Should Know About Floating Point Arithmetic" -- by David Goldberg (1991) function check_round ( fract_in : STD_ULOGIC; -- input fraction sign : STD_ULOGIC; -- sign bit remainder : UNSIGNED; -- remainder to round from sticky : STD_ULOGIC := '0'; -- Sticky bit constant round_style : round_type) -- rounding type return BOOLEAN is variable result : BOOLEAN; variable or_reduced : STD_ULOGIC; begin -- function check_round result := false; if (remainder'length > 0) then -- if remainder in a null array or_reduced := or (remainder & sticky); rounding_case : case round_style is when round_nearest => -- Round Nearest, default mode if remainder(remainder'high) = '1' then -- round if (remainder'length > 1) then if ((or (remainder(remainder'high-1 downto remainder'low)) = '1' or sticky = '1') or fract_in = '1') then -- Make the bottom bit zero if possible if we are at 1/2 result := true; end if; else result := (fract_in = '1' or sticky = '1'); end if; end if; when round_inf => -- round up if positive, else truncate. if or_reduced = '1' and sign = '0' then result := true; end if; when round_neginf => -- round down if negative, else truncate. if or_reduced = '1' and sign = '1' then result := true; end if; when round_zero => -- round toward 0 Truncate null; end case rounding_case; end if; return result; end function check_round; -- purpose: Rounds depending on the state of the "round_style" -- unsigned version procedure fp_round ( fract_in : in UNSIGNED; -- input fraction expon_in : in SIGNED; -- input exponent fract_out : out UNSIGNED; -- output fraction expon_out : out SIGNED) is -- output exponent begin -- procedure fp_round if and (fract_in) = '1' then -- Fraction is all "1" expon_out := expon_in + 1; fract_out := to_unsigned(0, fract_out'high+1); else expon_out := expon_in; fract_out := fract_in + 1; end if; end procedure fp_round; -- This version of break_number doesn't call "classfp" procedure break_number ( -- internal version arg : in UNRESOLVED_float; fptyp : in valid_fpstate; denormalize : in BOOLEAN := true; fract : out UNSIGNED; expon : out SIGNED) is constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction constant exponent_width : NATURAL := arg'high; -- length of FP output exponent constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable exp : SIGNED (expon'range); begin fract (fraction_width-1 downto 0) := UNSIGNED (to_slv(arg(-1 downto -fraction_width))); breakcase : case fptyp is when pos_zero \| neg_zero => fract (fraction_width) := '0'; exp := -expon_base; when pos_denormal \| neg_denormal => if denormalize then exp := -expon_base; fract (fraction_width) := '0'; else exp := -expon_base - 1; fract (fraction_width) := '1'; end if; when pos_normal \| neg_normal \| pos_inf \| neg_inf => fract (fraction_width) := '1'; exp := SIGNED(arg(exponent_width-1 downto 0)); exp (exponent_width-1) := not exp(exponent_width-1); when others => assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "BREAK_NUMBER: " & "Meta state detected in fp_break_number process" severity warning; -- complete the case, if a NAN goes in, a NAN comes out. exp := (others => '1'); fract (fraction_width) := '1'; end case breakcase; expon := exp; end procedure break_number; -- purpose: floating point to UNSIGNED -- Used by to_integer, to_unsigned, and to_signed functions procedure float_to_unsigned ( arg : in UNRESOLVED_float; -- floating point input variable sign : out STD_ULOGIC; -- sign of output variable frac : out UNSIGNED; -- unsigned biased output constant denormalize : in BOOLEAN; -- turn on denormalization constant bias : in NATURAL; -- bias for fixed point constant round_style : in round_type) is -- rounding method constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent variable fract : UNSIGNED (frac'range); -- internal version of frac variable isign : STD_ULOGIC; -- internal version of sign variable exp : INTEGER; -- Exponent variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp -- Base to divide fraction by variable frac_shift : UNSIGNED (frac'high+3 downto 0); -- Fraction shifted variable shift : INTEGER; variable remainder : UNSIGNED (2 downto 0); variable round : STD_ULOGIC; -- round BIT begin isign := to_x01(arg(arg'high)); -- exponent /= '0', normal floating point expon := to_01(SIGNED(arg (exponent_width-1 downto 0)), 'X'); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (expon); -- Figure out the fraction fract := (others => '0'); -- fill with zero fract (fract'high) := '1'; -- Add the "1.0". shift := (fract'high-1) - exp; if fraction_width > fract'high then -- Can only use size-2 bits fract (fract'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto -fract'high))); else -- can use all bits fract (fract'high-1 downto fract'high-fraction_width) := UNSIGNED (to_slv (arg(-1 downto -fraction_width))); end if; frac_shift := fract & "000"; if shift < 0 then -- Overflow fract := (others => '1'); else frac_shift := shift_right (frac_shift, shift); fract := frac_shift (frac_shift'high downto 3); remainder := frac_shift (2 downto 0); -- round (round_zero will bypass this and truncate) case round_style is when round_nearest => round := remainder(2) and (fract (0) or (or (remainder (1 downto 0)))); when round_inf => round := remainder(2) and not isign; when round_neginf => round := remainder(2) and isign; when others => round := '0'; end case; if round = '1' then fract := fract + 1; end if; end if; frac := fract; sign := isign; end procedure float_to_unsigned; -- purpose: returns a part of a vector, this function is here because -- or (fractr (to_integer(shiftx) downto 0)); -- can't be synthesized in some synthesis tools. function smallfract ( arg : UNSIGNED; shift : NATURAL) return STD_ULOGIC is variable orx : STD_ULOGIC; begin orx := arg(shift); for i in arg'range loop if i < shift then orx := arg(i) or orx; end if; end loop; return orx; end function smallfract; --------------------------------------------------------------------------- -- Visible functions --------------------------------------------------------------------------- -- purpose: converts the negative index to a positive one -- negative indices are illegal in 1164 and 1076.3 function to_sulv ( arg : UNRESOLVED_float) -- fp vector return STD_ULOGIC_VECTOR is subtype result_subtype is STD_ULOGIC_VECTOR (arg'length-1 downto 0); variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0); begin -- function to_std_ulogic_vector if arg'length < 1 then return NSLV; end if; result := result_subtype (arg); return result; end function to_sulv; -- Converts an fp into an SULV function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR is begin return to_sulv (arg); end function to_slv; -- purpose: normalizes a floating point number -- This version assumes an "unsigned" input with function normalize ( fract : UNRESOLVED_UNSIGNED; -- fraction, unnormalized expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1 sign : STD_ULOGIC; -- sign BIT sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is variable sfract : UNSIGNED (fract'high downto 0); -- shifted fraction variable rfract : UNSIGNED (fraction_width-1 downto 0); -- fraction variable exp : SIGNED (exponent_width+1 downto 0); -- exponent variable rexp : SIGNED (exponent_width+1 downto 0); -- result exponent variable rexpon : UNSIGNED (exponent_width-1 downto 0); -- exponent variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result variable shiftr : INTEGER; -- shift amount variable stickyx : STD_ULOGIC; -- version of sticky constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable round, zerores, infres : BOOLEAN; begin -- function normalize zerores := false; infres := false; round := false; shiftr := find_leftmost (to_01(fract), '1') -- Find the first "1" - fraction_width - nguard; -- subtract the length we want exp := resize (expon, exp'length) + shiftr; if (or (fract) = '0') then -- Zero zerores := true; elsif ((exp <= -resize(expon_base, exp'length)-1) and denormalize) or ((exp < -resize(expon_base, exp'length)-1) and not denormalize) then if (exp >= -resize(expon_base, exp'length)-fraction_width-1) and denormalize then exp := -resize(expon_base, exp'length)-1; shiftr := -to_integer (expon + expon_base); -- new shift else -- return zero zerores := true; end if; elsif (exp > expon_base-1) then -- infinity infres := true; end if; if zerores then result := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); elsif infres then result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else sfract := fract srl shiftr; -- shift if shiftr > 0 then -- stickyx := sticky or (or (fract (shiftr-1 downto 0))); stickyx := sticky or smallfract (fract, shiftr-1); else stickyx := sticky; end if; if nguard > 0 then round := check_round ( fract_in => sfract (nguard), sign => sign, remainder => sfract(nguard-1 downto 0), sticky => stickyx, round_style => round_style); end if; if round then fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard), expon_in => exp(rexp'range), fract_out => rfract, expon_out => rexp); else rfract := sfract (fraction_width-1+nguard downto nguard); rexp := exp(rexp'range); end if; -- result rexpon := UNSIGNED (rexp(exponent_width-1 downto 0)); rexpon (exponent_width-1) := not rexpon(exponent_width-1); result (rexpon'range) := UNRESOLVED_float(rexpon); result (-1 downto -fraction_width) := UNRESOLVED_float(rfract); end if; result (exponent_width) := sign; -- sign BIT return result; end function normalize; -- purpose: normalizes a floating point number -- This version assumes a "ufixed" input function normalize ( fract : UNRESOLVED_ufixed; -- unsigned fixed point expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1 sign : STD_ULOGIC; -- sign bit sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arguns : UNSIGNED (fract'high + fraction_width + nguard downto 0) := (others => '0'); begin -- function normalize arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) := UNSIGNED (to_slv (fract)); result := normalize (fract => arguns, expon => expon, sign => sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => nguard); return result; end function normalize; -- purpose: normalizes a floating point number -- This version assumes a "ufixed" input with a "size_res" input function normalize ( fract : UNRESOLVED_ufixed; -- unsigned fixed point expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1 sign : STD_ULOGIC; -- sign bit sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) size_res : UNRESOLVED_float; -- used for sizing only constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is constant fraction_width : NATURAL := -size_res'low; constant exponent_width : NATURAL := size_res'high; variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arguns : UNSIGNED (fract'high + fraction_width + nguard downto 0) := (others => '0'); begin -- function normalize arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) := UNSIGNED (to_slv (fract)); result := normalize (fract => arguns, expon => expon, sign => sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => nguard); return result; end function normalize; -- Regular "normalize" function with a "size_res" input. function normalize ( fract : UNRESOLVED_UNSIGNED; -- unsigned expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized sign : STD_ULOGIC; -- sign bit sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) size_res : UNRESOLVED_float; -- used for sizing only constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is begin return normalize (fract => fract, expon => expon, sign => sign, sticky => sticky, fraction_width => -size_res'low, exponent_width => size_res'high, round_style => round_style, denormalize => denormalize, nguard => nguard); end function normalize; -- Returns the class which X falls into function Classfp ( x : UNRESOLVED_float; -- floating point input check_error : BOOLEAN := float_check_error) -- check for errors return valid_fpstate is constant fraction_width : INTEGER := -mine(x'low, x'low); -- length of FP output fraction constant exponent_width : INTEGER := x'high; -- length of FP output exponent variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- classfp if (arg'length < 1 or fraction_width < 3 or exponent_width < 3 or x'left < x'right) then report FLOAT_GENERIC_PKG'instance_name & "CLASSFP: " & "Floating point number detected with a bad range" severity error; return isx; end if; -- Check for "X". arg := to_01 (x, 'X'); if (arg(0) = 'X') then return isx; -- If there is an X in the number -- Special cases, check for illegal number elsif check_error and (and (STD_ULOGIC_VECTOR (arg (exponent_width-1 downto 0))) = '1') then -- Exponent is all "1". if or (to_slv (arg (-1 downto -fraction_width))) /= '0' then -- Fraction must be all "0" or this is not a number. if (arg(-1) = '1') then -- From "W. Khan - IEEE standard return nan; -- 754 binary FP Signaling nan (Not a number) else return quiet_nan; end if; -- Check for infinity elsif arg(exponent_width) = '0' then return pos_inf; -- Positive infinity else return neg_inf; -- Negative infinity end if; -- check for "0" elsif or (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0))) = '0' then -- Exponent is all "0" if or (to_slv (arg (-1 downto -fraction_width))) = '0' then -- Fraction is all "0" if arg(exponent_width) = '0' then return pos_zero; -- Zero else return neg_zero; end if; else if arg(exponent_width) = '0' then return pos_denormal; -- Denormal number (ieee extended fp) else return neg_denormal; end if; end if; else if arg(exponent_width) = '0' then return pos_normal; -- Normal FP number else return neg_normal; end if; end if; end function Classfp; procedure break_number ( arg : in UNRESOLVED_float; denormalize : in BOOLEAN := float_denormalize; check_error : in BOOLEAN := float_check_error; fract : out UNRESOLVED_UNSIGNED; expon : out UNRESOLVED_SIGNED; sign : out STD_ULOGIC) is constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction variable fptyp : valid_fpstate; begin fptyp := Classfp (arg, check_error); sign := to_x01(arg(arg'high)); break_number ( arg => arg, fptyp => fptyp, denormalize => denormalize, fract => fract, expon => expon); end procedure break_number; procedure break_number ( arg : in UNRESOLVED_float; denormalize : in BOOLEAN := float_denormalize; check_error : in BOOLEAN := float_check_error; fract : out UNRESOLVED_ufixed; -- 1 downto -fraction_width expon : out UNRESOLVED_SIGNED; -- exponent_width-1 downto 0 sign : out STD_ULOGIC) is constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction variable fptyp : valid_fpstate; variable ufract : UNSIGNED (fraction_width downto 0); -- unsigned fraction begin fptyp := Classfp (arg, check_error); sign := to_x01(arg(arg'high)); break_number ( arg => arg, fptyp => fptyp, denormalize => denormalize, fract => ufract, expon => expon); fract (0 downto -fraction_width) := ufixed (ufract); end procedure break_number; -- Arithmetic functions function "abs" ( arg : UNRESOLVED_float) -- floating point input return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); -- result begin if (arg'length > 0) then result := to_01 (arg, 'X'); result (arg'high) := '0'; -- set the sign bit to positive return result; else return NAFP; end if; end function "abs"; -- IEEE 754 "negative" function function "-" ( arg : UNRESOLVED_float) -- floating point input return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); -- result begin if (arg'length > 0) then result := to_01 (arg, 'X'); result (arg'high) := not result (arg'high); -- invert sign bit return result; else return NAFP; end if; end function "-"; -- Addition, adds two floating point numbers function add ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant addguard : NATURAL := guard; -- add one guard bit variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable fractl, fractr : UNSIGNED (fraction_width+1+addguard downto 0); -- fractions variable fractc, fracts : UNSIGNED (fractl'range); -- constant and shifted variables variable urfract, ulfract : UNSIGNED (fraction_width downto 0); variable ufract : UNSIGNED (fraction_width+1+addguard downto 0); variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width downto 0); -- result exponent variable shiftx : SIGNED (exponent_width downto 0); -- shift fractions variable sign : STD_ULOGIC; -- sign of the output variable leftright : BOOLEAN; -- left or right used variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); variable sticky : STD_ULOGIC; -- Holds precision for rounding begin -- addition if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan) -- Return quiet NAN, IEEE754-1985-7.1,1 or (lfptype = pos_inf and rfptype = neg_inf) or (lfptype = neg_inf and rfptype = pos_inf) then -- Return quiet NAN, IEEE754-1985-7.1,2 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = pos_inf or rfptype = pos_inf) then -- x + inf = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = neg_inf or rfptype = neg_inf) then -- x - inf = -inf fpresult := neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = neg_zero and rfptype = neg_zero) then -- -0 + -0 = -0 fpresult := neg_zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); fractl := (others => '0'); fractl (fraction_width+addguard downto addguard) := ulfract; break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); fractr := (others => '0'); fractr (fraction_width+addguard downto addguard) := urfract; shiftx := (exponl(exponent_width-1) & exponl) - exponr; if shiftx < -fractl'high then rexpon := exponr(exponent_width-1) & exponr; fractc := fractr; fracts := (others => '0'); -- add zero leftright := false; sticky := or (fractl); elsif shiftx < 0 then shiftx := - shiftx; fracts := shift_right (fractl, to_integer(shiftx)); fractc := fractr; rexpon := exponr(exponent_width-1) & exponr; leftright := false; -- sticky := or (fractl (to_integer(shiftx) downto 0)); sticky := smallfract (fractl, to_integer(shiftx)); elsif shiftx = 0 then rexpon := exponl(exponent_width-1) & exponl; sticky := '0'; if fractr > fractl then fractc := fractr; fracts := fractl; leftright := false; else fractc := fractl; fracts := fractr; leftright := true; end if; elsif shiftx > fractr'high then rexpon := exponl(exponent_width-1) & exponl; fracts := (others => '0'); -- add zero fractc := fractl; leftright := true; sticky := or (fractr); elsif shiftx > 0 then fracts := shift_right (fractr, to_integer(shiftx)); fractc := fractl; rexpon := exponl(exponent_width-1) & exponl; leftright := true; -- sticky := or (fractr (to_integer(shiftx) downto 0)); sticky := smallfract (fractr, to_integer(shiftx)); end if; -- add fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB if l(l'high) = r(r'high) then ufract := fractc + fracts; sign := l(l'high); else -- signs are different ufract := fractc - fracts; -- always positive result if leftright then -- Figure out which sign to use sign := l(l'high); else sign := r(r'high); end if; end if; if or (ufract) = '0' then sign := '0'; -- IEEE 854, 6.3, paragraph 2. end if; -- normalize fpresult := normalize (fract => ufract, expon => rexpon, sign => sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => addguard); end if; return fpresult; end function add; -- Subtraction, Calls "add". function subtract ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable negr : UNRESOLVED_float (r'range); -- negative version of r begin negr := -r; -- r := -r return add (l => l, r => negr, round_style => round_style, guard => guard, check_error => check_error, denormalize => denormalize); end function subtract; -- Floating point multiply function multiply ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant multguard : NATURAL := guard; -- guard bits variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions variable rfract : UNSIGNED ((2(fraction_width))+1 downto 0); -- result fraction variable sfract : UNSIGNED (fraction_width+1+multguard downto 0); -- result fraction variable shifty : INTEGER; -- denormal shift variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent variable fp_sign : STD_ULOGIC; -- sign of result variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); variable sticky : STD_ULOGIC; -- Holds precision for rounding begin -- multiply if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif ((lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan)) then -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (((lfptype = pos_inf or lfptype = neg_inf) and (rfptype = pos_zero or rfptype = neg_zero)) or ((rfptype = pos_inf or rfptype = neg_inf) and (lfptype = pos_zero or lfptype = neg_zero))) then -- 0 inf -- Return quiet NAN, IEEE754-1985-7.1,3 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = pos_inf or rfptype = pos_inf or lfptype = neg_inf or rfptype = neg_inf) then -- x * inf = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); -- figure out the sign fp_sign := l(l'high) xor r(r'high); -- figure out the sign fpresult (exponent_width) := fp_sign; else fp_sign := l(l'high) xor r(r'high); -- figure out the sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => fractl, expon => exponl); break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => fractr, expon => exponr); if (rfptype = pos_denormal or rfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractr, '1'); fractr := shift_left (fractr, shifty); elsif (lfptype = pos_denormal or lfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractl, '1'); fractl := shift_left (fractl, shifty); else shifty := 0; -- Note that a denormal number * a denormal number is always zero. end if; -- multiply -- add the exponents rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1; rfract := fractl * fractr; -- Multiply the fraction sfract := rfract (rfract'high downto rfract'high - (fraction_width+1+multguard)); sticky := or (rfract (rfract'high-(fraction_width+1+multguard) downto 0)); -- normalize fpresult := normalize (fract => sfract, expon => rexpon, sign => fp_sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => multguard); end if; return fpresult; end function multiply; function short_divide ( lx, rx : UNSIGNED) return UNSIGNED is -- This is a special divider for the floating point routines. -- For a true unsigned divider, "stages" needs to = lx'high constant stages : INTEGER := lx'high - rx'high; -- number of stages variable partial : UNSIGNED (lx'range); variable q : UNSIGNED (stages downto 0); variable partial_argl : SIGNED (rx'high + 2 downto 0); variable partial_arg : SIGNED (rx'high + 2 downto 0); begin partial := lx; for i in stages downto 0 loop partial_argl := resize ("0" & SIGNED (partial(lx'high downto i)), partial_argl'length); partial_arg := partial_argl - SIGNED ("0" & rx); if (partial_arg (partial_arg'high) = '1') then -- negative q(i) := '0'; else q(i) := '1'; partial (lx'high+i-stages downto lx'high+i-stages-rx'high) := UNSIGNED (partial_arg(rx'range)); end if; end loop; -- to make the output look like that of the unsigned IEEE divide. return resize (q, lx'length); end function short_divide; -- 1/X function. Needed for algorithm development. function reciprocal ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : NATURAL := arg'high; -- length of FP output exponent constant divguard : NATURAL := guard; -- guard bits function onedivy ( arg : UNSIGNED) return UNSIGNED is variable q : UNSIGNED((2arg'high)+1 downto 0); variable one : UNSIGNED (q'range); begin one := (others => '0'); one(one'high) := '1'; q := short_divide (one, arg); -- Unsigned divide return resize (q, arg'length+1); end function onedivy; variable fptype : valid_fpstate; variable expon : SIGNED (exponent_width-1 downto 0); -- exponents variable denorm_offset : NATURAL range 0 to 2; variable fract : UNSIGNED (fraction_width downto 0); variable fractg : UNSIGNED (fraction_width+divguard downto 0); variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- reciprocal fptype := classfp(arg, check_error); classcase : case fptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => -- 1/inf, return 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); when neg_zero \| pos_zero => -- 1/0 report FLOAT_GENERIC_PKG'instance_name & "RECIPROCAL: Floating Point divide by zero" severity error; fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); when others => if (fptype = pos_denormal or fptype = neg_denormal) and ((arg (-1) or arg(-2)) /= '1') then -- 1/denormal = infinity, with the exception of 2-expon_base fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fpresult (exponent_width) := to_x01 (arg (exponent_width)); else break_number ( arg => arg, fptyp => fptype, denormalize => denormalize, fract => fract, expon => expon); fractg := (others => '0'); if (fptype = pos_denormal or fptype = neg_denormal) then -- The reciprocal of a denormal number is typically zero, -- except for two special cases which are trapped here. if (to_x01(arg (-1)) = '1') then fractg (fractg'high downto divguard+1) := fract (fract'high-1 downto 0); -- Shift to not denormal denorm_offset := 1; -- add 1 to exponent compensate else -- arg(-2) = '1' fractg (fractg'high downto divguard+2) := fract (fract'high-2 downto 0); -- Shift to not denormal denorm_offset := 2; -- add 2 to exponent compensate end if; else fractg (fractg'high downto divguard) := fract; denorm_offset := 0; end if; expon := - expon - 3 + denorm_offset; sfract := onedivy (fractg); -- normalize fpresult := normalize (fract => sfract, expon => expon, sign => arg(exponent_width), sticky => '1', fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => divguard); end if; end case classcase; return fpresult; end function reciprocal; -- floating point division function divide ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant divguard : NATURAL := guard; -- division guard bits variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable ulfract, urfract : UNSIGNED (fraction_width downto 0); variable fractl : UNSIGNED ((2(fraction_width+divguard)+1) downto 0); -- left variable fractr : UNSIGNED (fraction_width+divguard downto 0); -- right variable rfract : UNSIGNED (fractl'range); -- result fraction variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent variable fp_sign, sticky : STD_ULOGIC; -- sign of result variable shifty, shiftx : INTEGER; -- denormal number shift variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- divide if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; classcase : case rfptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => if lfptype = pos_inf or lfptype = neg_inf -- inf / inf or lfptype = quiet_nan or lfptype = nan then -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else -- x / inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when pos_zero \| neg_zero => if lfptype = pos_zero or lfptype = neg_zero -- 0 / 0 or lfptype = quiet_nan or lfptype = nan then -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else report float_generic_pkg'instance_name & "DIVIDE: Floating Point divide by zero" severity error; -- Infinity, define in 754-1985-7.2 fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when others => classcase2 : case lfptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => -- inf / x = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult(exponent_width) := fp_sign; when pos_zero \| neg_zero => -- 0 / X = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult(exponent_width) := fp_sign; when others => fp_sign := l(l'high) xor r(r'high); -- sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); -- right side break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); -- Compute the exponent rexpon := resize (exponl, rexpon'length) - exponr - 2; if (rfptype = pos_denormal or rfptype = neg_denormal) then -- Do the shifting here not after. That way we have a smaller -- shifter, and need a smaller divider, because the top -- bit in the divisor will always be a "1". shifty := fraction_width - find_leftmost(urfract, '1'); urfract := shift_left (urfract, shifty); rexpon := rexpon + shifty; end if; fractr := (others => '0'); fractr (fraction_width+divguard downto divguard) := urfract; if (lfptype = pos_denormal or lfptype = neg_denormal) then shiftx := fraction_width - find_leftmost(ulfract, '1'); ulfract := shift_left (ulfract, shiftx); rexpon := rexpon - shiftx; end if; fractl := (others => '0'); fractl (fractl'high downto fractl'high-fraction_width) := ulfract; -- divide rfract := short_divide (fractl, fractr); -- unsigned divide sfract := rfract (sfract'range); -- lower bits sticky := '1'; -- normalize fpresult := normalize (fract => sfract, expon => rexpon, sign => fp_sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => divguard); end case classcase2; end case classcase; return fpresult; end function divide; -- division by a power of 2 function dividebyp2 ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable ulfract, urfract : UNSIGNED (fraction_width downto 0); variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED(exponent_width downto 0); -- result exponent variable fp_sign : STD_ULOGIC; -- sign of result variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- divisionbyp2 if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; classcase : case rfptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => if lfptype = pos_inf or lfptype = neg_inf then -- inf / inf -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else -- x / inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when pos_zero \| neg_zero => if lfptype = pos_zero or lfptype = neg_zero then -- 0 / 0 -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else report FLOAT_GENERIC_PKG'instance_name & "DIVIDEBYP2: Floating Point divide by zero" severity error; -- Infinity, define in 754-1985-7.2 fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when others => classcase2 : case lfptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => -- inf / x = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (exponent_width) := fp_sign; -- sign when pos_zero \| neg_zero => -- 0 / X = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (exponent_width) := fp_sign; -- sign when others => fp_sign := l(l'high) xor r(r'high); -- sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); -- right side break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); assert (or (urfract (fraction_width-1 downto 0)) = '0') report FLOAT_GENERIC_PKG'instance_name & "DIVIDEBYP2: " & "Dividebyp2 called with a non power of two divisor" severity error; rexpon := (exponl(exponl'high)&exponl) - (exponr(exponr'high)&exponr) - 1; -- normalize fpresult := normalize (fract => ulfract, expon => rexpon, sign => fp_sign, sticky => '1', fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => 0); end case classcase2; end case classcase; return fpresult; end function dividebyp2; -- Multiply accumulate result = lr + c function mac ( l, r, c : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine (mine(l'low, r'low), c'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum (maximum(l'high, r'high), c'high); -- length of FP output exponent variable lfptype, rfptype, cfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions variable fractx : UNSIGNED (fraction_width+guard downto 0); variable fractc, fracts : UNSIGNED (fraction_width+1+guard downto 0); variable rfract : UNSIGNED ((2(fraction_width))+1 downto 0); -- result fraction variable sfract, ufract : UNSIGNED (fraction_width+1+guard downto 0); -- result fraction variable exponl, exponr, exponc : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon, rexpon2 : SIGNED (exponent_width+1 downto 0); -- result exponent variable shifty : INTEGER; -- denormal shift variable shiftx : SIGNED (rexpon'range); -- shift fractions variable fp_sign : STD_ULOGIC; -- sign of result variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); variable cresize : UNRESOLVED_float (exponent_width downto -fraction_width - guard); variable leftright : BOOLEAN; -- left or right used variable sticky : STD_ULOGIC; -- Holds precision for rounding begin -- multiply if (fraction_width = 0 or l'length < 7 or r'length < 7 or c'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); cfptype := classfp (c, check_error); end if; if (lfptype = isx or rfptype = isx or cfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan or cfptype = nan or cfptype = quiet_nan) then -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (((lfptype = pos_inf or lfptype = neg_inf) and (rfptype = pos_zero or rfptype = neg_zero)) or ((rfptype = pos_inf or rfptype = neg_inf) and (lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf -- Return quiet NAN, IEEE754-1985-7.1,3 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = pos_inf or rfptype = pos_inf or lfptype = neg_inf or rfptype = neg_inf -- x * inf = inf or cfptype = neg_inf or cfptype = pos_inf) then -- x + inf = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); -- figure out the sign fpresult (exponent_width) := l(l'high) xor r(r'high); else fp_sign := l(l'high) xor r(r'high); -- figure out the sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked cresize := resize (arg => to_x01(c), exponent_width => exponent_width, fraction_width => -cresize'low, denormalize_in => denormalize, denormalize => denormalize); cfptype := classfp (cresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => fractl, expon => exponl); break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => fractr, expon => exponr); break_number ( arg => cresize, fptyp => cfptype, denormalize => denormalize, fract => fractx, expon => exponc); if (rfptype = pos_denormal or rfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractr, '1'); fractr := shift_left (fractr, shifty); elsif (lfptype = pos_denormal or lfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractl, '1'); fractl := shift_left (fractl, shifty); else shifty := 0; -- Note that a denormal number * a denormal number is always zero. end if; -- multiply rfract := fractl * fractr; -- Multiply the fraction -- add the exponents rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1; shiftx := rexpon - exponc; if shiftx < -fractl'high then rexpon2 := resize (exponc, rexpon2'length); fractc := "0" & fractx; fracts := (others => '0'); sticky := or (rfract); elsif shiftx < 0 then shiftx := - shiftx; fracts := shift_right (rfract (rfract'high downto rfract'high - fracts'length+1), to_integer(shiftx)); fractc := "0" & fractx; rexpon2 := resize (exponc, rexpon2'length); leftright := false; sticky := or (rfract (to_integer(shiftx)+rfract'high - fracts'length downto 0)); elsif shiftx = 0 then rexpon2 := resize (exponc, rexpon2'length); sticky := or (rfract (rfract'high - fractc'length downto 0)); if rfract (rfract'high downto rfract'high - fractc'length+1) > fractx then fractc := "0" & fractx; fracts := rfract (rfract'high downto rfract'high - fracts'length+1); leftright := false; else fractc := rfract (rfract'high downto rfract'high - fractc'length+1); fracts := "0" & fractx; leftright := true; end if; elsif shiftx > fractx'high then rexpon2 := rexpon; fracts := (others => '0'); fractc := rfract (rfract'high downto rfract'high - fractc'length+1); leftright := true; sticky := or (fractx & rfract (rfract'high - fractc'length downto 0)); else -- fractx'high > shiftx > 0 rexpon2 := rexpon; fracts := "0" & shift_right (fractx, to_integer (shiftx)); fractc := rfract (rfract'high downto rfract'high - fractc'length+1); leftright := true; sticky := or (fractx (to_integer (shiftx) downto 0) & rfract (rfract'high - fractc'length downto 0)); end if; fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB if fp_sign = to_X01(c(c'high)) then ufract := fractc + fracts; fp_sign := fp_sign; else -- signs are different ufract := fractc - fracts; -- always positive result if leftright then -- Figure out which sign to use fp_sign := fp_sign; else fp_sign := c(c'high); end if; end if; -- normalize fpresult := normalize (fract => ufract, expon => rexpon2, sign => fp_sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => guard); end if; return fpresult; end function mac; -- "rem" function function remainder ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant divguard : NATURAL := guard; -- division guard bits variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable ulfract, urfract : UNSIGNED (fraction_width downto 0); variable fractr, fractl : UNSIGNED (fraction_width+divguard downto 0); -- right variable rfract : UNSIGNED (fractr'range); -- result fraction variable sfract : UNSIGNED (fraction_width+divguard downto 0); -- result fraction variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width downto 0); -- result exponent variable fp_sign : STD_ULOGIC; -- sign of result variable shifty : INTEGER; -- denormal number shift variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- remainder if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan) or (rfptype = nan or rfptype = quiet_nan) -- Return quiet NAN, IEEE754-1985-7.1,1 or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x -- Return quiet NAN, IEEE754-1985-7.1,5 or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0 -- Return quiet NAN, IEEE754-1985-7.1,5 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (abs(l) < abs(r)) then fpresult := l; else fp_sign := to_X01(l(l'high)); -- sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked fractl := (others => '0'); break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); fractl (fraction_width+divguard downto divguard) := ulfract; -- right side fractr := (others => '0'); break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); fractr (fraction_width+divguard downto divguard) := urfract; rexpon := (exponr(exponr'high)&exponr); shifty := to_integer(exponl - rexpon); if (shifty > 0) then fractr := shift_right (fractr, shifty); rexpon := rexpon + shifty; end if; if (fractr /= 0) then -- rem rfract := fractl rem fractr; -- unsigned rem sfract := rfract (sfract'range); -- lower bits -- normalize fpresult := normalize (fract => sfract, expon => rexpon, sign => fp_sign, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => divguard); else -- If we shift "fractr" so far that it becomes zero, return zero. fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); end if; end if; return fpresult; end function remainder; -- "mod" function function modulo ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := - mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable remres : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- remainder if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan) or (rfptype = nan or rfptype = quiet_nan) -- Return quiet NAN, IEEE754-1985-7.1,1 or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x -- Return quiet NAN, IEEE754-1985-7.1,5 or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0 -- Return quiet NAN, IEEE754-1985-7.1,5 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else remres := remainder (l => abs(l), r => abs(r), round_style => round_style, guard => guard, check_error => false, denormalize => denormalize); -- MOD is the same as REM, but you do something different with -- negative values if (is_negative (l)) then remres := - remres; end if; if (is_negative (l) = is_negative (r) or remres = 0) then fpresult := remres; else fpresult := add (l => remres, r => r, round_style => round_style, guard => guard, check_error => false, denormalize => denormalize); end if; end if; return fpresult; end function modulo; -- Square root of a floating point number. Done using Newton's Iteration. function sqrt ( arg : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; constant guard : NATURAL := float_guard_bits; constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_float is constant fraction_width : NATURAL := guard-arg'low; -- length of FP output fraction constant exponent_width : NATURAL := arg'high; -- length of FP output exponent variable sign : STD_ULOGIC; variable fpresult : float (arg'range); variable fptype : valid_fpstate; variable iexpon : SIGNED(exponent_width-1 downto 0); -- exponents variable expon : SIGNED(exponent_width downto 0); -- exponents variable ufact : ufixed (0 downto arg'low); variable fact : ufixed (2 downto -fraction_width); -- fraction variable resb : ufixed (fact'high+1 downto fact'low); begin -- square root fptype := Classfp (arg, check_error); classcase : case fptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan \| -- Return quiet NAN, IEEE754-1985-7.1,1 neg_normal \| neg_denormal \| neg_inf => -- sqrt (neg) -- Return quiet NAN, IEEE754-1985-7.1.6 fpresult := qnanfp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when pos_inf => -- Sqrt (inf), return infinity fpresult := pos_inffp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when pos_zero => -- return 0 fpresult := zerofp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when neg_zero => -- IEEE754-1985-6.3 return -0 fpresult := neg_zerofp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when others => break_number (arg => arg, denormalize => denormalize, check_error => false, fract => ufact, expon => iexpon, sign => sign); expon := resize (iexpon+1, expon'length); -- get exponent fact := resize (ufact, fact'high, fact'low); if (expon(0) = '1') then fact := fact sla 1; -- * 2.0 end if; expon := shift_right (expon, 1); -- exponent/2 -- Newton's iteration - root := (1 + arg) / 2 resb := (fact + 1) sra 1; for j in 0 to fraction_width/4 loop -- root := (root + (arg/root))/2 resb := resize (arg => (resb + (fact/resb)) sra 1, left_index => resb'high, right_index => resb'low, round_style => fixed_truncate, overflow_style => fixed_wrap); end loop; fpresult := normalize (fract => resb, expon => expon-1, sign => '0', exponent_width => arg'high, fraction_width => -arg'low, round_style => round_style, denormalize => denormalize, nguard => guard); end case classcase; return fpresult; end function sqrt; function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN is -- Technically -0 should return "false", but I'm leaving that case out. begin return (to_x01(arg(arg'high)) = '1'); end function Is_Negative; -- compare functions -- =, /=, >=, <=, <, > function eq ( -- equal = l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable lfptype, rfptype : valid_fpstate; variable is_equal, is_unordered : BOOLEAN; constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- equal if (fraction_width = 0 or l'length < 7 or r'length < 7) then return false; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = neg_zero or lfptype = pos_zero) and (rfptype = neg_zero or rfptype = pos_zero) then is_equal := true; else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); is_equal := (to_slv(lresize) = to_slv(rresize)); end if; if (check_error) then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return is_equal and not is_unordered; end function eq; function lt ( -- less than < l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable expl, expr : UNSIGNED (exponent_width-1 downto 0); variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0); variable is_less_than, is_unordered : BOOLEAN; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then is_less_than := false; else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits expl := UNSIGNED(lresize(exponent_width-1 downto 0)); expr := UNSIGNED(rresize(exponent_width-1 downto 0)); if expl = expr then fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width))); fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width))); if to_x01(l(l'high)) = '0' then -- positive number is_less_than := (fractl < fractr); else is_less_than := (fractl > fractr); -- negative end if; else if to_x01(l(l'high)) = '0' then -- positive number is_less_than := (expl < expr); else is_less_than := (expl > expr); -- negative end if; end if; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); if (lfptype = neg_zero and rfptype = pos_zero) then is_less_than := false; -- -0 < 0 returns false. else is_less_than := (to_x01(l(l'high)) > to_x01(r(r'high))); end if; end if; end if; if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return is_less_than and not is_unordered; end function lt; function gt ( -- greater than > l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable expl, expr : UNSIGNED (exponent_width-1 downto 0); variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0); variable is_greater_than : BOOLEAN; variable is_unordered : BOOLEAN; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- greater_than if (fraction_width = 0 or l'length < 7 or r'length < 7) then is_greater_than := false; else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits expl := UNSIGNED(lresize(exponent_width-1 downto 0)); expr := UNSIGNED(rresize(exponent_width-1 downto 0)); if expl = expr then fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width))); fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width))); if to_x01(l(l'high)) = '0' then -- positive number is_greater_than := fractl > fractr; else is_greater_than := fractl < fractr; -- negative end if; else if to_x01(l(l'high)) = '0' then -- positive number is_greater_than := expl > expr; else is_greater_than := expl < expr; -- negative end if; end if; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); if (lfptype = pos_zero and rfptype = neg_zero) then is_greater_than := false; -- 0 > -0 returns false. else is_greater_than := to_x01(l(l'high)) < to_x01(r(r'high)); end if; end if; end if; if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return is_greater_than and not is_unordered; end function gt; -- purpose: /= function function ne ( -- not equal /= l, r : UNRESOLVED_float; constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable is_equal, is_unordered : BOOLEAN; begin is_equal := eq (l => l, r => r, check_error => false, denormalize => denormalize); if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return not (is_equal and not is_unordered); end function ne; function le ( -- less than or equal to <= l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable is_greater_than, is_unordered : BOOLEAN; begin is_greater_than := gt (l => l, r => r, check_error => false, denormalize => denormalize); if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return not is_greater_than and not is_unordered; end function le; function ge ( -- greater than or equal to >= l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable is_less_than, is_unordered : BOOLEAN; begin is_less_than := lt (l => l, r => r, check_error => false, denormalize => denormalize); if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return not is_less_than and not is_unordered; end function ge; function "?=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable is_equal, is_unordered : STD_ULOGIC; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- ?= if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else lfptype := classfp (l, float_check_error); rfptype := classfp (r, float_check_error); end if; if (lfptype = neg_zero or lfptype = pos_zero) and (rfptype = neg_zero or rfptype = pos_zero) then is_equal := '1'; else lresize := resize (arg => l, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); rresize := resize (arg => r, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); is_equal := to_sulv(lresize) ?= to_sulv(rresize); end if; if (float_check_error) then if (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan) then is_unordered := '1'; else is_unordered := '0'; end if; else is_unordered := '0'; end if; return is_equal and not is_unordered; end function "?="; function "?/=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable is_equal, is_unordered : STD_ULOGIC; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- ?/= if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else lfptype := classfp (l, float_check_error); rfptype := classfp (r, float_check_error); end if; if (lfptype = neg_zero or lfptype = pos_zero) and (rfptype = neg_zero or rfptype = pos_zero) then is_equal := '1'; else lresize := resize (arg => l, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); rresize := resize (arg => r, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); is_equal := to_sulv(lresize) ?= to_sulv(rresize); end if; if (float_check_error) then if (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan) then is_unordered := '1'; else is_unordered := '0'; end if; else is_unordered := '0'; end if; return not (is_equal and not is_unordered); end function "?/="; function "?>" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?>"": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l > r then return '1'; else return '0'; end if; end if; end function "?>"; function "?>=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?>="": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l >= r then return '1'; else return '0'; end if; end if; end function "?>="; function "?<" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?<"": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l < r then return '1'; else return '0'; end if; end if; end function "?<"; function "?<=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?<="": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l <= r then return '1'; else return '0'; end if; end if; end function "?<="; function std_match (L, R : UNRESOLVED_float) return BOOLEAN is begin if (L'high = R'high and L'low = R'low) then return std_match(to_sulv(L), to_sulv(R)); else report float_generic_pkg'instance_name & "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE" severity warning; return false; end if; end function std_match; function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is begin for_loop : for i in arg'reverse_range loop if arg(i) ?= y then return i; end if; end loop; return arg'high+1; -- return out of bounds 'high end function find_rightmost; function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is begin for_loop : for i in arg'range loop if arg(i) ?= y then return i; end if; end loop; return arg'low-1; -- return out of bounds 'low end function find_leftmost; -- These override the defaults for the compare operators. function "=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return eq(l, r); end function "="; function "/=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return ne(l, r); end function "/="; function ">=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return ge(l, r); end function ">="; function "<=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return le(l, r); end function "<="; function ">" (l, r : UNRESOLVED_float) return BOOLEAN is begin return gt(l, r); end function ">"; function "<" (l, r : UNRESOLVED_float) return BOOLEAN is begin return lt(l, r); end function "<"; -- purpose: maximum of two numbers (overrides default) function maximum ( L, R : UNRESOLVED_float) return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin if ((L'length < 1) or (R'length < 1)) then return NAFP; end if; lresize := resize (l, exponent_width, fraction_width); rresize := resize (r, exponent_width, fraction_width); if lresize > rresize then return lresize; else return rresize; end if; end function maximum; function minimum ( L, R : UNRESOLVED_float) return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin if ((L'length < 1) or (R'length < 1)) then return NAFP; end if; lresize := resize (l, exponent_width, fraction_width); rresize := resize (r, exponent_width, fraction_width); if lresize > rresize then return rresize; else return lresize; end if; end function minimum; ----------------------------------------------------------------------------- -- conversion functions ----------------------------------------------------------------------------- -- Converts a floating point number of one format into another format function resize ( arg : UNRESOLVED_float; -- Floating point input constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant in_fraction_width : NATURAL := -arg'low; -- length of FP output fraction constant in_exponent_width : NATURAL := arg'high; -- length of FP output exponent variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result value variable fptype : valid_fpstate; variable expon_in : SIGNED (in_exponent_width-1 downto 0); variable fract_in : UNSIGNED (in_fraction_width downto 0); variable round : BOOLEAN; variable expon_out : SIGNED (exponent_width-1 downto 0); -- output fract variable fract_out : UNSIGNED (fraction_width downto 0); -- output fract variable passguard : NATURAL; begin fptype := classfp(arg, check_error); if ((fptype = pos_denormal or fptype = neg_denormal) and denormalize_in and (in_exponent_width < exponent_width or in_fraction_width < fraction_width)) or in_exponent_width > exponent_width or in_fraction_width > fraction_width then -- size reduction classcase : case fptype is when isx => result := (others => 'X'); when nan \| quiet_nan => result := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf => result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); when neg_inf => result := neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_zero \| neg_zero => result := zerofp (fraction_width => fraction_width, -- hate -0 exponent_width => exponent_width); when others => break_number ( arg => arg, fptyp => fptype, denormalize => denormalize_in, fract => fract_in, expon => expon_in); if fraction_width > in_fraction_width and denormalize_in then -- You only get here if you have a denormal input fract_out := (others => '0'); -- pad with zeros fract_out (fraction_width downto fraction_width - in_fraction_width) := fract_in; result := normalize ( fract => fract_out, expon => expon_in, sign => arg(arg'high), fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => 0); else result := normalize ( fract => fract_in, expon => expon_in, sign => arg(arg'high), fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => in_fraction_width - fraction_width); end if; end case classcase; else -- size increase or the same size if exponent_width > in_exponent_width then expon_in := SIGNED(arg (in_exponent_width-1 downto 0)); if fptype = pos_zero or fptype = neg_zero then result (exponent_width-1 downto 0) := (others => '0'); elsif expon_in = -1 then -- inf or nan (shorts out check_error) result (exponent_width-1 downto 0) := (others => '1'); else -- invert top BIT expon_in(expon_in'high) := not expon_in(expon_in'high); expon_out := resize (expon_in, expon_out'length); -- signed expand -- Flip it back. expon_out(expon_out'high) := not expon_out(expon_out'high); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon_out); end if; result (exponent_width) := arg (in_exponent_width); -- sign else -- exponent_width = in_exponent_width result (exponent_width downto 0) := arg (in_exponent_width downto 0); end if; if fraction_width > in_fraction_width then result (-1 downto -fraction_width) := (others => '0'); -- zeros result (-1 downto -in_fraction_width) := arg (-1 downto -in_fraction_width); else -- fraction_width = in_fraciton_width result (-1 downto -fraction_width) := arg (-1 downto -in_fraction_width); end if; end if; return result; end function resize; function resize ( arg : UNRESOLVED_float; -- floating point input size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := resize (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); return result; end if; end function resize; function to_float32 ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float32 is begin return resize (arg => arg, exponent_width => float32'high, fraction_width => -float32'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); end function to_float32; function to_float64 ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float64 is begin return resize (arg => arg, exponent_width => float64'high, fraction_width => -float64'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); end function to_float64; function to_float128 ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float128 is begin return resize (arg => arg, exponent_width => float128'high, fraction_width => -float128'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); end function to_float128; -- to_float (Real) -- typically not Synthesizable unless the input is a constant. function to_float ( arg : REAL; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arg_real : REAL; -- Real version of argument variable validfp : boundary_type; -- Check for valid results variable exp : INTEGER; -- Integer version of exponent variable expon : UNSIGNED (exponent_width - 1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fract : UNSIGNED (fraction_width-1 downto 0); variable frac : REAL; -- Real version of fraction constant roundfrac : REAL := 2.0 ** (-2 - fract'high); -- used for rounding variable round : BOOLEAN; -- to round or not to round begin result := (others => '0'); arg_real := arg; if arg_real < 0.0 then result (exponent_width) := '1'; arg_real := - arg_real; -- Make it positive. else result (exponent_width) := '0'; end if; test_boundary (arg => arg_real, fraction_width => fraction_width, exponent_width => exponent_width, denormalize => denormalize, btype => validfp, log2i => exp); if validfp = zero then return result; -- Result initialized to "0". elsif validfp = infinity then result (exponent_width - 1 downto 0) := (others => '1'); -- Exponent all "1" -- return infinity. return result; else if validfp = denormal then -- Exponent will default to "0". expon := (others => '0'); frac := arg_real * (2.0 (to_integer(expon_base)-1)); else -- Number less than 1. "normal" number expon := UNSIGNED (to_signed (exp-1, exponent_width)); expon(exponent_width-1) := not expon(exponent_width-1); frac := (arg_real / 2.0 exp) - 1.0; -- Number less than 1. end if; for i in 0 to fract'high loop if frac >= 2.0 (-1 - i) then fract (fract'high - i) := '1'; frac := frac - 2.0 (-1 - i); else fract (fract'high - i) := '0'; end if; end loop; round := false; case round_style is when round_nearest => if frac > roundfrac or ((frac = roundfrac) and fract(0) = '1') then round := true; end if; when round_inf => if frac /= 0.0 and result(exponent_width) = '0' then round := true; end if; when round_neginf => if frac /= 0.0 and result(exponent_width) = '1' then round := true; end if; when others => null; -- don't round end case; if (round) then if and(fract) = '1' then -- fraction is all "1" expon := expon + 1; fract := (others => '0'); else fract := fract + 1; end if; end if; result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(fract); return result; end if; end function to_float; -- to_float (Integer) function to_float ( arg : INTEGER; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arg_int : NATURAL; -- Natural version of argument variable expon : SIGNED (exponent_width-1 downto 0); variable exptmp : SIGNED (exponent_width-1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fract : UNSIGNED (fraction_width-1 downto 0) := (others => '0'); variable fracttmp : UNSIGNED (fraction_width-1 downto 0); variable round : BOOLEAN; variable shift : NATURAL; variable shiftr : NATURAL; variable roundfrac : NATURAL; -- used in rounding begin if arg < 0 then result (exponent_width) := '1'; arg_int := -arg; -- Make it positive. else result (exponent_width) := '0'; arg_int := arg; end if; if arg_int = 0 then result := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else -- If the number is larger than we can represent in this number system -- we need to return infinity. shift := log2(arg_int); if shift > to_integer(expon_base) then -- worry about infinity if result (exponent_width) = '0' then result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else -- return negative infinity. result := neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); end if; else -- Normal number (can't be denormal) -- Compute Exponent expon := to_signed (shift-1, expon'length); -- positive fraction. -- Compute Fraction arg_int := arg_int - 2shift; -- Subtract off the 1.0 shiftr := shift; for I in fract'high downto maximum (fract'high - shift + 1, 0) loop shiftr := shiftr - 1; if (arg_int >= 2shiftr) then arg_int := arg_int - 2shiftr; fract(I) := '1'; else fract(I) := '0'; end if; end loop; -- Rounding routine round := false; if arg_int > 0 then roundfrac := 2(shiftr-1); case round_style is when round_nearest => if arg_int > roundfrac or ((arg_int = roundfrac) and fract(0) = '1') then round := true; end if; when round_inf => if arg_int /= 0 and result (exponent_width) = '0' then round := true; end if; when round_neginf => if arg_int /= 0 and result (exponent_width) = '1' then round := true; end if; when others => null; end case; end if; if round then fp_round(fract_in => fract, expon_in => expon, fract_out => fracttmp, expon_out => exptmp); fract := fracttmp; expon := exptmp; end if; -- Put the number together and return expon(exponent_width-1) := not expon(exponent_width-1); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(fract); end if; end if; return result; end function to_float; -- to_float (unsigned) function to_float ( arg : UNRESOLVED_UNSIGNED; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG; variable sarg : SIGNED (ARG_LEFT+1 downto 0); -- signed version of arg begin if arg'length < 1 then return NAFP; end if; sarg (XARG'range) := SIGNED (XARG); sarg (sarg'high) := '0'; result := to_float (arg => sarg, exponent_width => exponent_width, fraction_width => fraction_width, round_style => round_style); return result; end function to_float; -- to_float (signed) function to_float ( arg : UNRESOLVED_SIGNED; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : SIGNED(ARG_LEFT downto 0) is ARG; variable arg_int : UNSIGNED(xarg'range); -- Real version of argument variable argb2 : UNSIGNED(xarg'high/2 downto 0); -- log2 of input variable rexp : SIGNED (exponent_width - 1 downto 0); variable exp : SIGNED (exponent_width - 1 downto 0); -- signed version of exp. variable expon : UNSIGNED (exponent_width - 1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable round : BOOLEAN; variable fract : UNSIGNED (fraction_width-1 downto 0); variable rfract : UNSIGNED (fraction_width-1 downto 0); variable sign : STD_ULOGIC; -- sign bit begin if arg'length < 1 then return NAFP; end if; if Is_X (xarg) then result := (others => 'X'); elsif (xarg = 0) then result := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else -- Normal number (can't be denormal) sign := to_X01(xarg (xarg'high)); arg_int := UNSIGNED(abs (to_01(xarg))); -- Compute Exponent argb2 := to_unsigned(find_leftmost(arg_int, '1'), argb2'length); -- Log2 if argb2 > UNSIGNED(expon_base) then result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); result (exponent_width) := sign; else exp := SIGNED(resize(argb2, exp'length)); arg_int := shift_left (arg_int, arg_int'high-to_integer(exp)); if (arg_int'high > fraction_width) then fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)); round := check_round ( fract_in => fract (0), sign => sign, remainder => arg_int((arg_int'high-fraction_width-1) downto 0), round_style => round_style); if round then fp_round(fract_in => fract, expon_in => exp, fract_out => rfract, expon_out => rexp); else rfract := fract; rexp := exp; end if; else rexp := exp; rfract := (others => '0'); rfract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) := arg_int (arg_int'high-1 downto 0); end if; result (exponent_width) := sign; expon := UNSIGNED (rexp-1); expon(exponent_width-1) := not expon(exponent_width-1); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(rfract); end if; end if; return result; end function to_float; -- std_logic_vector to float function to_float ( arg : STD_ULOGIC_VECTOR; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction return UNRESOLVED_float is variable fpvar : UNRESOLVED_float (exponent_width downto -fraction_width); begin if arg'length < 1 then return NAFP; end if; fpvar := UNRESOLVED_float(arg); return fpvar; end function to_float; -- purpose: converts a ufixed to a floating point function to_float ( arg : UNRESOLVED_ufixed; -- unsigned fixed point input constant exponent_width : NATURAL := float_exponent_width; -- width of exponent constant fraction_width : NATURAL := float_fraction_width; -- width of fraction constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions return UNRESOLVED_float is variable sarg : sfixed (arg'high+1 downto arg'low); -- Signed version of arg variable result : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- function to_float if (arg'length < 1) then return NAFP; end if; sarg (arg'range) := sfixed (arg); sarg (sarg'high) := '0'; result := to_float (arg => sarg, exponent_width => exponent_width, fraction_width => fraction_width, round_style => round_style, denormalize => denormalize); return result; end function to_float; function to_float ( arg : UNRESOLVED_sfixed; -- signed fixed point constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- rounding option return UNRESOLVED_float is constant integer_width : INTEGER := arg'high; constant in_fraction_width : INTEGER := arg'low; variable xresult : sfixed (integer_width downto in_fraction_width); variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arg_int : UNSIGNED(integer_width - in_fraction_width - 1 downto 0); -- signed version of argument variable argx : SIGNED (integer_width - in_fraction_width downto 0); variable exp, exptmp : SIGNED (exponent_width downto 0); variable expon : UNSIGNED (exponent_width - 1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) := (others => '0'); variable round : BOOLEAN := false; begin if (arg'length < 1) then return NAFP; end if; xresult := to_01(arg, 'X'); argx := SIGNED(to_slv(xresult)); if (Is_X (arg)) then result := (others => 'X'); elsif (argx = 0) then result := (others => '0'); else result := (others => '0'); -- zero out the result if argx(argx'left) = '1' then -- toss the sign bit result (exponent_width) := '1'; -- Negative number argx := -argx; -- Make it positive. else result (exponent_width) := '0'; end if; arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (argx(arg_int'range)))); -- Compute Exponent exp := to_signed(find_leftmost(arg_int, '1'), exp'length); -- Log2 if exp + in_fraction_width > expon_base then -- return infinity result (-1 downto -fraction_width) := (others => '0'); result (exponent_width -1 downto 0) := (others => '1'); return result; elsif (denormalize and (exp + in_fraction_width <= -resize(expon_base, exp'length))) then exp := -resize(expon_base, exp'length); -- shift by a constant arg_int := shift_left (arg_int, (arg_int'high + to_integer(expon_base) + in_fraction_width - 1)); if (arg_int'high > fraction_width) then fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)); round := check_round ( fract_in => arg_int(arg_int'high-fraction_width), sign => result(result'high), remainder => arg_int((arg_int'high-fraction_width-1) downto 0), round_style => round_style); if (round) then fp_round (fract_in => arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)), expon_in => exp, fract_out => fract, expon_out => exptmp); exp := exptmp; end if; else fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) := arg_int (arg_int'high-1 downto 0); end if; else arg_int := shift_left (arg_int, arg_int'high-to_integer(exp)); exp := exp + in_fraction_width; if (arg_int'high > fraction_width) then fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)); round := check_round ( fract_in => fract(0), sign => result(result'high), remainder => arg_int((arg_int'high-fraction_width-1) downto 0), round_style => round_style); if (round) then fp_round (fract_in => fract, expon_in => exp, fract_out => fracttmp, expon_out => exptmp); fract := fracttmp; exp := exptmp; end if; else fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) := arg_int (arg_int'high-1 downto 0); end if; end if; expon := UNSIGNED (resize(exp-1, exponent_width)); expon(exponent_width-1) := not expon(exponent_width-1); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(fract); end if; return result; end function to_float; -- size_res functions -- Integer to float function to_float ( arg : INTEGER; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style); return result; end if; end function to_float; -- real to float function to_float ( arg : REAL; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, denormalize => denormalize); return result; end if; end function to_float; -- unsigned to float function to_float ( arg : UNRESOLVED_UNSIGNED; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style); return result; end if; end function to_float; -- signed to float function to_float ( arg : UNRESOLVED_SIGNED; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style) -- rounding return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style); return result; end if; end function to_float; -- std_ulogic_vector to float function to_float ( arg : STD_ULOGIC_VECTOR; size_res : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low); return result; end if; end function to_float; -- unsigned fixed point to float function to_float ( arg : UNRESOLVED_ufixed; -- unsigned fixed point input size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, denormalize => denormalize); return result; end if; end function to_float; -- signed fixed point to float function to_float ( arg : UNRESOLVED_sfixed; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, denormalize => denormalize); return result; end if; end function to_float; -- to_integer (float) function to_integer ( arg : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return INTEGER is variable validfp : valid_fpstate; -- Valid FP state variable frac : UNSIGNED (-arg'low downto 0); -- Fraction variable fract : UNSIGNED (1-arg'low downto 0); -- Fraction variable expon : SIGNED (arg'high-1 downto 0); variable isign : STD_ULOGIC; -- internal version of sign variable round : STD_ULOGIC; -- is rounding needed? variable result : INTEGER; variable base : INTEGER; -- Integer exponent begin validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan \| pos_zero \| neg_zero \| pos_denormal \| neg_denormal => result := 0; -- return 0 when pos_inf => result := INTEGER'high; when neg_inf => result := INTEGER'low; when others => break_number ( arg => arg, fptyp => validfp, denormalize => false, fract => frac, expon => expon); fract (fract'high) := '0'; -- Add extra bit for 0.6 case fract (fract'high-1 downto 0) := frac; isign := to_x01 (arg (arg'high)); base := to_integer (expon) + 1; if base < -1 then result := 0; elsif base >= frac'high then result := to_integer (fract) * 2(base - frac'high); else -- We need to round if base = -1 then -- trap for 0.6 case. result := 0; else result := to_integer (fract (frac'high downto frac'high-base)); end if; -- rounding routine case round_style is when round_nearest => if frac'high - base > 1 then round := fract (frac'high - base - 1) and (fract (frac'high - base) or (or (fract (frac'high - base - 2 downto 0)))); else round := fract (frac'high - base - 1) and fract (frac'high - base); end if; when round_inf => round := fract(frac'high - base - 1) and not isign; when round_neginf => round := fract(frac'high - base - 1) and isign; when others => round := '0'; end case; if round = '1' then result := result + 1; end if; end if; if isign = '1' then result := - result; end if; end case classcase; return result; end function to_integer; -- to_unsigned (float) function to_unsigned ( arg : UNRESOLVED_float; -- floating point input constant size : NATURAL; -- length of output constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_UNSIGNED is variable validfp : valid_fpstate; -- Valid FP state variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction variable sign : STD_ULOGIC; -- not used begin validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan => frac := (others => 'X'); when pos_zero \| neg_inf \| neg_zero \| neg_normal \| pos_denormal \| neg_denormal => frac := (others => '0'); -- return 0 when pos_inf => frac := (others => '1'); when others => float_to_unsigned ( arg => arg, frac => frac, sign => sign, denormalize => false, bias => 0, round_style => round_style); end case classcase; return (frac); end function to_unsigned; -- to_signed (float) function to_signed ( arg : UNRESOLVED_float; -- floating point input constant size : NATURAL; -- length of output constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_SIGNED is variable sign : STD_ULOGIC; -- true if negative variable validfp : valid_fpstate; -- Valid FP state variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction variable result : UNRESOLVED_SIGNED (size-1 downto 0); begin validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan => result := (others => 'X'); when pos_zero \| neg_zero \| pos_denormal \| neg_denormal => result := (others => '0'); -- return 0 when pos_inf => result := (others => '1'); result (result'high) := '0'; when neg_inf => result := (others => '0'); result (result'high) := '1'; when others => float_to_unsigned ( arg => arg, sign => sign, frac => frac, denormalize => false, bias => 0, round_style => round_style); result (size-1) := '0'; result (size-2 downto 0) := UNRESOLVED_SIGNED(frac (size-2 downto 0)); if sign = '1' then -- Because the most negative signed number is 1 less than the most -- positive signed number, we need this code. if frac(frac'high) = '1' then -- return most negative number result := (others => '0'); result (result'high) := '1'; else result := -result; end if; else if frac(frac'high) = '1' then -- return most positive number result := (others => '1'); result (result'high) := '0'; end if; end if; end case classcase; return result; end function to_signed; -- purpose: Converts a float to ufixed function to_ufixed ( arg : UNRESOLVED_float; -- fp input constant left_index : INTEGER; -- integer part constant right_index : INTEGER; -- fraction part constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_ufixed is constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent constant size : INTEGER := left_index - right_index + 4; -- unsigned size variable expon_base : INTEGER; -- exponent offset variable validfp : valid_fpstate; -- Valid FP state variable exp : INTEGER; -- Exponent variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent -- Base to divide fraction by variable frac : UNSIGNED (size-1 downto 0) := (others => '0'); -- Fraction variable frac_shift : UNSIGNED (size-1 downto 0); -- Fraction shifted variable shift : INTEGER; variable result_big : UNRESOLVED_ufixed (left_index downto right_index-3); variable result : UNRESOLVED_ufixed (left_index downto right_index); -- result begin -- function to_ufixed validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan => frac := (others => 'X'); when pos_zero \| neg_inf \| neg_zero \| neg_normal \| neg_denormal => frac := (others => '0'); -- return 0 when pos_inf => frac := (others => '1'); -- always saturate when others => expon_base := 2(exponent_width-1) -1; -- exponent offset -- Figure out the fraction if (validfp = pos_denormal) and denormalize then exp := -expon_base +1; frac (frac'high) := '0'; -- Remove the "1.0". else -- exponent /= '0', normal floating point expon := UNSIGNED(arg (exponent_width-1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (SIGNED(expon)) +1; frac (frac'high) := '1'; -- Add the "1.0". end if; shift := (frac'high - 3 + right_index) - exp; if fraction_width > frac'high then -- Can only use size-2 bits frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto -frac'high))); else -- can use all bits frac (frac'high-1 downto frac'high-fraction_width) := UNSIGNED (to_slv (arg(-1 downto -fraction_width))); end if; frac_shift := frac srl shift; if shift < 0 then -- Overflow frac := (others => '1'); else frac := frac_shift; end if; end case classcase; result_big := to_ufixed ( arg => STD_ULOGIC_VECTOR(frac), left_index => left_index, right_index => (right_index-3)); result := resize (arg => result_big, left_index => left_index, right_index => right_index, round_style => round_style, overflow_style => overflow_style); return result; end function to_ufixed; -- purpose: Converts a float to sfixed function to_sfixed ( arg : UNRESOLVED_float; -- fp input constant left_index : INTEGER; -- integer part constant right_index : INTEGER; -- fraction part constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_sfixed is constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent constant size : INTEGER := left_index - right_index + 4; -- unsigned size variable expon_base : INTEGER; -- exponent offset variable validfp : valid_fpstate; -- Valid FP state variable exp : INTEGER; -- Exponent variable sign : BOOLEAN; -- true if negative variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent -- Base to divide fraction by variable frac : UNSIGNED (size-2 downto 0) := (others => '0'); -- Fraction variable frac_shift : UNSIGNED (size-2 downto 0); -- Fraction shifted variable shift : INTEGER; variable rsigned : SIGNED (size-1 downto 0); -- signed version of result variable result_big : UNRESOLVED_sfixed (left_index downto right_index-3); variable result : UNRESOLVED_sfixed (left_index downto right_index) := (others => '0'); -- result begin -- function to_sfixed validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan => result := (others => 'X'); when pos_zero \| neg_zero => result := (others => '0'); -- return 0 when neg_inf => result (left_index) := '1'; -- return smallest negative number when pos_inf => result := (others => '1'); -- return largest number result (left_index) := '0'; when others => expon_base := 2(exponent_width-1) -1; -- exponent offset if arg(exponent_width) = '0' then sign := false; else sign := true; end if; -- Figure out the fraction if (validfp = pos_denormal or validfp = neg_denormal) and denormalize then exp := -expon_base +1; frac (frac'high) := '0'; -- Add the "1.0". else -- exponent /= '0', normal floating point expon := UNSIGNED(arg (exponent_width-1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (SIGNED(expon)) +1; frac (frac'high) := '1'; -- Add the "1.0". end if; shift := (frac'high - 3 + right_index) - exp; if fraction_width > frac'high then -- Can only use size-2 bits frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto -frac'high))); else -- can use all bits frac (frac'high-1 downto frac'high-fraction_width) := UNSIGNED (to_slv (arg(-1 downto -fraction_width))); end if; frac_shift := frac srl shift; if shift < 0 then -- Overflow frac := (others => '1'); else frac := frac_shift; end if; if not sign then rsigned := SIGNED("0" & frac); else rsigned := -(SIGNED("0" & frac)); end if; result_big := to_sfixed ( arg => STD_LOGIC_VECTOR(rsigned), left_index => left_index, right_index => (right_index-3)); result := resize (arg => result_big, left_index => left_index, right_index => right_index, round_style => round_style, overflow_style => overflow_style); end case classcase; return result; end function to_sfixed; -- size_res versions -- float to unsigned function to_unsigned ( arg : UNRESOLVED_float; -- floating point input size_res : UNRESOLVED_UNSIGNED; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_UNSIGNED is variable result : UNRESOLVED_UNSIGNED (size_res'range); begin if (SIZE_RES'length = 0) then return result; else result := to_unsigned ( arg => arg, size => size_res'length, round_style => round_style, check_error => check_error); return result; end if; end function to_unsigned; -- float to signed function to_signed ( arg : UNRESOLVED_float; -- floating point input size_res : UNRESOLVED_SIGNED; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_SIGNED is variable result : UNRESOLVED_SIGNED (size_res'range); begin if (SIZE_RES'length = 0) then return result; else result := to_signed ( arg => arg, size => size_res'length, round_style => round_style, check_error => check_error); return result; end if; end function to_signed; -- purpose: Converts a float to unsigned fixed point function to_ufixed ( arg : UNRESOLVED_float; -- fp input size_res : UNRESOLVED_ufixed; constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_ufixed is variable result : UNRESOLVED_ufixed (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_ufixed ( arg => arg, left_index => size_res'high, right_index => size_res'low, overflow_style => overflow_style, round_style => round_style, check_error => check_error, denormalize => denormalize); return result; end if; end function to_ufixed; -- float to signed fixed point function to_sfixed ( arg : UNRESOLVED_float; -- fp input size_res : UNRESOLVED_sfixed; constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_sfixed is variable result : UNRESOLVED_sfixed (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_sfixed ( arg => arg, left_index => size_res'high, right_index => size_res'low, overflow_style => overflow_style, round_style => round_style, check_error => check_error, denormalize => denormalize); return result; end if; end function to_sfixed; -- to_real (float) -- typically not Synthesizable unless the input is a constant. function to_real ( arg : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return REAL is constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent variable sign : REAL; -- Sign, + or - 1 variable exp : INTEGER; -- Exponent variable expon_base : INTEGER; -- exponent offset variable frac : REAL := 0.0; -- Fraction variable validfp : valid_fpstate; -- Valid FP state variable expon : UNSIGNED (exponent_width - 1 downto 0) := (others => '1'); -- Vectorized exponent begin validfp := classfp (arg, check_error); classcase : case validfp is when isx \| pos_zero \| neg_zero \| nan \| quiet_nan => return 0.0; when neg_inf => return REAL'low; -- Negative infinity. when pos_inf => return REAL'high; -- Positive infinity when others => expon_base := 2(exponent_width-1) -1; if to_X01(arg(exponent_width)) = '0' then sign := 1.0; else sign := -1.0; end if; -- Figure out the fraction for i in 0 to fraction_width-1 loop if to_X01(arg (-1 - i)) = '1' then frac := frac + (2.0 *(-1 - i)); end if; end loop; -- i if validfp = pos_normal or validfp = neg_normal or not denormalize then -- exponent /= '0', normal floating point expon := UNSIGNED(arg (exponent_width-1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (SIGNED(expon)) +1; sign := sign (2.0 ** exp) * (1.0 + frac); else -- exponent = '0', IEEE extended floating point exp := 1 - expon_base; sign := sign * (2.0 ** exp) * frac; end if; return sign; end case classcase; end function to_real; -- For Verilog compatability function realtobits (arg : REAL) return STD_ULOGIC_VECTOR is variable result : float64; -- 64 bit floating point begin result := to_float (arg => arg, exponent_width => float64'high, fraction_width => -float64'low); return to_sulv (result); end function realtobits; function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL is variable arg64 : float64; -- arg converted to float begin arg64 := to_float (arg => arg, exponent_width => float64'high, fraction_width => -float64'low); return to_real (arg64); end function bitstoreal; -- purpose: Removes meta-logical values from FP string function to_01 ( arg : UNRESOLVED_float; -- floating point input XMAP : STD_LOGIC := '0') return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin -- function to_01 if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_01: null detected, returning NULL" severity warning; return NAFP; end if; result := UNRESOLVED_float (STD_LOGIC_VECTOR(to_01(UNSIGNED(to_slv(arg)), XMAP))); return result; end function to_01; function Is_X (arg : UNRESOLVED_float) return BOOLEAN is begin return Is_X (to_slv(arg)); end function Is_X; function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_X01: null detected, returning NULL" severity warning; return NAFP; else result := UNRESOLVED_float (to_X01(to_slv(arg))); return result; end if; end function to_X01; function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_X01Z: null detected, returning NULL" severity warning; return NAFP; else result := UNRESOLVED_float (to_X01Z(to_slv(arg))); return result; end if; end function to_X01Z; function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_UX01: null detected, returning NULL" severity warning; return NAFP; else result := UNRESOLVED_float (to_UX01(to_slv(arg))); return result; end if; end function to_UX01; -- These allows the base math functions to use the default values -- of their parameters. Thus they do full IEEE floating point. function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return add (l, r); end function "+"; function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return subtract (l, r); end function "-"; function "" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return multiply (l, r); end function ""; function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return divide (l, r); end function "/"; function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return remainder (l, r); end function "rem"; function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return modulo (l, r); end function "mod"; -- overloaded versions function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return add (l, r_float); end function "+"; function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return add (l_float, r); end function "+"; function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return add (l, r_float); end function "+"; function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return add (l_float, r); end function "+"; function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return subtract (l, r_float); end function "-"; function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return subtract (l_float, r); end function "-"; function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return subtract (l, r_float); end function "-"; function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return subtract (l_float, r); end function "-"; function "" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return multiply (l, r_float); end function ""; function "" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return multiply (l_float, r); end function ""; function "" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return multiply (l, r_float); end function ""; function "" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return multiply (l_float, r); end function ""; function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return divide (l, r_float); end function "/"; function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return divide (l_float, r); end function "/"; function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return divide (l, r_float); end function "/"; function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return divide (l_float, r); end function "/"; function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return remainder (l, r_float); end function "rem"; function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return remainder (l_float, r); end function "rem"; function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return remainder (l, r_float); end function "rem"; function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return remainder (l_float, r); end function "rem"; function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return modulo (l, r_float); end function "mod"; function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return modulo (l_float, r); end function "mod"; function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return modulo (l, r_float); end function "mod"; function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return modulo (l_float, r); end function "mod"; function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return eq (l, r_float); end function "="; function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ne (l, r_float); end function "/="; function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ge (l, r_float); end function ">="; function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return le (l, r_float); end function "<="; function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return gt (l, r_float); end function ">"; function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return lt (l, r_float); end function "<"; function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return eq (l_float, r); end function "="; function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ne (l_float, r); end function "/="; function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ge (l_float, r); end function ">="; function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return le (l_float, r); end function "<="; function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return gt (l_float, r); end function ">"; function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return lt (l_float, r); end function "<"; function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return eq (l, r_float); end function "="; function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ne (l, r_float); end function "/="; function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ge (l, r_float); end function ">="; function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return le (l, r_float); end function "<="; function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return gt (l, r_float); end function ">"; function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return lt (l, r_float); end function "<"; function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return eq (l_float, r); end function "="; function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ne (l_float, r); end function "/="; function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ge (l_float, r); end function ">="; function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return le (l_float, r); end function "<="; function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return gt (l_float, r); end function ">"; function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return lt (l_float, r); end function "<"; -- ?= overloads function "?=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?= r_float; end function "?="; function "?/=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?/= r_float; end function "?/="; function "?>" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?> r_float; end function "?>"; function "?>=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?>= r_float; end function "?>="; function "?<" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?< r_float; end function "?<"; function "?<=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?<= r_float; end function "?<="; -- real and float function "?=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?= r; end function "?="; function "?/=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?/= r; end function "?/="; function "?>" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?> r; end function "?>"; function "?>=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?>= r; end function "?>="; function "?<" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?< r; end function "?<"; function "?<=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?<= r; end function "?<="; -- ?= overloads function "?=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?= r_float; end function "?="; function "?/=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?/= r_float; end function "?/="; function "?>" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?> r_float; end function "?>"; function "?>=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?>= r_float; end function "?>="; function "?<" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?< r_float; end function "?<"; function "?<=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?<= r_float; end function "?<="; -- integer and float function "?=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?= r; end function "?="; function "?/=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?/= r; end function "?/="; function "?>" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?> r; end function "?>"; function "?>=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?>= r; end function "?>="; function "?<" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?< r; end function "?<"; function "?<=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?<= r; end function "?<="; -- minimum and maximum overloads function minimum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return minimum (l, r_float); end function minimum; function maximum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return maximum (l, r_float); end function maximum; function minimum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return minimum (l_float, r); end function minimum; function maximum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return maximum (l_float, r); end function maximum; function minimum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return minimum (l, r_float); end function minimum; function maximum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return maximum (l, r_float); end function maximum; function minimum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return minimum (l_float, r); end function minimum; function maximum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return maximum (l_float, r); end function maximum; ---------------------------------------------------------------------------- -- logical functions ---------------------------------------------------------------------------- function "not" (L : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin RESULT := not to_sulv(L); return to_float (RESULT, L'high, -L'low); end function "not"; function "and" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) and to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """and"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "and"; function "or" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) or to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """or"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "or"; function "nand" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) nand to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """nand"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "nand"; function "nor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) nor to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """nor"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "nor"; function "xor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) xor to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """xor"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "xor"; function "xnor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) xnor to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """xnor"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "xnor"; -- Vector and std_ulogic functions, same as functions in numeric_std function "and" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L and to_sulv(R)); return result; end function "and"; function "and" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) and R); return result; end function "and"; function "or" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L or to_sulv(R)); return result; end function "or"; function "or" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) or R); return result; end function "or"; function "nand" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L nand to_sulv(R)); return result; end function "nand"; function "nand" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) nand R); return result; end function "nand"; function "nor" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L nor to_sulv(R)); return result; end function "nor"; function "nor" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) nor R); return result; end function "nor"; function "xor" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L xor to_sulv(R)); return result; end function "xor"; function "xor" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) xor R); return result; end function "xor"; function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L xnor to_sulv(R)); return result; end function "xnor"; function "xnor" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) xnor R); return result; end function "xnor"; -- Reduction operators, same as numeric_std functions function "and" (l : UNRESOLVED_float) return STD_ULOGIC is begin return and to_sulv(l); end function "and"; function "nand" (l : UNRESOLVED_float) return STD_ULOGIC is begin return nand to_sulv(l); end function "nand"; function "or" (l : UNRESOLVED_float) return STD_ULOGIC is begin return or to_sulv(l); end function "or"; function "nor" (l : UNRESOLVED_float) return STD_ULOGIC is begin return nor to_sulv(l); end function "nor"; function "xor" (l : UNRESOLVED_float) return STD_ULOGIC is begin return xor to_sulv(l); end function "xor"; function "xnor" (l : UNRESOLVED_float) return STD_ULOGIC is begin return xnor to_sulv(l); end function "xnor"; ----------------------------------------------------------------------------- -- Recommended Functions from the IEEE 754 Appendix ----------------------------------------------------------------------------- -- returns x with the sign of y. function Copysign ( x, y : UNRESOLVED_float) -- floating point input return UNRESOLVED_float is begin return y(y'high) & x (x'high-1 downto x'low); end function Copysign; -- Returns y * 2n for integral values of N without computing 2n function Scalb ( y : UNRESOLVED_float; -- floating point input N : INTEGER; -- exponent to add constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(y'low, y'low); -- length of FP output fraction constant exponent_width : NATURAL := y'high; -- length of FP output exponent variable arg, result : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp variable exp : SIGNED (exponent_width downto 0); variable ufract : UNSIGNED (fraction_width downto 0); constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fptype : valid_fpstate; begin -- This can be done by simply adding N to the exponent. arg := to_01 (y, 'X'); fptype := classfp(arg, check_error); classcase : case fptype is when isx => result := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 result := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when others => break_number ( arg => arg, fptyp => fptype, denormalize => denormalize, fract => ufract, expon => expon); exp := resize (expon, exp'length) + N; result := normalize ( fract => ufract, expon => exp, sign => to_x01 (arg (arg'high)), fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => 0); end case classcase; return result; end function Scalb; -- Returns y * 2n for integral values of N without computing 2n function Scalb ( y : UNRESOLVED_float; -- floating point input N : UNRESOLVED_SIGNED; -- exponent to add constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable n_int : INTEGER; begin n_int := to_integer(N); return Scalb (y => y, N => n_int, round_style => round_style, check_error => check_error, denormalize => denormalize); end function Scalb; -- returns the unbiased exponent of x function Logb ( x : UNRESOLVED_float) -- floating point input return INTEGER is constant fraction_width : NATURAL := -mine (x'low, x'low); -- length of FP output fraction constant exponent_width : NATURAL := x'high; -- length of FP output exponent variable result : INTEGER; -- result variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument variable expon : SIGNED (exponent_width - 1 downto 0); variable fract : UNSIGNED (fraction_width downto 0); constant expon_base : INTEGER := 2*(exponent_width-1) -1; -- exponent -- offset +1 variable fptype : valid_fpstate; begin -- Just return the exponent. arg := to_01 (x, 'X'); fptype := classfp(arg); classcase : case fptype is when isx \| nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 result := 0; when pos_denormal \| neg_denormal => fract (fraction_width) := '0'; fract (fraction_width-1 downto 0) := UNSIGNED (to_slv(arg(-1 downto -fraction_width))); result := find_leftmost (fract, '1') -- Find the first "1" - fraction_width; -- subtract the length we want result := -expon_base + 1 + result; when others => expon := SIGNED(arg (exponent_width - 1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); expon := expon + 1; result := to_integer (expon); end case classcase; return result; end function Logb; -- returns the unbiased exponent of x function Logb ( x : UNRESOLVED_float) -- floating point input return UNRESOLVED_SIGNED is constant exponent_width : NATURAL := x'high; -- length of FP output exponent variable result : SIGNED (exponent_width - 1 downto 0); -- result begin -- Just return the exponent. result := to_signed (Logb (x), exponent_width); return result; end function Logb; -- returns the next representable neighbor of x in the direction toward y function Nextafter ( x, y : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(x'low, x'low); -- length of FP output fraction constant exponent_width : NATURAL := x'high; -- length of FP output exponent function "=" ( l, r : UNRESOLVED_float) -- inputs return BOOLEAN is begin -- function "=" return eq (l => l, r => r, check_error => false); end function "="; function ">" ( l, r : UNRESOLVED_float) -- inputs return BOOLEAN is begin -- function ">" return gt (l => l, r => r, check_error => false); end function ">"; variable fract : UNSIGNED (fraction_width-1 downto 0); variable expon : UNSIGNED (exponent_width-1 downto 0); variable sign : STD_ULOGIC; variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable validfpx, validfpy : valid_fpstate; -- Valid FP state begin -- fp_Nextafter -- If Y > X, add one to the fraction, otherwise subtract. validfpx := classfp (x, check_error); validfpy := classfp (y, check_error); if validfpx = isx or validfpy = isx then result := (others => 'X'); return result; elsif (validfpx = nan or validfpy = nan) then return nanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (validfpx = quiet_nan or validfpy = quiet_nan) then return qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif x = y then -- Return X return x; else fract := UNSIGNED (to_slv (x (-1 downto -fraction_width))); -- Fraction expon := UNSIGNED (x (exponent_width - 1 downto 0)); -- exponent sign := x(exponent_width); -- sign bit if (y > x) then -- Increase the number given if validfpx = neg_inf then -- return most negative number expon := (others => '1'); expon (0) := '0'; fract := (others => '1'); elsif validfpx = pos_zero or validfpx = neg_zero then -- return smallest denormal number sign := '0'; expon := (others => '0'); fract := (others => '0'); fract(0) := '1'; elsif validfpx = pos_normal then if and (fract) = '1' then -- fraction is all "1". if and (expon (exponent_width-1 downto 1)) = '1' and expon (0) = '0' then -- Exponent is one away from infinity. assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "FP_NEXTAFTER: NextAfter overflow" severity warning; return pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else expon := expon + 1; fract := (others => '0'); end if; else fract := fract + 1; end if; elsif validfpx = pos_denormal then if and (fract) = '1' then -- fraction is all "1". -- return smallest possible normal number expon := (others => '0'); expon(0) := '1'; fract := (others => '0'); else fract := fract + 1; end if; elsif validfpx = neg_normal then if or (fract) = '0' then -- fraction is all "0". if or (expon (exponent_width-1 downto 1)) = '0' and expon (0) = '1' then -- Smallest exponent -- return the largest negative denormal number expon := (others => '0'); fract := (others => '1'); else expon := expon - 1; fract := (others => '1'); end if; else fract := fract - 1; end if; elsif validfpx = neg_denormal then if or (fract(fract'high downto 1)) = '0' and fract (0) = '1' then -- Smallest possible fraction return zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else fract := fract - 1; end if; end if; else -- Decrease the number if validfpx = pos_inf then -- return most positive number expon := (others => '1'); expon (0) := '0'; fract := (others => '1'); elsif validfpx = pos_zero or classfp (x) = neg_zero then -- return smallest negative denormal number sign := '1'; expon := (others => '0'); fract := (others => '0'); fract(0) := '1'; elsif validfpx = neg_normal then if and (fract) = '1' then -- fraction is all "1". if and (expon (exponent_width-1 downto 1)) = '1' and expon (0) = '0' then -- Exponent is one away from infinity. assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "FP_NEXTAFTER: NextAfter overflow" severity warning; return neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else expon := expon + 1; -- Fraction overflow fract := (others => '0'); end if; else fract := fract + 1; end if; elsif validfpx = neg_denormal then if and (fract) = '1' then -- fraction is all "1". -- return smallest possible normal number expon := (others => '0'); expon(0) := '1'; fract := (others => '0'); else fract := fract + 1; end if; elsif validfpx = pos_normal then if or (fract) = '0' then -- fraction is all "0". if or (expon (exponent_width-1 downto 1)) = '0' and expon (0) = '1' then -- Smallest exponent -- return the largest positive denormal number expon := (others => '0'); fract := (others => '1'); else expon := expon - 1; fract := (others => '1'); end if; else fract := fract - 1; end if; elsif validfpx = pos_denormal then if or (fract(fract'high downto 1)) = '0' and fract (0) = '1' then -- Smallest possible fraction return zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else fract := fract - 1; end if; end if; end if; result (-1 downto -fraction_width) := UNRESOLVED_float(fract); result (exponent_width -1 downto 0) := UNRESOLVED_float(expon); result (exponent_width) := sign; return result; end if; end function Nextafter; -- Returns True if X is unordered with Y. function Unordered ( x, y : UNRESOLVED_float) -- floating point input return BOOLEAN is variable lfptype, rfptype : valid_fpstate; begin lfptype := classfp (x); rfptype := classfp (y); if (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan or lfptype = isx or rfptype = isx) then return true; else return false; end if; end function Unordered; function Finite ( x : UNRESOLVED_float) return BOOLEAN is variable fp_state : valid_fpstate; -- fp state begin fp_state := Classfp (x); if (fp_state = pos_inf) or (fp_state = neg_inf) then return true; else return false; end if; end function Finite; function Isnan ( x : UNRESOLVED_float) return BOOLEAN is variable fp_state : valid_fpstate; -- fp state begin fp_state := Classfp (x); if (fp_state = nan) or (fp_state = quiet_nan) then return true; else return false; end if; end function Isnan; -- Function to return constants. function zerofp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is constant result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin return result; end function zerofp; function nanfp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1" result (-1) := '1'; -- MSB of Fraction "1" -- Note: From W. Khan "IEEE Standard 754 for Binary Floating Point" -- The difference between a signaling NAN and a quiet NAN is that -- the MSB of the Fraction is a "1" in a Signaling NAN, and is a -- "0" in a quiet NAN. return result; end function nanfp; function qnanfp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1" result (-fraction_width) := '1'; -- LSB of Fraction "1" -- (Could have been any bit) return result; end function qnanfp; function pos_inffp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1" return result; end function pos_inffp; function neg_inffp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width downto 0) := (others => '1'); -- top bits all "1" return result; end function neg_inffp; function neg_zerofp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width) := '1'; return result; end function neg_zerofp; -- size_res versions function zerofp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return zerofp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function zerofp; function nanfp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return nanfp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function nanfp; function qnanfp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return qnanfp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function qnanfp; function pos_inffp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return pos_inffp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function pos_inffp; function neg_inffp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return neg_inffp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function neg_inffp; function neg_zerofp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return neg_zerofp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function neg_zerofp; -- Textio functions -- purpose: writes float into a line (NOTE changed basetype) type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error); type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER; type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC; type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus; constant NBSP : CHARACTER := CHARACTER'val(160); -- space character constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-"; constant char_to_MVL9 : MVL9_indexed_by_char := ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U'); constant char_to_MVL9plus : MVL9plus_indexed_by_char := ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error); -- purpose: Skips white space procedure skip_whitespace ( L : inout LINE) is variable readOk : BOOLEAN; variable c : CHARACTER; begin while L /= null and L.all'length /= 0 loop c := l (l'left); if (c = ' ' or c = NBSP or c = HT) then read (l, c, readOk); else exit; end if; end loop; end procedure skip_whitespace; -- purpose: Checks the punctuation in a line procedure check_punctuation ( arg : in STRING; colon : out BOOLEAN; -- There was a colon in the line dot : out BOOLEAN; -- There was a dot in the line good : out BOOLEAN; -- True if enough characters found chars : in INTEGER) is -- Examples. Legal inputs are "0000000", "0000.000", "0:000:000" alias xarg : STRING (1 to arg'length) is arg; -- make it downto range variable icolon, idot : BOOLEAN; -- internal variable j : INTEGER := 0; -- charters read begin good := false; icolon := false; idot := false; for i in 1 to arg'length loop if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j = chars then exit; elsif xarg(i) = ':' then icolon := true; elsif xarg(i) = '.' then idot := true; elsif xarg (i) /= '_' then j := j + 1; end if; end loop; if j = chars then good := true; -- There are enough charactes to read end if; colon := icolon; if idot and icolon then dot := false; else dot := idot; end if; end procedure check_punctuation; -- purpose: Searches a line for a ":" and replaces it with a ".". procedure fix_colon ( arg : inout STRING; chars : in integer) is alias xarg : STRING (1 to arg'length) is arg; -- make it downto range variable j : INTEGER := 0; -- charters read begin for i in 1 to arg'length loop if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j > chars then exit; elsif xarg(i) = ':' then xarg (i) := '.'; elsif xarg (i) /= '_' then j := j + 1; end if; end loop; end procedure fix_colon; procedure WRITE ( L : inout LINE; -- input line VALUE : in UNRESOLVED_float; -- floating point input JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable s : STRING(1 to value'high - value'low +3); variable sindx : INTEGER; begin -- function write s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high))); s(2) := ':'; sindx := 3; for i in VALUE'high-1 downto 0 loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; s(sindx) := ':'; sindx := sindx + 1; for i in -1 downto VALUE'low loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; WRITE (L, s, JUSTIFIED, FIELD); end procedure WRITE; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float) is -- Possible data: 0:0000:0000000 -- 000000000000 variable c : CHARACTER; variable mv : UNRESOLVED_float (VALUE'range); variable readOk : BOOLEAN; variable lastu : BOOLEAN := false; -- last character was an "_" variable i : INTEGER; -- index variable begin -- READ VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); READ (l, c, readOk); if VALUE'length > 0 then i := value'high; readloop : loop if readOk = false then -- Bail out if there was a bad read report float_generic_pkg'instance_name & "READ(float): " & "Error end of file encountered." severity error; return; elsif c = ' ' or c = CR or c = HT then -- reading done. if (i /= value'low) then report float_generic_pkg'instance_name & "READ(float): " & "Warning: Value truncated." severity warning; return; end if; elsif c = '_' then if i = value'high then -- Begins with an "_" report float_generic_pkg'instance_name & "READ(float): " & "String begins with an ""_""" severity error; return; elsif lastu then -- "__" detected report float_generic_pkg'instance_name & "READ(float): " & "Two underscores detected in input string ""__""" severity error; return; else lastu := true; end if; elsif c = ':' or c = '.' then -- separator, ignore if not (i = -1 or i = value'high-1) then report float_generic_pkg'instance_name & "READ(float): " & "Warning: Separator point does not match number format: '" & c & "' encountered at location " & INTEGER'image(i) & "." severity warning; end if; lastu := false; elsif (char_to_MVL9plus(c) = error) then report float_generic_pkg'instance_name & "READ(float): " & "Error: Character '" & c & "' read, expected STD_ULOGIC literal." severity error; return; else mv (i) := char_to_MVL9(c); i := i - 1; if i < value'low then VALUE := mv; return; end if; lastu := false; end if; READ (l, c, readOk); end loop readloop; end if; end procedure READ; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is -- Possible data: 0:0000:0000000 -- 000000000000 variable c : CHARACTER; variable mv : UNRESOLVED_float (VALUE'range); variable lastu : BOOLEAN := false; -- last character was an "_" variable i : INTEGER; -- index variable variable readOk : BOOLEAN; begin -- READ VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); READ (l, c, readOk); if VALUE'length > 0 then i := value'high; good := false; readloop : loop if readOk = false then -- Bail out if there was a bad read return; elsif c = ' ' or c = CR or c = HT then -- reading done return; elsif c = '_' then if i = 0 then -- Begins with an "_" return; elsif lastu then -- "__" detected return; else lastu := true; end if; elsif c = ':' or c = '.' then -- separator, ignore -- good := (i = -1 or i = value'high-1); lastu := false; elsif (char_to_MVL9plus(c) = error) then return; else mv (i) := char_to_MVL9(c); i := i - 1; if i < value'low then good := true; VALUE := mv; return; end if; lastu := false; end if; READ (l, c, readOk); end loop readloop; else good := true; -- read into a null array end if; end procedure READ; procedure OWRITE ( L : inout LINE; -- access type (pointer) VALUE : in UNRESOLVED_float; -- value to write JUSTIFIED : in SIDE := right; -- which side to justify text FIELD : in WIDTH := 0) is -- width of field begin WRITE (L => L, VALUE => to_ostring(VALUE), JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure OWRITE; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is constant ne : INTEGER := ((value'length+2)/3) 3; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/3); if not ok then report float_generic_pkg'instance_name & "OREAD: " & "short string encounted: " & L.all & " needs to have " & integer'image (ne/3) & " valid octal characters." severity error; return; elsif dot then OREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "OREAD: " & "error encounted reading STRING " & L.all severity error; return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then OREAD (L, nybble, ok); -- read the sign bit if not ok then report float_generic_pkg'instance_name & "OREAD: " & "End of string encountered" severity error; return; elsif nybble (2 downto 1) /= "00" then report float_generic_pkg'instance_name & "OREAD: " & "Illegal sign bit STRING encounted " severity error; return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/3); -- replaces the colon with a ".". OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "OREAD: " & "error encounted reading STRING " & L.all severity error; return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else OREAD (L, slv, ok); if not ok then report float_generic_pkg'instance_name & "OREAD: " & "Error encounted during read" severity error; return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then report float_generic_pkg'instance_name & "OREAD: " & "Vector truncated." severity error; return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; end if; end procedure OREAD; procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" GOOD := false; Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/3); if not ok then return; elsif dot then OREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then OREAD (L, nybble, ok); -- read the sign bit if not ok then return; elsif nybble (2 downto 1) /= "00" then return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/3); -- replaces the colon with a ".". OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else OREAD (L, slv, ok); if not ok then return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; GOOD := true; end if; end procedure OREAD; procedure HWRITE ( L : inout LINE; -- access type (pointer) VALUE : in UNRESOLVED_float; -- value to write JUSTIFIED : in SIDE := right; -- which side to justify text FIELD : in WIDTH := 0) is -- width of field begin WRITE (L => L, VALUE => to_hstring(VALUE), JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure HWRITE; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/4); if not ok then report float_generic_pkg'instance_name & "HREAD: " & "short string encounted: " & L.all & " needs to have " & integer'image (ne/4) & " valid hex characters." severity error; return; elsif dot then HREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "HREAD: " & "error encounted reading STRING " & L.all severity error; return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then HREAD (L, nybble, ok); -- read the sign bit if not ok then report float_generic_pkg'instance_name & "HREAD: " & "End of string encountered" severity error; return; elsif nybble (3 downto 1) /= "000" then report float_generic_pkg'instance_name & "HREAD: " & "Illegal sign bit STRING encounted " severity error; return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/4); -- replaces the colon with a ".". HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "HREAD: " & "error encounted reading STRING " & L.all severity error; return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else HREAD (L, slv, ok); if not ok then report float_generic_pkg'instance_name & "HREAD: " & "Error encounted during read" severity error; return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then report float_generic_pkg'instance_name & "HREAD: " & "Vector truncated." severity error; return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; end if; end procedure HREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" GOOD := false; Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/4); if not ok then return; elsif dot then HREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then HREAD (L, nybble, ok); -- read the sign bit if not ok then return; elsif nybble (3 downto 1) /= "000" then return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/4); -- replaces the colon with a ".". HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else HREAD (L, slv, ok); if not ok then return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; GOOD := true; end if; end procedure HREAD; function to_string (value : UNRESOLVED_float) return STRING is variable s : STRING(1 to value'high - value'low +3); variable sindx : INTEGER; begin -- function write s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high))); s(2) := ':'; sindx := 3; for i in VALUE'high-1 downto 0 loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; s(sindx) := ':'; sindx := sindx + 1; for i in -1 downto VALUE'low loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; return s; end function to_string; function to_hstring (value : UNRESOLVED_float) return STRING is variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0); begin floop : for i in slv'range loop slv(i) := to_X01Z (value(i + value'low)); end loop floop; return to_hstring (slv); end function to_hstring; function to_ostring (value : UNRESOLVED_float) return STRING is variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0); begin floop : for i in slv'range loop slv(i) := to_X01Z (value(i + value'low)); end loop floop; return to_ostring (slv); end function to_ostring; function from_string ( bstring : STRING; -- binary string constant exponent_width : NATURAL := float_exponent_width; constant fraction_width : NATURAL := float_fraction_width) return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable L : LINE; variable good : BOOLEAN; begin L := new STRING'(bstring); READ (L, result, good); deallocate (L); assert (good) report FLOAT_GENERIC_PKG'instance_name & "from_string: Bad string " & bstring severity error; return result; end function from_string; function from_ostring ( ostring : STRING; -- Octal string constant exponent_width : NATURAL := float_exponent_width; constant fraction_width : NATURAL := float_fraction_width) return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable L : LINE; variable good : BOOLEAN; begin L := new STRING'(ostring); OREAD (L, result, good); deallocate (L); assert (good) report FLOAT_GENERIC_PKG'instance_name & "from_ostring: Bad string " & ostring severity error; return result; end function from_ostring; function from_hstring ( hstring : STRING; -- hex string constant exponent_width : NATURAL := float_exponent_width; constant fraction_width : NATURAL := float_fraction_width) return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable L : LINE; variable good : BOOLEAN; begin L := new STRING'(hstring); HREAD (L, result, good); deallocate (L); assert (good) report FLOAT_GENERIC_PKG'instance_name & "from_hstring: Bad string " & hstring severity error; return result; end function from_hstring; function from_string ( bstring : STRING; -- binary string size_res : UNRESOLVED_float) -- used for sizing only return UNRESOLVED_float is begin return from_string (bstring => bstring, exponent_width => size_res'high, fraction_width => -size_res'low); end function from_string; function from_ostring ( ostring : STRING; -- Octal string size_res : UNRESOLVED_float) -- used for sizing only return UNRESOLVED_float is begin return from_ostring (ostring => ostring, exponent_width => size_res'high, fraction_width => -size_res'low); end function from_ostring; function from_hstring ( hstring : STRING; -- hex string size_res : UNRESOLVED_float) -- used for sizing only return UNRESOLVED_float is begin return from_hstring (hstring => hstring, exponent_width => size_res'high, fraction_width => -size_res'low); end function from_hstring; end package body float_generic_pkg;
-- -------------------------------------------------------------------- -- -- Copyright © 2008 by IEEE. All rights reserved. -- -- This source file is an essential part of IEEE Std 1076-2008, -- IEEE Standard VHDL Language Reference Manual. This source file may not be -- copied, sold, or included with software that is sold without written -- permission from the IEEE Standards Department. This source file may be -- copied for individual use between licensed users. This source file is -- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR -- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE -- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify -- and hold IEEE harmless from any damages or liability arising out of the -- use thereof. -- -- Title : Floating-point package (Generic package body) -- : -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: Accellera VHDL-TC and IEEE P1076 Working Group -- : -- Purpose : This packages defines basic binary floating point -- : arithmetic functions -- : -- Note : This package may be modified to include additional data -- : required by tools, but it must in no way change the -- : external interfaces or simulation behavior of the -- : description. It is permissible to add comments and/or -- : attributes to the package declarations, but not to change -- : or delete any original lines of the package declaration. -- : The package body may be changed only in accordance with -- : the terms of Clause 16 of this standard. -- : -- -------------------------------------------------------------------- -- $Revision: 1220 $ -- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ -- -------------------------------------------------------------------- package body float_generic_pkg is -- Author David Bishop ([email protected]) ----------------------------------------------------------------------------- -- type declarations ----------------------------------------------------------------------------- -- This deferred constant will tell you if the package body is synthesizable -- or implemented as real numbers, set to "true" if synthesizable. constant fphdlsynth_or_real : BOOLEAN := true; -- deferred constant -- types of boundary conditions type boundary_type is (normal, infinity, zero, denormal); -- null range array constant constant NAFP : UNRESOLVED_float (0 downto 1) := (others => '0'); constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0'); -- Special version of "minimum" to do some boundary checking function mine (L, R : INTEGER) return INTEGER is begin -- function minimum if (L = INTEGER'low or R = INTEGER'low) then report float_generic_pkg'instance_name & " Unbounded number passed, was a literal used?" severity error; return 0; end if; return minimum (L, R); end function mine; -- Generates the base number for the exponent normalization offset. function gen_expon_base ( constant exponent_width : NATURAL) return SIGNED is variable result : SIGNED (exponent_width-1 downto 0); begin result := (others => '1'); result (exponent_width-1) := '0'; return result; end function gen_expon_base; -- Integer version of the "log2" command (contributed by Peter Ashenden) function log2 (A : NATURAL) return NATURAL is variable quotient : NATURAL; variable result : NATURAL := 0; begin quotient := A / 2; while quotient > 0 loop quotient := quotient / 2; result := result + 1; end loop; return result; end function log2; -- Function similar to the ILOGB function in MATH_REAL function log2 (A : REAL) return INTEGER is variable Y : REAL; variable N : INTEGER := 0; begin if (A = 1.0 or A = 0.0) then return 0; end if; Y := A; if(A > 1.0) then while Y >= 2.0 loop Y := Y / 2.0; N := N + 1; end loop; return N; end if; -- O < Y < 1 while Y < 1.0 loop Y := Y * 2.0; N := N - 1; end loop; return N; end function log2; -- purpose: Test the boundary conditions of a Real number procedure test_boundary ( arg : in REAL; -- Input, converted to real constant fraction_width : in NATURAL; -- length of FP output fraction constant exponent_width : in NATURAL; -- length of FP exponent constant denormalize : in BOOLEAN := true; -- Use IEEE extended FP variable btype : out boundary_type; variable log2i : out INTEGER ) is constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset constant exp_min : SIGNED (12 downto 0) := -(resize(expon_base, 13)) + 1; -- Minimum normal exponent constant exp_ext_min : SIGNED (12 downto 0) := exp_min - fraction_width; -- Minimum for denormal exponent variable log2arg : INTEGER; -- log2 of argument begin -- function test_boundary -- Check to see if the exponent is big enough -- Note that the argument is always an absolute value at this point. log2arg := log2(arg); if arg = 0.0 then btype := zero; elsif exponent_width > 11 then -- Exponent for Real is 11 (64 bit) btype := normal; else if log2arg < to_integer(exp_min) then if denormalize then if log2arg < to_integer(exp_ext_min) then btype := zero; else btype := denormal; end if; else if log2arg < to_integer(exp_min)-1 then btype := zero; else btype := normal; -- Can still represent this number end if; end if; elsif exponent_width < 11 then if log2arg > to_integer(expon_base)+1 then btype := infinity; else btype := normal; end if; else btype := normal; end if; end if; log2i := log2arg; end procedure test_boundary; -- purpose: Rounds depending on the state of the "round_style" -- Logic taken from -- "What Every Computer Scientist Should Know About Floating Point Arithmetic" -- by David Goldberg (1991) function check_round ( fract_in : STD_ULOGIC; -- input fraction sign : STD_ULOGIC; -- sign bit remainder : UNSIGNED; -- remainder to round from sticky : STD_ULOGIC := '0'; -- Sticky bit constant round_style : round_type) -- rounding type return BOOLEAN is variable result : BOOLEAN; variable or_reduced : STD_ULOGIC; begin -- function check_round result := false; if (remainder'length > 0) then -- if remainder in a null array or_reduced := or (remainder & sticky); rounding_case : case round_style is when round_nearest => -- Round Nearest, default mode if remainder(remainder'high) = '1' then -- round if (remainder'length > 1) then if ((or (remainder(remainder'high-1 downto remainder'low)) = '1' or sticky = '1') or fract_in = '1') then -- Make the bottom bit zero if possible if we are at 1/2 result := true; end if; else result := (fract_in = '1' or sticky = '1'); end if; end if; when round_inf => -- round up if positive, else truncate. if or_reduced = '1' and sign = '0' then result := true; end if; when round_neginf => -- round down if negative, else truncate. if or_reduced = '1' and sign = '1' then result := true; end if; when round_zero => -- round toward 0 Truncate null; end case rounding_case; end if; return result; end function check_round; -- purpose: Rounds depending on the state of the "round_style" -- unsigned version procedure fp_round ( fract_in : in UNSIGNED; -- input fraction expon_in : in SIGNED; -- input exponent fract_out : out UNSIGNED; -- output fraction expon_out : out SIGNED) is -- output exponent begin -- procedure fp_round if and (fract_in) = '1' then -- Fraction is all "1" expon_out := expon_in + 1; fract_out := to_unsigned(0, fract_out'high+1); else expon_out := expon_in; fract_out := fract_in + 1; end if; end procedure fp_round; -- This version of break_number doesn't call "classfp" procedure break_number ( -- internal version arg : in UNRESOLVED_float; fptyp : in valid_fpstate; denormalize : in BOOLEAN := true; fract : out UNSIGNED; expon : out SIGNED) is constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction constant exponent_width : NATURAL := arg'high; -- length of FP output exponent constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable exp : SIGNED (expon'range); begin fract (fraction_width-1 downto 0) := UNSIGNED (to_slv(arg(-1 downto -fraction_width))); breakcase : case fptyp is when pos_zero \| neg_zero => fract (fraction_width) := '0'; exp := -expon_base; when pos_denormal \| neg_denormal => if denormalize then exp := -expon_base; fract (fraction_width) := '0'; else exp := -expon_base - 1; fract (fraction_width) := '1'; end if; when pos_normal \| neg_normal \| pos_inf \| neg_inf => fract (fraction_width) := '1'; exp := SIGNED(arg(exponent_width-1 downto 0)); exp (exponent_width-1) := not exp(exponent_width-1); when others => assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "BREAK_NUMBER: " & "Meta state detected in fp_break_number process" severity warning; -- complete the case, if a NAN goes in, a NAN comes out. exp := (others => '1'); fract (fraction_width) := '1'; end case breakcase; expon := exp; end procedure break_number; -- purpose: floating point to UNSIGNED -- Used by to_integer, to_unsigned, and to_signed functions procedure float_to_unsigned ( arg : in UNRESOLVED_float; -- floating point input variable sign : out STD_ULOGIC; -- sign of output variable frac : out UNSIGNED; -- unsigned biased output constant denormalize : in BOOLEAN; -- turn on denormalization constant bias : in NATURAL; -- bias for fixed point constant round_style : in round_type) is -- rounding method constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent variable fract : UNSIGNED (frac'range); -- internal version of frac variable isign : STD_ULOGIC; -- internal version of sign variable exp : INTEGER; -- Exponent variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp -- Base to divide fraction by variable frac_shift : UNSIGNED (frac'high+3 downto 0); -- Fraction shifted variable shift : INTEGER; variable remainder : UNSIGNED (2 downto 0); variable round : STD_ULOGIC; -- round BIT begin isign := to_x01(arg(arg'high)); -- exponent /= '0', normal floating point expon := to_01(SIGNED(arg (exponent_width-1 downto 0)), 'X'); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (expon); -- Figure out the fraction fract := (others => '0'); -- fill with zero fract (fract'high) := '1'; -- Add the "1.0". shift := (fract'high-1) - exp; if fraction_width > fract'high then -- Can only use size-2 bits fract (fract'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto -fract'high))); else -- can use all bits fract (fract'high-1 downto fract'high-fraction_width) := UNSIGNED (to_slv (arg(-1 downto -fraction_width))); end if; frac_shift := fract & "000"; if shift < 0 then -- Overflow fract := (others => '1'); else frac_shift := shift_right (frac_shift, shift); fract := frac_shift (frac_shift'high downto 3); remainder := frac_shift (2 downto 0); -- round (round_zero will bypass this and truncate) case round_style is when round_nearest => round := remainder(2) and (fract (0) or (or (remainder (1 downto 0)))); when round_inf => round := remainder(2) and not isign; when round_neginf => round := remainder(2) and isign; when others => round := '0'; end case; if round = '1' then fract := fract + 1; end if; end if; frac := fract; sign := isign; end procedure float_to_unsigned; -- purpose: returns a part of a vector, this function is here because -- or (fractr (to_integer(shiftx) downto 0)); -- can't be synthesized in some synthesis tools. function smallfract ( arg : UNSIGNED; shift : NATURAL) return STD_ULOGIC is variable orx : STD_ULOGIC; begin orx := arg(shift); for i in arg'range loop if i < shift then orx := arg(i) or orx; end if; end loop; return orx; end function smallfract; --------------------------------------------------------------------------- -- Visible functions --------------------------------------------------------------------------- -- purpose: converts the negative index to a positive one -- negative indices are illegal in 1164 and 1076.3 function to_sulv ( arg : UNRESOLVED_float) -- fp vector return STD_ULOGIC_VECTOR is subtype result_subtype is STD_ULOGIC_VECTOR (arg'length-1 downto 0); variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0); begin -- function to_std_ulogic_vector if arg'length < 1 then return NSLV; end if; result := result_subtype (arg); return result; end function to_sulv; -- Converts an fp into an SULV function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR is begin return to_sulv (arg); end function to_slv; -- purpose: normalizes a floating point number -- This version assumes an "unsigned" input with function normalize ( fract : UNRESOLVED_UNSIGNED; -- fraction, unnormalized expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1 sign : STD_ULOGIC; -- sign BIT sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is variable sfract : UNSIGNED (fract'high downto 0); -- shifted fraction variable rfract : UNSIGNED (fraction_width-1 downto 0); -- fraction variable exp : SIGNED (exponent_width+1 downto 0); -- exponent variable rexp : SIGNED (exponent_width+1 downto 0); -- result exponent variable rexpon : UNSIGNED (exponent_width-1 downto 0); -- exponent variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result variable shiftr : INTEGER; -- shift amount variable stickyx : STD_ULOGIC; -- version of sticky constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable round, zerores, infres : BOOLEAN; begin -- function normalize zerores := false; infres := false; round := false; shiftr := find_leftmost (to_01(fract), '1') -- Find the first "1" - fraction_width - nguard; -- subtract the length we want exp := resize (expon, exp'length) + shiftr; if (or (fract) = '0') then -- Zero zerores := true; elsif ((exp <= -resize(expon_base, exp'length)-1) and denormalize) or ((exp < -resize(expon_base, exp'length)-1) and not denormalize) then if (exp >= -resize(expon_base, exp'length)-fraction_width-1) and denormalize then exp := -resize(expon_base, exp'length)-1; shiftr := -to_integer (expon + expon_base); -- new shift else -- return zero zerores := true; end if; elsif (exp > expon_base-1) then -- infinity infres := true; end if; if zerores then result := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); elsif infres then result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else sfract := fract srl shiftr; -- shift if shiftr > 0 then -- stickyx := sticky or (or (fract (shiftr-1 downto 0))); stickyx := sticky or smallfract (fract, shiftr-1); else stickyx := sticky; end if; if nguard > 0 then round := check_round ( fract_in => sfract (nguard), sign => sign, remainder => sfract(nguard-1 downto 0), sticky => stickyx, round_style => round_style); end if; if round then fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard), expon_in => exp(rexp'range), fract_out => rfract, expon_out => rexp); else rfract := sfract (fraction_width-1+nguard downto nguard); rexp := exp(rexp'range); end if; -- result rexpon := UNSIGNED (rexp(exponent_width-1 downto 0)); rexpon (exponent_width-1) := not rexpon(exponent_width-1); result (rexpon'range) := UNRESOLVED_float(rexpon); result (-1 downto -fraction_width) := UNRESOLVED_float(rfract); end if; result (exponent_width) := sign; -- sign BIT return result; end function normalize; -- purpose: normalizes a floating point number -- This version assumes a "ufixed" input function normalize ( fract : UNRESOLVED_ufixed; -- unsigned fixed point expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1 sign : STD_ULOGIC; -- sign bit sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arguns : UNSIGNED (fract'high + fraction_width + nguard downto 0) := (others => '0'); begin -- function normalize arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) := UNSIGNED (to_slv (fract)); result := normalize (fract => arguns, expon => expon, sign => sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => nguard); return result; end function normalize; -- purpose: normalizes a floating point number -- This version assumes a "ufixed" input with a "size_res" input function normalize ( fract : UNRESOLVED_ufixed; -- unsigned fixed point expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1 sign : STD_ULOGIC; -- sign bit sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) size_res : UNRESOLVED_float; -- used for sizing only constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is constant fraction_width : NATURAL := -size_res'low; constant exponent_width : NATURAL := size_res'high; variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arguns : UNSIGNED (fract'high + fraction_width + nguard downto 0) := (others => '0'); begin -- function normalize arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) := UNSIGNED (to_slv (fract)); result := normalize (fract => arguns, expon => expon, sign => sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => nguard); return result; end function normalize; -- Regular "normalize" function with a "size_res" input. function normalize ( fract : UNRESOLVED_UNSIGNED; -- unsigned expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized sign : STD_ULOGIC; -- sign bit sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) size_res : UNRESOLVED_float; -- used for sizing only constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is begin return normalize (fract => fract, expon => expon, sign => sign, sticky => sticky, fraction_width => -size_res'low, exponent_width => size_res'high, round_style => round_style, denormalize => denormalize, nguard => nguard); end function normalize; -- Returns the class which X falls into function Classfp ( x : UNRESOLVED_float; -- floating point input check_error : BOOLEAN := float_check_error) -- check for errors return valid_fpstate is constant fraction_width : INTEGER := -mine(x'low, x'low); -- length of FP output fraction constant exponent_width : INTEGER := x'high; -- length of FP output exponent variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- classfp if (arg'length < 1 or fraction_width < 3 or exponent_width < 3 or x'left < x'right) then report FLOAT_GENERIC_PKG'instance_name & "CLASSFP: " & "Floating point number detected with a bad range" severity error; return isx; end if; -- Check for "X". arg := to_01 (x, 'X'); if (arg(0) = 'X') then return isx; -- If there is an X in the number -- Special cases, check for illegal number elsif check_error and (and (STD_ULOGIC_VECTOR (arg (exponent_width-1 downto 0))) = '1') then -- Exponent is all "1". if or (to_slv (arg (-1 downto -fraction_width))) /= '0' then -- Fraction must be all "0" or this is not a number. if (arg(-1) = '1') then -- From "W. Khan - IEEE standard return nan; -- 754 binary FP Signaling nan (Not a number) else return quiet_nan; end if; -- Check for infinity elsif arg(exponent_width) = '0' then return pos_inf; -- Positive infinity else return neg_inf; -- Negative infinity end if; -- check for "0" elsif or (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0))) = '0' then -- Exponent is all "0" if or (to_slv (arg (-1 downto -fraction_width))) = '0' then -- Fraction is all "0" if arg(exponent_width) = '0' then return pos_zero; -- Zero else return neg_zero; end if; else if arg(exponent_width) = '0' then return pos_denormal; -- Denormal number (ieee extended fp) else return neg_denormal; end if; end if; else if arg(exponent_width) = '0' then return pos_normal; -- Normal FP number else return neg_normal; end if; end if; end function Classfp; procedure break_number ( arg : in UNRESOLVED_float; denormalize : in BOOLEAN := float_denormalize; check_error : in BOOLEAN := float_check_error; fract : out UNRESOLVED_UNSIGNED; expon : out UNRESOLVED_SIGNED; sign : out STD_ULOGIC) is constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction variable fptyp : valid_fpstate; begin fptyp := Classfp (arg, check_error); sign := to_x01(arg(arg'high)); break_number ( arg => arg, fptyp => fptyp, denormalize => denormalize, fract => fract, expon => expon); end procedure break_number; procedure break_number ( arg : in UNRESOLVED_float; denormalize : in BOOLEAN := float_denormalize; check_error : in BOOLEAN := float_check_error; fract : out UNRESOLVED_ufixed; -- 1 downto -fraction_width expon : out UNRESOLVED_SIGNED; -- exponent_width-1 downto 0 sign : out STD_ULOGIC) is constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction variable fptyp : valid_fpstate; variable ufract : UNSIGNED (fraction_width downto 0); -- unsigned fraction begin fptyp := Classfp (arg, check_error); sign := to_x01(arg(arg'high)); break_number ( arg => arg, fptyp => fptyp, denormalize => denormalize, fract => ufract, expon => expon); fract (0 downto -fraction_width) := ufixed (ufract); end procedure break_number; -- Arithmetic functions function "abs" ( arg : UNRESOLVED_float) -- floating point input return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); -- result begin if (arg'length > 0) then result := to_01 (arg, 'X'); result (arg'high) := '0'; -- set the sign bit to positive return result; else return NAFP; end if; end function "abs"; -- IEEE 754 "negative" function function "-" ( arg : UNRESOLVED_float) -- floating point input return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); -- result begin if (arg'length > 0) then result := to_01 (arg, 'X'); result (arg'high) := not result (arg'high); -- invert sign bit return result; else return NAFP; end if; end function "-"; -- Addition, adds two floating point numbers function add ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant addguard : NATURAL := guard; -- add one guard bit variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable fractl, fractr : UNSIGNED (fraction_width+1+addguard downto 0); -- fractions variable fractc, fracts : UNSIGNED (fractl'range); -- constant and shifted variables variable urfract, ulfract : UNSIGNED (fraction_width downto 0); variable ufract : UNSIGNED (fraction_width+1+addguard downto 0); variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width downto 0); -- result exponent variable shiftx : SIGNED (exponent_width downto 0); -- shift fractions variable sign : STD_ULOGIC; -- sign of the output variable leftright : BOOLEAN; -- left or right used variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); variable sticky : STD_ULOGIC; -- Holds precision for rounding begin -- addition if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan) -- Return quiet NAN, IEEE754-1985-7.1,1 or (lfptype = pos_inf and rfptype = neg_inf) or (lfptype = neg_inf and rfptype = pos_inf) then -- Return quiet NAN, IEEE754-1985-7.1,2 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = pos_inf or rfptype = pos_inf) then -- x + inf = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = neg_inf or rfptype = neg_inf) then -- x - inf = -inf fpresult := neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = neg_zero and rfptype = neg_zero) then -- -0 + -0 = -0 fpresult := neg_zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); fractl := (others => '0'); fractl (fraction_width+addguard downto addguard) := ulfract; break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); fractr := (others => '0'); fractr (fraction_width+addguard downto addguard) := urfract; shiftx := (exponl(exponent_width-1) & exponl) - exponr; if shiftx < -fractl'high then rexpon := exponr(exponent_width-1) & exponr; fractc := fractr; fracts := (others => '0'); -- add zero leftright := false; sticky := or (fractl); elsif shiftx < 0 then shiftx := - shiftx; fracts := shift_right (fractl, to_integer(shiftx)); fractc := fractr; rexpon := exponr(exponent_width-1) & exponr; leftright := false; -- sticky := or (fractl (to_integer(shiftx) downto 0)); sticky := smallfract (fractl, to_integer(shiftx)); elsif shiftx = 0 then rexpon := exponl(exponent_width-1) & exponl; sticky := '0'; if fractr > fractl then fractc := fractr; fracts := fractl; leftright := false; else fractc := fractl; fracts := fractr; leftright := true; end if; elsif shiftx > fractr'high then rexpon := exponl(exponent_width-1) & exponl; fracts := (others => '0'); -- add zero fractc := fractl; leftright := true; sticky := or (fractr); elsif shiftx > 0 then fracts := shift_right (fractr, to_integer(shiftx)); fractc := fractl; rexpon := exponl(exponent_width-1) & exponl; leftright := true; -- sticky := or (fractr (to_integer(shiftx) downto 0)); sticky := smallfract (fractr, to_integer(shiftx)); end if; -- add fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB if l(l'high) = r(r'high) then ufract := fractc + fracts; sign := l(l'high); else -- signs are different ufract := fractc - fracts; -- always positive result if leftright then -- Figure out which sign to use sign := l(l'high); else sign := r(r'high); end if; end if; if or (ufract) = '0' then sign := '0'; -- IEEE 854, 6.3, paragraph 2. end if; -- normalize fpresult := normalize (fract => ufract, expon => rexpon, sign => sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => addguard); end if; return fpresult; end function add; -- Subtraction, Calls "add". function subtract ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable negr : UNRESOLVED_float (r'range); -- negative version of r begin negr := -r; -- r := -r return add (l => l, r => negr, round_style => round_style, guard => guard, check_error => check_error, denormalize => denormalize); end function subtract; -- Floating point multiply function multiply ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant multguard : NATURAL := guard; -- guard bits variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions variable rfract : UNSIGNED ((2(fraction_width))+1 downto 0); -- result fraction variable sfract : UNSIGNED (fraction_width+1+multguard downto 0); -- result fraction variable shifty : INTEGER; -- denormal shift variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent variable fp_sign : STD_ULOGIC; -- sign of result variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); variable sticky : STD_ULOGIC; -- Holds precision for rounding begin -- multiply if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif ((lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan)) then -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (((lfptype = pos_inf or lfptype = neg_inf) and (rfptype = pos_zero or rfptype = neg_zero)) or ((rfptype = pos_inf or rfptype = neg_inf) and (lfptype = pos_zero or lfptype = neg_zero))) then -- 0 inf -- Return quiet NAN, IEEE754-1985-7.1,3 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = pos_inf or rfptype = pos_inf or lfptype = neg_inf or rfptype = neg_inf) then -- x * inf = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); -- figure out the sign fp_sign := l(l'high) xor r(r'high); -- figure out the sign fpresult (exponent_width) := fp_sign; else fp_sign := l(l'high) xor r(r'high); -- figure out the sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => fractl, expon => exponl); break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => fractr, expon => exponr); if (rfptype = pos_denormal or rfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractr, '1'); fractr := shift_left (fractr, shifty); elsif (lfptype = pos_denormal or lfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractl, '1'); fractl := shift_left (fractl, shifty); else shifty := 0; -- Note that a denormal number * a denormal number is always zero. end if; -- multiply -- add the exponents rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1; rfract := fractl * fractr; -- Multiply the fraction sfract := rfract (rfract'high downto rfract'high - (fraction_width+1+multguard)); sticky := or (rfract (rfract'high-(fraction_width+1+multguard) downto 0)); -- normalize fpresult := normalize (fract => sfract, expon => rexpon, sign => fp_sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => multguard); end if; return fpresult; end function multiply; function short_divide ( lx, rx : UNSIGNED) return UNSIGNED is -- This is a special divider for the floating point routines. -- For a true unsigned divider, "stages" needs to = lx'high constant stages : INTEGER := lx'high - rx'high; -- number of stages variable partial : UNSIGNED (lx'range); variable q : UNSIGNED (stages downto 0); variable partial_argl : SIGNED (rx'high + 2 downto 0); variable partial_arg : SIGNED (rx'high + 2 downto 0); begin partial := lx; for i in stages downto 0 loop partial_argl := resize ("0" & SIGNED (partial(lx'high downto i)), partial_argl'length); partial_arg := partial_argl - SIGNED ("0" & rx); if (partial_arg (partial_arg'high) = '1') then -- negative q(i) := '0'; else q(i) := '1'; partial (lx'high+i-stages downto lx'high+i-stages-rx'high) := UNSIGNED (partial_arg(rx'range)); end if; end loop; -- to make the output look like that of the unsigned IEEE divide. return resize (q, lx'length); end function short_divide; -- 1/X function. Needed for algorithm development. function reciprocal ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : NATURAL := arg'high; -- length of FP output exponent constant divguard : NATURAL := guard; -- guard bits function onedivy ( arg : UNSIGNED) return UNSIGNED is variable q : UNSIGNED((2arg'high)+1 downto 0); variable one : UNSIGNED (q'range); begin one := (others => '0'); one(one'high) := '1'; q := short_divide (one, arg); -- Unsigned divide return resize (q, arg'length+1); end function onedivy; variable fptype : valid_fpstate; variable expon : SIGNED (exponent_width-1 downto 0); -- exponents variable denorm_offset : NATURAL range 0 to 2; variable fract : UNSIGNED (fraction_width downto 0); variable fractg : UNSIGNED (fraction_width+divguard downto 0); variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- reciprocal fptype := classfp(arg, check_error); classcase : case fptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => -- 1/inf, return 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); when neg_zero \| pos_zero => -- 1/0 report FLOAT_GENERIC_PKG'instance_name & "RECIPROCAL: Floating Point divide by zero" severity error; fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); when others => if (fptype = pos_denormal or fptype = neg_denormal) and ((arg (-1) or arg(-2)) /= '1') then -- 1/denormal = infinity, with the exception of 2-expon_base fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fpresult (exponent_width) := to_x01 (arg (exponent_width)); else break_number ( arg => arg, fptyp => fptype, denormalize => denormalize, fract => fract, expon => expon); fractg := (others => '0'); if (fptype = pos_denormal or fptype = neg_denormal) then -- The reciprocal of a denormal number is typically zero, -- except for two special cases which are trapped here. if (to_x01(arg (-1)) = '1') then fractg (fractg'high downto divguard+1) := fract (fract'high-1 downto 0); -- Shift to not denormal denorm_offset := 1; -- add 1 to exponent compensate else -- arg(-2) = '1' fractg (fractg'high downto divguard+2) := fract (fract'high-2 downto 0); -- Shift to not denormal denorm_offset := 2; -- add 2 to exponent compensate end if; else fractg (fractg'high downto divguard) := fract; denorm_offset := 0; end if; expon := - expon - 3 + denorm_offset; sfract := onedivy (fractg); -- normalize fpresult := normalize (fract => sfract, expon => expon, sign => arg(exponent_width), sticky => '1', fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => divguard); end if; end case classcase; return fpresult; end function reciprocal; -- floating point division function divide ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant divguard : NATURAL := guard; -- division guard bits variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable ulfract, urfract : UNSIGNED (fraction_width downto 0); variable fractl : UNSIGNED ((2(fraction_width+divguard)+1) downto 0); -- left variable fractr : UNSIGNED (fraction_width+divguard downto 0); -- right variable rfract : UNSIGNED (fractl'range); -- result fraction variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent variable fp_sign, sticky : STD_ULOGIC; -- sign of result variable shifty, shiftx : INTEGER; -- denormal number shift variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- divide if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; classcase : case rfptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => if lfptype = pos_inf or lfptype = neg_inf -- inf / inf or lfptype = quiet_nan or lfptype = nan then -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else -- x / inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when pos_zero \| neg_zero => if lfptype = pos_zero or lfptype = neg_zero -- 0 / 0 or lfptype = quiet_nan or lfptype = nan then -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else report float_generic_pkg'instance_name & "DIVIDE: Floating Point divide by zero" severity error; -- Infinity, define in 754-1985-7.2 fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when others => classcase2 : case lfptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => -- inf / x = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult(exponent_width) := fp_sign; when pos_zero \| neg_zero => -- 0 / X = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult(exponent_width) := fp_sign; when others => fp_sign := l(l'high) xor r(r'high); -- sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); -- right side break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); -- Compute the exponent rexpon := resize (exponl, rexpon'length) - exponr - 2; if (rfptype = pos_denormal or rfptype = neg_denormal) then -- Do the shifting here not after. That way we have a smaller -- shifter, and need a smaller divider, because the top -- bit in the divisor will always be a "1". shifty := fraction_width - find_leftmost(urfract, '1'); urfract := shift_left (urfract, shifty); rexpon := rexpon + shifty; end if; fractr := (others => '0'); fractr (fraction_width+divguard downto divguard) := urfract; if (lfptype = pos_denormal or lfptype = neg_denormal) then shiftx := fraction_width - find_leftmost(ulfract, '1'); ulfract := shift_left (ulfract, shiftx); rexpon := rexpon - shiftx; end if; fractl := (others => '0'); fractl (fractl'high downto fractl'high-fraction_width) := ulfract; -- divide rfract := short_divide (fractl, fractr); -- unsigned divide sfract := rfract (sfract'range); -- lower bits sticky := '1'; -- normalize fpresult := normalize (fract => sfract, expon => rexpon, sign => fp_sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => divguard); end case classcase2; end case classcase; return fpresult; end function divide; -- division by a power of 2 function dividebyp2 ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable ulfract, urfract : UNSIGNED (fraction_width downto 0); variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED(exponent_width downto 0); -- result exponent variable fp_sign : STD_ULOGIC; -- sign of result variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- divisionbyp2 if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; classcase : case rfptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => if lfptype = pos_inf or lfptype = neg_inf then -- inf / inf -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else -- x / inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when pos_zero \| neg_zero => if lfptype = pos_zero or lfptype = neg_zero then -- 0 / 0 -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else report FLOAT_GENERIC_PKG'instance_name & "DIVIDEBYP2: Floating Point divide by zero" severity error; -- Infinity, define in 754-1985-7.2 fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when others => classcase2 : case lfptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf \| neg_inf => -- inf / x = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (exponent_width) := fp_sign; -- sign when pos_zero \| neg_zero => -- 0 / X = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (exponent_width) := fp_sign; -- sign when others => fp_sign := l(l'high) xor r(r'high); -- sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); -- right side break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); assert (or (urfract (fraction_width-1 downto 0)) = '0') report FLOAT_GENERIC_PKG'instance_name & "DIVIDEBYP2: " & "Dividebyp2 called with a non power of two divisor" severity error; rexpon := (exponl(exponl'high)&exponl) - (exponr(exponr'high)&exponr) - 1; -- normalize fpresult := normalize (fract => ulfract, expon => rexpon, sign => fp_sign, sticky => '1', fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => 0); end case classcase2; end case classcase; return fpresult; end function dividebyp2; -- Multiply accumulate result = lr + c function mac ( l, r, c : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine (mine(l'low, r'low), c'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum (maximum(l'high, r'high), c'high); -- length of FP output exponent variable lfptype, rfptype, cfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions variable fractx : UNSIGNED (fraction_width+guard downto 0); variable fractc, fracts : UNSIGNED (fraction_width+1+guard downto 0); variable rfract : UNSIGNED ((2(fraction_width))+1 downto 0); -- result fraction variable sfract, ufract : UNSIGNED (fraction_width+1+guard downto 0); -- result fraction variable exponl, exponr, exponc : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon, rexpon2 : SIGNED (exponent_width+1 downto 0); -- result exponent variable shifty : INTEGER; -- denormal shift variable shiftx : SIGNED (rexpon'range); -- shift fractions variable fp_sign : STD_ULOGIC; -- sign of result variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); variable cresize : UNRESOLVED_float (exponent_width downto -fraction_width - guard); variable leftright : BOOLEAN; -- left or right used variable sticky : STD_ULOGIC; -- Holds precision for rounding begin -- multiply if (fraction_width = 0 or l'length < 7 or r'length < 7 or c'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); cfptype := classfp (c, check_error); end if; if (lfptype = isx or rfptype = isx or cfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan or cfptype = nan or cfptype = quiet_nan) then -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (((lfptype = pos_inf or lfptype = neg_inf) and (rfptype = pos_zero or rfptype = neg_zero)) or ((rfptype = pos_inf or rfptype = neg_inf) and (lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf -- Return quiet NAN, IEEE754-1985-7.1,3 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = pos_inf or rfptype = pos_inf or lfptype = neg_inf or rfptype = neg_inf -- x * inf = inf or cfptype = neg_inf or cfptype = pos_inf) then -- x + inf = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); -- figure out the sign fpresult (exponent_width) := l(l'high) xor r(r'high); else fp_sign := l(l'high) xor r(r'high); -- figure out the sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked cresize := resize (arg => to_x01(c), exponent_width => exponent_width, fraction_width => -cresize'low, denormalize_in => denormalize, denormalize => denormalize); cfptype := classfp (cresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => fractl, expon => exponl); break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => fractr, expon => exponr); break_number ( arg => cresize, fptyp => cfptype, denormalize => denormalize, fract => fractx, expon => exponc); if (rfptype = pos_denormal or rfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractr, '1'); fractr := shift_left (fractr, shifty); elsif (lfptype = pos_denormal or lfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractl, '1'); fractl := shift_left (fractl, shifty); else shifty := 0; -- Note that a denormal number * a denormal number is always zero. end if; -- multiply rfract := fractl * fractr; -- Multiply the fraction -- add the exponents rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1; shiftx := rexpon - exponc; if shiftx < -fractl'high then rexpon2 := resize (exponc, rexpon2'length); fractc := "0" & fractx; fracts := (others => '0'); sticky := or (rfract); elsif shiftx < 0 then shiftx := - shiftx; fracts := shift_right (rfract (rfract'high downto rfract'high - fracts'length+1), to_integer(shiftx)); fractc := "0" & fractx; rexpon2 := resize (exponc, rexpon2'length); leftright := false; sticky := or (rfract (to_integer(shiftx)+rfract'high - fracts'length downto 0)); elsif shiftx = 0 then rexpon2 := resize (exponc, rexpon2'length); sticky := or (rfract (rfract'high - fractc'length downto 0)); if rfract (rfract'high downto rfract'high - fractc'length+1) > fractx then fractc := "0" & fractx; fracts := rfract (rfract'high downto rfract'high - fracts'length+1); leftright := false; else fractc := rfract (rfract'high downto rfract'high - fractc'length+1); fracts := "0" & fractx; leftright := true; end if; elsif shiftx > fractx'high then rexpon2 := rexpon; fracts := (others => '0'); fractc := rfract (rfract'high downto rfract'high - fractc'length+1); leftright := true; sticky := or (fractx & rfract (rfract'high - fractc'length downto 0)); else -- fractx'high > shiftx > 0 rexpon2 := rexpon; fracts := "0" & shift_right (fractx, to_integer (shiftx)); fractc := rfract (rfract'high downto rfract'high - fractc'length+1); leftright := true; sticky := or (fractx (to_integer (shiftx) downto 0) & rfract (rfract'high - fractc'length downto 0)); end if; fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB if fp_sign = to_X01(c(c'high)) then ufract := fractc + fracts; fp_sign := fp_sign; else -- signs are different ufract := fractc - fracts; -- always positive result if leftright then -- Figure out which sign to use fp_sign := fp_sign; else fp_sign := c(c'high); end if; end if; -- normalize fpresult := normalize (fract => ufract, expon => rexpon2, sign => fp_sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => guard); end if; return fpresult; end function mac; -- "rem" function function remainder ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant divguard : NATURAL := guard; -- division guard bits variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable ulfract, urfract : UNSIGNED (fraction_width downto 0); variable fractr, fractl : UNSIGNED (fraction_width+divguard downto 0); -- right variable rfract : UNSIGNED (fractr'range); -- result fraction variable sfract : UNSIGNED (fraction_width+divguard downto 0); -- result fraction variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width downto 0); -- result exponent variable fp_sign : STD_ULOGIC; -- sign of result variable shifty : INTEGER; -- denormal number shift variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- remainder if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan) or (rfptype = nan or rfptype = quiet_nan) -- Return quiet NAN, IEEE754-1985-7.1,1 or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x -- Return quiet NAN, IEEE754-1985-7.1,5 or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0 -- Return quiet NAN, IEEE754-1985-7.1,5 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (abs(l) < abs(r)) then fpresult := l; else fp_sign := to_X01(l(l'high)); -- sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked fractl := (others => '0'); break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); fractl (fraction_width+divguard downto divguard) := ulfract; -- right side fractr := (others => '0'); break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); fractr (fraction_width+divguard downto divguard) := urfract; rexpon := (exponr(exponr'high)&exponr); shifty := to_integer(exponl - rexpon); if (shifty > 0) then fractr := shift_right (fractr, shifty); rexpon := rexpon + shifty; end if; if (fractr /= 0) then -- rem rfract := fractl rem fractr; -- unsigned rem sfract := rfract (sfract'range); -- lower bits -- normalize fpresult := normalize (fract => sfract, expon => rexpon, sign => fp_sign, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => divguard); else -- If we shift "fractr" so far that it becomes zero, return zero. fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); end if; end if; return fpresult; end function remainder; -- "mod" function function modulo ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := - mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable remres : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- remainder if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan) or (rfptype = nan or rfptype = quiet_nan) -- Return quiet NAN, IEEE754-1985-7.1,1 or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x -- Return quiet NAN, IEEE754-1985-7.1,5 or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0 -- Return quiet NAN, IEEE754-1985-7.1,5 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else remres := remainder (l => abs(l), r => abs(r), round_style => round_style, guard => guard, check_error => false, denormalize => denormalize); -- MOD is the same as REM, but you do something different with -- negative values if (is_negative (l)) then remres := - remres; end if; if (is_negative (l) = is_negative (r) or remres = 0) then fpresult := remres; else fpresult := add (l => remres, r => r, round_style => round_style, guard => guard, check_error => false, denormalize => denormalize); end if; end if; return fpresult; end function modulo; -- Square root of a floating point number. Done using Newton's Iteration. function sqrt ( arg : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; constant guard : NATURAL := float_guard_bits; constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_float is constant fraction_width : NATURAL := guard-arg'low; -- length of FP output fraction constant exponent_width : NATURAL := arg'high; -- length of FP output exponent variable sign : STD_ULOGIC; variable fpresult : float (arg'range); variable fptype : valid_fpstate; variable iexpon : SIGNED(exponent_width-1 downto 0); -- exponents variable expon : SIGNED(exponent_width downto 0); -- exponents variable ufact : ufixed (0 downto arg'low); variable fact : ufixed (2 downto -fraction_width); -- fraction variable resb : ufixed (fact'high+1 downto fact'low); begin -- square root fptype := Classfp (arg, check_error); classcase : case fptype is when isx => fpresult := (others => 'X'); when nan \| quiet_nan \| -- Return quiet NAN, IEEE754-1985-7.1,1 neg_normal \| neg_denormal \| neg_inf => -- sqrt (neg) -- Return quiet NAN, IEEE754-1985-7.1.6 fpresult := qnanfp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when pos_inf => -- Sqrt (inf), return infinity fpresult := pos_inffp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when pos_zero => -- return 0 fpresult := zerofp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when neg_zero => -- IEEE754-1985-6.3 return -0 fpresult := neg_zerofp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when others => break_number (arg => arg, denormalize => denormalize, check_error => false, fract => ufact, expon => iexpon, sign => sign); expon := resize (iexpon+1, expon'length); -- get exponent fact := resize (ufact, fact'high, fact'low); if (expon(0) = '1') then fact := fact sla 1; -- * 2.0 end if; expon := shift_right (expon, 1); -- exponent/2 -- Newton's iteration - root := (1 + arg) / 2 resb := (fact + 1) sra 1; for j in 0 to fraction_width/4 loop -- root := (root + (arg/root))/2 resb := resize (arg => (resb + (fact/resb)) sra 1, left_index => resb'high, right_index => resb'low, round_style => fixed_truncate, overflow_style => fixed_wrap); end loop; fpresult := normalize (fract => resb, expon => expon-1, sign => '0', exponent_width => arg'high, fraction_width => -arg'low, round_style => round_style, denormalize => denormalize, nguard => guard); end case classcase; return fpresult; end function sqrt; function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN is -- Technically -0 should return "false", but I'm leaving that case out. begin return (to_x01(arg(arg'high)) = '1'); end function Is_Negative; -- compare functions -- =, /=, >=, <=, <, > function eq ( -- equal = l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable lfptype, rfptype : valid_fpstate; variable is_equal, is_unordered : BOOLEAN; constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- equal if (fraction_width = 0 or l'length < 7 or r'length < 7) then return false; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = neg_zero or lfptype = pos_zero) and (rfptype = neg_zero or rfptype = pos_zero) then is_equal := true; else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); is_equal := (to_slv(lresize) = to_slv(rresize)); end if; if (check_error) then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return is_equal and not is_unordered; end function eq; function lt ( -- less than < l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable expl, expr : UNSIGNED (exponent_width-1 downto 0); variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0); variable is_less_than, is_unordered : BOOLEAN; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then is_less_than := false; else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits expl := UNSIGNED(lresize(exponent_width-1 downto 0)); expr := UNSIGNED(rresize(exponent_width-1 downto 0)); if expl = expr then fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width))); fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width))); if to_x01(l(l'high)) = '0' then -- positive number is_less_than := (fractl < fractr); else is_less_than := (fractl > fractr); -- negative end if; else if to_x01(l(l'high)) = '0' then -- positive number is_less_than := (expl < expr); else is_less_than := (expl > expr); -- negative end if; end if; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); if (lfptype = neg_zero and rfptype = pos_zero) then is_less_than := false; -- -0 < 0 returns false. else is_less_than := (to_x01(l(l'high)) > to_x01(r(r'high))); end if; end if; end if; if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return is_less_than and not is_unordered; end function lt; function gt ( -- greater than > l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable expl, expr : UNSIGNED (exponent_width-1 downto 0); variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0); variable is_greater_than : BOOLEAN; variable is_unordered : BOOLEAN; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- greater_than if (fraction_width = 0 or l'length < 7 or r'length < 7) then is_greater_than := false; else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits expl := UNSIGNED(lresize(exponent_width-1 downto 0)); expr := UNSIGNED(rresize(exponent_width-1 downto 0)); if expl = expr then fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width))); fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width))); if to_x01(l(l'high)) = '0' then -- positive number is_greater_than := fractl > fractr; else is_greater_than := fractl < fractr; -- negative end if; else if to_x01(l(l'high)) = '0' then -- positive number is_greater_than := expl > expr; else is_greater_than := expl < expr; -- negative end if; end if; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); if (lfptype = pos_zero and rfptype = neg_zero) then is_greater_than := false; -- 0 > -0 returns false. else is_greater_than := to_x01(l(l'high)) < to_x01(r(r'high)); end if; end if; end if; if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return is_greater_than and not is_unordered; end function gt; -- purpose: /= function function ne ( -- not equal /= l, r : UNRESOLVED_float; constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable is_equal, is_unordered : BOOLEAN; begin is_equal := eq (l => l, r => r, check_error => false, denormalize => denormalize); if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return not (is_equal and not is_unordered); end function ne; function le ( -- less than or equal to <= l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable is_greater_than, is_unordered : BOOLEAN; begin is_greater_than := gt (l => l, r => r, check_error => false, denormalize => denormalize); if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return not is_greater_than and not is_unordered; end function le; function ge ( -- greater than or equal to >= l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable is_less_than, is_unordered : BOOLEAN; begin is_less_than := lt (l => l, r => r, check_error => false, denormalize => denormalize); if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return not is_less_than and not is_unordered; end function ge; function "?=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable is_equal, is_unordered : STD_ULOGIC; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- ?= if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else lfptype := classfp (l, float_check_error); rfptype := classfp (r, float_check_error); end if; if (lfptype = neg_zero or lfptype = pos_zero) and (rfptype = neg_zero or rfptype = pos_zero) then is_equal := '1'; else lresize := resize (arg => l, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); rresize := resize (arg => r, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); is_equal := to_sulv(lresize) ?= to_sulv(rresize); end if; if (float_check_error) then if (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan) then is_unordered := '1'; else is_unordered := '0'; end if; else is_unordered := '0'; end if; return is_equal and not is_unordered; end function "?="; function "?/=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable is_equal, is_unordered : STD_ULOGIC; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- ?/= if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else lfptype := classfp (l, float_check_error); rfptype := classfp (r, float_check_error); end if; if (lfptype = neg_zero or lfptype = pos_zero) and (rfptype = neg_zero or rfptype = pos_zero) then is_equal := '1'; else lresize := resize (arg => l, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); rresize := resize (arg => r, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); is_equal := to_sulv(lresize) ?= to_sulv(rresize); end if; if (float_check_error) then if (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan) then is_unordered := '1'; else is_unordered := '0'; end if; else is_unordered := '0'; end if; return not (is_equal and not is_unordered); end function "?/="; function "?>" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?>"": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l > r then return '1'; else return '0'; end if; end if; end function "?>"; function "?>=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?>="": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l >= r then return '1'; else return '0'; end if; end if; end function "?>="; function "?<" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?<"": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l < r then return '1'; else return '0'; end if; end if; end function "?<"; function "?<=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?<="": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l <= r then return '1'; else return '0'; end if; end if; end function "?<="; function std_match (L, R : UNRESOLVED_float) return BOOLEAN is begin if (L'high = R'high and L'low = R'low) then return std_match(to_sulv(L), to_sulv(R)); else report float_generic_pkg'instance_name & "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE" severity warning; return false; end if; end function std_match; function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is begin for_loop : for i in arg'reverse_range loop if arg(i) ?= y then return i; end if; end loop; return arg'high+1; -- return out of bounds 'high end function find_rightmost; function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is begin for_loop : for i in arg'range loop if arg(i) ?= y then return i; end if; end loop; return arg'low-1; -- return out of bounds 'low end function find_leftmost; -- These override the defaults for the compare operators. function "=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return eq(l, r); end function "="; function "/=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return ne(l, r); end function "/="; function ">=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return ge(l, r); end function ">="; function "<=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return le(l, r); end function "<="; function ">" (l, r : UNRESOLVED_float) return BOOLEAN is begin return gt(l, r); end function ">"; function "<" (l, r : UNRESOLVED_float) return BOOLEAN is begin return lt(l, r); end function "<"; -- purpose: maximum of two numbers (overrides default) function maximum ( L, R : UNRESOLVED_float) return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin if ((L'length < 1) or (R'length < 1)) then return NAFP; end if; lresize := resize (l, exponent_width, fraction_width); rresize := resize (r, exponent_width, fraction_width); if lresize > rresize then return lresize; else return rresize; end if; end function maximum; function minimum ( L, R : UNRESOLVED_float) return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin if ((L'length < 1) or (R'length < 1)) then return NAFP; end if; lresize := resize (l, exponent_width, fraction_width); rresize := resize (r, exponent_width, fraction_width); if lresize > rresize then return rresize; else return lresize; end if; end function minimum; ----------------------------------------------------------------------------- -- conversion functions ----------------------------------------------------------------------------- -- Converts a floating point number of one format into another format function resize ( arg : UNRESOLVED_float; -- Floating point input constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant in_fraction_width : NATURAL := -arg'low; -- length of FP output fraction constant in_exponent_width : NATURAL := arg'high; -- length of FP output exponent variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result value variable fptype : valid_fpstate; variable expon_in : SIGNED (in_exponent_width-1 downto 0); variable fract_in : UNSIGNED (in_fraction_width downto 0); variable round : BOOLEAN; variable expon_out : SIGNED (exponent_width-1 downto 0); -- output fract variable fract_out : UNSIGNED (fraction_width downto 0); -- output fract variable passguard : NATURAL; begin fptype := classfp(arg, check_error); if ((fptype = pos_denormal or fptype = neg_denormal) and denormalize_in and (in_exponent_width < exponent_width or in_fraction_width < fraction_width)) or in_exponent_width > exponent_width or in_fraction_width > fraction_width then -- size reduction classcase : case fptype is when isx => result := (others => 'X'); when nan \| quiet_nan => result := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf => result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); when neg_inf => result := neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_zero \| neg_zero => result := zerofp (fraction_width => fraction_width, -- hate -0 exponent_width => exponent_width); when others => break_number ( arg => arg, fptyp => fptype, denormalize => denormalize_in, fract => fract_in, expon => expon_in); if fraction_width > in_fraction_width and denormalize_in then -- You only get here if you have a denormal input fract_out := (others => '0'); -- pad with zeros fract_out (fraction_width downto fraction_width - in_fraction_width) := fract_in; result := normalize ( fract => fract_out, expon => expon_in, sign => arg(arg'high), fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => 0); else result := normalize ( fract => fract_in, expon => expon_in, sign => arg(arg'high), fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => in_fraction_width - fraction_width); end if; end case classcase; else -- size increase or the same size if exponent_width > in_exponent_width then expon_in := SIGNED(arg (in_exponent_width-1 downto 0)); if fptype = pos_zero or fptype = neg_zero then result (exponent_width-1 downto 0) := (others => '0'); elsif expon_in = -1 then -- inf or nan (shorts out check_error) result (exponent_width-1 downto 0) := (others => '1'); else -- invert top BIT expon_in(expon_in'high) := not expon_in(expon_in'high); expon_out := resize (expon_in, expon_out'length); -- signed expand -- Flip it back. expon_out(expon_out'high) := not expon_out(expon_out'high); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon_out); end if; result (exponent_width) := arg (in_exponent_width); -- sign else -- exponent_width = in_exponent_width result (exponent_width downto 0) := arg (in_exponent_width downto 0); end if; if fraction_width > in_fraction_width then result (-1 downto -fraction_width) := (others => '0'); -- zeros result (-1 downto -in_fraction_width) := arg (-1 downto -in_fraction_width); else -- fraction_width = in_fraciton_width result (-1 downto -fraction_width) := arg (-1 downto -in_fraction_width); end if; end if; return result; end function resize; function resize ( arg : UNRESOLVED_float; -- floating point input size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := resize (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); return result; end if; end function resize; function to_float32 ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float32 is begin return resize (arg => arg, exponent_width => float32'high, fraction_width => -float32'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); end function to_float32; function to_float64 ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float64 is begin return resize (arg => arg, exponent_width => float64'high, fraction_width => -float64'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); end function to_float64; function to_float128 ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float128 is begin return resize (arg => arg, exponent_width => float128'high, fraction_width => -float128'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); end function to_float128; -- to_float (Real) -- typically not Synthesizable unless the input is a constant. function to_float ( arg : REAL; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arg_real : REAL; -- Real version of argument variable validfp : boundary_type; -- Check for valid results variable exp : INTEGER; -- Integer version of exponent variable expon : UNSIGNED (exponent_width - 1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fract : UNSIGNED (fraction_width-1 downto 0); variable frac : REAL; -- Real version of fraction constant roundfrac : REAL := 2.0 ** (-2 - fract'high); -- used for rounding variable round : BOOLEAN; -- to round or not to round begin result := (others => '0'); arg_real := arg; if arg_real < 0.0 then result (exponent_width) := '1'; arg_real := - arg_real; -- Make it positive. else result (exponent_width) := '0'; end if; test_boundary (arg => arg_real, fraction_width => fraction_width, exponent_width => exponent_width, denormalize => denormalize, btype => validfp, log2i => exp); if validfp = zero then return result; -- Result initialized to "0". elsif validfp = infinity then result (exponent_width - 1 downto 0) := (others => '1'); -- Exponent all "1" -- return infinity. return result; else if validfp = denormal then -- Exponent will default to "0". expon := (others => '0'); frac := arg_real * (2.0 (to_integer(expon_base)-1)); else -- Number less than 1. "normal" number expon := UNSIGNED (to_signed (exp-1, exponent_width)); expon(exponent_width-1) := not expon(exponent_width-1); frac := (arg_real / 2.0 exp) - 1.0; -- Number less than 1. end if; for i in 0 to fract'high loop if frac >= 2.0 (-1 - i) then fract (fract'high - i) := '1'; frac := frac - 2.0 (-1 - i); else fract (fract'high - i) := '0'; end if; end loop; round := false; case round_style is when round_nearest => if frac > roundfrac or ((frac = roundfrac) and fract(0) = '1') then round := true; end if; when round_inf => if frac /= 0.0 and result(exponent_width) = '0' then round := true; end if; when round_neginf => if frac /= 0.0 and result(exponent_width) = '1' then round := true; end if; when others => null; -- don't round end case; if (round) then if and(fract) = '1' then -- fraction is all "1" expon := expon + 1; fract := (others => '0'); else fract := fract + 1; end if; end if; result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(fract); return result; end if; end function to_float; -- to_float (Integer) function to_float ( arg : INTEGER; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arg_int : NATURAL; -- Natural version of argument variable expon : SIGNED (exponent_width-1 downto 0); variable exptmp : SIGNED (exponent_width-1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fract : UNSIGNED (fraction_width-1 downto 0) := (others => '0'); variable fracttmp : UNSIGNED (fraction_width-1 downto 0); variable round : BOOLEAN; variable shift : NATURAL; variable shiftr : NATURAL; variable roundfrac : NATURAL; -- used in rounding begin if arg < 0 then result (exponent_width) := '1'; arg_int := -arg; -- Make it positive. else result (exponent_width) := '0'; arg_int := arg; end if; if arg_int = 0 then result := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else -- If the number is larger than we can represent in this number system -- we need to return infinity. shift := log2(arg_int); if shift > to_integer(expon_base) then -- worry about infinity if result (exponent_width) = '0' then result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else -- return negative infinity. result := neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); end if; else -- Normal number (can't be denormal) -- Compute Exponent expon := to_signed (shift-1, expon'length); -- positive fraction. -- Compute Fraction arg_int := arg_int - 2shift; -- Subtract off the 1.0 shiftr := shift; for I in fract'high downto maximum (fract'high - shift + 1, 0) loop shiftr := shiftr - 1; if (arg_int >= 2shiftr) then arg_int := arg_int - 2shiftr; fract(I) := '1'; else fract(I) := '0'; end if; end loop; -- Rounding routine round := false; if arg_int > 0 then roundfrac := 2(shiftr-1); case round_style is when round_nearest => if arg_int > roundfrac or ((arg_int = roundfrac) and fract(0) = '1') then round := true; end if; when round_inf => if arg_int /= 0 and result (exponent_width) = '0' then round := true; end if; when round_neginf => if arg_int /= 0 and result (exponent_width) = '1' then round := true; end if; when others => null; end case; end if; if round then fp_round(fract_in => fract, expon_in => expon, fract_out => fracttmp, expon_out => exptmp); fract := fracttmp; expon := exptmp; end if; -- Put the number together and return expon(exponent_width-1) := not expon(exponent_width-1); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(fract); end if; end if; return result; end function to_float; -- to_float (unsigned) function to_float ( arg : UNRESOLVED_UNSIGNED; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG; variable sarg : SIGNED (ARG_LEFT+1 downto 0); -- signed version of arg begin if arg'length < 1 then return NAFP; end if; sarg (XARG'range) := SIGNED (XARG); sarg (sarg'high) := '0'; result := to_float (arg => sarg, exponent_width => exponent_width, fraction_width => fraction_width, round_style => round_style); return result; end function to_float; -- to_float (signed) function to_float ( arg : UNRESOLVED_SIGNED; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : SIGNED(ARG_LEFT downto 0) is ARG; variable arg_int : UNSIGNED(xarg'range); -- Real version of argument variable argb2 : UNSIGNED(xarg'high/2 downto 0); -- log2 of input variable rexp : SIGNED (exponent_width - 1 downto 0); variable exp : SIGNED (exponent_width - 1 downto 0); -- signed version of exp. variable expon : UNSIGNED (exponent_width - 1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable round : BOOLEAN; variable fract : UNSIGNED (fraction_width-1 downto 0); variable rfract : UNSIGNED (fraction_width-1 downto 0); variable sign : STD_ULOGIC; -- sign bit begin if arg'length < 1 then return NAFP; end if; if Is_X (xarg) then result := (others => 'X'); elsif (xarg = 0) then result := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else -- Normal number (can't be denormal) sign := to_X01(xarg (xarg'high)); arg_int := UNSIGNED(abs (to_01(xarg))); -- Compute Exponent argb2 := to_unsigned(find_leftmost(arg_int, '1'), argb2'length); -- Log2 if argb2 > UNSIGNED(expon_base) then result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); result (exponent_width) := sign; else exp := SIGNED(resize(argb2, exp'length)); arg_int := shift_left (arg_int, arg_int'high-to_integer(exp)); if (arg_int'high > fraction_width) then fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)); round := check_round ( fract_in => fract (0), sign => sign, remainder => arg_int((arg_int'high-fraction_width-1) downto 0), round_style => round_style); if round then fp_round(fract_in => fract, expon_in => exp, fract_out => rfract, expon_out => rexp); else rfract := fract; rexp := exp; end if; else rexp := exp; rfract := (others => '0'); rfract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) := arg_int (arg_int'high-1 downto 0); end if; result (exponent_width) := sign; expon := UNSIGNED (rexp-1); expon(exponent_width-1) := not expon(exponent_width-1); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(rfract); end if; end if; return result; end function to_float; -- std_logic_vector to float function to_float ( arg : STD_ULOGIC_VECTOR; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction return UNRESOLVED_float is variable fpvar : UNRESOLVED_float (exponent_width downto -fraction_width); begin if arg'length < 1 then return NAFP; end if; fpvar := UNRESOLVED_float(arg); return fpvar; end function to_float; -- purpose: converts a ufixed to a floating point function to_float ( arg : UNRESOLVED_ufixed; -- unsigned fixed point input constant exponent_width : NATURAL := float_exponent_width; -- width of exponent constant fraction_width : NATURAL := float_fraction_width; -- width of fraction constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions return UNRESOLVED_float is variable sarg : sfixed (arg'high+1 downto arg'low); -- Signed version of arg variable result : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- function to_float if (arg'length < 1) then return NAFP; end if; sarg (arg'range) := sfixed (arg); sarg (sarg'high) := '0'; result := to_float (arg => sarg, exponent_width => exponent_width, fraction_width => fraction_width, round_style => round_style, denormalize => denormalize); return result; end function to_float; function to_float ( arg : UNRESOLVED_sfixed; -- signed fixed point constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- rounding option return UNRESOLVED_float is constant integer_width : INTEGER := arg'high; constant in_fraction_width : INTEGER := arg'low; variable xresult : sfixed (integer_width downto in_fraction_width); variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arg_int : UNSIGNED(integer_width - in_fraction_width - 1 downto 0); -- signed version of argument variable argx : SIGNED (integer_width - in_fraction_width downto 0); variable exp, exptmp : SIGNED (exponent_width downto 0); variable expon : UNSIGNED (exponent_width - 1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) := (others => '0'); variable round : BOOLEAN := false; begin if (arg'length < 1) then return NAFP; end if; xresult := to_01(arg, 'X'); argx := SIGNED(to_slv(xresult)); if (Is_X (arg)) then result := (others => 'X'); elsif (argx = 0) then result := (others => '0'); else result := (others => '0'); -- zero out the result if argx(argx'left) = '1' then -- toss the sign bit result (exponent_width) := '1'; -- Negative number argx := -argx; -- Make it positive. else result (exponent_width) := '0'; end if; arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (argx(arg_int'range)))); -- Compute Exponent exp := to_signed(find_leftmost(arg_int, '1'), exp'length); -- Log2 if exp + in_fraction_width > expon_base then -- return infinity result (-1 downto -fraction_width) := (others => '0'); result (exponent_width -1 downto 0) := (others => '1'); return result; elsif (denormalize and (exp + in_fraction_width <= -resize(expon_base, exp'length))) then exp := -resize(expon_base, exp'length); -- shift by a constant arg_int := shift_left (arg_int, (arg_int'high + to_integer(expon_base) + in_fraction_width - 1)); if (arg_int'high > fraction_width) then fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)); round := check_round ( fract_in => arg_int(arg_int'high-fraction_width), sign => result(result'high), remainder => arg_int((arg_int'high-fraction_width-1) downto 0), round_style => round_style); if (round) then fp_round (fract_in => arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)), expon_in => exp, fract_out => fract, expon_out => exptmp); exp := exptmp; end if; else fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) := arg_int (arg_int'high-1 downto 0); end if; else arg_int := shift_left (arg_int, arg_int'high-to_integer(exp)); exp := exp + in_fraction_width; if (arg_int'high > fraction_width) then fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)); round := check_round ( fract_in => fract(0), sign => result(result'high), remainder => arg_int((arg_int'high-fraction_width-1) downto 0), round_style => round_style); if (round) then fp_round (fract_in => fract, expon_in => exp, fract_out => fracttmp, expon_out => exptmp); fract := fracttmp; exp := exptmp; end if; else fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) := arg_int (arg_int'high-1 downto 0); end if; end if; expon := UNSIGNED (resize(exp-1, exponent_width)); expon(exponent_width-1) := not expon(exponent_width-1); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(fract); end if; return result; end function to_float; -- size_res functions -- Integer to float function to_float ( arg : INTEGER; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style); return result; end if; end function to_float; -- real to float function to_float ( arg : REAL; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, denormalize => denormalize); return result; end if; end function to_float; -- unsigned to float function to_float ( arg : UNRESOLVED_UNSIGNED; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style); return result; end if; end function to_float; -- signed to float function to_float ( arg : UNRESOLVED_SIGNED; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style) -- rounding return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style); return result; end if; end function to_float; -- std_ulogic_vector to float function to_float ( arg : STD_ULOGIC_VECTOR; size_res : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low); return result; end if; end function to_float; -- unsigned fixed point to float function to_float ( arg : UNRESOLVED_ufixed; -- unsigned fixed point input size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, denormalize => denormalize); return result; end if; end function to_float; -- signed fixed point to float function to_float ( arg : UNRESOLVED_sfixed; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, denormalize => denormalize); return result; end if; end function to_float; -- to_integer (float) function to_integer ( arg : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return INTEGER is variable validfp : valid_fpstate; -- Valid FP state variable frac : UNSIGNED (-arg'low downto 0); -- Fraction variable fract : UNSIGNED (1-arg'low downto 0); -- Fraction variable expon : SIGNED (arg'high-1 downto 0); variable isign : STD_ULOGIC; -- internal version of sign variable round : STD_ULOGIC; -- is rounding needed? variable result : INTEGER; variable base : INTEGER; -- Integer exponent begin validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan \| pos_zero \| neg_zero \| pos_denormal \| neg_denormal => result := 0; -- return 0 when pos_inf => result := INTEGER'high; when neg_inf => result := INTEGER'low; when others => break_number ( arg => arg, fptyp => validfp, denormalize => false, fract => frac, expon => expon); fract (fract'high) := '0'; -- Add extra bit for 0.6 case fract (fract'high-1 downto 0) := frac; isign := to_x01 (arg (arg'high)); base := to_integer (expon) + 1; if base < -1 then result := 0; elsif base >= frac'high then result := to_integer (fract) * 2(base - frac'high); else -- We need to round if base = -1 then -- trap for 0.6 case. result := 0; else result := to_integer (fract (frac'high downto frac'high-base)); end if; -- rounding routine case round_style is when round_nearest => if frac'high - base > 1 then round := fract (frac'high - base - 1) and (fract (frac'high - base) or (or (fract (frac'high - base - 2 downto 0)))); else round := fract (frac'high - base - 1) and fract (frac'high - base); end if; when round_inf => round := fract(frac'high - base - 1) and not isign; when round_neginf => round := fract(frac'high - base - 1) and isign; when others => round := '0'; end case; if round = '1' then result := result + 1; end if; end if; if isign = '1' then result := - result; end if; end case classcase; return result; end function to_integer; -- to_unsigned (float) function to_unsigned ( arg : UNRESOLVED_float; -- floating point input constant size : NATURAL; -- length of output constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_UNSIGNED is variable validfp : valid_fpstate; -- Valid FP state variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction variable sign : STD_ULOGIC; -- not used begin validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan => frac := (others => 'X'); when pos_zero \| neg_inf \| neg_zero \| neg_normal \| pos_denormal \| neg_denormal => frac := (others => '0'); -- return 0 when pos_inf => frac := (others => '1'); when others => float_to_unsigned ( arg => arg, frac => frac, sign => sign, denormalize => false, bias => 0, round_style => round_style); end case classcase; return (frac); end function to_unsigned; -- to_signed (float) function to_signed ( arg : UNRESOLVED_float; -- floating point input constant size : NATURAL; -- length of output constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_SIGNED is variable sign : STD_ULOGIC; -- true if negative variable validfp : valid_fpstate; -- Valid FP state variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction variable result : UNRESOLVED_SIGNED (size-1 downto 0); begin validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan => result := (others => 'X'); when pos_zero \| neg_zero \| pos_denormal \| neg_denormal => result := (others => '0'); -- return 0 when pos_inf => result := (others => '1'); result (result'high) := '0'; when neg_inf => result := (others => '0'); result (result'high) := '1'; when others => float_to_unsigned ( arg => arg, sign => sign, frac => frac, denormalize => false, bias => 0, round_style => round_style); result (size-1) := '0'; result (size-2 downto 0) := UNRESOLVED_SIGNED(frac (size-2 downto 0)); if sign = '1' then -- Because the most negative signed number is 1 less than the most -- positive signed number, we need this code. if frac(frac'high) = '1' then -- return most negative number result := (others => '0'); result (result'high) := '1'; else result := -result; end if; else if frac(frac'high) = '1' then -- return most positive number result := (others => '1'); result (result'high) := '0'; end if; end if; end case classcase; return result; end function to_signed; -- purpose: Converts a float to ufixed function to_ufixed ( arg : UNRESOLVED_float; -- fp input constant left_index : INTEGER; -- integer part constant right_index : INTEGER; -- fraction part constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_ufixed is constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent constant size : INTEGER := left_index - right_index + 4; -- unsigned size variable expon_base : INTEGER; -- exponent offset variable validfp : valid_fpstate; -- Valid FP state variable exp : INTEGER; -- Exponent variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent -- Base to divide fraction by variable frac : UNSIGNED (size-1 downto 0) := (others => '0'); -- Fraction variable frac_shift : UNSIGNED (size-1 downto 0); -- Fraction shifted variable shift : INTEGER; variable result_big : UNRESOLVED_ufixed (left_index downto right_index-3); variable result : UNRESOLVED_ufixed (left_index downto right_index); -- result begin -- function to_ufixed validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan => frac := (others => 'X'); when pos_zero \| neg_inf \| neg_zero \| neg_normal \| neg_denormal => frac := (others => '0'); -- return 0 when pos_inf => frac := (others => '1'); -- always saturate when others => expon_base := 2(exponent_width-1) -1; -- exponent offset -- Figure out the fraction if (validfp = pos_denormal) and denormalize then exp := -expon_base +1; frac (frac'high) := '0'; -- Remove the "1.0". else -- exponent /= '0', normal floating point expon := UNSIGNED(arg (exponent_width-1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (SIGNED(expon)) +1; frac (frac'high) := '1'; -- Add the "1.0". end if; shift := (frac'high - 3 + right_index) - exp; if fraction_width > frac'high then -- Can only use size-2 bits frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto -frac'high))); else -- can use all bits frac (frac'high-1 downto frac'high-fraction_width) := UNSIGNED (to_slv (arg(-1 downto -fraction_width))); end if; frac_shift := frac srl shift; if shift < 0 then -- Overflow frac := (others => '1'); else frac := frac_shift; end if; end case classcase; result_big := to_ufixed ( arg => STD_ULOGIC_VECTOR(frac), left_index => left_index, right_index => (right_index-3)); result := resize (arg => result_big, left_index => left_index, right_index => right_index, round_style => round_style, overflow_style => overflow_style); return result; end function to_ufixed; -- purpose: Converts a float to sfixed function to_sfixed ( arg : UNRESOLVED_float; -- fp input constant left_index : INTEGER; -- integer part constant right_index : INTEGER; -- fraction part constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_sfixed is constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent constant size : INTEGER := left_index - right_index + 4; -- unsigned size variable expon_base : INTEGER; -- exponent offset variable validfp : valid_fpstate; -- Valid FP state variable exp : INTEGER; -- Exponent variable sign : BOOLEAN; -- true if negative variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent -- Base to divide fraction by variable frac : UNSIGNED (size-2 downto 0) := (others => '0'); -- Fraction variable frac_shift : UNSIGNED (size-2 downto 0); -- Fraction shifted variable shift : INTEGER; variable rsigned : SIGNED (size-1 downto 0); -- signed version of result variable result_big : UNRESOLVED_sfixed (left_index downto right_index-3); variable result : UNRESOLVED_sfixed (left_index downto right_index) := (others => '0'); -- result begin -- function to_sfixed validfp := classfp (arg, check_error); classcase : case validfp is when isx \| nan \| quiet_nan => result := (others => 'X'); when pos_zero \| neg_zero => result := (others => '0'); -- return 0 when neg_inf => result (left_index) := '1'; -- return smallest negative number when pos_inf => result := (others => '1'); -- return largest number result (left_index) := '0'; when others => expon_base := 2(exponent_width-1) -1; -- exponent offset if arg(exponent_width) = '0' then sign := false; else sign := true; end if; -- Figure out the fraction if (validfp = pos_denormal or validfp = neg_denormal) and denormalize then exp := -expon_base +1; frac (frac'high) := '0'; -- Add the "1.0". else -- exponent /= '0', normal floating point expon := UNSIGNED(arg (exponent_width-1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (SIGNED(expon)) +1; frac (frac'high) := '1'; -- Add the "1.0". end if; shift := (frac'high - 3 + right_index) - exp; if fraction_width > frac'high then -- Can only use size-2 bits frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto -frac'high))); else -- can use all bits frac (frac'high-1 downto frac'high-fraction_width) := UNSIGNED (to_slv (arg(-1 downto -fraction_width))); end if; frac_shift := frac srl shift; if shift < 0 then -- Overflow frac := (others => '1'); else frac := frac_shift; end if; if not sign then rsigned := SIGNED("0" & frac); else rsigned := -(SIGNED("0" & frac)); end if; result_big := to_sfixed ( arg => STD_LOGIC_VECTOR(rsigned), left_index => left_index, right_index => (right_index-3)); result := resize (arg => result_big, left_index => left_index, right_index => right_index, round_style => round_style, overflow_style => overflow_style); end case classcase; return result; end function to_sfixed; -- size_res versions -- float to unsigned function to_unsigned ( arg : UNRESOLVED_float; -- floating point input size_res : UNRESOLVED_UNSIGNED; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_UNSIGNED is variable result : UNRESOLVED_UNSIGNED (size_res'range); begin if (SIZE_RES'length = 0) then return result; else result := to_unsigned ( arg => arg, size => size_res'length, round_style => round_style, check_error => check_error); return result; end if; end function to_unsigned; -- float to signed function to_signed ( arg : UNRESOLVED_float; -- floating point input size_res : UNRESOLVED_SIGNED; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_SIGNED is variable result : UNRESOLVED_SIGNED (size_res'range); begin if (SIZE_RES'length = 0) then return result; else result := to_signed ( arg => arg, size => size_res'length, round_style => round_style, check_error => check_error); return result; end if; end function to_signed; -- purpose: Converts a float to unsigned fixed point function to_ufixed ( arg : UNRESOLVED_float; -- fp input size_res : UNRESOLVED_ufixed; constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_ufixed is variable result : UNRESOLVED_ufixed (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_ufixed ( arg => arg, left_index => size_res'high, right_index => size_res'low, overflow_style => overflow_style, round_style => round_style, check_error => check_error, denormalize => denormalize); return result; end if; end function to_ufixed; -- float to signed fixed point function to_sfixed ( arg : UNRESOLVED_float; -- fp input size_res : UNRESOLVED_sfixed; constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_sfixed is variable result : UNRESOLVED_sfixed (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_sfixed ( arg => arg, left_index => size_res'high, right_index => size_res'low, overflow_style => overflow_style, round_style => round_style, check_error => check_error, denormalize => denormalize); return result; end if; end function to_sfixed; -- to_real (float) -- typically not Synthesizable unless the input is a constant. function to_real ( arg : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return REAL is constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent variable sign : REAL; -- Sign, + or - 1 variable exp : INTEGER; -- Exponent variable expon_base : INTEGER; -- exponent offset variable frac : REAL := 0.0; -- Fraction variable validfp : valid_fpstate; -- Valid FP state variable expon : UNSIGNED (exponent_width - 1 downto 0) := (others => '1'); -- Vectorized exponent begin validfp := classfp (arg, check_error); classcase : case validfp is when isx \| pos_zero \| neg_zero \| nan \| quiet_nan => return 0.0; when neg_inf => return REAL'low; -- Negative infinity. when pos_inf => return REAL'high; -- Positive infinity when others => expon_base := 2(exponent_width-1) -1; if to_X01(arg(exponent_width)) = '0' then sign := 1.0; else sign := -1.0; end if; -- Figure out the fraction for i in 0 to fraction_width-1 loop if to_X01(arg (-1 - i)) = '1' then frac := frac + (2.0 *(-1 - i)); end if; end loop; -- i if validfp = pos_normal or validfp = neg_normal or not denormalize then -- exponent /= '0', normal floating point expon := UNSIGNED(arg (exponent_width-1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (SIGNED(expon)) +1; sign := sign (2.0 ** exp) * (1.0 + frac); else -- exponent = '0', IEEE extended floating point exp := 1 - expon_base; sign := sign * (2.0 ** exp) * frac; end if; return sign; end case classcase; end function to_real; -- For Verilog compatability function realtobits (arg : REAL) return STD_ULOGIC_VECTOR is variable result : float64; -- 64 bit floating point begin result := to_float (arg => arg, exponent_width => float64'high, fraction_width => -float64'low); return to_sulv (result); end function realtobits; function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL is variable arg64 : float64; -- arg converted to float begin arg64 := to_float (arg => arg, exponent_width => float64'high, fraction_width => -float64'low); return to_real (arg64); end function bitstoreal; -- purpose: Removes meta-logical values from FP string function to_01 ( arg : UNRESOLVED_float; -- floating point input XMAP : STD_LOGIC := '0') return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin -- function to_01 if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_01: null detected, returning NULL" severity warning; return NAFP; end if; result := UNRESOLVED_float (STD_LOGIC_VECTOR(to_01(UNSIGNED(to_slv(arg)), XMAP))); return result; end function to_01; function Is_X (arg : UNRESOLVED_float) return BOOLEAN is begin return Is_X (to_slv(arg)); end function Is_X; function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_X01: null detected, returning NULL" severity warning; return NAFP; else result := UNRESOLVED_float (to_X01(to_slv(arg))); return result; end if; end function to_X01; function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_X01Z: null detected, returning NULL" severity warning; return NAFP; else result := UNRESOLVED_float (to_X01Z(to_slv(arg))); return result; end if; end function to_X01Z; function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_UX01: null detected, returning NULL" severity warning; return NAFP; else result := UNRESOLVED_float (to_UX01(to_slv(arg))); return result; end if; end function to_UX01; -- These allows the base math functions to use the default values -- of their parameters. Thus they do full IEEE floating point. function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return add (l, r); end function "+"; function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return subtract (l, r); end function "-"; function "" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return multiply (l, r); end function ""; function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return divide (l, r); end function "/"; function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return remainder (l, r); end function "rem"; function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return modulo (l, r); end function "mod"; -- overloaded versions function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return add (l, r_float); end function "+"; function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return add (l_float, r); end function "+"; function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return add (l, r_float); end function "+"; function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return add (l_float, r); end function "+"; function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return subtract (l, r_float); end function "-"; function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return subtract (l_float, r); end function "-"; function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return subtract (l, r_float); end function "-"; function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return subtract (l_float, r); end function "-"; function "" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return multiply (l, r_float); end function ""; function "" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return multiply (l_float, r); end function ""; function "" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return multiply (l, r_float); end function ""; function "" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return multiply (l_float, r); end function ""; function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return divide (l, r_float); end function "/"; function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return divide (l_float, r); end function "/"; function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return divide (l, r_float); end function "/"; function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return divide (l_float, r); end function "/"; function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return remainder (l, r_float); end function "rem"; function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return remainder (l_float, r); end function "rem"; function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return remainder (l, r_float); end function "rem"; function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return remainder (l_float, r); end function "rem"; function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return modulo (l, r_float); end function "mod"; function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return modulo (l_float, r); end function "mod"; function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return modulo (l, r_float); end function "mod"; function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return modulo (l_float, r); end function "mod"; function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return eq (l, r_float); end function "="; function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ne (l, r_float); end function "/="; function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ge (l, r_float); end function ">="; function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return le (l, r_float); end function "<="; function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return gt (l, r_float); end function ">"; function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return lt (l, r_float); end function "<"; function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return eq (l_float, r); end function "="; function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ne (l_float, r); end function "/="; function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ge (l_float, r); end function ">="; function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return le (l_float, r); end function "<="; function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return gt (l_float, r); end function ">"; function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return lt (l_float, r); end function "<"; function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return eq (l, r_float); end function "="; function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ne (l, r_float); end function "/="; function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ge (l, r_float); end function ">="; function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return le (l, r_float); end function "<="; function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return gt (l, r_float); end function ">"; function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return lt (l, r_float); end function "<"; function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return eq (l_float, r); end function "="; function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ne (l_float, r); end function "/="; function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ge (l_float, r); end function ">="; function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return le (l_float, r); end function "<="; function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return gt (l_float, r); end function ">"; function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return lt (l_float, r); end function "<"; -- ?= overloads function "?=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?= r_float; end function "?="; function "?/=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?/= r_float; end function "?/="; function "?>" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?> r_float; end function "?>"; function "?>=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?>= r_float; end function "?>="; function "?<" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?< r_float; end function "?<"; function "?<=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?<= r_float; end function "?<="; -- real and float function "?=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?= r; end function "?="; function "?/=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?/= r; end function "?/="; function "?>" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?> r; end function "?>"; function "?>=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?>= r; end function "?>="; function "?<" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?< r; end function "?<"; function "?<=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?<= r; end function "?<="; -- ?= overloads function "?=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?= r_float; end function "?="; function "?/=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?/= r_float; end function "?/="; function "?>" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?> r_float; end function "?>"; function "?>=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?>= r_float; end function "?>="; function "?<" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?< r_float; end function "?<"; function "?<=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?<= r_float; end function "?<="; -- integer and float function "?=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?= r; end function "?="; function "?/=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?/= r; end function "?/="; function "?>" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?> r; end function "?>"; function "?>=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?>= r; end function "?>="; function "?<" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?< r; end function "?<"; function "?<=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?<= r; end function "?<="; -- minimum and maximum overloads function minimum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return minimum (l, r_float); end function minimum; function maximum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return maximum (l, r_float); end function maximum; function minimum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return minimum (l_float, r); end function minimum; function maximum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return maximum (l_float, r); end function maximum; function minimum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return minimum (l, r_float); end function minimum; function maximum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return maximum (l, r_float); end function maximum; function minimum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return minimum (l_float, r); end function minimum; function maximum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return maximum (l_float, r); end function maximum; ---------------------------------------------------------------------------- -- logical functions ---------------------------------------------------------------------------- function "not" (L : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin RESULT := not to_sulv(L); return to_float (RESULT, L'high, -L'low); end function "not"; function "and" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) and to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """and"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "and"; function "or" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) or to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """or"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "or"; function "nand" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) nand to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """nand"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "nand"; function "nor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) nor to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """nor"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "nor"; function "xor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) xor to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """xor"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "xor"; function "xnor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) xnor to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """xnor"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "xnor"; -- Vector and std_ulogic functions, same as functions in numeric_std function "and" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L and to_sulv(R)); return result; end function "and"; function "and" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) and R); return result; end function "and"; function "or" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L or to_sulv(R)); return result; end function "or"; function "or" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) or R); return result; end function "or"; function "nand" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L nand to_sulv(R)); return result; end function "nand"; function "nand" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) nand R); return result; end function "nand"; function "nor" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L nor to_sulv(R)); return result; end function "nor"; function "nor" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) nor R); return result; end function "nor"; function "xor" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L xor to_sulv(R)); return result; end function "xor"; function "xor" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) xor R); return result; end function "xor"; function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L xnor to_sulv(R)); return result; end function "xnor"; function "xnor" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) xnor R); return result; end function "xnor"; -- Reduction operators, same as numeric_std functions function "and" (l : UNRESOLVED_float) return STD_ULOGIC is begin return and to_sulv(l); end function "and"; function "nand" (l : UNRESOLVED_float) return STD_ULOGIC is begin return nand to_sulv(l); end function "nand"; function "or" (l : UNRESOLVED_float) return STD_ULOGIC is begin return or to_sulv(l); end function "or"; function "nor" (l : UNRESOLVED_float) return STD_ULOGIC is begin return nor to_sulv(l); end function "nor"; function "xor" (l : UNRESOLVED_float) return STD_ULOGIC is begin return xor to_sulv(l); end function "xor"; function "xnor" (l : UNRESOLVED_float) return STD_ULOGIC is begin return xnor to_sulv(l); end function "xnor"; ----------------------------------------------------------------------------- -- Recommended Functions from the IEEE 754 Appendix ----------------------------------------------------------------------------- -- returns x with the sign of y. function Copysign ( x, y : UNRESOLVED_float) -- floating point input return UNRESOLVED_float is begin return y(y'high) & x (x'high-1 downto x'low); end function Copysign; -- Returns y * 2n for integral values of N without computing 2n function Scalb ( y : UNRESOLVED_float; -- floating point input N : INTEGER; -- exponent to add constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(y'low, y'low); -- length of FP output fraction constant exponent_width : NATURAL := y'high; -- length of FP output exponent variable arg, result : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp variable exp : SIGNED (exponent_width downto 0); variable ufract : UNSIGNED (fraction_width downto 0); constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fptype : valid_fpstate; begin -- This can be done by simply adding N to the exponent. arg := to_01 (y, 'X'); fptype := classfp(arg, check_error); classcase : case fptype is when isx => result := (others => 'X'); when nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 result := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when others => break_number ( arg => arg, fptyp => fptype, denormalize => denormalize, fract => ufract, expon => expon); exp := resize (expon, exp'length) + N; result := normalize ( fract => ufract, expon => exp, sign => to_x01 (arg (arg'high)), fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => 0); end case classcase; return result; end function Scalb; -- Returns y * 2n for integral values of N without computing 2n function Scalb ( y : UNRESOLVED_float; -- floating point input N : UNRESOLVED_SIGNED; -- exponent to add constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable n_int : INTEGER; begin n_int := to_integer(N); return Scalb (y => y, N => n_int, round_style => round_style, check_error => check_error, denormalize => denormalize); end function Scalb; -- returns the unbiased exponent of x function Logb ( x : UNRESOLVED_float) -- floating point input return INTEGER is constant fraction_width : NATURAL := -mine (x'low, x'low); -- length of FP output fraction constant exponent_width : NATURAL := x'high; -- length of FP output exponent variable result : INTEGER; -- result variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument variable expon : SIGNED (exponent_width - 1 downto 0); variable fract : UNSIGNED (fraction_width downto 0); constant expon_base : INTEGER := 2*(exponent_width-1) -1; -- exponent -- offset +1 variable fptype : valid_fpstate; begin -- Just return the exponent. arg := to_01 (x, 'X'); fptype := classfp(arg); classcase : case fptype is when isx \| nan \| quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 result := 0; when pos_denormal \| neg_denormal => fract (fraction_width) := '0'; fract (fraction_width-1 downto 0) := UNSIGNED (to_slv(arg(-1 downto -fraction_width))); result := find_leftmost (fract, '1') -- Find the first "1" - fraction_width; -- subtract the length we want result := -expon_base + 1 + result; when others => expon := SIGNED(arg (exponent_width - 1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); expon := expon + 1; result := to_integer (expon); end case classcase; return result; end function Logb; -- returns the unbiased exponent of x function Logb ( x : UNRESOLVED_float) -- floating point input return UNRESOLVED_SIGNED is constant exponent_width : NATURAL := x'high; -- length of FP output exponent variable result : SIGNED (exponent_width - 1 downto 0); -- result begin -- Just return the exponent. result := to_signed (Logb (x), exponent_width); return result; end function Logb; -- returns the next representable neighbor of x in the direction toward y function Nextafter ( x, y : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(x'low, x'low); -- length of FP output fraction constant exponent_width : NATURAL := x'high; -- length of FP output exponent function "=" ( l, r : UNRESOLVED_float) -- inputs return BOOLEAN is begin -- function "=" return eq (l => l, r => r, check_error => false); end function "="; function ">" ( l, r : UNRESOLVED_float) -- inputs return BOOLEAN is begin -- function ">" return gt (l => l, r => r, check_error => false); end function ">"; variable fract : UNSIGNED (fraction_width-1 downto 0); variable expon : UNSIGNED (exponent_width-1 downto 0); variable sign : STD_ULOGIC; variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable validfpx, validfpy : valid_fpstate; -- Valid FP state begin -- fp_Nextafter -- If Y > X, add one to the fraction, otherwise subtract. validfpx := classfp (x, check_error); validfpy := classfp (y, check_error); if validfpx = isx or validfpy = isx then result := (others => 'X'); return result; elsif (validfpx = nan or validfpy = nan) then return nanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (validfpx = quiet_nan or validfpy = quiet_nan) then return qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif x = y then -- Return X return x; else fract := UNSIGNED (to_slv (x (-1 downto -fraction_width))); -- Fraction expon := UNSIGNED (x (exponent_width - 1 downto 0)); -- exponent sign := x(exponent_width); -- sign bit if (y > x) then -- Increase the number given if validfpx = neg_inf then -- return most negative number expon := (others => '1'); expon (0) := '0'; fract := (others => '1'); elsif validfpx = pos_zero or validfpx = neg_zero then -- return smallest denormal number sign := '0'; expon := (others => '0'); fract := (others => '0'); fract(0) := '1'; elsif validfpx = pos_normal then if and (fract) = '1' then -- fraction is all "1". if and (expon (exponent_width-1 downto 1)) = '1' and expon (0) = '0' then -- Exponent is one away from infinity. assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "FP_NEXTAFTER: NextAfter overflow" severity warning; return pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else expon := expon + 1; fract := (others => '0'); end if; else fract := fract + 1; end if; elsif validfpx = pos_denormal then if and (fract) = '1' then -- fraction is all "1". -- return smallest possible normal number expon := (others => '0'); expon(0) := '1'; fract := (others => '0'); else fract := fract + 1; end if; elsif validfpx = neg_normal then if or (fract) = '0' then -- fraction is all "0". if or (expon (exponent_width-1 downto 1)) = '0' and expon (0) = '1' then -- Smallest exponent -- return the largest negative denormal number expon := (others => '0'); fract := (others => '1'); else expon := expon - 1; fract := (others => '1'); end if; else fract := fract - 1; end if; elsif validfpx = neg_denormal then if or (fract(fract'high downto 1)) = '0' and fract (0) = '1' then -- Smallest possible fraction return zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else fract := fract - 1; end if; end if; else -- Decrease the number if validfpx = pos_inf then -- return most positive number expon := (others => '1'); expon (0) := '0'; fract := (others => '1'); elsif validfpx = pos_zero or classfp (x) = neg_zero then -- return smallest negative denormal number sign := '1'; expon := (others => '0'); fract := (others => '0'); fract(0) := '1'; elsif validfpx = neg_normal then if and (fract) = '1' then -- fraction is all "1". if and (expon (exponent_width-1 downto 1)) = '1' and expon (0) = '0' then -- Exponent is one away from infinity. assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "FP_NEXTAFTER: NextAfter overflow" severity warning; return neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else expon := expon + 1; -- Fraction overflow fract := (others => '0'); end if; else fract := fract + 1; end if; elsif validfpx = neg_denormal then if and (fract) = '1' then -- fraction is all "1". -- return smallest possible normal number expon := (others => '0'); expon(0) := '1'; fract := (others => '0'); else fract := fract + 1; end if; elsif validfpx = pos_normal then if or (fract) = '0' then -- fraction is all "0". if or (expon (exponent_width-1 downto 1)) = '0' and expon (0) = '1' then -- Smallest exponent -- return the largest positive denormal number expon := (others => '0'); fract := (others => '1'); else expon := expon - 1; fract := (others => '1'); end if; else fract := fract - 1; end if; elsif validfpx = pos_denormal then if or (fract(fract'high downto 1)) = '0' and fract (0) = '1' then -- Smallest possible fraction return zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else fract := fract - 1; end if; end if; end if; result (-1 downto -fraction_width) := UNRESOLVED_float(fract); result (exponent_width -1 downto 0) := UNRESOLVED_float(expon); result (exponent_width) := sign; return result; end if; end function Nextafter; -- Returns True if X is unordered with Y. function Unordered ( x, y : UNRESOLVED_float) -- floating point input return BOOLEAN is variable lfptype, rfptype : valid_fpstate; begin lfptype := classfp (x); rfptype := classfp (y); if (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan or lfptype = isx or rfptype = isx) then return true; else return false; end if; end function Unordered; function Finite ( x : UNRESOLVED_float) return BOOLEAN is variable fp_state : valid_fpstate; -- fp state begin fp_state := Classfp (x); if (fp_state = pos_inf) or (fp_state = neg_inf) then return true; else return false; end if; end function Finite; function Isnan ( x : UNRESOLVED_float) return BOOLEAN is variable fp_state : valid_fpstate; -- fp state begin fp_state := Classfp (x); if (fp_state = nan) or (fp_state = quiet_nan) then return true; else return false; end if; end function Isnan; -- Function to return constants. function zerofp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is constant result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin return result; end function zerofp; function nanfp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1" result (-1) := '1'; -- MSB of Fraction "1" -- Note: From W. Khan "IEEE Standard 754 for Binary Floating Point" -- The difference between a signaling NAN and a quiet NAN is that -- the MSB of the Fraction is a "1" in a Signaling NAN, and is a -- "0" in a quiet NAN. return result; end function nanfp; function qnanfp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1" result (-fraction_width) := '1'; -- LSB of Fraction "1" -- (Could have been any bit) return result; end function qnanfp; function pos_inffp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1" return result; end function pos_inffp; function neg_inffp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width downto 0) := (others => '1'); -- top bits all "1" return result; end function neg_inffp; function neg_zerofp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width) := '1'; return result; end function neg_zerofp; -- size_res versions function zerofp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return zerofp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function zerofp; function nanfp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return nanfp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function nanfp; function qnanfp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return qnanfp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function qnanfp; function pos_inffp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return pos_inffp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function pos_inffp; function neg_inffp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return neg_inffp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function neg_inffp; function neg_zerofp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return neg_zerofp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function neg_zerofp; -- Textio functions -- purpose: writes float into a line (NOTE changed basetype) type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error); type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER; type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC; type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus; constant NBSP : CHARACTER := CHARACTER'val(160); -- space character constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-"; constant char_to_MVL9 : MVL9_indexed_by_char := ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U'); constant char_to_MVL9plus : MVL9plus_indexed_by_char := ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error); -- purpose: Skips white space procedure skip_whitespace ( L : inout LINE) is variable readOk : BOOLEAN; variable c : CHARACTER; begin while L /= null and L.all'length /= 0 loop c := l (l'left); if (c = ' ' or c = NBSP or c = HT) then read (l, c, readOk); else exit; end if; end loop; end procedure skip_whitespace; -- purpose: Checks the punctuation in a line procedure check_punctuation ( arg : in STRING; colon : out BOOLEAN; -- There was a colon in the line dot : out BOOLEAN; -- There was a dot in the line good : out BOOLEAN; -- True if enough characters found chars : in INTEGER) is -- Examples. Legal inputs are "0000000", "0000.000", "0:000:000" alias xarg : STRING (1 to arg'length) is arg; -- make it downto range variable icolon, idot : BOOLEAN; -- internal variable j : INTEGER := 0; -- charters read begin good := false; icolon := false; idot := false; for i in 1 to arg'length loop if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j = chars then exit; elsif xarg(i) = ':' then icolon := true; elsif xarg(i) = '.' then idot := true; elsif xarg (i) /= '_' then j := j + 1; end if; end loop; if j = chars then good := true; -- There are enough charactes to read end if; colon := icolon; if idot and icolon then dot := false; else dot := idot; end if; end procedure check_punctuation; -- purpose: Searches a line for a ":" and replaces it with a ".". procedure fix_colon ( arg : inout STRING; chars : in integer) is alias xarg : STRING (1 to arg'length) is arg; -- make it downto range variable j : INTEGER := 0; -- charters read begin for i in 1 to arg'length loop if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j > chars then exit; elsif xarg(i) = ':' then xarg (i) := '.'; elsif xarg (i) /= '_' then j := j + 1; end if; end loop; end procedure fix_colon; procedure WRITE ( L : inout LINE; -- input line VALUE : in UNRESOLVED_float; -- floating point input JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable s : STRING(1 to value'high - value'low +3); variable sindx : INTEGER; begin -- function write s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high))); s(2) := ':'; sindx := 3; for i in VALUE'high-1 downto 0 loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; s(sindx) := ':'; sindx := sindx + 1; for i in -1 downto VALUE'low loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; WRITE (L, s, JUSTIFIED, FIELD); end procedure WRITE; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float) is -- Possible data: 0:0000:0000000 -- 000000000000 variable c : CHARACTER; variable mv : UNRESOLVED_float (VALUE'range); variable readOk : BOOLEAN; variable lastu : BOOLEAN := false; -- last character was an "_" variable i : INTEGER; -- index variable begin -- READ VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); READ (l, c, readOk); if VALUE'length > 0 then i := value'high; readloop : loop if readOk = false then -- Bail out if there was a bad read report float_generic_pkg'instance_name & "READ(float): " & "Error end of file encountered." severity error; return; elsif c = ' ' or c = CR or c = HT then -- reading done. if (i /= value'low) then report float_generic_pkg'instance_name & "READ(float): " & "Warning: Value truncated." severity warning; return; end if; elsif c = '_' then if i = value'high then -- Begins with an "_" report float_generic_pkg'instance_name & "READ(float): " & "String begins with an ""_""" severity error; return; elsif lastu then -- "__" detected report float_generic_pkg'instance_name & "READ(float): " & "Two underscores detected in input string ""__""" severity error; return; else lastu := true; end if; elsif c = ':' or c = '.' then -- separator, ignore if not (i = -1 or i = value'high-1) then report float_generic_pkg'instance_name & "READ(float): " & "Warning: Separator point does not match number format: '" & c & "' encountered at location " & INTEGER'image(i) & "." severity warning; end if; lastu := false; elsif (char_to_MVL9plus(c) = error) then report float_generic_pkg'instance_name & "READ(float): " & "Error: Character '" & c & "' read, expected STD_ULOGIC literal." severity error; return; else mv (i) := char_to_MVL9(c); i := i - 1; if i < value'low then VALUE := mv; return; end if; lastu := false; end if; READ (l, c, readOk); end loop readloop; end if; end procedure READ; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is -- Possible data: 0:0000:0000000 -- 000000000000 variable c : CHARACTER; variable mv : UNRESOLVED_float (VALUE'range); variable lastu : BOOLEAN := false; -- last character was an "_" variable i : INTEGER; -- index variable variable readOk : BOOLEAN; begin -- READ VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); READ (l, c, readOk); if VALUE'length > 0 then i := value'high; good := false; readloop : loop if readOk = false then -- Bail out if there was a bad read return; elsif c = ' ' or c = CR or c = HT then -- reading done return; elsif c = '_' then if i = 0 then -- Begins with an "_" return; elsif lastu then -- "__" detected return; else lastu := true; end if; elsif c = ':' or c = '.' then -- separator, ignore -- good := (i = -1 or i = value'high-1); lastu := false; elsif (char_to_MVL9plus(c) = error) then return; else mv (i) := char_to_MVL9(c); i := i - 1; if i < value'low then good := true; VALUE := mv; return; end if; lastu := false; end if; READ (l, c, readOk); end loop readloop; else good := true; -- read into a null array end if; end procedure READ; procedure OWRITE ( L : inout LINE; -- access type (pointer) VALUE : in UNRESOLVED_float; -- value to write JUSTIFIED : in SIDE := right; -- which side to justify text FIELD : in WIDTH := 0) is -- width of field begin WRITE (L => L, VALUE => to_ostring(VALUE), JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure OWRITE; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is constant ne : INTEGER := ((value'length+2)/3) 3; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/3); if not ok then report float_generic_pkg'instance_name & "OREAD: " & "short string encounted: " & L.all & " needs to have " & integer'image (ne/3) & " valid octal characters." severity error; return; elsif dot then OREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "OREAD: " & "error encounted reading STRING " & L.all severity error; return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then OREAD (L, nybble, ok); -- read the sign bit if not ok then report float_generic_pkg'instance_name & "OREAD: " & "End of string encountered" severity error; return; elsif nybble (2 downto 1) /= "00" then report float_generic_pkg'instance_name & "OREAD: " & "Illegal sign bit STRING encounted " severity error; return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/3); -- replaces the colon with a ".". OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "OREAD: " & "error encounted reading STRING " & L.all severity error; return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else OREAD (L, slv, ok); if not ok then report float_generic_pkg'instance_name & "OREAD: " & "Error encounted during read" severity error; return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then report float_generic_pkg'instance_name & "OREAD: " & "Vector truncated." severity error; return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; end if; end procedure OREAD; procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" GOOD := false; Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/3); if not ok then return; elsif dot then OREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then OREAD (L, nybble, ok); -- read the sign bit if not ok then return; elsif nybble (2 downto 1) /= "00" then return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/3); -- replaces the colon with a ".". OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else OREAD (L, slv, ok); if not ok then return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; GOOD := true; end if; end procedure OREAD; procedure HWRITE ( L : inout LINE; -- access type (pointer) VALUE : in UNRESOLVED_float; -- value to write JUSTIFIED : in SIDE := right; -- which side to justify text FIELD : in WIDTH := 0) is -- width of field begin WRITE (L => L, VALUE => to_hstring(VALUE), JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure HWRITE; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/4); if not ok then report float_generic_pkg'instance_name & "HREAD: " & "short string encounted: " & L.all & " needs to have " & integer'image (ne/4) & " valid hex characters." severity error; return; elsif dot then HREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "HREAD: " & "error encounted reading STRING " & L.all severity error; return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then HREAD (L, nybble, ok); -- read the sign bit if not ok then report float_generic_pkg'instance_name & "HREAD: " & "End of string encountered" severity error; return; elsif nybble (3 downto 1) /= "000" then report float_generic_pkg'instance_name & "HREAD: " & "Illegal sign bit STRING encounted " severity error; return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/4); -- replaces the colon with a ".". HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "HREAD: " & "error encounted reading STRING " & L.all severity error; return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else HREAD (L, slv, ok); if not ok then report float_generic_pkg'instance_name & "HREAD: " & "Error encounted during read" severity error; return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then report float_generic_pkg'instance_name & "HREAD: " & "Vector truncated." severity error; return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; end if; end procedure HREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" GOOD := false; Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/4); if not ok then return; elsif dot then HREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then HREAD (L, nybble, ok); -- read the sign bit if not ok then return; elsif nybble (3 downto 1) /= "000" then return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/4); -- replaces the colon with a ".". HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else HREAD (L, slv, ok); if not ok then return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; GOOD := true; end if; end procedure HREAD; function to_string (value : UNRESOLVED_float) return STRING is variable s : STRING(1 to value'high - value'low +3); variable sindx : INTEGER; begin -- function write s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high))); s(2) := ':'; sindx := 3; for i in VALUE'high-1 downto 0 loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; s(sindx) := ':'; sindx := sindx + 1; for i in -1 downto VALUE'low loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; return s; end function to_string; function to_hstring (value : UNRESOLVED_float) return STRING is variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0); begin floop : for i in slv'range loop slv(i) := to_X01Z (value(i + value'low)); end loop floop; return to_hstring (slv); end function to_hstring; function to_ostring (value : UNRESOLVED_float) return STRING is variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0); begin floop : for i in slv'range loop slv(i) := to_X01Z (value(i + value'low)); end loop floop; return to_ostring (slv); end function to_ostring; function from_string ( bstring : STRING; -- binary string constant exponent_width : NATURAL := float_exponent_width; constant fraction_width : NATURAL := float_fraction_width) return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable L : LINE; variable good : BOOLEAN; begin L := new STRING'(bstring); READ (L, result, good); deallocate (L); assert (good) report FLOAT_GENERIC_PKG'instance_name & "from_string: Bad string " & bstring severity error; return result; end function from_string; function from_ostring ( ostring : STRING; -- Octal string constant exponent_width : NATURAL := float_exponent_width; constant fraction_width : NATURAL := float_fraction_width) return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable L : LINE; variable good : BOOLEAN; begin L := new STRING'(ostring); OREAD (L, result, good); deallocate (L); assert (good) report FLOAT_GENERIC_PKG'instance_name & "from_ostring: Bad string " & ostring severity error; return result; end function from_ostring; function from_hstring ( hstring : STRING; -- hex string constant exponent_width : NATURAL := float_exponent_width; constant fraction_width : NATURAL := float_fraction_width) return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable L : LINE; variable good : BOOLEAN; begin L := new STRING'(hstring); HREAD (L, result, good); deallocate (L); assert (good) report FLOAT_GENERIC_PKG'instance_name & "from_hstring: Bad string " & hstring severity error; return result; end function from_hstring; function from_string ( bstring : STRING; -- binary string size_res : UNRESOLVED_float) -- used for sizing only return UNRESOLVED_float is begin return from_string (bstring => bstring, exponent_width => size_res'high, fraction_width => -size_res'low); end function from_string; function from_ostring ( ostring : STRING; -- Octal string size_res : UNRESOLVED_float) -- used for sizing only return UNRESOLVED_float is begin return from_ostring (ostring => ostring, exponent_width => size_res'high, fraction_width => -size_res'low); end function from_ostring; function from_hstring ( hstring : STRING; -- hex string size_res : UNRESOLVED_float) -- used for sizing only return UNRESOLVED_float is begin return from_hstring (hstring => hstring, exponent_width => size_res'high, fraction_width => -size_res'low); end function from_hstring; end package body float_generic_pkg;
------------------------------------------------------------------------------------- -- Copyright (c) 2006, University of Kansas - Hybridthreads Group -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- * Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- * Redistributions in binary form must reproduce the above copyright notice, -- this list of conditions and the following disclaimer in the documentation -- and/or other materials provided with the distribution. -- * Neither the name of the University of Kansas nor the name of the -- Hybridthreads Group nor the names of its contributors may be used to -- endorse or promote products derived from this software without specific -- prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use work.common.all; entity mutex_store is generic ( C_AWIDTH : integer := 32; C_DWIDTH : integer := 32; C_TWIDTH : integer := 8; C_MWIDTH : integer := 6; C_CWIDTH : integer := 8 ); port ( clk : in std_logic; rst : in std_logic; miaddr : in std_logic_vector(0 to C_MWIDTH-1); miena : in std_logic; miwea : in std_logic; miowner : in std_logic_vector(0 to C_TWIDTH-1); minext : in std_logic_vector(0 to C_TWIDTH-1); milast : in std_logic_vector(0 to C_TWIDTH-1); mikind : in std_logic_vector(0 to 1); micount : in std_logic_vector(0 to C_CWIDTH-1); sysrst : in std_logic; rstdone : out std_logic; moowner : out std_logic_vector(0 to C_TWIDTH-1); monext : out std_logic_vector(0 to C_TWIDTH-1); molast : out std_logic_vector(0 to C_TWIDTH-1); mokind : out std_logic_vector(0 to 1); mocount : out std_logic_vector(0 to C_CWIDTH-1) ); end mutex_store; architecture behavioral of mutex_store is -- Calculate the number of mutexes to use constant MUTEXES : integer := pow2( C_MWIDTH ); -- Constant for the last position to be reset constant RST_END : std_logic_vector(0 to C_MWIDTH-1) := (others => '1'); -- Calculate the beginning and ending bit positions for data constant OWN_SRT : integer := 0; constant OWN_END : integer := OWN_SRT + C_TWIDTH-1; constant NXT_SRT : integer := OWN_END+1; constant NXT_END : integer := NXT_SRT + C_TWIDTH-1; constant LST_SRT : integer := NXT_END+1; constant LST_END : integer := LST_SRT + C_TWIDTH-1; constant KND_SRT : integer := LST_END+1; constant KND_END : integer := KND_SRT + 1; constant CNT_SRT : integer := KND_END + 1; constant CNT_END : integer := CNT_SRT + C_CWIDTH-1; -- Declare a storage area for the mutex data type mstore is array(0 to MUTEXES-1) of std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); -- Declare signals for the mutex storage area signal store : mstore; signal mena : std_logic; signal mwea : std_logic; signal maddr : std_logic_vector(0 to C_MWIDTH-1); signal minput : std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); signal moutput : std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1); -- Type for the reset state machine type rststate is ( IDLE, RESET ); -- Declare signals for the reset signal rena : std_logic; signal rwea : std_logic; signal rst_cs : rststate; signal raddr : std_logic_vector(0 to C_MWIDTH-1); signal raddrn : std_logic_vector(0 to C_MWIDTH-1); signal rowner : std_logic_vector(0 to C_TWIDTH-1); signal rnext : std_logic_vector(0 to C_TWIDTH-1); signal rlast : std_logic_vector(0 to C_TWIDTH-1); signal rkind : std_logic_vector(0 to 1); signal rcount : std_logic_vector(0 to C_CWIDTH-1); begin moowner <= moutput(OWN_SRT to OWN_END); monext <= moutput(NXT_SRT to NXT_END); molast <= moutput(LST_SRT to LST_END); mokind <= moutput(KND_SRT to KND_END); mocount <= moutput(CNT_SRT to CNT_END); mutex_mux : process(clk,rst,sysrst,rena,rwea,raddr,rowner,rnext,rlast,rkind,rcount, miena,miwea,miaddr,miowner,milast,mikind,micount) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then mena <= rena; mwea <= rwea; maddr <= raddr; minput <= rowner & rnext & rlast & rkind & rcount; else mena <= miena; mwea <= miwea; maddr <= miaddr; minput <= miowner & minext & milast & mikind & micount; end if; end if; end process mutex_mux; mutex_reset_controller : process(clk,rst) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then rst_cs <= RESET; raddr <= raddrn; else rst_cs <= IDLE; end if; end if; end process mutex_reset_controller; mutex_reset_logic : process(rst_cs,raddr) is begin rena <= '1'; rwea <= '1'; rstdone <= '1'; rowner <= (others => '0'); rnext <= (others => '0'); rlast <= (others => '0'); rkind <= (others => '0'); rcount <= (others => '0'); case rst_cs is when IDLE => raddrn <= (others => '0'); when RESET => if( raddr = RST_END ) then raddrn <= raddr; else rstdone <= '0'; raddrn <= raddr + 1; end if; end case; end process mutex_reset_logic; mutex_store_controller : process (clk) is begin if( rising_edge(clk) ) then if( mena = '1' ) then if( mwea = '1' ) then store( conv_integer(maddr) ) <= minput; end if; moutput <= store( conv_integer(maddr) ); end if; end if; end process mutex_store_controller; end behavioral;
------------------------------------------------------------------------------------- -- Copyright (c) 2006, University of Kansas - Hybridthreads Group -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- * Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- * Redistributions in binary form must reproduce the above copyright notice, -- this list of conditions and the following disclaimer in the documentation -- and/or other materials provided with the distribution. -- * Neither the name of the University of Kansas nor the name of the -- Hybridthreads Group nor the names of its contributors may be used to -- endorse or promote products derived from this software without specific -- prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use work.common.all; entity mutex_store is generic ( C_AWIDTH : integer := 32; C_DWIDTH : integer := 32; C_TWIDTH : integer := 8; C_MWIDTH : integer := 6; C_CWIDTH : integer := 8 ); port ( clk : in std_logic; rst : in std_logic; miaddr : in std_logic_vector(0 to C_MWIDTH-1); miena : in std_logic; miwea : in std_logic; miowner : in std_logic_vector(0 to C_TWIDTH-1); minext : in std_logic_vector(0 to C_TWIDTH-1); milast : in std_logic_vector(0 to C_TWIDTH-1); mikind : in std_logic_vector(0 to 1); micount : in std_logic_vector(0 to C_CWIDTH-1); sysrst : in std_logic; rstdone : out std_logic; moowner : out std_logic_vector(0 to C_TWIDTH-1); monext : out std_logic_vector(0 to C_TWIDTH-1); molast : out std_logic_vector(0 to C_TWIDTH-1); mokind : out std_logic_vector(0 to 1); mocount : out std_logic_vector(0 to C_CWIDTH-1) ); end mutex_store; architecture behavioral of mutex_store is -- Calculate the number of mutexes to use constant MUTEXES : integer := pow2( C_MWIDTH ); -- Constant for the last position to be reset constant RST_END : std_logic_vector(0 to C_MWIDTH-1) := (others => '1'); -- Calculate the beginning and ending bit positions for data constant OWN_SRT : integer := 0; constant OWN_END : integer := OWN_SRT + C_TWIDTH-1; constant NXT_SRT : integer := OWN_END+1; constant NXT_END : integer := NXT_SRT + C_TWIDTH-1; constant LST_SRT : integer := NXT_END+1; constant LST_END : integer := LST_SRT + C_TWIDTH-1; constant KND_SRT : integer := LST_END+1; constant KND_END : integer := KND_SRT + 1; constant CNT_SRT : integer := KND_END + 1; constant CNT_END : integer := CNT_SRT + C_CWIDTH-1; -- Declare a storage area for the mutex data type mstore is array(0 to MUTEXES-1) of std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); -- Declare signals for the mutex storage area signal store : mstore; signal mena : std_logic; signal mwea : std_logic; signal maddr : std_logic_vector(0 to C_MWIDTH-1); signal minput : std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); signal moutput : std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1); -- Type for the reset state machine type rststate is ( IDLE, RESET ); -- Declare signals for the reset signal rena : std_logic; signal rwea : std_logic; signal rst_cs : rststate; signal raddr : std_logic_vector(0 to C_MWIDTH-1); signal raddrn : std_logic_vector(0 to C_MWIDTH-1); signal rowner : std_logic_vector(0 to C_TWIDTH-1); signal rnext : std_logic_vector(0 to C_TWIDTH-1); signal rlast : std_logic_vector(0 to C_TWIDTH-1); signal rkind : std_logic_vector(0 to 1); signal rcount : std_logic_vector(0 to C_CWIDTH-1); begin moowner <= moutput(OWN_SRT to OWN_END); monext <= moutput(NXT_SRT to NXT_END); molast <= moutput(LST_SRT to LST_END); mokind <= moutput(KND_SRT to KND_END); mocount <= moutput(CNT_SRT to CNT_END); mutex_mux : process(clk,rst,sysrst,rena,rwea,raddr,rowner,rnext,rlast,rkind,rcount, miena,miwea,miaddr,miowner,milast,mikind,micount) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then mena <= rena; mwea <= rwea; maddr <= raddr; minput <= rowner & rnext & rlast & rkind & rcount; else mena <= miena; mwea <= miwea; maddr <= miaddr; minput <= miowner & minext & milast & mikind & micount; end if; end if; end process mutex_mux; mutex_reset_controller : process(clk,rst) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then rst_cs <= RESET; raddr <= raddrn; else rst_cs <= IDLE; end if; end if; end process mutex_reset_controller; mutex_reset_logic : process(rst_cs,raddr) is begin rena <= '1'; rwea <= '1'; rstdone <= '1'; rowner <= (others => '0'); rnext <= (others => '0'); rlast <= (others => '0'); rkind <= (others => '0'); rcount <= (others => '0'); case rst_cs is when IDLE => raddrn <= (others => '0'); when RESET => if( raddr = RST_END ) then raddrn <= raddr; else rstdone <= '0'; raddrn <= raddr + 1; end if; end case; end process mutex_reset_logic; mutex_store_controller : process (clk) is begin if( rising_edge(clk) ) then if( mena = '1' ) then if( mwea = '1' ) then store( conv_integer(maddr) ) <= minput; end if; moutput <= store( conv_integer(maddr) ); end if; end if; end process mutex_store_controller; end behavioral;
------------------------------------------------------------------------------------- -- Copyright (c) 2006, University of Kansas - Hybridthreads Group -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- * Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- * Redistributions in binary form must reproduce the above copyright notice, -- this list of conditions and the following disclaimer in the documentation -- and/or other materials provided with the distribution. -- * Neither the name of the University of Kansas nor the name of the -- Hybridthreads Group nor the names of its contributors may be used to -- endorse or promote products derived from this software without specific -- prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use work.common.all; entity mutex_store is generic ( C_AWIDTH : integer := 32; C_DWIDTH : integer := 32; C_TWIDTH : integer := 8; C_MWIDTH : integer := 6; C_CWIDTH : integer := 8 ); port ( clk : in std_logic; rst : in std_logic; miaddr : in std_logic_vector(0 to C_MWIDTH-1); miena : in std_logic; miwea : in std_logic; miowner : in std_logic_vector(0 to C_TWIDTH-1); minext : in std_logic_vector(0 to C_TWIDTH-1); milast : in std_logic_vector(0 to C_TWIDTH-1); mikind : in std_logic_vector(0 to 1); micount : in std_logic_vector(0 to C_CWIDTH-1); sysrst : in std_logic; rstdone : out std_logic; moowner : out std_logic_vector(0 to C_TWIDTH-1); monext : out std_logic_vector(0 to C_TWIDTH-1); molast : out std_logic_vector(0 to C_TWIDTH-1); mokind : out std_logic_vector(0 to 1); mocount : out std_logic_vector(0 to C_CWIDTH-1) ); end mutex_store; architecture behavioral of mutex_store is -- Calculate the number of mutexes to use constant MUTEXES : integer := pow2( C_MWIDTH ); -- Constant for the last position to be reset constant RST_END : std_logic_vector(0 to C_MWIDTH-1) := (others => '1'); -- Calculate the beginning and ending bit positions for data constant OWN_SRT : integer := 0; constant OWN_END : integer := OWN_SRT + C_TWIDTH-1; constant NXT_SRT : integer := OWN_END+1; constant NXT_END : integer := NXT_SRT + C_TWIDTH-1; constant LST_SRT : integer := NXT_END+1; constant LST_END : integer := LST_SRT + C_TWIDTH-1; constant KND_SRT : integer := LST_END+1; constant KND_END : integer := KND_SRT + 1; constant CNT_SRT : integer := KND_END + 1; constant CNT_END : integer := CNT_SRT + C_CWIDTH-1; -- Declare a storage area for the mutex data type mstore is array(0 to MUTEXES-1) of std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); -- Declare signals for the mutex storage area signal store : mstore; signal mena : std_logic; signal mwea : std_logic; signal maddr : std_logic_vector(0 to C_MWIDTH-1); signal minput : std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); signal moutput : std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1); -- Type for the reset state machine type rststate is ( IDLE, RESET ); -- Declare signals for the reset signal rena : std_logic; signal rwea : std_logic; signal rst_cs : rststate; signal raddr : std_logic_vector(0 to C_MWIDTH-1); signal raddrn : std_logic_vector(0 to C_MWIDTH-1); signal rowner : std_logic_vector(0 to C_TWIDTH-1); signal rnext : std_logic_vector(0 to C_TWIDTH-1); signal rlast : std_logic_vector(0 to C_TWIDTH-1); signal rkind : std_logic_vector(0 to 1); signal rcount : std_logic_vector(0 to C_CWIDTH-1); begin moowner <= moutput(OWN_SRT to OWN_END); monext <= moutput(NXT_SRT to NXT_END); molast <= moutput(LST_SRT to LST_END); mokind <= moutput(KND_SRT to KND_END); mocount <= moutput(CNT_SRT to CNT_END); mutex_mux : process(clk,rst,sysrst,rena,rwea,raddr,rowner,rnext,rlast,rkind,rcount, miena,miwea,miaddr,miowner,milast,mikind,micount) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then mena <= rena; mwea <= rwea; maddr <= raddr; minput <= rowner & rnext & rlast & rkind & rcount; else mena <= miena; mwea <= miwea; maddr <= miaddr; minput <= miowner & minext & milast & mikind & micount; end if; end if; end process mutex_mux; mutex_reset_controller : process(clk,rst) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then rst_cs <= RESET; raddr <= raddrn; else rst_cs <= IDLE; end if; end if; end process mutex_reset_controller; mutex_reset_logic : process(rst_cs,raddr) is begin rena <= '1'; rwea <= '1'; rstdone <= '1'; rowner <= (others => '0'); rnext <= (others => '0'); rlast <= (others => '0'); rkind <= (others => '0'); rcount <= (others => '0'); case rst_cs is when IDLE => raddrn <= (others => '0'); when RESET => if( raddr = RST_END ) then raddrn <= raddr; else rstdone <= '0'; raddrn <= raddr + 1; end if; end case; end process mutex_reset_logic; mutex_store_controller : process (clk) is begin if( rising_edge(clk) ) then if( mena = '1' ) then if( mwea = '1' ) then store( conv_integer(maddr) ) <= minput; end if; moutput <= store( conv_integer(maddr) ); end if; end if; end process mutex_store_controller; end behavioral;
------------------------------------------------------------------------------------- -- Copyright (c) 2006, University of Kansas - Hybridthreads Group -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- * Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- * Redistributions in binary form must reproduce the above copyright notice, -- this list of conditions and the following disclaimer in the documentation -- and/or other materials provided with the distribution. -- * Neither the name of the University of Kansas nor the name of the -- Hybridthreads Group nor the names of its contributors may be used to -- endorse or promote products derived from this software without specific -- prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use work.common.all; entity mutex_store is generic ( C_AWIDTH : integer := 32; C_DWIDTH : integer := 32; C_TWIDTH : integer := 8; C_MWIDTH : integer := 6; C_CWIDTH : integer := 8 ); port ( clk : in std_logic; rst : in std_logic; miaddr : in std_logic_vector(0 to C_MWIDTH-1); miena : in std_logic; miwea : in std_logic; miowner : in std_logic_vector(0 to C_TWIDTH-1); minext : in std_logic_vector(0 to C_TWIDTH-1); milast : in std_logic_vector(0 to C_TWIDTH-1); mikind : in std_logic_vector(0 to 1); micount : in std_logic_vector(0 to C_CWIDTH-1); sysrst : in std_logic; rstdone : out std_logic; moowner : out std_logic_vector(0 to C_TWIDTH-1); monext : out std_logic_vector(0 to C_TWIDTH-1); molast : out std_logic_vector(0 to C_TWIDTH-1); mokind : out std_logic_vector(0 to 1); mocount : out std_logic_vector(0 to C_CWIDTH-1) ); end mutex_store; architecture behavioral of mutex_store is -- Calculate the number of mutexes to use constant MUTEXES : integer := pow2( C_MWIDTH ); -- Constant for the last position to be reset constant RST_END : std_logic_vector(0 to C_MWIDTH-1) := (others => '1'); -- Calculate the beginning and ending bit positions for data constant OWN_SRT : integer := 0; constant OWN_END : integer := OWN_SRT + C_TWIDTH-1; constant NXT_SRT : integer := OWN_END+1; constant NXT_END : integer := NXT_SRT + C_TWIDTH-1; constant LST_SRT : integer := NXT_END+1; constant LST_END : integer := LST_SRT + C_TWIDTH-1; constant KND_SRT : integer := LST_END+1; constant KND_END : integer := KND_SRT + 1; constant CNT_SRT : integer := KND_END + 1; constant CNT_END : integer := CNT_SRT + C_CWIDTH-1; -- Declare a storage area for the mutex data type mstore is array(0 to MUTEXES-1) of std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); -- Declare signals for the mutex storage area signal store : mstore; signal mena : std_logic; signal mwea : std_logic; signal maddr : std_logic_vector(0 to C_MWIDTH-1); signal minput : std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); signal moutput : std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1); -- Type for the reset state machine type rststate is ( IDLE, RESET ); -- Declare signals for the reset signal rena : std_logic; signal rwea : std_logic; signal rst_cs : rststate; signal raddr : std_logic_vector(0 to C_MWIDTH-1); signal raddrn : std_logic_vector(0 to C_MWIDTH-1); signal rowner : std_logic_vector(0 to C_TWIDTH-1); signal rnext : std_logic_vector(0 to C_TWIDTH-1); signal rlast : std_logic_vector(0 to C_TWIDTH-1); signal rkind : std_logic_vector(0 to 1); signal rcount : std_logic_vector(0 to C_CWIDTH-1); begin moowner <= moutput(OWN_SRT to OWN_END); monext <= moutput(NXT_SRT to NXT_END); molast <= moutput(LST_SRT to LST_END); mokind <= moutput(KND_SRT to KND_END); mocount <= moutput(CNT_SRT to CNT_END); mutex_mux : process(clk,rst,sysrst,rena,rwea,raddr,rowner,rnext,rlast,rkind,rcount, miena,miwea,miaddr,miowner,milast,mikind,micount) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then mena <= rena; mwea <= rwea; maddr <= raddr; minput <= rowner & rnext & rlast & rkind & rcount; else mena <= miena; mwea <= miwea; maddr <= miaddr; minput <= miowner & minext & milast & mikind & micount; end if; end if; end process mutex_mux; mutex_reset_controller : process(clk,rst) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then rst_cs <= RESET; raddr <= raddrn; else rst_cs <= IDLE; end if; end if; end process mutex_reset_controller; mutex_reset_logic : process(rst_cs,raddr) is begin rena <= '1'; rwea <= '1'; rstdone <= '1'; rowner <= (others => '0'); rnext <= (others => '0'); rlast <= (others => '0'); rkind <= (others => '0'); rcount <= (others => '0'); case rst_cs is when IDLE => raddrn <= (others => '0'); when RESET => if( raddr = RST_END ) then raddrn <= raddr; else rstdone <= '0'; raddrn <= raddr + 1; end if; end case; end process mutex_reset_logic; mutex_store_controller : process (clk) is begin if( rising_edge(clk) ) then if( mena = '1' ) then if( mwea = '1' ) then store( conv_integer(maddr) ) <= minput; end if; moutput <= store( conv_integer(maddr) ); end if; end if; end process mutex_store_controller; end behavioral;
------------------------------------------------------------------------------------- -- Copyright (c) 2006, University of Kansas - Hybridthreads Group -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- * Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- * Redistributions in binary form must reproduce the above copyright notice, -- this list of conditions and the following disclaimer in the documentation -- and/or other materials provided with the distribution. -- * Neither the name of the University of Kansas nor the name of the -- Hybridthreads Group nor the names of its contributors may be used to -- endorse or promote products derived from this software without specific -- prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use work.common.all; entity mutex_store is generic ( C_AWIDTH : integer := 32; C_DWIDTH : integer := 32; C_TWIDTH : integer := 8; C_MWIDTH : integer := 6; C_CWIDTH : integer := 8 ); port ( clk : in std_logic; rst : in std_logic; miaddr : in std_logic_vector(0 to C_MWIDTH-1); miena : in std_logic; miwea : in std_logic; miowner : in std_logic_vector(0 to C_TWIDTH-1); minext : in std_logic_vector(0 to C_TWIDTH-1); milast : in std_logic_vector(0 to C_TWIDTH-1); mikind : in std_logic_vector(0 to 1); micount : in std_logic_vector(0 to C_CWIDTH-1); sysrst : in std_logic; rstdone : out std_logic; moowner : out std_logic_vector(0 to C_TWIDTH-1); monext : out std_logic_vector(0 to C_TWIDTH-1); molast : out std_logic_vector(0 to C_TWIDTH-1); mokind : out std_logic_vector(0 to 1); mocount : out std_logic_vector(0 to C_CWIDTH-1) ); end mutex_store; architecture behavioral of mutex_store is -- Calculate the number of mutexes to use constant MUTEXES : integer := pow2( C_MWIDTH ); -- Constant for the last position to be reset constant RST_END : std_logic_vector(0 to C_MWIDTH-1) := (others => '1'); -- Calculate the beginning and ending bit positions for data constant OWN_SRT : integer := 0; constant OWN_END : integer := OWN_SRT + C_TWIDTH-1; constant NXT_SRT : integer := OWN_END+1; constant NXT_END : integer := NXT_SRT + C_TWIDTH-1; constant LST_SRT : integer := NXT_END+1; constant LST_END : integer := LST_SRT + C_TWIDTH-1; constant KND_SRT : integer := LST_END+1; constant KND_END : integer := KND_SRT + 1; constant CNT_SRT : integer := KND_END + 1; constant CNT_END : integer := CNT_SRT + C_CWIDTH-1; -- Declare a storage area for the mutex data type mstore is array(0 to MUTEXES-1) of std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); -- Declare signals for the mutex storage area signal store : mstore; signal mena : std_logic; signal mwea : std_logic; signal maddr : std_logic_vector(0 to C_MWIDTH-1); signal minput : std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); signal moutput : std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1); -- Type for the reset state machine type rststate is ( IDLE, RESET ); -- Declare signals for the reset signal rena : std_logic; signal rwea : std_logic; signal rst_cs : rststate; signal raddr : std_logic_vector(0 to C_MWIDTH-1); signal raddrn : std_logic_vector(0 to C_MWIDTH-1); signal rowner : std_logic_vector(0 to C_TWIDTH-1); signal rnext : std_logic_vector(0 to C_TWIDTH-1); signal rlast : std_logic_vector(0 to C_TWIDTH-1); signal rkind : std_logic_vector(0 to 1); signal rcount : std_logic_vector(0 to C_CWIDTH-1); begin moowner <= moutput(OWN_SRT to OWN_END); monext <= moutput(NXT_SRT to NXT_END); molast <= moutput(LST_SRT to LST_END); mokind <= moutput(KND_SRT to KND_END); mocount <= moutput(CNT_SRT to CNT_END); mutex_mux : process(clk,rst,sysrst,rena,rwea,raddr,rowner,rnext,rlast,rkind,rcount, miena,miwea,miaddr,miowner,milast,mikind,micount) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then mena <= rena; mwea <= rwea; maddr <= raddr; minput <= rowner & rnext & rlast & rkind & rcount; else mena <= miena; mwea <= miwea; maddr <= miaddr; minput <= miowner & minext & milast & mikind & micount; end if; end if; end process mutex_mux; mutex_reset_controller : process(clk,rst) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then rst_cs <= RESET; raddr <= raddrn; else rst_cs <= IDLE; end if; end if; end process mutex_reset_controller; mutex_reset_logic : process(rst_cs,raddr) is begin rena <= '1'; rwea <= '1'; rstdone <= '1'; rowner <= (others => '0'); rnext <= (others => '0'); rlast <= (others => '0'); rkind <= (others => '0'); rcount <= (others => '0'); case rst_cs is when IDLE => raddrn <= (others => '0'); when RESET => if( raddr = RST_END ) then raddrn <= raddr; else rstdone <= '0'; raddrn <= raddr + 1; end if; end case; end process mutex_reset_logic; mutex_store_controller : process (clk) is begin if( rising_edge(clk) ) then if( mena = '1' ) then if( mwea = '1' ) then store( conv_integer(maddr) ) <= minput; end if; moutput <= store( conv_integer(maddr) ); end if; end if; end process mutex_store_controller; end behavioral;
------------------------------------------------------------------------------------- -- Copyright (c) 2006, University of Kansas - Hybridthreads Group -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- * Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- * Redistributions in binary form must reproduce the above copyright notice, -- this list of conditions and the following disclaimer in the documentation -- and/or other materials provided with the distribution. -- * Neither the name of the University of Kansas nor the name of the -- Hybridthreads Group nor the names of its contributors may be used to -- endorse or promote products derived from this software without specific -- prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use work.common.all; entity mutex_store is generic ( C_AWIDTH : integer := 32; C_DWIDTH : integer := 32; C_TWIDTH : integer := 8; C_MWIDTH : integer := 6; C_CWIDTH : integer := 8 ); port ( clk : in std_logic; rst : in std_logic; miaddr : in std_logic_vector(0 to C_MWIDTH-1); miena : in std_logic; miwea : in std_logic; miowner : in std_logic_vector(0 to C_TWIDTH-1); minext : in std_logic_vector(0 to C_TWIDTH-1); milast : in std_logic_vector(0 to C_TWIDTH-1); mikind : in std_logic_vector(0 to 1); micount : in std_logic_vector(0 to C_CWIDTH-1); sysrst : in std_logic; rstdone : out std_logic; moowner : out std_logic_vector(0 to C_TWIDTH-1); monext : out std_logic_vector(0 to C_TWIDTH-1); molast : out std_logic_vector(0 to C_TWIDTH-1); mokind : out std_logic_vector(0 to 1); mocount : out std_logic_vector(0 to C_CWIDTH-1) ); end mutex_store; architecture behavioral of mutex_store is -- Calculate the number of mutexes to use constant MUTEXES : integer := pow2( C_MWIDTH ); -- Constant for the last position to be reset constant RST_END : std_logic_vector(0 to C_MWIDTH-1) := (others => '1'); -- Calculate the beginning and ending bit positions for data constant OWN_SRT : integer := 0; constant OWN_END : integer := OWN_SRT + C_TWIDTH-1; constant NXT_SRT : integer := OWN_END+1; constant NXT_END : integer := NXT_SRT + C_TWIDTH-1; constant LST_SRT : integer := NXT_END+1; constant LST_END : integer := LST_SRT + C_TWIDTH-1; constant KND_SRT : integer := LST_END+1; constant KND_END : integer := KND_SRT + 1; constant CNT_SRT : integer := KND_END + 1; constant CNT_END : integer := CNT_SRT + C_CWIDTH-1; -- Declare a storage area for the mutex data type mstore is array(0 to MUTEXES-1) of std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); -- Declare signals for the mutex storage area signal store : mstore; signal mena : std_logic; signal mwea : std_logic; signal maddr : std_logic_vector(0 to C_MWIDTH-1); signal minput : std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); signal moutput : std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1); -- Type for the reset state machine type rststate is ( IDLE, RESET ); -- Declare signals for the reset signal rena : std_logic; signal rwea : std_logic; signal rst_cs : rststate; signal raddr : std_logic_vector(0 to C_MWIDTH-1); signal raddrn : std_logic_vector(0 to C_MWIDTH-1); signal rowner : std_logic_vector(0 to C_TWIDTH-1); signal rnext : std_logic_vector(0 to C_TWIDTH-1); signal rlast : std_logic_vector(0 to C_TWIDTH-1); signal rkind : std_logic_vector(0 to 1); signal rcount : std_logic_vector(0 to C_CWIDTH-1); begin moowner <= moutput(OWN_SRT to OWN_END); monext <= moutput(NXT_SRT to NXT_END); molast <= moutput(LST_SRT to LST_END); mokind <= moutput(KND_SRT to KND_END); mocount <= moutput(CNT_SRT to CNT_END); mutex_mux : process(clk,rst,sysrst,rena,rwea,raddr,rowner,rnext,rlast,rkind,rcount, miena,miwea,miaddr,miowner,milast,mikind,micount) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then mena <= rena; mwea <= rwea; maddr <= raddr; minput <= rowner & rnext & rlast & rkind & rcount; else mena <= miena; mwea <= miwea; maddr <= miaddr; minput <= miowner & minext & milast & mikind & micount; end if; end if; end process mutex_mux; mutex_reset_controller : process(clk,rst) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then rst_cs <= RESET; raddr <= raddrn; else rst_cs <= IDLE; end if; end if; end process mutex_reset_controller; mutex_reset_logic : process(rst_cs,raddr) is begin rena <= '1'; rwea <= '1'; rstdone <= '1'; rowner <= (others => '0'); rnext <= (others => '0'); rlast <= (others => '0'); rkind <= (others => '0'); rcount <= (others => '0'); case rst_cs is when IDLE => raddrn <= (others => '0'); when RESET => if( raddr = RST_END ) then raddrn <= raddr; else rstdone <= '0'; raddrn <= raddr + 1; end if; end case; end process mutex_reset_logic; mutex_store_controller : process (clk) is begin if( rising_edge(clk) ) then if( mena = '1' ) then if( mwea = '1' ) then store( conv_integer(maddr) ) <= minput; end if; moutput <= store( conv_integer(maddr) ); end if; end if; end process mutex_store_controller; end behavioral;
------------------------------------------------------------------------------------- -- Copyright (c) 2006, University of Kansas - Hybridthreads Group -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- * Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- * Redistributions in binary form must reproduce the above copyright notice, -- this list of conditions and the following disclaimer in the documentation -- and/or other materials provided with the distribution. -- * Neither the name of the University of Kansas nor the name of the -- Hybridthreads Group nor the names of its contributors may be used to -- endorse or promote products derived from this software without specific -- prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use work.common.all; entity mutex_store is generic ( C_AWIDTH : integer := 32; C_DWIDTH : integer := 32; C_TWIDTH : integer := 8; C_MWIDTH : integer := 6; C_CWIDTH : integer := 8 ); port ( clk : in std_logic; rst : in std_logic; miaddr : in std_logic_vector(0 to C_MWIDTH-1); miena : in std_logic; miwea : in std_logic; miowner : in std_logic_vector(0 to C_TWIDTH-1); minext : in std_logic_vector(0 to C_TWIDTH-1); milast : in std_logic_vector(0 to C_TWIDTH-1); mikind : in std_logic_vector(0 to 1); micount : in std_logic_vector(0 to C_CWIDTH-1); sysrst : in std_logic; rstdone : out std_logic; moowner : out std_logic_vector(0 to C_TWIDTH-1); monext : out std_logic_vector(0 to C_TWIDTH-1); molast : out std_logic_vector(0 to C_TWIDTH-1); mokind : out std_logic_vector(0 to 1); mocount : out std_logic_vector(0 to C_CWIDTH-1) ); end mutex_store; architecture behavioral of mutex_store is -- Calculate the number of mutexes to use constant MUTEXES : integer := pow2( C_MWIDTH ); -- Constant for the last position to be reset constant RST_END : std_logic_vector(0 to C_MWIDTH-1) := (others => '1'); -- Calculate the beginning and ending bit positions for data constant OWN_SRT : integer := 0; constant OWN_END : integer := OWN_SRT + C_TWIDTH-1; constant NXT_SRT : integer := OWN_END+1; constant NXT_END : integer := NXT_SRT + C_TWIDTH-1; constant LST_SRT : integer := NXT_END+1; constant LST_END : integer := LST_SRT + C_TWIDTH-1; constant KND_SRT : integer := LST_END+1; constant KND_END : integer := KND_SRT + 1; constant CNT_SRT : integer := KND_END + 1; constant CNT_END : integer := CNT_SRT + C_CWIDTH-1; -- Declare a storage area for the mutex data type mstore is array(0 to MUTEXES-1) of std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); -- Declare signals for the mutex storage area signal store : mstore; signal mena : std_logic; signal mwea : std_logic; signal maddr : std_logic_vector(0 to C_MWIDTH-1); signal minput : std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); signal moutput : std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1); -- Type for the reset state machine type rststate is ( IDLE, RESET ); -- Declare signals for the reset signal rena : std_logic; signal rwea : std_logic; signal rst_cs : rststate; signal raddr : std_logic_vector(0 to C_MWIDTH-1); signal raddrn : std_logic_vector(0 to C_MWIDTH-1); signal rowner : std_logic_vector(0 to C_TWIDTH-1); signal rnext : std_logic_vector(0 to C_TWIDTH-1); signal rlast : std_logic_vector(0 to C_TWIDTH-1); signal rkind : std_logic_vector(0 to 1); signal rcount : std_logic_vector(0 to C_CWIDTH-1); begin moowner <= moutput(OWN_SRT to OWN_END); monext <= moutput(NXT_SRT to NXT_END); molast <= moutput(LST_SRT to LST_END); mokind <= moutput(KND_SRT to KND_END); mocount <= moutput(CNT_SRT to CNT_END); mutex_mux : process(clk,rst,sysrst,rena,rwea,raddr,rowner,rnext,rlast,rkind,rcount, miena,miwea,miaddr,miowner,milast,mikind,micount) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then mena <= rena; mwea <= rwea; maddr <= raddr; minput <= rowner & rnext & rlast & rkind & rcount; else mena <= miena; mwea <= miwea; maddr <= miaddr; minput <= miowner & minext & milast & mikind & micount; end if; end if; end process mutex_mux; mutex_reset_controller : process(clk,rst) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then rst_cs <= RESET; raddr <= raddrn; else rst_cs <= IDLE; end if; end if; end process mutex_reset_controller; mutex_reset_logic : process(rst_cs,raddr) is begin rena <= '1'; rwea <= '1'; rstdone <= '1'; rowner <= (others => '0'); rnext <= (others => '0'); rlast <= (others => '0'); rkind <= (others => '0'); rcount <= (others => '0'); case rst_cs is when IDLE => raddrn <= (others => '0'); when RESET => if( raddr = RST_END ) then raddrn <= raddr; else rstdone <= '0'; raddrn <= raddr + 1; end if; end case; end process mutex_reset_logic; mutex_store_controller : process (clk) is begin if( rising_edge(clk) ) then if( mena = '1' ) then if( mwea = '1' ) then store( conv_integer(maddr) ) <= minput; end if; moutput <= store( conv_integer(maddr) ); end if; end if; end process mutex_store_controller; end behavioral;
------------------------------------------------------------------------------------- -- Copyright (c) 2006, University of Kansas - Hybridthreads Group -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- * Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- * Redistributions in binary form must reproduce the above copyright notice, -- this list of conditions and the following disclaimer in the documentation -- and/or other materials provided with the distribution. -- * Neither the name of the University of Kansas nor the name of the -- Hybridthreads Group nor the names of its contributors may be used to -- endorse or promote products derived from this software without specific -- prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use work.common.all; entity mutex_store is generic ( C_AWIDTH : integer := 32; C_DWIDTH : integer := 32; C_TWIDTH : integer := 8; C_MWIDTH : integer := 6; C_CWIDTH : integer := 8 ); port ( clk : in std_logic; rst : in std_logic; miaddr : in std_logic_vector(0 to C_MWIDTH-1); miena : in std_logic; miwea : in std_logic; miowner : in std_logic_vector(0 to C_TWIDTH-1); minext : in std_logic_vector(0 to C_TWIDTH-1); milast : in std_logic_vector(0 to C_TWIDTH-1); mikind : in std_logic_vector(0 to 1); micount : in std_logic_vector(0 to C_CWIDTH-1); sysrst : in std_logic; rstdone : out std_logic; moowner : out std_logic_vector(0 to C_TWIDTH-1); monext : out std_logic_vector(0 to C_TWIDTH-1); molast : out std_logic_vector(0 to C_TWIDTH-1); mokind : out std_logic_vector(0 to 1); mocount : out std_logic_vector(0 to C_CWIDTH-1) ); end mutex_store; architecture behavioral of mutex_store is -- Calculate the number of mutexes to use constant MUTEXES : integer := pow2( C_MWIDTH ); -- Constant for the last position to be reset constant RST_END : std_logic_vector(0 to C_MWIDTH-1) := (others => '1'); -- Calculate the beginning and ending bit positions for data constant OWN_SRT : integer := 0; constant OWN_END : integer := OWN_SRT + C_TWIDTH-1; constant NXT_SRT : integer := OWN_END+1; constant NXT_END : integer := NXT_SRT + C_TWIDTH-1; constant LST_SRT : integer := NXT_END+1; constant LST_END : integer := LST_SRT + C_TWIDTH-1; constant KND_SRT : integer := LST_END+1; constant KND_END : integer := KND_SRT + 1; constant CNT_SRT : integer := KND_END + 1; constant CNT_END : integer := CNT_SRT + C_CWIDTH-1; -- Declare a storage area for the mutex data type mstore is array(0 to MUTEXES-1) of std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); -- Declare signals for the mutex storage area signal store : mstore; signal mena : std_logic; signal mwea : std_logic; signal maddr : std_logic_vector(0 to C_MWIDTH-1); signal minput : std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); signal moutput : std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1); -- Type for the reset state machine type rststate is ( IDLE, RESET ); -- Declare signals for the reset signal rena : std_logic; signal rwea : std_logic; signal rst_cs : rststate; signal raddr : std_logic_vector(0 to C_MWIDTH-1); signal raddrn : std_logic_vector(0 to C_MWIDTH-1); signal rowner : std_logic_vector(0 to C_TWIDTH-1); signal rnext : std_logic_vector(0 to C_TWIDTH-1); signal rlast : std_logic_vector(0 to C_TWIDTH-1); signal rkind : std_logic_vector(0 to 1); signal rcount : std_logic_vector(0 to C_CWIDTH-1); begin moowner <= moutput(OWN_SRT to OWN_END); monext <= moutput(NXT_SRT to NXT_END); molast <= moutput(LST_SRT to LST_END); mokind <= moutput(KND_SRT to KND_END); mocount <= moutput(CNT_SRT to CNT_END); mutex_mux : process(clk,rst,sysrst,rena,rwea,raddr,rowner,rnext,rlast,rkind,rcount, miena,miwea,miaddr,miowner,milast,mikind,micount) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then mena <= rena; mwea <= rwea; maddr <= raddr; minput <= rowner & rnext & rlast & rkind & rcount; else mena <= miena; mwea <= miwea; maddr <= miaddr; minput <= miowner & minext & milast & mikind & micount; end if; end if; end process mutex_mux; mutex_reset_controller : process(clk,rst) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then rst_cs <= RESET; raddr <= raddrn; else rst_cs <= IDLE; end if; end if; end process mutex_reset_controller; mutex_reset_logic : process(rst_cs,raddr) is begin rena <= '1'; rwea <= '1'; rstdone <= '1'; rowner <= (others => '0'); rnext <= (others => '0'); rlast <= (others => '0'); rkind <= (others => '0'); rcount <= (others => '0'); case rst_cs is when IDLE => raddrn <= (others => '0'); when RESET => if( raddr = RST_END ) then raddrn <= raddr; else rstdone <= '0'; raddrn <= raddr + 1; end if; end case; end process mutex_reset_logic; mutex_store_controller : process (clk) is begin if( rising_edge(clk) ) then if( mena = '1' ) then if( mwea = '1' ) then store( conv_integer(maddr) ) <= minput; end if; moutput <= store( conv_integer(maddr) ); end if; end if; end process mutex_store_controller; end behavioral;
------------------------------------------------------------------------------------- -- Copyright (c) 2006, University of Kansas - Hybridthreads Group -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- * Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- * Redistributions in binary form must reproduce the above copyright notice, -- this list of conditions and the following disclaimer in the documentation -- and/or other materials provided with the distribution. -- * Neither the name of the University of Kansas nor the name of the -- Hybridthreads Group nor the names of its contributors may be used to -- endorse or promote products derived from this software without specific -- prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use work.common.all; entity mutex_store is generic ( C_AWIDTH : integer := 32; C_DWIDTH : integer := 32; C_TWIDTH : integer := 8; C_MWIDTH : integer := 6; C_CWIDTH : integer := 8 ); port ( clk : in std_logic; rst : in std_logic; miaddr : in std_logic_vector(0 to C_MWIDTH-1); miena : in std_logic; miwea : in std_logic; miowner : in std_logic_vector(0 to C_TWIDTH-1); minext : in std_logic_vector(0 to C_TWIDTH-1); milast : in std_logic_vector(0 to C_TWIDTH-1); mikind : in std_logic_vector(0 to 1); micount : in std_logic_vector(0 to C_CWIDTH-1); sysrst : in std_logic; rstdone : out std_logic; moowner : out std_logic_vector(0 to C_TWIDTH-1); monext : out std_logic_vector(0 to C_TWIDTH-1); molast : out std_logic_vector(0 to C_TWIDTH-1); mokind : out std_logic_vector(0 to 1); mocount : out std_logic_vector(0 to C_CWIDTH-1) ); end mutex_store; architecture behavioral of mutex_store is -- Calculate the number of mutexes to use constant MUTEXES : integer := pow2( C_MWIDTH ); -- Constant for the last position to be reset constant RST_END : std_logic_vector(0 to C_MWIDTH-1) := (others => '1'); -- Calculate the beginning and ending bit positions for data constant OWN_SRT : integer := 0; constant OWN_END : integer := OWN_SRT + C_TWIDTH-1; constant NXT_SRT : integer := OWN_END+1; constant NXT_END : integer := NXT_SRT + C_TWIDTH-1; constant LST_SRT : integer := NXT_END+1; constant LST_END : integer := LST_SRT + C_TWIDTH-1; constant KND_SRT : integer := LST_END+1; constant KND_END : integer := KND_SRT + 1; constant CNT_SRT : integer := KND_END + 1; constant CNT_END : integer := CNT_SRT + C_CWIDTH-1; -- Declare a storage area for the mutex data type mstore is array(0 to MUTEXES-1) of std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); -- Declare signals for the mutex storage area signal store : mstore; signal mena : std_logic; signal mwea : std_logic; signal maddr : std_logic_vector(0 to C_MWIDTH-1); signal minput : std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); signal moutput : std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1); -- Type for the reset state machine type rststate is ( IDLE, RESET ); -- Declare signals for the reset signal rena : std_logic; signal rwea : std_logic; signal rst_cs : rststate; signal raddr : std_logic_vector(0 to C_MWIDTH-1); signal raddrn : std_logic_vector(0 to C_MWIDTH-1); signal rowner : std_logic_vector(0 to C_TWIDTH-1); signal rnext : std_logic_vector(0 to C_TWIDTH-1); signal rlast : std_logic_vector(0 to C_TWIDTH-1); signal rkind : std_logic_vector(0 to 1); signal rcount : std_logic_vector(0 to C_CWIDTH-1); begin moowner <= moutput(OWN_SRT to OWN_END); monext <= moutput(NXT_SRT to NXT_END); molast <= moutput(LST_SRT to LST_END); mokind <= moutput(KND_SRT to KND_END); mocount <= moutput(CNT_SRT to CNT_END); mutex_mux : process(clk,rst,sysrst,rena,rwea,raddr,rowner,rnext,rlast,rkind,rcount, miena,miwea,miaddr,miowner,milast,mikind,micount) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then mena <= rena; mwea <= rwea; maddr <= raddr; minput <= rowner & rnext & rlast & rkind & rcount; else mena <= miena; mwea <= miwea; maddr <= miaddr; minput <= miowner & minext & milast & mikind & micount; end if; end if; end process mutex_mux; mutex_reset_controller : process(clk,rst) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then rst_cs <= RESET; raddr <= raddrn; else rst_cs <= IDLE; end if; end if; end process mutex_reset_controller; mutex_reset_logic : process(rst_cs,raddr) is begin rena <= '1'; rwea <= '1'; rstdone <= '1'; rowner <= (others => '0'); rnext <= (others => '0'); rlast <= (others => '0'); rkind <= (others => '0'); rcount <= (others => '0'); case rst_cs is when IDLE => raddrn <= (others => '0'); when RESET => if( raddr = RST_END ) then raddrn <= raddr; else rstdone <= '0'; raddrn <= raddr + 1; end if; end case; end process mutex_reset_logic; mutex_store_controller : process (clk) is begin if( rising_edge(clk) ) then if( mena = '1' ) then if( mwea = '1' ) then store( conv_integer(maddr) ) <= minput; end if; moutput <= store( conv_integer(maddr) ); end if; end if; end process mutex_store_controller; end behavioral;
------------------------------------------------------------------------------------- -- Copyright (c) 2006, University of Kansas - Hybridthreads Group -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- * Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- * Redistributions in binary form must reproduce the above copyright notice, -- this list of conditions and the following disclaimer in the documentation -- and/or other materials provided with the distribution. -- * Neither the name of the University of Kansas nor the name of the -- Hybridthreads Group nor the names of its contributors may be used to -- endorse or promote products derived from this software without specific -- prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use work.common.all; entity mutex_store is generic ( C_AWIDTH : integer := 32; C_DWIDTH : integer := 32; C_TWIDTH : integer := 8; C_MWIDTH : integer := 6; C_CWIDTH : integer := 8 ); port ( clk : in std_logic; rst : in std_logic; miaddr : in std_logic_vector(0 to C_MWIDTH-1); miena : in std_logic; miwea : in std_logic; miowner : in std_logic_vector(0 to C_TWIDTH-1); minext : in std_logic_vector(0 to C_TWIDTH-1); milast : in std_logic_vector(0 to C_TWIDTH-1); mikind : in std_logic_vector(0 to 1); micount : in std_logic_vector(0 to C_CWIDTH-1); sysrst : in std_logic; rstdone : out std_logic; moowner : out std_logic_vector(0 to C_TWIDTH-1); monext : out std_logic_vector(0 to C_TWIDTH-1); molast : out std_logic_vector(0 to C_TWIDTH-1); mokind : out std_logic_vector(0 to 1); mocount : out std_logic_vector(0 to C_CWIDTH-1) ); end mutex_store; architecture behavioral of mutex_store is -- Calculate the number of mutexes to use constant MUTEXES : integer := pow2( C_MWIDTH ); -- Constant for the last position to be reset constant RST_END : std_logic_vector(0 to C_MWIDTH-1) := (others => '1'); -- Calculate the beginning and ending bit positions for data constant OWN_SRT : integer := 0; constant OWN_END : integer := OWN_SRT + C_TWIDTH-1; constant NXT_SRT : integer := OWN_END+1; constant NXT_END : integer := NXT_SRT + C_TWIDTH-1; constant LST_SRT : integer := NXT_END+1; constant LST_END : integer := LST_SRT + C_TWIDTH-1; constant KND_SRT : integer := LST_END+1; constant KND_END : integer := KND_SRT + 1; constant CNT_SRT : integer := KND_END + 1; constant CNT_END : integer := CNT_SRT + C_CWIDTH-1; -- Declare a storage area for the mutex data type mstore is array(0 to MUTEXES-1) of std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); -- Declare signals for the mutex storage area signal store : mstore; signal mena : std_logic; signal mwea : std_logic; signal maddr : std_logic_vector(0 to C_MWIDTH-1); signal minput : std_logic_vector(0 to 3C_TWIDTH+C_CWIDTH+1); signal moutput : std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1); -- Type for the reset state machine type rststate is ( IDLE, RESET ); -- Declare signals for the reset signal rena : std_logic; signal rwea : std_logic; signal rst_cs : rststate; signal raddr : std_logic_vector(0 to C_MWIDTH-1); signal raddrn : std_logic_vector(0 to C_MWIDTH-1); signal rowner : std_logic_vector(0 to C_TWIDTH-1); signal rnext : std_logic_vector(0 to C_TWIDTH-1); signal rlast : std_logic_vector(0 to C_TWIDTH-1); signal rkind : std_logic_vector(0 to 1); signal rcount : std_logic_vector(0 to C_CWIDTH-1); begin moowner <= moutput(OWN_SRT to OWN_END); monext <= moutput(NXT_SRT to NXT_END); molast <= moutput(LST_SRT to LST_END); mokind <= moutput(KND_SRT to KND_END); mocount <= moutput(CNT_SRT to CNT_END); mutex_mux : process(clk,rst,sysrst,rena,rwea,raddr,rowner,rnext,rlast,rkind,rcount, miena,miwea,miaddr,miowner,milast,mikind,micount) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then mena <= rena; mwea <= rwea; maddr <= raddr; minput <= rowner & rnext & rlast & rkind & rcount; else mena <= miena; mwea <= miwea; maddr <= miaddr; minput <= miowner & minext & milast & mikind & micount; end if; end if; end process mutex_mux; mutex_reset_controller : process(clk,rst) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then rst_cs <= RESET; raddr <= raddrn; else rst_cs <= IDLE; end if; end if; end process mutex_reset_controller; mutex_reset_logic : process(rst_cs,raddr) is begin rena <= '1'; rwea <= '1'; rstdone <= '1'; rowner <= (others => '0'); rnext <= (others => '0'); rlast <= (others => '0'); rkind <= (others => '0'); rcount <= (others => '0'); case rst_cs is when IDLE => raddrn <= (others => '0'); when RESET => if( raddr = RST_END ) then raddrn <= raddr; else rstdone <= '0'; raddrn <= raddr + 1; end if; end case; end process mutex_reset_logic; mutex_store_controller : process (clk) is begin if( rising_edge(clk) ) then if( mena = '1' ) then if( mwea = '1' ) then store( conv_integer(maddr) ) <= minput; end if; moutput <= store( conv_integer(maddr) ); end if; end if; end process mutex_store_controller; end behavioral;
entity e is end entity; architecture a of e is function f return boolean is begin return false; end function; begin assert f report "message" severity note; end architecture;
--------------------------------------------------- -- School: University of Massachusetts Dartmouth -- Department: Computer and Electrical Engineering -- Engineer: Daniel Noyes -- -- Create Date: SPRING 2014 -- Module Name: counter -- Project Name: CLOCK COUNTER -- Target Devices: Spartan-3E -- Tool versions: Xilinx ISE 14.7 -- Description: Clock toplevel -- Top level design of the clock counter --------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.all; entity clock_toplevel is Port ( CLK : in STD_LOGIC; -- 50 MHz Oscillator BTN : in STD_LOGIC; -- Reset Button SW : in STD_LOGIC_VECTOR (1 downto 0); -- Switch 0:add/sub, 1: clk speed LED : out STD_LOGIC_VECTOR (7 downto 0)); end clock_toplevel; architecture Structural of clock_toplevel is signal CLOCK_DIVIDER : STD_LOGIC := '0'; -- Divided Clock Output signal CLK2 : STD_LOGIC := '0'; -- 2 HZ line signal CLK4 : STD_LOGIC := '0'; -- 4 HZ line begin ----- Structural Components: ----- clk2Hz: entity work.clk2Hz port map( CLK_IN => CLK, RST => BTN, CLK_OUT => CLK2); clk4Hz: entity work.clk4Hz port map( CLK_IN => CLK, RST => BTN, CLK_OUT => CLK4); mux1: entity work.mux_2to1 port map( SEL => SW(1), IN_1 => CLK2, IN_2 => CLK4, MOUT => CLOCK_DIVIDER); counter: entity work.counter port map( CLK => CLOCK_DIVIDER, DIRECTION => SW(0), RST => BTN, COUNT_OUT => LED); ----- End Structural Components ----- end Structural;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.aua_types.all; entity aua is port ( clk_in : in std_logic; reset_pin : in std_logic; switch_pins : in std_logic_vector(15 downto 0); led_pins : out std_logic_vector(15 downto 0); digit0_pins : out std_logic_vector(6 downto 0); digit1_pins : out std_logic_vector(6 downto 0); digit2_pins : out std_logic_vector(6 downto 0); digit3_pins : out std_logic_vector(6 downto 0); digit4_pins : out std_logic_vector(6 downto 0); digit5_pins : out std_logic_vector(6 downto 0); sram_addr : out std_logic_vector(RAM_ADDR_SIZE-1 downto 0); sram_dq : inout word_t; sram_we : out std_logic; -- sram_oe : out std_logic; sram_ub : out std_logic; sram_lb : out std_logic; -- sram_ce : out std_logic txd : out std_logic; rxd : in std_logic --~ ncts : in std_logic; --~ nrts : out std_logic ); end aua; architecture sat1 of aua is component aua_pll is port( areset : in std_logic; inclk0 : in std_logic; c0 : out std_logic ); end component; component ent_if is generic ( INIT_VECTOR : pc_t ); port ( clk : in std_logic; reset : in std_logic; -- pipeline register outputs opcode_out : out opcode_t; dest_out : out reg_t; pc_out : out pc_t; pcnxt_out : out pc_t; rega_out : out reg_t; regb_out : out reg_t; imm_out : out std_logic_vector(7 downto 0); -- asynchron register outputs async_rega : out reg_t; async_regb : out reg_t; -- branches (from ID) pc_in : in pc_t; branch : in std_logic; -- cache instr_addr : out word_t; instr_valid : in std_logic; instr_data : in word_t; -- interlock lock : in std_logic ); end component; component id is port ( clk : in std_logic; reset : in std_logic; -- pipeline register inputs opcode_in : in opcode_t; dest_in : in reg_t; pc_in : in pc_t; pcnxt_in : in pc_t; rega_in : in reg_t; regb_in : in reg_t; imm_in : in std_logic_vector(7 downto 0); -- asynchron register inputs async_rega : in reg_t; async_regb : in reg_t; -- results from wb to reg file regr : in reg_t; valr : in word_t; -- pipeline register outputs opcode_out : out opcode_t; dest_out : out reg_t; opa_out : out word_t; opb_out : out word_t; -- needed for EX forwarding rega_out : out reg_t; regb_out : out reg_t; opb_isfrom_regb : out boolean; -- branch decision pc_out : out pc_t; branch_out : out std_logic; -- interlock lock : in std_logic; id_locks : out std_logic ); end component; component ex is port ( clk : in std_logic; reset : in std_logic; -- pipeline register inputs opcode : in opcode_t; dest_in : in reg_t; opa : in word_t; opb : in word_t; -- pipeline register outputs dest_out : out reg_t; result_out : out word_t; -- interface to MMU mmu_address : out word_t; mmu_result : in word_t; mmu_st_data : out word_t; mmu_enable : out std_logic; mmu_opcode : out std_logic_vector(1 downto 0); mmu_done : in std_logic; -- pipeline interlock ex_locks : out std_ulogic; ex_locks_async : out std_ulogic ); end component; component instr_cache is port ( clk : in std_logic; reset : in std_logic; -- cache/if id_instr_addr : in word_t; id_instr_valid : out std_logic; id_instr : out word_t; -- cache/mmu mmu_instr_addr : out word_t; mmu_enable : out std_logic; mmu_instr_valid : in std_logic; mmu_instr : in word_t ); end component; component mmu is generic ( CLK_FREQ : natural; SRAM_RD_FREQ : natural; SRAM_WR_FREQ : natural ); port ( clk : in std_logic; reset : in std_logic; -- IF stage instr_addr : in word_t; instr_enable: in std_logic; instr_data : out word_t; instr_valid : out std_logic; -- interface to EX stage ex_address : in word_t; ex_rd_data : out word_t; ex_wr_data : in word_t; ex_enable : in std_logic; ex_opcode : in std_logic_vector(1 downto 0); ex_done : out std_logic; -- SimpCon interface to IO devices sc_io_in : in sc_in_t; sc_io_out : out sc_out_t; -- interface to SRAM sram_addr : out std_logic_vector(RAM_ADDR_SIZE-1 downto 0); sram_dq : inout word_t; sram_we : out std_logic; -- write enable, low active, 0=enable, 1=disable -- sram_oe : out std_logic; -- output enable, low active sram_ub : out std_logic; -- upper byte, low active sram_lb : out std_logic -- lower byte, low active -- sram_ce : out std_logic -- chip enable, low active ); end component; component sc_de2_switches is port ( clk : in std_logic; reset : in std_logic; -- SimpCon slave interface to IO ctrl address : in sc_addr_t; wr_data : in sc_data_t; rd : in std_logic; wr : in std_logic; rd_data : out sc_data_t; rdy_cnt : out sc_rdy_cnt_t; -- pins switch_pins : in std_logic_vector(15 downto 0); led_pins : out std_logic_vector(15 downto 0) ); end component; component sc_de2_digits is port ( clk : in std_logic; reset : in std_logic; -- SimpCon slave interface to IO ctrl address : in sc_addr_t; wr_data : in sc_data_t; rd : in std_logic; wr : in std_logic; rd_data : out sc_data_t; rdy_cnt : out sc_rdy_cnt_t; -- pins digit0_pins : out std_logic_vector(6 downto 0); digit1_pins : out std_logic_vector(6 downto 0); digit2_pins : out std_logic_vector(6 downto 0); digit3_pins : out std_logic_vector(6 downto 0); digit4_pins : out std_logic_vector(6 downto 0); digit5_pins : out std_logic_vector(6 downto 0) ); end component; component sc_uart is generic( clk_freq : integer; baud_rate : integer; txf_depth : integer; txf_thres : integer; rxf_depth : integer; rxf_thres : integer ); port ( clk : in std_logic; reset : in std_logic; -- SimpCon slave interface to IO ctrl address : in sc_addr_t; wr_data : in sc_data_t; rd : in std_logic; wr : in std_logic; rd_data : out sc_data_t; rdy_cnt : out sc_rdy_cnt_t; -- pins txd : out std_logic; rxd : in std_logic; ncts : in std_logic; nrts : out std_logic ); end component; component sc_test_slave is port ( clk : in std_logic; reset : in std_logic; -- SimpCon slave interface to IO ctrl address : in sc_addr_t; wr_data : in sc_data_t; rd : in std_logic; wr : in std_logic; rd_data : out sc_data_t; rdy_cnt : out sc_rdy_cnt_t ); end component; signal reset : std_logic; -- clk Signal aus PLL signal clk : std_logic; -- pipeline registers (written by top) -- IF/ID signal ifid_opcode_out : opcode_t; signal ifid_dest_out : reg_t; signal ifid_pc_out : pc_t; signal ifid_pcnxt_out : pc_t; signal ifid_rega_out : reg_t; signal ifid_regb_out : reg_t; signal ifid_async_rega_out : reg_t; signal ifid_async_regb_out : reg_t; signal ifid_imm_out : std_logic_vector(7 downto 0); -- ID/IF signal idif_pc_out : pc_t; signal idif_branch_out : std_logic; -- ID/EX signal idex_opcode_out : opcode_t; signal idex_dest_out : reg_t; signal idex_opa_out : word_t; signal idex_opb_out : word_t; -- EX/ID (for WB) signal exid_dest_out : reg_t; signal exid_result_out : word_t; -- pipeline registers (read by top) -- IF/ID signal ifid_opcode_in : opcode_t; signal ifid_dest_in : reg_t; signal ifid_pc_in : pc_t; signal ifid_pcnxt_in : pc_t; signal ifid_rega_in : reg_t; signal ifid_regb_in : reg_t; signal ifid_async_rega_in : reg_t; signal ifid_async_regb_in : reg_t; signal ifid_imm_in : std_logic_vector(7 downto 0); -- ID/IF signal idif_pc_in : pc_t; signal idif_branch_in : std_logic; -- ID/EX signal idex_opcode_in : opcode_t; signal idex_dest_in : reg_t; signal idex_opa_in : word_t; signal idex_opb_in : word_t; -- EX/ID (for WB) signal exid_dest_in : reg_t; signal exid_result_in : word_t; -- IF/CACHE/MMU signal ifcache_addr : word_t; signal ifcache_data : word_t; signal ifcache_valid : std_logic; signal cachemmu_addr : word_t; signal cachemmu_data : word_t; signal cachemmu_valid : std_logic; signal cachemmu_enable : std_logic; -- MMU interfaces -- EX/MMU signal exmmu_address : word_t; signal exmmu_result_mmu : word_t; signal exmmu_wr_data : word_t; signal exmmu_enable : std_logic; signal exmmu_mmu_opcode : std_logic_vector(1 downto 0); signal exmmu_valid : std_logic; -- MMU/IO signal mmuio_out : sc_out_t; signal mmuio_outa : sc_out_at; signal mmuio_in : sc_in_t; signal mmuio_ina : sc_in_at; --forwarding signal id_rega_in : reg_t; signal id_regb_in : reg_t; signal id_opb_isfrom_regb : boolean; signal exid_dest : reg_t; signal exid_result : word_t; --interlocks signal ex_locks : std_logic; signal ex_locks_async : std_logic; signal lock_if : std_logic; signal lock_id : std_logic; signal id_locks_async : std_logic; -- IO helpers signal sc_sel, sc_sel_reg : integer range 0 to 2*SC_ADDR_BITS; -- one more than needed (for NC) signal sc_addr : sc_addr_t; signal reset_sync : std_logic; -- reset pin is async! so we synchronize it: see sync_reset signal reset_pll : std_logic; begin cmp_pll: aua_pll port map(reset_pll, clk_in, clk); cmp_if: ent_if generic map(RST_VECTOR) port map(clk, reset, ifid_opcode_in, ifid_dest_in, ifid_pc_in, ifid_pcnxt_in, ifid_rega_in, ifid_regb_in, ifid_imm_in, ifid_async_rega_in, ifid_async_regb_in, idif_pc_out, idif_branch_out, ifcache_addr, ifcache_valid, ifcache_data, lock_if); cmp_id: id port map(clk, reset, ifid_opcode_out, ifid_dest_out, ifid_pc_out, ifid_pcnxt_out, ifid_rega_out, ifid_regb_out, ifid_imm_out, ifid_async_rega_out, ifid_async_regb_out, exid_dest_out, exid_result_out, idex_opcode_in, idex_dest_in, idex_opa_in, idex_opb_in, id_rega_in, id_regb_in, id_opb_isfrom_regb, idif_pc_in, idif_branch_in, lock_id, id_locks_async); cmp_ex: ex port map(clk, reset, idex_opcode_out, idex_dest_out, idex_opa_out, idex_opb_out, exid_dest_in, exid_result_in, exmmu_address, exmmu_result_mmu, exmmu_wr_data, exmmu_enable, exmmu_mmu_opcode, exmmu_valid, ex_locks, ex_locks_async); cmp_icache: instr_cache port map(clk, reset, ifcache_addr, ifcache_valid, ifcache_data, cachemmu_addr, cachemmu_enable, cachemmu_valid, cachemmu_data); cmp_mmu: mmu generic map(CLK_FREQ, SRAM_RD_FREQ, SRAM_WR_FREQ) port map(clk, reset, cachemmu_addr, cachemmu_enable, cachemmu_data, cachemmu_valid, exmmu_address, exmmu_result_mmu, exmmu_wr_data, exmmu_enable, exmmu_mmu_opcode, exmmu_valid, mmuio_in, mmuio_out, sram_addr, sram_dq, sram_we, sram_ub, sram_lb); -- taken from http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf sync_reset: process (clk, reset_pin) begin if (reset_pin = '0') then reset_sync <= '1'; reset <= '1'; elsif rising_edge(clk) then reset_sync <= '0'; reset <= reset_sync; end if; end process; reset_pll <= not reset_pin; -- needs to be async (think about it. :) ifid_opcode_out <= ifid_opcode_in; ifid_dest_out <= ifid_dest_in; ifid_pc_out <= ifid_pc_in; ifid_pcnxt_out <= ifid_pcnxt_in; ifid_rega_out <= ifid_rega_in; ifid_regb_out <= ifid_regb_in; ifid_async_rega_out <= ifid_async_rega_in; ifid_async_regb_out <= ifid_async_regb_in; ifid_imm_out <= ifid_imm_in; idif_pc_out <= idif_pc_in; idif_branch_out <= idif_branch_in; idex_opcode_out <= idex_opcode_in; idex_dest_out <= idex_dest_in; exid_dest_out <= exid_dest_in; exid_result_out <= exid_result_in; lock_if <= ex_locks_async or id_locks_async; lock_id <= ex_locks_async; ex_fw: process(id_rega_in, id_regb_in, exid_dest, exid_result, idex_opa_in, idex_opb_in, id_opb_isfrom_regb, ex_locks) begin if id_rega_in = exid_dest and ex_locks = '0' then idex_opa_out <= exid_result; else idex_opa_out <= idex_opa_in; end if; if id_regb_in = exid_dest and id_opb_isfrom_regb and ex_locks = '0' then idex_opb_out <= exid_result; else idex_opb_out <= idex_opb_in; end if; end process; sync: process (clk, reset) begin if reset = '1' then exid_dest <= (others => '0'); exid_result <= (others => '0'); elsif rising_edge(clk) then exid_dest <= exid_dest_in; exid_result <= exid_result_in; end if; end process; sc_sync: process(clk, reset) begin if (reset='1') then sc_sel_reg <= 0; -- sc_sel_reg <= SC_SLAVE_CNT; -- would be correct, but does not work on all devices; procudes warning elsif rising_edge(clk) then sc_sel_reg <= sc_sel; end if; end process; sc_in_mux: process (mmuio_ina, sc_sel_reg) begin if sc_sel_reg /= SC_SLAVE_CNT then mmuio_in.rd_data <= mmuio_ina(sc_sel_reg).rd_data; mmuio_in.rdy_cnt <= mmuio_ina(sc_sel_reg).rdy_cnt; else mmuio_in.rd_data <= (others => '0'); mmuio_in.rdy_cnt <= (others => '0'); end if; end process; sc_rdwr_mux: for i in 0 to SC_SLAVE_CNT-1 generate mmuio_outa(i).rd <= mmuio_out.rd when i=sc_sel else '0'; mmuio_outa(i).wr <= mmuio_out.wr when i=sc_sel else '0'; end generate; -- 0 --> ram -- 10* --> rom -- 11* --> simcon... -- 1111* --> Blöcke 0xF000/4 -- 11111111 * --> Blöcke 0xFF00/8 (I/O Devices) -- 11111111 0000* --> Switches 0xFF00/12 -- 11111111 0001* --> Digits 0xFF10/12 -- 11111111 0002* --> uart 0XFF20/12 -- -- 11111111 1111111* --> Test 0xFFFE/15 -- FEDCBA98 76543210 sc_addr <= mmuio_out.address; sc_sc_selector: process (mmuio_out, sc_addr) begin if((sc_addr and x"FFF0") = x"FF00") then sc_sel <= 0; elsif((sc_addr and x"FFF0") = x"FF10") then sc_sel <= 1; elsif((sc_addr and x"FFF0") = x"FF20") then sc_sel <= 2; elsif((sc_addr and x"FFFE") = x"FFFE") then sc_sel <= 3; else sc_sel <= SC_SLAVE_CNT; end if; end process; --IO devices below cmp_switches: sc_de2_switches port map(clk, reset, mmuio_out.address, mmuio_out.wr_data, mmuio_outa(0).rd, mmuio_outa(0).wr, mmuio_ina(0).rd_data, mmuio_ina(0).rdy_cnt, switch_pins, led_pins); cmp_digits: sc_de2_digits port map(clk, reset, mmuio_out.address, mmuio_out.wr_data, mmuio_outa(1).rd, mmuio_outa(1).wr, mmuio_ina(1).rd_data, mmuio_ina(1).rdy_cnt, digit0_pins, digit1_pins, digit2_pins, digit3_pins, digit4_pins, digit5_pins); cmp_uart: sc_uart generic map(CLK_FREQ, UART_RATE, 4, 2, 4, 2) port map(clk, reset, mmuio_out.address, mmuio_out.wr_data, mmuio_outa(2).rd, mmuio_outa(2).wr, mmuio_ina(2).rd_data, mmuio_ina(2).rdy_cnt, txd, rxd, '0', open); cmp_test: sc_test_slave port map(clk, reset, mmuio_out.address, mmuio_out.wr_data, mmuio_outa(3).rd, mmuio_outa(3).wr, mmuio_ina(3).rd_data, mmuio_ina(3).rdy_cnt); end sat1; use WORK.all; configuration aua_cache of aua is for sat1 for cmp_icache : instr_cache use entity work.instr_cache(cache_null); --~ use entity work.instr_cache(cache_direct); end for; for cmp_ex: ex use entity work.ex(sat1); for sat1 for cmp_alu: alu use entity work.alu(old); --~ use entity work.alu(opt); end for; end for; end for; -- does not work... why? --~ for cmp_mmu: mmu --~ use entity work.mmu(sat1) --~ generic map(1) -- irq_cnt --~ port map(clk, reset, cachemmu_addr, cachemmu_data, cachemmu_valid, exmmu_address, exmmu_result_mmu, exmmu_wr_data, exmmu_enable, exmmu_mmu_opcode, exmmu_valid, --~ mmuio_address, mmuio_wr_data, mmuio_rd, mmuio_wr, mmuio_rd_data, mmuio_rdy_cnt, --~ sram_addr, sram_dq, sram_we, sram_oe, sram_ub, sram_lb, sram_ce); --~ end for; end for; end aua_cache;
-- -- Front-end for SpaceWire Receiver -- -- This entity samples the input signals DataIn and StrobeIn to detect -- valid bit transitions. Received bits are handed to the application. -- -- Inputs are sampled on the rising edge of the system clock, therefore -- the maximum bitrate of the incoming signal must be significantly lower -- than system clock frequency. -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity spwrecvfront_generic is port ( -- System clock. clk: in std_logic; -- High to enable receiver; low to disable and reset receiver. rxen: in std_logic; -- High if there has been recent activity on the input lines. inact: out std_logic; -- High if inbits contains a valid received bit. -- If inbvalid='1', the application must sample inbits on -- the rising edge of clk. inbvalid: out std_logic; -- Received bit inbits: out std_logic_vector(0 downto 0); -- Data In signal from SpaceWire bus. spw_di: in std_logic; -- Strobe In signal from SpaceWire bus. spw_si: in std_logic ); end entity spwrecvfront_generic; architecture spwrecvfront_arch of spwrecvfront_generic is -- input flip-flops signal s_spwdi1: std_ulogic; signal s_spwsi1: std_ulogic; signal s_spwdi2: std_ulogic; signal s_spwsi2: std_ulogic; -- data/strobe decoding signal s_spwsi3: std_ulogic; -- output registers signal s_inbvalid: std_ulogic; signal s_inbit: std_ulogic; begin -- drive outputs inact <= s_inbvalid; inbvalid <= s_inbvalid; inbits(0) <= s_inbit; -- synchronous process process (clk) is begin if rising_edge(clk) then -- sample input signal s_spwdi1 <= spw_di; s_spwsi1 <= spw_si; -- more flip-flops for safe synchronization s_spwdi2 <= s_spwdi1; s_spwsi2 <= s_spwsi1; -- keep strobe signal for data/strobe decoding s_spwsi3 <= s_spwsi2; -- keep data bit for data/strobe decoding s_inbit <= s_spwdi2; if rxen = '1' then -- data/strobe decoding s_inbvalid <= s_spwdi2 xor s_spwsi2 xor s_inbit xor s_spwsi3; else -- reset receiver s_inbvalid <= '0'; end if; end if; end process; end architecture spwrecvfront_arch;
-- -- Front-end for SpaceWire Receiver -- -- This entity samples the input signals DataIn and StrobeIn to detect -- valid bit transitions. Received bits are handed to the application. -- -- Inputs are sampled on the rising edge of the system clock, therefore -- the maximum bitrate of the incoming signal must be significantly lower -- than system clock frequency. -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity spwrecvfront_generic is port ( -- System clock. clk: in std_logic; -- High to enable receiver; low to disable and reset receiver. rxen: in std_logic; -- High if there has been recent activity on the input lines. inact: out std_logic; -- High if inbits contains a valid received bit. -- If inbvalid='1', the application must sample inbits on -- the rising edge of clk. inbvalid: out std_logic; -- Received bit inbits: out std_logic_vector(0 downto 0); -- Data In signal from SpaceWire bus. spw_di: in std_logic; -- Strobe In signal from SpaceWire bus. spw_si: in std_logic ); end entity spwrecvfront_generic; architecture spwrecvfront_arch of spwrecvfront_generic is -- input flip-flops signal s_spwdi1: std_ulogic; signal s_spwsi1: std_ulogic; signal s_spwdi2: std_ulogic; signal s_spwsi2: std_ulogic; -- data/strobe decoding signal s_spwsi3: std_ulogic; -- output registers signal s_inbvalid: std_ulogic; signal s_inbit: std_ulogic; begin -- drive outputs inact <= s_inbvalid; inbvalid <= s_inbvalid; inbits(0) <= s_inbit; -- synchronous process process (clk) is begin if rising_edge(clk) then -- sample input signal s_spwdi1 <= spw_di; s_spwsi1 <= spw_si; -- more flip-flops for safe synchronization s_spwdi2 <= s_spwdi1; s_spwsi2 <= s_spwsi1; -- keep strobe signal for data/strobe decoding s_spwsi3 <= s_spwsi2; -- keep data bit for data/strobe decoding s_inbit <= s_spwdi2; if rxen = '1' then -- data/strobe decoding s_inbvalid <= s_spwdi2 xor s_spwsi2 xor s_inbit xor s_spwsi3; else -- reset receiver s_inbvalid <= '0'; end if; end if; end process; end architecture spwrecvfront_arch;
-- ATA interface constant CFG_ATA : integer := CONFIG_ATA_ENABLE; constant CFG_ATAIO : integer := 16#CONFIG_ATAIO#; constant CFG_ATAIRQ : integer := CONFIG_ATAIRQ; constant CFG_ATADMA : integer := CONFIG_ATA_MWDMA; constant CFG_ATAFIFO : integer := CONFIG_ATA_FIFO;
-- ATA interface constant CFG_ATA : integer := CONFIG_ATA_ENABLE; constant CFG_ATAIO : integer := 16#CONFIG_ATAIO#; constant CFG_ATAIRQ : integer := CONFIG_ATAIRQ; constant CFG_ATADMA : integer := CONFIG_ATA_MWDMA; constant CFG_ATAFIFO : integer := CONFIG_ATA_FIFO;
library verilog; use verilog.vl_types.all; entity InstruMemory is generic( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 32 ); port( data : in vl_logic_vector; addr : in vl_logic_vector; we : in vl_logic_vector(3 downto 0); clk : in vl_logic; q : out vl_logic_vector ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of DATA_WIDTH : constant is 1; attribute mti_svvh_generic_type of ADDR_WIDTH : constant is 1; end InstruMemory;
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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block IEKs3v1U4ZrGtQ0GJBj1GObroWn7qUtVIk6ehVj6p8tNCmuXfFQoj3MBJ+irsY7fQnr2QERnclSa DTPzAxU7nw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bHXxs0PerrsoqTiziZzG96TBw9FgFyfq3QWTqZzWJZWI61WJwGHGqBZH5euavmse+ICawYH7T8Bu C1kvVj/yUX+nC+pJuS2BLbB2NVDcPRPAS13yOEyRxKnIqRGYF6XRt1dbAPJiKBUg80NJZUdoDQ+P 6xFUSmJ+jaJFMmSR6D0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block IEKs3v1U4ZrGtQ0GJBj1GObroWn7qUtVIk6ehVj6p8tNCmuXfFQoj3MBJ+irsY7fQnr2QERnclSa DTPzAxU7nw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bHXxs0PerrsoqTiziZzG96TBw9FgFyfq3QWTqZzWJZWI61WJwGHGqBZH5euavmse+ICawYH7T8Bu C1kvVj/yUX+nC+pJuS2BLbB2NVDcPRPAS13yOEyRxKnIqRGYF6XRt1dbAPJiKBUg80NJZUdoDQ+P 6xFUSmJ+jaJFMmSR6D0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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library ieee; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; use work.VHDL_lib.all; entity modn is generic( size:integer := 4 ); port ( clk : in std_logic; output : out std_logic_vector(log2(size)-1 downto 0) ); end modn; architecture arch of modn is signal count: std_logic_vector(log2(size)-1 downto 0); begin counter:process(clk) begin if(clk'event and clk = '1')then output <= count; if(count < size-1) then count <= count + 1; else count <= (others=>'0'); end if; end if; end process; end arch;
---------------------------------------------------------------------------------- -- Module Name: tb_aux_test - Behavioral -- -- Description: A testbench for the aux_test -- ---------------------------------------------------------------------------------- -- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort ------------------------------------------------------------------------------------ -- The MIT License (MIT) -- -- Copyright (c) 2015 Michael Alan Field <[email protected]> -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -- THE SOFTWARE. ------------------------------------------------------------------------------------ ----- Want to say thanks? ---------------------------------------------------------- ------------------------------------------------------------------------------------ -- -- This design has taken many hours - 3 months of work. I'm more than happy -- to share it if you can make use of it. It is released under the MIT license, -- so you are not under any onus to say thanks, but.... -- -- If you what to say thanks for this design either drop me an email, or how about -- trying PayPal to my email ([email protected])? -- -- Educational use - Enough for a beer -- Hobbyist use - Enough for a pizza -- Research use - Enough to take the family out to dinner -- Commercial use - A weeks pay for an engineer (I wish!) -------------------------------------------------------------------------------------- -- Ver \| Date \| Change --------+------------+--------------------------------------------------------------- -- 0.1 \| 2015-09-17 \| Initial Version ------------------------------------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity tb_aux_test is end entity; architecture arch of tb_aux_test is component aux_test is port ( clk : in std_logic; -- Needs to be a 100 MHz signal debug_pmod : out std_logic_vector(7 downto 0); dp_tx_aux_p : inout std_logic; dp_tx_aux_n : inout std_logic; dp_rx_aux_p : inout std_logic; dp_rx_aux_n : inout std_logic; dp_tx_hpd : in std_logic ); end component; signal clk : std_logic := '0'; signal debug_pmod : std_logic_vector := (others => '0'); signal dp_tx_aux_p : std_logic := '0'; signal dp_tx_aux_n : std_logic := '0'; signal dp_rx_aux_p : std_logic := '0'; signal dp_rx_aux_n : std_logic := '0'; signal dp_tx_hpd : std_logic := '0'; begin uut: aux_test PORT MAP ( clk => clk, debug_pmod => debug_pmod, dp_tx_aux_p => dp_tx_aux_p, dp_tx_aux_n => dp_tx_aux_n, dp_rx_aux_p => dp_rx_aux_p, dp_rx_aux_n => dp_rx_aux_n, dp_tx_hpd => dp_tx_hpd ); process begin wait for 5 ns; clk <= '1'; wait for 5 ns; clk <= '0'; end process; end architecture;
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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block MpIeCp0eEPDTj3K4Uv1riW1H2tnuvhS05btKYb/YEbeFY3QFo6naj1wSotWcBhOEG17yHatKDut6 7muS7y6JZA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block J6hu5EOU+eo5Azqym0gz1IN5zG5pxk4nC9LguQybDiiH+Z4ynYQn9eKFZYZP8K0veFCTLYHHefsk tpngEFOui/ihqeYyxhal9dg0LpElQF/s4Y8K2ySnsnGS9VVF8XUr+ZCUtWLLsnKR3SAxUC1XTe0z qf5mho7wWKCSRwqtfD4= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block BFCljXRp1rI1+Y0U2Z/ZKGyt38cgLBhNgpMeQrzoYiFF4rXG1yCthnFbJ7jRRp4vgguypYEPk+Ed GObj4Sn6wPqSfs1SnMzL8rNbrR8msNIxK8UCbPdC5eqH8rsWiM5F+PKHQBeH9N5jA28qdyAqFJ/h OrFpv3HWMPWXMr0gCC3SHKypr7BnrpyFG1LGkz+ZVoplJFem6O336evvaFAuW2UlM8krMZXP7KYX shJ8+0Sh6FVClGFZsSe1aS5vap5MNAFsxCUGSuV0tSJEZSWzkn0H75w9jmLzIRcLc7RV/MGnq30/ V8tLNmYKQEWtVztgNG4haBNlXOHTrnif604dSQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KgBY+JElMQLwoy/PHQcKPX1kBJFDyy2cOmv4EzEzrfuSU3jJut1ngnxyvuUV0cdaDdHxqso9rYM5 gyO1hvEgFdXq7eB3Xt69j6Mj26It/f5wfo84y5RPoDoT9i9wkeOFFuU9c252HCvGgmVUMRXP8aTv +Sr01GDHoJX2gTv0F9c= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block a+OcNnMEm68meW6uNCVGL8ZpZIpHA2bFrE5u+qmk43LRhJ2Tm96hYzvERSrOJzbP0xIgs0OesVqp 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block MpIeCp0eEPDTj3K4Uv1riW1H2tnuvhS05btKYb/YEbeFY3QFo6naj1wSotWcBhOEG17yHatKDut6 7muS7y6JZA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block J6hu5EOU+eo5Azqym0gz1IN5zG5pxk4nC9LguQybDiiH+Z4ynYQn9eKFZYZP8K0veFCTLYHHefsk tpngEFOui/ihqeYyxhal9dg0LpElQF/s4Y8K2ySnsnGS9VVF8XUr+ZCUtWLLsnKR3SAxUC1XTe0z qf5mho7wWKCSRwqtfD4= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block MpIeCp0eEPDTj3K4Uv1riW1H2tnuvhS05btKYb/YEbeFY3QFo6naj1wSotWcBhOEG17yHatKDut6 7muS7y6JZA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block J6hu5EOU+eo5Azqym0gz1IN5zG5pxk4nC9LguQybDiiH+Z4ynYQn9eKFZYZP8K0veFCTLYHHefsk tpngEFOui/ihqeYyxhal9dg0LpElQF/s4Y8K2ySnsnGS9VVF8XUr+ZCUtWLLsnKR3SAxUC1XTe0z qf5mho7wWKCSRwqtfD4= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block BFCljXRp1rI1+Y0U2Z/ZKGyt38cgLBhNgpMeQrzoYiFF4rXG1yCthnFbJ7jRRp4vgguypYEPk+Ed GObj4Sn6wPqSfs1SnMzL8rNbrR8msNIxK8UCbPdC5eqH8rsWiM5F+PKHQBeH9N5jA28qdyAqFJ/h OrFpv3HWMPWXMr0gCC3SHKypr7BnrpyFG1LGkz+ZVoplJFem6O336evvaFAuW2UlM8krMZXP7KYX shJ8+0Sh6FVClGFZsSe1aS5vap5MNAFsxCUGSuV0tSJEZSWzkn0H75w9jmLzIRcLc7RV/MGnq30/ V8tLNmYKQEWtVztgNG4haBNlXOHTrnif604dSQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KgBY+JElMQLwoy/PHQcKPX1kBJFDyy2cOmv4EzEzrfuSU3jJut1ngnxyvuUV0cdaDdHxqso9rYM5 gyO1hvEgFdXq7eB3Xt69j6Mj26It/f5wfo84y5RPoDoT9i9wkeOFFuU9c252HCvGgmVUMRXP8aTv +Sr01GDHoJX2gTv0F9c= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block a+OcNnMEm68meW6uNCVGL8ZpZIpHA2bFrE5u+qmk43LRhJ2Tm96hYzvERSrOJzbP0xIgs0OesVqp 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block MpIeCp0eEPDTj3K4Uv1riW1H2tnuvhS05btKYb/YEbeFY3QFo6naj1wSotWcBhOEG17yHatKDut6 7muS7y6JZA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block J6hu5EOU+eo5Azqym0gz1IN5zG5pxk4nC9LguQybDiiH+Z4ynYQn9eKFZYZP8K0veFCTLYHHefsk tpngEFOui/ihqeYyxhal9dg0LpElQF/s4Y8K2ySnsnGS9VVF8XUr+ZCUtWLLsnKR3SAxUC1XTe0z qf5mho7wWKCSRwqtfD4= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block BFCljXRp1rI1+Y0U2Z/ZKGyt38cgLBhNgpMeQrzoYiFF4rXG1yCthnFbJ7jRRp4vgguypYEPk+Ed GObj4Sn6wPqSfs1SnMzL8rNbrR8msNIxK8UCbPdC5eqH8rsWiM5F+PKHQBeH9N5jA28qdyAqFJ/h OrFpv3HWMPWXMr0gCC3SHKypr7BnrpyFG1LGkz+ZVoplJFem6O336evvaFAuW2UlM8krMZXP7KYX shJ8+0Sh6FVClGFZsSe1aS5vap5MNAFsxCUGSuV0tSJEZSWzkn0H75w9jmLzIRcLc7RV/MGnq30/ V8tLNmYKQEWtVztgNG4haBNlXOHTrnif604dSQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KgBY+JElMQLwoy/PHQcKPX1kBJFDyy2cOmv4EzEzrfuSU3jJut1ngnxyvuUV0cdaDdHxqso9rYM5 gyO1hvEgFdXq7eB3Xt69j6Mj26It/f5wfo84y5RPoDoT9i9wkeOFFuU9c252HCvGgmVUMRXP8aTv +Sr01GDHoJX2gTv0F9c= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block a+OcNnMEm68meW6uNCVGL8ZpZIpHA2bFrE5u+qmk43LRhJ2Tm96hYzvERSrOJzbP0xIgs0OesVqp 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-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1001.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c06s03b00x00p09n01i01001pkg is type TWO is range 1 to 2; end c06s03b00x00p09n01i01001pkg; use work.c06s03b00x00p09n01i01001pkg.all; ENTITY c06s03b00x00p09n01i01001ent IS END c06s03b00x00p09n01i01001ent; ARCHITECTURE c06s03b00x00p09n01i01001arch OF c06s03b00x00p09n01i01001ent IS BEGIN TESTING: PROCESS subtype ST6 is c06s03b00x00p09n01i01001pkg.UNKNOWN; -- SEMANTIC ERROR: ILLEGAL EXPANDED NAME BEGIN assert FALSE report "***FAILED TEST: c06s03b00x00p09n01i01001 - Expanded name is illegal." severity ERROR; wait; END PROCESS TESTING; END c06s03b00x00p09n01i01001arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1001.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c06s03b00x00p09n01i01001pkg is type TWO is range 1 to 2; end c06s03b00x00p09n01i01001pkg; use work.c06s03b00x00p09n01i01001pkg.all; ENTITY c06s03b00x00p09n01i01001ent IS END c06s03b00x00p09n01i01001ent; ARCHITECTURE c06s03b00x00p09n01i01001arch OF c06s03b00x00p09n01i01001ent IS BEGIN TESTING: PROCESS subtype ST6 is c06s03b00x00p09n01i01001pkg.UNKNOWN; -- SEMANTIC ERROR: ILLEGAL EXPANDED NAME BEGIN assert FALSE report "***FAILED TEST: c06s03b00x00p09n01i01001 - Expanded name is illegal." severity ERROR; wait; END PROCESS TESTING; END c06s03b00x00p09n01i01001arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1001.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c06s03b00x00p09n01i01001pkg is type TWO is range 1 to 2; end c06s03b00x00p09n01i01001pkg; use work.c06s03b00x00p09n01i01001pkg.all; ENTITY c06s03b00x00p09n01i01001ent IS END c06s03b00x00p09n01i01001ent; ARCHITECTURE c06s03b00x00p09n01i01001arch OF c06s03b00x00p09n01i01001ent IS BEGIN TESTING: PROCESS subtype ST6 is c06s03b00x00p09n01i01001pkg.UNKNOWN; -- SEMANTIC ERROR: ILLEGAL EXPANDED NAME BEGIN assert FALSE report "***FAILED TEST: c06s03b00x00p09n01i01001 - Expanded name is illegal." severity ERROR; wait; END PROCESS TESTING; END c06s03b00x00p09n01i01001arch;
architecture rtl of fifo is type t_record is record a : std_logic; b : std_logic; end record t_record; type t_record is record a : std_logic; b : std_logic; end record t_record; begin end architecture rtl;
architecture rtl of fifo is type t_record is record a : std_logic; b : std_logic; end record t_record; type t_record is record a : std_logic; b : std_logic; end record t_record; begin end architecture rtl;
architecture rtl of fifo is type t_record is record a : std_logic; b : std_logic; end record t_record; type t_record is record a : std_logic; b : std_logic; end record t_record; begin end architecture rtl;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1839.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c07s01b00x00p08n01i01839pkg is type small_int is range 0 to 7; type cmd_bus is array (small_int range <>) of small_int; constant bus_width : small_int := 7; end c07s01b00x00p08n01i01839pkg; use work.c07s01b00x00p08n01i01839pkg.all; entity c07s01b00x00p08n01i01839ent_a is port ( signal in_bus : in cmd_bus (0 to bus_width); signal out_bus : out cmd_bus (0 to bus_width)); end c07s01b00x00p08n01i01839ent_a; architecture c07s01b00x00p08n01i01839arch_a of c07s01b00x00p08n01i01839ent_a is begin end c07s01b00x00p08n01i01839arch_a; use work.c07s01b00x00p08n01i01839pkg.all; ENTITY c07s01b00x00p08n01i01839ent IS END c07s01b00x00p08n01i01839ent; ARCHITECTURE c07s01b00x00p08n01i01839arch OF c07s01b00x00p08n01i01839ent IS signal ibus, obus : cmd_bus(small_int); component test port ( signal in_bus : in cmd_bus (0 to small_int(bus_width)); signal out_bus : out cmd_bus (0 to small_int(bus_width))); end component; for err : test use entity work.c07s01b00x00p08n01i01839ent_a(c07s01b00x00p08n01i01839arch_a); BEGIN err : test port map ( ibus, c07s01b00x00p08n01i01839ent ); --entity name illegal here TESTING : PROCESS BEGIN wait for 5 ns; assert FALSE report "***FAILED TEST: c07s01b00x00p08n01i01839 - Entity names are not permitted as primaries in a component instantiation port map statement." severity ERROR; wait; END PROCESS TESTING; ENDc07s01b00x00p08n01i01839arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1839.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c07s01b00x00p08n01i01839pkg is type small_int is range 0 to 7; type cmd_bus is array (small_int range <>) of small_int; constant bus_width : small_int := 7; end c07s01b00x00p08n01i01839pkg; use work.c07s01b00x00p08n01i01839pkg.all; entity c07s01b00x00p08n01i01839ent_a is port ( signal in_bus : in cmd_bus (0 to bus_width); signal out_bus : out cmd_bus (0 to bus_width)); end c07s01b00x00p08n01i01839ent_a; architecture c07s01b00x00p08n01i01839arch_a of c07s01b00x00p08n01i01839ent_a is begin end c07s01b00x00p08n01i01839arch_a; use work.c07s01b00x00p08n01i01839pkg.all; ENTITY c07s01b00x00p08n01i01839ent IS END c07s01b00x00p08n01i01839ent; ARCHITECTURE c07s01b00x00p08n01i01839arch OF c07s01b00x00p08n01i01839ent IS signal ibus, obus : cmd_bus(small_int); component test port ( signal in_bus : in cmd_bus (0 to small_int(bus_width)); signal out_bus : out cmd_bus (0 to small_int(bus_width))); end component; for err : test use entity work.c07s01b00x00p08n01i01839ent_a(c07s01b00x00p08n01i01839arch_a); BEGIN err : test port map ( ibus, c07s01b00x00p08n01i01839ent ); --entity name illegal here TESTING : PROCESS BEGIN wait for 5 ns; assert FALSE report "***FAILED TEST: c07s01b00x00p08n01i01839 - Entity names are not permitted as primaries in a component instantiation port map statement." severity ERROR; wait; END PROCESS TESTING; ENDc07s01b00x00p08n01i01839arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1839.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c07s01b00x00p08n01i01839pkg is type small_int is range 0 to 7; type cmd_bus is array (small_int range <>) of small_int; constant bus_width : small_int := 7; end c07s01b00x00p08n01i01839pkg; use work.c07s01b00x00p08n01i01839pkg.all; entity c07s01b00x00p08n01i01839ent_a is port ( signal in_bus : in cmd_bus (0 to bus_width); signal out_bus : out cmd_bus (0 to bus_width)); end c07s01b00x00p08n01i01839ent_a; architecture c07s01b00x00p08n01i01839arch_a of c07s01b00x00p08n01i01839ent_a is begin end c07s01b00x00p08n01i01839arch_a; use work.c07s01b00x00p08n01i01839pkg.all; ENTITY c07s01b00x00p08n01i01839ent IS END c07s01b00x00p08n01i01839ent; ARCHITECTURE c07s01b00x00p08n01i01839arch OF c07s01b00x00p08n01i01839ent IS signal ibus, obus : cmd_bus(small_int); component test port ( signal in_bus : in cmd_bus (0 to small_int(bus_width)); signal out_bus : out cmd_bus (0 to small_int(bus_width))); end component; for err : test use entity work.c07s01b00x00p08n01i01839ent_a(c07s01b00x00p08n01i01839arch_a); BEGIN err : test port map ( ibus, c07s01b00x00p08n01i01839ent ); --entity name illegal here TESTING : PROCESS BEGIN wait for 5 ns; assert FALSE report "***FAILED TEST: c07s01b00x00p08n01i01839 - Entity names are not permitted as primaries in a component instantiation port map statement." severity ERROR; wait; END PROCESS TESTING; ENDc07s01b00x00p08n01i01839arch;
library ieee; use ieee.std_logic_1164.all; entity reg8 is port ( clk : in std_logic; clr : in std_logic; load : in std_logic; D : in std_logic_vector(7 downto 0); Q : out std_logic_vector(7 downto 0) ); end entity; architecture rtlreg8 of reg8 is begin process(clk,clr) begin if (clr = '1') then Q <= "00000000"; elsif rising_edge(clk) then if (load = '1') then Q <= D; end if; end if; end process; end rtlreg8;
entity data_8b10b_tb is end; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.tb_pack.all; use work.codec_8b10b_pack.all; architecture tb of data_8b10b_tb is begin process is variable b8_i : b8_t; variable b10_o : b10_t; variable rd_o : rd_t; begin for i in 0 to 255 loop b8_i := b8_t(to_unsigned(i, 8)); data_8b10b(b8_i, minus1, b10_o, rd_o); report "data_8b10b(0x" & to_hstring(b8_i) & ", minus1) => 0x" & to_hstring(b10_o) & ", " & rd_t'image(rd_o); end loop; wait; end process; end;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: fifo_dgen.vhd -- -- Description: -- Used for write interface stimulus generation -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_misc.all; LIBRARY work; USE work.fifo_pkg.ALL; ENTITY fifo_dgen IS GENERIC ( C_DIN_WIDTH : INTEGER := 32; C_DOUT_WIDTH : INTEGER := 32; C_CH_TYPE : INTEGER := 0; TB_SEED : INTEGER := 2 ); PORT ( RESET : IN STD_LOGIC; WR_CLK : IN STD_LOGIC; PRC_WR_EN : IN STD_LOGIC; FULL : IN STD_LOGIC; WR_EN : OUT STD_LOGIC; WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) ); END ENTITY; ARCHITECTURE fg_dg_arch OF fifo_dgen IS CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); SIGNAL pr_w_en : STD_LOGIC := '0'; SIGNAL rand_num : STD_LOGIC_VECTOR(8LOOP_COUNT-1 DOWNTO 0); SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); BEGIN WR_EN <= PRC_WR_EN ; WR_DATA <= wr_data_i AFTER 100 ns; ---------------------------------------------- -- Generation of DATA ---------------------------------------------- gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE rd_gen_inst1:fifo_rng GENERIC MAP( WIDTH => 8, SEED => TB_SEED+N ) PORT MAP( CLK => WR_CLK, RESET => RESET, RANDOM_NUM => rand_num(8(N+1)-1 downto 8*N), ENABLE => pr_w_en ); END GENERATE; pr_w_en <= PRC_WR_EN AND NOT FULL; wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0); END ARCHITECTURE;
-- ------------------------------------------------------------- -- -- Entity Declaration for pad_pads_e -- -- Generated -- by: wig -- on: Wed Dec 14 12:20:57 2005 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../padio.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: pad_pads_e-e.vhd,v 1.4 2005/12/14 12:38:04 wig Exp $ -- $Date: 2005/12/14 12:38:04 $ -- $Log: pad_pads_e-e.vhd,v $ -- Revision 1.4 2005/12/14 12:38:04 wig -- Updated some testcases (verilog, padio) -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.72 2005/11/30 14:01:21 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.43 , [email protected] -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity pad_pads_e -- entity pad_pads_e is -- Generics: -- No Generated Generics for Entity pad_pads_e -- Generated Port Declaration: port( -- Generated Port for Entity pad_pads_e p_mix_pad_di_12_go : out std_ulogic; p_mix_pad_di_13_go : out std_ulogic; p_mix_pad_di_14_go : out std_ulogic; p_mix_pad_di_15_go : out std_ulogic; p_mix_pad_di_16_go : out std_ulogic; p_mix_pad_di_17_go : out std_ulogic; p_mix_pad_di_18_go : out std_ulogic; p_mix_pad_di_1_go : out std_ulogic; p_mix_pad_di_31_go : out std_ulogic; p_mix_pad_di_32_go : out std_ulogic; p_mix_pad_di_33_go : out std_ulogic; p_mix_pad_di_34_go : out std_ulogic; p_mix_pad_di_39_go : out std_ulogic; p_mix_pad_di_40_go : out std_ulogic; p_mix_pad_do_12_gi : in std_ulogic; p_mix_pad_do_13_gi : in std_ulogic; p_mix_pad_do_14_gi : in std_ulogic; p_mix_pad_do_15_gi : in std_ulogic; p_mix_pad_do_16_gi : in std_ulogic; p_mix_pad_do_17_gi : in std_ulogic; p_mix_pad_do_18_gi : in std_ulogic; p_mix_pad_do_2_gi : in std_ulogic; p_mix_pad_do_31_gi : in std_ulogic; p_mix_pad_do_32_gi : in std_ulogic; p_mix_pad_do_35_gi : in std_ulogic; p_mix_pad_do_36_gi : in std_ulogic; p_mix_pad_do_39_gi : in std_ulogic; p_mix_pad_do_40_gi : in std_ulogic; p_mix_pad_en_12_gi : in std_ulogic; p_mix_pad_en_13_gi : in std_ulogic; p_mix_pad_en_14_gi : in std_ulogic; p_mix_pad_en_15_gi : in std_ulogic; p_mix_pad_en_16_gi : in std_ulogic; p_mix_pad_en_17_gi : in std_ulogic; p_mix_pad_en_18_gi : in std_ulogic; p_mix_pad_en_2_gi : in std_ulogic; p_mix_pad_en_31_gi : in std_ulogic; p_mix_pad_en_32_gi : in std_ulogic; p_mix_pad_en_35_gi : in std_ulogic; p_mix_pad_en_36_gi : in std_ulogic; p_mix_pad_en_39_gi : in std_ulogic; p_mix_pad_en_40_gi : in std_ulogic; p_mix_pad_pu_31_gi : in std_ulogic; p_mix_pad_pu_32_gi : in std_ulogic -- End of Generated Port for Entity pad_pads_e ); end pad_pads_e; -- -- End of Generated Entity pad_pads_e -- -- --!End of Entity/ies -- --------------------------------------------------------------
-- ######################################################################## -- $Software: busiac -- $section : hardware component -- $Id: rs232out.vhd 322 2015-05-29 06:43:59Z ia $ -- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/rs232out.vhd $ -- $Author : Ivan Auge (Email: [email protected]) -- ######################################################################## -- -- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge. -- -- This program is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at your -- option) any later version. -- -- BUSIAC software is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY ; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General -- Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with the GNU C Library; see the file COPYING. If not, write to the Free -- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -- -- ######################################################################/ ------------------------------------------------------------------------------- -- ATTENTION: -- Ceci un template, les trous marqués "..." doivent être comblés pour -- pouvoir être compilé, puis fonctionné. ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Ce module sérialise l'entrée DATA de 8 bits sur la sortie TX. -- -- le format écrit est: -- - 1 start bit -- - 8 bit de données -- - 1 stop bits -- -- La sortie BUSY indique que le module est en train de sérialiser. -- -- Pour sérialiser une nouvelle valeur, il faut: -- attendre que BUSY soit nul. -- * la positionner sur DATA et mettre NDATA à 1 au moins 1 cycle. -- -- Pour fixer le BAUD du composant utilisez les paramètres génériques -- BAUD et FREQ ci dessous. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity rs232out is generic( FREQ : integer := 50000000; -- Frequence de clk BAUD : integer := 9600); -- Baud de Rx port( clk : in STD_LOGIC; reset : in STD_LOGIC; Tx : out STD_LOGIC; Data : in STD_LOGIC_VECTOR(7 downto 0); Ndata : in STD_LOGIC; Busy : out STD_LOGIC); end rs232out; architecture montage of rs232out is ------------------------------------------------------------------------------- -- Partie Opérative ------------------------------------------------------------------------------- type T_CMD_i is (NOOP, COUNT, INIT); signal CMD_i : T_CMD_i ; signal R_i : integer RANGE 0 TO 15; signal VT_endLoop: STD_LOGIC; type T_CMD_baud is (NOOP, COUNT, INIT); signal CMD_baud : T_CMD_baud ; signal R_baud: integer RANGE 0 TO (FREQ)/BAUD; signal VT_endbaud: STD_LOGIC; type T_CMD_data is (NOOP, SHIFT, INIT); signal CMD_data : T_CMD_data ; signal R_data : STD_LOGIC_VECTOR(8 downto 0); -- 0 : 1 start bit -- 8:1 : 8 data bits ------------------------------------------------------------------------------- -- Partie Contrôle ------------------------------------------------------------------------------- --Description des états type STATE_TYPE is (ST_BEGIN, ST_FOR, ST_ATT, ST_ADV); signal state : STATE_TYPE; begin ------------------------------------------------------------------------------- -- Partie Opérative ------------------------------------------------------------------------------- process (clk) begin if clk'event and clk = '1' then -- R_i if ( CMD_i = INIT ) then R_i <= 11 ; elsif ( CMD_i = COUNT ) then R_i <= R_i - 1; else R_i <= R_i; end if; -- R_baud if ( CMD_baud = INIT ) then R_baud <= FREQ/BAUD ; elsif ( CMD_baud = COUNT ) then R_baud <= R_baud - 1; else R_baud <= R_baud; end if; -- R_data if ( CMD_data = INIT ) then -- V = E + '0' R_data(8 downto 1) <= Data; R_data(0) <= '0'; elsif ( CMD_data = SHIFT ) then -- v = '1' + (v >> 1) R_data(7 downto 0) <= R_data(8 downto 1); R_data(8) <= '1'; else R_data <= R_data; end if ; end if; end process; VT_endbaud <= '1' WHEN R_Baud = 0 ELSE '0' ; VT_endLoop <= '1' WHEN R_i = 0 ELSE '0' ; ------------------------------------------------------------------------------- -- Partie Contrôle ------------------------------------------------------------------------------- -- Inputs: Ndata VT_endLoop VT_endBaud -- Outputs: Tx Busy CMD_i CMD_baud CMD_data ------------------------------------------------------------------------------- -- fonction de transitition process (reset,clk) begin if reset = '1' then state <= ST_BEGIN; elsif clk'event and clk = '1' then case state is when ST_BEGIN => -- si go, alors on commence à serialiser if Ndata = '1' then state <= ST_FOR; end if; when ST_FOR => if VT_endLoop = '1' then state <= ST_BEGIN; else state <= ST_ATT; end if; when ST_ATT => if VT_endbaud = '1' then state <= ST_ADV; end if; when ST_ADV => state <= ST_FOR; end case; end if; end process; -- fonction de sortie with state select tx <= '1' when ST_BEGIN, R_Data(0) when others ; with state select busy <= '0' when ST_BEGIN, '1' when others ; with state select CMD_i <= INIT when ST_BEGIN, COUNT when ST_ADV, NOOP when others ; with state select CMD_baud <= COUNT when ST_ATT, INIT when others ; with state select CMD_data <= INIT when ST_BEGIN, SHIFT when ST_ADV, NOOP when others ; end montage;
-------------------------------------------------------------------------------- --! @file width_pulse_sync.vhd --! @brief Produce a pulse of specified width in a different clock domain. --! @author Yuan Mei --! --! Produce a pulse of specified width in a different clock domain --! following a 1-CLKO wide reset pulse. --! Ideally suited to change iodelay taps and iserdes bitslip --! MODE := 0 output one pulse of duration PW --! := 1 a train of 1-clk wide pulses (of number PW) --! PW = 0 will still generate RSTO but no PO. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values USE ieee.numeric_std.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. LIBRARY UNISIM; USE UNISIM.VComponents.ALL; ENTITY width_pulse_sync IS GENERIC ( DATA_WIDTH : positive := 8; MODE : natural := 0 -- 0: output one pulse of duration PW -- 1: a train of 1-clk wide pulses (of number PW) ); PORT ( RESET : IN std_logic; CLK : IN std_logic; PW : IN std_logic_vector(DATA_WIDTH-1 DOWNTO 0); START : IN std_logic; -- should be synchronous to CLK, of any width BUSY : OUT std_logic; -- CLKO : IN std_logic; RSTO : OUT std_logic; PO : OUT std_logic ); END width_pulse_sync; ARCHITECTURE Behavioral OF width_pulse_sync IS SIGNAL prev : std_logic; SIGNAL prevb : std_logic; SIGNAL prevb1 : std_logic; SIGNAL prevo : std_logic; SIGNAL prevo1 : std_logic; SIGNAL busy_buf : std_logic; SIGNAL busy_bufo : std_logic; SIGNAL pw_buf : std_logic_vector(DATA_WIDTH-1 DOWNTO 0); SIGNAL po_buf : std_logic; BEGIN PROCESS (CLK, RESET) IS BEGIN IF RESET = '1' THEN prev <= '0'; busy_buf <= '0'; pw_buf <= (OTHERS => '0'); prevb <= '0'; prevb1 <= '0'; ELSIF rising_edge(CLK) THEN prev <= START; -- Capture the rising edge of START, which is synchronous to CLK, of any width IF (prev = '0' AND START = '1' AND prevb1 = '0') THEN busy_buf <= '1'; pw_buf <= PW; END IF; prevb <= busy_bufo; prevb1 <= prevb; -- Capture the falling edge of busy_bufo IF (prevb = '0' AND prevb1 = '1') THEN busy_buf <= '0'; END IF; END IF; END PROCESS; BUSY <= busy_buf; -- output clock domain PROCESS (CLKO) IS VARIABLE counter : unsigned(DATA_WIDTH DOWNTO 0); BEGIN IF rising_edge(CLKO) THEN prevo <= busy_buf; prevo1 <= prevo; busy_bufo <= '0'; po_buf <= '0'; RSTO <= '0'; -- Capture the rising edge of busy_buf IF (prevo1 = '0' AND prevo = '1') THEN busy_bufo <= '1'; counter := (OTHERS => '0'); RSTO <= '1'; ELSIF counter = 0 THEN busy_bufo <= '1'; counter := counter + 1; ELSIF counter <= unsigned(pw_buf) THEN busy_bufo <= '1'; IF MODE = 0 THEN counter := counter + 1; po_buf <= '1'; ELSIF MODE = 1 THEN IF po_buf = '0' THEN counter := counter + 1; END IF; po_buf <= NOT po_buf; END IF; END IF; END IF; END PROCESS; PO <= po_buf; END Behavioral;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: ac.uk:user:lms_pcore:1.0 -- IP Revision: 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY lms_pcore_v1_00_a; USE lms_pcore_v1_00_a.lms_pcore; ENTITY ip_design_lms_pcore_0_0 IS PORT ( IPCORE_CLK : IN STD_LOGIC; IPCORE_RESETN : IN STD_LOGIC; AXI4_Lite_ACLK : IN STD_LOGIC; AXI4_Lite_ARESETN : IN STD_LOGIC; AXI4_Lite_AWADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0); AXI4_Lite_AWVALID : IN STD_LOGIC; AXI4_Lite_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); AXI4_Lite_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); AXI4_Lite_WVALID : IN STD_LOGIC; AXI4_Lite_BREADY : IN STD_LOGIC; AXI4_Lite_ARADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0); AXI4_Lite_ARVALID : IN STD_LOGIC; AXI4_Lite_RREADY : IN STD_LOGIC; AXI4_Lite_AWREADY : OUT STD_LOGIC; AXI4_Lite_WREADY : OUT STD_LOGIC; AXI4_Lite_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); AXI4_Lite_BVALID : OUT STD_LOGIC; AXI4_Lite_ARREADY : OUT STD_LOGIC; AXI4_Lite_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); AXI4_Lite_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); AXI4_Lite_RVALID : OUT STD_LOGIC ); END ip_design_lms_pcore_0_0; ARCHITECTURE ip_design_lms_pcore_0_0_arch OF ip_design_lms_pcore_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF ip_design_lms_pcore_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT lms_pcore IS PORT ( IPCORE_CLK : IN STD_LOGIC; IPCORE_RESETN : IN STD_LOGIC; AXI4_Lite_ACLK : IN STD_LOGIC; AXI4_Lite_ARESETN : IN STD_LOGIC; AXI4_Lite_AWADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0); AXI4_Lite_AWVALID : IN STD_LOGIC; AXI4_Lite_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); AXI4_Lite_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); AXI4_Lite_WVALID : IN STD_LOGIC; AXI4_Lite_BREADY : IN STD_LOGIC; AXI4_Lite_ARADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0); AXI4_Lite_ARVALID : IN STD_LOGIC; AXI4_Lite_RREADY : IN STD_LOGIC; AXI4_Lite_AWREADY : OUT STD_LOGIC; AXI4_Lite_WREADY : OUT STD_LOGIC; AXI4_Lite_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); AXI4_Lite_BVALID : OUT STD_LOGIC; AXI4_Lite_ARREADY : OUT STD_LOGIC; AXI4_Lite_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); AXI4_Lite_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); AXI4_Lite_RVALID : OUT STD_LOGIC ); END COMPONENT lms_pcore; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF ip_design_lms_pcore_0_0_arch: ARCHITECTURE IS "lms_pcore,Vivado 2017.3"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF ip_design_lms_pcore_0_0_arch : ARCHITECTURE IS "ip_design_lms_pcore_0_0,lms_pcore,{}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_PARAMETER : STRING; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite RVALID"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite RRESP"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite RDATA"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite BVALID"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite BRESP"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite WREADY"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite RREADY"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite BREADY"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite WVALID"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite WDATA"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite AWVALID"; ATTRIBUTE X_INTERFACE_PARAMETER OF AXI4_Lite_AWADDR: SIGNAL IS "XIL_INTERFACENAME AXI4_Lite, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite AWADDR"; ATTRIBUTE X_INTERFACE_PARAMETER OF AXI4_Lite_ARESETN: SIGNAL IS "XIL_INTERFACENAME AXI4_Lite_ARESETN, POLARITY ACTIVE_LOW"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI4_Lite_ARESETN RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF AXI4_Lite_ACLK: SIGNAL IS "XIL_INTERFACENAME AXI4_Lite_ACLK, ASSOCIATED_RESET AXI4_Lite_ARESETN, ASSOCIATED_BUSIF AXI4_Lite, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXI4_Lite_ACLK CLK"; ATTRIBUTE X_INTERFACE_PARAMETER OF IPCORE_RESETN: SIGNAL IS "XIL_INTERFACENAME IPCORE_RESETN, POLARITY ACTIVE_LOW"; ATTRIBUTE X_INTERFACE_INFO OF IPCORE_RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 IPCORE_RESETN RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF IPCORE_CLK: SIGNAL IS "XIL_INTERFACENAME IPCORE_CLK, ASSOCIATED_RESET IPCORE_RESETN, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0"; ATTRIBUTE X_INTERFACE_INFO OF IPCORE_CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 IPCORE_CLK CLK"; BEGIN U0 : lms_pcore PORT MAP ( IPCORE_CLK => IPCORE_CLK, IPCORE_RESETN => IPCORE_RESETN, AXI4_Lite_ACLK => AXI4_Lite_ACLK, AXI4_Lite_ARESETN => AXI4_Lite_ARESETN, AXI4_Lite_AWADDR => AXI4_Lite_AWADDR, AXI4_Lite_AWVALID => AXI4_Lite_AWVALID, AXI4_Lite_WDATA => AXI4_Lite_WDATA, AXI4_Lite_WSTRB => AXI4_Lite_WSTRB, AXI4_Lite_WVALID => AXI4_Lite_WVALID, AXI4_Lite_BREADY => AXI4_Lite_BREADY, AXI4_Lite_ARADDR => AXI4_Lite_ARADDR, AXI4_Lite_ARVALID => AXI4_Lite_ARVALID, AXI4_Lite_RREADY => AXI4_Lite_RREADY, AXI4_Lite_AWREADY => AXI4_Lite_AWREADY, AXI4_Lite_WREADY => AXI4_Lite_WREADY, AXI4_Lite_BRESP => AXI4_Lite_BRESP, AXI4_Lite_BVALID => AXI4_Lite_BVALID, AXI4_Lite_ARREADY => AXI4_Lite_ARREADY, AXI4_Lite_RDATA => AXI4_Lite_RDATA, AXI4_Lite_RRESP => AXI4_Lite_RRESP, AXI4_Lite_RVALID => AXI4_Lite_RVALID ); END ip_design_lms_pcore_0_0_arch;
---------------------------------------------------------------------- -- Project : Invent a Chip -- Authors : Jan Dürre -- Year : 2013 -- Description : This example waits for an uart-command, which is -- then saved and send back to the sender. ---------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.iac_pkg.all; entity invent_a_chip is port ( -- Global Signals clock : in std_ulogic; reset : in std_ulogic; -- Interface Signals -- 7-Seg sevenseg_cs : out std_ulogic; sevenseg_wr : out std_ulogic; sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0); sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0); sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0); -- ADC/DAC adc_dac_cs : out std_ulogic; adc_dac_wr : out std_ulogic; adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0); adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0); adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0); -- AUDIO audio_cs : out std_ulogic; audio_wr : out std_ulogic; audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0); audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0); audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0); audio_irq_left : in std_ulogic; audio_irq_right : in std_ulogic; audio_ack_left : out std_ulogic; audio_ack_right : out std_ulogic; -- Infra-red Receiver ir_cs : out std_ulogic; ir_wr : out std_ulogic; ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0); ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0); ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0); ir_irq_rx : in std_ulogic; ir_ack_rx : out std_ulogic; -- LCD lcd_cs : out std_ulogic; lcd_wr : out std_ulogic; lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0); lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0); lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0); lcd_irq_rdy : in std_ulogic; lcd_ack_rdy : out std_ulogic; -- SRAM sram_cs : out std_ulogic; sram_wr : out std_ulogic; sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0); sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0); sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0); -- UART uart_cs : out std_ulogic; uart_wr : out std_ulogic; uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0); uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0); uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0); uart_irq_rx : in std_ulogic; uart_irq_tx : in std_ulogic; uart_ack_rx : out std_ulogic; uart_ack_tx : out std_ulogic; -- GPIO gp_ctrl : out std_ulogic_vector(15 downto 0); gp_in : in std_ulogic_vector(15 downto 0); gp_out : out std_ulogic_vector(15 downto 0); -- LED/Switches/Keys led_green : out std_ulogic_vector(8 downto 0); led_red : out std_ulogic_vector(17 downto 0); switch : in std_ulogic_vector(17 downto 0); key : in std_ulogic_vector(2 downto 0) ); end invent_a_chip; architecture rtl of invent_a_chip is -- state register type state_t is (RECEIVED_LOOP, SEND_LOOP); signal state, state_nxt : state_t; -- register for received data signal received_data, received_data_nxt : std_ulogic_vector(7 downto 0); begin -- sequential process process (clock, reset) begin -- async reset if reset = '1' then state <= RECEIVED_LOOP; received_data <= (others => '0'); elsif rising_edge(clock) then state <= state_nxt; received_data <= received_data_nxt; end if; end process; -- logic process (state, received_data, uart_irq_rx, uart_irq_tx, uart_din) begin -- standard assignments -- hold values of registers state_nxt <= state; received_data_nxt <= received_data; -- set bus signals to standard values (not in use) uart_cs <= '0'; uart_wr <= '0'; uart_addr <= (others => '0'); uart_dout <= (others => '0'); uart_ack_rx <= '0'; uart_ack_tx <= '0'; -- turn of leds led_green <= (others => '0'); led_red <= (others => '0'); -- state machine case state is -- wait for and save data when RECEIVED_LOOP => led_green(0) <= '1'; -- data is ready in receive-register if uart_irq_rx = '1' then -- select uart-interface uart_cs <= '1'; -- address of send/receive-register uart_addr <= CV_ADDR_UART_DATA_RX; -- write-mode uart_wr <= '0'; -- save data received_data_nxt <= uart_din(7 downto 0); -- next state state_nxt <= SEND_LOOP; end if; -- send back saved data when SEND_LOOP => led_green(1) <= '1'; -- check if send-register is empty if uart_irq_tx = '1' then -- select uart-interface uart_cs <= '1'; -- address of send/receive-register uart_addr <= CV_ADDR_UART_DATA_TX; -- write-mode uart_wr <= '1'; -- select received data uart_dout(7 downto 0) <= received_data; -- next state state_nxt <= RECEIVED_LOOP; end if; end case; end process; -- default assignments for unused signals gp_ctrl <= (others => '0'); gp_out <= (others => '0'); sevenseg_cs <= '0'; sevenseg_wr <= '0'; sevenseg_addr <= (others => '0'); sevenseg_dout <= (others => '0'); adc_dac_cs <= '0'; adc_dac_wr <= '0'; adc_dac_addr <= (others => '0'); adc_dac_dout <= (others => '0'); audio_cs <= '0'; audio_wr <= '0'; audio_addr <= (others => '0'); audio_dout <= (others => '0'); audio_ack_left <= '0'; audio_ack_right <= '0'; ir_cs <= '0'; ir_wr <= '0'; ir_addr <= (others => '0'); ir_dout <= (others => '0'); ir_ack_rx <= '0'; lcd_cs <= '0'; lcd_wr <= '0'; lcd_addr <= (others => '0'); lcd_dout <= (others => '0'); lcd_ack_rdy <= '0'; sram_cs <= '0'; sram_wr <= '0'; sram_addr <= (others => '0'); sram_dout <= (others => '0'); end rtl;
-------------------------------------------------------------------------------- -- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 14.7 -- \ \ Application : xaw2vhdl -- / / Filename : dcm.vhd -- /___/ /\ Timestamp : 03/07/2016 00:14:36 -- \ \ / \ -- \___\/\___\ -- --Command: xaw2vhdl-intstyle C:/Users/Yakov/OneDrive/School/University Stuff/ENEL500/test232/ipcore_dir/dcm.xaw -st dcm.vhd --Design Name: dcm --Device: xc3s250e-4vq100 -- -- Module dcm -- Generated by Xilinx Architecture Wizard -- Written for synthesis tool: XST -- Period Jitter (unit interval) for block DCM_SP_INST = 0.06 UI -- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 2.91 ns library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity dcm is port ( CLKIN_IN : in std_logic; CLKFX_OUT : out std_logic; CLKIN_IBUFG_OUT : out std_logic; CLK0_OUT : out std_logic); end dcm; architecture BEHAVIORAL of dcm is signal CLKFB_IN : std_logic; signal CLKFX_BUF : std_logic; signal CLKIN_IBUFG : std_logic; signal CLK0_BUF : std_logic; signal GND_BIT : std_logic; begin GND_BIT <= '0'; CLKIN_IBUFG_OUT <= CLKIN_IBUFG; CLK0_OUT <= CLKFB_IN; CLKFX_BUFG_INST : BUFG port map (I=>CLKFX_BUF, O=>CLKFX_OUT); CLKIN_IBUFG_INST : IBUFG port map (I=>CLKIN_IN, O=>CLKIN_IBUFG); CLK0_BUFG_INST : BUFG port map (I=>CLK0_BUF, O=>CLKFB_IN); DCM_SP_INST : DCM_SP generic map( CLK_FEEDBACK => "1X", CLKDV_DIVIDE => 2.0, CLKFX_DIVIDE => 32, CLKFX_MULTIPLY => 19, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 31.250, CLKOUT_PHASE_SHIFT => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, FACTORY_JF => x"C080", PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) port map (CLKFB=>CLKFB_IN, CLKIN=>CLKIN_IBUFG, DSSEN=>GND_BIT, PSCLK=>GND_BIT, PSEN=>GND_BIT, PSINCDEC=>GND_BIT, RST=>GND_BIT, CLKDV=>open, CLKFX=>CLKFX_BUF, CLKFX180=>open, CLK0=>CLK0_BUF, CLK2X=>open, CLK2X180=>open, CLK90=>open, CLK180=>open, CLK270=>open, LOCKED=>open, PSDONE=>open, STATUS=>open); end BEHAVIORAL;

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 19:32:46 06/20/2014 -- Design Name: -- Module Name: channel_avg - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values USE ieee.numeric_std.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. LIBRARY UNISIM; USE UNISIM.VComponents.ALL; ENTITY channel_avg IS GENERIC ( NCH : positive := 16; OUTCH_WIDTH : positive := 16; INTERNAL_WIDTH : positive := 32; INDATA_WIDTH : positive := 256; OUTDATA_WIDTH : positive := 256 ); PORT ( RESET : IN std_logic; CLK : IN std_logic; -- high 4-bit is offset, 2**(low 4-bit) is number of points to average CONFIG : IN std_logic_vector(7 DOWNTO 0); TRIG : IN std_logic; INDATA_Q : IN std_logic_vector(INDATA_WIDTH-1 DOWNTO 0); OUTVALID : OUT std_logic; OUTDATA_Q : OUT std_logic_vector(OUTDATA_WIDTH-1 DOWNTO 0) ); END channel_avg; ARCHITECTURE Behavioral OF channel_avg IS SIGNAL trig_prev : std_logic; SIGNAL trig_prev1 : std_logic; SIGNAL trig_prev2 : std_logic; SIGNAL trig_synced : std_logic; -- SIGNAL avg_n : positive; -- TYPE INTERNALVAL IS ARRAY(NCH-1 DOWNTO 0) OF signed(INTERNAL_WIDTH-1 DOWNTO 0); SIGNAL inch_val : INTERNALVAL; SIGNAL internal_val : INTERNALVAL; BEGIN PROCESS (CLK) IS VARIABLE i : integer; BEGIN IF falling_edge(CLK) THEN -- register half-cycle earlier FOR i IN 0 TO NCH-1 LOOP inch_val(i) <= resize(signed(INDATA_Q(16*(i+1)-1 DOWNTO 16*i)), INTERNAL_WIDTH); END LOOP; END IF; END PROCESS; -- capture the rising edge of trigger PROCESS (CLK, RESET) IS BEGIN IF RESET = '1' THEN trig_prev <= '0'; trig_prev1 <= '0'; trig_prev2 <= '0'; ELSIF rising_edge(CLK) THEN trig_prev <= TRIG; trig_prev1 <= trig_prev; trig_prev2 <= trig_prev1; END IF; END PROCESS; trig_synced <= '1' WHEN trig_prev2 = '0' AND trig_prev1 = '1' ELSE '0'; avg_n <= to_integer(unsigned(CONFIG(3 DOWNTO 0))); PROCESS (CLK, RESET) IS VARIABLE i : integer; VARIABLE j : unsigned(15 DOWNTO 0); BEGIN IF RESET = '1' THEN FOR i IN 0 TO NCH-1 LOOP internal_val(i) <= (OTHERS => '0'); END LOOP; OUTVALID <= '0'; j := (OTHERS => '0'); ELSIF rising_edge(CLK) THEN IF trig_synced = '1' THEN j := resize(unsigned(CONFIG(7 DOWNTO 4)), j'length) + 1; END IF; FOR i IN 0 TO NCH-1 LOOP IF j = 1 THEN internal_val(i) <= inch_val(i); ELSE internal_val(i) <= internal_val(i) + inch_val(i); END IF; END LOOP; IF j(avg_n) = '1' THEN j := to_unsigned(1, j'length); OUTVALID <= '1'; ELSE j := j + 1; OUTVALID <= '0'; END IF; END IF; END PROCESS; outdata_q_inst : FOR i IN 0 TO NCH-1 GENERATE OUTDATA_Q(OUTCH_WIDTH*(i+1)-1 DOWNTO OUTCH_WIDTH*i) <= std_logic_vector(internal_val(i)(OUTCH_WIDTH-1+avg_n DOWNTO avg_n)); END GENERATE; END Behavioral;

-- $Id: serport_1clock.vhd 1181 2019-07-08 17:00:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2011-2015 by Walter F.J. Mueller <[email protected]> -- ------------------------------------------------------------------------------ -- Module Name: serport_1clock - syn -- Description: serial port: serial port module, 1 clock domain -- -- Dependencies: serport_uart_rxtx_ab -- serport_xonrx -- serport_xontx -- memlib/fifo_1c_dram -- Test bench: - -- Target Devices: generic -- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri -- 2015-04-12 666 14.7 131013 xc6slx16-2 171 239 32 94 s 6.3 -- 2011-11-13 424 13.1 O40d xc3s1000-4 157 337 64 232 s 9.9 -- -- Revision History: -- Date Rev Version Comment -- 2015-04-11 666 1.1.1 add sim assertions for RXOVR and RXERR -- 2015-02-01 641 1.1 add CLKDIV_F for autobaud; -- 2011-12-10 438 1.0.2 internal reset on abact -- 2011-12-09 437 1.0.1 rename stat->moni port -- 2011-11-13 424 1.0 Initial version -- 2011-10-23 419 0.5 First draft ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; use work.serportlib.all; use work.memlib.all; entity serport_1clock is -- serial port module, 1 clock domain generic ( CDWIDTH : positive := 13; -- clk divider width CDINIT : natural := 15; -- clk divider initial/reset setting RXFAWIDTH : natural := 5; -- rx fifo address width TXFAWIDTH : natural := 5); -- tx fifo address width port ( CLK : in slbit; -- clock CE_MSEC : in slbit; -- 1 msec clock enable RESET : in slbit; -- reset ENAXON : in slbit; -- enable xon/xoff handling ENAESC : in slbit; -- enable xon/xoff escaping RXDATA : out slv8; -- receiver data out RXVAL : out slbit; -- receiver data valid RXHOLD : in slbit; -- receiver data hold TXDATA : in slv8; -- transmit data in TXENA : in slbit; -- transmit data enable TXBUSY : out slbit; -- transmit busy MONI : out serport_moni_type; -- serport monitor port RXSD : in slbit; -- receive serial data (uart view) TXSD : out slbit; -- transmit serial data (uart view) RXRTS_N : out slbit; -- receive rts (uart view, act.low) TXCTS_N : in slbit -- transmit cts (uart view, act.low) ); end serport_1clock; architecture syn of serport_1clock is signal R_RXOK : slbit := '1'; signal RESET_INT : slbit := '0'; signal UART_RXDATA : slv8 := (others=>'0'); signal UART_RXVAL : slbit := '0'; signal UART_TXDATA : slv8 := (others=>'0'); signal UART_TXENA : slbit := '0'; signal UART_TXBUSY : slbit := '0'; signal XONTX_TXENA : slbit := '0'; signal XONTX_TXBUSY : slbit := '0'; signal RXFIFO_DI : slv8 := (others=>'0'); signal RXFIFO_ENA : slbit := '0'; signal RXFIFO_BUSY : slbit := '0'; signal RXFIFO_SIZE : slv(RXFAWIDTH downto 0) := (others=>'0'); signal TXFIFO_DO : slv8 := (others=>'0'); signal TXFIFO_VAL : slbit := '0'; signal TXFIFO_HOLD : slbit := '0'; signal RXERR : slbit := '0'; signal RXOVR : slbit := '0'; signal RXACT : slbit := '0'; signal ABACT : slbit := '0'; signal ABDONE : slbit := '0'; signal ABCLKDIV : slv(CDWIDTH-1 downto 0) := (others=>'0'); signal ABCLKDIV_F : slv3 := (others=>'0'); signal TXOK : slbit := '0'; signal RXOK : slbit := '0'; begin assert CDWIDTH<=16 report "assert(CDWIDTH<=16): max width of UART clock divider" severity failure; UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo generic map ( CDWIDTH => CDWIDTH, CDINIT => CDINIT) port map ( CLK => CLK, CE_MSEC => CE_MSEC, RESET => RESET, RXSD => RXSD, RXDATA => UART_RXDATA, RXVAL => UART_RXVAL, RXERR => RXERR, RXACT => RXACT, TXSD => TXSD, TXDATA => UART_TXDATA, TXENA => UART_TXENA, TXBUSY => UART_TXBUSY, ABACT => ABACT, ABDONE => ABDONE, ABCLKDIV => ABCLKDIV, ABCLKDIV_F => ABCLKDIV_F ); RESET_INT <= RESET or ABACT; XONRX : serport_xonrx -- xon/xoff logic rx path port map ( CLK => CLK, RESET => RESET_INT, ENAXON => ENAXON, ENAESC => ENAESC, UART_RXDATA => UART_RXDATA, UART_RXVAL => UART_RXVAL, RXDATA => RXFIFO_DI, RXVAL => RXFIFO_ENA, RXHOLD => RXFIFO_BUSY, RXOVR => RXOVR, TXOK => TXOK ); XONTX : serport_xontx -- xon/xoff logic tx path port map ( CLK => CLK, RESET => RESET_INT, ENAXON => ENAXON, ENAESC => ENAESC, UART_TXDATA => UART_TXDATA, UART_TXENA => XONTX_TXENA, UART_TXBUSY => XONTX_TXBUSY, TXDATA => TXFIFO_DO, TXENA => TXFIFO_VAL, TXBUSY => TXFIFO_HOLD, RXOK => RXOK, TXOK => TXOK ); RXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based generic map ( AWIDTH => RXFAWIDTH, DWIDTH => 8) port map ( CLK => CLK, RESET => RESET_INT, DI => RXFIFO_DI, ENA => RXFIFO_ENA, BUSY => RXFIFO_BUSY, DO => RXDATA, VAL => RXVAL, HOLD => RXHOLD, SIZE => RXFIFO_SIZE ); TXFIFO : fifo_1c_dram -- output fifo, 1 clock, dram based generic map ( AWIDTH => TXFAWIDTH, DWIDTH => 8) port map ( CLK => CLK, RESET => RESET_INT, DI => TXDATA, ENA => TXENA, BUSY => TXBUSY, DO => TXFIFO_DO, VAL => TXFIFO_VAL, HOLD => TXFIFO_HOLD, SIZE => open ); -- receive back pressure -- on if fifo more than 3/4 full -- off if fifo less than 1/2 full proc_rxok: process (CLK) constant rxsize_rxok_off : slv3 := "011"; constant rxsize_rxok_on : slv3 := "010"; variable rxsize_msb : slv3 := "000"; begin if rising_edge(CLK) then if RESET_INT = '1' then R_RXOK <= '1'; else rxsize_msb := RXFIFO_SIZE(RXFAWIDTH downto RXFAWIDTH-2); if unsigned(rxsize_msb) >= unsigned(rxsize_rxok_off) then R_RXOK <= '0'; elsif unsigned(rxsize_msb) <= unsigned(rxsize_rxok_on) then R_RXOK <= '1'; end if; end if; end if; end process proc_rxok; RXOK <= R_RXOK; RXRTS_N <= not R_RXOK; proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY) begin if TXCTS_N = '0' then -- transmit cts asserted UART_TXENA <= XONTX_TXENA; XONTX_TXBUSY <= UART_TXBUSY; else -- transmit cts not asserted UART_TXENA <= '0'; XONTX_TXBUSY <= '1'; end if; end process proc_cts; MONI.rxerr <= RXERR; MONI.rxovr <= RXOVR; MONI.rxact <= RXACT; MONI.txact <= UART_TXBUSY; MONI.abact <= ABACT; MONI.abdone <= ABDONE; MONI.rxok <= RXOK; MONI.txok <= TXOK; proc_abclkdiv: process (ABCLKDIV, ABCLKDIV_F) begin MONI.abclkdiv <= (others=>'0'); MONI.abclkdiv(ABCLKDIV'range) <= ABCLKDIV; MONI.abclkdiv_f <= ABCLKDIV_F; end process proc_abclkdiv; -- synthesis translate_off proc_check: process (CLK) begin if rising_edge(CLK) then assert RXOVR = '0' report "serport_1clock-W: RXOVR = " & slbit'image(RXOVR) & "; data loss in receive fifo" severity warning; assert RXERR = '0' report "serport_1clock-W: RXERR = " & slbit'image(RXERR) & "; spurious receive error" severity warning; end if; end process proc_check; -- synthesis translate_on end syn;

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block j568ylTKCX1ijKCu3zCEYX4KzYIJPurwijBGL11yx0O4LKHLMP8dlqw1rKJAJyrIFXxSA8VDlDyI zGGu45lCWA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Zsr0AQ+BVB+qiaA/LMGWEJP/NrZG3InNL+c379B92bObAE0efeTZpmUE1xBqjehQpvWUAwUx+nu1 ovOY8kEzNgIq2y7PBozDXLUFYCGPeG8YSvcca9nazpYZq3J1pYo73+j7dFLANXGQbyuVYrJ2fYen tlUyhv+6QbaysUJuVbI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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entity sig is end; architecture behav of sig is signal s : natural; signal last : time; begin s <= 1 after 20 ns; b: block port (q : boolean); port map (q => s'quiet(10 ns)); begin process (q) begin report "q is " & boolean'image (q); last <= now; end process; end block; process begin wait for 100 ns; assert last = 30 ns severity failure; wait; end process; end;

-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2094.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY vests9 IS END vests9; ARCHITECTURE c07s02b04x00p20n01i02094arch OF vests9 IS TYPE boolean_v is array (integer range <>) of boolean; SUBTYPE boolean_4 is boolean_v (1 to 4); SUBTYPE boolean_8 is boolean_v (1 to 8); FUNCTION return_array RETURN boolean_4 is constant l_operand : boolean_4 := (true,false,true,false); begin RETURN l_operand; end return_array; BEGIN l : block generic ( info : boolean_8 ); generic map ( return_array & return_array ); begin assert NOT(info = (true,false,true,false,true,false,true,false)) report "***PASSED TEST: c07s02b04x00p20n01i02094" severity NOTE; assert (info = (true,false,true,false,true,false,true,false)) report "***FAILED TEST: c07s02b04x00p20n01i02094 - Function array concatenation did not succeed." severity ERROR; end block; END c07s02b04x00p20n01i02094arch;

------------------------------------------------------------------- -- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. -- -- -- -- This file contains confidential and proprietary information -- -- of Xilinx, Inc. and is protected under U.S. and -- -- international copyright and other intellectual property -- -- laws. -- -- -- -- DISCLAIMER -- -- This disclaimer is not a license and does not grant any -- -- rights to the materials distributed herewith. Except as -- -- otherwise provided in a valid license issued to you by -- -- Xilinx, and to the maximum extent permitted by applicable -- -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- -- (2) Xilinx shall not be liable (whether in contract or tort, -- -- including negligence, or under any other theory of -- -- liability) for any loss or damage of any kind or nature -- -- related to, arising under or in connection with these -- -- materials, including for any direct, or any indirect, -- -- special, incidental, or consequential loss or damage -- -- (including loss of data, profits, goodwill, or any type of -- -- loss or damage suffered as a result of any action brought -- -- by a third party) even if such damage or loss was -- -- reasonably foreseeable or Xilinx had been advised of the -- -- possibility of the same. -- -- -- -- CRITICAL APPLICATIONS -- -- Xilinx products are not designed or intended to be fail- -- -- safe, or for use in any application requiring fail-safe -- -- performance, such as life-support or safety devices or -- -- systems, Class III medical devices, nuclear facilities, -- -- applications related to the deployment of airbags, or any -- -- other applications that could lead to death, personal -- -- injury, or severe property or environmental damage -- -- (individually and collectively, "Critical -- -- Applications"). Customer assumes the sole risk and -- -- liability of any use of Xilinx products in Critical -- -- Applications, subject only to applicable laws and -- -- regulations governing limitations on product liability. -- -- -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------- -- ************************************************************************ -- ------------------------------------------------------------------------------- -- Filename: address_decoder.vhd -- Version: v1.01.a -- Description: Address decoder utilizing unconstrained arrays for Base -- Address specification and ce number. ------------------------------------------------------------------------------- -- Structure: This section shows the hierarchical structure of axi_lite_ipif. -- -- --axi_lite_ipif.vhd -- --slave_attachment.vhd -- --address_decoder.vhd ------------------------------------------------------------------------------- -- Author: BSB -- -- History: -- -- BSB 05/20/10 -- First version -- ~~~~~~ -- - Created the first version v1.00.a -- ^^^^^^ -- ~~~~~~ -- SK 08/09/2010 -- -- - updated the core with optimziation. Closed CR 574507 -- - combined the CE generation logic to further optimize the code. -- ^^^^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; use work.common_types.all; ------------------------------------------------------------------------------- -- Definition of Generics ------------------------------------------------------------------------------- -- C_BUS_AWIDTH -- Address bus width -- C_S_AXI_MIN_SIZE -- Minimum address range of the IP -- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range -- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range -- C_FAMILY -- Target FPGA family ------------------------------------------------------------------------------- -- Definition of Ports ------------------------------------------------------------------------------- -- Bus_clk -- Clock -- Bus_rst -- Reset -- Address_In_Erly -- Adddress in -- Address_Valid_Erly -- Address is valid -- Bus_RNW -- Read or write registered -- Bus_RNW_Erly -- Read or Write -- CS_CE_ld_enable -- chip select and chip enable registered -- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear -- RW_CE_ld_enable -- Read or Write Chip Enable -- CS_for_gaps -- CS generation for the gaps between address ranges -- CS_Out -- Chip select -- RdCE_Out -- Read Chip enable -- WrCE_Out -- Write chip enable ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Entity Declaration ------------------------------------------------------------------------------- entity address_decoder is generic ( C_BUS_AWIDTH : integer := 32; C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF"; C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := ( X"0000_0000_1000_0000", -- IP user0 base address X"0000_0000_1000_01FF", -- IP user0 high address X"0000_0000_1000_0200", -- IP user1 base address X"0000_0000_1000_02FF" -- IP user1 high address ); C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 8, -- User0 CE Number 1 -- User1 CE Number ); C_FAMILY : string := "virtex6" ); port ( Bus_clk : in std_logic; Bus_rst : in std_logic; -- PLB Interface signals Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1); Address_Valid_Erly : in std_logic; Bus_RNW : in std_logic; Bus_RNW_Erly : in std_logic; -- Registering control signals CS_CE_ld_enable : in std_logic; Clear_CS_CE_Reg : in std_logic; RW_CE_ld_enable : in std_logic; CS_for_gaps : out std_logic; -- Decode output signals CS_Out : out std_logic_vector (0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1); RdCE_Out : out std_logic_vector (0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1); WrCE_Out : out std_logic_vector (0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) ); end entity address_decoder; ------------------------------------------------------------------------------- -- Architecture section ------------------------------------------------------------------------------- architecture IMP of address_decoder is -- local type declarations ---------------------------------------------------- type decode_bit_array_type is Array(natural range 0 to ( (C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of integer; type short_addr_array_type is Array(natural range 0 to C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of std_logic_vector(0 to C_BUS_AWIDTH-1); ------------------------------------------------------------------------------- -- Function Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- This function converts a 64 bit address range array to a AWIDTH bit -- address range array. ------------------------------------------------------------------------------- function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE; awidth : integer) return short_addr_array_type is variable temp_addr : std_logic_vector(0 to 63); variable slv_array : short_addr_array_type; begin for array_index in 0 to slv64_addr_array'length-1 loop temp_addr := slv64_addr_array(array_index); slv_array(array_index) := temp_addr((64-awidth) to 63); end loop; return(slv_array); end function slv64_2_slv_awidth; ------------------------------------------------------------------------------- --Function Addr_bits --function to convert an address range (base address and an upper address) --into the number of upper address bits needed for decoding a device --select signal. will handle slices and big or little endian ------------------------------------------------------------------------------- function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1)) return integer is variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1); begin addr_nor := x xor y; for i in 0 to C_BUS_AWIDTH-1 loop if addr_nor(i)='1' then return i; end if; end loop; --coverage off return(C_BUS_AWIDTH); --coverage on end function Addr_Bits; ------------------------------------------------------------------------------- --Function Get_Addr_Bits --function calculates the array which has the decode bits for the each address --range. ------------------------------------------------------------------------------- function Get_Addr_Bits (baseaddrs : short_addr_array_type) return decode_bit_array_type is variable num_bits : decode_bit_array_type; begin for i in 0 to ((baseaddrs'length)/2)-1 loop num_bits(i) := Addr_Bits (baseaddrs(i*2), baseaddrs(i*2+1)); end loop; return(num_bits); end function Get_Addr_Bits; ------------------------------------------------------------------------------- -- NEEDED_ADDR_BITS -- -- Function Description: -- This function calculates the number of address bits required -- to support the CE generation logic. This is determined by -- multiplying the number of CEs for an address space by the -- data width of the address space (in bytes). Each address -- space entry is processed and the biggest of the spaces is -- used to set the number of address bits required to be latched -- and used for CE decoding. A minimum value of 1 is returned by -- this function. -- ------------------------------------------------------------------------------- function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE) return integer is constant NUM_CE_ENTRIES : integer := CE_ARRAY'length; variable biggest : integer := 2; variable req_ce_addr_size : integer := 0; variable num_addr_bits : integer := 0; begin for i in 0 to NUM_CE_ENTRIES-1 loop req_ce_addr_size := ce_array(i) * 4; if (req_ce_addr_size > biggest) Then biggest := req_ce_addr_size; end if; end loop; num_addr_bits := clog2(biggest); return(num_addr_bits); end function NEEDED_ADDR_BITS; ----------------------------------------------------------------------------- -- Function calc_high_address -- -- This function is used to calculate the high address of the each address -- range ----------------------------------------------------------------------------- function calc_high_address (high_address : short_addr_array_type; index : integer) return std_logic_vector is variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1); begin If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31); else calc_high_addr := high_address(index*2+2); end if; return(calc_high_addr); end function calc_high_address; ---------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type := slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY, C_BUS_AWIDTH); constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2; constant DECODE_BITS : decode_bit_array_type := Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY); constant NUM_CE_SIGNALS : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY); constant NUM_S_H_ADDR_BITS : integer := needed_addr_bits(C_ARD_NUM_CE_ARRAY); ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- signal pselect_hit_i : std_logic_vector (0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1); signal cs_out_i : std_logic_vector (0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1); signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); -- signal cs_ce_clr : std_logic; signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1); signal Bus_RNW_reg : std_logic; ------------------------------------------------------------------------------- -- Begin architecture ------------------------------------------------------------------------------- begin -- architecture IMP -- Register clears cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg; addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS to C_BUS_AWIDTH-1); ------------------------------------------------------------------------------- -- MEM_DECODE_GEN: Universal Address Decode Block ------------------------------------------------------------------------------- MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate --------------- constant CE_INDEX_START : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index); constant CE_ADDR_SIZE : Integer range 0 to 15 := clog2(C_ARD_NUM_CE_ARRAY(bar_index)); constant OFFSET : integer := 2; constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1) := ARD_ADDR_RANGE_ARRAY(bar_index*2+1); constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1) := calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index); --constant DECODE_BITS_0 : integer:= DECODE_BITS(0); --------- begin --------- -- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address -- ----------------- GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate -- Instantiate the basic Base Address Decoders MEM_SELECT_I: entity work.pselect_f generic map ( C_AB => DECODE_BITS(bar_index), C_AW => C_BUS_AWIDTH, C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2), C_FAMILY => C_FAMILY ) port map ( A => Address_In_Erly, -- [in] AValid => Address_Valid_Erly, -- [in] CS => pselect_hit_i(bar_index) -- [out] ); end generate GEN_FOR_MULTI_CS; -- GEN_FOR_ONE_CS: below logic decodes the CS for single address range -- --------------- GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate pselect_hit_i(bar_index) <= Address_Valid_Erly; end generate GEN_FOR_ONE_CS; -- Instantate backend registers for the Chip Selects BKEND_CS_REG : process(Bus_Clk) begin if(Bus_Clk'EVENT and Bus_Clk = '1')then if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then cs_out_i(bar_index) <= '0'; elsif(CS_CE_ld_enable='1')then cs_out_i(bar_index) <= pselect_hit_i(bar_index); end if; end if; end process BKEND_CS_REG; ------------------------------------------------------------------------- -- PER_CE_GEN: Now expand the individual CEs for each base address. ------------------------------------------------------------------------- PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate ----------- begin ----------- ---------------------------------------------------------------------- -- CE decoders for multiple CE's ---------------------------------------------------------------------- MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) := std_logic_vector(to_unsigned(j,CE_ADDR_SIZE)); begin CE_I : entity work.pselect_f generic map ( C_AB => CE_ADDR_SIZE , C_AW => CE_ADDR_SIZE , C_BAR => BAR , C_FAMILY => C_FAMILY ) port map ( A => addr_out_s_h (NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE to NUM_S_H_ADDR_BITS - OFFSET - 1) , AValid => pselect_hit_i(bar_index) , CS => ce_expnd_i(CE_INDEX_START+j) ); end generate MULTIPLE_CES_THIS_CS_GEN; -------------------------------------- ---------------------------------------------------------------------- -- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE ---------------------------------------------------------------------- SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index); end generate; ------------- end generate PER_CE_GEN; ------------------------ end generate MEM_DECODE_GEN; -- RNW_REG_P: Register the incoming RNW signal at the time of registering the -- address. This is need to generate the CE's separately. RNW_REG_P:process(Bus_Clk) begin if(Bus_Clk'EVENT and Bus_Clk = '1')then if(RW_CE_ld_enable='1')then Bus_RNW_reg <= Bus_RNW_Erly; end if; end if; end process RNW_REG_P; --------------------------------------------------------------------------- -- GEN_BKEND_CE_REGISTERS -- This ForGen implements the backend registering for -- the CE, RdCE, and WrCE output buses. --------------------------------------------------------------------------- GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); ------ begin ------ BKEND_RDCE_REG : process(Bus_Clk) begin if(Bus_Clk'EVENT and Bus_Clk = '1')then if(cs_ce_clr='1')then ce_out_i(ce_index) <= '0'; elsif(RW_CE_ld_enable='1')then ce_out_i(ce_index) <= ce_expnd_i(ce_index); end if; end if; end process BKEND_RDCE_REG; rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg; wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg; ------------------------------- end generate GEN_BKEND_CE_REGISTERS; ------------------------------------------------------------------------------- CS_for_gaps <= '0'; -- Removed the GAP adecoder logic --------------------------------- CS_Out <= cs_out_i ; RdCE_Out <= rdce_out_i ; WrCE_Out <= wrce_out_i ; end architecture IMP;

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- package: uart -- File: uart.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: UART types and components ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; package uart is type uart_in_type is record rxd : std_ulogic; ctsn : std_ulogic; extclk : std_ulogic; end record; type uart_out_type is record rtsn : std_ulogic; txd : std_ulogic; scaler : std_logic_vector(31 downto 0); txen : std_ulogic; flow : std_ulogic; rxen : std_ulogic; end record; component apbuart generic ( pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff#; console : integer := 0; pirq : integer := 0; parity : integer := 1; flow : integer := 1; fifosize : integer range 1 to 32 := 1; abits : integer := 8; sbits : integer range 12 to 32 := 12); port ( rst : in std_ulogic; clk : in std_ulogic; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; uarti : in uart_in_type; uarto : out uart_out_type); end component; component ahbuart generic ( hindex : integer := 0; pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff# ); port ( rst : in std_ulogic; clk : in std_ulogic; uarti : in uart_in_type; uarto : out uart_out_type; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; ahbi : in ahb_mst_in_type; ahbo : out ahb_mst_out_type); end component; end;

-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc881.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c10s01b00x00p06n01i00881PKG is -- VAL1 is here a constant constant VAL1 : INTEGER := 65; type DBLINTREC is record -- VAL1 is here a record element VAL1 : INTEGER; VAL2 : INTEGER; end record; end c10s01b00x00p06n01i00881PKG; use WORK.c10s01b00x00p06n01i00881PKG.DBLINTREC; entity c10s01b00x00p06n01i00881ent_a is port ( PS1: in DBLINTREC; PS2: out DBLINTREC ); end c10s01b00x00p06n01i00881ent_a; architecture c10s01b00x00p06n01i00881arch_a of c10s01b00x00p06n01i00881ent_a is begin process begin PS2.VAL1 <= PS1.VAL1 + 1; PS2.VAL2 <= PS1.VAL2 + 2; wait; end process; end c10s01b00x00p06n01i00881arch_a; use WORK.c10s01b00x00p06n01i00881PKG.DBLINTREC; use WORK.c10s01b00x00p06n01i00881ent_a; ENTITY c10s01b00x00p06n01i00881ent IS END c10s01b00x00p06n01i00881ent; ARCHITECTURE c10s01b00x00p06n01i00881arch OF c10s01b00x00p06n01i00881ent IS component c10s01b00x00p06n01i00881ent_a port ( PS1: in DBLINTREC; PS2: out DBLINTREC ); end component; for A1: c10s01b00x00p06n01i00881ent_a use entity work.c10s01b00x00p06n01i00881ent_a ( c10s01b00x00p06n01i00881arch_a ); signal S1: DBLINTREC := (3, 9); signal S2: DBLINTREC := (0, 0); BEGIN A1: c10s01b00x00p06n01i00881ent_a port map ( S1, S2 ); TESTING: PROCESS BEGIN wait for 1 ns; -- let a time increment go by so init done assert ( S2.VAL1 = 4 ) report "didn't add to record element S2.VAL1 correctly" severity FAILURE; assert ( S2.VAL2 = 11 ) report "didn't add to record element S2.VAL2 correctly" severity FAILURE; assert NOT( S2.VAL1 = 4 and S2.VAL2 =11 ) report "***PASSED TEST: c10s01b00x00p06n01i00881" severity NOTE; assert ( S2.VAL1 = 4 and S2.VAL2 =11 ) report "***FAILED TEST: c10s01b00x00p06n01i00881 - A declaratione region is formed by a record type declaration." severity ERROR; wait; END PROCESS TESTING; END c10s01b00x00p06n01i00881arch;

-- -- A simulation model of VIC20 hardware -- Copyright (c) MikeJ - March 2003 -- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written permission. -- -- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- You are responsible for any legal issues arising from your use of this code. -- -- The latest version of this file can be found at: www.fpgaarcade.com -- -- Email [email protected] -- -- -- Revision list -- -- version 004 fixes to PB7 T1 control and Mode 0 Shift Register operation -- version 003 fix reset of T1/T2 IFR flags if T1/T2 is reload via reg5/reg9 from wolfgang (WoS) -- Ported to numeric_std and simulation fix for signal initializations from arnim laeuger -- version 002 fix from Mark McDougall, untested -- version 001 initial release -- not very sure about the shift register, documentation is a bit light. library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity M6522 is port ( I_RS : in std_logic_vector(3 downto 0); I_DATA : in std_logic_vector(7 downto 0); O_DATA : out std_logic_vector(7 downto 0); O_DATA_OE_L : out std_logic; I_RW_L : in std_logic; I_CS1 : in std_logic; I_CS2_L : in std_logic; O_IRQ_L : out std_logic; -- note, not open drain -- port a I_CA1 : in std_logic; I_CA2 : in std_logic; O_CA2 : out std_logic; O_CA2_OE_L : out std_logic; I_PA : in std_logic_vector(7 downto 0); O_PA : out std_logic_vector(7 downto 0); O_PA_OE_L : out std_logic_vector(7 downto 0); -- port b I_CB1 : in std_logic; O_CB1 : out std_logic; O_CB1_OE_L : out std_logic; I_CB2 : in std_logic; O_CB2 : out std_logic; O_CB2_OE_L : out std_logic; I_PB : in std_logic_vector(7 downto 0); O_PB : out std_logic_vector(7 downto 0); O_PB_OE_L : out std_logic_vector(7 downto 0); I_P2_H : in std_logic; -- high for phase 2 clock ____----__ RESET_L : in std_logic; ENA_4 : in std_logic; -- clk enable CLK : in std_logic ); end; architecture RTL of M6522 is signal phase : std_logic_vector(1 downto 0):="00"; signal p2_h_t1 : std_logic; signal cs : std_logic; -- registers signal r_ddra : std_logic_vector(7 downto 0); signal r_ora : std_logic_vector(7 downto 0); signal r_ira : std_logic_vector(7 downto 0); signal r_ddrb : std_logic_vector(7 downto 0); signal r_orb : std_logic_vector(7 downto 0); signal r_irb : std_logic_vector(7 downto 0); signal r_t1l_l : std_logic_vector(7 downto 0); signal r_t1l_h : std_logic_vector(7 downto 0); signal r_t2l_l : std_logic_vector(7 downto 0); signal r_t2l_h : std_logic_vector(7 downto 0); -- not in real chip signal r_sr : std_logic_vector(7 downto 0); signal r_acr : std_logic_vector(7 downto 0); signal r_pcr : std_logic_vector(7 downto 0); signal r_ifr : std_logic_vector(7 downto 0); signal r_ier : std_logic_vector(6 downto 0); signal sr_write_ena : boolean; signal sr_read_ena : boolean; signal ifr_write_ena : boolean; signal ier_write_ena : boolean; signal clear_irq : std_logic_vector(7 downto 0); signal load_data : std_logic_vector(7 downto 0); -- timer 1 signal t1c : std_logic_vector(15 downto 0) := (others => '1'); -- simulators may not catch up w/o init here... signal t1c_active : boolean; signal t1c_done : boolean; signal t1_w_reset_int : boolean; signal t1_r_reset_int : boolean; signal t1_load_counter : boolean; signal t1_reload_counter : boolean; signal t1_toggle : std_logic; signal t1_irq : std_logic := '0'; -- timer 2 signal t2c : std_logic_vector(15 downto 0) := (others => '1'); -- simulators may not catch up w/o init here... signal t2c_active : boolean; signal t2c_done : boolean; signal t2_pb6 : std_logic; signal t2_pb6_t1 : std_logic; signal t2_w_reset_int : boolean; signal t2_r_reset_int : boolean; signal t2_load_counter : boolean; signal t2_reload_counter : boolean; signal t2_irq : std_logic := '0'; signal t2_sr_ena : boolean; -- shift reg signal sr_cnt : std_logic_vector(3 downto 0); signal sr_cb1_oe_l : std_logic; signal sr_cb1_out : std_logic; signal sr_drive_cb2 : std_logic; signal sr_strobe : std_logic; signal sr_strobe_t1 : std_logic; signal sr_strobe_falling : boolean; signal sr_strobe_rising : boolean; signal sr_irq : std_logic; signal sr_out : std_logic; signal sr_off_delay : std_logic; -- io signal w_orb_hs : std_logic; signal w_ora_hs : std_logic; signal r_irb_hs : std_logic; signal r_ira_hs : std_logic; signal ca_hs_sr : std_logic; signal ca_hs_pulse : std_logic; signal cb_hs_sr : std_logic; signal cb_hs_pulse : std_logic; signal cb1_in_mux : std_logic; signal ca1_ip_reg : std_logic; signal cb1_ip_reg : std_logic; signal ca1_int : boolean; signal cb1_int : boolean; signal ca1_irq : std_logic; signal cb1_irq : std_logic; signal ca2_ip_reg : std_logic; signal cb2_ip_reg : std_logic; signal ca2_int : boolean; signal cb2_int : boolean; signal ca2_irq : std_logic; signal cb2_irq : std_logic; signal final_irq : std_logic; begin p_phase : process begin -- internal clock phase wait until rising_edge(CLK); if (ENA_4 = '1') then p2_h_t1 <= I_P2_H; if (p2_h_t1 = '0') and (I_P2_H = '1') then phase <= "11"; else phase <= phase + "1"; end if; end if; end process; p_cs : process(I_CS1, I_CS2_L, I_P2_H) begin cs <= '0'; if (I_CS1 = '1') and (I_CS2_L = '0') and (I_P2_H = '1') then cs <= '1'; end if; end process; -- peripheral control reg (pcr) -- 0 ca1 interrupt control (0 +ve edge, 1 -ve edge) -- 3..1 ca2 operation -- 000 input -ve edge -- 001 independend interrupt input -ve edge -- 010 input +ve edge -- 011 independend interrupt input +ve edge -- 100 handshake output -- 101 pulse output -- 110 low output -- 111 high output -- 7..4 as 3..0 for cb1,cb2 -- auxiliary control reg (acr) -- 0 input latch PA (0 disable, 1 enable) -- 1 input latch PB (0 disable, 1 enable) -- 4..2 shift reg control -- 000 disable -- 001 shift in using t2 -- 010 shift in using o2 -- 011 shift in using ext clk -- 100 shift out free running t2 rate -- 101 shift out using t2 -- 101 shift out using o2 -- 101 shift out using ext clk -- 5 t2 timer control (0 timed interrupt, 1 count down with pulses on pb6) -- 7..6 t1 timer control -- 00 timed interrupt each time t1 is loaded pb7 disable -- 01 continuous interrupts pb7 disable -- 00 timed interrupt each time t1 is loaded pb7 one shot output -- 01 continuous interrupts pb7 square wave output -- p_write_reg_reset : process(RESET_L, CLK) begin if (RESET_L = '0') then r_ora <= x"00"; r_orb <= x"00"; r_ddra <= x"00"; r_ddrb <= x"00"; r_acr <= x"00"; r_pcr <= x"00"; w_orb_hs <= '0'; w_ora_hs <= '0'; elsif rising_edge(CLK) then if (ENA_4 = '1') then w_orb_hs <= '0'; w_ora_hs <= '0'; if (cs = '1') and (I_RW_L = '0') then case I_RS is when x"0" => r_orb <= I_DATA; w_orb_hs <= '1'; when x"1" => r_ora <= I_DATA; w_ora_hs <= '1'; when x"2" => r_ddrb <= I_DATA; when x"3" => r_ddra <= I_DATA; when x"B" => r_acr <= I_DATA; when x"C" => r_pcr <= I_DATA; when x"F" => r_ora <= I_DATA; when others => null; end case; end if; if r_acr(7) = '1' then -- DMB: Forgetting to clear B7 broke Acornsoft Planetoid if t1_load_counter then r_orb(7) <= '0'; -- writing T1C-H resets bit 7 elsif t1_toggle = '1' then r_orb(7) <= not r_orb(7); -- toggle end if; end if; end if; end if; end process; p_write_reg : process (RESET_L, CLK) is begin if (RESET_L = '0') then -- The spec says, this is not reset. -- Fact is that the 1541 VIA1 timer won't work, -- as the firmware ONLY sets the r_t1l_h latch!!!! r_t1l_l <= (others => '0'); r_t1l_h <= (others => '0'); r_t2l_l <= (others => '0'); r_t2l_h <= (others => '0'); elsif rising_edge(CLK) then if (ENA_4 = '1') then t1_w_reset_int <= false; t1_load_counter <= false; t2_w_reset_int <= false; t2_load_counter <= false; load_data <= x"00"; sr_write_ena <= false; ifr_write_ena <= false; ier_write_ena <= false; if (cs = '1') and (I_RW_L = '0') then load_data <= I_DATA; case I_RS is when x"4" => r_t1l_l <= I_DATA; when x"5" => r_t1l_h <= I_DATA; t1_w_reset_int <= true; t1_load_counter <= true; when x"6" => r_t1l_l <= I_DATA; when x"7" => r_t1l_h <= I_DATA; t1_w_reset_int <= true; when x"8" => r_t2l_l <= I_DATA; when x"9" => r_t2l_h <= I_DATA; t2_w_reset_int <= true; t2_load_counter <= true; when x"A" => sr_write_ena <= true; when x"D" => ifr_write_ena <= true; when x"E" => ier_write_ena <= true; when others => null; end case; end if; end if; end if; end process; p_oe : process(cs, I_RW_L) begin O_DATA_OE_L <= '1'; if (cs = '1') and (I_RW_L = '1') then O_DATA_OE_L <= '0'; end if; end process; p_read : process(cs, I_RW_L, I_RS, r_irb, r_ira, r_ddrb, r_ddra, t1c, r_t1l_l, r_t1l_h, t2c, r_sr, r_acr, r_pcr, r_ifr, r_ier, r_orb) begin t1_r_reset_int <= false; t2_r_reset_int <= false; sr_read_ena <= false; r_irb_hs <= '0'; r_ira_hs <= '0'; O_DATA <= x"00"; -- default if (cs = '1') and (I_RW_L = '1') then case I_RS is --when x"0" => O_DATA <= r_irb; r_irb_hs <= '1'; -- fix from Mark McDougall, untested when x"0" => O_DATA <= (r_irb and not r_ddrb) or (r_orb and r_ddrb); r_irb_hs <= '1'; when x"1" => O_DATA <= r_ira; r_ira_hs <= '1'; when x"2" => O_DATA <= r_ddrb; when x"3" => O_DATA <= r_ddra; when x"4" => O_DATA <= t1c( 7 downto 0); t1_r_reset_int <= true; when x"5" => O_DATA <= t1c(15 downto 8); when x"6" => O_DATA <= r_t1l_l; when x"7" => O_DATA <= r_t1l_h; when x"8" => O_DATA <= t2c( 7 downto 0); t2_r_reset_int <= true; when x"9" => O_DATA <= t2c(15 downto 8); when x"A" => O_DATA <= r_sr; sr_read_ena <= true; when x"B" => O_DATA <= r_acr; when x"C" => O_DATA <= r_pcr; when x"D" => O_DATA <= r_ifr; when x"E" => O_DATA <= ('0' & r_ier); when x"F" => O_DATA <= r_ira; when others => null; end case; end if; end process; -- -- IO -- p_ca1_cb1_sel : process(sr_cb1_oe_l, sr_cb1_out, I_CB1) begin -- if the shift register is enabled, cb1 may be an output -- in this case, we should listen to the CB1_OUT for the interrupt if (sr_cb1_oe_l = '1') then cb1_in_mux <= I_CB1; else cb1_in_mux <= sr_cb1_out; end if; end process; p_ca1_cb1_int : process(r_pcr, ca1_ip_reg, I_CA1, cb1_ip_reg, cb1_in_mux) begin if (r_pcr(0) = '0') then -- ca1 control -- negative edge ca1_int <= (ca1_ip_reg = '1') and (I_CA1 = '0'); else -- positive edge ca1_int <= (ca1_ip_reg = '0') and (I_CA1 = '1'); end if; if (r_pcr(4) = '0') then -- cb1 control -- negative edge cb1_int <= (cb1_ip_reg = '1') and (cb1_in_mux = '0'); else -- positive edge cb1_int <= (cb1_ip_reg = '0') and (cb1_in_mux = '1'); end if; end process; p_ca2_cb2_int : process(r_pcr, ca2_ip_reg, I_CA2, cb2_ip_reg, I_CB2) begin ca2_int <= false; if (r_pcr(3) = '0') then -- ca2 input if (r_pcr(2) = '0') then -- ca2 edge -- negative edge ca2_int <= (ca2_ip_reg = '1') and (I_CA2 = '0'); else -- positive edge ca2_int <= (ca2_ip_reg = '0') and (I_CA2 = '1'); end if; end if; cb2_int <= false; if (r_pcr(7) = '0') then -- cb2 input if (r_pcr(6) = '0') then -- cb2 edge -- negative edge cb2_int <= (cb2_ip_reg = '1') and (I_CB2 = '0'); else -- positive edge cb2_int <= (cb2_ip_reg = '0') and (I_CB2 = '1'); end if; end if; end process; p_ca2_cb2 : process(RESET_L, CLK) begin if (RESET_L = '0') then O_CA2 <= '0'; O_CA2_OE_L <= '1'; O_CB2 <= '0'; O_CB2_OE_L <= '1'; ca_hs_sr <= '0'; ca_hs_pulse <= '0'; cb_hs_sr <= '0'; cb_hs_pulse <= '0'; elsif rising_edge(CLK) then if (ENA_4 = '1') then -- ca if (phase = "00") and ((w_ora_hs = '1') or (r_ira_hs = '1')) then ca_hs_sr <= '1'; elsif ca1_int then ca_hs_sr <= '0'; end if; if (phase = "00") then ca_hs_pulse <= w_ora_hs or r_ira_hs; end if; O_CA2_OE_L <= not r_pcr(3); -- ca2 output case r_pcr(3 downto 1) is when "000" => O_CA2 <= '0'; -- input when "001" => O_CA2 <= '0'; -- input when "010" => O_CA2 <= '0'; -- input when "011" => O_CA2 <= '0'; -- input when "100" => O_CA2 <= not (ca_hs_sr); -- handshake when "101" => O_CA2 <= not (ca_hs_pulse); -- pulse when "110" => O_CA2 <= '0'; -- low when "111" => O_CA2 <= '1'; -- high when others => null; end case; -- cb if (phase = "00") and (w_orb_hs = '1') then cb_hs_sr <= '1'; elsif cb1_int then cb_hs_sr <= '0'; end if; if (phase = "00") then cb_hs_pulse <= w_orb_hs; end if; O_CB2_OE_L <= not (r_pcr(7) or sr_drive_cb2); -- cb2 output or serial if (sr_drive_cb2 = '1') then -- serial output O_CB2 <= sr_out; else case r_pcr(7 downto 5) is when "000" => O_CB2 <= '0'; -- input when "001" => O_CB2 <= '0'; -- input when "010" => O_CB2 <= '0'; -- input when "011" => O_CB2 <= '0'; -- input when "100" => O_CB2 <= not (cb_hs_sr); -- handshake when "101" => O_CB2 <= not (cb_hs_pulse); -- pulse when "110" => O_CB2 <= '0'; -- low when "111" => O_CB2 <= '1'; -- high when others => null; end case; end if; end if; end if; end process; O_CB1 <= sr_cb1_out; O_CB1_OE_L <= sr_cb1_oe_l; p_ca_cb_irq : process(RESET_L, CLK) begin if (RESET_L = '0') then ca1_irq <= '0'; ca2_irq <= '0'; cb1_irq <= '0'; cb2_irq <= '0'; elsif rising_edge(CLK) then if (ENA_4 = '1') then -- not pretty if ca1_int then ca1_irq <= '1'; elsif (r_ira_hs = '1') or (w_ora_hs = '1') or (clear_irq(1) = '1') then ca1_irq <= '0'; end if; if ca2_int then ca2_irq <= '1'; else if (((r_ira_hs = '1') or (w_ora_hs = '1')) and (r_pcr(1) = '0')) or (clear_irq(0) = '1') then ca2_irq <= '0'; end if; end if; if cb1_int then cb1_irq <= '1'; elsif (r_irb_hs = '1') or (w_orb_hs = '1') or (clear_irq(4) = '1') then cb1_irq <= '0'; end if; if cb2_int then cb2_irq <= '1'; else if (((r_irb_hs = '1') or (w_orb_hs = '1')) and (r_pcr(5) = '0')) or (clear_irq(3) = '1') then cb2_irq <= '0'; end if; end if; end if; end if; end process; p_input_reg : process(RESET_L, CLK) begin if (RESET_L = '0') then ca1_ip_reg <= '0'; cb1_ip_reg <= '0'; ca2_ip_reg <= '0'; cb2_ip_reg <= '0'; r_ira <= x"00"; r_irb <= x"00"; elsif rising_edge(CLK) then if (ENA_4 = '1') then -- we have a fast clock, so we can have input registers ca1_ip_reg <= I_CA1; cb1_ip_reg <= cb1_in_mux; ca2_ip_reg <= I_CA2; cb2_ip_reg <= I_CB2; if (r_acr(0) = '0') then r_ira <= I_PA; else -- enable latching if ca1_int then r_ira <= I_PA; end if; end if; if (r_acr(1) = '0') then r_irb <= I_PB; else -- enable latching if cb1_int then r_irb <= I_PB; end if; end if; end if; end if; end process; p_buffers : process(r_ddra, r_ora, r_ddrb, r_acr, r_orb) begin -- data direction reg (ddr) 0 = input, 1 = output O_PA <= r_ora; O_PA_OE_L <= not r_ddra; if (r_acr(7) = '1') then -- not clear if r_ddrb(7) must be 1 as well O_PB_OE_L(7) <= '0'; -- an output if under t1 control else O_PB_OE_L(7) <= not (r_ddrb(7)); end if; O_PB_OE_L(6 downto 0) <= not r_ddrb(6 downto 0); O_PB(7 downto 0) <= r_orb(7 downto 0); end process; -- -- Timer 1 -- p_timer1_done : process variable done : boolean; begin wait until rising_edge(CLK); if (ENA_4 = '1') then done := (t1c = x"0000"); t1c_done <= done and (phase = "11"); if (phase = "11") then t1_reload_counter <= done and (r_acr(6) = '1'); end if; if t1_load_counter then -- done reset on load! t1c_done <= false; end if; end if; end process; p_timer1 : process begin wait until rising_edge(CLK); if (ENA_4 = '1') then if t1_load_counter or (t1_reload_counter and phase = "11") then t1c( 7 downto 0) <= r_t1l_l; t1c(15 downto 8) <= r_t1l_h; elsif (phase="11") then t1c <= t1c - "1"; end if; if t1_load_counter or t1_reload_counter then t1c_active <= true; elsif t1c_done then t1c_active <= false; end if; t1_toggle <= '0'; if t1c_active and t1c_done then t1_toggle <= '1'; t1_irq <= '1'; elsif t1_w_reset_int or t1_r_reset_int or (clear_irq(6) = '1') then t1_irq <= '0'; end if; if t1_load_counter then -- irq reset on load! t1_irq <= '0'; end if; end if; end process; -- -- Timer2 -- p_timer2_pb6_input : process begin wait until rising_edge(CLK); if (ENA_4 = '1') then if (phase = "01") then -- leading edge p2_h t2_pb6 <= I_PB(6); t2_pb6_t1 <= t2_pb6; end if; end if; end process; p_timer2_done : process variable done : boolean; begin wait until rising_edge(CLK); if (ENA_4 = '1') then done := (t2c = x"0000"); t2c_done <= done and (phase = "11"); if (phase = "11") then t2_reload_counter <= done; end if; if t2_load_counter then -- done reset on load! t2c_done <= false; end if; end if; end process; p_timer2 : process variable ena : boolean; begin wait until rising_edge(CLK); if (ENA_4 = '1') then if (r_acr(5) = '0') then ena := true; else ena := (t2_pb6_t1 = '1') and (t2_pb6 = '0'); -- falling edge end if; if t2_load_counter or (t2_reload_counter and phase = "11") then -- not sure if t2c_reload should be here. Does timer2 just continue to -- count down, or is it reloaded ? Reloaded makes more sense if using -- it to generate a clock for the shift register. t2c( 7 downto 0) <= r_t2l_l; t2c(15 downto 8) <= r_t2l_h; else if (phase="11") and ena then -- or count mode t2c <= t2c - "1"; end if; end if; t2_sr_ena <= (t2c(7 downto 0) = x"00") and (phase = "11"); if t2_load_counter then t2c_active <= true; elsif t2c_done then t2c_active <= false; end if; if t2c_active and t2c_done then t2_irq <= '1'; elsif t2_w_reset_int or t2_r_reset_int or (clear_irq(5) = '1') then t2_irq <= '0'; end if; if t2_load_counter then -- irq reset on load! t2_irq <= '0'; end if; end if; end process; -- -- Shift Register -- p_sr : process(RESET_L, CLK) variable dir_out : std_logic; variable ena : std_logic; variable cb1_op : std_logic; variable cb1_ip : std_logic; variable use_t2 : std_logic; variable free_run : std_logic; variable sr_count_ena : boolean; begin if (RESET_L = '0') then r_sr <= x"00"; sr_drive_cb2 <= '0'; sr_cb1_oe_l <= '1'; sr_cb1_out <= '0'; sr_strobe <= '1'; sr_cnt <= "0000"; sr_irq <= '0'; sr_out <= '1'; sr_off_delay <= '0'; elsif rising_edge(CLK) then if (ENA_4 = '1') then -- decode mode dir_out := r_acr(4); -- output on cb2 cb1_op := '0'; cb1_ip := '0'; use_t2 := '0'; free_run := '0'; -- DMB: SR still runs even in disabled mode (on rising edge of CB1). -- It just doesn't generate any interrupts. -- Ref BBC micro advanced user guide p409 case r_acr(4 downto 2) is -- DMB: in disabled mode, configure cb1 as an input when "000" => ena := '0'; cb1_ip := '1'; when "001" => ena := '1'; cb1_op := '1'; use_t2 := '1'; when "010" => ena := '1'; cb1_op := '1'; when "011" => ena := '1'; cb1_ip := '1'; when "100" => ena := '1'; use_t2 := '1'; free_run := '1'; when "101" => ena := '1'; cb1_op := '1'; use_t2 := '1'; when "110" => ena := '1'; when "111" => ena := '1'; cb1_ip := '1'; when others => null; end case; -- clock select -- DMB: in disabled mode, strobe from cb1 if (cb1_ip = '1') then sr_strobe <= I_CB1; else if (sr_cnt(3) = '0') and (free_run = '0') then sr_strobe <= '1'; else if ((use_t2 = '1') and t2_sr_ena) or ((use_t2 = '0') and (phase = "00")) then sr_strobe <= not sr_strobe; end if; end if; end if; -- latch on rising edge, shift on falling edge if sr_write_ena then r_sr <= load_data; else -- DMB: allow shifting in all modes if (dir_out = '0') then -- input if (sr_cnt(3) = '1') or (cb1_ip = '1') then if sr_strobe_rising then r_sr(0) <= I_CB2; elsif sr_strobe_falling then r_sr(7 downto 1) <= r_sr(6 downto 0); end if; end if; sr_out <= '1'; else -- output if (sr_cnt(3) = '1') or (sr_off_delay = '1') or (cb1_ip = '1') or (free_run = '1') then if sr_strobe_falling then r_sr(7 downto 1) <= r_sr(6 downto 0); r_sr(0) <= r_sr(7); sr_out <= r_sr(7); end if; else sr_out <= '1'; end if; end if; end if; sr_count_ena := sr_strobe_rising; -- DMB: reseting sr_count when not enabled cause the sr to -- start running immediately it was enabled, which is incorrect -- and broke the latest SmartSPI ROM on the BBC Micro if ena = '1' and (sr_write_ena or sr_read_ena) then -- some documentation says sr bit in IFR must be set as well ? sr_cnt <= "1000"; elsif sr_count_ena and (sr_cnt(3) = '1') then sr_cnt <= sr_cnt + "1"; end if; if (phase = "00") then sr_off_delay <= sr_cnt(3); -- give some hold time when shifting out end if; if sr_count_ena and (sr_cnt = "1111") and (ena = '1') and (free_run = '0') then sr_irq <= '1'; elsif sr_write_ena or sr_read_ena or (clear_irq(2) = '1') then sr_irq <= '0'; end if; -- assign ops sr_drive_cb2 <= dir_out; sr_cb1_oe_l <= not cb1_op; sr_cb1_out <= sr_strobe; end if; end if; end process; p_sr_strobe_rise_fall : process begin wait until rising_edge(CLK); if (ENA_4 = '1') then sr_strobe_t1 <= sr_strobe; sr_strobe_rising <= (sr_strobe_t1 = '0') and (sr_strobe = '1'); sr_strobe_falling <= (sr_strobe_t1 = '1') and (sr_strobe = '0'); end if; end process; -- -- Interrupts -- p_ier : process(RESET_L, CLK) begin if (RESET_L = '0') then r_ier <= "0000000"; elsif rising_edge(CLK) then if (ENA_4 = '1') then if ier_write_ena then if (load_data(7) = '1') then -- set r_ier <= r_ier or load_data(6 downto 0); else -- clear r_ier <= r_ier and not load_data(6 downto 0); end if; end if; end if; end if; end process; p_ifr : process(t1_irq, t2_irq, final_irq, ca1_irq, ca2_irq, sr_irq, cb1_irq, cb2_irq) begin r_ifr(7) <= final_irq; r_ifr(6) <= t1_irq; r_ifr(5) <= t2_irq; r_ifr(4) <= cb1_irq; r_ifr(3) <= cb2_irq; r_ifr(2) <= sr_irq; r_ifr(1) <= ca1_irq; r_ifr(0) <= ca2_irq; O_IRQ_L <= not final_irq; end process; p_irq : process(RESET_L, CLK) begin if (RESET_L = '0') then final_irq <= '0'; elsif rising_edge(CLK) then if (ENA_4 = '1') then if ((r_ifr(6 downto 0) and r_ier(6 downto 0)) = "0000000") then final_irq <= '0'; -- no interrupts else final_irq <= '1'; end if; end if; end if; end process; p_clear_irq : process(ifr_write_ena, load_data) begin clear_irq <= x"00"; if ifr_write_ena then clear_irq <= load_data; end if; end process; end architecture RTL;

------------------------------------------------------------------------------- -- Title : test_order -- Project : ------------------------------------------------------------------------------- -- File : test_order.vhd -- Author : <kristoffer.nordstrom@HELVNB0100> -- Company : -- Created : 2015-04-27 -- Last update: 2015-05-20 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2015 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2015-04-27 1.0 kn Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.test_order_pkg.all; ------------------------------------------------------------------------------- entity test_order is port ( Clk : in std_logic; Clr : in std_logic; Order_A : in std_logic_vector(3 downto 0); Order_B : in std_logic_vector(3 downto 0); Order_AB : out std_logic_vector(4 downto 0) ); end entity test_order; ------------------------------------------------------------------------------- architecture str of test_order is ----------------------------------------------------------------------------- -- Internal signal declarations ----------------------------------------------------------------------------- signal AB : unsigned(Order_AB'range); begin -- architecture str ----------------------------------------------------------------------------- -- Output assignments ----------------------------------------------------------------------------- Order_AB <= std_logic_vector(AB); ----------------------------------------------------------------------------- -- Component instantiations ----------------------------------------------------------------------------- p_addAandB: process (Clk) is begin -- process p_addAandB if Clk'event and Clk = '1' then -- rising clock edge if Clr = '1' then AB <= to_unsigned(0, AB'length); else AB <= resize(unsigned(Order_A), AB'length) + resize(unsigned(Order_B), AB'length); end if; end if; end process p_addAandB; assert THE_TRUTH = 42 report "No answer to the question." severity error; end architecture str; -------------------------------------------------------------------------------

-------------------------------------------------------------------------------- -- -- FIFO Generator Core - core top file for implementation -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_1_exdes.vhd -- -- Description: -- This is the FIFO core wrapper with BUFG instances for clock connections. -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; -------------------------------------------------------------------------------- -- Entity Declaration -------------------------------------------------------------------------------- entity system_axi_dma_0_wrapper_fifo_generator_v9_3_1_exdes is PORT ( CLK : IN std_logic; DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0); WR_ACK : OUT std_logic; VALID : OUT std_logic; ALMOST_EMPTY : OUT std_logic; SRST : IN std_logic; WR_EN : IN std_logic; RD_EN : IN std_logic; DIN : IN std_logic_vector(39-1 DOWNTO 0); DOUT : OUT std_logic_vector(39-1 DOWNTO 0); FULL : OUT std_logic; EMPTY : OUT std_logic); end system_axi_dma_0_wrapper_fifo_generator_v9_3_1_exdes; architecture xilinx of system_axi_dma_0_wrapper_fifo_generator_v9_3_1_exdes is signal clk_i : std_logic; component system_axi_dma_0_wrapper_fifo_generator_v9_3_1 is PORT ( CLK : IN std_logic; DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0); WR_ACK : OUT std_logic; VALID : OUT std_logic; ALMOST_EMPTY : OUT std_logic; SRST : IN std_logic; WR_EN : IN std_logic; RD_EN : IN std_logic; DIN : IN std_logic_vector(39-1 DOWNTO 0); DOUT : OUT std_logic_vector(39-1 DOWNTO 0); FULL : OUT std_logic; EMPTY : OUT std_logic); end component; begin clk_buf: bufg PORT map( i => CLK, o => clk_i ); exdes_inst : system_axi_dma_0_wrapper_fifo_generator_v9_3_1 PORT MAP ( CLK => clk_i, DATA_COUNT => data_count, WR_ACK => wr_ack, VALID => valid, ALMOST_EMPTY => almost_empty, SRST => srst, WR_EN => wr_en, RD_EN => rd_en, DIN => din, DOUT => dout, FULL => full, EMPTY => empty); end xilinx;

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library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_decoder_GNBT6YIKS3 is generic ( decode : string := "011"; pipeline : natural := 1; width : natural := 3); port( aclr : in std_logic; clock : in std_logic; data : in std_logic_vector((width)-1 downto 0); dec : out std_logic; ena : in std_logic; sclr : in std_logic); end entity; architecture rtl of alt_dspbuilder_decoder_GNBT6YIKS3 is Begin -- DSP Builder Block - Simulink Block "Decoder" Decoderi : alt_dspbuilder_sdecoderaltr Generic map ( width => 3, decode => "011", pipeline => 1) port map ( aclr => aclr, user_aclr => '0', sclr => sclr, clock => clock, data => data, dec => dec); end architecture;

-------------------------------------------------------------------------------- -- -- Distributed Memory Generator v6.3 Core - Top-level core wrapper -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -------------------------------------------------------------------------------- -- -- -- Description: -- This is the actual DMG core wrapper. -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; -------------------------------------------------------------------------------- -- Entity Declaration -------------------------------------------------------------------------------- entity ROM_GAUSS_COE_exdes is PORT ( A : IN STD_LOGIC_VECTOR(4-1-(4*0*boolean'pos(4>4)) downto 0) := (OTHERS => '0'); D : IN STD_LOGIC_VECTOR(135-1 downto 0) := (OTHERS => '0'); DPRA : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS => '0'); SPRA : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS => '0'); CLK : IN STD_LOGIC := '0'; WE : IN STD_LOGIC := '0'; I_CE : IN STD_LOGIC := '1'; QSPO_CE : IN STD_LOGIC := '1'; QDPO_CE : IN STD_LOGIC := '1'; QDPO_CLK : IN STD_LOGIC := '0'; QSPO_RST : IN STD_LOGIC := '0'; QDPO_RST : IN STD_LOGIC := '0'; QSPO_SRST : IN STD_LOGIC := '0'; QDPO_SRST : IN STD_LOGIC := '0'; SPO : OUT STD_LOGIC_VECTOR(135-1 downto 0); DPO : OUT STD_LOGIC_VECTOR(135-1 downto 0); QSPO : OUT STD_LOGIC_VECTOR(135-1 downto 0); QDPO : OUT STD_LOGIC_VECTOR(135-1 downto 0) ); end ROM_GAUSS_COE_exdes; architecture xilinx of ROM_GAUSS_COE_exdes is SIGNAL CLK_i : std_logic; component ROM_GAUSS_COE is PORT ( CLK : IN STD_LOGIC; WE : IN STD_LOGIC; SPO : OUT STD_LOGIC_VECTOR(135-1 downto 0); A : IN STD_LOGIC_VECTOR(4-1-(4*0*boolean'pos(4>4)) downto 0) := (OTHERS => '0'); D : IN STD_LOGIC_VECTOR(135-1 downto 0) := (OTHERS => '0') ); end component; begin dmg0 : ROM_GAUSS_COE port map ( CLK => CLK_i, WE => WE, SPO => SPO, A => A, D => D ); clk_buf: bufg PORT map( i => CLK, o => CLK_i ); end xilinx;

--Part of Mano Basic Computer --Behzad Mokhtari; [email protected] --Sahand University of Technology; sut.ac.ir --Licensed under GPLv3 --ALU Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all; Library manoBasic; use manoBasic.defines.all, manoBasic.devices.all; entity tb_ALU is end tb_ALU; architecture tb of tb_ALU is signal cmd: instALU; signal Ei: std_logic := '0'; signal Eo: std_logic; signal IP: std_logic_vector(15 downto 0); signal AC: std_logic_vector(15 downto 0); signal DR: std_logic_vector(15 downto 0); signal Q,qq: std_logic_vector(15 downto 0); signal Check: std_logic := '1'; begin A0: ALU generic map(width =>16) port map( cmd => cmd, Ei => Ei, Eo => Eo, IP => IP, AC => AC, DR => DR, Q => Q ); test: process begin IP <= "0000111100001111"; cmd <= aluINPR; wait for 1 ns; if(IP = Q) then Check <= '1'; else Check <= '0'; end if; AC <= IP; DR <= not IP; cmd <= aluAND; wait for 1 ns; if(Q = (AC and DR)) then Check <= '1'; else Check <= '0'; end if; wait for 1 ns; cmd <= aluADD; wait for 1 ns; if(to_integer(unsigned(Q)) = (to_integer(unsigned(AC)) + to_integer(unsigned(DR)))) then Check <= '1'; else Check <= '0'; end if; wait for 1 ns; cmd <= aluDR; wait for 1 ns; if(Q = DR) then Check <= '1'; else Check <= '0'; end if; wait for 1 ns; cmd <= aluCOM; wait for 1 ns; if(Q = not AC) then Check <= '1'; else Check <= '0'; end if; wait for 1 ns; cmd <= aluSHR; qq <= '0' & AC(15 downto 1); wait for 1 ns; if(Q = qq) then Check <= '1'; else Check <= '0'; end if; wait for 1 ns; cmd <= aluSHL; qq <= AC(14 downto 0) & '0'; wait for 1 ns; if(Q = qq) then Check <= '1'; else Check <= '0'; end if; wait; end process test; end architecture tb;

library verilog; use verilog.vl_types.all; entity sum is port( a : in vl_logic_vector(9 downto 0); b : in vl_logic_vector(9 downto 0); y : out vl_logic_vector(9 downto 0) ); end sum;

-- $Id: tb_w11a_n2.vhd 314 2010-07-09 17:38:41Z mueller $ -- -- Copyright 2010- by Walter F.J. Mueller <[email protected]> -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free -- Software Foundation, either version 2, or at your option any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY -- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for complete details. -- ------------------------------------------------------------------------------ -- Module Name: tb_w11a_n2 -- Description: Configuration for tb_w11a_n2 for tb_nexys2_fusp -- -- Dependencies: sys_w11a_n2 -- -- To test: sys_w11a_n2 -- -- Verified (with (#1) ../../tb/tb_rritba_pdp11core_stim.dat -- (#2) ../../tb/tb_pdp11_core_stim.dat): -- Date Rev Code ghdl ise Target Comment -- 2010-05-28 295 - -.-- - - -:-- -- -- Revision History: -- Date Rev Version Comment -- 2010-05-26 295 1.0 Initial version (cloned from _s3) ------------------------------------------------------------------------------ configuration tb_w11a_n2 of tb_nexys2_fusp is for sim for all : nexys2_fusp_aif use entity work.sys_w11a_n2; end for; end for; end tb_w11a_n2;

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2013, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: grethc -- File: grethc.vhd -- Author: Marko Isomaki -- Description: Ethernet Media Access Controller with Ethernet Debug -- Communication Link ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library grlib; use grlib.stdlib.all; library eth; use eth.grethpkg.all; entity grethc is generic( ifg_gap : integer := 24; attempt_limit : integer := 16; backoff_limit : integer := 10; mdcscaler : integer range 0 to 255 := 25; enable_mdio : integer range 0 to 1 := 0; fifosize : integer range 4 to 512 := 8; nsync : integer range 1 to 2 := 2; edcl : integer range 0 to 3 := 0; edclbufsz : integer range 1 to 64 := 1; macaddrh : integer := 16#00005E#; macaddrl : integer := 16#000000#; ipaddrh : integer := 16#c0a8#; ipaddrl : integer := 16#0035#; phyrstadr : integer range 0 to 32 := 0; rmii : integer range 0 to 1 := 0; oepol : integer range 0 to 1 := 0; scanen : integer range 0 to 1 := 0; mdint_pol : integer range 0 to 1 := 0; enable_mdint : integer range 0 to 1 := 0; multicast : integer range 0 to 1 := 0; edclsepahbg : integer range 0 to 1 := 0; ramdebug : integer range 0 to 2 := 0; mdiohold : integer := 1; maxsize : integer := 1500); port( rst : in std_ulogic; clk : in std_ulogic; --ahb mst in hgrant : in std_ulogic; hready : in std_ulogic; hresp : in std_logic_vector(1 downto 0); hrdata : in std_logic_vector(31 downto 0); --ahb mst out hbusreq : out std_ulogic; hlock : out std_ulogic; htrans : out std_logic_vector(1 downto 0); haddr : out std_logic_vector(31 downto 0); hwrite : out std_ulogic; hsize : out std_logic_vector(2 downto 0); hburst : out std_logic_vector(2 downto 0); hprot : out std_logic_vector(3 downto 0); hwdata : out std_logic_vector(31 downto 0); --edcl ahb mst in ehgrant : in std_ulogic; ehready : in std_ulogic; ehresp : in std_logic_vector(1 downto 0); ehrdata : in std_logic_vector(31 downto 0); --edcl ahb mst out ehbusreq : out std_ulogic; ehlock : out std_ulogic; ehtrans : out std_logic_vector(1 downto 0); ehaddr : out std_logic_vector(31 downto 0); ehwrite : out std_ulogic; ehsize : out std_logic_vector(2 downto 0); ehburst : out std_logic_vector(2 downto 0); ehprot : out std_logic_vector(3 downto 0); ehwdata : out std_logic_vector(31 downto 0); --apb slv in psel : in std_ulogic; penable : in std_ulogic; paddr : in std_logic_vector(31 downto 0); pwrite : in std_ulogic; pwdata : in std_logic_vector(31 downto 0); --apb slv out prdata : out std_logic_vector(31 downto 0); --irq irq : out std_logic; --rx ahb fifo rxrenable : out std_ulogic; rxraddress : out std_logic_vector(10 downto 0); rxwrite : out std_ulogic; rxwdata : out std_logic_vector(31 downto 0); rxwaddress : out std_logic_vector(10 downto 0); rxrdata : in std_logic_vector(31 downto 0); --tx ahb fifo txrenable : out std_ulogic; txraddress : out std_logic_vector(10 downto 0); txwrite : out std_ulogic; txwdata : out std_logic_vector(31 downto 0); txwaddress : out std_logic_vector(10 downto 0); txrdata : in std_logic_vector(31 downto 0); --edcl buf erenable : out std_ulogic; eraddress : out std_logic_vector(15 downto 0); ewritem : out std_ulogic; ewritel : out std_ulogic; ewaddressm : out std_logic_vector(15 downto 0); ewaddressl : out std_logic_vector(15 downto 0); ewdata : out std_logic_vector(31 downto 0); erdata : in std_logic_vector(31 downto 0); --ethernet input signals rmii_clk : in std_ulogic; tx_clk : in std_ulogic; rx_clk : in std_ulogic; rxd : in std_logic_vector(3 downto 0); rx_dv : in std_ulogic; rx_er : in std_ulogic; rx_col : in std_ulogic; rx_crs : in std_ulogic; mdio_i : in std_ulogic; phyrstaddr : in std_logic_vector(4 downto 0); mdint : in std_ulogic; --ethernet output signals reset : out std_ulogic; txd : out std_logic_vector(3 downto 0); tx_en : out std_ulogic; tx_er : out std_ulogic; mdc : out std_ulogic; mdio_o : out std_ulogic; mdio_oe : out std_ulogic; --scantest testrst : in std_ulogic; testen : in std_ulogic; testoen : in std_ulogic; edcladdr : in std_logic_vector(3 downto 0) := "0000"; edclsepahb : in std_ulogic; edcldisable : in std_ulogic; speed : out std_ulogic ); attribute sync_set_reset of rst : signal is "true"; end entity; architecture rtl of grethc is procedure sel_op_mode( capbil : in std_logic_vector(4 downto 0); speed : out std_ulogic; duplex : out std_ulogic) is variable vspeed : std_ulogic; variable vduplex : std_ulogic; begin vspeed := '0'; vduplex := '0'; vspeed := orv(capbil(4 downto 2)); vduplex := (vspeed and capbil(3)) or ((not vspeed) and capbil(1)); speed := vspeed; duplex := vduplex; end procedure; --host constants constant fabits : integer := log2(fifosize); constant burstlength : integer := setburstlength(fifosize); constant burstbits : integer := log2(burstlength); constant ctrlopcode : std_logic_vector(15 downto 0) := X"8808"; constant broadcast : std_logic_vector(47 downto 0) := X"FFFFFFFFFFFF"; -- constant maxsizetx : integer := 1514; constant index : integer := log2(edclbufsz); constant receiveOK : std_logic_vector(3 downto 0) := "0000"; constant frameCheckError : std_logic_vector(3 downto 0) := "0100"; constant alignmentError : std_logic_vector(3 downto 0) := "0001"; constant frameTooLong : std_logic_vector(3 downto 0) := "0010"; constant overrun : std_logic_vector(3 downto 0) := "1000"; constant minpload : std_logic_vector(10 downto 0) := conv_std_logic_vector(60, 11); --mdio constants constant divisor : std_logic_vector(7 downto 0) := conv_std_logic_vector(mdcscaler, 8); --receiver constants constant maxsizerx : unsigned(15 downto 0) := to_unsigned(maxsize + 18 - 4, 16); --tranceiver constants constant maxsizetx : unsigned(15 downto 0) := to_unsigned(maxsize + 18 - 4, 16); --edcl constants type szvct is array (0 to 6) of integer; constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256); constant blbits : szvct := (6, 7, 7, 8, 8, 8, 8); constant winsz : szvct := (4, 4, 8, 8, 16, 32, 64); constant macaddrt : std_logic_vector(47 downto 0) := conv_std_logic_vector(macaddrh, 24) & conv_std_logic_vector(macaddrl, 24); constant bpbits : integer := blbits(log2(edclbufsz)); constant wsz : integer := winsz(log2(edclbufsz)); constant bselbits : integer := log2(wsz); constant eabits: integer := log2(edclbufsz) + 8; constant ebufmax : std_logic_vector(bpbits-1 downto 0) := (others => '1'); constant bufsize : std_logic_vector(2 downto 0) := conv_std_logic_vector(log2(edclbufsz), 3); constant ebufsize : integer := ebuf(log2(edclbufsz)); constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize); constant txfabits : integer := log2(txfifosize); constant txfifosizev : std_logic_vector(txfabits downto 0) := conv_std_logic_vector(txfifosize, txfabits+1); constant rxburstlen : std_logic_vector(fabits downto 0) := conv_std_logic_vector(burstlength, fabits+1); constant txburstlen : std_logic_vector(txfabits downto 0) := conv_std_logic_vector(burstlength, txfabits+1); type edclrstate_type is (idle, wrda, wrdsa, wrsa, wrtype, ip, ipdata, oplength, arp, iplength, ipcrc, arpop, udp, spill); type duplexstate_type is (start, waitop, nextop, selmode, done); --host types type txd_state_type is (idle, read_desc, check_desc, req, fill_fifo, check_result, write_result, readhdr, start, wrbus1, etdone, getlen, ahberror, fill_fifo2, wrbus2); type rxd_state_type is (idle, read_desc, check_desc, read_req, read_fifo, discard, write_status, write_status2); --mdio types type mdio_state_type is (idle, preamble, startst, op, op2, phyadr, regadr, ta, ta2, ta3, data, dataend); type ctrl_reg_type is record txen : std_ulogic; rxen : std_ulogic; tx_irqen : std_ulogic; rx_irqen : std_ulogic; full_duplex : std_ulogic; prom : std_ulogic; reset : std_ulogic; speed : std_ulogic; pstatirqen : std_ulogic; mcasten : std_ulogic; ramdebugen : std_ulogic; edcldis : std_ulogic; end record; type status_reg_type is record tx_int : std_ulogic; rx_int : std_ulogic; rx_err : std_ulogic; tx_err : std_ulogic; txahberr : std_ulogic; rxahberr : std_ulogic; toosmall : std_ulogic; invaddr : std_ulogic; phystat : std_ulogic; end record; type mdio_ctrl_reg_type is record phyadr : std_logic_vector(4 downto 0); regadr : std_logic_vector(4 downto 0); write : std_ulogic; read : std_ulogic; data : std_logic_vector(15 downto 0); busy : std_ulogic; linkfail : std_ulogic; end record; subtype mac_addr_reg_type is std_logic_vector(47 downto 0); type fifo_access_in_type is record renable : std_ulogic; raddress : std_logic_vector(fabits-1 downto 0); write : std_ulogic; waddress : std_logic_vector(fabits-1 downto 0); datain : std_logic_vector(31 downto 0); end record; type fifo_access_out_type is record data : std_logic_vector(31 downto 0); end record; type tx_fifo_access_in_type is record renable : std_ulogic; raddress : std_logic_vector(txfabits-1 downto 0); write : std_ulogic; waddress : std_logic_vector(txfabits-1 downto 0); datain : std_logic_vector(31 downto 0); end record; type tx_fifo_access_out_type is record data : std_logic_vector(31 downto 0); end record; type edcl_ram_in_type is record renable : std_ulogic; raddress : std_logic_vector(eabits-1 downto 0); writem : std_ulogic; writel : std_ulogic; waddressm : std_logic_vector(eabits-1 downto 0); waddressl : std_logic_vector(eabits-1 downto 0); datain : std_logic_vector(31 downto 0); end record; type edcl_ram_out_type is record data : std_logic_vector(31 downto 0); end record; type reg_type is record --user registers ctrl : ctrl_reg_type; status : status_reg_type; mdio_ctrl : mdio_ctrl_reg_type; mac_addr : mac_addr_reg_type; hash : std_logic_vector(63 downto 0); txdesc : std_logic_vector(31 downto 10); rxdesc : std_logic_vector(31 downto 10); edclip : std_logic_vector(31 downto 0); --master tx interface txdsel : std_logic_vector(9 downto 3); tmsto : eth_tx_ahb_in_type; tmsto2 : eth_tx_ahb_in_type; txdstate : txd_state_type; txwrap : std_ulogic; txden : std_ulogic; txirq : std_ulogic; txaddr : std_logic_vector(31 downto 2); txlength : std_logic_vector(10 downto 0); txburstcnt : std_logic_vector(burstbits downto 0); tfwpnt : std_logic_vector(txfabits-1 downto 0); tfrpnt : std_logic_vector(txfabits-1 downto 0); tfcnt : std_logic_vector(txfabits downto 0); txcnt : std_logic_vector(10 downto 0); txstart : std_ulogic; txirqgen : std_ulogic; txstatus : std_logic_vector(1 downto 0); txvalid : std_ulogic; txdata : std_logic_vector(31 downto 0); writeok : std_ulogic; txread : std_logic_vector(nsync-1 downto 0); txrestart : std_logic_vector(nsync downto 0); txdone : std_logic_vector(nsync downto 0); txstart_sync : std_ulogic; txreadack : std_ulogic; txdataav : std_ulogic; txburstav : std_ulogic; --master rx interface rxrenable : std_ulogic; rxdsel : std_logic_vector(9 downto 3); rmsto : eth_rx_ahb_in_type; rxdstate : rxd_state_type; rxstatus : std_logic_vector(4 downto 0); rxaddr : std_logic_vector(31 downto 2); rxlength : std_logic_vector(10 downto 0); rxbytecount : std_logic_vector(10 downto 0); rxwrap : std_ulogic; rxirq : std_ulogic; rfwpnt : std_logic_vector(fabits-1 downto 0); rfrpnt : std_logic_vector(fabits-1 downto 0); rfcnt : std_logic_vector(fabits downto 0); rxcnt : std_logic_vector(10 downto 0); rxdoneold : std_ulogic; rxdoneack : std_ulogic; rxdone : std_logic_vector(nsync-1 downto 0); rxstart : std_logic_vector(nsync downto 0); rxwrite : std_logic_vector(nsync-1 downto 0); rxwriteack : std_ulogic; rxburstcnt : std_logic_vector(burstbits downto 0); addrok : std_ulogic; addrdone : std_ulogic; ctrlpkt : std_ulogic; check : std_ulogic; checkdata : std_logic_vector(31 downto 0); usesizefield : std_ulogic; rxden : std_ulogic; gotframe : std_ulogic; bcast : std_ulogic; msbgood : std_ulogic; rxburstav : std_ulogic; hashlookup : std_ulogic; mcast : std_ulogic; mcastacc : std_ulogic; --mdio mdccnt : std_logic_vector(7 downto 0); mdioclk : std_ulogic; mdioclkold : std_logic_vector(mdiohold-1 downto 0); mdio_state : mdio_state_type; mdioo : std_ulogic; mdioi : std_ulogic; mdioen : std_ulogic; cnt : std_logic_vector(4 downto 0); duplexstate : duplexstate_type; disableduplex : std_ulogic; init_busy : std_ulogic; ext : std_ulogic; extcap : std_ulogic; regaddr : std_logic_vector(4 downto 0); phywr : std_ulogic; rstphy : std_ulogic; capbil : std_logic_vector(4 downto 0); rstaneg : std_ulogic; mdint_sync : std_logic_vector(2 downto 0); --edcl erenable : std_ulogic; edclrstate : edclrstate_type; edclactive : std_ulogic; nak : std_ulogic; ewr : std_ulogic; write : std_logic_vector(wsz-1 downto 0); seq : std_logic_vector(13 downto 0); abufs : std_logic_vector(bselbits downto 0); tpnt : std_logic_vector(bselbits-1 downto 0); rpnt : std_logic_vector(bselbits-1 downto 0); tcnt : std_logic_vector(bpbits-1 downto 0); rcntm : std_logic_vector(bpbits-1 downto 0); rcntl : std_logic_vector(bpbits-1 downto 0); ipcrc : std_logic_vector(17 downto 0); applength : std_logic_vector(15 downto 0); oplen : std_logic_vector(9 downto 0); udpsrc : std_logic_vector(15 downto 0); ecnt : std_logic_vector(3 downto 0); tarp : std_ulogic; tnak : std_ulogic; tedcl : std_ulogic; edclbcast : std_ulogic; etxidle : std_ulogic; erxidle : std_ulogic; emacaddr : std_logic_vector(47 downto 0); edclsepahb : std_ulogic; end record; --host signals signal arst : std_ulogic; signal irst : std_ulogic; signal vcc : std_ulogic; signal tmsto : eth_tx_ahb_in_type; signal tmsti : eth_tx_ahb_out_type; signal tmsto2 : eth_tx_ahb_in_type; signal tmsti2 : eth_tx_ahb_out_type; signal rmsto : eth_rx_ahb_in_type; signal rmsti : eth_rx_ahb_out_type; signal ahbmi : ahbc_mst_in_type; signal ahbmo : ahbc_mst_out_type; signal ahbmi2 : ahbc_mst_in_type; signal ahbmo2 : ahbc_mst_out_type; signal txi : host_tx_type; signal txo : tx_host_type; signal rxi : host_rx_type; signal rxo : rx_host_type; signal r, rin : reg_type; attribute sync_set_reset of irst : signal is "true"; attribute async_set_reset of arst : signal is "true"; begin --reset generators for transmitter and receiver vcc <= '1'; arst <= testrst when (scanen = 1) and (testen = '1') else rst and not r.ctrl.reset; irst <= rst and not r.ctrl.reset; comb : process(rst, irst, r, rmsti, tmsti, txo, rxo, psel, paddr, penable, erdata, pwrite, pwdata, rxrdata, txrdata, mdio_i, phyrstaddr, testen, testrst, edcladdr, mdint, tmsti2, edcldisable, edclsepahb) is variable v : reg_type; variable vpirq : std_ulogic; variable vprdata : std_logic_vector(31 downto 0); variable txvalid : std_ulogic; variable vtxfi : tx_fifo_access_in_type; variable vrxfi : fifo_access_in_type; variable lengthav : std_ulogic; variable txdone : std_ulogic; variable txread : std_ulogic; variable txrestart : std_ulogic; variable rxstart : std_ulogic; variable rxdone : std_ulogic; variable vrxwrite : std_ulogic; variable ovrunstop : std_ulogic; variable edcldbgread : std_ulogic; --mdio variable mdioindex : integer range 0 to 31; variable mclk : std_ulogic; --rising mdio clk edge variable nmclk : std_ulogic; --falling mdio clk edge variable mclkvec : std_logic_vector(mdiohold downto 0); --edcl variable veri : edcl_ram_in_type; variable swap : std_ulogic; variable setmz : std_ulogic; variable ipcrctmp : std_logic_vector(15 downto 0); variable ipcrctmp2 : std_logic_vector(17 downto 0); variable vrxenable : std_ulogic; variable crctmp : std_ulogic; variable vecnt : integer; begin v := r; vprdata := (others => '0'); vpirq := '0'; v.check := '0'; lengthav := r.rxdoneold;-- or r.usesizefield; ovrunstop := '0'; vrxfi.raddress := v.rfrpnt; if edcl /= 0 then veri.renable := r.erenable; veri.datain := rxo.dataout; veri.writem := '0'; veri.writel := '0'; veri.waddressm := r.rpnt & r.rcntm; veri.waddressl := r.rpnt & r.rcntl; end if; vtxfi.renable := '0'; vtxfi.datain := tmsti.data; vtxfi.raddress := r.tfrpnt; vtxfi.write := '0'; vtxfi.waddress := r.tfwpnt; vrxfi.datain := rxo.dataout; vrxfi.write := '0'; vrxfi.waddress := r.rfwpnt; vrxfi.renable := r.rxrenable; vrxenable := r.ctrl.rxen; --synchronization v.txdone(0) := txo.done; v.txread(0) := txo.read; v.txrestart(0) := txo.restart; v.rxstart(0) := rxo.start; v.rxdone(0) := rxo.done; v.rxwrite(0) := rxo.write; if nsync = 2 then v.txdone(1) := r.txdone(0); v.txread(1) := r.txread(0); v.txrestart(1) := r.txrestart(0); v.rxstart(1) := r.rxstart(0); v.rxdone(1) := r.rxdone(0); v.rxwrite(1) := r.rxwrite(0); end if; if enable_mdint = 1 then v.mdint_sync(0) := mdint; v.mdint_sync(1) := r.mdint_sync(0); v.mdint_sync(2) := r.mdint_sync(1); end if; txdone := r.txdone(nsync) xor r.txdone(nsync-1); txread := r.txreadack xor r.txread(nsync-1); txrestart := r.txrestart(nsync) xor r.txrestart(nsync-1); rxstart := r.rxstart(nsync) xor r.rxstart(nsync-1); rxdone := r.rxdoneack xor r.rxdone(nsync-1); vrxwrite := r.rxwriteack xor r.rxwrite(nsync-1); if txdone = '1' then v.txstatus := txo.status; end if; ------------------------------------------------------------------------------- -- HOST INTERFACE ------------------------------------------------------------- ------------------------------------------------------------------------------- --SLAVE INTERFACE if ramdebug = 2 then edcldbgread := '0'; end if; --write if (psel and penable and pwrite) = '1' then if (ramdebug = 0) or (paddr(17 downto 16) = "00") then case paddr(5 downto 2) is when "0000" => --ctrl reg if ramdebug /= 0 then v.ctrl.ramdebugen := pwdata(13); end if; if edcl /= 0 then v.ctrl.edcldis := pwdata(14); v.disableduplex := pwdata(12); end if; if multicast = 1 then v.ctrl.mcasten := pwdata(11); end if; if enable_mdint = 1 then v.ctrl.pstatirqen := pwdata(10); end if; if rmii = 1 then v.ctrl.speed := pwdata(7); end if; v.ctrl.reset := pwdata(6); v.ctrl.prom := pwdata(5); v.ctrl.full_duplex := pwdata(4); v.ctrl.rx_irqen := pwdata(3); v.ctrl.tx_irqen := pwdata(2); v.ctrl.rxen := pwdata(1); v.ctrl.txen := pwdata(0); when "0001" => --status/int source reg if enable_mdint = 1 then if pwdata(8) = '1' then v.status.phystat := '0'; end if; end if; if pwdata(7) = '1' then v.status.invaddr := '0'; end if; if pwdata(6) = '1' then v.status.toosmall := '0'; end if; if pwdata(5) = '1' then v.status.txahberr := '0'; end if; if pwdata(4) = '1' then v.status.rxahberr := '0'; end if; if pwdata(3) = '1' then v.status.tx_int := '0'; end if; if pwdata(2) = '1' then v.status.rx_int := '0'; end if; if pwdata(1) = '1' then v.status.tx_err := '0'; end if; if pwdata(0) = '1' then v.status.rx_err := '0'; end if; when "0010" => --mac addr msb v.mac_addr(47 downto 32) := pwdata(15 downto 0); when "0011" => --mac addr lsb v.mac_addr(31 downto 0) := pwdata(31 downto 0); when "0100" => --mdio ctrl/status if enable_mdio = 1 then if r.mdio_ctrl.busy = '0' then v.mdio_ctrl.data := pwdata(31 downto 16); v.mdio_ctrl.phyadr := pwdata(15 downto 11); v.mdio_ctrl.regadr := pwdata(10 downto 6); v.mdio_ctrl.read := pwdata(1); v.mdio_ctrl.write := pwdata(0); v.mdio_ctrl.busy := pwdata(1) or pwdata(0); end if; end if; when "0101" => --tx descriptor v.txdesc := pwdata(31 downto 10); v.txdsel := pwdata(9 downto 3); when "0110" => --rx descriptor v.rxdesc := pwdata(31 downto 10); v.rxdsel := pwdata(9 downto 3); when "0111" => --edcl ip if (edcl /= 0) then v.edclip := pwdata; end if; when "1000" => --hash msb if multicast = 1 then v.hash(63 downto 32) := pwdata; end if; when "1001" => --hash lsb if multicast = 1 then v.hash(31 downto 0) := pwdata; end if; when "1010" => if edcl /= 0 then v.emacaddr(47 downto 32) := pwdata(15 downto 0); end if; when "1011" => if edcl /= 0 then v.emacaddr(31 downto 0) := pwdata; end if; when others => null; end case; elsif ((ramdebug /= 0) and (paddr(17 downto 16) = "01")) then if r.ctrl.ramdebugen = '1' then vtxfi.write := '1'; vtxfi.waddress := paddr(txfabits+1 downto 2); vtxfi.datain := pwdata; end if; elsif ((ramdebug /= 0) and (paddr(17 downto 16) = "10")) then if r.ctrl.ramdebugen = '1' then vrxfi.write := '1'; vrxfi.waddress := paddr(fabits+1 downto 2); vrxfi.datain := pwdata; end if; elsif ((ramdebug = 2) and (edcl /= 0) and (paddr(17 downto 16) = "11")) then if r.ctrl.ramdebugen = '1' then veri.datain := pwdata; veri.waddressm := paddr(eabits+1 downto 2); veri.waddressl := paddr(eabits+1 downto 2); veri.writem := '1'; veri.writel := '1'; end if; end if; end if; --read if (ramdebug = 0) or (paddr(17 downto 16) = "00") then case paddr(5 downto 2) is when "0000" => --ctrl reg if ramdebug /= 0 then vprdata(13) := r.ctrl.ramdebugen; end if; if (edcl /= 0) then vprdata(31) := '1'; vprdata(30 downto 28) := bufsize; vprdata(14) := r.ctrl.edcldis; vprdata(12) := r.disableduplex; end if; if enable_mdint = 1 then vprdata(26) := '1'; vprdata(10) := r.ctrl.pstatirqen; end if; if multicast = 1 then vprdata(25) := '1'; vprdata(11) := r.ctrl.mcasten; end if; if rmii = 1 then vprdata(7) := r.ctrl.speed; end if; vprdata(6) := r.ctrl.reset; vprdata(5) := r.ctrl.prom; vprdata(4) := r.ctrl.full_duplex; vprdata(3) := r.ctrl.rx_irqen; vprdata(2) := r.ctrl.tx_irqen; vprdata(1) := r.ctrl.rxen; vprdata(0) := r.ctrl.txen; when "0001" => --status/int source reg vprdata(9) := not (r.etxidle or r.erxidle); if enable_mdint = 1 then vprdata(8) := r.status.phystat; end if; vprdata(7) := r.status.invaddr; vprdata(6) := r.status.toosmall; vprdata(5) := r.status.txahberr; vprdata(4) := r.status.rxahberr; vprdata(3) := r.status.tx_int; vprdata(2) := r.status.rx_int; vprdata(1) := r.status.tx_err; vprdata(0) := r.status.rx_err; when "0010" => --mac addr msb/mdio address vprdata(15 downto 0) := r.mac_addr(47 downto 32); when "0011" => --mac addr lsb vprdata := r.mac_addr(31 downto 0); when "0100" => --mdio ctrl/status vprdata(31 downto 16) := r.mdio_ctrl.data; vprdata(15 downto 11) := r.mdio_ctrl.phyadr; vprdata(10 downto 6) := r.mdio_ctrl.regadr; vprdata(3) := r.mdio_ctrl.busy; vprdata(2) := r.mdio_ctrl.linkfail; vprdata(1) := r.mdio_ctrl.read; vprdata(0) := r.mdio_ctrl.write; when "0101" => --tx descriptor vprdata(31 downto 10) := r.txdesc; vprdata(9 downto 3) := r.txdsel; when "0110" => --rx descriptor vprdata(31 downto 10) := r.rxdesc; vprdata(9 downto 3) := r.rxdsel; when "0111" => --edcl ip if (edcl /= 0) then vprdata := r.edclip; end if; when "1000" => if multicast = 1 then vprdata := r.hash(63 downto 32); end if; when "1001" => if multicast = 1 then vprdata := r.hash(31 downto 0); end if; when "1010" => if edcl /= 0 then vprdata(15 downto 0) := r.emacaddr(47 downto 32); end if; when "1011" => if edcl /= 0 then vprdata := r.emacaddr(31 downto 0); end if; when others => null; end case; elsif ((ramdebug /= 0) and (paddr(17 downto 16) = "01")) then if r.ctrl.ramdebugen = '1' then vtxfi.renable := '1'; vtxfi.raddress := paddr(txfabits+1 downto 2); vprdata := txrdata; end if; elsif ((ramdebug /= 0) and (paddr(17 downto 16) = "10")) then if r.ctrl.ramdebugen = '1' then vrxfi.renable := '1'; vrxfi.raddress := paddr(fabits+1 downto 2); vprdata := rxrdata; end if; elsif ((ramdebug = 2) and (edcl /= 0) and (paddr(17 downto 16) = "11")) then if r.ctrl.ramdebugen = '1' then edcldbgread := '1'; veri.renable := '1'; veri.raddress := paddr(eabits+1 downto 2); vprdata := erdata; end if; end if; --PHY STATUS DETECTION if enable_mdint = 1 then if mdint_pol = 0 then if (r.mdint_sync(2) and not r.mdint_sync(1)) = '1' then v.status.phystat := '1'; if r.ctrl.pstatirqen = '1' then vpirq := '1'; end if; end if; else if (r.mdint_sync(1) and not r.mdint_sync(2)) = '1' then v.status.phystat := '1'; if r.ctrl.pstatirqen = '1' then vpirq := '1'; end if; end if; end if; end if; --MASTER INTERFACE v.txburstav := '0'; if (txfifosizev - r.tfcnt) >= txburstlen then v.txburstav := '1'; end if; if (conv_integer(r.abufs) /= 0) then v.etxidle := '0'; else v.etxidle := '1'; end if; --tx dma fsm case r.txdstate is when idle => v.txcnt := (others => '0'); v.txburstcnt := (others => '0'); if (edcl /= 0) then v.tedcl := '0'; v.erenable := '0'; end if; if (edcl /= 0) and (conv_integer(r.abufs) /= 0) and (r.ctrl.edcldis = '0') then v.erenable := '1'; v.etxidle := '0'; if r.erenable = '1' then v.txdstate := getlen; end if; v.tcnt := conv_std_logic_vector(10, bpbits); elsif r.ctrl.txen = '1' then v.txdstate := read_desc; v.tmsto.write := '0'; v.tmsto.addr := r.txdesc & r.txdsel & "000"; v.tmsto.req := '1'; end if; if r.txirqgen = '1' then vpirq := '1'; v.txirqgen := '0'; end if; if txrestart = '1' then v.txrestart(nsync) := r.txrestart(nsync-1); v.tfcnt := (others => '0'); v.tfrpnt := (others => '0'); v.tfwpnt := (others => '0'); end if; when read_desc => v.tmsto.write := '0'; v.txstatus := (others => '0'); v.tfwpnt := (others => '0'); v.tfrpnt := (others => '0'); v.tfcnt := (others => '0'); if tmsti.grant = '1' then v.txburstcnt := r.txburstcnt + 1; v.tmsto.addr := r.tmsto.addr + 4; if r.txburstcnt(0) = '1' then v.tmsto.req := '0'; end if; end if; if tmsti.ready = '1' then v.txcnt := r.txcnt + 1; case r.txcnt(1 downto 0) is when "00" => v.txlength := tmsti.data(10 downto 0); v.txden := tmsti.data(11); v.txwrap := tmsti.data(12); v.txirq := tmsti.data(13); v.ctrl.txen := tmsti.data(11); when "01" => v.txaddr := tmsti.data(31 downto 2); v.txdstate := check_desc; when others => null; end case; end if; when check_desc => v.txstart := '0'; v.txburstcnt := (others => '0'); if r.txden = '1' then if (unsigned(r.txlength) > unsigned(maxsizetx)) or (conv_integer(r.txlength) = 0) then v.txdstate := write_result; v.tmsto.req := '1'; v.tmsto.write := '1'; v.tmsto.addr := r.txdesc & r.txdsel & "000"; v.tmsto.data := (others => '0'); else v.txdstate := req; v.tmsto.addr := r.txaddr & "00"; v.txcnt(10 downto 0) := r.txlength; end if; else v.txdstate := idle; end if; when req => if txrestart = '1' then v.txdstate := idle; v.txstart := '0'; if (edcl /= 0) and (r.tedcl = '1') then v.txdstate := idle; end if; elsif txdone = '1' then v.txdstate := check_result; v.tfcnt := (others => '0'); v.tfrpnt := (others => '0'); v.tfwpnt := (others => '0'); if (edcl /= 0) and (r.tedcl = '1') then v.txdstate := etdone; end if; elsif conv_integer(r.txcnt) = 0 then v.txdstate := check_result; if (edcl /= 0) and (r.tedcl = '1') then v.txdstate := etdone; v.txstart_sync := not r.txstart_sync; end if; elsif (r.txburstav = '1') or (r.tedcl = '1') then if (edclsepahbg = 0) or (edcl = 0) or (r.edclsepahb = '0') or (r.tedcl = '0') then v.tmsto.req := '1'; v.txdstate := fill_fifo; else v.tmsto2.req := '1'; v.txdstate := fill_fifo2; end if; end if; v.txburstcnt := (others => '0'); when fill_fifo => v.txburstav := '0'; if tmsti.grant = '1' then v.tmsto.addr := r.tmsto.addr + 4; if ((conv_integer(r.txcnt) <= 8) and (tmsti.ready = '1')) or ((conv_integer(r.txcnt) <= 4) and (tmsti.ready = '0')) then v.tmsto.req := '0'; end if; v.txburstcnt := r.txburstcnt + 1; if (conv_integer(r.txburstcnt) = burstlength-1) then v.tmsto.req := '0'; end if; end if; if (tmsti.ready = '1') or ((edcl /= 0) and (r.tedcl and tmsti.error) = '1') then v.tfwpnt := r.tfwpnt + 1; v.tfcnt := r.tfcnt + 1; vtxfi.write := '1'; if r.tmsto.req = '0' then v.txdstate := req; if (r.txstart = '0') and not ((edcl /= 0) and (r.tedcl = '1')) then v.txstart := '1'; v.txstart_sync := not r.txstart_sync; end if; end if; if conv_integer(r.txcnt) > 3 then v.txcnt := r.txcnt - 4; else v.txcnt := (others => '0'); end if; end if; when fill_fifo2 => if edclsepahbg = 1 then v.txburstav := '0'; vtxfi.datain := tmsti2.data; if tmsti2.grant = '1' then v.tmsto2.addr := r.tmsto2.addr + 4; if ((conv_integer(r.txcnt) <= 8) and (tmsti2.ready = '1')) or ((conv_integer(r.txcnt) <= 4) and (tmsti2.ready = '0')) then v.tmsto2.req := '0'; end if; v.txburstcnt := r.txburstcnt + 1; if (conv_integer(r.txburstcnt) = burstlength-1) then v.tmsto2.req := '0'; end if; end if; if (tmsti2.ready = '1') or ((edcl /= 0) and (r.tedcl and tmsti2.error) = '1') then v.tfwpnt := r.tfwpnt + 1; v.tfcnt := r.tfcnt + 1; vtxfi.write := '1'; if r.tmsto2.req = '0' then v.txdstate := req; if (r.txstart = '0') and not ((edcl /= 0) and (r.tedcl = '1')) then v.txstart := '1'; v.txstart_sync := not r.txstart_sync; end if; end if; if conv_integer(r.txcnt) > 3 then v.txcnt := r.txcnt - 4; else v.txcnt := (others => '0'); end if; end if; end if; when check_result => if txdone = '1' then v.txdstate := write_result; v.tmsto.req := '1'; v.txstart := '0'; v.tmsto.write := '1'; v.tmsto.addr := r.txdesc & r.txdsel & "000"; v.tmsto.data(31 downto 16) := (others => '0'); v.tmsto.data(15 downto 14) := v.txstatus; v.tmsto.data(13 downto 0) := (others => '0'); v.txdone(nsync) := r.txdone(nsync-1); elsif txrestart = '1' then v.txdstate := idle; v.txstart := '0'; end if; when write_result => if tmsti.grant = '1' then v.tmsto.req := '0'; v.tmsto.addr := r.tmsto.addr + 4; end if; if tmsti.ready = '1' then v.txdstate := idle; v.txirqgen := r.ctrl.tx_irqen and r.txirq; if r.txwrap = '0' then v.txdsel := r.txdsel + 1; else v.txdsel := (others => '0'); end if; if conv_integer(r.txstatus) = 0 then v.status.tx_int := '1'; else v.status.tx_err := '1'; end if; end if; when ahberror => v.tfcnt := (others => '0'); v.tfwpnt := (others => '0'); v.tfrpnt := (others => '0'); v.status.txahberr := '1'; v.ctrl.txen := '0'; if not ((edcl /= 0) and (r.tedcl = '1')) then if r.txstart = '1' then if txdone = '1' then v.txdstate := idle; v.txdone(nsync) := r.txdone(nsync-1); end if; else v.txdstate := idle; end if; else v.txdstate := idle; v.abufs := r.abufs - 1; v.tpnt := r.tpnt + 1; end if; when others => null; end case; --tx fifo read v.txdataav := '0'; if conv_integer(r.tfcnt) /= 0 then v.txdataav := '1'; end if; if txread = '1' then v.txreadack := not r.txreadack; if r.txdataav = '1' then if conv_integer(r.tfcnt) < 2 then v.txdataav := '0'; end if; v.txvalid := '1'; v.tfcnt := v.tfcnt - 1; v.tfrpnt := r.tfrpnt + 1; else v.txvalid := '0'; end if; v.txdata := txrdata; end if; v.rxburstav := '0'; if r.rfcnt >= rxburstlen then v.rxburstav := '1'; end if; if ramdebug = 0 then vtxfi.renable := v.txdataav; else vtxfi.renable := vtxfi.renable or v.txdataav; end if; --rx dma fsm case r.rxdstate is when idle => v.rmsto.req := '0'; v.rmsto.write := '0'; v.addrok := '0'; v.rxburstcnt := (others => '0'); v.addrdone := '0'; v.rxcnt := (others => '0'); v.rxdoneold := '0'; v.ctrlpkt := '0'; v.bcast := '0'; v.edclactive := '0'; v.msbgood := '0'; v.rxrenable := '0'; if multicast = 1 then v.mcast := '0'; v.mcastacc := '0'; end if; if r.ctrl.rxen = '1' then v.rxdstate := read_desc; v.rmsto.req := '1'; v.rmsto.addr := r.rxdesc & r.rxdsel & "000"; elsif rxstart = '1' then v.rxstart(nsync) := r.rxstart(nsync-1); v.rxdstate := discard; end if; when read_desc => v.rxstatus := (others => '0'); if rmsti.grant = '1' then v.rxburstcnt := r.rxburstcnt + 1; v.rmsto.addr := r.rmsto.addr + 4; if r.rxburstcnt(0) = '1' then v.rmsto.req := '0'; end if; end if; if rmsti.ready = '1' then v.rxcnt := r.rxcnt + 1; case r.rxcnt(1 downto 0) is when "00" => v.ctrl.rxen := rmsti.data(11); v.rxden := rmsti.data(11); v.rxwrap := rmsti.data(12); v.rxirq := rmsti.data(13); when "01" => v.rxaddr := rmsti.data(31 downto 2); v.rxdstate := check_desc; v.rxrenable := '1'; when others => null; end case; end if; if rmsti.error = '1' then v.rmsto.req := '0'; v.rxdstate := idle; v.status.rxahberr := '1'; v.ctrl.rxen := '0'; end if; when check_desc => v.rxcnt := (others => '0'); v.usesizefield := '0'; v.rmsto.write := '1'; if r.rxden = '1' then if rxstart = '1' then v.rxdstate := read_req; v.rxstart(nsync) := r.rxstart(nsync-1); end if; else v.rxdstate := idle; end if; v.rmsto.addr := r.rxaddr & "00"; when read_req => if r.edclactive = '1' then v.rxdstate := discard; elsif (r.rxdoneold and r.rxstatus(3)) = '1' then v.rxdstate := write_status; v.rfcnt := (others => '0'); v.rfwpnt := (others => '0'); v.rfrpnt := (others => '0'); v.writeok := '1'; v.rxbytecount := (others => '0'); v.rxlength := (others => '0'); elsif ((r.addrdone and not r.addrok) or r.ctrlpkt) = '1' then v.rxdstate := discard; v.status.invaddr := '1'; elsif ((r.rxdoneold = '1') and r.rxcnt >= r.rxlength) then if r.gotframe = '1' then v.rxdstate := write_status; else v.rxdstate := discard; v.status.toosmall := '1'; end if; elsif (r.rxburstav or r.rxdoneold) = '1' then v.rmsto.req := '1'; v.rxdstate := read_fifo; v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1; end if; v.rxburstcnt := (others => '0'); v.rmsto.data := rxrdata; when read_fifo => v.rxburstav := '0'; if rmsti.grant = '1' then v.rmsto.addr := r.rmsto.addr + 4; if (lengthav = '1') then if ((conv_integer(r.rxcnt) >= (conv_integer(r.rxlength) - 8)) and (rmsti.ready = '1')) or ((conv_integer(r.rxcnt) >= (conv_integer(r.rxlength) - 4)) and (rmsti.ready = '0')) then v.rmsto.req := '0'; end if; end if; v.rxburstcnt := r.rxburstcnt + 1; if (conv_integer(r.rxburstcnt) = burstlength-1) then v.rmsto.req := '0'; end if; end if; if rmsti.ready = '1' then v.rmsto.data := rxrdata; v.rxcnt := r.rxcnt + 4; if r.rmsto.req = '0' then v.rxdstate := read_req; else v.rfcnt := r.rfcnt - 1; v.rfrpnt := r.rfrpnt + 1; end if; v.check := '1'; v.checkdata := r.rmsto.data; end if; if rmsti.error = '1' then v.rmsto.req := '0'; v.rxdstate := discard; v.rxcnt := r.rxcnt + 4; v.status.rxahberr := '1'; v.ctrl.rxen := '0'; end if; when write_status => v.rmsto.req := '1'; v.rmsto.addr := r.rxdesc & r.rxdsel & "000"; v.rxdstate := write_status2; if multicast = 1 then v.rmsto.data := "00000" & r.mcastacc & "0000000" & r.rxstatus & "000" & r.rxlength; else v.rmsto.data := "0000000000000" & r.rxstatus & "000" & r.rxlength; end if; when write_status2 => if rmsti.grant = '1' then v.rmsto.req := '0'; v.rmsto.addr := r.rmsto.addr + 4; end if; if rmsti.ready = '1' then if (r.rxstatus(4) or not r.rxstatus(3)) = '1' then v.rxdstate := discard; else v.rxdstate := idle; end if; if (r.ctrl.rx_irqen and r.rxirq) = '1' then vpirq := '1'; end if; if conv_integer(r.rxstatus) = 0 then v.status.rx_int := '1'; else v.status.rx_err := '1'; end if; if r.rxwrap = '1' then v.rxdsel := (others => '0'); else v.rxdsel := r.rxdsel + 1; end if; end if; if rmsti.error = '1' then v.rmsto.req := '0'; v.rxdstate := idle; v.status.rxahberr := '1'; v.ctrl.rxen := '0'; end if; when discard => if (r.rxdoneold = '0') then if conv_integer(r.rfcnt) /= 0 then v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1; v.rxcnt := r.rxcnt + 4; end if; else if r.rxstatus(3) = '1' then v.rfcnt := (others => '0'); v.rfwpnt := (others => '0'); v.rfrpnt := (others => '0'); v.writeok := '1'; v.rxbytecount := (others => '0'); v.rxlength := (others => '0'); v.rxdstate := idle; elsif (conv_integer(r.rxcnt) < conv_integer(r.rxbytecount)) then if conv_integer(r.rfcnt) /= 0 then v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1; v.rxcnt := r.rxcnt + 4; end if; else v.rxdstate := idle; v.ctrlpkt := '0'; end if; end if; when others => null; end case; --rx address/type check if r.check = '1' and r.rxcnt(10 downto 5) = "000000" then case r.rxcnt(4 downto 2) is when "001" => if r.ctrl.prom = '1' then v.addrok := '1'; end if; v.mcast := r.checkdata(24); if r.checkdata = broadcast(47 downto 16) then v.bcast := '1'; end if; if r.checkdata = r.mac_addr(47 downto 16) then v.msbgood := '1'; end if; when "010" => if r.checkdata(31 downto 16) = broadcast(15 downto 0) then if r.bcast = '1' then v.addrok := '1'; end if; else v.bcast := '0'; end if; if r.checkdata(31 downto 16) = r.mac_addr(15 downto 0) then if r.msbgood = '1' then v.addrok := '1'; end if; end if; if multicast = 1 then v.hashlookup := r.hash(conv_integer(rxo.mcasthash)); end if; when "011" => if multicast = 1 then if (r.hashlookup and r.ctrl.mcasten and r.mcast) = '1' then v.addrok := '1'; if r.bcast = '0' then v.mcastacc := '1'; end if; end if; end if; when "100" => if r.checkdata(31 downto 16) = ctrlopcode then v.ctrlpkt := '1'; end if; v.addrdone := '1'; when others => null; end case; end if; --rx packet done if (rxdone and not rxstart) = '1' then v.gotframe := rxo.gotframe; v.rxbytecount := rxo.byte_count; v.rxstatus(3 downto 0) := rxo.status; if (unsigned(rxo.lentype) > maxsizerx) or (rxo.status /= "0000") then v.rxlength := rxo.byte_count; else v.rxlength := rxo.lentype(10 downto 0); if (rxo.lentype(10 downto 0) > minpload) and (rxo.lentype(10 downto 0) /= rxo.byte_count) then if rxo.status(2 downto 0) = "000" then v.rxstatus(4) := '1'; v.rxlength := rxo.byte_count; v.usesizefield := '0'; end if; elsif (rxo.lentype(10 downto 0) <= minpload) and (rxo.byte_count /= minpload) then if rxo.status(2 downto 0) = "000" then v.rxstatus(4) := '1'; v.rxlength := rxo.byte_count; v.usesizefield := '0'; end if; end if; end if; v.rxdoneold := '1'; v.rxdoneack := not r.rxdoneack; end if; --rx fifo write if vrxwrite = '1' then v.rxwriteack := not r.rxwriteack; if (not r.rfcnt(fabits)) = '1' then v.rfwpnt := r.rfwpnt + 1; v.rfcnt := v.rfcnt + 1; v.writeok := '1'; vrxfi.write := '1'; else v.writeok := '0'; end if; end if; --must be placed here because it uses variable if (ramdebug = 0) or (r.ctrl.ramdebugen = '0') then vrxfi.raddress := v.rfrpnt; end if; ------------------------------------------------------------------------------- -- MDIO INTERFACE ------------------------------------------------------------- ------------------------------------------------------------------------------- --mdio commands if enable_mdio = 1 then mclkvec := r.mdioclkold & r.mdioclk; mclk := mclkvec(mdiohold-1) and not mclkvec(mdiohold); nmclk := mclkvec(1) and not mclkvec(0); v.mdioclkold := mclkvec(mdiohold-1 downto 0); if r.mdccnt = "00000000" then v.mdccnt := divisor; v.mdioclk := not r.mdioclk; else v.mdccnt := r.mdccnt - 1; end if; mdioindex := conv_integer(r.cnt); v.mdioi := mdio_i; case r.mdio_state is when idle => if (enable_mdio = 1) and (edcl = 0) and (r.ctrl.reset = '1') then v.mdio_state := idle; v.mdio_ctrl.read := '0'; v.mdio_ctrl.write := '0'; v.mdio_ctrl.busy := '0'; v.mdio_ctrl.data := (others => '0'); v.mdio_ctrl.regadr := (others => '0'); v.ctrl.reset := '0'; if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if; end if; if mclk = '1' then v.cnt := (others => '0'); if r.mdio_ctrl.busy = '1' then v.mdio_ctrl.linkfail := '0'; if r.mdio_ctrl.read = '1' then v.mdio_ctrl.write := '0'; end if; v.mdio_state := preamble; v.mdioo := '1'; if OEPOL = 0 then v.mdioen := '0'; else v.mdioen := '1'; end if; end if; end if; when preamble => if mclk = '1' then v.cnt := r.cnt + 1; if r.cnt = "11111" then v.mdioo := '0'; v.mdio_state := startst; end if; end if; when startst => if mclk = '1' then v.mdioo := '1'; v.mdio_state := op; v.cnt := (others => '0'); end if; when op => if mclk = '1' then v.mdio_state := op2; if r.mdio_ctrl.read = '1' then v.mdioo := '1'; else v.mdioo := '0'; end if; end if; when op2 => if mclk = '1' then v.mdioo := not r.mdioo; v.mdio_state := phyadr; v.cnt := (others => '0'); end if; when phyadr => if mclk = '1' then v.cnt := r.cnt + 1; case mdioindex is when 0 => v.mdioo := r.mdio_ctrl.phyadr(4); when 1 => v.mdioo := r.mdio_ctrl.phyadr(3); when 2 => v.mdioo := r.mdio_ctrl.phyadr(2); when 3 => v.mdioo := r.mdio_ctrl.phyadr(1); when 4 => v.mdioo := r.mdio_ctrl.phyadr(0); v.mdio_state := regadr; v.cnt := (others => '0'); when others => null; end case; end if; when regadr => if mclk = '1' then v.cnt := r.cnt + 1; case mdioindex is when 0 => v.mdioo := r.mdio_ctrl.regadr(4); when 1 => v.mdioo := r.mdio_ctrl.regadr(3); when 2 => v.mdioo := r.mdio_ctrl.regadr(2); when 3 => v.mdioo := r.mdio_ctrl.regadr(1); when 4 => v.mdioo := r.mdio_ctrl.regadr(0); v.mdio_state := ta; v.cnt := (others => '0'); when others => null; end case; end if; when ta => if mclk = '1' then v.mdio_state := ta2; if r.mdio_ctrl.read = '1' then if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if; else v.mdioo := '1'; end if; end if; when ta2 => if mclk = '1' then v.cnt := "01111"; v.mdio_state := ta3; if r.mdio_ctrl.write = '1' then v.mdioo := '0'; v.mdio_state := data; end if; end if; when ta3 => if mclk = '1' then v.mdio_state := data; end if; if nmclk = '1' then if r.mdioi /= '0' then v.mdio_ctrl.linkfail := '1'; end if; end if; when data => if mclk = '1' then v.cnt := r.cnt - 1; if r.cnt = "00000" then v.mdio_state := dataend; end if; if r.mdio_ctrl.read = '0' then v.mdioo := r.mdio_ctrl.data(mdioindex); end if; end if; if nmclk = '1' then if r.mdio_ctrl.read = '1' then v.mdio_ctrl.data(mdioindex) := r.mdioi; end if; end if; when dataend => if mclk = '1' then if (rmii = 1) or (edcl /= 0) then v.init_busy := '0'; if r.duplexstate = done then v.mdio_ctrl.busy := '0'; end if; else v.mdio_ctrl.busy := '0'; end if; v.mdio_ctrl.read := '0'; v.mdio_ctrl.write := '0'; v.mdio_state := idle; if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if; end if; when others => null; end case; end if; ------------------------------------------------------------------------------- -- EDCL ----------------------------------------------------------------------- ------------------------------------------------------------------------------- if (edcl /= 0) then if (ramdebug /= 2) or (r.ctrl.ramdebugen = '0') then veri.renable := r.erenable; veri.writem := '0'; veri.writel := '0'; veri.waddressm := r.rpnt & r.rcntm; veri.waddressl := r.rpnt & r.rcntl; vrxenable := '1'; end if; swap := '0'; vecnt := conv_integer(r.ecnt); setmz := '0'; if vrxwrite = '1' then if r.ctrl.edcldis = '0' then v.rxwriteack := not r.rxwriteack; end if; end if; --edcl receiver case r.edclrstate is when idle => v.edclbcast := '0'; v.erxidle := '1'; if (ramdebug /= 2) or (r.ctrl.ramdebugen = '0') then if (rxstart and not r.ctrl.edcldis) = '1' then v.edclrstate := wrda; v.edclactive := '0'; v.erxidle := '0'; v.rcntm := conv_std_logic_vector(2, bpbits); v.rcntl := conv_std_logic_vector(1, bpbits); end if; end if; when wrda => if vrxwrite = '1' then v.edclrstate := wrdsa; veri.writem := '1'; veri.writel := '1'; swap := '1'; v.rcntm := r.rcntm - 2; v.rcntl := r.rcntl + 1; if (r.emacaddr(47 downto 16) /= rxo.dataout) and (X"FFFFFFFF" /= rxo.dataout) then v.edclrstate := spill; elsif (X"FFFFFFFF" = rxo.dataout) then v.edclbcast := '1'; end if; if conv_integer(r.abufs) = wsz then v.edclrstate := spill; end if; end if; if (rxdone and not rxstart) = '1' then v.edclrstate := idle; end if; when wrdsa => if vrxwrite = '1' then v.edclrstate := wrsa; swap := '1'; veri.writem := '1'; veri.writel := '1'; v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl - 2; if (r.emacaddr(15 downto 0) /= rxo.dataout(31 downto 16)) and (X"FFFF" /= rxo.dataout(31 downto 16)) then v.edclrstate := spill; elsif (X"FFFF" = rxo.dataout(31 downto 16)) then v.edclbcast := r.edclbcast; end if; end if; if (rxdone and not rxstart) = '1' then v.edclrstate := idle; end if; when wrsa => if vrxwrite = '1' then veri.writem := '1'; veri.writel := '1'; v.edclrstate := wrtype; swap := '1'; v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl + 3; end if; if (rxdone and not rxstart) = '1' then v.edclrstate := idle; end if; when wrtype => if vrxwrite = '1' then veri.writem := '1'; veri.writel := '1'; v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1; if X"0800" = rxo.dataout(31 downto 16) and (r.edclbcast = '0') then v.edclrstate := ip; elsif X"0806" = rxo.dataout(31 downto 16) and (r.edclbcast = '1') then v.edclrstate := arp; else v.edclrstate := spill; end if; end if; v.ecnt := (others => '0'); v.ipcrc := (others => '0'); if (rxdone and not rxstart) = '1' then v.edclrstate := idle; end if; when ip => if vrxwrite = '1' then v.ecnt := r.ecnt + 1; veri.writem := '1'; veri.writel := '1'; case vecnt is when 0 => v.ipcrc := crcadder(not rxo.dataout(31 downto 16), r.ipcrc); v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1; when 1 => v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 2; when 2 => v.ipcrc := crcadder(not rxo.dataout(31 downto 16), r.ipcrc); v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl - 1; when 3 => v.rcntm := r.rcntm - 1; v.rcntl := r.rcntl + 2; when 4 => v.udpsrc := rxo.dataout(15 downto 0); v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl + 1; when 5 => setmz := '1'; v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1; when 6 => v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1; when 7 => v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1; if (rxo.dataout(31 downto 18) = r.seq) then v.nak := '0'; else v.nak := '1'; veri.datain(31 downto 18) := r.seq; end if; veri.datain(17) := v.nak; v.ewr := rxo.dataout(17); if (rxo.dataout(17) or v.nak) = '1' then veri.datain(16 downto 7) := (others => '0'); end if; v.oplen := rxo.dataout(16 downto 7); v.applength := "000000" & veri.datain(16 downto 7); v.ipcrc := crcadder(v.applength + 38, r.ipcrc); v.write(conv_integer(r.rpnt)) := rxo.dataout(17); when 8 => ipcrctmp := (others => '0'); ipcrctmp(1 downto 0) := r.ipcrc(17 downto 16); ipcrctmp2 := "00" & r.ipcrc(15 downto 0); v.ipcrc := crcadder(ipcrctmp, ipcrctmp2); v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1; v.edclrstate := ipdata; when others => null; end case; end if; if (rxdone and not rxstart) = '1' then v.edclrstate := idle; end if; when ipdata => if (vrxwrite and r.ewr and not r.nak) = '1' and (r.rcntm /= ebufmax) then veri.writem := '1'; veri.writel := '1'; v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1; end if; if rxdone = '1' then v.edclrstate := ipcrc; v.rcntm := conv_std_logic_vector(6, bpbits); ipcrctmp := (others => '0'); ipcrctmp(1 downto 0) := r.ipcrc(17 downto 16); ipcrctmp2 := "00" & r.ipcrc(15 downto 0); v.ipcrc := crcadder(ipcrctmp, ipcrctmp2); if conv_integer(v.rxstatus(3 downto 0)) /= 0 then v.edclrstate := idle; end if; end if; when ipcrc => veri.writem := '1'; veri.datain(31 downto 16) := not r.ipcrc(15 downto 0); v.edclrstate := udp; v.rcntm := conv_std_logic_vector(9, bpbits); v.rcntl := conv_std_logic_vector(9, bpbits); when udp => veri.writem := '1'; veri.writel := '1'; v.edclrstate := iplength; veri.datain(31 downto 16) := r.udpsrc; veri.datain(15 downto 0) := r.applength + 18; v.rcntm := conv_std_logic_vector(4, bpbits); when iplength => veri.writem := '1'; veri.datain(31 downto 16) := r.applength + 38; v.edclrstate := oplength; v.rcntm := conv_std_logic_vector(10, bpbits); v.rcntl := conv_std_logic_vector(10, bpbits); when oplength => if rxstart = '0' then v.abufs := r.abufs + 1; v.rpnt := r.rpnt + 1; veri.writel := '1'; veri.writem := '1'; end if; if r.nak = '0' then v.seq := r.seq + 1; end if; v.edclrstate := idle; veri.datain(31 downto 0) := (others => '0'); veri.datain(15 downto 0) := "00000" & r.nak & r.oplen; when arp => if vrxwrite = '1' then v.ecnt := r.ecnt + 1; veri.writem := '1'; veri.writel := '1'; case vecnt is when 0 => v.rcntm := r.rcntm + 4; when 1 => swap := '1'; veri.writel := '0'; v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 4; when 2 => swap := '1'; v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1; when 3 => swap := '1'; v.rcntm := r.rcntm - 4; v.rcntl := r.rcntl - 4; when 4 => veri.datain := r.emacaddr(31 downto 16) & r.emacaddr(47 downto 32); v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1; when 5 => v.rcntl := r.rcntl + 1; veri.datain(31 downto 16) := rxo.dataout(15 downto 0); veri.datain(15 downto 0) := r.emacaddr(15 downto 0); if rxo.dataout(15 downto 0) /= r.edclip(31 downto 16) then v.edclrstate := spill; end if; when 6 => swap := '1'; veri.writem := '0'; v.rcntm := conv_std_logic_vector(5, bpbits); v.rcntl := conv_std_logic_vector(1, bpbits); if rxo.dataout(31 downto 16) /= r.edclip(15 downto 0) then v.edclrstate := spill; else v.edclactive := '1'; end if; when 7 => veri.writem := '0'; veri.datain(15 downto 0) := r.emacaddr(47 downto 32); v.rcntl := r.rcntl + 1; v.rcntm := conv_std_logic_vector(2, bpbits); when 8 => v.edclrstate := arpop; veri.datain := r.emacaddr(31 downto 0); v.rcntm := conv_std_logic_vector(5, bpbits); when others => null; end case; end if; if (rxdone and not rxstart) = '1' then v.edclrstate := idle; end if; when arpop => veri.writem := '1'; veri.datain(31 downto 16) := X"0002"; if (rxdone and not rxstart) = '1' then v.edclrstate := idle; if conv_integer(v.rxstatus) = 0 and (rxo.gotframe = '1') then v.abufs := r.abufs + 1; v.rpnt := r.rpnt + 1; end if; end if; when spill => if (rxdone and not rxstart) = '1' then v.edclrstate := idle; end if; end case; --edcl transmitter case r.txdstate is when getlen => v.tcnt := r.tcnt + 1; if conv_integer(r.tcnt) = 10 then v.txlength := '0' & erdata(9 downto 0); v.tnak := erdata(10); v.txcnt := v.txlength; if (r.write(conv_integer(r.tpnt)) or v.tnak) = '1' then v.txlength := (others => '0'); end if; end if; if conv_integer(r.tcnt) = 11 then v.txdstate := readhdr; v.tcnt := (others => '0'); end if; when readhdr => v.tcnt := r.tcnt + 1; vtxfi.write := '1'; v.tfwpnt := r.tfwpnt + 1; v.tfcnt := v.tfcnt + 1; vtxfi.datain := erdata; if conv_integer(r.tcnt) = 12 then v.txaddr := erdata(31 downto 2); end if; if conv_integer(r.tcnt) = 3 then if erdata(31 downto 16) = X"0806" then v.tarp := '1'; v.txlength := conv_std_logic_vector(42, 11); else v.tarp := '0'; v.txlength := r.txlength + 52; end if; end if; if r.tarp = '0' then if conv_integer(r.tcnt) = 12 then v.txdstate := start; end if; else if conv_integer(r.tcnt) = 10 then v.txdstate := start; end if; end if; if (txrestart or txdone) = '1' then v.txdstate := etdone; end if; when start => v.tmsto.addr := r.txaddr & "00"; v.tmsto.write := r.write(conv_integer(r.tpnt)); if (edclsepahbg /= 0) and (edcl /= 0) then v.tmsto2.addr := r.txaddr & "00"; v.tmsto2.write := r.write(conv_integer(r.tpnt)); end if; if (conv_integer(r.txcnt) = 0) or (r.tarp or r.tnak) = '1' then v.txdstate := etdone; v.txstart_sync := not r.txstart_sync; v.tmsto.req := '0'; if (edclsepahbg /= 0) and (edcl /= 0) then v.tmsto2.req := '0'; end if; elsif r.write(conv_integer(r.tpnt)) = '0' then v.txdstate := req; v.tedcl := '1'; else v.txstart_sync := not r.txstart_sync; v.tedcl := '1'; v.tcnt := r.tcnt + 1; if (edclsepahbg = 0) or (edcl = 0) or (r.edclsepahb = '0') then v.tmsto.req := '1'; v.tmsto.data := erdata; v.txdstate := wrbus1; else v.tmsto2.req := '1'; v.tmsto2.data := erdata; v.txdstate := wrbus2; end if; end if; if (txrestart or txdone) = '1' then v.txdstate := etdone; end if; when wrbus1 => if tmsti.grant = '1' then v.tmsto.addr := r.tmsto.addr + 4; if ((conv_integer(r.txcnt) <= 4) and (tmsti.ready = '0')) or ((conv_integer(r.txcnt) <= 8) and (tmsti.ready = '1')) then v.tmsto.req := '0'; end if; end if; if (tmsti.ready or tmsti.error) = '1' then v.tmsto.data := erdata; v.tcnt := r.tcnt + 1; v.txcnt := r.txcnt - 4; if r.tmsto.req = '0' then v.txdstate := etdone; end if; end if; if tmsti.retry = '1' then v.tmsto.addr := r.tmsto.addr - 4; v.tmsto.req := '1'; end if; when wrbus2 => if tmsti2.grant = '1' then v.tmsto2.addr := r.tmsto2.addr + 4; if ((conv_integer(r.txcnt) <= 4) and (tmsti2.ready = '0')) or ((conv_integer(r.txcnt) <= 8) and (tmsti2.ready = '1')) then v.tmsto2.req := '0'; end if; end if; if (tmsti2.ready or tmsti2.error) = '1' then v.tmsto2.data := erdata; v.tcnt := r.tcnt + 1; v.txcnt := r.txcnt - 4; if r.tmsto2.req = '0' then v.txdstate := etdone; end if; end if; if tmsti2.retry = '1' then v.tmsto2.addr := r.tmsto2.addr - 4; v.tmsto2.req := '1'; end if; when etdone => if txdone = '1' then v.txdstate := idle; v.txdone(nsync) := r.txdone(nsync-1); v.abufs := v.abufs - 1; v.tpnt := r.tpnt + 1; v.tfcnt := (others => '0'); v.tfrpnt := (others => '0'); v.tfwpnt := (others => '0'); elsif txrestart = '1' then v.txdstate := idle; end if; when others => null; end case; if swap = '1' then veri.datain(31 downto 16) := rxo.dataout(15 downto 0); veri.datain(15 downto 0) := rxo.dataout(31 downto 16); end if; if setmz = '1' then veri.datain(31 downto 16) := (others => '0'); end if; if (ramdebug /= 2) or (edcl = 0) or (edcldbgread = '0') then veri.raddress := r.tpnt & v.tcnt; end if; end if; --edcl duplex mode read if (rmii = 1) or (edcl /= 0) then --edcl, gbit link mode check case r.duplexstate is when start => v.mdio_ctrl.regadr := r.regaddr; v.init_busy := '1'; v.mdio_ctrl.busy := '1'; v.duplexstate := waitop; if (r.phywr or r.rstphy) = '1' then v.mdio_ctrl.write := '1'; else v.mdio_ctrl.read := '1'; end if; if r.rstphy = '1' then v.mdio_ctrl.data := X"9000"; end if; when waitop => if r.init_busy = '0' then if r.mdio_ctrl.linkfail = '1' then v.duplexstate := start; elsif r.rstphy = '1' then v.duplexstate := start; v.rstphy := '0'; else v.duplexstate := nextop; end if; end if; when nextop => case r.regaddr is when "00000" => if r.mdio_ctrl.data(15) = '1' then --rst not finished v.duplexstate := start; elsif (r.phywr and not r.rstaneg) = '1' then --forced to 10 Mbit HD v.duplexstate := selmode; elsif r.mdio_ctrl.data(12) = '0' then --no auto neg v.duplexstate := start; v.phywr := '1'; v.mdio_ctrl.data := (others => '0'); else v.duplexstate := start; v.regaddr := "00001"; end if; if r.rstaneg = '1' then v.phywr := '0'; end if; when "00001" => v.ext := r.mdio_ctrl.data(8); --extended status register v.extcap := r.mdio_ctrl.data(1); --extended register capabilities v.duplexstate := start; if r.mdio_ctrl.data(0) = '0' then --no extended register capabilites, unable to read aneg config --forcing 10 Mbit v.duplexstate := start; v.phywr := '1'; v.mdio_ctrl.data := (others => '0'); v.regaddr := (others => '0'); elsif (r.mdio_ctrl.data(8) and not r.rstaneg) = '1' then --phy gbit capable, disable gbit v.regaddr := "01001"; elsif r.mdio_ctrl.data(5) = '1' then --auto neg completed v.regaddr := "00100"; elsif r.disableduplex = '1' then v.duplexstate := done; v.mdio_ctrl.busy := '0'; end if; when "00100" => v.duplexstate := start; v.regaddr := "00101"; v.capbil(4 downto 0) := r.mdio_ctrl.data(9 downto 5); when "00101" => v.duplexstate := selmode; v.capbil(4 downto 0) := r.capbil(4 downto 0) and r.mdio_ctrl.data(9 downto 5); when "01001" => if r.phywr = '0' then v.duplexstate := start; v.phywr := '1'; v.mdio_ctrl.data(9 downto 8) := (others => '0'); else v.regaddr := "00000"; v.duplexstate := start; v.phywr := '1'; v.mdio_ctrl.data := X"3300"; v.rstaneg := '1'; end if; when others => null; end case; when selmode => v.duplexstate := done; v.mdio_ctrl.busy := '0'; if r.phywr = '1' then v.ctrl.full_duplex := '0'; v.ctrl.speed := '0'; else sel_op_mode(r.capbil, v.ctrl.speed, v.ctrl.full_duplex); end if; when done => null; end case; end if; --transmitter retry if tmsti.retry = '1' then v.tmsto.req := '1'; v.tmsto.addr := r.tmsto.addr - 4; v.txburstcnt := r.txburstcnt - 1; end if; --transmitter AHB error if tmsti.error = '1' and (not ((edcl /= 0) and (r.tedcl = '1'))) then v.tmsto.req := '0'; v.txdstate := ahberror; end if; if (edclsepahbg /= 0) and (edcl /= 0) then --transmitter retry if tmsti2.retry = '1' then v.tmsto2.req := '1'; v.tmsto2.addr := r.tmsto2.addr - 4; v.txburstcnt := r.txburstcnt - 1; end if; --transmitter AHB error if tmsti2.error = '1' and (not ((edcl /= 0) and (r.tedcl = '1'))) then v.tmsto2.req := '0'; v.txdstate := ahberror; end if; end if; --receiver retry if rmsti.retry = '1' then v.rmsto.req := '1'; v.rmsto.addr := r.rmsto.addr - 4; v.rxburstcnt := r.rxburstcnt - 1; end if; ------------------------------------------------------------------------------ -- RESET ---------------------------------------------------------------------- ------------------------------------------------------------------------------- if irst = '0' then v.txdstate := idle; v.rxdstate := idle; v.rfrpnt := (others => '0'); v.tmsto.req := '0'; v.tmsto2.req := '0'; v.rfwpnt := (others => '0'); v.rfcnt := (others => '0'); v.ctrl.txen := '0'; v.txirqgen := '0'; v.ctrl.rxen := '0'; v.txdsel := (others => '0'); v.txstart_sync := '0'; v.txread := (others => '0'); v.txrestart := (others => '0'); v.txdone := (others => '0'); v.txreadack := '0'; v.rxdsel := (others => '0'); v.rxdone := (others => '0'); v.rxdoneold := '0'; v.rxdoneack := '0'; v.rxwriteack := '0'; v.rxstart := (others => '0'); v.rxwrite := (others => '0'); v.status.invaddr := '0'; v.status.toosmall := '0'; v.ctrl.full_duplex := '0'; v.writeok := '1'; if (enable_mdio = 0) or (edcl /= 0) then v.ctrl.reset := '0'; end if; if enable_mdint = 1 then v.status.phystat := '0'; v.ctrl.pstatirqen := '0'; end if; if (edcl /= 0) then v.tpnt := (others => '0'); v.rpnt := (others => '0'); v.tcnt := (others => '0'); v.edclactive := '0'; v.tarp := '0'; v.abufs := (others => '0'); v.edclrstate := idle; v.emacaddr := macaddrt; end if; if (rmii = 1) then v.ctrl.speed := '1'; end if; v.ctrl.tx_irqen := '0'; v.ctrl.rx_irqen := '0'; v.ctrl.prom := '0'; if multicast = 1 then v.ctrl.mcasten := '0'; end if; if ramdebug /= 0 then v.ctrl.ramdebugen := '0'; end if; end if; if edcl = 0 then v.edclrstate := idle; v.edclactive := '0'; v.nak := '0'; v.ewr := '0'; v.write := (others => '0'); v.seq := (others => '0'); v.abufs := (others => '0'); v.tpnt := (others => '0'); v.rpnt := (others => '0'); v.tcnt := (others => '0'); v.rcntm := (others => '0'); v.rcntl := (others => '0'); v.ipcrc := (others => '0'); v.applength := (others => '0'); v.oplen := (others => '0'); v.udpsrc := (others => '0'); v.ecnt := (others => '0'); v.tarp := '0'; v.tnak := '0'; v.tedcl := '0'; v.edclbcast := '0'; end if; --some parts of edcl are only affected by hw reset if rst = '0' then v.edclip := conv_std_logic_vector(ipaddrh, 16) & conv_std_logic_vector(ipaddrl, 16); if edcl > 1 then v.edclip(3 downto 0) := edcladdr; v.emacaddr(3 downto 0) := edcladdr; end if; v.duplexstate := start; v.regaddr := (others => '0'); v.phywr := '0'; v.rstphy := '1'; v.rstaneg := '0'; if phyrstadr /= 32 then v.mdio_ctrl.phyadr := conv_std_logic_vector(phyrstadr, 5); else v.mdio_ctrl.phyadr := phyrstaddr; end if; v.seq := (others => '0'); if (enable_mdio = 1) then v.mdccnt := divisor; v.mdioclk := '0'; end if; if edcl /= 0 then v.disableduplex := '0'; end if; if edcl = 3 then v.ctrl.edcldis := edcldisable; elsif edcl /= 0 then v.ctrl.edcldis := '0'; end if; v.ctrl.reset := '0'; if (enable_mdio = 1) then v.mdio_state := idle; v.mdio_ctrl.read := '0'; v.mdio_ctrl.write := '0'; v.mdio_ctrl.busy := '0'; v.mdio_ctrl.data := (others => '0'); v.mdio_ctrl.regadr := (others => '0'); v.ctrl.reset := '0'; v.mdio_ctrl.linkfail := '1'; if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if; v.cnt := (others => '0'); end if; if edclsepahbg /= 0 then v.edclsepahb := edclsepahb; end if; v.txcnt := (others => '0'); v.txburstcnt := (others => '0'); v.tedcl := '0'; v.erenable := '0'; v.rmsto.req := '0'; v.rmsto.write := '0'; v.addrok := '0'; v.rxburstcnt := (others => '0'); v.addrdone := '0'; v.rxcnt := (others => '0'); v.rxdoneold := '0'; v.ctrlpkt := '0'; v.bcast := '0'; v.edclactive := '0'; v.msbgood := '0'; v.rxrenable := '0'; if multicast = 1 then v.mcast := '0'; v.mcastacc := '0'; end if; v.tnak := '0'; v.tedcl := '0'; v.edclbcast := '0'; v.gotframe := '0'; v.rxbytecount := (others => '0'); v.rxlength := (others => '0'); v.txburstav := '0'; v.txdataav := '0'; v.txstatus := (others => '0'); v.txstart := '0'; v.tfcnt := (others => '0'); v.tfrpnt := (others => '0'); v.tfwpnt := (others => '0'); v.txaddr := (others => '0'); v.cnt := (others => '0'); v.rxaddr := (others => '0'); v.rxstatus := (others => '0'); v.rxwrap := '0'; v.rxden := '0'; v.rmsto.addr := (others => '0'); v.tmsto.addr := (others => '0'); v.nak := '0'; v.ewr := '0'; v.write := (others => '0'); v.applength := (others => '0'); v.oplen := (others => '0'); v.udpsrc := (others => '0'); v.ecnt := (others => '0'); v.rcntm := (others => '0'); v.rcntl := (others => '0'); end if; ------------------------------------------------------------------------------- -- SIGNAL ASSIGNMENTS --------------------------------------------------------- ------------------------------------------------------------------------------- rin <= v; prdata <= vprdata; irq <= vpirq; --rx ahb fifo rxrenable <= vrxfi.renable; rxraddress(10 downto fabits) <= (others => '0'); rxraddress(fabits-1 downto 0) <= vrxfi.raddress; rxwrite <= vrxfi.write; rxwdata <= vrxfi.datain; rxwaddress(10 downto fabits) <= (others => '0'); rxwaddress(fabits-1 downto 0) <= vrxfi.waddress; --tx ahb fifo txrenable <= vtxfi.renable; txraddress(10 downto txfabits) <= (others => '0'); txraddress(txfabits-1 downto 0) <= vtxfi.raddress; txwrite <= vtxfi.write; txwdata <= vtxfi.datain; txwaddress(10 downto txfabits) <= (others => '0'); txwaddress(txfabits-1 downto 0) <= vtxfi.waddress; --edcl buf erenable <= veri.renable; eraddress(15 downto eabits) <= (others => '0'); eraddress(eabits-1 downto 0) <= veri.raddress; ewritem <= veri.writem; ewritel <= veri.writel; ewaddressm(15 downto eabits) <= (others => '0'); ewaddressm(eabits-1 downto 0) <= veri.waddressm(eabits-1 downto 0); ewaddressl(15 downto eabits) <= (others => '0'); ewaddressl(eabits-1 downto 0) <= veri.waddressl(eabits-1 downto 0); ewdata <= veri.datain; rxi.enable <= vrxenable; end process; rxi.writeack <= r.rxwriteack; rxi.doneack <= r.rxdoneack; rxi.speed <= r.ctrl.speed; rxi.writeok <= r.writeok; rxi.rxd <= rxd; rxi.rx_dv <= rx_dv; rxi.rx_crs <= rx_crs; rxi.rx_er <= rx_er; txi.rx_col <= rx_col; txi.rx_crs <= rx_crs; txi.full_duplex <= r.ctrl.full_duplex; txi.start <= r.txstart_sync; txi.readack <= r.txreadack; txi.speed <= r.ctrl.speed; txi.data <= r.txdata; txi.valid <= r.txvalid; txi.len <= r.txlength; mdc <= r.mdioclk; mdio_o <= r.mdioo; mdio_oe <= testoen when (scanen/=0 and testen/='0') else r.mdioen; tmsto <= r.tmsto; rmsto <= r.rmsto; tmsto2 <= r.tmsto2; txd <= txo.txd; tx_en <= txo.tx_en; tx_er <= txo.tx_er; ahbmi.hgrant <= hgrant; ahbmi.hready <= hready; ahbmi.hresp <= hresp; ahbmi.hrdata <= hrdata; hbusreq <= ahbmo.hbusreq; hlock <= ahbmo.hlock; htrans <= ahbmo.htrans; haddr <= ahbmo.haddr; hwrite <= ahbmo.hwrite; hsize <= ahbmo.hsize; hburst <= ahbmo.hburst; hprot <= ahbmo.hprot; hwdata <= ahbmo.hwdata; ahbmi2.hgrant <= ehgrant; ahbmi2.hready <= ehready; ahbmi2.hresp <= ehresp; ahbmi2.hrdata <= ehrdata; ehbusreq <= ahbmo2.hbusreq; ehlock <= ahbmo2.hlock; ehtrans <= ahbmo2.htrans; ehaddr <= ahbmo2.haddr; ehwrite <= ahbmo2.hwrite; ehsize <= ahbmo2.hsize; ehburst <= ahbmo2.hburst; ehprot <= ahbmo2.hprot; ehwdata <= ahbmo2.hwdata; speed <= r.ctrl.speed; reset <= irst; regs : process(clk) is begin if rising_edge(clk) then r <= rin; end if; end process; ------------------------------------------------------------------------------- -- TRANSMITTER----------------------------------------------------------------- ------------------------------------------------------------------------------- tx_rmii0 : if rmii = 0 generate tx0: greth_tx generic map( ifg_gap => ifg_gap, attempt_limit => attempt_limit, backoff_limit => backoff_limit, nsync => nsync, rmii => rmii) port map( rst => arst, clk => tx_clk, txi => txi, txo => txo); end generate; tx_rmii1 : if rmii = 1 generate tx0: greth_tx generic map( ifg_gap => ifg_gap, attempt_limit => attempt_limit, backoff_limit => backoff_limit, nsync => nsync, rmii => rmii) port map( rst => arst, clk => rmii_clk, txi => txi, txo => txo); end generate; ------------------------------------------------------------------------------- -- RECEIVER ------------------------------------------------------------------- ------------------------------------------------------------------------------- rx_rmii0 : if rmii = 0 generate rx0 : greth_rx generic map( nsync => nsync, rmii => rmii, multicast => multicast, maxsize => maxsize) port map( rst => arst, clk => rx_clk, rxi => rxi, rxo => rxo); end generate; rx_rmii1 : if rmii = 1 generate rx0 : greth_rx generic map( nsync => nsync, rmii => rmii, multicast => multicast, maxsize => maxsize) port map( rst => arst, clk => rmii_clk, rxi => rxi, rxo => rxo); end generate; ------------------------------------------------------------------------------- -- AHB MST INTERFACE ---------------------------------------------------------- ------------------------------------------------------------------------------- ahb0 : eth_ahb_mst port map(rst, clk, ahbmi, ahbmo, tmsto, tmsti, rmsto, rmsti); edclmst : if edclsepahbg = 1 generate ahb1 : eth_edcl_ahb_mst port map(rst, clk, ahbmi2, ahbmo2, tmsto2, tmsti2); end generate; end architecture;

-- ------------------------------------------------------------- -- -- Entity Declaration for inst_eda_e -- -- Generated -- by: wig -- on: Mon Mar 22 13:27:43 2004 -- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_eda_e-e.vhd,v 1.1 2004/04/06 10:50:07 wig Exp $ -- $Date: 2004/04/06 10:50:07 $ -- $Log: inst_eda_e-e.vhd,v $ -- Revision 1.1 2004/04/06 10:50:07 wig -- Adding result/mde_tests -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp -- -- Generator: mix_0.pl Version: Revision: 1.26 , [email protected] -- (C) 2003 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity inst_eda_e -- entity inst_eda_e is -- Generics: -- No Generated Generics for Entity inst_eda_e -- Generated Port Declaration: port( -- Generated Port for Entity inst_eda_e cgs_ramclk : out std_ulogic; nreset : out std_ulogic; nreset_s : out std_ulogic; vclkl27 : out std_ulogic -- End of Generated Port for Entity inst_eda_e ); end inst_eda_e; -- -- End of Generated Entity inst_eda_e -- -- --!End of Entity/ies -- --------------------------------------------------------------

-- Automatically generated VHDL-93 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.MATH_REAL.ALL; use std.textio.all; use work.all; use work.packetprocessor_types.all; entity packetprocessor_blockram is port(rd : in unsigned(10 downto 0); wrm : in std_logic_vector(19 downto 0); -- clock system1000 : in std_logic; result : out unsigned(7 downto 0)); end; architecture structural of packetprocessor_blockram is signal x2 : unsigned(10 downto 0); signal wild2_app_arg : signed(63 downto 0); signal y : unsigned(7 downto 0); signal wild2 : signed(63 downto 0); signal x1 : packetprocessor_types.tup2_0; signal result_0 : signed(63 downto 0); signal wild_app_arg : signed(63 downto 0); signal case_alt : unsigned(7 downto 0); signal case_alt_0 : signed(63 downto 0); signal wild : signed(63 downto 0); signal app_arg : unsigned(7 downto 0); signal app_arg_0 : signed(63 downto 0); signal app_arg_1 : boolean; signal result_1 : signed(63 downto 0); begin -- blockRam begin packetprocessor_blockram_blockram : block signal ram : packetprocessor_types.array_of_unsigned_8(0 to 2047) := (packetprocessor_types.array_of_unsigned_8'(0 to 2048-1 => to_unsigned(0,8) )); signal dout : unsigned(7 downto 0); signal rd_0 : integer range 0 to 2048 - 1; signal wr : integer range 0 to 2048 - 1; begin rd_0 <= to_integer(result_1) -- pragma translate_off mod 2048 -- pragma translate_on ; wr <= to_integer(app_arg_0) -- pragma translate_off mod 2048 -- pragma translate_on ; blockram_sync : process(system1000) begin if rising_edge(system1000) then if app_arg_1 then ram(wr) <= app_arg; end if; dout <= ram(rd_0); end if; end process; result <= dout; end block; -- blockRam end x2 <= x1.tup2_0_sel0; wild2_app_arg <= signed(std_logic_vector(resize(x2,64))); y <= x1.tup2_0_sel1; wild2 <= wild2_app_arg; x1 <= (tup2_0_sel0 => unsigned(wrm(18 downto 8)) ,tup2_0_sel1 => unsigned(wrm(7 downto 0))); result_0 <= wild2; wild_app_arg <= signed(std_logic_vector(resize(rd,64))); case_alt <= y; case_alt_0 <= result_0; wild <= wild_app_arg; with (wrm(19 downto 19)) select app_arg <= unsigned'(0 to 7 => 'X') when "0", case_alt when others; with (wrm(19 downto 19)) select app_arg_0 <= signed'(0 to 63 => 'X') when "0", case_alt_0 when others; with (wrm(19 downto 19)) select app_arg_1 <= false when "0", true when others; result_1 <= wild; end;

-------------------------------------------------------------------------------- -- -- BLK MEM GEN v6_3 Core - Synthesizable Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: bmg_tb_synth.vhd -- -- Description: -- Synthesizable Testbench -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_MISC.ALL; LIBRARY STD; USE STD.TEXTIO.ALL; LIBRARY unisim; USE unisim.vcomponents.ALL; LIBRARY work; USE work.ALL; USE work.BMG_TB_PKG.ALL; ENTITY BMG_TB IS PORT( CLK_IN : IN STD_LOGIC; CLKB_IN : IN STD_LOGIC; RESET_IN : IN STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA ); END ENTITY; ARCHITECTURE BMG_TB_ARCH OF BMG_TB IS COMPONENT RAM_WRITE_top PORT ( --Inputs - Port A WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(255 DOWNTO 0); DOUTA : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); CLKA : IN STD_LOGIC; --Inputs - Port B WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0); DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); CLKB : IN STD_LOGIC ); END COMPONENT; SIGNAL CLKA: STD_LOGIC := '0'; SIGNAL RSTA: STD_LOGIC := '0'; SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA: STD_LOGIC_VECTOR(255 DOWNTO 0) := (OTHERS => '0'); SIGNAL DOUTA: STD_LOGIC_VECTOR(255 DOWNTO 0); SIGNAL CLKB: STD_LOGIC := '0'; SIGNAL RSTB: STD_LOGIC := '0'; SIGNAL WEB: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRB: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINB: STD_LOGIC_VECTOR( 7 DOWNTO 0) := (OTHERS => '0'); SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL CHECKER_EN : STD_LOGIC:='0'; SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); SIGNAL clk_in_i: STD_LOGIC; SIGNAL RESET_SYNC_R1 : STD_LOGIC; SIGNAL RESET_SYNC_R2 : STD_LOGIC; SIGNAL RESET_SYNC_R3 : STD_LOGIC; SIGNAL clkb_in_i: STD_LOGIC; SIGNAL RESETB_SYNC_R1 : STD_LOGIC; SIGNAL RESETB_SYNC_R2 : STD_LOGIC; SIGNAL RESETB_SYNC_R3 : STD_LOGIC; SIGNAL ITER_R0 : STD_LOGIC := '0'; SIGNAL ITER_R1 : STD_LOGIC := '0'; SIGNAL ITER_R2 : STD_LOGIC := '0'; SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); BEGIN clk_buf: bufg PORT map( i => CLK_IN, o => clk_in_i ); CLKA <= clk_in_i; clkb_buf: bufg PORT map( i => CLKB_IN, o => clkb_in_i ); CLKB <= clkb_in_i; RSTA <= RESET_IN; PROCESS(clk_in_i) BEGIN IF(RISING_EDGE(clk_in_i)) THEN RESET_SYNC_R1 <= RESET_IN; RESET_SYNC_R2 <= RESET_SYNC_R1; RESET_SYNC_R3 <= RESET_SYNC_R2; END IF; END PROCESS; RSTB <= RESET_IN; PROCESS(clkb_in_i) BEGIN IF(RISING_EDGE(clkb_in_i)) THEN RESETB_SYNC_R1 <= RESET_IN; RESETB_SYNC_R2 <= RESETB_SYNC_R1; RESETB_SYNC_R3 <= RESETB_SYNC_R2; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ISSUE_FLAG_STATUS<= (OTHERS => '0'); ELSE ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; END IF; END IF; END PROCESS; STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; BMG_DATA_CHECKER_INST_A: ENTITY work.CHECKER GENERIC MAP ( WRITE_WIDTH => 256, READ_WIDTH => 256 ) PORT MAP ( CLK => CLKA, RST => RSTA, EN => CHECK_DATA_TDP(0), DATA_IN => DOUTA, STATUS => ISSUE_FLAG(0) ); BMG_DATA_CHECKER_INST_B: ENTITY work.CHECKER GENERIC MAP ( WRITE_WIDTH => 8, READ_WIDTH => 8 ) PORT MAP ( CLK => CLKB, RST => RSTB, EN => CHECK_DATA_TDP(1), DATA_IN => DOUTB, STATUS => ISSUE_FLAG(1) ); BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN PORT MAP( CLKA => CLKA, CLKB => CLKB, TB_RST => RSTA, ADDRA => ADDRA, DINA => DINA, WEA => WEA, WEB => WEB, ADDRB => ADDRB, DINB => DINB, CHECK_DATA => CHECK_DATA_TDP ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STATUS(8) <= '0'; iter_r2 <= '0'; iter_r1 <= '0'; iter_r0 <= '0'; ELSE STATUS(8) <= iter_r2; iter_r2 <= iter_r1; iter_r1 <= iter_r0; iter_r0 <= STIMULUS_FLOW(8); END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STIMULUS_FLOW <= (OTHERS => '0'); ELSIF(WEA(0)='1') THEN STIMULUS_FLOW <= STIMULUS_FLOW+1; END IF; END IF; END PROCESS; BMG_PORT: RAM_WRITE_top PORT MAP ( --Port A WEA => WEA, ADDRA => ADDRA, DINA => DINA, DOUTA => DOUTA, CLKA => CLKA, --Port B WEB => WEB, ADDRB => ADDRB, DINB => DINB, DOUTB => DOUTB, CLKB => CLKB ); END ARCHITECTURE;

------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package caph_processing_component is component dy_net port ( i_f: out std_logic; i: in std_logic_vector(9 downto 0); i_wr: in std_logic; o_e: out std_logic; o: out std_logic_vector(9 downto 0); o_rd: in std_logic; clock: in std_logic; reset: in std_logic ); end component; component conv33_port_net is port ( i_f: out std_logic; i: in std_logic_vector(9 downto 0); i_wr: in std_logic; k0_f: out std_logic; k0: in std_logic_vector(15 downto 0); k0_wr: in std_logic; k1_f: out std_logic; k1: in std_logic_vector(15 downto 0); k1_wr: in std_logic; k2_f: out std_logic; k2: in std_logic_vector(15 downto 0); k2_wr: in std_logic; k3_f: out std_logic; k3: in std_logic_vector(15 downto 0); k3_wr: in std_logic; k4_f: out std_logic; k4: in std_logic_vector(15 downto 0); k4_wr: in std_logic; k5_f: out std_logic; k5: in std_logic_vector(15 downto 0); k5_wr: in std_logic; k6_f: out std_logic; k6: in std_logic_vector(15 downto 0); k6_wr: in std_logic; k7_f: out std_logic; k7: in std_logic_vector(15 downto 0); k7_wr: in std_logic; k8_f: out std_logic; k8: in std_logic_vector(15 downto 0); k8_wr: in std_logic; n_f: out std_logic; n: in std_logic_vector(7 downto 0); n_wr: in std_logic; o_e: out std_logic; o: out std_logic_vector(9 downto 0); o_rd: in std_logic; clock: in std_logic; reset: in std_logic ); end component; component dx_net port ( w3_f: out std_logic; w3: in std_logic_vector(9 downto 0); w3_wr: in std_logic; w6_e: out std_logic; w6: out std_logic_vector(9 downto 0); w6_rd: in std_logic; clock: in std_logic; reset: in std_logic ); end component; component inv_net is port ( w3_f: out std_logic; w3: in std_logic_vector(9 downto 0); w3_wr: in std_logic; w6_e: out std_logic; w6: out std_logic_vector(9 downto 0); w6_rd: in std_logic; clock: in std_logic; reset: in std_logic ); end component; component conv_net is port ( w8_f: out std_logic; w8: in std_logic_vector(9 downto 0); w8_wr: in std_logic; w15_e: out std_logic; w15: out std_logic_vector(9 downto 0); w15_rd: in std_logic; clock: in std_logic; reset: in std_logic ); end component; component port_test_net port ( w4_f: out std_logic; w4: in std_logic_vector(9 downto 0); w4_wr: in std_logic; w6_f: out std_logic; w6: in std_logic_vector(7 downto 0); w6_wr: in std_logic; w9_e: out std_logic; w9: out std_logic_vector(9 downto 0); w9_rd: in std_logic; clock: in std_logic; reset: in std_logic ); end component; end caph_processing_component;

package STRSYN is attribute SigDir : string; attribute SigType : string; attribute SigBias : string; end STRSYN; entity op is port ( terminal in1: electrical; terminal in2: electrical; terminal out1: electrical; terminal vbias4: electrical; terminal gnd: electrical; terminal vdd: electrical; terminal vbias2: electrical; terminal vbias1: electrical; terminal vbias3: electrical); end op; architecture simple of op is -- Attributes for Ports attribute SigDir of in1:terminal is "input"; attribute SigType of in1:terminal is "voltage"; attribute SigDir of in2:terminal is "input"; attribute SigType of in2:terminal is "voltage"; attribute SigDir of out1:terminal is "output"; attribute SigType of out1:terminal is "voltage"; attribute SigDir of vbias4:terminal is "reference"; attribute SigType of vbias4:terminal is "voltage"; attribute SigDir of gnd:terminal is "reference"; attribute SigType of gnd:terminal is "current"; attribute SigBias of gnd:terminal is "negative"; attribute SigDir of vdd:terminal is "reference"; attribute SigType of vdd:terminal is "current"; attribute SigBias of vdd:terminal is "positive"; attribute SigDir of vbias2:terminal is "reference"; attribute SigType of vbias2:terminal is "voltage"; attribute SigDir of vbias1:terminal is "reference"; attribute SigType of vbias1:terminal is "voltage"; attribute SigDir of vbias3:terminal is "reference"; attribute SigType of vbias3:terminal is "voltage"; terminal net1: electrical; terminal net2: electrical; terminal net3: electrical; terminal net4: electrical; terminal net5: electrical; terminal net6: electrical; terminal net7: electrical; terminal net8: electrical; begin subnet0_subnet0_m1 : entity nmos(behave) generic map( L => Ldiff_0, W => Wdiff_0, scope => private ) port map( D => net2, G => in1, S => net4 ); subnet0_subnet0_m2 : entity nmos(behave) generic map( L => Ldiff_0, W => Wdiff_0, scope => private ) port map( D => net1, G => in2, S => net4 ); subnet0_subnet0_m3 : entity nmos(behave) generic map( L => LBias, W => W_0 ) port map( D => net4, G => vbias4, S => gnd ); subnet0_subnet0_m4 : entity nmos(behave) generic map( L => Ldiff_0, W => Wdiff_0, scope => private ) port map( D => net5, G => in1, S => net4 ); subnet0_subnet0_m5 : entity nmos(behave) generic map( L => Ldiff_0, W => Wdiff_0, scope => private ) port map( D => net5, G => in2, S => net4 ); subnet0_subnet0_m6 : entity pmos(behave) generic map( L => Lcmdiffp_0, W => Wcmdiffp_0, scope => private ) port map( D => net5, G => net5, S => vdd ); subnet0_subnet0_m7 : entity pmos(behave) generic map( L => Lcmdiffp_0, W => Wcmdiffp_0, scope => private ) port map( D => net5, G => net5, S => vdd ); subnet0_subnet0_m8 : entity pmos(behave) generic map( L => Lcmdiffp_0, W => Wcmdiffp_0, scope => private ) port map( D => net1, G => net5, S => vdd ); subnet0_subnet0_m9 : entity pmos(behave) generic map( L => Lcmdiffp_0, W => Wcmdiffp_0, scope => private ) port map( D => net2, G => net5, S => vdd ); subnet0_subnet1_m1 : entity nmos(behave) generic map( L => Lsrc, W => Wsrc_2, scope => Wprivate, symmetry_scope => sym_7 ) port map( D => net3, G => net1, S => gnd ); subnet0_subnet2_m1 : entity nmos(behave) generic map( L => Lsrc, W => Wsrc_2, scope => Wprivate, symmetry_scope => sym_7 ) port map( D => out1, G => net2, S => gnd ); subnet0_subnet3_m1 : entity pmos(behave) generic map( L => LBias, W => Wcmcasc_1, scope => Wprivate ) port map( D => net3, G => vbias2, S => net6 ); subnet0_subnet3_m2 : entity pmos(behave) generic map( L => Lcm_1, W => Wcm_1, scope => private ) port map( D => net6, G => net3, S => vdd ); subnet0_subnet3_m3 : entity pmos(behave) generic map( L => Lcm_1, W => Wcmout_1, scope => private ) port map( D => net7, G => net3, S => vdd ); subnet0_subnet3_m4 : entity pmos(behave) generic map( L => LBias, W => Wcmcasc_1, scope => Wprivate ) port map( D => out1, G => vbias2, S => net7 ); subnet1_subnet0_m1 : entity pmos(behave) generic map( L => LBias, W => (pfak)*(WBias) ) port map( D => vbias1, G => vbias1, S => vdd ); subnet1_subnet0_m2 : entity pmos(behave) generic map( L => (pfak)*(LBias), W => (pfak)*(WBias) ) port map( D => vbias2, G => vbias2, S => vbias1 ); subnet1_subnet0_i1 : entity idc(behave) generic map( dc => 1.145e-05 ) port map( P => vdd, N => vbias3 ); subnet1_subnet0_m3 : entity nmos(behave) generic map( L => (pfak)*(LBias), W => WBias ) port map( D => vbias3, G => vbias3, S => vbias4 ); subnet1_subnet0_m4 : entity nmos(behave) generic map( L => LBias, W => WBias ) port map( D => vbias2, G => vbias3, S => net8 ); subnet1_subnet0_m5 : entity nmos(behave) generic map( L => LBias, W => WBias ) port map( D => vbias4, G => vbias4, S => gnd ); subnet1_subnet0_m6 : entity nmos(behave) generic map( L => LBias, W => WBias ) port map( D => net8, G => vbias4, S => gnd ); end simple;

library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity shiftreg_nov is port( clock: in std_logic; input: in std_logic_vector(0 downto 0); output: out std_logic_vector(0 downto 0) ); end shiftreg_nov; architecture behaviour of shiftreg_nov is constant st0: std_logic_vector(2 downto 0) := "000"; constant st1: std_logic_vector(2 downto 0) := "100"; constant st2: std_logic_vector(2 downto 0) := "011"; constant st3: std_logic_vector(2 downto 0) := "111"; constant st4: std_logic_vector(2 downto 0) := "010"; constant st5: std_logic_vector(2 downto 0) := "110"; constant st6: std_logic_vector(2 downto 0) := "001"; constant st7: std_logic_vector(2 downto 0) := "101"; signal current_state, next_state: std_logic_vector(2 downto 0); begin process(clock) begin if rising_edge(clock) then current_state <= next_state; end if; end process; process(input, current_state) begin next_state <= "---"; output <= "-"; case current_state is when st0 => if std_match(input, "0") then next_state <= st0; output <= "0"; elsif std_match(input, "1") then next_state <= st4; output <= "0"; end if; when st1 => if std_match(input, "0") then next_state <= st0; output <= "1"; elsif std_match(input, "1") then next_state <= st4; output <= "1"; end if; when st2 => if std_match(input, "0") then next_state <= st1; output <= "0"; elsif std_match(input, "1") then next_state <= st5; output <= "0"; end if; when st3 => if std_match(input, "0") then next_state <= st1; output <= "1"; elsif std_match(input, "1") then next_state <= st5; output <= "1"; end if; when st4 => if std_match(input, "0") then next_state <= st2; output <= "0"; elsif std_match(input, "1") then next_state <= st6; output <= "0"; end if; when st5 => if std_match(input, "0") then next_state <= st2; output <= "1"; elsif std_match(input, "1") then next_state <= st6; output <= "1"; end if; when st6 => if std_match(input, "0") then next_state <= st3; output <= "0"; elsif std_match(input, "1") then next_state <= st7; output <= "0"; end if; when st7 => if std_match(input, "0") then next_state <= st3; output <= "1"; elsif std_match(input, "1") then next_state <= st7; output <= "1"; end if; when others => next_state <= "---"; output <= "-"; end case; end process; end behaviour;

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.tl_flat_memory_model_pkg.all; use work.mem_bus_pkg.all; use work.cart_slot_pkg.all; use work.io_bus_pkg.all; use work.io_bus_bfm_pkg.all; use work.command_if_pkg.all; entity harness_v5 is end harness_v5; architecture tb of harness_v5 is constant c_uart_divisor : natural := 434; signal PHI2 : std_logic := '0'; signal RSTn : std_logic := 'H'; signal DOTCLK : std_logic := '1'; signal BUFFER_ENn : std_logic := '1'; signal BA : std_logic := '0'; signal DMAn : std_logic := '1'; signal EXROMn : std_logic; signal GAMEn : std_logic; signal ROMHn : std_logic := '1'; signal ROMLn : std_logic := '1'; signal IO1n : std_logic := '1'; signal IO2n : std_logic := '1'; signal IRQn : std_logic := '1'; signal NMIn : std_logic := '1'; signal SDRAM_CSn : std_logic; signal SDRAM_RASn : std_logic; signal SDRAM_CASn : std_logic; signal SDRAM_WEn : std_logic; signal SDRAM_CKE : std_logic; signal SDRAM_CLK : std_logic; signal SDRAM_DQM : std_logic; signal LB_ADDR : std_logic_vector(14 downto 0); signal LB_DATA : std_logic_vector(7 downto 0) := X"00"; signal logic_SDRAM_CSn : std_logic; signal logic_SDRAM_RASn : std_logic; signal logic_SDRAM_CASn : std_logic; signal logic_SDRAM_WEn : std_logic; signal logic_SDRAM_CKE : std_logic; signal logic_SDRAM_CLK : std_logic; signal logic_SDRAM_DQM : std_logic; signal logic_LB_ADDR : std_logic_vector(14 downto 0); signal PWM_OUT : std_logic_vector(1 downto 0); signal IEC_ATN : std_logic := '1'; signal IEC_DATA : std_logic := '1'; signal IEC_CLOCK : std_logic := '1'; signal IEC_RESET : std_logic := '1'; signal IEC_SRQ_IN : std_logic := '1'; signal DISK_ACTn : std_logic; -- activity LED signal CART_LEDn : std_logic; signal SDACT_LEDn : std_logic; signal MOTOR_LEDn : std_logic; signal UART_TXD : std_logic; signal UART_RXD : std_logic := '1'; signal SD_SSn : std_logic; signal SD_CLK : std_logic; signal SD_MOSI : std_logic; signal SD_MISO : std_logic := '1'; signal SD_WP : std_logic := '1'; signal SD_CARDDETn : std_logic := '1'; signal BUTTON : std_logic_vector(2 downto 0) := "000"; signal SLOT_ADDR : std_logic_vector(15 downto 0); signal SLOT_DATA : std_logic_vector(7 downto 0); signal RWn : std_logic := '1'; signal CAS_MOTOR : std_logic := '1'; signal CAS_SENSE : std_logic := '0'; signal CAS_READ : std_logic := '0'; signal CAS_WRITE : std_logic := '0'; signal RTC_CS : std_logic; signal RTC_SCK : std_logic; signal RTC_MOSI : std_logic; signal RTC_MISO : std_logic := '1'; signal FLASH_CSn : std_logic; signal FLASH_SCK : std_logic; signal FLASH_MOSI : std_logic; signal FLASH_MISO : std_logic := '1'; signal ULPI_CLOCK : std_logic := '0'; signal ULPI_RESET : std_logic := '0'; signal ULPI_NXT : std_logic := '0'; signal ULPI_STP : std_logic; signal ULPI_DIR : std_logic := '0'; signal ULPI_DATA : std_logic_vector(7 downto 0) := (others => 'H'); signal sys_clock : std_logic := '0'; signal sys_reset : std_logic := '0'; signal sys_shifted : std_logic := '0'; signal rx_char : std_logic_vector(7 downto 0); signal rx_char_d : std_logic_vector(7 downto 0); signal rx_ack : std_logic; signal tx_char : std_logic_vector(7 downto 0) := X"00"; signal tx_done : std_logic; signal do_tx : std_logic := '0'; shared variable dram : h_mem_object; shared variable ram : h_mem_object; -- shared variable rom : h_mem_object; -- shared variable bram : h_mem_object; -- memory controller interconnect signal memctrl_inhibit : std_logic := '0'; signal mem_req : t_mem_req; signal mem_resp : t_mem_resp; signal mem_req_cached : t_mem_burst_req; signal mem_resp_cached : t_mem_burst_resp; signal io_req : t_io_req; signal io_resp : t_io_resp; -- cache monitoring signal hit_count : unsigned(31 downto 0); signal miss_count : unsigned(31 downto 0); signal hit_ratio : real := 0.0; begin mut: entity work.ultimate_logic generic map ( g_simulation => true, g_uart => true, g_drive_1541 => true, g_drive_1541_2 => true, g_hardware_gcr => true, g_cartridge => true, g_command_intf => true, g_stereo_sid => true, g_ram_expansion => true, g_extended_reu => true, g_hardware_iec => true, g_c2n_streamer => true, g_c2n_recorder => true, g_drive_sound => true, g_rtc_chip => true, g_rtc_timer => true, g_usb_host => true, g_spi_flash => true ) port map ( sys_clock => sys_clock, sys_reset => sys_reset, PHI2 => PHI2, DOTCLK => DOTCLK, RSTn => RSTn, BUFFER_ENn => BUFFER_ENn, SLOT_ADDR => SLOT_ADDR, SLOT_DATA => SLOT_DATA, RWn => RWn, BA => BA, DMAn => DMAn, EXROMn => EXROMn, GAMEn => GAMEn, ROMHn => ROMHn, ROMLn => ROMLn, IO1n => IO1n, IO2n => IO2n, IRQn => IRQn, NMIn => NMIn, -- local bus side mem_inhibit => memctrl_inhibit, --memctrl_idle => memctrl_idle, mem_req => mem_req, mem_resp => mem_resp, -- io bus for simulation sim_io_req => io_req, sim_io_resp => io_resp, -- PWM outputs (for audio) PWM_OUT => PWM_OUT, -- IEC bus IEC_ATN => IEC_ATN, IEC_DATA => IEC_DATA, IEC_CLOCK => IEC_CLOCK, IEC_RESET => IEC_RESET, IEC_SRQ_IN => IEC_SRQ_IN, DISK_ACTn => DISK_ACTn, -- activity LED CART_LEDn => CART_LEDn, SDACT_LEDn => SDACT_LEDn, MOTOR_LEDn => MOTOR_LEDn, -- Debug UART UART_TXD => UART_TXD, UART_RXD => UART_RXD, -- SD Card Interface SD_SSn => SD_SSn, SD_CLK => SD_CLK, SD_MOSI => SD_MOSI, SD_MISO => SD_MISO, SD_CARDDETn => SD_CARDDETn, -- Cassette Interface CAS_MOTOR => CAS_MOTOR, CAS_SENSE => CAS_SENSE, CAS_READ => CAS_READ, CAS_WRITE => CAS_WRITE, -- RTC Interface RTC_CS => RTC_CS, RTC_SCK => RTC_SCK, RTC_MOSI => RTC_MOSI, RTC_MISO => RTC_MISO, -- Flash Interface FLASH_CSn => FLASH_CSn, FLASH_SCK => FLASH_SCK, FLASH_MOSI => FLASH_MOSI, FLASH_MISO => FLASH_MISO, -- USB Interface (ULPI) ULPI_CLOCK => ULPI_CLOCK, ULPI_RESET => ULPI_RESET, ULPI_NXT => ULPI_NXT, ULPI_STP => ULPI_STP, ULPI_DIR => ULPI_DIR, ULPI_DATA => ULPI_DATA, -- Buttons BUTTON => BUTTON ); i_cache: entity work.dm_cache port map ( clock => sys_clock, reset => sys_reset, client_req => mem_req, client_resp => mem_resp, mem_req => mem_req_cached, mem_resp => mem_resp_cached, hit_count => hit_count, miss_count => miss_count ); hit_ratio <= real(to_integer(hit_count)) / real(to_integer(miss_count) + to_integer(hit_count) + 1); i_memctrl: entity work.ext_mem_ctrl_v5_sdr generic map ( g_simulation => true, A_Width => 15 ) port map ( clock => sys_clock, clk_shifted => sys_shifted, reset => sys_reset, inhibit => '0', --memctrl_inhibit, is_idle => open, --memctrl_idle, req => mem_req_cached, resp => mem_resp_cached, SDRAM_CSn => logic_SDRAM_CSn, SDRAM_RASn => logic_SDRAM_RASn, SDRAM_CASn => logic_SDRAM_CASn, SDRAM_WEn => logic_SDRAM_WEn, SDRAM_CKE => logic_SDRAM_CKE, SDRAM_CLK => logic_SDRAM_CLK, MEM_A => logic_LB_ADDR, MEM_D => LB_DATA ); -- clock to out.. for data it is inside of the memory controller, because it's bidirectional SDRAM_CSn <= transport logic_SDRAM_CSn after 4.9 ns; SDRAM_RASn <= transport logic_SDRAM_RASn after 4.9 ns; SDRAM_CASn <= transport logic_SDRAM_CASn after 4.9 ns; SDRAM_WEn <= transport logic_SDRAM_WEn after 4.9 ns; SDRAM_CKE <= transport logic_SDRAM_CKE after 4.9 ns; SDRAM_CLK <= transport logic_SDRAM_CLK after 4.9 ns; LB_ADDR <= transport logic_LB_ADDR after 4.9 ns; sys_clock <= not sys_clock after 10 ns; -- 50 MHz sys_reset <= '1', '0' after 100 ns; sys_shifted <= transport sys_clock after 15 ns; -- 270 degrees ULPI_CLOCK <= not ULPI_CLOCK after 8.333 ns; -- 60 MHz ULPI_RESET <= '1', '0' after 100 ns; PHI2 <= not PHI2 after 507.5 ns; -- 0.98525 MHz RSTn <= '0', 'H' after 6 us, '0' after 100 us, 'H' after 105 us; i_ulpi_phy: entity work.ulpi_phy_bfm generic map ( g_rx_interval => 100000 ) port map ( clock => ULPI_CLOCK, reset => ULPI_RESET, ULPI_DATA => ULPI_DATA, ULPI_DIR => ULPI_DIR, ULPI_NXT => ULPI_NXT, ULPI_STP => ULPI_STP ); i_io_bfm: entity work.io_bus_bfm generic map ( g_name => "io_bfm" ) port map ( clock => sys_clock, req => io_req, resp => io_resp ); process begin bind_mem_model("intram", ram); bind_mem_model("dram", dram); load_memory("../../software/1st_boot/result/1st_boot.bin", ram, X"00000000"); -- 1st boot will try to load the 2nd bootloader and application from flash. In simulation this is a cumbersome -- process. It would work with a good model of the serial spi flash, but since it is not included in the public -- archive, you need to create a special boot image that just jumps to 0x20000 and load the application here to dram: load_memory("../../software/ultimate/result/ultimate.bin", dram, X"00020000"); wait; end process; SLOT_DATA <= (others => 'H'); ROMHn <= '1'; ROMLn <= not PHI2 after 50 ns; IO1n <= '1'; IO2n <= '1'; process begin SLOT_ADDR <= X"D400"; RWn <= '1'; while true loop wait until PHI2 = '0'; --SLOT_ADDR(8 downto 0) <= std_logic_vector(unsigned(SLOT_ADDR(8 downto 0)) + 1); SLOT_ADDR <= std_logic_vector(unsigned(SLOT_ADDR) + 1); RWn <= '1'; wait until PHI2 = '0'; RWn <= '0'; end loop; end process; process begin BA <= '1'; for i in 0 to 100 loop wait until PHI2='0'; end loop; BA <= '0'; for i in 0 to 10 loop wait until PHI2='0'; end loop; end process; dram_bfm: entity work.dram_model_8 generic map( g_given_name => "dram", g_cas_latency => 2, g_burst_len_r => 4, g_burst_len_w => 4, g_column_bits => 10, g_row_bits => 13, g_bank_bits => 2 ) port map ( CLK => SDRAM_CLK, CKE => SDRAM_CKE, A => LB_ADDR(12 downto 0), BA => LB_ADDR(14 downto 13), CSn => SDRAM_CSn, RASn => SDRAM_RASn, CASn => SDRAM_CASn, WEn => SDRAM_WEn, DQM => SDRAM_DQM, DQ => LB_DATA); i_rx: entity work.rx generic map (c_uart_divisor) port map ( clk => sys_clock, reset => sys_reset, rxd => UART_TXD, rxchar => rx_char, rx_ack => rx_ack ); i_tx: entity work.tx generic map (c_uart_divisor) port map ( clk => sys_clock, reset => sys_reset, dotx => do_tx, txchar => tx_char, done => tx_done, txd => UART_RXD ); process(sys_clock) begin if rising_edge(sys_clock) then if rx_ack='1' then rx_char_d <= rx_char; end if; end if; end process; -- procedure register_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object); -- procedure bind_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object); -- procedure io_read(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0)); -- procedure io_write(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0)); -- constant c_cart_c64_mode : unsigned(3 downto 0) := X"0"; -- constant c_cart_c64_stop : unsigned(3 downto 0) := X"1"; -- constant c_cart_c64_stop_mode : unsigned(3 downto 0) := X"2"; -- constant c_cart_c64_clock_detect : unsigned(3 downto 0) := X"3"; -- constant c_cart_cartridge_rom_base : unsigned(3 downto 0) := X"4"; -- constant c_cart_cartridge_type : unsigned(3 downto 0) := X"5"; -- constant c_cart_cartridge_kill : unsigned(3 downto 0) := X"6"; -- constant c_cart_reu_enable : unsigned(3 downto 0) := X"8"; -- constant c_cart_reu_size : unsigned(3 downto 0) := X"9"; -- constant c_cart_swap_buttons : unsigned(3 downto 0) := X"A"; -- constant c_cart_ethernet_enable : unsigned(3 downto 0) := X"F"; process variable io : p_io_bus_bfm_object; begin wait until sys_reset='0'; wait until sys_clock='1'; bind_io_bus_bfm("io_bfm", io); io_write(io, X"40000" + c_cart_c64_mode, X"04"); -- reset io_write(io, X"40000" + c_cart_cartridge_type, X"06"); -- retro io_write(io, X"40000" + c_cart_c64_mode, X"08"); -- unreset io_write(io, X"44000" + c_cif_io_slot_base, X"7E"); io_write(io, X"44000" + c_cif_io_slot_enable, X"01"); wait for 6 us; wait until sys_clock='1'; io_write(io, X"42002", X"42"); wait; end process; process procedure send_char(i: std_logic_vector(7 downto 0)) is begin if tx_done /= '1' then wait until tx_done = '1'; end if; wait until sys_clock='1'; tx_char <= i; do_tx <= '1'; wait until tx_done = '0'; wait until sys_clock='1'; do_tx <= '0'; end procedure; procedure send_string(i : string) is variable b : std_logic_vector(7 downto 0); begin for n in i'range loop b := std_logic_vector(to_unsigned(character'pos(i(n)), 8)); send_char(b); end loop; send_char(X"0d"); send_char(X"0a"); end procedure; begin wait for 2 ms; --send_string("wd 4005000 12345678"); send_string("run"); -- send_string("m 100000"); -- send_string("w 400000F 4"); wait; end process; -- check timing data process(PHI2) begin if falling_edge(PHI2) then assert SLOT_DATA'last_event >= 189 ns report "Timing error on C64 bus." severity error; end if; end process; end tb;

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity D6_C1 is port( rst : in STD_LOGIC; sel : in STD_LOGIC; clk : in STD_LOGIC; seg1 : out STD_LOGIC_VECTOR(7 downto 0);--hang don vi seg2 : out STD_LOGIC_VECTOR(7 downto 0)--hang chuc ); end D6_C1; architecture D6_C1 of D6_C1 is begin process(rst,clk,sel) variable temp1:integer range 0 to 10; variable temp2:integer range 0 to 10; begin if (rst='1') then temp1:=0; temp2:=0; elsif (rising_edge(clk)) then if (sel='1') then if (temp1=10) then temp1:=0; temp2:=temp2+1; if (temp2=10) then temp2:=0; end if; else temp1:=temp1+1; end if; elsif (sel='0') then if(temp1=0) then temp1:=9; temp2:=temp2-1; if (temp2=0) then temp2:=9; end if; else temp1:=temp1-1; end if; end if; end if; case temp1 is when 0 => seg1<= x"C0"; when 1 => seg1<= x"F9"; when 2 => seg1<= x"A4"; when 3 => seg1<= x"B0"; when 4 => seg1<= x"99"; when 5 => seg1<= x"92"; when 6 => seg1<= x"82"; when 7 => seg1<= x"F8"; when 8 => seg1<= x"80"; when 9 => seg1<= x"90"; when others =>NULL; end case; case temp2 is when 0 => seg2<= x"C0"; when 1 => seg2<= x"F9"; when 2 => seg2<= x"A4"; when 3 => seg2<= x"B0"; when 4 => seg2<= x"99"; when 5 => seg2<= x"92"; when 6 => seg2<= x"82"; when 7 => seg2<= x"F8"; when 8 => seg2<= x"80"; when 9 => seg2<= x"90"; when others =>NULL; end case; end process; end D6_C1; -- rst= 10kHz; sel=50Khz; clk=20Mhz;

------------------------------------------------------------------------------- -- Title : Commutation control via Hall sensors ------------------------------------------------------------------------------- -- Author : Fabian Greif <[email protected]> -- Company : Roboterclub Aachen e.V. -- Platform : Spartan 3 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.motor_control_pkg.all; package commutation_pkg is component commutation is port ( driver_stage_p : out bldc_driver_stage_type; hall_p : in hall_sensor_type; pwm_p : in half_bridge_type; dir_p : in std_logic; sd_p : in std_logic; clk : in std_logic); end component commutation; end commutation_pkg; ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.commutation_pkg.all; use work.motor_control_pkg.all; entity commutation is port ( driver_stage_p : out bldc_driver_stage_type; -- Driver Stage of 3 half bridges hall_p : in hall_sensor_type; -- Hall Sensors pwm_p : in half_bridge_type; dir_p : in std_logic; -- Direction sd_p : in std_logic; -- Shutdown clk : in std_logic ); end commutation; architecture behavioral of commutation is type commutation_type is record hall_1r : std_logic_vector(2 downto 0); hall_2r : std_logic_vector(2 downto 0); driver : bldc_driver_stage_type; end record; signal r, rin : commutation_type; begin seq_proc : process(clk) begin if rising_edge(clk) then r <= rin; end if; end process seq_proc; comb_proc : process(dir_p, hall_p.a, hall_p.b, hall_p.c, pwm_p.high, pwm_p.low, r, r.hall_1r, r.hall_2r, r.driver.a.high, r.driver.a.low, r.driver.b.high, r.driver.b.low, r.driver.c.high, r.driver.c.low, sd_p) variable v : commutation_type; variable index : integer range 0 to 6; begin v := r; -- synchronise Hall sensors inputs v.hall_1r := hall_p.a & hall_p.b & hall_p.c; v.hall_2r := r.hall_1r; if dir_p = '0' then case r.hall_2r is when "101" => index := 1; when "100" => index := 2; when "110" => index := 3; when "010" => index := 4; when "011" => index := 5; when "001" => index := 6; when others => index := 0; end case; else case r.hall_2r is when "101" => index := 4; when "100" => index := 5; when "110" => index := 6; when "010" => index := 1; when "011" => index := 2; when "001" => index := 3; when others => index := 0; end case; end if; case index is when 1 => v.driver := (a => (pwm_p.high, pwm_p.low), b => ('0', '1'), c => ('0', '0')); when 2 => v.driver := (a => (pwm_p.high, pwm_p.low), b => ('0', '0'), c => ('0', '1')); when 3 => v.driver := (a => ('0', '0'), b => (pwm_p.high, pwm_p.low), c => ('0', '1')); when 4 => v.driver := (a => ('0', '1'), b => (pwm_p.high, pwm_p.low), c => ('0', '0')); when 5 => v.driver := (a => ('0', '1'), b => ('0', '0'), c => (pwm_p.high, pwm_p.low)); when 6 => v.driver := (a => ('0', '0'), b => ('0', '1'), c => (pwm_p.high, pwm_p.low)); when others => -- Error in the readings of the Hall-Sensors => Disable PWM v.driver := (a => ('0', '0'), b => ('0', '0'), c => ('0', '0')); end case; if sd_p = '1' then v.driver := (a => ('0', '0'), b => ('0', '0'), c => ('0', '0')); end if; rin <= v; end process comb_proc; driver_stage_p <= r.driver; end behavioral;

------------------------------------------------------------------------------- --! @file ab.vhd --! @author Johannes Walter <[email protected]> --! @copyright CERN TE-EPC-CCE --! @date 2014-07-08 --! @brief Analogue board control and filters. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.ab_pkg.all; use work.nf_pkg.all; use work.ads1281_filter_pkg.all; --! @brief Entity declaration of ab --! @details --! This component controls the analogue board switches, DAC and ADCs. It --! also provides FIR filter implementations for the ADCs and has an internal --! pattern generator for test purposes. entity ab is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Analogue board interface --! @{ --! Inputs ab_i : in ab_in_t; --! Outputs ab_o : out ab_out_t; --! @} --! @name Internal interface --! @{ --! Millisecond strobe ms_strobe_i : in std_ulogic; --! Millisecond strobe indicating start of cycle ms_0_strobe_i : in std_ulogic; --! Commands command_i : in nf_command_t; --! SEFI detector sefi_o : out std_ulogic_vector(5 downto 0); --! Voltage reference when ramping down pf_vref_i : in std_ulogic_vector(15 downto 0); --! Voltage reference enable pf_vref_en_i : in std_ulogic; --! Voltage reference override pf_vref_ovr_i : in std_ulogic; --! @} --! @name ADC results --! @{ --! ADC VS result adc_vs_o : out std_ulogic_vector(23 downto 0); --! ADC VS result enable adc_vs_en_o : out std_ulogic; --! ADC IA result adc_ia_o : out std_ulogic_vector(23 downto 0); --! ADC IA result enable adc_ia_en_o : out std_ulogic; --! ADC IB result adc_ib_o : out std_ulogic_vector(23 downto 0); --! ADC IB result enable adc_ib_en_o : out std_ulogic; --! @} --! @name Accumulator results --! @{ --! Accumulator VS result acc_vs_o : out std_ulogic_vector(31 downto 0); --! Accumulator VS result enable acc_vs_en_o : out std_ulogic; --! Accumulator IA result acc_ia_o : out std_ulogic_vector(31 downto 0); --! Accumulator IA result enable acc_ia_en_o : out std_ulogic; --! Accumulator IB result acc_ib_o : out std_ulogic_vector(31 downto 0); --! Accumulator IB result enable acc_ib_en_o : out std_ulogic); --! @} end entity ab; --! RTL implementation of ab architecture rtl of ab is --------------------------------------------------------------------------- --! @name Types and Constants --------------------------------------------------------------------------- --! @{ type acc_result_t is array (0 to 2) of std_ulogic_vector(27 downto 0); type sefi_mode_t is array (0 to 5) of std_ulogic_vector(1 downto 0); --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal adc_m0 : std_ulogic_vector(2 downto 0); signal adc_m1 : std_ulogic_vector(2 downto 0); signal adc_result : ads1281_filter_result_t; signal adc_result_en : std_ulogic_vector(2 downto 0); signal acc_result : acc_result_t; signal acc_result_en : std_ulogic_vector(2 downto 0); signal ab : ab_out_t; signal sample_strb : std_ulogic; signal adc_m : std_ulogic_vector(5 downto 0); signal sefi_in : std_ulogic_vector(5 downto 0); signal sefi_mode : sefi_mode_t; signal vref : std_ulogic_vector(15 downto 0); signal vref_en : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- -- Power up analogue board ab_o.pwr_on_n <= '0'; -- Start temperature control on analogue board ab_o.temp_stop <= '0'; ab_o.cal_dac <= ab.cal_dac; ab_o.cal_offset <= ab.cal_offset; ab_o.cal_vref_p <= ab.cal_vref_p; ab_o.cal_vref_n <= ab.cal_vref_n; ab_o.adc_vs_rst_n <= ab.adc_vs_rst_n; ab_o.sw_in_vs <= ab.sw_in_vs; ab_o.adc_a_rst_n <= ab.adc_a_rst_n; ab_o.sw_in_a <= ab.sw_in_a; ab_o.adc_b_rst_n <= ab.adc_b_rst_n; ab_o.sw_in_b <= ab.sw_in_b; adc_vs_o <= adc_result(0); adc_vs_en_o <= adc_result_en(0); adc_ia_o <= adc_result(1); adc_ia_en_o <= adc_result_en(1); adc_ib_o <= adc_result(2); adc_ib_en_o <= adc_result_en(2); acc_vs_o(31 downto 28) <= (31 downto 28 => acc_result(0)(acc_result(0)'high)); acc_vs_o(27 downto 0) <= acc_result(0); acc_vs_en_o <= acc_result_en(0); acc_ia_o(31 downto 28) <= (31 downto 28 => acc_result(1)(acc_result(1)'high)); acc_ia_o(27 downto 0) <= acc_result(1); acc_ia_en_o <= acc_result_en(1); acc_ib_o(31 downto 28) <= (31 downto 28 => acc_result(2)(acc_result(2)'high)); acc_ib_o(27 downto 0) <= acc_result(2); acc_ib_en_o <= acc_result_en(2); --------------------------------------------------------------------------- -- Signal Assignments --------------------------------------------------------------------------- adc_m0 <= ab_i.adc_vs(0) & ab_i.adc_a(0) & ab_i.adc_b(0); adc_m1 <= ab_i.adc_vs(1) & ab_i.adc_a(1) & ab_i.adc_b(1); adc_m <= ab_i.adc_b & ab_i.adc_a & ab_i.adc_vs; sefi_mode(0) <= command_i.sefi_test_vs_m0; sefi_mode(1) <= command_i.sefi_test_vs_m1; sefi_mode(2) <= command_i.sefi_test_ia_m0; sefi_mode(3) <= command_i.sefi_test_ia_m1; sefi_mode(4) <= command_i.sefi_test_ib_m0; sefi_mode(5) <= command_i.sefi_test_ib_m1; vref <= pf_vref_i when pf_vref_ovr_i = '1' else command_i.v_ref; vref_en <= pf_vref_en_i when pf_vref_ovr_i = '1' else ms_0_strobe_i; --------------------------------------------------------------------------- -- Instances --------------------------------------------------------------------------- --! SEFI detector test sefi_test_gen : for i in 0 to 5 generate sefi_test_inst : entity work.sefi_detector_test port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, ms_0_strobe_i => ms_0_strobe_i, en_i => command_i.vs_cmd(0), mode_i => sefi_mode(i), strb_i => sample_strb, adc_i => adc_m(i), test_o => sefi_in(i)); end generate sefi_test_gen; --! SEFI detectors sefi_detector_gen : for i in 0 to 5 generate sefi_detector_inst : entity work.sefi_detector generic map ( num_g => 30) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => ms_0_strobe_i, en_i => sample_strb, sig_i => sefi_in(i), sefi_o => sefi_o(i)); end generate sefi_detector_gen; --! Analogue board DAC interface max5541_interface_inst : entity work.max5541_interface port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, data_i => vref, data_en_i => vref_en, busy_o => open, done_o => open, cs_o => ab_o.dac_cs, sclk_o => ab_o.dac_sclk, din_o => ab_o.dac_din); --! ADS1281 filter ads1281_filter_inst : entity work.ads1281_filter port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, strb_ms_i => ms_strobe_i, strb_sample_o => sample_strb, adc_m0_i => adc_m0, adc_m1_i => adc_m1, result_o => adc_result, result_en_o => adc_result_en); --! ADS1281 result accumulator ads1281_result_accumulator_gen : for i in 0 to 2 generate ads1281_result_accumulator_inst : entity work.ads1281_result_accumulator generic map ( num_results_g => 10) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => ms_0_strobe_i, result_i => adc_result(i), result_en_i => adc_result_en(i), result_o => acc_result(i), result_en_o => acc_result_en(i)); end generate ads1281_result_accumulator_gen; --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin ab.cal_dac <= '0'; ab.cal_offset <= '0'; ab.cal_vref_p <= '0'; ab.cal_vref_n <= '0'; ab.adc_vs_rst_n <= '1'; ab.sw_in_vs <= '0'; ab.adc_a_rst_n <= '1'; ab.sw_in_a <= '0'; ab.adc_b_rst_n <= '1'; ab.sw_in_b <= '0'; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; elsif ms_0_strobe_i = '1' then case command_i.cal_source is when "00" => ab.cal_dac <= '0'; ab.cal_offset <= '1'; ab.cal_vref_n <= '0'; ab.cal_vref_p <= '0'; when "01" => ab.cal_dac <= '0'; ab.cal_offset <= '0'; ab.cal_vref_n <= '0'; ab.cal_vref_p <= '1'; when "10" => ab.cal_dac <= '0'; ab.cal_offset <= '0'; ab.cal_vref_n <= '1'; ab.cal_vref_p <= '0'; when "11" => ab.cal_dac <= '1'; ab.cal_offset <= '0'; ab.cal_vref_n <= '0'; ab.cal_vref_p <= '0'; when others => null; end case; ab.adc_vs_rst_n <= command_i.adc_vs_reset_n; ab.adc_a_rst_n <= command_i.adc_ia_reset_n; ab.adc_b_rst_n <= command_i.adc_ib_reset_n; if command_i.vs_cmd(0) = '0' then ab.sw_in_vs <= command_i.cal_vs_en; ab.sw_in_a <= command_i.cal_ia_en; ab.sw_in_b <= command_i.cal_ib_en; else ab.sw_in_vs <= '0'; ab.sw_in_a <= '0'; ab.sw_in_b <= '0'; end if; end if; end if; end process regs; end architecture rtl;

architecture RTL of FIFO is begin process begin -- Comment loop end loop; -- Comment LOOP_LABEL : loop end loop; -- Comment while condition loop end loop; -- Comment for x in (31 downto 0) loop end loop; loop end loop; LOOP_LABEL : loop end loop; while condition loop end loop; for x in (31 downto 0) loop end loop; -- Violations below a <= b; loop end loop; a <= b; LOOP_LABEL : loop end loop; a <= b; while condition loop end loop; a <= b; for x in (31 downto 0) loop end loop; end process; end;

------------------------------------------------------------------------------ -- mgt_fifo1.vhd - entity/architecture pair ------------------------------------------------------------------------------ -- IMPORTANT: -- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS. -- -- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED. -- -- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW -- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION -- OF THE USER_LOGIC ENTITY. ------------------------------------------------------------------------------ -- -- *************************************************************************** -- ** Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** Xilinx, Inc. ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** -- ** FOR A PARTICULAR PURPOSE. ** -- ** ** -- ** YOU MAY COPY AND MODIFY THESE FILES FOR YOUR OWN INTERNAL USE SOLELY ** -- ** WITH XILINX PROGRAMMABLE LOGIC DEVICES AND XILINX EDK SYSTEM OR ** -- ** CREATE IP MODULES SOLELY FOR XILINX PROGRAMMABLE LOGIC DEVICES AND ** -- ** XILINX EDK SYSTEM. NO RIGHTS ARE GRANTED TO DISTRIBUTE ANY FILES ** -- ** UNLESS THEY ARE DISTRIBUTED IN XILINX PROGRAMMABLE LOGIC DEVICES. ** -- ** ** -- *************************************************************************** -- ------------------------------------------------------------------------------ -- Filename: mgt_fifo1.vhd -- Version: 1.00.a -- Description: Top level design, instantiates IPIF and user logic. -- Date: Tue Jul 05 10:18:46 2005 (by Create and Import Peripheral Wizard) -- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- device pins: "*_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC>" ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v2_00_a; use proc_common_v2_00_a.proc_common_pkg.all; use proc_common_v2_00_a.ipif_pkg.all; library opb_ipif_v3_01_a; use opb_ipif_v3_01_a.all; library mgt_fifo1_v1_00_a; use mgt_fifo1_v1_00_a.all; ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_BASEADDR -- User logic base address -- C_HIGHADDR -- User logic high address -- C_OPB_AWIDTH -- OPB address bus width -- C_OPB_DWIDTH -- OPB data bus width -- C_FAMILY -- Target FPGA architecture -- -- Definition of Ports: -- OPB_Clk -- OPB Clock -- OPB_Rst -- OPB Reset -- Sl_DBus -- Slave data bus -- Sl_errAck -- Slave error acknowledge -- Sl_retry -- Slave retry -- Sl_toutSup -- Slave timeout suppress -- Sl_xferAck -- Slave transfer acknowledge -- OPB_ABus -- OPB address bus -- OPB_BE -- OPB byte enable -- OPB_DBus -- OPB data bus -- OPB_RNW -- OPB read/not write -- OPB_select -- OPB select -- OPB_seqAddr -- OPB sequential address ------------------------------------------------------------------------------ entity mgt_fifo1 is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_BASEADDR : std_logic_vector := X"00000000"; C_HIGHADDR : std_logic_vector := X"0000FFFF"; C_OPB_AWIDTH : integer := 32; C_OPB_DWIDTH : integer := 32; C_FAMILY : string := "virtex2p" -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here iTOP_REF_CLK : in std_logic; iRXN : in std_logic; iRXP : in std_logic; iTXN : out std_logic; iTXP : out std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete OPB_Clk : in std_logic; OPB_Rst : in std_logic; Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); Sl_errAck : out std_logic; Sl_retry : out std_logic; Sl_toutSup : out std_logic; Sl_xferAck : out std_logic; OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); OPB_RNW : in std_logic; OPB_select : in std_logic; OPB_seqAddr : in std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute SIGIS : string; attribute SIGIS of OPB_Clk : signal is "Clk"; attribute SIGIS of OPB_Rst : signal is "Rst"; end entity mgt_fifo1; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of mgt_fifo1 is ------------------------------------------ -- Constant: array of address range identifiers ------------------------------------------ constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => USER_00, -- user logic S/W register address space 1 => IPIF_RDFIFO_REG, -- include read FIFO register service 2 => IPIF_RDFIFO_DATA, -- include read FIFO service 3 => IPIF_WRFIFO_REG, -- include write FIFO register service 4 => IPIF_WRFIFO_DATA -- include write FIFO service ); ------------------------------------------ -- Constant: array of address pairs for each address range ------------------------------------------ constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0'); constant USER_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000"; constant USER_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF"; constant RDFIFO_REG_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100"; constant RDFIFO_REG_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF"; constant RDFIFO_DATA_BASEADDR : std_logic_vector := C_BASEADDR or X"00000200"; constant RDFIFO_DATA_HIGHADDR : std_logic_vector := C_BASEADDR or X"000002FF"; constant WRFIFO_REG_BASEADDR : std_logic_vector := C_BASEADDR or X"00000300"; constant WRFIFO_REG_HIGHADDR : std_logic_vector := C_BASEADDR or X"000003FF"; constant WRFIFO_DATA_BASEADDR : std_logic_vector := C_BASEADDR or X"00000400"; constant WRFIFO_DATA_HIGHADDR : std_logic_vector := C_BASEADDR or X"000004FF"; constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address ZERO_ADDR_PAD & USER_HIGHADDR, -- user logic high address ZERO_ADDR_PAD & RDFIFO_REG_BASEADDR, -- read FIFO register base address ZERO_ADDR_PAD & RDFIFO_REG_HIGHADDR, -- read FIFO register high address ZERO_ADDR_PAD & RDFIFO_DATA_BASEADDR, -- read FIFO data base address ZERO_ADDR_PAD & RDFIFO_DATA_HIGHADDR, -- read FIFO data high address ZERO_ADDR_PAD & WRFIFO_REG_BASEADDR, -- write FIFO register base address ZERO_ADDR_PAD & WRFIFO_REG_HIGHADDR, -- write FIFO register high address ZERO_ADDR_PAD & WRFIFO_DATA_BASEADDR, -- write FIFO data base address ZERO_ADDR_PAD & WRFIFO_DATA_HIGHADDR -- write FIFO data high address ); ------------------------------------------ -- Constant: array of data widths for each target address range ------------------------------------------ constant USER_DWIDTH : integer := 32; constant USER_RDFIFO_DWIDTH : integer := 32; constant USER_WRFIFO_DWIDTH : integer := 32; constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => USER_DWIDTH, -- user logic data width 1 => C_OPB_DWIDTH, -- read FIFO register data width 2 => USER_RDFIFO_DWIDTH, -- read FIFO data width 3 => C_OPB_DWIDTH, -- write FIFO register data width 4 => USER_WRFIFO_DWIDTH -- write FIFO data width ); ------------------------------------------ -- Constant: array of desired number of chip enables for each address range ------------------------------------------ constant USER_NUM_CE : integer := 2; constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => pad_power2(USER_NUM_CE), -- user logic number of CEs 1 => 2, -- read FIFO register - 2 CEs 2 => 1, -- read FIFO data - 1 CE 3 => 2, -- write FIFO register - 2 CEs 4 => 1 -- write FIFO data - 1 CE ); ------------------------------------------ -- Constant: array of unique properties for each address range ------------------------------------------ constant USER_RDFIFO_DEPTH : integer := 512; constant USER_RDFIFO_INCLUDE_PACKET_MODE : boolean := false; constant USER_RDFIFO_INCLUDE_VACANCY : boolean := true; constant USER_WRFIFO_DEPTH : integer := 512; constant USER_WRFIFO_INCLUDE_PACKET_MODE : boolean := false; constant USER_WRFIFO_INCLUDE_VACANCY : boolean := true; constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE := ( 0 => (others => 0), -- user logic slave space dependent properties (none defined) 1 => (others => 0), -- IPIF read pfifo register dependent properties (none defined) 2 => ( -- IPIF read pfifo data dependent properties FIFO_CAPACITY_BITS => USER_RDFIFO_DEPTH*USER_RDFIFO_DWIDTH, WR_WIDTH_BITS => USER_RDFIFO_DWIDTH, RD_WIDTH_BITS => USER_RDFIFO_DWIDTH, EXCLUDE_PACKET_MODE => 1-boolean'pos(USER_RDFIFO_INCLUDE_PACKET_MODE), EXCLUDE_VACANCY => 1-boolean'pos(USER_RDFIFO_INCLUDE_VACANCY), others => 0), 3 => (others => 0), -- IPIF write pfifo register dependent properties (none defined) 4 => ( -- IPIF write pfifo data dependent properties FIFO_CAPACITY_BITS => USER_WRFIFO_DEPTH*USER_WRFIFO_DWIDTH, WR_WIDTH_BITS => USER_WRFIFO_DWIDTH, RD_WIDTH_BITS => USER_WRFIFO_DWIDTH, EXCLUDE_PACKET_MODE => 1-boolean'pos(USER_WRFIFO_INCLUDE_PACKET_MODE), EXCLUDE_VACANCY => 1-boolean'pos(USER_WRFIFO_INCLUDE_VACANCY), others => 0) ); ------------------------------------------ -- Constant: pipeline mode -- 1 = include OPB-In pipeline registers -- 2 = include IP pipeline registers -- 3 = include OPB-In and IP pipeline registers -- 4 = include OPB-Out pipeline registers -- 5 = include OPB-In and OPB-Out pipeline registers -- 6 = include IP and OPB-Out pipeline registers -- 7 = include OPB-In, IP, and OPB-Out pipeline registers -- Note: -- only mode 4, 5, 7 are supported for this release ------------------------------------------ constant PIPELINE_MODEL : integer := 5; ------------------------------------------ -- Constant: user core ID code ------------------------------------------ constant DEV_BLK_ID : integer := 0; ------------------------------------------ -- Constant: enable MIR/Reset register ------------------------------------------ constant DEV_MIR_ENABLE : integer := 0; ------------------------------------------ -- Constant: array of IP interrupt mode -- 1 = Active-high interrupt condition -- 2 = Active-low interrupt condition -- 3 = Active-high pulse interrupt event -- 4 = Active-low pulse interrupt event -- 5 = Positive-edge interrupt event -- 6 = Negative-edge interrupt event ------------------------------------------ constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => 0 -- not used ); ------------------------------------------ -- Constant: enable device burst ------------------------------------------ constant DEV_BURST_ENABLE : integer := 0; ------------------------------------------ -- Constant: include address counter for burst transfers ------------------------------------------ constant INCLUDE_ADDR_CNTR : integer := 0; ------------------------------------------ -- Constant: include write buffer that decouples OPB and IPIC write transactions ------------------------------------------ constant INCLUDE_WR_BUF : integer := 0; ------------------------------------------ -- Constant: index for CS/CE ------------------------------------------ constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00); constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX); ------------------------------------------ -- IP Interconnect (IPIC) signal declarations -- do not delete -- prefix 'i' stands for IPIF while prefix 'u' stands for user logic -- typically user logic will be hooked up to IPIF directly via i<sig> -- unless signal slicing and muxing are needed via u<sig> ------------------------------------------ signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1); signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1); signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0'); signal iIP2Bus_Ack : std_logic := '0'; signal iIP2Bus_Error : std_logic := '0'; signal iIP2Bus_Retry : std_logic := '0'; signal iIP2Bus_ToutSup : std_logic := '0'; signal ZERO_IP2Bus_PostedWrInh : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping signal iIP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0'); signal iIP2RFIFO_WrReq : std_logic := '0'; signal iRFIFO2IP_AlmostFull : std_logic; signal iRFIFO2IP_Full : std_logic; signal iRFIFO2IP_Vacancy : std_logic_vector(0 to bits_needed_for_vac(find_ard_id(ARD_ID_ARRAY, IPIF_RDFIFO_DATA), ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA)))-1); signal iRFIFO2IP_WrAck : std_logic; signal iIP2WFIFO_RdReq : std_logic := '0'; signal iWFIFO2IP_AlmostEmpty : std_logic; signal iWFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0'); signal iWFIFO2IP_Empty : std_logic; signal iWFIFO2IP_Occupancy : std_logic_vector(0 to bits_needed_for_vac(find_ard_id(ARD_ID_ARRAY, IPIF_WRFIFO_DATA), ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA)))-1); signal iWFIFO2IP_RdAck : std_logic; signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping signal iBus2IP_Clk : std_logic; signal iBus2IP_Reset : std_logic; signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1); signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1); signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1); signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1); signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1); ------------------------------------------ -- Component declaration for verilog user logic ------------------------------------------ component user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_DWIDTH : integer := 32; C_NUM_CE : integer := 2; C_RDFIFO_DWIDTH : integer := 32; C_RDFIFO_DEPTH : integer := 512; C_WRFIFO_DWIDTH : integer := 32; C_WRFIFO_DEPTH : integer := 512 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here TOP_REF_CLK : in std_logic; RXP : in std_logic; RXN : in std_logic; TXP : out std_logic; TXN : out std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Reset : in std_logic; Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1); Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1); Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1); Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1); IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1); IP2Bus_Ack : out std_logic; IP2Bus_Retry : out std_logic; IP2Bus_Error : out std_logic; IP2Bus_ToutSup : out std_logic; IP2RFIFO_WrReq : out std_logic; IP2RFIFO_Data : out std_logic_vector(0 to C_RDFIFO_DWIDTH-1); RFIFO2IP_WrAck : in std_logic; RFIFO2IP_AlmostFull : in std_logic; RFIFO2IP_Full : in std_logic; RFIFO2IP_Vacancy : in std_logic_vector(0 to log2(C_RDFIFO_DEPTH)); IP2WFIFO_RdReq : out std_logic; WFIFO2IP_Data : in std_logic_vector(0 to C_WRFIFO_DWIDTH-1); WFIFO2IP_RdAck : in std_logic; WFIFO2IP_AlmostEmpty : in std_logic; WFIFO2IP_Empty : in std_logic; WFIFO2IP_Occupancy : in std_logic_vector(0 to log2(C_WRFIFO_DEPTH)) -- DO NOT EDIT ABOVE THIS LINE --------------------- ); end component user_logic; begin ------------------------------------------ -- instantiate the OPB IPIF ------------------------------------------ OPB_IPIF_I : entity opb_ipif_v3_01_a.opb_ipif generic map ( C_ARD_ID_ARRAY => ARD_ID_ARRAY, C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY, C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY, C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY, C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY, C_PIPELINE_MODEL => PIPELINE_MODEL, C_DEV_BLK_ID => DEV_BLK_ID, C_DEV_MIR_ENABLE => DEV_MIR_ENABLE, C_OPB_AWIDTH => C_OPB_AWIDTH, C_OPB_DWIDTH => C_OPB_DWIDTH, C_FAMILY => C_FAMILY, C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY, C_DEV_BURST_ENABLE => DEV_BURST_ENABLE, C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR, C_INCLUDE_WR_BUF => INCLUDE_WR_BUF ) port map ( OPB_select => OPB_select, OPB_DBus => OPB_DBus, OPB_ABus => OPB_ABus, OPB_BE => OPB_BE, OPB_RNW => OPB_RNW, OPB_seqAddr => OPB_seqAddr, Sln_DBus => Sl_DBus, Sln_xferAck => Sl_xferAck, Sln_errAck => Sl_errAck, Sln_retry => Sl_retry, Sln_toutSup => Sl_toutSup, Bus2IP_CS => open, Bus2IP_CE => open, Bus2IP_RdCE => iBus2IP_RdCE, Bus2IP_WrCE => iBus2IP_WrCE, Bus2IP_Data => iBus2IP_Data, Bus2IP_Addr => open, Bus2IP_AddrValid => open, Bus2IP_BE => iBus2IP_BE, Bus2IP_RNW => open, Bus2IP_Burst => open, IP2Bus_Data => iIP2Bus_Data, IP2Bus_Ack => iIP2Bus_Ack, IP2Bus_AddrAck => '0', IP2Bus_Error => iIP2Bus_Error, IP2Bus_Retry => iIP2Bus_Retry, IP2Bus_ToutSup => iIP2Bus_ToutSup, IP2Bus_PostedWrInh => ZERO_IP2Bus_PostedWrInh, IP2RFIFO_Data => iIP2RFIFO_Data, IP2RFIFO_WrMark => '0', IP2RFIFO_WrRelease => '0', IP2RFIFO_WrReq => iIP2RFIFO_WrReq, IP2RFIFO_WrRestore => '0', RFIFO2IP_AlmostFull => iRFIFO2IP_AlmostFull, RFIFO2IP_Full => iRFIFO2IP_Full, RFIFO2IP_Vacancy => iRFIFO2IP_Vacancy, RFIFO2IP_WrAck => iRFIFO2IP_WrAck, IP2WFIFO_RdMark => '0', IP2WFIFO_RdRelease => '0', IP2WFIFO_RdReq => iIP2WFIFO_RdReq, IP2WFIFO_RdRestore => '0', WFIFO2IP_AlmostEmpty => iWFIFO2IP_AlmostEmpty, WFIFO2IP_Data => iWFIFO2IP_Data, WFIFO2IP_Empty => iWFIFO2IP_Empty, WFIFO2IP_Occupancy => iWFIFO2IP_Occupancy, WFIFO2IP_RdAck => iWFIFO2IP_RdAck, IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent, IP2INTC_Irpt => open, Freeze => '0', Bus2IP_Freeze => open, OPB_Clk => OPB_Clk, Bus2IP_Clk => iBus2IP_Clk, IP2Bus_Clk => '0', Reset => OPB_Rst, Bus2IP_Reset => iBus2IP_Reset ); ------------------------------------------ -- instantiate the User Logic ------------------------------------------ USER_LOGIC_I : component user_logic generic map ( -- MAP USER GENERICS BELOW THIS LINE --------------- --USER generics mapped here -- MAP USER GENERICS ABOVE THIS LINE --------------- C_DWIDTH => USER_DWIDTH, C_NUM_CE => USER_NUM_CE, C_RDFIFO_DWIDTH => USER_RDFIFO_DWIDTH, C_RDFIFO_DEPTH => USER_RDFIFO_DEPTH, C_WRFIFO_DWIDTH => USER_WRFIFO_DWIDTH, C_WRFIFO_DEPTH => USER_WRFIFO_DEPTH ) port map ( -- MAP USER PORTS BELOW THIS LINE ------------------ --USER ports mapped here TOP_REF_CLK => iTOP_REF_CLK, RXP => iRXP, RXN => iRXN, TXP => iTXP, TXN => iTXN, -- MAP USER PORTS ABOVE THIS LINE ------------------ Bus2IP_Clk => iBus2IP_Clk, Bus2IP_Reset => iBus2IP_Reset, Bus2IP_Data => uBus2IP_Data, Bus2IP_BE => uBus2IP_BE, Bus2IP_RdCE => uBus2IP_RdCE, Bus2IP_WrCE => uBus2IP_WrCE, IP2Bus_Data => uIP2Bus_Data, IP2Bus_Ack => iIP2Bus_Ack, IP2Bus_Retry => iIP2Bus_Retry, IP2Bus_Error => iIP2Bus_Error, IP2Bus_ToutSup => iIP2Bus_ToutSup, IP2RFIFO_WrReq => iIP2RFIFO_WrReq, IP2RFIFO_Data => iIP2RFIFO_Data, RFIFO2IP_WrAck => iRFIFO2IP_WrAck, RFIFO2IP_AlmostFull => iRFIFO2IP_AlmostFull, RFIFO2IP_Full => iRFIFO2IP_Full, RFIFO2IP_Vacancy => iRFIFO2IP_Vacancy, IP2WFIFO_RdReq => iIP2WFIFO_RdReq, WFIFO2IP_Data => iWFIFO2IP_Data, WFIFO2IP_RdAck => iWFIFO2IP_RdAck, WFIFO2IP_AlmostEmpty => iWFIFO2IP_AlmostEmpty, WFIFO2IP_Empty => iWFIFO2IP_Empty, WFIFO2IP_Occupancy => iWFIFO2IP_Occupancy ); ------------------------------------------ -- hooking up signal slicing ------------------------------------------ uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1); uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1); uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1); uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1); iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data; end IMP;

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_cast_GNMYKU6OLE is generic ( round : natural := 0; saturate : natural := 0); port( input : in std_logic_vector(15 downto 0); output : out std_logic_vector(3 downto 0)); end entity; architecture rtl of alt_dspbuilder_cast_GNMYKU6OLE is Begin -- Output - I/O assignment from Simulink Block "Output" Outputi : alt_dspbuilder_SBF generic map( width_inl=> 4 + 1 , width_inr=> 12, width_outl=> 4, width_outr=> 0, lpm_signed=> BusIsUnsigned , round=> round, satur=> saturate) port map ( xin(15 downto 0) => input, xin(16) => '0', yout => output ); end architecture;

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ORGATE IS PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END ORGATE; ARCHITECTURE OR1 OF ORGATE IS BEGIN C <= A OR B; END OR1;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity logical is Port ( A : in STD_LOGIC_VECTOR (3 downto 0); B : in STD_LOGIC_VECTOR (3 downto 0); op : in STD_LOGIC_VECTOR (1 downto 0); R : out STD_LOGIC_VECTOR (3 downto 0) ); end logical; architecture Behavioral of logical is --output signals signal and_R : std_logic_vector (3 downto 0); signal or_R : std_logic_vector (3 downto 0); signal nor_R : std_logic_vector (3 downto 0); signal xor_R : std_logic_vector (3 downto 0); begin --crunch all possible values and_R <= A AND B; or_R <= A OR B; nor_R <= A NOR B; xor_R <= A XOR B; --select output based on opcode output: entity work.mux4 port map (nor_R, and_R, or_R, xor_R, op, R); end Behavioral;

-- -------------------------------------------------------------------- -- -- Copyright © 2008 by IEEE. All rights reserved. -- -- This source file is an essential part of IEEE Std 1076-2008, -- IEEE Standard VHDL Language Reference Manual. This source file may not be -- copied, sold, or included with software that is sold without written -- permission from the IEEE Standards Department. This source file may be -- copied for individual use between licensed users. This source file is -- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR -- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE -- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify -- and hold IEEE harmless from any damages or liability arising out of the -- use thereof. -- -- Title : Floating-point package (Generic package body) -- : -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: Accellera VHDL-TC and IEEE P1076 Working Group -- : -- Purpose : This packages defines basic binary floating point -- : arithmetic functions -- : -- Note : This package may be modified to include additional data -- : required by tools, but it must in no way change the -- : external interfaces or simulation behavior of the -- : description. It is permissible to add comments and/or -- : attributes to the package declarations, but not to change -- : or delete any original lines of the package declaration. -- : The package body may be changed only in accordance with -- : the terms of Clause 16 of this standard. -- : -- -------------------------------------------------------------------- -- $Revision: 1220 $ -- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ -- -------------------------------------------------------------------- package body float_generic_pkg is -- Author David Bishop ([email protected]) ----------------------------------------------------------------------------- -- type declarations ----------------------------------------------------------------------------- -- This deferred constant will tell you if the package body is synthesizable -- or implemented as real numbers, set to "true" if synthesizable. constant fphdlsynth_or_real : BOOLEAN := true; -- deferred constant -- types of boundary conditions type boundary_type is (normal, infinity, zero, denormal); -- null range array constant constant NAFP : UNRESOLVED_float (0 downto 1) := (others => '0'); constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0'); -- Special version of "minimum" to do some boundary checking function mine (L, R : INTEGER) return INTEGER is begin -- function minimum if (L = INTEGER'low or R = INTEGER'low) then report float_generic_pkg'instance_name & " Unbounded number passed, was a literal used?" severity error; return 0; end if; return minimum (L, R); end function mine; -- Generates the base number for the exponent normalization offset. function gen_expon_base ( constant exponent_width : NATURAL) return SIGNED is variable result : SIGNED (exponent_width-1 downto 0); begin result := (others => '1'); result (exponent_width-1) := '0'; return result; end function gen_expon_base; -- Integer version of the "log2" command (contributed by Peter Ashenden) function log2 (A : NATURAL) return NATURAL is variable quotient : NATURAL; variable result : NATURAL := 0; begin quotient := A / 2; while quotient > 0 loop quotient := quotient / 2; result := result + 1; end loop; return result; end function log2; -- Function similar to the ILOGB function in MATH_REAL function log2 (A : REAL) return INTEGER is variable Y : REAL; variable N : INTEGER := 0; begin if (A = 1.0 or A = 0.0) then return 0; end if; Y := A; if(A > 1.0) then while Y >= 2.0 loop Y := Y / 2.0; N := N + 1; end loop; return N; end if; -- O < Y < 1 while Y < 1.0 loop Y := Y * 2.0; N := N - 1; end loop; return N; end function log2; -- purpose: Test the boundary conditions of a Real number procedure test_boundary ( arg : in REAL; -- Input, converted to real constant fraction_width : in NATURAL; -- length of FP output fraction constant exponent_width : in NATURAL; -- length of FP exponent constant denormalize : in BOOLEAN := true; -- Use IEEE extended FP variable btype : out boundary_type; variable log2i : out INTEGER ) is constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset constant exp_min : SIGNED (12 downto 0) := -(resize(expon_base, 13)) + 1; -- Minimum normal exponent constant exp_ext_min : SIGNED (12 downto 0) := exp_min - fraction_width; -- Minimum for denormal exponent variable log2arg : INTEGER; -- log2 of argument begin -- function test_boundary -- Check to see if the exponent is big enough -- Note that the argument is always an absolute value at this point. log2arg := log2(arg); if arg = 0.0 then btype := zero; elsif exponent_width > 11 then -- Exponent for Real is 11 (64 bit) btype := normal; else if log2arg < to_integer(exp_min) then if denormalize then if log2arg < to_integer(exp_ext_min) then btype := zero; else btype := denormal; end if; else if log2arg < to_integer(exp_min)-1 then btype := zero; else btype := normal; -- Can still represent this number end if; end if; elsif exponent_width < 11 then if log2arg > to_integer(expon_base)+1 then btype := infinity; else btype := normal; end if; else btype := normal; end if; end if; log2i := log2arg; end procedure test_boundary; -- purpose: Rounds depending on the state of the "round_style" -- Logic taken from -- "What Every Computer Scientist Should Know About Floating Point Arithmetic" -- by David Goldberg (1991) function check_round ( fract_in : STD_ULOGIC; -- input fraction sign : STD_ULOGIC; -- sign bit remainder : UNSIGNED; -- remainder to round from sticky : STD_ULOGIC := '0'; -- Sticky bit constant round_style : round_type) -- rounding type return BOOLEAN is variable result : BOOLEAN; variable or_reduced : STD_ULOGIC; begin -- function check_round result := false; if (remainder'length > 0) then -- if remainder in a null array or_reduced := or (remainder & sticky); rounding_case : case round_style is when round_nearest => -- Round Nearest, default mode if remainder(remainder'high) = '1' then -- round if (remainder'length > 1) then if ((or (remainder(remainder'high-1 downto remainder'low)) = '1' or sticky = '1') or fract_in = '1') then -- Make the bottom bit zero if possible if we are at 1/2 result := true; end if; else result := (fract_in = '1' or sticky = '1'); end if; end if; when round_inf => -- round up if positive, else truncate. if or_reduced = '1' and sign = '0' then result := true; end if; when round_neginf => -- round down if negative, else truncate. if or_reduced = '1' and sign = '1' then result := true; end if; when round_zero => -- round toward 0 Truncate null; end case rounding_case; end if; return result; end function check_round; -- purpose: Rounds depending on the state of the "round_style" -- unsigned version procedure fp_round ( fract_in : in UNSIGNED; -- input fraction expon_in : in SIGNED; -- input exponent fract_out : out UNSIGNED; -- output fraction expon_out : out SIGNED) is -- output exponent begin -- procedure fp_round if and (fract_in) = '1' then -- Fraction is all "1" expon_out := expon_in + 1; fract_out := to_unsigned(0, fract_out'high+1); else expon_out := expon_in; fract_out := fract_in + 1; end if; end procedure fp_round; -- This version of break_number doesn't call "classfp" procedure break_number ( -- internal version arg : in UNRESOLVED_float; fptyp : in valid_fpstate; denormalize : in BOOLEAN := true; fract : out UNSIGNED; expon : out SIGNED) is constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction constant exponent_width : NATURAL := arg'high; -- length of FP output exponent constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable exp : SIGNED (expon'range); begin fract (fraction_width-1 downto 0) := UNSIGNED (to_slv(arg(-1 downto -fraction_width))); breakcase : case fptyp is when pos_zero | neg_zero => fract (fraction_width) := '0'; exp := -expon_base; when pos_denormal | neg_denormal => if denormalize then exp := -expon_base; fract (fraction_width) := '0'; else exp := -expon_base - 1; fract (fraction_width) := '1'; end if; when pos_normal | neg_normal | pos_inf | neg_inf => fract (fraction_width) := '1'; exp := SIGNED(arg(exponent_width-1 downto 0)); exp (exponent_width-1) := not exp(exponent_width-1); when others => assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "BREAK_NUMBER: " & "Meta state detected in fp_break_number process" severity warning; -- complete the case, if a NAN goes in, a NAN comes out. exp := (others => '1'); fract (fraction_width) := '1'; end case breakcase; expon := exp; end procedure break_number; -- purpose: floating point to UNSIGNED -- Used by to_integer, to_unsigned, and to_signed functions procedure float_to_unsigned ( arg : in UNRESOLVED_float; -- floating point input variable sign : out STD_ULOGIC; -- sign of output variable frac : out UNSIGNED; -- unsigned biased output constant denormalize : in BOOLEAN; -- turn on denormalization constant bias : in NATURAL; -- bias for fixed point constant round_style : in round_type) is -- rounding method constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent variable fract : UNSIGNED (frac'range); -- internal version of frac variable isign : STD_ULOGIC; -- internal version of sign variable exp : INTEGER; -- Exponent variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp -- Base to divide fraction by variable frac_shift : UNSIGNED (frac'high+3 downto 0); -- Fraction shifted variable shift : INTEGER; variable remainder : UNSIGNED (2 downto 0); variable round : STD_ULOGIC; -- round BIT begin isign := to_x01(arg(arg'high)); -- exponent /= '0', normal floating point expon := to_01(SIGNED(arg (exponent_width-1 downto 0)), 'X'); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (expon); -- Figure out the fraction fract := (others => '0'); -- fill with zero fract (fract'high) := '1'; -- Add the "1.0". shift := (fract'high-1) - exp; if fraction_width > fract'high then -- Can only use size-2 bits fract (fract'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto -fract'high))); else -- can use all bits fract (fract'high-1 downto fract'high-fraction_width) := UNSIGNED (to_slv (arg(-1 downto -fraction_width))); end if; frac_shift := fract & "000"; if shift < 0 then -- Overflow fract := (others => '1'); else frac_shift := shift_right (frac_shift, shift); fract := frac_shift (frac_shift'high downto 3); remainder := frac_shift (2 downto 0); -- round (round_zero will bypass this and truncate) case round_style is when round_nearest => round := remainder(2) and (fract (0) or (or (remainder (1 downto 0)))); when round_inf => round := remainder(2) and not isign; when round_neginf => round := remainder(2) and isign; when others => round := '0'; end case; if round = '1' then fract := fract + 1; end if; end if; frac := fract; sign := isign; end procedure float_to_unsigned; -- purpose: returns a part of a vector, this function is here because -- or (fractr (to_integer(shiftx) downto 0)); -- can't be synthesized in some synthesis tools. function smallfract ( arg : UNSIGNED; shift : NATURAL) return STD_ULOGIC is variable orx : STD_ULOGIC; begin orx := arg(shift); for i in arg'range loop if i < shift then orx := arg(i) or orx; end if; end loop; return orx; end function smallfract; --------------------------------------------------------------------------- -- Visible functions --------------------------------------------------------------------------- -- purpose: converts the negative index to a positive one -- negative indices are illegal in 1164 and 1076.3 function to_sulv ( arg : UNRESOLVED_float) -- fp vector return STD_ULOGIC_VECTOR is subtype result_subtype is STD_ULOGIC_VECTOR (arg'length-1 downto 0); variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0); begin -- function to_std_ulogic_vector if arg'length < 1 then return NSLV; end if; result := result_subtype (arg); return result; end function to_sulv; -- Converts an fp into an SULV function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR is begin return to_sulv (arg); end function to_slv; -- purpose: normalizes a floating point number -- This version assumes an "unsigned" input with function normalize ( fract : UNRESOLVED_UNSIGNED; -- fraction, unnormalized expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1 sign : STD_ULOGIC; -- sign BIT sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is variable sfract : UNSIGNED (fract'high downto 0); -- shifted fraction variable rfract : UNSIGNED (fraction_width-1 downto 0); -- fraction variable exp : SIGNED (exponent_width+1 downto 0); -- exponent variable rexp : SIGNED (exponent_width+1 downto 0); -- result exponent variable rexpon : UNSIGNED (exponent_width-1 downto 0); -- exponent variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result variable shiftr : INTEGER; -- shift amount variable stickyx : STD_ULOGIC; -- version of sticky constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable round, zerores, infres : BOOLEAN; begin -- function normalize zerores := false; infres := false; round := false; shiftr := find_leftmost (to_01(fract), '1') -- Find the first "1" - fraction_width - nguard; -- subtract the length we want exp := resize (expon, exp'length) + shiftr; if (or (fract) = '0') then -- Zero zerores := true; elsif ((exp <= -resize(expon_base, exp'length)-1) and denormalize) or ((exp < -resize(expon_base, exp'length)-1) and not denormalize) then if (exp >= -resize(expon_base, exp'length)-fraction_width-1) and denormalize then exp := -resize(expon_base, exp'length)-1; shiftr := -to_integer (expon + expon_base); -- new shift else -- return zero zerores := true; end if; elsif (exp > expon_base-1) then -- infinity infres := true; end if; if zerores then result := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); elsif infres then result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else sfract := fract srl shiftr; -- shift if shiftr > 0 then -- stickyx := sticky or (or (fract (shiftr-1 downto 0))); stickyx := sticky or smallfract (fract, shiftr-1); else stickyx := sticky; end if; if nguard > 0 then round := check_round ( fract_in => sfract (nguard), sign => sign, remainder => sfract(nguard-1 downto 0), sticky => stickyx, round_style => round_style); end if; if round then fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard), expon_in => exp(rexp'range), fract_out => rfract, expon_out => rexp); else rfract := sfract (fraction_width-1+nguard downto nguard); rexp := exp(rexp'range); end if; -- result rexpon := UNSIGNED (rexp(exponent_width-1 downto 0)); rexpon (exponent_width-1) := not rexpon(exponent_width-1); result (rexpon'range) := UNRESOLVED_float(rexpon); result (-1 downto -fraction_width) := UNRESOLVED_float(rfract); end if; result (exponent_width) := sign; -- sign BIT return result; end function normalize; -- purpose: normalizes a floating point number -- This version assumes a "ufixed" input function normalize ( fract : UNRESOLVED_ufixed; -- unsigned fixed point expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1 sign : STD_ULOGIC; -- sign bit sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arguns : UNSIGNED (fract'high + fraction_width + nguard downto 0) := (others => '0'); begin -- function normalize arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) := UNSIGNED (to_slv (fract)); result := normalize (fract => arguns, expon => expon, sign => sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => nguard); return result; end function normalize; -- purpose: normalizes a floating point number -- This version assumes a "ufixed" input with a "size_res" input function normalize ( fract : UNRESOLVED_ufixed; -- unsigned fixed point expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1 sign : STD_ULOGIC; -- sign bit sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) size_res : UNRESOLVED_float; -- used for sizing only constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is constant fraction_width : NATURAL := -size_res'low; constant exponent_width : NATURAL := size_res'high; variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arguns : UNSIGNED (fract'high + fraction_width + nguard downto 0) := (others => '0'); begin -- function normalize arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) := UNSIGNED (to_slv (fract)); result := normalize (fract => arguns, expon => expon, sign => sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => nguard); return result; end function normalize; -- Regular "normalize" function with a "size_res" input. function normalize ( fract : UNRESOLVED_UNSIGNED; -- unsigned expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized sign : STD_ULOGIC; -- sign bit sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding) size_res : UNRESOLVED_float; -- used for sizing only constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant nguard : NATURAL := float_guard_bits) -- guard bits return UNRESOLVED_float is begin return normalize (fract => fract, expon => expon, sign => sign, sticky => sticky, fraction_width => -size_res'low, exponent_width => size_res'high, round_style => round_style, denormalize => denormalize, nguard => nguard); end function normalize; -- Returns the class which X falls into function Classfp ( x : UNRESOLVED_float; -- floating point input check_error : BOOLEAN := float_check_error) -- check for errors return valid_fpstate is constant fraction_width : INTEGER := -mine(x'low, x'low); -- length of FP output fraction constant exponent_width : INTEGER := x'high; -- length of FP output exponent variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- classfp if (arg'length < 1 or fraction_width < 3 or exponent_width < 3 or x'left < x'right) then report FLOAT_GENERIC_PKG'instance_name & "CLASSFP: " & "Floating point number detected with a bad range" severity error; return isx; end if; -- Check for "X". arg := to_01 (x, 'X'); if (arg(0) = 'X') then return isx; -- If there is an X in the number -- Special cases, check for illegal number elsif check_error and (and (STD_ULOGIC_VECTOR (arg (exponent_width-1 downto 0))) = '1') then -- Exponent is all "1". if or (to_slv (arg (-1 downto -fraction_width))) /= '0' then -- Fraction must be all "0" or this is not a number. if (arg(-1) = '1') then -- From "W. Khan - IEEE standard return nan; -- 754 binary FP Signaling nan (Not a number) else return quiet_nan; end if; -- Check for infinity elsif arg(exponent_width) = '0' then return pos_inf; -- Positive infinity else return neg_inf; -- Negative infinity end if; -- check for "0" elsif or (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0))) = '0' then -- Exponent is all "0" if or (to_slv (arg (-1 downto -fraction_width))) = '0' then -- Fraction is all "0" if arg(exponent_width) = '0' then return pos_zero; -- Zero else return neg_zero; end if; else if arg(exponent_width) = '0' then return pos_denormal; -- Denormal number (ieee extended fp) else return neg_denormal; end if; end if; else if arg(exponent_width) = '0' then return pos_normal; -- Normal FP number else return neg_normal; end if; end if; end function Classfp; procedure break_number ( arg : in UNRESOLVED_float; denormalize : in BOOLEAN := float_denormalize; check_error : in BOOLEAN := float_check_error; fract : out UNRESOLVED_UNSIGNED; expon : out UNRESOLVED_SIGNED; sign : out STD_ULOGIC) is constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction variable fptyp : valid_fpstate; begin fptyp := Classfp (arg, check_error); sign := to_x01(arg(arg'high)); break_number ( arg => arg, fptyp => fptyp, denormalize => denormalize, fract => fract, expon => expon); end procedure break_number; procedure break_number ( arg : in UNRESOLVED_float; denormalize : in BOOLEAN := float_denormalize; check_error : in BOOLEAN := float_check_error; fract : out UNRESOLVED_ufixed; -- 1 downto -fraction_width expon : out UNRESOLVED_SIGNED; -- exponent_width-1 downto 0 sign : out STD_ULOGIC) is constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction variable fptyp : valid_fpstate; variable ufract : UNSIGNED (fraction_width downto 0); -- unsigned fraction begin fptyp := Classfp (arg, check_error); sign := to_x01(arg(arg'high)); break_number ( arg => arg, fptyp => fptyp, denormalize => denormalize, fract => ufract, expon => expon); fract (0 downto -fraction_width) := ufixed (ufract); end procedure break_number; -- Arithmetic functions function "abs" ( arg : UNRESOLVED_float) -- floating point input return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); -- result begin if (arg'length > 0) then result := to_01 (arg, 'X'); result (arg'high) := '0'; -- set the sign bit to positive return result; else return NAFP; end if; end function "abs"; -- IEEE 754 "negative" function function "-" ( arg : UNRESOLVED_float) -- floating point input return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); -- result begin if (arg'length > 0) then result := to_01 (arg, 'X'); result (arg'high) := not result (arg'high); -- invert sign bit return result; else return NAFP; end if; end function "-"; -- Addition, adds two floating point numbers function add ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant addguard : NATURAL := guard; -- add one guard bit variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable fractl, fractr : UNSIGNED (fraction_width+1+addguard downto 0); -- fractions variable fractc, fracts : UNSIGNED (fractl'range); -- constant and shifted variables variable urfract, ulfract : UNSIGNED (fraction_width downto 0); variable ufract : UNSIGNED (fraction_width+1+addguard downto 0); variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width downto 0); -- result exponent variable shiftx : SIGNED (exponent_width downto 0); -- shift fractions variable sign : STD_ULOGIC; -- sign of the output variable leftright : BOOLEAN; -- left or right used variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); variable sticky : STD_ULOGIC; -- Holds precision for rounding begin -- addition if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan) -- Return quiet NAN, IEEE754-1985-7.1,1 or (lfptype = pos_inf and rfptype = neg_inf) or (lfptype = neg_inf and rfptype = pos_inf) then -- Return quiet NAN, IEEE754-1985-7.1,2 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = pos_inf or rfptype = pos_inf) then -- x + inf = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = neg_inf or rfptype = neg_inf) then -- x - inf = -inf fpresult := neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = neg_zero and rfptype = neg_zero) then -- -0 + -0 = -0 fpresult := neg_zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); fractl := (others => '0'); fractl (fraction_width+addguard downto addguard) := ulfract; break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); fractr := (others => '0'); fractr (fraction_width+addguard downto addguard) := urfract; shiftx := (exponl(exponent_width-1) & exponl) - exponr; if shiftx < -fractl'high then rexpon := exponr(exponent_width-1) & exponr; fractc := fractr; fracts := (others => '0'); -- add zero leftright := false; sticky := or (fractl); elsif shiftx < 0 then shiftx := - shiftx; fracts := shift_right (fractl, to_integer(shiftx)); fractc := fractr; rexpon := exponr(exponent_width-1) & exponr; leftright := false; -- sticky := or (fractl (to_integer(shiftx) downto 0)); sticky := smallfract (fractl, to_integer(shiftx)); elsif shiftx = 0 then rexpon := exponl(exponent_width-1) & exponl; sticky := '0'; if fractr > fractl then fractc := fractr; fracts := fractl; leftright := false; else fractc := fractl; fracts := fractr; leftright := true; end if; elsif shiftx > fractr'high then rexpon := exponl(exponent_width-1) & exponl; fracts := (others => '0'); -- add zero fractc := fractl; leftright := true; sticky := or (fractr); elsif shiftx > 0 then fracts := shift_right (fractr, to_integer(shiftx)); fractc := fractl; rexpon := exponl(exponent_width-1) & exponl; leftright := true; -- sticky := or (fractr (to_integer(shiftx) downto 0)); sticky := smallfract (fractr, to_integer(shiftx)); end if; -- add fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB if l(l'high) = r(r'high) then ufract := fractc + fracts; sign := l(l'high); else -- signs are different ufract := fractc - fracts; -- always positive result if leftright then -- Figure out which sign to use sign := l(l'high); else sign := r(r'high); end if; end if; if or (ufract) = '0' then sign := '0'; -- IEEE 854, 6.3, paragraph 2. end if; -- normalize fpresult := normalize (fract => ufract, expon => rexpon, sign => sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => addguard); end if; return fpresult; end function add; -- Subtraction, Calls "add". function subtract ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable negr : UNRESOLVED_float (r'range); -- negative version of r begin negr := -r; -- r := -r return add (l => l, r => negr, round_style => round_style, guard => guard, check_error => check_error, denormalize => denormalize); end function subtract; -- Floating point multiply function multiply ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant multguard : NATURAL := guard; -- guard bits variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction variable sfract : UNSIGNED (fraction_width+1+multguard downto 0); -- result fraction variable shifty : INTEGER; -- denormal shift variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent variable fp_sign : STD_ULOGIC; -- sign of result variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); variable sticky : STD_ULOGIC; -- Holds precision for rounding begin -- multiply if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif ((lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan)) then -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (((lfptype = pos_inf or lfptype = neg_inf) and (rfptype = pos_zero or rfptype = neg_zero)) or ((rfptype = pos_inf or rfptype = neg_inf) and (lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf -- Return quiet NAN, IEEE754-1985-7.1,3 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = pos_inf or rfptype = pos_inf or lfptype = neg_inf or rfptype = neg_inf) then -- x * inf = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); -- figure out the sign fp_sign := l(l'high) xor r(r'high); -- figure out the sign fpresult (exponent_width) := fp_sign; else fp_sign := l(l'high) xor r(r'high); -- figure out the sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => fractl, expon => exponl); break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => fractr, expon => exponr); if (rfptype = pos_denormal or rfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractr, '1'); fractr := shift_left (fractr, shifty); elsif (lfptype = pos_denormal or lfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractl, '1'); fractl := shift_left (fractl, shifty); else shifty := 0; -- Note that a denormal number * a denormal number is always zero. end if; -- multiply -- add the exponents rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1; rfract := fractl * fractr; -- Multiply the fraction sfract := rfract (rfract'high downto rfract'high - (fraction_width+1+multguard)); sticky := or (rfract (rfract'high-(fraction_width+1+multguard) downto 0)); -- normalize fpresult := normalize (fract => sfract, expon => rexpon, sign => fp_sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => multguard); end if; return fpresult; end function multiply; function short_divide ( lx, rx : UNSIGNED) return UNSIGNED is -- This is a special divider for the floating point routines. -- For a true unsigned divider, "stages" needs to = lx'high constant stages : INTEGER := lx'high - rx'high; -- number of stages variable partial : UNSIGNED (lx'range); variable q : UNSIGNED (stages downto 0); variable partial_argl : SIGNED (rx'high + 2 downto 0); variable partial_arg : SIGNED (rx'high + 2 downto 0); begin partial := lx; for i in stages downto 0 loop partial_argl := resize ("0" & SIGNED (partial(lx'high downto i)), partial_argl'length); partial_arg := partial_argl - SIGNED ("0" & rx); if (partial_arg (partial_arg'high) = '1') then -- negative q(i) := '0'; else q(i) := '1'; partial (lx'high+i-stages downto lx'high+i-stages-rx'high) := UNSIGNED (partial_arg(rx'range)); end if; end loop; -- to make the output look like that of the unsigned IEEE divide. return resize (q, lx'length); end function short_divide; -- 1/X function. Needed for algorithm development. function reciprocal ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : NATURAL := arg'high; -- length of FP output exponent constant divguard : NATURAL := guard; -- guard bits function onedivy ( arg : UNSIGNED) return UNSIGNED is variable q : UNSIGNED((2*arg'high)+1 downto 0); variable one : UNSIGNED (q'range); begin one := (others => '0'); one(one'high) := '1'; q := short_divide (one, arg); -- Unsigned divide return resize (q, arg'length+1); end function onedivy; variable fptype : valid_fpstate; variable expon : SIGNED (exponent_width-1 downto 0); -- exponents variable denorm_offset : NATURAL range 0 to 2; variable fract : UNSIGNED (fraction_width downto 0); variable fractg : UNSIGNED (fraction_width+divguard downto 0); variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- reciprocal fptype := classfp(arg, check_error); classcase : case fptype is when isx => fpresult := (others => 'X'); when nan | quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf | neg_inf => -- 1/inf, return 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); when neg_zero | pos_zero => -- 1/0 report FLOAT_GENERIC_PKG'instance_name & "RECIPROCAL: Floating Point divide by zero" severity error; fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); when others => if (fptype = pos_denormal or fptype = neg_denormal) and ((arg (-1) or arg(-2)) /= '1') then -- 1/denormal = infinity, with the exception of 2**-expon_base fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fpresult (exponent_width) := to_x01 (arg (exponent_width)); else break_number ( arg => arg, fptyp => fptype, denormalize => denormalize, fract => fract, expon => expon); fractg := (others => '0'); if (fptype = pos_denormal or fptype = neg_denormal) then -- The reciprocal of a denormal number is typically zero, -- except for two special cases which are trapped here. if (to_x01(arg (-1)) = '1') then fractg (fractg'high downto divguard+1) := fract (fract'high-1 downto 0); -- Shift to not denormal denorm_offset := 1; -- add 1 to exponent compensate else -- arg(-2) = '1' fractg (fractg'high downto divguard+2) := fract (fract'high-2 downto 0); -- Shift to not denormal denorm_offset := 2; -- add 2 to exponent compensate end if; else fractg (fractg'high downto divguard) := fract; denorm_offset := 0; end if; expon := - expon - 3 + denorm_offset; sfract := onedivy (fractg); -- normalize fpresult := normalize (fract => sfract, expon => expon, sign => arg(exponent_width), sticky => '1', fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => divguard); end if; end case classcase; return fpresult; end function reciprocal; -- floating point division function divide ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant divguard : NATURAL := guard; -- division guard bits variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable ulfract, urfract : UNSIGNED (fraction_width downto 0); variable fractl : UNSIGNED ((2*(fraction_width+divguard)+1) downto 0); -- left variable fractr : UNSIGNED (fraction_width+divguard downto 0); -- right variable rfract : UNSIGNED (fractl'range); -- result fraction variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent variable fp_sign, sticky : STD_ULOGIC; -- sign of result variable shifty, shiftx : INTEGER; -- denormal number shift variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- divide if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; classcase : case rfptype is when isx => fpresult := (others => 'X'); when nan | quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf | neg_inf => if lfptype = pos_inf or lfptype = neg_inf -- inf / inf or lfptype = quiet_nan or lfptype = nan then -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else -- x / inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when pos_zero | neg_zero => if lfptype = pos_zero or lfptype = neg_zero -- 0 / 0 or lfptype = quiet_nan or lfptype = nan then -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else report float_generic_pkg'instance_name & "DIVIDE: Floating Point divide by zero" severity error; -- Infinity, define in 754-1985-7.2 fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when others => classcase2 : case lfptype is when isx => fpresult := (others => 'X'); when nan | quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf | neg_inf => -- inf / x = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult(exponent_width) := fp_sign; when pos_zero | neg_zero => -- 0 / X = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult(exponent_width) := fp_sign; when others => fp_sign := l(l'high) xor r(r'high); -- sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); -- right side break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); -- Compute the exponent rexpon := resize (exponl, rexpon'length) - exponr - 2; if (rfptype = pos_denormal or rfptype = neg_denormal) then -- Do the shifting here not after. That way we have a smaller -- shifter, and need a smaller divider, because the top -- bit in the divisor will always be a "1". shifty := fraction_width - find_leftmost(urfract, '1'); urfract := shift_left (urfract, shifty); rexpon := rexpon + shifty; end if; fractr := (others => '0'); fractr (fraction_width+divguard downto divguard) := urfract; if (lfptype = pos_denormal or lfptype = neg_denormal) then shiftx := fraction_width - find_leftmost(ulfract, '1'); ulfract := shift_left (ulfract, shiftx); rexpon := rexpon - shiftx; end if; fractl := (others => '0'); fractl (fractl'high downto fractl'high-fraction_width) := ulfract; -- divide rfract := short_divide (fractl, fractr); -- unsigned divide sfract := rfract (sfract'range); -- lower bits sticky := '1'; -- normalize fpresult := normalize (fract => sfract, expon => rexpon, sign => fp_sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => divguard); end case classcase2; end case classcase; return fpresult; end function divide; -- division by a power of 2 function dividebyp2 ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable ulfract, urfract : UNSIGNED (fraction_width downto 0); variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED(exponent_width downto 0); -- result exponent variable fp_sign : STD_ULOGIC; -- sign of result variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- divisionbyp2 if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; classcase : case rfptype is when isx => fpresult := (others => 'X'); when nan | quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf | neg_inf => if lfptype = pos_inf or lfptype = neg_inf then -- inf / inf -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else -- x / inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when pos_zero | neg_zero => if lfptype = pos_zero or lfptype = neg_zero then -- 0 / 0 -- Return quiet NAN, IEEE754-1985-7.1,4 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); else report FLOAT_GENERIC_PKG'instance_name & "DIVIDEBYP2: Floating Point divide by zero" severity error; -- Infinity, define in 754-1985-7.2 fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (fpresult'high) := fp_sign; -- sign end if; when others => classcase2 : case lfptype is when isx => fpresult := (others => 'X'); when nan | quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf | neg_inf => -- inf / x = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (exponent_width) := fp_sign; -- sign when pos_zero | neg_zero => -- 0 / X = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); fp_sign := l(l'high) xor r(r'high); -- sign fpresult (exponent_width) := fp_sign; -- sign when others => fp_sign := l(l'high) xor r(r'high); -- sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); -- right side break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); assert (or (urfract (fraction_width-1 downto 0)) = '0') report FLOAT_GENERIC_PKG'instance_name & "DIVIDEBYP2: " & "Dividebyp2 called with a non power of two divisor" severity error; rexpon := (exponl(exponl'high)&exponl) - (exponr(exponr'high)&exponr) - 1; -- normalize fpresult := normalize (fract => ulfract, expon => rexpon, sign => fp_sign, sticky => '1', fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => 0); end case classcase2; end case classcase; return fpresult; end function dividebyp2; -- Multiply accumulate result = l*r + c function mac ( l, r, c : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine (mine(l'low, r'low), c'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum (maximum(l'high, r'high), c'high); -- length of FP output exponent variable lfptype, rfptype, cfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions variable fractx : UNSIGNED (fraction_width+guard downto 0); variable fractc, fracts : UNSIGNED (fraction_width+1+guard downto 0); variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction variable sfract, ufract : UNSIGNED (fraction_width+1+guard downto 0); -- result fraction variable exponl, exponr, exponc : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon, rexpon2 : SIGNED (exponent_width+1 downto 0); -- result exponent variable shifty : INTEGER; -- denormal shift variable shiftx : SIGNED (rexpon'range); -- shift fractions variable fp_sign : STD_ULOGIC; -- sign of result variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); variable cresize : UNRESOLVED_float (exponent_width downto -fraction_width - guard); variable leftright : BOOLEAN; -- left or right used variable sticky : STD_ULOGIC; -- Holds precision for rounding begin -- multiply if (fraction_width = 0 or l'length < 7 or r'length < 7 or c'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); cfptype := classfp (c, check_error); end if; if (lfptype = isx or rfptype = isx or cfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan or cfptype = nan or cfptype = quiet_nan) then -- Return quiet NAN, IEEE754-1985-7.1,1 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (((lfptype = pos_inf or lfptype = neg_inf) and (rfptype = pos_zero or rfptype = neg_zero)) or ((rfptype = pos_inf or rfptype = neg_inf) and (lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf -- Return quiet NAN, IEEE754-1985-7.1,3 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (lfptype = pos_inf or rfptype = pos_inf or lfptype = neg_inf or rfptype = neg_inf -- x * inf = inf or cfptype = neg_inf or cfptype = pos_inf) then -- x + inf = inf fpresult := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); -- figure out the sign fpresult (exponent_width) := l(l'high) xor r(r'high); else fp_sign := l(l'high) xor r(r'high); -- figure out the sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked cresize := resize (arg => to_x01(c), exponent_width => exponent_width, fraction_width => -cresize'low, denormalize_in => denormalize, denormalize => denormalize); cfptype := classfp (cresize, false); -- errors already checked break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => fractl, expon => exponl); break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => fractr, expon => exponr); break_number ( arg => cresize, fptyp => cfptype, denormalize => denormalize, fract => fractx, expon => exponc); if (rfptype = pos_denormal or rfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractr, '1'); fractr := shift_left (fractr, shifty); elsif (lfptype = pos_denormal or lfptype = neg_denormal) then shifty := fraction_width - find_leftmost(fractl, '1'); fractl := shift_left (fractl, shifty); else shifty := 0; -- Note that a denormal number * a denormal number is always zero. end if; -- multiply rfract := fractl * fractr; -- Multiply the fraction -- add the exponents rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1; shiftx := rexpon - exponc; if shiftx < -fractl'high then rexpon2 := resize (exponc, rexpon2'length); fractc := "0" & fractx; fracts := (others => '0'); sticky := or (rfract); elsif shiftx < 0 then shiftx := - shiftx; fracts := shift_right (rfract (rfract'high downto rfract'high - fracts'length+1), to_integer(shiftx)); fractc := "0" & fractx; rexpon2 := resize (exponc, rexpon2'length); leftright := false; sticky := or (rfract (to_integer(shiftx)+rfract'high - fracts'length downto 0)); elsif shiftx = 0 then rexpon2 := resize (exponc, rexpon2'length); sticky := or (rfract (rfract'high - fractc'length downto 0)); if rfract (rfract'high downto rfract'high - fractc'length+1) > fractx then fractc := "0" & fractx; fracts := rfract (rfract'high downto rfract'high - fracts'length+1); leftright := false; else fractc := rfract (rfract'high downto rfract'high - fractc'length+1); fracts := "0" & fractx; leftright := true; end if; elsif shiftx > fractx'high then rexpon2 := rexpon; fracts := (others => '0'); fractc := rfract (rfract'high downto rfract'high - fractc'length+1); leftright := true; sticky := or (fractx & rfract (rfract'high - fractc'length downto 0)); else -- fractx'high > shiftx > 0 rexpon2 := rexpon; fracts := "0" & shift_right (fractx, to_integer (shiftx)); fractc := rfract (rfract'high downto rfract'high - fractc'length+1); leftright := true; sticky := or (fractx (to_integer (shiftx) downto 0) & rfract (rfract'high - fractc'length downto 0)); end if; fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB if fp_sign = to_X01(c(c'high)) then ufract := fractc + fracts; fp_sign := fp_sign; else -- signs are different ufract := fractc - fracts; -- always positive result if leftright then -- Figure out which sign to use fp_sign := fp_sign; else fp_sign := c(c'high); end if; end if; -- normalize fpresult := normalize (fract => ufract, expon => rexpon2, sign => fp_sign, sticky => sticky, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => guard); end if; return fpresult; end function mac; -- "rem" function function remainder ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent constant divguard : NATURAL := guard; -- division guard bits variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable ulfract, urfract : UNSIGNED (fraction_width downto 0); variable fractr, fractl : UNSIGNED (fraction_width+divguard downto 0); -- right variable rfract : UNSIGNED (fractr'range); -- result fraction variable sfract : UNSIGNED (fraction_width+divguard downto 0); -- result fraction variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents variable rexpon : SIGNED (exponent_width downto 0); -- result exponent variable fp_sign : STD_ULOGIC; -- sign of result variable shifty : INTEGER; -- denormal number shift variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- remainder if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan) or (rfptype = nan or rfptype = quiet_nan) -- Return quiet NAN, IEEE754-1985-7.1,1 or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x -- Return quiet NAN, IEEE754-1985-7.1,5 or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0 -- Return quiet NAN, IEEE754-1985-7.1,5 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (abs(l) < abs(r)) then fpresult := l; else fp_sign := to_X01(l(l'high)); -- sign lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); lfptype := classfp (lresize, false); -- errors already checked rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rfptype := classfp (rresize, false); -- errors already checked fractl := (others => '0'); break_number ( arg => lresize, fptyp => lfptype, denormalize => denormalize, fract => ulfract, expon => exponl); fractl (fraction_width+divguard downto divguard) := ulfract; -- right side fractr := (others => '0'); break_number ( arg => rresize, fptyp => rfptype, denormalize => denormalize, fract => urfract, expon => exponr); fractr (fraction_width+divguard downto divguard) := urfract; rexpon := (exponr(exponr'high)&exponr); shifty := to_integer(exponl - rexpon); if (shifty > 0) then fractr := shift_right (fractr, shifty); rexpon := rexpon + shifty; end if; if (fractr /= 0) then -- rem rfract := fractl rem fractr; -- unsigned rem sfract := rfract (sfract'range); -- lower bits -- normalize fpresult := normalize (fract => sfract, expon => rexpon, sign => fp_sign, fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => divguard); else -- If we shift "fractr" so far that it becomes zero, return zero. fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); end if; end if; return fpresult; end function remainder; -- "mod" function function modulo ( l, r : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant guard : NATURAL := float_guard_bits; -- number of guard bits constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := - mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width); variable remres : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- remainder if (fraction_width = 0 or l'length < 7 or r'length < 7) then lfptype := isx; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = isx or rfptype = isx) then fpresult := (others => 'X'); elsif (lfptype = nan or lfptype = quiet_nan) or (rfptype = nan or rfptype = quiet_nan) -- Return quiet NAN, IEEE754-1985-7.1,1 or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x -- Return quiet NAN, IEEE754-1985-7.1,5 or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0 -- Return quiet NAN, IEEE754-1985-7.1,5 fpresult := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0 fpresult := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else remres := remainder (l => abs(l), r => abs(r), round_style => round_style, guard => guard, check_error => false, denormalize => denormalize); -- MOD is the same as REM, but you do something different with -- negative values if (is_negative (l)) then remres := - remres; end if; if (is_negative (l) = is_negative (r) or remres = 0) then fpresult := remres; else fpresult := add (l => remres, r => r, round_style => round_style, guard => guard, check_error => false, denormalize => denormalize); end if; end if; return fpresult; end function modulo; -- Square root of a floating point number. Done using Newton's Iteration. function sqrt ( arg : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; constant guard : NATURAL := float_guard_bits; constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_float is constant fraction_width : NATURAL := guard-arg'low; -- length of FP output fraction constant exponent_width : NATURAL := arg'high; -- length of FP output exponent variable sign : STD_ULOGIC; variable fpresult : float (arg'range); variable fptype : valid_fpstate; variable iexpon : SIGNED(exponent_width-1 downto 0); -- exponents variable expon : SIGNED(exponent_width downto 0); -- exponents variable ufact : ufixed (0 downto arg'low); variable fact : ufixed (2 downto -fraction_width); -- fraction variable resb : ufixed (fact'high+1 downto fact'low); begin -- square root fptype := Classfp (arg, check_error); classcase : case fptype is when isx => fpresult := (others => 'X'); when nan | quiet_nan | -- Return quiet NAN, IEEE754-1985-7.1,1 neg_normal | neg_denormal | neg_inf => -- sqrt (neg) -- Return quiet NAN, IEEE754-1985-7.1.6 fpresult := qnanfp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when pos_inf => -- Sqrt (inf), return infinity fpresult := pos_inffp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when pos_zero => -- return 0 fpresult := zerofp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when neg_zero => -- IEEE754-1985-6.3 return -0 fpresult := neg_zerofp (fraction_width => fraction_width-guard, exponent_width => exponent_width); when others => break_number (arg => arg, denormalize => denormalize, check_error => false, fract => ufact, expon => iexpon, sign => sign); expon := resize (iexpon+1, expon'length); -- get exponent fact := resize (ufact, fact'high, fact'low); if (expon(0) = '1') then fact := fact sla 1; -- * 2.0 end if; expon := shift_right (expon, 1); -- exponent/2 -- Newton's iteration - root := (1 + arg) / 2 resb := (fact + 1) sra 1; for j in 0 to fraction_width/4 loop -- root := (root + (arg/root))/2 resb := resize (arg => (resb + (fact/resb)) sra 1, left_index => resb'high, right_index => resb'low, round_style => fixed_truncate, overflow_style => fixed_wrap); end loop; fpresult := normalize (fract => resb, expon => expon-1, sign => '0', exponent_width => arg'high, fraction_width => -arg'low, round_style => round_style, denormalize => denormalize, nguard => guard); end case classcase; return fpresult; end function sqrt; function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN is -- Technically -0 should return "false", but I'm leaving that case out. begin return (to_x01(arg(arg'high)) = '1'); end function Is_Negative; -- compare functions -- =, /=, >=, <=, <, > function eq ( -- equal = l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable lfptype, rfptype : valid_fpstate; variable is_equal, is_unordered : BOOLEAN; constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- equal if (fraction_width = 0 or l'length < 7 or r'length < 7) then return false; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); end if; if (lfptype = neg_zero or lfptype = pos_zero) and (rfptype = neg_zero or rfptype = pos_zero) then is_equal := true; else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); is_equal := (to_slv(lresize) = to_slv(rresize)); end if; if (check_error) then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return is_equal and not is_unordered; end function eq; function lt ( -- less than < l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable expl, expr : UNSIGNED (exponent_width-1 downto 0); variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0); variable is_less_than, is_unordered : BOOLEAN; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then is_less_than := false; else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits expl := UNSIGNED(lresize(exponent_width-1 downto 0)); expr := UNSIGNED(rresize(exponent_width-1 downto 0)); if expl = expr then fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width))); fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width))); if to_x01(l(l'high)) = '0' then -- positive number is_less_than := (fractl < fractr); else is_less_than := (fractl > fractr); -- negative end if; else if to_x01(l(l'high)) = '0' then -- positive number is_less_than := (expl < expr); else is_less_than := (expl > expr); -- negative end if; end if; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); if (lfptype = neg_zero and rfptype = pos_zero) then is_less_than := false; -- -0 < 0 returns false. else is_less_than := (to_x01(l(l'high)) > to_x01(r(r'high))); end if; end if; end if; if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return is_less_than and not is_unordered; end function lt; function gt ( -- greater than > l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable expl, expr : UNSIGNED (exponent_width-1 downto 0); variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0); variable is_greater_than : BOOLEAN; variable is_unordered : BOOLEAN; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- greater_than if (fraction_width = 0 or l'length < 7 or r'length < 7) then is_greater_than := false; else lresize := resize (arg => to_x01(l), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); rresize := resize (arg => to_x01(r), exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => denormalize, denormalize => denormalize); if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits expl := UNSIGNED(lresize(exponent_width-1 downto 0)); expr := UNSIGNED(rresize(exponent_width-1 downto 0)); if expl = expr then fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width))); fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width))); if to_x01(l(l'high)) = '0' then -- positive number is_greater_than := fractl > fractr; else is_greater_than := fractl < fractr; -- negative end if; else if to_x01(l(l'high)) = '0' then -- positive number is_greater_than := expl > expr; else is_greater_than := expl < expr; -- negative end if; end if; else lfptype := classfp (l, check_error); rfptype := classfp (r, check_error); if (lfptype = pos_zero and rfptype = neg_zero) then is_greater_than := false; -- 0 > -0 returns false. else is_greater_than := to_x01(l(l'high)) < to_x01(r(r'high)); end if; end if; end if; if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return is_greater_than and not is_unordered; end function gt; -- purpose: /= function function ne ( -- not equal /= l, r : UNRESOLVED_float; constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable is_equal, is_unordered : BOOLEAN; begin is_equal := eq (l => l, r => r, check_error => false, denormalize => denormalize); if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return not (is_equal and not is_unordered); end function ne; function le ( -- less than or equal to <= l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable is_greater_than, is_unordered : BOOLEAN; begin is_greater_than := gt (l => l, r => r, check_error => false, denormalize => denormalize); if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return not is_greater_than and not is_unordered; end function le; function ge ( -- greater than or equal to >= l, r : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; constant denormalize : BOOLEAN := float_denormalize) return BOOLEAN is variable is_less_than, is_unordered : BOOLEAN; begin is_less_than := lt (l => l, r => r, check_error => false, denormalize => denormalize); if check_error then is_unordered := Unordered (x => l, y => r); else is_unordered := false; end if; return not is_less_than and not is_unordered; end function ge; function "?=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable is_equal, is_unordered : STD_ULOGIC; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- ?= if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else lfptype := classfp (l, float_check_error); rfptype := classfp (r, float_check_error); end if; if (lfptype = neg_zero or lfptype = pos_zero) and (rfptype = neg_zero or rfptype = pos_zero) then is_equal := '1'; else lresize := resize (arg => l, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); rresize := resize (arg => r, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); is_equal := to_sulv(lresize) ?= to_sulv(rresize); end if; if (float_check_error) then if (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan) then is_unordered := '1'; else is_unordered := '0'; end if; else is_unordered := '0'; end if; return is_equal and not is_unordered; end function "?="; function "?/=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lfptype, rfptype : valid_fpstate; variable is_equal, is_unordered : STD_ULOGIC; variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- ?/= if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else lfptype := classfp (l, float_check_error); rfptype := classfp (r, float_check_error); end if; if (lfptype = neg_zero or lfptype = pos_zero) and (rfptype = neg_zero or rfptype = pos_zero) then is_equal := '1'; else lresize := resize (arg => l, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); rresize := resize (arg => r, exponent_width => exponent_width, fraction_width => fraction_width, denormalize_in => float_denormalize, denormalize => float_denormalize); is_equal := to_sulv(lresize) ?= to_sulv(rresize); end if; if (float_check_error) then if (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan) then is_unordered := '1'; else is_unordered := '0'; end if; else is_unordered := '0'; end if; return not (is_equal and not is_unordered); end function "?/="; function "?>" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?>"": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l > r then return '1'; else return '0'; end if; end if; end function "?>"; function "?>=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?>="": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l >= r then return '1'; else return '0'; end if; end if; end function "?>="; function "?<" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?<"": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l < r then return '1'; else return '0'; end if; end if; end function "?<"; function "?<=" (L, R : UNRESOLVED_float) return STD_ULOGIC is constant fraction_width : NATURAL := -mine(l'low, r'low); variable founddash : BOOLEAN := false; begin if (fraction_width = 0 or l'length < 7 or r'length < 7) then return 'X'; else for i in L'range loop if L(i) = '-' then founddash := true; end if; end loop; for i in R'range loop if R(i) = '-' then founddash := true; end if; end loop; if founddash then report float_generic_pkg'instance_name & " ""?<="": '-' found in compare string" severity error; return 'X'; elsif is_x(l) or is_x(r) then return 'X'; elsif l <= r then return '1'; else return '0'; end if; end if; end function "?<="; function std_match (L, R : UNRESOLVED_float) return BOOLEAN is begin if (L'high = R'high and L'low = R'low) then return std_match(to_sulv(L), to_sulv(R)); else report float_generic_pkg'instance_name & "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE" severity warning; return false; end if; end function std_match; function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is begin for_loop : for i in arg'reverse_range loop if arg(i) ?= y then return i; end if; end loop; return arg'high+1; -- return out of bounds 'high end function find_rightmost; function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is begin for_loop : for i in arg'range loop if arg(i) ?= y then return i; end if; end loop; return arg'low-1; -- return out of bounds 'low end function find_leftmost; -- These override the defaults for the compare operators. function "=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return eq(l, r); end function "="; function "/=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return ne(l, r); end function "/="; function ">=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return ge(l, r); end function ">="; function "<=" (l, r : UNRESOLVED_float) return BOOLEAN is begin return le(l, r); end function "<="; function ">" (l, r : UNRESOLVED_float) return BOOLEAN is begin return gt(l, r); end function ">"; function "<" (l, r : UNRESOLVED_float) return BOOLEAN is begin return lt(l, r); end function "<"; -- purpose: maximum of two numbers (overrides default) function maximum ( L, R : UNRESOLVED_float) return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin if ((L'length < 1) or (R'length < 1)) then return NAFP; end if; lresize := resize (l, exponent_width, fraction_width); rresize := resize (r, exponent_width, fraction_width); if lresize > rresize then return lresize; else return rresize; end if; end function maximum; function minimum ( L, R : UNRESOLVED_float) return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width); begin if ((L'length < 1) or (R'length < 1)) then return NAFP; end if; lresize := resize (l, exponent_width, fraction_width); rresize := resize (r, exponent_width, fraction_width); if lresize > rresize then return rresize; else return lresize; end if; end function minimum; ----------------------------------------------------------------------------- -- conversion functions ----------------------------------------------------------------------------- -- Converts a floating point number of one format into another format function resize ( arg : UNRESOLVED_float; -- Floating point input constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant in_fraction_width : NATURAL := -arg'low; -- length of FP output fraction constant in_exponent_width : NATURAL := arg'high; -- length of FP output exponent variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result value variable fptype : valid_fpstate; variable expon_in : SIGNED (in_exponent_width-1 downto 0); variable fract_in : UNSIGNED (in_fraction_width downto 0); variable round : BOOLEAN; variable expon_out : SIGNED (exponent_width-1 downto 0); -- output fract variable fract_out : UNSIGNED (fraction_width downto 0); -- output fract variable passguard : NATURAL; begin fptype := classfp(arg, check_error); if ((fptype = pos_denormal or fptype = neg_denormal) and denormalize_in and (in_exponent_width < exponent_width or in_fraction_width < fraction_width)) or in_exponent_width > exponent_width or in_fraction_width > fraction_width then -- size reduction classcase : case fptype is when isx => result := (others => 'X'); when nan | quiet_nan => result := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_inf => result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); when neg_inf => result := neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); when pos_zero | neg_zero => result := zerofp (fraction_width => fraction_width, -- hate -0 exponent_width => exponent_width); when others => break_number ( arg => arg, fptyp => fptype, denormalize => denormalize_in, fract => fract_in, expon => expon_in); if fraction_width > in_fraction_width and denormalize_in then -- You only get here if you have a denormal input fract_out := (others => '0'); -- pad with zeros fract_out (fraction_width downto fraction_width - in_fraction_width) := fract_in; result := normalize ( fract => fract_out, expon => expon_in, sign => arg(arg'high), fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => 0); else result := normalize ( fract => fract_in, expon => expon_in, sign => arg(arg'high), fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => in_fraction_width - fraction_width); end if; end case classcase; else -- size increase or the same size if exponent_width > in_exponent_width then expon_in := SIGNED(arg (in_exponent_width-1 downto 0)); if fptype = pos_zero or fptype = neg_zero then result (exponent_width-1 downto 0) := (others => '0'); elsif expon_in = -1 then -- inf or nan (shorts out check_error) result (exponent_width-1 downto 0) := (others => '1'); else -- invert top BIT expon_in(expon_in'high) := not expon_in(expon_in'high); expon_out := resize (expon_in, expon_out'length); -- signed expand -- Flip it back. expon_out(expon_out'high) := not expon_out(expon_out'high); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon_out); end if; result (exponent_width) := arg (in_exponent_width); -- sign else -- exponent_width = in_exponent_width result (exponent_width downto 0) := arg (in_exponent_width downto 0); end if; if fraction_width > in_fraction_width then result (-1 downto -fraction_width) := (others => '0'); -- zeros result (-1 downto -in_fraction_width) := arg (-1 downto -in_fraction_width); else -- fraction_width = in_fraciton_width result (-1 downto -fraction_width) := arg (-1 downto -in_fraction_width); end if; end if; return result; end function resize; function resize ( arg : UNRESOLVED_float; -- floating point input size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := resize (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); return result; end if; end function resize; function to_float32 ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float32 is begin return resize (arg => arg, exponent_width => float32'high, fraction_width => -float32'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); end function to_float32; function to_float64 ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float64 is begin return resize (arg => arg, exponent_width => float64'high, fraction_width => -float64'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); end function to_float64; function to_float128 ( arg : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float128 is begin return resize (arg => arg, exponent_width => float128'high, fraction_width => -float128'low, round_style => round_style, check_error => check_error, denormalize_in => denormalize_in, denormalize => denormalize); end function to_float128; -- to_float (Real) -- typically not Synthesizable unless the input is a constant. function to_float ( arg : REAL; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arg_real : REAL; -- Real version of argument variable validfp : boundary_type; -- Check for valid results variable exp : INTEGER; -- Integer version of exponent variable expon : UNSIGNED (exponent_width - 1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fract : UNSIGNED (fraction_width-1 downto 0); variable frac : REAL; -- Real version of fraction constant roundfrac : REAL := 2.0 ** (-2 - fract'high); -- used for rounding variable round : BOOLEAN; -- to round or not to round begin result := (others => '0'); arg_real := arg; if arg_real < 0.0 then result (exponent_width) := '1'; arg_real := - arg_real; -- Make it positive. else result (exponent_width) := '0'; end if; test_boundary (arg => arg_real, fraction_width => fraction_width, exponent_width => exponent_width, denormalize => denormalize, btype => validfp, log2i => exp); if validfp = zero then return result; -- Result initialized to "0". elsif validfp = infinity then result (exponent_width - 1 downto 0) := (others => '1'); -- Exponent all "1" -- return infinity. return result; else if validfp = denormal then -- Exponent will default to "0". expon := (others => '0'); frac := arg_real * (2.0 ** (to_integer(expon_base)-1)); else -- Number less than 1. "normal" number expon := UNSIGNED (to_signed (exp-1, exponent_width)); expon(exponent_width-1) := not expon(exponent_width-1); frac := (arg_real / 2.0 ** exp) - 1.0; -- Number less than 1. end if; for i in 0 to fract'high loop if frac >= 2.0 ** (-1 - i) then fract (fract'high - i) := '1'; frac := frac - 2.0 ** (-1 - i); else fract (fract'high - i) := '0'; end if; end loop; round := false; case round_style is when round_nearest => if frac > roundfrac or ((frac = roundfrac) and fract(0) = '1') then round := true; end if; when round_inf => if frac /= 0.0 and result(exponent_width) = '0' then round := true; end if; when round_neginf => if frac /= 0.0 and result(exponent_width) = '1' then round := true; end if; when others => null; -- don't round end case; if (round) then if and(fract) = '1' then -- fraction is all "1" expon := expon + 1; fract := (others => '0'); else fract := fract + 1; end if; end if; result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(fract); return result; end if; end function to_float; -- to_float (Integer) function to_float ( arg : INTEGER; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arg_int : NATURAL; -- Natural version of argument variable expon : SIGNED (exponent_width-1 downto 0); variable exptmp : SIGNED (exponent_width-1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fract : UNSIGNED (fraction_width-1 downto 0) := (others => '0'); variable fracttmp : UNSIGNED (fraction_width-1 downto 0); variable round : BOOLEAN; variable shift : NATURAL; variable shiftr : NATURAL; variable roundfrac : NATURAL; -- used in rounding begin if arg < 0 then result (exponent_width) := '1'; arg_int := -arg; -- Make it positive. else result (exponent_width) := '0'; arg_int := arg; end if; if arg_int = 0 then result := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else -- If the number is larger than we can represent in this number system -- we need to return infinity. shift := log2(arg_int); if shift > to_integer(expon_base) then -- worry about infinity if result (exponent_width) = '0' then result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else -- return negative infinity. result := neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); end if; else -- Normal number (can't be denormal) -- Compute Exponent expon := to_signed (shift-1, expon'length); -- positive fraction. -- Compute Fraction arg_int := arg_int - 2**shift; -- Subtract off the 1.0 shiftr := shift; for I in fract'high downto maximum (fract'high - shift + 1, 0) loop shiftr := shiftr - 1; if (arg_int >= 2**shiftr) then arg_int := arg_int - 2**shiftr; fract(I) := '1'; else fract(I) := '0'; end if; end loop; -- Rounding routine round := false; if arg_int > 0 then roundfrac := 2**(shiftr-1); case round_style is when round_nearest => if arg_int > roundfrac or ((arg_int = roundfrac) and fract(0) = '1') then round := true; end if; when round_inf => if arg_int /= 0 and result (exponent_width) = '0' then round := true; end if; when round_neginf => if arg_int /= 0 and result (exponent_width) = '1' then round := true; end if; when others => null; end case; end if; if round then fp_round(fract_in => fract, expon_in => expon, fract_out => fracttmp, expon_out => exptmp); fract := fracttmp; expon := exptmp; end if; -- Put the number together and return expon(exponent_width-1) := not expon(exponent_width-1); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(fract); end if; end if; return result; end function to_float; -- to_float (unsigned) function to_float ( arg : UNRESOLVED_UNSIGNED; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG; variable sarg : SIGNED (ARG_LEFT+1 downto 0); -- signed version of arg begin if arg'length < 1 then return NAFP; end if; sarg (XARG'range) := SIGNED (XARG); sarg (sarg'high) := '0'; result := to_float (arg => sarg, exponent_width => exponent_width, fraction_width => fraction_width, round_style => round_style); return result; end function to_float; -- to_float (signed) function to_float ( arg : UNRESOLVED_SIGNED; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : SIGNED(ARG_LEFT downto 0) is ARG; variable arg_int : UNSIGNED(xarg'range); -- Real version of argument variable argb2 : UNSIGNED(xarg'high/2 downto 0); -- log2 of input variable rexp : SIGNED (exponent_width - 1 downto 0); variable exp : SIGNED (exponent_width - 1 downto 0); -- signed version of exp. variable expon : UNSIGNED (exponent_width - 1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable round : BOOLEAN; variable fract : UNSIGNED (fraction_width-1 downto 0); variable rfract : UNSIGNED (fraction_width-1 downto 0); variable sign : STD_ULOGIC; -- sign bit begin if arg'length < 1 then return NAFP; end if; if Is_X (xarg) then result := (others => 'X'); elsif (xarg = 0) then result := zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else -- Normal number (can't be denormal) sign := to_X01(xarg (xarg'high)); arg_int := UNSIGNED(abs (to_01(xarg))); -- Compute Exponent argb2 := to_unsigned(find_leftmost(arg_int, '1'), argb2'length); -- Log2 if argb2 > UNSIGNED(expon_base) then result := pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); result (exponent_width) := sign; else exp := SIGNED(resize(argb2, exp'length)); arg_int := shift_left (arg_int, arg_int'high-to_integer(exp)); if (arg_int'high > fraction_width) then fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)); round := check_round ( fract_in => fract (0), sign => sign, remainder => arg_int((arg_int'high-fraction_width-1) downto 0), round_style => round_style); if round then fp_round(fract_in => fract, expon_in => exp, fract_out => rfract, expon_out => rexp); else rfract := fract; rexp := exp; end if; else rexp := exp; rfract := (others => '0'); rfract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) := arg_int (arg_int'high-1 downto 0); end if; result (exponent_width) := sign; expon := UNSIGNED (rexp-1); expon(exponent_width-1) := not expon(exponent_width-1); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(rfract); end if; end if; return result; end function to_float; -- std_logic_vector to float function to_float ( arg : STD_ULOGIC_VECTOR; constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction return UNRESOLVED_float is variable fpvar : UNRESOLVED_float (exponent_width downto -fraction_width); begin if arg'length < 1 then return NAFP; end if; fpvar := UNRESOLVED_float(arg); return fpvar; end function to_float; -- purpose: converts a ufixed to a floating point function to_float ( arg : UNRESOLVED_ufixed; -- unsigned fixed point input constant exponent_width : NATURAL := float_exponent_width; -- width of exponent constant fraction_width : NATURAL := float_fraction_width; -- width of fraction constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions return UNRESOLVED_float is variable sarg : sfixed (arg'high+1 downto arg'low); -- Signed version of arg variable result : UNRESOLVED_float (exponent_width downto -fraction_width); begin -- function to_float if (arg'length < 1) then return NAFP; end if; sarg (arg'range) := sfixed (arg); sarg (sarg'high) := '0'; result := to_float (arg => sarg, exponent_width => exponent_width, fraction_width => fraction_width, round_style => round_style, denormalize => denormalize); return result; end function to_float; function to_float ( arg : UNRESOLVED_sfixed; -- signed fixed point constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- rounding option return UNRESOLVED_float is constant integer_width : INTEGER := arg'high; constant in_fraction_width : INTEGER := arg'low; variable xresult : sfixed (integer_width downto in_fraction_width); variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable arg_int : UNSIGNED(integer_width - in_fraction_width - 1 downto 0); -- signed version of argument variable argx : SIGNED (integer_width - in_fraction_width downto 0); variable exp, exptmp : SIGNED (exponent_width downto 0); variable expon : UNSIGNED (exponent_width - 1 downto 0); -- Unsigned version of exp. constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) := (others => '0'); variable round : BOOLEAN := false; begin if (arg'length < 1) then return NAFP; end if; xresult := to_01(arg, 'X'); argx := SIGNED(to_slv(xresult)); if (Is_X (arg)) then result := (others => 'X'); elsif (argx = 0) then result := (others => '0'); else result := (others => '0'); -- zero out the result if argx(argx'left) = '1' then -- toss the sign bit result (exponent_width) := '1'; -- Negative number argx := -argx; -- Make it positive. else result (exponent_width) := '0'; end if; arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (argx(arg_int'range)))); -- Compute Exponent exp := to_signed(find_leftmost(arg_int, '1'), exp'length); -- Log2 if exp + in_fraction_width > expon_base then -- return infinity result (-1 downto -fraction_width) := (others => '0'); result (exponent_width -1 downto 0) := (others => '1'); return result; elsif (denormalize and (exp + in_fraction_width <= -resize(expon_base, exp'length))) then exp := -resize(expon_base, exp'length); -- shift by a constant arg_int := shift_left (arg_int, (arg_int'high + to_integer(expon_base) + in_fraction_width - 1)); if (arg_int'high > fraction_width) then fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)); round := check_round ( fract_in => arg_int(arg_int'high-fraction_width), sign => result(result'high), remainder => arg_int((arg_int'high-fraction_width-1) downto 0), round_style => round_style); if (round) then fp_round (fract_in => arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)), expon_in => exp, fract_out => fract, expon_out => exptmp); exp := exptmp; end if; else fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) := arg_int (arg_int'high-1 downto 0); end if; else arg_int := shift_left (arg_int, arg_int'high-to_integer(exp)); exp := exp + in_fraction_width; if (arg_int'high > fraction_width) then fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width)); round := check_round ( fract_in => fract(0), sign => result(result'high), remainder => arg_int((arg_int'high-fraction_width-1) downto 0), round_style => round_style); if (round) then fp_round (fract_in => fract, expon_in => exp, fract_out => fracttmp, expon_out => exptmp); fract := fracttmp; exp := exptmp; end if; else fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) := arg_int (arg_int'high-1 downto 0); end if; end if; expon := UNSIGNED (resize(exp-1, exponent_width)); expon(exponent_width-1) := not expon(exponent_width-1); result (exponent_width-1 downto 0) := UNRESOLVED_float(expon); result (-1 downto -fraction_width) := UNRESOLVED_float(fract); end if; return result; end function to_float; -- size_res functions -- Integer to float function to_float ( arg : INTEGER; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style); return result; end if; end function to_float; -- real to float function to_float ( arg : REAL; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding option constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, denormalize => denormalize); return result; end if; end function to_float; -- unsigned to float function to_float ( arg : UNRESOLVED_UNSIGNED; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style); return result; end if; end function to_float; -- signed to float function to_float ( arg : UNRESOLVED_SIGNED; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style) -- rounding return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style); return result; end if; end function to_float; -- std_ulogic_vector to float function to_float ( arg : STD_ULOGIC_VECTOR; size_res : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low); return result; end if; end function to_float; -- unsigned fixed point to float function to_float ( arg : UNRESOLVED_ufixed; -- unsigned fixed point input size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, denormalize => denormalize); return result; end if; end function to_float; -- signed fixed point to float function to_float ( arg : UNRESOLVED_sfixed; size_res : UNRESOLVED_float; constant round_style : round_type := float_round_style; -- rounding constant denormalize : BOOLEAN := float_denormalize) -- rounding option return UNRESOLVED_float is variable result : UNRESOLVED_float (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_float (arg => arg, exponent_width => size_res'high, fraction_width => -size_res'low, round_style => round_style, denormalize => denormalize); return result; end if; end function to_float; -- to_integer (float) function to_integer ( arg : UNRESOLVED_float; -- floating point input constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return INTEGER is variable validfp : valid_fpstate; -- Valid FP state variable frac : UNSIGNED (-arg'low downto 0); -- Fraction variable fract : UNSIGNED (1-arg'low downto 0); -- Fraction variable expon : SIGNED (arg'high-1 downto 0); variable isign : STD_ULOGIC; -- internal version of sign variable round : STD_ULOGIC; -- is rounding needed? variable result : INTEGER; variable base : INTEGER; -- Integer exponent begin validfp := classfp (arg, check_error); classcase : case validfp is when isx | nan | quiet_nan | pos_zero | neg_zero | pos_denormal | neg_denormal => result := 0; -- return 0 when pos_inf => result := INTEGER'high; when neg_inf => result := INTEGER'low; when others => break_number ( arg => arg, fptyp => validfp, denormalize => false, fract => frac, expon => expon); fract (fract'high) := '0'; -- Add extra bit for 0.6 case fract (fract'high-1 downto 0) := frac; isign := to_x01 (arg (arg'high)); base := to_integer (expon) + 1; if base < -1 then result := 0; elsif base >= frac'high then result := to_integer (fract) * 2**(base - frac'high); else -- We need to round if base = -1 then -- trap for 0.6 case. result := 0; else result := to_integer (fract (frac'high downto frac'high-base)); end if; -- rounding routine case round_style is when round_nearest => if frac'high - base > 1 then round := fract (frac'high - base - 1) and (fract (frac'high - base) or (or (fract (frac'high - base - 2 downto 0)))); else round := fract (frac'high - base - 1) and fract (frac'high - base); end if; when round_inf => round := fract(frac'high - base - 1) and not isign; when round_neginf => round := fract(frac'high - base - 1) and isign; when others => round := '0'; end case; if round = '1' then result := result + 1; end if; end if; if isign = '1' then result := - result; end if; end case classcase; return result; end function to_integer; -- to_unsigned (float) function to_unsigned ( arg : UNRESOLVED_float; -- floating point input constant size : NATURAL; -- length of output constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_UNSIGNED is variable validfp : valid_fpstate; -- Valid FP state variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction variable sign : STD_ULOGIC; -- not used begin validfp := classfp (arg, check_error); classcase : case validfp is when isx | nan | quiet_nan => frac := (others => 'X'); when pos_zero | neg_inf | neg_zero | neg_normal | pos_denormal | neg_denormal => frac := (others => '0'); -- return 0 when pos_inf => frac := (others => '1'); when others => float_to_unsigned ( arg => arg, frac => frac, sign => sign, denormalize => false, bias => 0, round_style => round_style); end case classcase; return (frac); end function to_unsigned; -- to_signed (float) function to_signed ( arg : UNRESOLVED_float; -- floating point input constant size : NATURAL; -- length of output constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_SIGNED is variable sign : STD_ULOGIC; -- true if negative variable validfp : valid_fpstate; -- Valid FP state variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction variable result : UNRESOLVED_SIGNED (size-1 downto 0); begin validfp := classfp (arg, check_error); classcase : case validfp is when isx | nan | quiet_nan => result := (others => 'X'); when pos_zero | neg_zero | pos_denormal | neg_denormal => result := (others => '0'); -- return 0 when pos_inf => result := (others => '1'); result (result'high) := '0'; when neg_inf => result := (others => '0'); result (result'high) := '1'; when others => float_to_unsigned ( arg => arg, sign => sign, frac => frac, denormalize => false, bias => 0, round_style => round_style); result (size-1) := '0'; result (size-2 downto 0) := UNRESOLVED_SIGNED(frac (size-2 downto 0)); if sign = '1' then -- Because the most negative signed number is 1 less than the most -- positive signed number, we need this code. if frac(frac'high) = '1' then -- return most negative number result := (others => '0'); result (result'high) := '1'; else result := -result; end if; else if frac(frac'high) = '1' then -- return most positive number result := (others => '1'); result (result'high) := '0'; end if; end if; end case classcase; return result; end function to_signed; -- purpose: Converts a float to ufixed function to_ufixed ( arg : UNRESOLVED_float; -- fp input constant left_index : INTEGER; -- integer part constant right_index : INTEGER; -- fraction part constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_ufixed is constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent constant size : INTEGER := left_index - right_index + 4; -- unsigned size variable expon_base : INTEGER; -- exponent offset variable validfp : valid_fpstate; -- Valid FP state variable exp : INTEGER; -- Exponent variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent -- Base to divide fraction by variable frac : UNSIGNED (size-1 downto 0) := (others => '0'); -- Fraction variable frac_shift : UNSIGNED (size-1 downto 0); -- Fraction shifted variable shift : INTEGER; variable result_big : UNRESOLVED_ufixed (left_index downto right_index-3); variable result : UNRESOLVED_ufixed (left_index downto right_index); -- result begin -- function to_ufixed validfp := classfp (arg, check_error); classcase : case validfp is when isx | nan | quiet_nan => frac := (others => 'X'); when pos_zero | neg_inf | neg_zero | neg_normal | neg_denormal => frac := (others => '0'); -- return 0 when pos_inf => frac := (others => '1'); -- always saturate when others => expon_base := 2**(exponent_width-1) -1; -- exponent offset -- Figure out the fraction if (validfp = pos_denormal) and denormalize then exp := -expon_base +1; frac (frac'high) := '0'; -- Remove the "1.0". else -- exponent /= '0', normal floating point expon := UNSIGNED(arg (exponent_width-1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (SIGNED(expon)) +1; frac (frac'high) := '1'; -- Add the "1.0". end if; shift := (frac'high - 3 + right_index) - exp; if fraction_width > frac'high then -- Can only use size-2 bits frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto -frac'high))); else -- can use all bits frac (frac'high-1 downto frac'high-fraction_width) := UNSIGNED (to_slv (arg(-1 downto -fraction_width))); end if; frac_shift := frac srl shift; if shift < 0 then -- Overflow frac := (others => '1'); else frac := frac_shift; end if; end case classcase; result_big := to_ufixed ( arg => STD_ULOGIC_VECTOR(frac), left_index => left_index, right_index => (right_index-3)); result := resize (arg => result_big, left_index => left_index, right_index => right_index, round_style => round_style, overflow_style => overflow_style); return result; end function to_ufixed; -- purpose: Converts a float to sfixed function to_sfixed ( arg : UNRESOLVED_float; -- fp input constant left_index : INTEGER; -- integer part constant right_index : INTEGER; -- fraction part constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_sfixed is constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent constant size : INTEGER := left_index - right_index + 4; -- unsigned size variable expon_base : INTEGER; -- exponent offset variable validfp : valid_fpstate; -- Valid FP state variable exp : INTEGER; -- Exponent variable sign : BOOLEAN; -- true if negative variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent -- Base to divide fraction by variable frac : UNSIGNED (size-2 downto 0) := (others => '0'); -- Fraction variable frac_shift : UNSIGNED (size-2 downto 0); -- Fraction shifted variable shift : INTEGER; variable rsigned : SIGNED (size-1 downto 0); -- signed version of result variable result_big : UNRESOLVED_sfixed (left_index downto right_index-3); variable result : UNRESOLVED_sfixed (left_index downto right_index) := (others => '0'); -- result begin -- function to_sfixed validfp := classfp (arg, check_error); classcase : case validfp is when isx | nan | quiet_nan => result := (others => 'X'); when pos_zero | neg_zero => result := (others => '0'); -- return 0 when neg_inf => result (left_index) := '1'; -- return smallest negative number when pos_inf => result := (others => '1'); -- return largest number result (left_index) := '0'; when others => expon_base := 2**(exponent_width-1) -1; -- exponent offset if arg(exponent_width) = '0' then sign := false; else sign := true; end if; -- Figure out the fraction if (validfp = pos_denormal or validfp = neg_denormal) and denormalize then exp := -expon_base +1; frac (frac'high) := '0'; -- Add the "1.0". else -- exponent /= '0', normal floating point expon := UNSIGNED(arg (exponent_width-1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (SIGNED(expon)) +1; frac (frac'high) := '1'; -- Add the "1.0". end if; shift := (frac'high - 3 + right_index) - exp; if fraction_width > frac'high then -- Can only use size-2 bits frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto -frac'high))); else -- can use all bits frac (frac'high-1 downto frac'high-fraction_width) := UNSIGNED (to_slv (arg(-1 downto -fraction_width))); end if; frac_shift := frac srl shift; if shift < 0 then -- Overflow frac := (others => '1'); else frac := frac_shift; end if; if not sign then rsigned := SIGNED("0" & frac); else rsigned := -(SIGNED("0" & frac)); end if; result_big := to_sfixed ( arg => STD_LOGIC_VECTOR(rsigned), left_index => left_index, right_index => (right_index-3)); result := resize (arg => result_big, left_index => left_index, right_index => right_index, round_style => round_style, overflow_style => overflow_style); end case classcase; return result; end function to_sfixed; -- size_res versions -- float to unsigned function to_unsigned ( arg : UNRESOLVED_float; -- floating point input size_res : UNRESOLVED_UNSIGNED; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_UNSIGNED is variable result : UNRESOLVED_UNSIGNED (size_res'range); begin if (SIZE_RES'length = 0) then return result; else result := to_unsigned ( arg => arg, size => size_res'length, round_style => round_style, check_error => check_error); return result; end if; end function to_unsigned; -- float to signed function to_signed ( arg : UNRESOLVED_float; -- floating point input size_res : UNRESOLVED_SIGNED; constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error) -- check for errors return UNRESOLVED_SIGNED is variable result : UNRESOLVED_SIGNED (size_res'range); begin if (SIZE_RES'length = 0) then return result; else result := to_signed ( arg => arg, size => size_res'length, round_style => round_style, check_error => check_error); return result; end if; end function to_signed; -- purpose: Converts a float to unsigned fixed point function to_ufixed ( arg : UNRESOLVED_float; -- fp input size_res : UNRESOLVED_ufixed; constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_ufixed is variable result : UNRESOLVED_ufixed (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_ufixed ( arg => arg, left_index => size_res'high, right_index => size_res'low, overflow_style => overflow_style, round_style => round_style, check_error => check_error, denormalize => denormalize); return result; end if; end function to_ufixed; -- float to signed fixed point function to_sfixed ( arg : UNRESOLVED_float; -- fp input size_res : UNRESOLVED_sfixed; constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate constant round_style : fixed_round_style_type := fixed_round_style; -- rounding constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_sfixed is variable result : UNRESOLVED_sfixed (size_res'left downto size_res'right); begin if (result'length < 1) then return result; else result := to_sfixed ( arg => arg, left_index => size_res'high, right_index => size_res'low, overflow_style => overflow_style, round_style => round_style, check_error => check_error, denormalize => denormalize); return result; end if; end function to_sfixed; -- to_real (float) -- typically not Synthesizable unless the input is a constant. function to_real ( arg : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return REAL is constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction constant exponent_width : INTEGER := arg'high; -- length of FP output exponent variable sign : REAL; -- Sign, + or - 1 variable exp : INTEGER; -- Exponent variable expon_base : INTEGER; -- exponent offset variable frac : REAL := 0.0; -- Fraction variable validfp : valid_fpstate; -- Valid FP state variable expon : UNSIGNED (exponent_width - 1 downto 0) := (others => '1'); -- Vectorized exponent begin validfp := classfp (arg, check_error); classcase : case validfp is when isx | pos_zero | neg_zero | nan | quiet_nan => return 0.0; when neg_inf => return REAL'low; -- Negative infinity. when pos_inf => return REAL'high; -- Positive infinity when others => expon_base := 2**(exponent_width-1) -1; if to_X01(arg(exponent_width)) = '0' then sign := 1.0; else sign := -1.0; end if; -- Figure out the fraction for i in 0 to fraction_width-1 loop if to_X01(arg (-1 - i)) = '1' then frac := frac + (2.0 **(-1 - i)); end if; end loop; -- i if validfp = pos_normal or validfp = neg_normal or not denormalize then -- exponent /= '0', normal floating point expon := UNSIGNED(arg (exponent_width-1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); exp := to_integer (SIGNED(expon)) +1; sign := sign * (2.0 ** exp) * (1.0 + frac); else -- exponent = '0', IEEE extended floating point exp := 1 - expon_base; sign := sign * (2.0 ** exp) * frac; end if; return sign; end case classcase; end function to_real; -- For Verilog compatability function realtobits (arg : REAL) return STD_ULOGIC_VECTOR is variable result : float64; -- 64 bit floating point begin result := to_float (arg => arg, exponent_width => float64'high, fraction_width => -float64'low); return to_sulv (result); end function realtobits; function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL is variable arg64 : float64; -- arg converted to float begin arg64 := to_float (arg => arg, exponent_width => float64'high, fraction_width => -float64'low); return to_real (arg64); end function bitstoreal; -- purpose: Removes meta-logical values from FP string function to_01 ( arg : UNRESOLVED_float; -- floating point input XMAP : STD_LOGIC := '0') return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin -- function to_01 if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_01: null detected, returning NULL" severity warning; return NAFP; end if; result := UNRESOLVED_float (STD_LOGIC_VECTOR(to_01(UNSIGNED(to_slv(arg)), XMAP))); return result; end function to_01; function Is_X (arg : UNRESOLVED_float) return BOOLEAN is begin return Is_X (to_slv(arg)); end function Is_X; function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_X01: null detected, returning NULL" severity warning; return NAFP; else result := UNRESOLVED_float (to_X01(to_slv(arg))); return result; end if; end function to_X01; function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_X01Z: null detected, returning NULL" severity warning; return NAFP; else result := UNRESOLVED_float (to_X01Z(to_slv(arg))); return result; end if; end function to_X01Z; function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (arg'range); begin if (arg'length < 1) then assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "TO_UX01: null detected, returning NULL" severity warning; return NAFP; else result := UNRESOLVED_float (to_UX01(to_slv(arg))); return result; end if; end function to_UX01; -- These allows the base math functions to use the default values -- of their parameters. Thus they do full IEEE floating point. function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return add (l, r); end function "+"; function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return subtract (l, r); end function "-"; function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return multiply (l, r); end function "*"; function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return divide (l, r); end function "/"; function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return remainder (l, r); end function "rem"; function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float is begin return modulo (l, r); end function "mod"; -- overloaded versions function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return add (l, r_float); end function "+"; function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return add (l_float, r); end function "+"; function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return add (l, r_float); end function "+"; function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return add (l_float, r); end function "+"; function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return subtract (l, r_float); end function "-"; function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return subtract (l_float, r); end function "-"; function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return subtract (l, r_float); end function "-"; function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return subtract (l_float, r); end function "-"; function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return multiply (l, r_float); end function "*"; function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return multiply (l_float, r); end function "*"; function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return multiply (l, r_float); end function "*"; function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return multiply (l_float, r); end function "*"; function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return divide (l, r_float); end function "/"; function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return divide (l_float, r); end function "/"; function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return divide (l, r_float); end function "/"; function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return divide (l_float, r); end function "/"; function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return remainder (l, r_float); end function "rem"; function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return remainder (l_float, r); end function "rem"; function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return remainder (l, r_float); end function "rem"; function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return remainder (l_float, r); end function "rem"; function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return modulo (l, r_float); end function "mod"; function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return modulo (l_float, r); end function "mod"; function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return modulo (l, r_float); end function "mod"; function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return modulo (l_float, r); end function "mod"; function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return eq (l, r_float); end function "="; function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ne (l, r_float); end function "/="; function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ge (l, r_float); end function ">="; function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return le (l, r_float); end function "<="; function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return gt (l, r_float); end function ">"; function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return lt (l, r_float); end function "<"; function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return eq (l_float, r); end function "="; function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ne (l_float, r); end function "/="; function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ge (l_float, r); end function ">="; function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return le (l_float, r); end function "<="; function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return gt (l_float, r); end function ">"; function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return lt (l_float, r); end function "<"; function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return eq (l, r_float); end function "="; function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ne (l, r_float); end function "/="; function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return ge (l, r_float); end function ">="; function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return le (l, r_float); end function "<="; function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return gt (l, r_float); end function ">"; function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return lt (l, r_float); end function "<"; function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return eq (l_float, r); end function "="; function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ne (l_float, r); end function "/="; function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return ge (l_float, r); end function ">="; function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return le (l_float, r); end function "<="; function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return gt (l_float, r); end function ">"; function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float(l, r'high, -r'low); return lt (l_float, r); end function "<"; -- ?= overloads function "?=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?= r_float; end function "?="; function "?/=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?/= r_float; end function "?/="; function "?>" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?> r_float; end function "?>"; function "?>=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?>= r_float; end function "?>="; function "?<" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?< r_float; end function "?<"; function "?<=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?<= r_float; end function "?<="; -- real and float function "?=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?= r; end function "?="; function "?/=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?/= r; end function "?/="; function "?>" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?> r; end function "?>"; function "?>=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?>= r; end function "?>="; function "?<" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?< r; end function "?<"; function "?<=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?<= r; end function "?<="; -- ?= overloads function "?=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?= r_float; end function "?="; function "?/=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?/= r_float; end function "?/="; function "?>" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?> r_float; end function "?>"; function "?>=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?>= r_float; end function "?>="; function "?<" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?< r_float; end function "?<"; function "?<=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return l ?<= r_float; end function "?<="; -- integer and float function "?=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?= r; end function "?="; function "?/=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?/= r; end function "?/="; function "?>" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?> r; end function "?>"; function "?>=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?>= r; end function "?>="; function "?<" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?< r; end function "?<"; function "?<=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return l_float ?<= r; end function "?<="; -- minimum and maximum overloads function minimum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return minimum (l, r_float); end function minimum; function maximum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return maximum (l, r_float); end function maximum; function minimum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return minimum (l_float, r); end function minimum; function maximum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return maximum (l_float, r); end function maximum; function minimum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return minimum (l, r_float); end function minimum; function maximum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is variable r_float : UNRESOLVED_float (l'range); begin r_float := to_float (r, l'high, -l'low); return maximum (l, r_float); end function maximum; function minimum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return minimum (l_float, r); end function minimum; function maximum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is variable l_float : UNRESOLVED_float (r'range); begin l_float := to_float (l, r'high, -r'low); return maximum (l_float, r); end function maximum; ---------------------------------------------------------------------------- -- logical functions ---------------------------------------------------------------------------- function "not" (L : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin RESULT := not to_sulv(L); return to_float (RESULT, L'high, -L'low); end function "not"; function "and" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) and to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """and"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "and"; function "or" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) or to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """or"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "or"; function "nand" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) nand to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """nand"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "nand"; function "nor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) nor to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """nor"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "nor"; function "xor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) xor to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """xor"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "xor"; function "xnor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto begin if (L'high = R'high and L'low = R'low) then RESULT := to_sulv(L) xnor to_sulv(R); else assert NO_WARNING report float_generic_pkg'instance_name & """xnor"": Range error L'RANGE /= R'RANGE" severity warning; RESULT := (others => 'X'); end if; return to_float (RESULT, L'high, -L'low); end function "xnor"; -- Vector and std_ulogic functions, same as functions in numeric_std function "and" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L and to_sulv(R)); return result; end function "and"; function "and" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) and R); return result; end function "and"; function "or" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L or to_sulv(R)); return result; end function "or"; function "or" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) or R); return result; end function "or"; function "nand" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L nand to_sulv(R)); return result; end function "nand"; function "nand" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) nand R); return result; end function "nand"; function "nor" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L nor to_sulv(R)); return result; end function "nor"; function "nor" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) nor R); return result; end function "nor"; function "xor" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L xor to_sulv(R)); return result; end function "xor"; function "xor" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) xor R); return result; end function "xor"; function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_float) return UNRESOLVED_float is variable result : UNRESOLVED_float (R'range); begin result := UNRESOLVED_float (L xnor to_sulv(R)); return result; end function "xnor"; function "xnor" (L : UNRESOLVED_float; R : STD_ULOGIC) return UNRESOLVED_float is variable result : UNRESOLVED_float (L'range); begin result := UNRESOLVED_float (to_sulv(L) xnor R); return result; end function "xnor"; -- Reduction operators, same as numeric_std functions function "and" (l : UNRESOLVED_float) return STD_ULOGIC is begin return and to_sulv(l); end function "and"; function "nand" (l : UNRESOLVED_float) return STD_ULOGIC is begin return nand to_sulv(l); end function "nand"; function "or" (l : UNRESOLVED_float) return STD_ULOGIC is begin return or to_sulv(l); end function "or"; function "nor" (l : UNRESOLVED_float) return STD_ULOGIC is begin return nor to_sulv(l); end function "nor"; function "xor" (l : UNRESOLVED_float) return STD_ULOGIC is begin return xor to_sulv(l); end function "xor"; function "xnor" (l : UNRESOLVED_float) return STD_ULOGIC is begin return xnor to_sulv(l); end function "xnor"; ----------------------------------------------------------------------------- -- Recommended Functions from the IEEE 754 Appendix ----------------------------------------------------------------------------- -- returns x with the sign of y. function Copysign ( x, y : UNRESOLVED_float) -- floating point input return UNRESOLVED_float is begin return y(y'high) & x (x'high-1 downto x'low); end function Copysign; -- Returns y * 2**n for integral values of N without computing 2**n function Scalb ( y : UNRESOLVED_float; -- floating point input N : INTEGER; -- exponent to add constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(y'low, y'low); -- length of FP output fraction constant exponent_width : NATURAL := y'high; -- length of FP output exponent variable arg, result : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp variable exp : SIGNED (exponent_width downto 0); variable ufract : UNSIGNED (fraction_width downto 0); constant expon_base : SIGNED (exponent_width-1 downto 0) := gen_expon_base(exponent_width); -- exponent offset variable fptype : valid_fpstate; begin -- This can be done by simply adding N to the exponent. arg := to_01 (y, 'X'); fptype := classfp(arg, check_error); classcase : case fptype is when isx => result := (others => 'X'); when nan | quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 result := qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); when others => break_number ( arg => arg, fptyp => fptype, denormalize => denormalize, fract => ufract, expon => expon); exp := resize (expon, exp'length) + N; result := normalize ( fract => ufract, expon => exp, sign => to_x01 (arg (arg'high)), fraction_width => fraction_width, exponent_width => exponent_width, round_style => round_style, denormalize => denormalize, nguard => 0); end case classcase; return result; end function Scalb; -- Returns y * 2**n for integral values of N without computing 2**n function Scalb ( y : UNRESOLVED_float; -- floating point input N : UNRESOLVED_SIGNED; -- exponent to add constant round_style : round_type := float_round_style; -- rounding option constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP return UNRESOLVED_float is variable n_int : INTEGER; begin n_int := to_integer(N); return Scalb (y => y, N => n_int, round_style => round_style, check_error => check_error, denormalize => denormalize); end function Scalb; -- returns the unbiased exponent of x function Logb ( x : UNRESOLVED_float) -- floating point input return INTEGER is constant fraction_width : NATURAL := -mine (x'low, x'low); -- length of FP output fraction constant exponent_width : NATURAL := x'high; -- length of FP output exponent variable result : INTEGER; -- result variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument variable expon : SIGNED (exponent_width - 1 downto 0); variable fract : UNSIGNED (fraction_width downto 0); constant expon_base : INTEGER := 2**(exponent_width-1) -1; -- exponent -- offset +1 variable fptype : valid_fpstate; begin -- Just return the exponent. arg := to_01 (x, 'X'); fptype := classfp(arg); classcase : case fptype is when isx | nan | quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1 result := 0; when pos_denormal | neg_denormal => fract (fraction_width) := '0'; fract (fraction_width-1 downto 0) := UNSIGNED (to_slv(arg(-1 downto -fraction_width))); result := find_leftmost (fract, '1') -- Find the first "1" - fraction_width; -- subtract the length we want result := -expon_base + 1 + result; when others => expon := SIGNED(arg (exponent_width - 1 downto 0)); expon(exponent_width-1) := not expon(exponent_width-1); expon := expon + 1; result := to_integer (expon); end case classcase; return result; end function Logb; -- returns the unbiased exponent of x function Logb ( x : UNRESOLVED_float) -- floating point input return UNRESOLVED_SIGNED is constant exponent_width : NATURAL := x'high; -- length of FP output exponent variable result : SIGNED (exponent_width - 1 downto 0); -- result begin -- Just return the exponent. result := to_signed (Logb (x), exponent_width); return result; end function Logb; -- returns the next representable neighbor of x in the direction toward y function Nextafter ( x, y : UNRESOLVED_float; -- floating point input constant check_error : BOOLEAN := float_check_error; -- check for errors constant denormalize : BOOLEAN := float_denormalize) return UNRESOLVED_float is constant fraction_width : NATURAL := -mine(x'low, x'low); -- length of FP output fraction constant exponent_width : NATURAL := x'high; -- length of FP output exponent function "=" ( l, r : UNRESOLVED_float) -- inputs return BOOLEAN is begin -- function "=" return eq (l => l, r => r, check_error => false); end function "="; function ">" ( l, r : UNRESOLVED_float) -- inputs return BOOLEAN is begin -- function ">" return gt (l => l, r => r, check_error => false); end function ">"; variable fract : UNSIGNED (fraction_width-1 downto 0); variable expon : UNSIGNED (exponent_width-1 downto 0); variable sign : STD_ULOGIC; variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable validfpx, validfpy : valid_fpstate; -- Valid FP state begin -- fp_Nextafter -- If Y > X, add one to the fraction, otherwise subtract. validfpx := classfp (x, check_error); validfpy := classfp (y, check_error); if validfpx = isx or validfpy = isx then result := (others => 'X'); return result; elsif (validfpx = nan or validfpy = nan) then return nanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif (validfpx = quiet_nan or validfpy = quiet_nan) then return qnanfp (fraction_width => fraction_width, exponent_width => exponent_width); elsif x = y then -- Return X return x; else fract := UNSIGNED (to_slv (x (-1 downto -fraction_width))); -- Fraction expon := UNSIGNED (x (exponent_width - 1 downto 0)); -- exponent sign := x(exponent_width); -- sign bit if (y > x) then -- Increase the number given if validfpx = neg_inf then -- return most negative number expon := (others => '1'); expon (0) := '0'; fract := (others => '1'); elsif validfpx = pos_zero or validfpx = neg_zero then -- return smallest denormal number sign := '0'; expon := (others => '0'); fract := (others => '0'); fract(0) := '1'; elsif validfpx = pos_normal then if and (fract) = '1' then -- fraction is all "1". if and (expon (exponent_width-1 downto 1)) = '1' and expon (0) = '0' then -- Exponent is one away from infinity. assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "FP_NEXTAFTER: NextAfter overflow" severity warning; return pos_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else expon := expon + 1; fract := (others => '0'); end if; else fract := fract + 1; end if; elsif validfpx = pos_denormal then if and (fract) = '1' then -- fraction is all "1". -- return smallest possible normal number expon := (others => '0'); expon(0) := '1'; fract := (others => '0'); else fract := fract + 1; end if; elsif validfpx = neg_normal then if or (fract) = '0' then -- fraction is all "0". if or (expon (exponent_width-1 downto 1)) = '0' and expon (0) = '1' then -- Smallest exponent -- return the largest negative denormal number expon := (others => '0'); fract := (others => '1'); else expon := expon - 1; fract := (others => '1'); end if; else fract := fract - 1; end if; elsif validfpx = neg_denormal then if or (fract(fract'high downto 1)) = '0' and fract (0) = '1' then -- Smallest possible fraction return zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else fract := fract - 1; end if; end if; else -- Decrease the number if validfpx = pos_inf then -- return most positive number expon := (others => '1'); expon (0) := '0'; fract := (others => '1'); elsif validfpx = pos_zero or classfp (x) = neg_zero then -- return smallest negative denormal number sign := '1'; expon := (others => '0'); fract := (others => '0'); fract(0) := '1'; elsif validfpx = neg_normal then if and (fract) = '1' then -- fraction is all "1". if and (expon (exponent_width-1 downto 1)) = '1' and expon (0) = '0' then -- Exponent is one away from infinity. assert NO_WARNING report FLOAT_GENERIC_PKG'instance_name & "FP_NEXTAFTER: NextAfter overflow" severity warning; return neg_inffp (fraction_width => fraction_width, exponent_width => exponent_width); else expon := expon + 1; -- Fraction overflow fract := (others => '0'); end if; else fract := fract + 1; end if; elsif validfpx = neg_denormal then if and (fract) = '1' then -- fraction is all "1". -- return smallest possible normal number expon := (others => '0'); expon(0) := '1'; fract := (others => '0'); else fract := fract + 1; end if; elsif validfpx = pos_normal then if or (fract) = '0' then -- fraction is all "0". if or (expon (exponent_width-1 downto 1)) = '0' and expon (0) = '1' then -- Smallest exponent -- return the largest positive denormal number expon := (others => '0'); fract := (others => '1'); else expon := expon - 1; fract := (others => '1'); end if; else fract := fract - 1; end if; elsif validfpx = pos_denormal then if or (fract(fract'high downto 1)) = '0' and fract (0) = '1' then -- Smallest possible fraction return zerofp (fraction_width => fraction_width, exponent_width => exponent_width); else fract := fract - 1; end if; end if; end if; result (-1 downto -fraction_width) := UNRESOLVED_float(fract); result (exponent_width -1 downto 0) := UNRESOLVED_float(expon); result (exponent_width) := sign; return result; end if; end function Nextafter; -- Returns True if X is unordered with Y. function Unordered ( x, y : UNRESOLVED_float) -- floating point input return BOOLEAN is variable lfptype, rfptype : valid_fpstate; begin lfptype := classfp (x); rfptype := classfp (y); if (lfptype = nan or lfptype = quiet_nan or rfptype = nan or rfptype = quiet_nan or lfptype = isx or rfptype = isx) then return true; else return false; end if; end function Unordered; function Finite ( x : UNRESOLVED_float) return BOOLEAN is variable fp_state : valid_fpstate; -- fp state begin fp_state := Classfp (x); if (fp_state = pos_inf) or (fp_state = neg_inf) then return true; else return false; end if; end function Finite; function Isnan ( x : UNRESOLVED_float) return BOOLEAN is variable fp_state : valid_fpstate; -- fp state begin fp_state := Classfp (x); if (fp_state = nan) or (fp_state = quiet_nan) then return true; else return false; end if; end function Isnan; -- Function to return constants. function zerofp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is constant result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin return result; end function zerofp; function nanfp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1" result (-1) := '1'; -- MSB of Fraction "1" -- Note: From W. Khan "IEEE Standard 754 for Binary Floating Point" -- The difference between a signaling NAN and a quiet NAN is that -- the MSB of the Fraction is a "1" in a Signaling NAN, and is a -- "0" in a quiet NAN. return result; end function nanfp; function qnanfp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1" result (-fraction_width) := '1'; -- LSB of Fraction "1" -- (Could have been any bit) return result; end function qnanfp; function pos_inffp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1" return result; end function pos_inffp; function neg_inffp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width downto 0) := (others => '1'); -- top bits all "1" return result; end function neg_inffp; function neg_zerofp ( constant exponent_width : NATURAL := float_exponent_width; -- exponent constant fraction_width : NATURAL := float_fraction_width) -- fraction return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width) := (others => '0'); -- zero begin result (exponent_width) := '1'; return result; end function neg_zerofp; -- size_res versions function zerofp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return zerofp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function zerofp; function nanfp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return nanfp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function nanfp; function qnanfp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return qnanfp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function qnanfp; function pos_inffp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return pos_inffp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function pos_inffp; function neg_inffp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return neg_inffp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function neg_inffp; function neg_zerofp ( size_res : UNRESOLVED_float) -- variable is only use for sizing return UNRESOLVED_float is begin return neg_zerofp ( exponent_width => size_res'high, fraction_width => -size_res'low); end function neg_zerofp; -- Textio functions -- purpose: writes float into a line (NOTE changed basetype) type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error); type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER; type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC; type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus; constant NBSP : CHARACTER := CHARACTER'val(160); -- space character constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-"; constant char_to_MVL9 : MVL9_indexed_by_char := ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U'); constant char_to_MVL9plus : MVL9plus_indexed_by_char := ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error); -- purpose: Skips white space procedure skip_whitespace ( L : inout LINE) is variable readOk : BOOLEAN; variable c : CHARACTER; begin while L /= null and L.all'length /= 0 loop c := l (l'left); if (c = ' ' or c = NBSP or c = HT) then read (l, c, readOk); else exit; end if; end loop; end procedure skip_whitespace; -- purpose: Checks the punctuation in a line procedure check_punctuation ( arg : in STRING; colon : out BOOLEAN; -- There was a colon in the line dot : out BOOLEAN; -- There was a dot in the line good : out BOOLEAN; -- True if enough characters found chars : in INTEGER) is -- Examples. Legal inputs are "0000000", "0000.000", "0:000:000" alias xarg : STRING (1 to arg'length) is arg; -- make it downto range variable icolon, idot : BOOLEAN; -- internal variable j : INTEGER := 0; -- charters read begin good := false; icolon := false; idot := false; for i in 1 to arg'length loop if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j = chars then exit; elsif xarg(i) = ':' then icolon := true; elsif xarg(i) = '.' then idot := true; elsif xarg (i) /= '_' then j := j + 1; end if; end loop; if j = chars then good := true; -- There are enough charactes to read end if; colon := icolon; if idot and icolon then dot := false; else dot := idot; end if; end procedure check_punctuation; -- purpose: Searches a line for a ":" and replaces it with a ".". procedure fix_colon ( arg : inout STRING; chars : in integer) is alias xarg : STRING (1 to arg'length) is arg; -- make it downto range variable j : INTEGER := 0; -- charters read begin for i in 1 to arg'length loop if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j > chars then exit; elsif xarg(i) = ':' then xarg (i) := '.'; elsif xarg (i) /= '_' then j := j + 1; end if; end loop; end procedure fix_colon; procedure WRITE ( L : inout LINE; -- input line VALUE : in UNRESOLVED_float; -- floating point input JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable s : STRING(1 to value'high - value'low +3); variable sindx : INTEGER; begin -- function write s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high))); s(2) := ':'; sindx := 3; for i in VALUE'high-1 downto 0 loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; s(sindx) := ':'; sindx := sindx + 1; for i in -1 downto VALUE'low loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; WRITE (L, s, JUSTIFIED, FIELD); end procedure WRITE; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float) is -- Possible data: 0:0000:0000000 -- 000000000000 variable c : CHARACTER; variable mv : UNRESOLVED_float (VALUE'range); variable readOk : BOOLEAN; variable lastu : BOOLEAN := false; -- last character was an "_" variable i : INTEGER; -- index variable begin -- READ VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); READ (l, c, readOk); if VALUE'length > 0 then i := value'high; readloop : loop if readOk = false then -- Bail out if there was a bad read report float_generic_pkg'instance_name & "READ(float): " & "Error end of file encountered." severity error; return; elsif c = ' ' or c = CR or c = HT then -- reading done. if (i /= value'low) then report float_generic_pkg'instance_name & "READ(float): " & "Warning: Value truncated." severity warning; return; end if; elsif c = '_' then if i = value'high then -- Begins with an "_" report float_generic_pkg'instance_name & "READ(float): " & "String begins with an ""_""" severity error; return; elsif lastu then -- "__" detected report float_generic_pkg'instance_name & "READ(float): " & "Two underscores detected in input string ""__""" severity error; return; else lastu := true; end if; elsif c = ':' or c = '.' then -- separator, ignore if not (i = -1 or i = value'high-1) then report float_generic_pkg'instance_name & "READ(float): " & "Warning: Separator point does not match number format: '" & c & "' encountered at location " & INTEGER'image(i) & "." severity warning; end if; lastu := false; elsif (char_to_MVL9plus(c) = error) then report float_generic_pkg'instance_name & "READ(float): " & "Error: Character '" & c & "' read, expected STD_ULOGIC literal." severity error; return; else mv (i) := char_to_MVL9(c); i := i - 1; if i < value'low then VALUE := mv; return; end if; lastu := false; end if; READ (l, c, readOk); end loop readloop; end if; end procedure READ; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is -- Possible data: 0:0000:0000000 -- 000000000000 variable c : CHARACTER; variable mv : UNRESOLVED_float (VALUE'range); variable lastu : BOOLEAN := false; -- last character was an "_" variable i : INTEGER; -- index variable variable readOk : BOOLEAN; begin -- READ VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); READ (l, c, readOk); if VALUE'length > 0 then i := value'high; good := false; readloop : loop if readOk = false then -- Bail out if there was a bad read return; elsif c = ' ' or c = CR or c = HT then -- reading done return; elsif c = '_' then if i = 0 then -- Begins with an "_" return; elsif lastu then -- "__" detected return; else lastu := true; end if; elsif c = ':' or c = '.' then -- separator, ignore -- good := (i = -1 or i = value'high-1); lastu := false; elsif (char_to_MVL9plus(c) = error) then return; else mv (i) := char_to_MVL9(c); i := i - 1; if i < value'low then good := true; VALUE := mv; return; end if; lastu := false; end if; READ (l, c, readOk); end loop readloop; else good := true; -- read into a null array end if; end procedure READ; procedure OWRITE ( L : inout LINE; -- access type (pointer) VALUE : in UNRESOLVED_float; -- value to write JUSTIFIED : in SIDE := right; -- which side to justify text FIELD : in WIDTH := 0) is -- width of field begin WRITE (L => L, VALUE => to_ostring(VALUE), JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure OWRITE; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/3); if not ok then report float_generic_pkg'instance_name & "OREAD: " & "short string encounted: " & L.all & " needs to have " & integer'image (ne/3) & " valid octal characters." severity error; return; elsif dot then OREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "OREAD: " & "error encounted reading STRING " & L.all severity error; return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then OREAD (L, nybble, ok); -- read the sign bit if not ok then report float_generic_pkg'instance_name & "OREAD: " & "End of string encountered" severity error; return; elsif nybble (2 downto 1) /= "00" then report float_generic_pkg'instance_name & "OREAD: " & "Illegal sign bit STRING encounted " severity error; return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/3); -- replaces the colon with a ".". OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "OREAD: " & "error encounted reading STRING " & L.all severity error; return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else OREAD (L, slv, ok); if not ok then report float_generic_pkg'instance_name & "OREAD: " & "Error encounted during read" severity error; return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then report float_generic_pkg'instance_name & "OREAD: " & "Vector truncated." severity error; return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; end if; end procedure OREAD; procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" GOOD := false; Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/3); if not ok then return; elsif dot then OREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then OREAD (L, nybble, ok); -- read the sign bit if not ok then return; elsif nybble (2 downto 1) /= "00" then return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/3); -- replaces the colon with a ".". OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else OREAD (L, slv, ok); if not ok then return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; GOOD := true; end if; end procedure OREAD; procedure HWRITE ( L : inout LINE; -- access type (pointer) VALUE : in UNRESOLVED_float; -- value to write JUSTIFIED : in SIDE := right; -- which side to justify text FIELD : in WIDTH := 0) is -- width of field begin WRITE (L => L, VALUE => to_hstring(VALUE), JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure HWRITE; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/4); if not ok then report float_generic_pkg'instance_name & "HREAD: " & "short string encounted: " & L.all & " needs to have " & integer'image (ne/4) & " valid hex characters." severity error; return; elsif dot then HREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "HREAD: " & "error encounted reading STRING " & L.all severity error; return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then HREAD (L, nybble, ok); -- read the sign bit if not ok then report float_generic_pkg'instance_name & "HREAD: " & "End of string encountered" severity error; return; elsif nybble (3 downto 1) /= "000" then report float_generic_pkg'instance_name & "HREAD: " & "Illegal sign bit STRING encounted " severity error; return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/4); -- replaces the colon with a ".". HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then report float_generic_pkg'instance_name & "HREAD: " & "error encounted reading STRING " & L.all severity error; return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else HREAD (L, slv, ok); if not ok then report float_generic_pkg'instance_name & "HREAD: " & "Error encounted during read" severity error; return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then report float_generic_pkg'instance_name & "HREAD: " & "Vector truncated." severity error; return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; end if; end procedure HREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv variable slvu : ufixed (VALUE'range); -- Unsigned fixed point variable c : CHARACTER; variable ok : BOOLEAN; variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits variable colon, dot : BOOLEAN; begin VALUE := (VALUE'range => 'U'); -- initialize to a "U" GOOD := false; Skip_whitespace (L); if VALUE'length > 0 then check_punctuation (arg => L.all, colon => colon, dot => dot, good => ok, chars => ne/4); if not ok then return; elsif dot then HREAD (L, slvu, ok); -- read it like a UFIXED number if not ok then return; else VALUE := UNRESOLVED_float (slvu); end if; elsif colon then HREAD (L, nybble, ok); -- read the sign bit if not ok then return; elsif nybble (3 downto 1) /= "000" then return; end if; read (l, c, ok); -- read the colon fix_colon (L.all, ne/4); -- replaces the colon with a ".". HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number if not ok then return; else slvu (slvu'high) := nybble (0); VALUE := UNRESOLVED_float (slvu); end if; else HREAD (L, slv, ok); if not ok then return; end if; if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then return; end if; VALUE := to_float (slv(VALUE'high-VALUE'low downto 0), VALUE'high, -VALUE'low); end if; GOOD := true; end if; end procedure HREAD; function to_string (value : UNRESOLVED_float) return STRING is variable s : STRING(1 to value'high - value'low +3); variable sindx : INTEGER; begin -- function write s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high))); s(2) := ':'; sindx := 3; for i in VALUE'high-1 downto 0 loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; s(sindx) := ':'; sindx := sindx + 1; for i in -1 downto VALUE'low loop s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i))); sindx := sindx + 1; end loop; return s; end function to_string; function to_hstring (value : UNRESOLVED_float) return STRING is variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0); begin floop : for i in slv'range loop slv(i) := to_X01Z (value(i + value'low)); end loop floop; return to_hstring (slv); end function to_hstring; function to_ostring (value : UNRESOLVED_float) return STRING is variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0); begin floop : for i in slv'range loop slv(i) := to_X01Z (value(i + value'low)); end loop floop; return to_ostring (slv); end function to_ostring; function from_string ( bstring : STRING; -- binary string constant exponent_width : NATURAL := float_exponent_width; constant fraction_width : NATURAL := float_fraction_width) return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable L : LINE; variable good : BOOLEAN; begin L := new STRING'(bstring); READ (L, result, good); deallocate (L); assert (good) report FLOAT_GENERIC_PKG'instance_name & "from_string: Bad string " & bstring severity error; return result; end function from_string; function from_ostring ( ostring : STRING; -- Octal string constant exponent_width : NATURAL := float_exponent_width; constant fraction_width : NATURAL := float_fraction_width) return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable L : LINE; variable good : BOOLEAN; begin L := new STRING'(ostring); OREAD (L, result, good); deallocate (L); assert (good) report FLOAT_GENERIC_PKG'instance_name & "from_ostring: Bad string " & ostring severity error; return result; end function from_ostring; function from_hstring ( hstring : STRING; -- hex string constant exponent_width : NATURAL := float_exponent_width; constant fraction_width : NATURAL := float_fraction_width) return UNRESOLVED_float is variable result : UNRESOLVED_float (exponent_width downto -fraction_width); variable L : LINE; variable good : BOOLEAN; begin L := new STRING'(hstring); HREAD (L, result, good); deallocate (L); assert (good) report FLOAT_GENERIC_PKG'instance_name & "from_hstring: Bad string " & hstring severity error; return result; end function from_hstring; function from_string ( bstring : STRING; -- binary string size_res : UNRESOLVED_float) -- used for sizing only return UNRESOLVED_float is begin return from_string (bstring => bstring, exponent_width => size_res'high, fraction_width => -size_res'low); end function from_string; function from_ostring ( ostring : STRING; -- Octal string size_res : UNRESOLVED_float) -- used for sizing only return UNRESOLVED_float is begin return from_ostring (ostring => ostring, exponent_width => size_res'high, fraction_width => -size_res'low); end function from_ostring; function from_hstring ( hstring : STRING; -- hex string size_res : UNRESOLVED_float) -- used for sizing only return UNRESOLVED_float is begin return from_hstring (hstring => hstring, exponent_width => size_res'high, fraction_width => -size_res'low); end function from_hstring; end package body float_generic_pkg;

------------------------------------------------------------------------------------- -- Copyright (c) 2006, University of Kansas - Hybridthreads Group -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- * Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- * Redistributions in binary form must reproduce the above copyright notice, -- this list of conditions and the following disclaimer in the documentation -- and/or other materials provided with the distribution. -- * Neither the name of the University of Kansas nor the name of the -- Hybridthreads Group nor the names of its contributors may be used to -- endorse or promote products derived from this software without specific -- prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use work.common.all; entity mutex_store is generic ( C_AWIDTH : integer := 32; C_DWIDTH : integer := 32; C_TWIDTH : integer := 8; C_MWIDTH : integer := 6; C_CWIDTH : integer := 8 ); port ( clk : in std_logic; rst : in std_logic; miaddr : in std_logic_vector(0 to C_MWIDTH-1); miena : in std_logic; miwea : in std_logic; miowner : in std_logic_vector(0 to C_TWIDTH-1); minext : in std_logic_vector(0 to C_TWIDTH-1); milast : in std_logic_vector(0 to C_TWIDTH-1); mikind : in std_logic_vector(0 to 1); micount : in std_logic_vector(0 to C_CWIDTH-1); sysrst : in std_logic; rstdone : out std_logic; moowner : out std_logic_vector(0 to C_TWIDTH-1); monext : out std_logic_vector(0 to C_TWIDTH-1); molast : out std_logic_vector(0 to C_TWIDTH-1); mokind : out std_logic_vector(0 to 1); mocount : out std_logic_vector(0 to C_CWIDTH-1) ); end mutex_store; architecture behavioral of mutex_store is -- Calculate the number of mutexes to use constant MUTEXES : integer := pow2( C_MWIDTH ); -- Constant for the last position to be reset constant RST_END : std_logic_vector(0 to C_MWIDTH-1) := (others => '1'); -- Calculate the beginning and ending bit positions for data constant OWN_SRT : integer := 0; constant OWN_END : integer := OWN_SRT + C_TWIDTH-1; constant NXT_SRT : integer := OWN_END+1; constant NXT_END : integer := NXT_SRT + C_TWIDTH-1; constant LST_SRT : integer := NXT_END+1; constant LST_END : integer := LST_SRT + C_TWIDTH-1; constant KND_SRT : integer := LST_END+1; constant KND_END : integer := KND_SRT + 1; constant CNT_SRT : integer := KND_END + 1; constant CNT_END : integer := CNT_SRT + C_CWIDTH-1; -- Declare a storage area for the mutex data type mstore is array(0 to MUTEXES-1) of std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1); -- Declare signals for the mutex storage area signal store : mstore; signal mena : std_logic; signal mwea : std_logic; signal maddr : std_logic_vector(0 to C_MWIDTH-1); signal minput : std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1); signal moutput : std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1); -- Type for the reset state machine type rststate is ( IDLE, RESET ); -- Declare signals for the reset signal rena : std_logic; signal rwea : std_logic; signal rst_cs : rststate; signal raddr : std_logic_vector(0 to C_MWIDTH-1); signal raddrn : std_logic_vector(0 to C_MWIDTH-1); signal rowner : std_logic_vector(0 to C_TWIDTH-1); signal rnext : std_logic_vector(0 to C_TWIDTH-1); signal rlast : std_logic_vector(0 to C_TWIDTH-1); signal rkind : std_logic_vector(0 to 1); signal rcount : std_logic_vector(0 to C_CWIDTH-1); begin moowner <= moutput(OWN_SRT to OWN_END); monext <= moutput(NXT_SRT to NXT_END); molast <= moutput(LST_SRT to LST_END); mokind <= moutput(KND_SRT to KND_END); mocount <= moutput(CNT_SRT to CNT_END); mutex_mux : process(clk,rst,sysrst,rena,rwea,raddr,rowner,rnext,rlast,rkind,rcount, miena,miwea,miaddr,miowner,milast,mikind,micount) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then mena <= rena; mwea <= rwea; maddr <= raddr; minput <= rowner & rnext & rlast & rkind & rcount; else mena <= miena; mwea <= miwea; maddr <= miaddr; minput <= miowner & minext & milast & mikind & micount; end if; end if; end process mutex_mux; mutex_reset_controller : process(clk,rst) is begin if( rising_edge(clk) ) then if( rst = '1' or sysrst = '1' ) then rst_cs <= RESET; raddr <= raddrn; else rst_cs <= IDLE; end if; end if; end process mutex_reset_controller; mutex_reset_logic : process(rst_cs,raddr) is begin rena <= '1'; rwea <= '1'; rstdone <= '1'; rowner <= (others => '0'); rnext <= (others => '0'); rlast <= (others => '0'); rkind <= (others => '0'); rcount <= (others => '0'); case rst_cs is when IDLE => raddrn <= (others => '0'); when RESET => if( raddr = RST_END ) then raddrn <= raddr; else rstdone <= '0'; raddrn <= raddr + 1; end if; end case; end process mutex_reset_logic; mutex_store_controller : process (clk) is begin if( rising_edge(clk) ) then if( mena = '1' ) then if( mwea = '1' ) then store( conv_integer(maddr) ) <= minput; end if; moutput <= store( conv_integer(maddr) ); end if; end if; end process mutex_store_controller; end behavioral;

entity e is end entity; architecture a of e is function f return boolean is begin return false; end function; begin assert f report "message" severity note; end architecture;

--------------------------------------------------- -- School: University of Massachusetts Dartmouth -- Department: Computer and Electrical Engineering -- Engineer: Daniel Noyes -- -- Create Date: SPRING 2014 -- Module Name: counter -- Project Name: CLOCK COUNTER -- Target Devices: Spartan-3E -- Tool versions: Xilinx ISE 14.7 -- Description: Clock toplevel -- Top level design of the clock counter --------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.all; entity clock_toplevel is Port ( CLK : in STD_LOGIC; -- 50 MHz Oscillator BTN : in STD_LOGIC; -- Reset Button SW : in STD_LOGIC_VECTOR (1 downto 0); -- Switch 0:add/sub, 1: clk speed LED : out STD_LOGIC_VECTOR (7 downto 0)); end clock_toplevel; architecture Structural of clock_toplevel is signal CLOCK_DIVIDER : STD_LOGIC := '0'; -- Divided Clock Output signal CLK2 : STD_LOGIC := '0'; -- 2 HZ line signal CLK4 : STD_LOGIC := '0'; -- 4 HZ line begin ----- Structural Components: ----- clk2Hz: entity work.clk2Hz port map( CLK_IN => CLK, RST => BTN, CLK_OUT => CLK2); clk4Hz: entity work.clk4Hz port map( CLK_IN => CLK, RST => BTN, CLK_OUT => CLK4); mux1: entity work.mux_2to1 port map( SEL => SW(1), IN_1 => CLK2, IN_2 => CLK4, MOUT => CLOCK_DIVIDER); counter: entity work.counter port map( CLK => CLOCK_DIVIDER, DIRECTION => SW(0), RST => BTN, COUNT_OUT => LED); ----- End Structural Components ----- end Structural;

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.aua_types.all; entity aua is port ( clk_in : in std_logic; reset_pin : in std_logic; switch_pins : in std_logic_vector(15 downto 0); led_pins : out std_logic_vector(15 downto 0); digit0_pins : out std_logic_vector(6 downto 0); digit1_pins : out std_logic_vector(6 downto 0); digit2_pins : out std_logic_vector(6 downto 0); digit3_pins : out std_logic_vector(6 downto 0); digit4_pins : out std_logic_vector(6 downto 0); digit5_pins : out std_logic_vector(6 downto 0); sram_addr : out std_logic_vector(RAM_ADDR_SIZE-1 downto 0); sram_dq : inout word_t; sram_we : out std_logic; -- sram_oe : out std_logic; sram_ub : out std_logic; sram_lb : out std_logic; -- sram_ce : out std_logic txd : out std_logic; rxd : in std_logic --~ ncts : in std_logic; --~ nrts : out std_logic ); end aua; architecture sat1 of aua is component aua_pll is port( areset : in std_logic; inclk0 : in std_logic; c0 : out std_logic ); end component; component ent_if is generic ( INIT_VECTOR : pc_t ); port ( clk : in std_logic; reset : in std_logic; -- pipeline register outputs opcode_out : out opcode_t; dest_out : out reg_t; pc_out : out pc_t; pcnxt_out : out pc_t; rega_out : out reg_t; regb_out : out reg_t; imm_out : out std_logic_vector(7 downto 0); -- asynchron register outputs async_rega : out reg_t; async_regb : out reg_t; -- branches (from ID) pc_in : in pc_t; branch : in std_logic; -- cache instr_addr : out word_t; instr_valid : in std_logic; instr_data : in word_t; -- interlock lock : in std_logic ); end component; component id is port ( clk : in std_logic; reset : in std_logic; -- pipeline register inputs opcode_in : in opcode_t; dest_in : in reg_t; pc_in : in pc_t; pcnxt_in : in pc_t; rega_in : in reg_t; regb_in : in reg_t; imm_in : in std_logic_vector(7 downto 0); -- asynchron register inputs async_rega : in reg_t; async_regb : in reg_t; -- results from wb to reg file regr : in reg_t; valr : in word_t; -- pipeline register outputs opcode_out : out opcode_t; dest_out : out reg_t; opa_out : out word_t; opb_out : out word_t; -- needed for EX forwarding rega_out : out reg_t; regb_out : out reg_t; opb_isfrom_regb : out boolean; -- branch decision pc_out : out pc_t; branch_out : out std_logic; -- interlock lock : in std_logic; id_locks : out std_logic ); end component; component ex is port ( clk : in std_logic; reset : in std_logic; -- pipeline register inputs opcode : in opcode_t; dest_in : in reg_t; opa : in word_t; opb : in word_t; -- pipeline register outputs dest_out : out reg_t; result_out : out word_t; -- interface to MMU mmu_address : out word_t; mmu_result : in word_t; mmu_st_data : out word_t; mmu_enable : out std_logic; mmu_opcode : out std_logic_vector(1 downto 0); mmu_done : in std_logic; -- pipeline interlock ex_locks : out std_ulogic; ex_locks_async : out std_ulogic ); end component; component instr_cache is port ( clk : in std_logic; reset : in std_logic; -- cache/if id_instr_addr : in word_t; id_instr_valid : out std_logic; id_instr : out word_t; -- cache/mmu mmu_instr_addr : out word_t; mmu_enable : out std_logic; mmu_instr_valid : in std_logic; mmu_instr : in word_t ); end component; component mmu is generic ( CLK_FREQ : natural; SRAM_RD_FREQ : natural; SRAM_WR_FREQ : natural ); port ( clk : in std_logic; reset : in std_logic; -- IF stage instr_addr : in word_t; instr_enable: in std_logic; instr_data : out word_t; instr_valid : out std_logic; -- interface to EX stage ex_address : in word_t; ex_rd_data : out word_t; ex_wr_data : in word_t; ex_enable : in std_logic; ex_opcode : in std_logic_vector(1 downto 0); ex_done : out std_logic; -- SimpCon interface to IO devices sc_io_in : in sc_in_t; sc_io_out : out sc_out_t; -- interface to SRAM sram_addr : out std_logic_vector(RAM_ADDR_SIZE-1 downto 0); sram_dq : inout word_t; sram_we : out std_logic; -- write enable, low active, 0=enable, 1=disable -- sram_oe : out std_logic; -- output enable, low active sram_ub : out std_logic; -- upper byte, low active sram_lb : out std_logic -- lower byte, low active -- sram_ce : out std_logic -- chip enable, low active ); end component; component sc_de2_switches is port ( clk : in std_logic; reset : in std_logic; -- SimpCon slave interface to IO ctrl address : in sc_addr_t; wr_data : in sc_data_t; rd : in std_logic; wr : in std_logic; rd_data : out sc_data_t; rdy_cnt : out sc_rdy_cnt_t; -- pins switch_pins : in std_logic_vector(15 downto 0); led_pins : out std_logic_vector(15 downto 0) ); end component; component sc_de2_digits is port ( clk : in std_logic; reset : in std_logic; -- SimpCon slave interface to IO ctrl address : in sc_addr_t; wr_data : in sc_data_t; rd : in std_logic; wr : in std_logic; rd_data : out sc_data_t; rdy_cnt : out sc_rdy_cnt_t; -- pins digit0_pins : out std_logic_vector(6 downto 0); digit1_pins : out std_logic_vector(6 downto 0); digit2_pins : out std_logic_vector(6 downto 0); digit3_pins : out std_logic_vector(6 downto 0); digit4_pins : out std_logic_vector(6 downto 0); digit5_pins : out std_logic_vector(6 downto 0) ); end component; component sc_uart is generic( clk_freq : integer; baud_rate : integer; txf_depth : integer; txf_thres : integer; rxf_depth : integer; rxf_thres : integer ); port ( clk : in std_logic; reset : in std_logic; -- SimpCon slave interface to IO ctrl address : in sc_addr_t; wr_data : in sc_data_t; rd : in std_logic; wr : in std_logic; rd_data : out sc_data_t; rdy_cnt : out sc_rdy_cnt_t; -- pins txd : out std_logic; rxd : in std_logic; ncts : in std_logic; nrts : out std_logic ); end component; component sc_test_slave is port ( clk : in std_logic; reset : in std_logic; -- SimpCon slave interface to IO ctrl address : in sc_addr_t; wr_data : in sc_data_t; rd : in std_logic; wr : in std_logic; rd_data : out sc_data_t; rdy_cnt : out sc_rdy_cnt_t ); end component; signal reset : std_logic; -- clk Signal aus PLL signal clk : std_logic; -- pipeline registers (written by top) -- IF/ID signal ifid_opcode_out : opcode_t; signal ifid_dest_out : reg_t; signal ifid_pc_out : pc_t; signal ifid_pcnxt_out : pc_t; signal ifid_rega_out : reg_t; signal ifid_regb_out : reg_t; signal ifid_async_rega_out : reg_t; signal ifid_async_regb_out : reg_t; signal ifid_imm_out : std_logic_vector(7 downto 0); -- ID/IF signal idif_pc_out : pc_t; signal idif_branch_out : std_logic; -- ID/EX signal idex_opcode_out : opcode_t; signal idex_dest_out : reg_t; signal idex_opa_out : word_t; signal idex_opb_out : word_t; -- EX/ID (for WB) signal exid_dest_out : reg_t; signal exid_result_out : word_t; -- pipeline registers (read by top) -- IF/ID signal ifid_opcode_in : opcode_t; signal ifid_dest_in : reg_t; signal ifid_pc_in : pc_t; signal ifid_pcnxt_in : pc_t; signal ifid_rega_in : reg_t; signal ifid_regb_in : reg_t; signal ifid_async_rega_in : reg_t; signal ifid_async_regb_in : reg_t; signal ifid_imm_in : std_logic_vector(7 downto 0); -- ID/IF signal idif_pc_in : pc_t; signal idif_branch_in : std_logic; -- ID/EX signal idex_opcode_in : opcode_t; signal idex_dest_in : reg_t; signal idex_opa_in : word_t; signal idex_opb_in : word_t; -- EX/ID (for WB) signal exid_dest_in : reg_t; signal exid_result_in : word_t; -- IF/CACHE/MMU signal ifcache_addr : word_t; signal ifcache_data : word_t; signal ifcache_valid : std_logic; signal cachemmu_addr : word_t; signal cachemmu_data : word_t; signal cachemmu_valid : std_logic; signal cachemmu_enable : std_logic; -- MMU interfaces -- EX/MMU signal exmmu_address : word_t; signal exmmu_result_mmu : word_t; signal exmmu_wr_data : word_t; signal exmmu_enable : std_logic; signal exmmu_mmu_opcode : std_logic_vector(1 downto 0); signal exmmu_valid : std_logic; -- MMU/IO signal mmuio_out : sc_out_t; signal mmuio_outa : sc_out_at; signal mmuio_in : sc_in_t; signal mmuio_ina : sc_in_at; --forwarding signal id_rega_in : reg_t; signal id_regb_in : reg_t; signal id_opb_isfrom_regb : boolean; signal exid_dest : reg_t; signal exid_result : word_t; --interlocks signal ex_locks : std_logic; signal ex_locks_async : std_logic; signal lock_if : std_logic; signal lock_id : std_logic; signal id_locks_async : std_logic; -- IO helpers signal sc_sel, sc_sel_reg : integer range 0 to 2**SC_ADDR_BITS; -- one more than needed (for NC) signal sc_addr : sc_addr_t; signal reset_sync : std_logic; -- reset pin is async! so we synchronize it: see sync_reset signal reset_pll : std_logic; begin cmp_pll: aua_pll port map(reset_pll, clk_in, clk); cmp_if: ent_if generic map(RST_VECTOR) port map(clk, reset, ifid_opcode_in, ifid_dest_in, ifid_pc_in, ifid_pcnxt_in, ifid_rega_in, ifid_regb_in, ifid_imm_in, ifid_async_rega_in, ifid_async_regb_in, idif_pc_out, idif_branch_out, ifcache_addr, ifcache_valid, ifcache_data, lock_if); cmp_id: id port map(clk, reset, ifid_opcode_out, ifid_dest_out, ifid_pc_out, ifid_pcnxt_out, ifid_rega_out, ifid_regb_out, ifid_imm_out, ifid_async_rega_out, ifid_async_regb_out, exid_dest_out, exid_result_out, idex_opcode_in, idex_dest_in, idex_opa_in, idex_opb_in, id_rega_in, id_regb_in, id_opb_isfrom_regb, idif_pc_in, idif_branch_in, lock_id, id_locks_async); cmp_ex: ex port map(clk, reset, idex_opcode_out, idex_dest_out, idex_opa_out, idex_opb_out, exid_dest_in, exid_result_in, exmmu_address, exmmu_result_mmu, exmmu_wr_data, exmmu_enable, exmmu_mmu_opcode, exmmu_valid, ex_locks, ex_locks_async); cmp_icache: instr_cache port map(clk, reset, ifcache_addr, ifcache_valid, ifcache_data, cachemmu_addr, cachemmu_enable, cachemmu_valid, cachemmu_data); cmp_mmu: mmu generic map(CLK_FREQ, SRAM_RD_FREQ, SRAM_WR_FREQ) port map(clk, reset, cachemmu_addr, cachemmu_enable, cachemmu_data, cachemmu_valid, exmmu_address, exmmu_result_mmu, exmmu_wr_data, exmmu_enable, exmmu_mmu_opcode, exmmu_valid, mmuio_in, mmuio_out, sram_addr, sram_dq, sram_we, sram_ub, sram_lb); -- taken from http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf sync_reset: process (clk, reset_pin) begin if (reset_pin = '0') then reset_sync <= '1'; reset <= '1'; elsif rising_edge(clk) then reset_sync <= '0'; reset <= reset_sync; end if; end process; reset_pll <= not reset_pin; -- needs to be async (think about it. :) ifid_opcode_out <= ifid_opcode_in; ifid_dest_out <= ifid_dest_in; ifid_pc_out <= ifid_pc_in; ifid_pcnxt_out <= ifid_pcnxt_in; ifid_rega_out <= ifid_rega_in; ifid_regb_out <= ifid_regb_in; ifid_async_rega_out <= ifid_async_rega_in; ifid_async_regb_out <= ifid_async_regb_in; ifid_imm_out <= ifid_imm_in; idif_pc_out <= idif_pc_in; idif_branch_out <= idif_branch_in; idex_opcode_out <= idex_opcode_in; idex_dest_out <= idex_dest_in; exid_dest_out <= exid_dest_in; exid_result_out <= exid_result_in; lock_if <= ex_locks_async or id_locks_async; lock_id <= ex_locks_async; ex_fw: process(id_rega_in, id_regb_in, exid_dest, exid_result, idex_opa_in, idex_opb_in, id_opb_isfrom_regb, ex_locks) begin if id_rega_in = exid_dest and ex_locks = '0' then idex_opa_out <= exid_result; else idex_opa_out <= idex_opa_in; end if; if id_regb_in = exid_dest and id_opb_isfrom_regb and ex_locks = '0' then idex_opb_out <= exid_result; else idex_opb_out <= idex_opb_in; end if; end process; sync: process (clk, reset) begin if reset = '1' then exid_dest <= (others => '0'); exid_result <= (others => '0'); elsif rising_edge(clk) then exid_dest <= exid_dest_in; exid_result <= exid_result_in; end if; end process; sc_sync: process(clk, reset) begin if (reset='1') then sc_sel_reg <= 0; -- sc_sel_reg <= SC_SLAVE_CNT; -- would be correct, but does not work on all devices; procudes warning elsif rising_edge(clk) then sc_sel_reg <= sc_sel; end if; end process; sc_in_mux: process (mmuio_ina, sc_sel_reg) begin if sc_sel_reg /= SC_SLAVE_CNT then mmuio_in.rd_data <= mmuio_ina(sc_sel_reg).rd_data; mmuio_in.rdy_cnt <= mmuio_ina(sc_sel_reg).rdy_cnt; else mmuio_in.rd_data <= (others => '0'); mmuio_in.rdy_cnt <= (others => '0'); end if; end process; sc_rdwr_mux: for i in 0 to SC_SLAVE_CNT-1 generate mmuio_outa(i).rd <= mmuio_out.rd when i=sc_sel else '0'; mmuio_outa(i).wr <= mmuio_out.wr when i=sc_sel else '0'; end generate; -- 0* --> ram -- 10* --> rom -- 11* --> simcon... -- 1111* --> Blöcke 0xF000/4 -- 11111111 * --> Blöcke 0xFF00/8 (I/O Devices) -- 11111111 0000* --> Switches 0xFF00/12 -- 11111111 0001* --> Digits 0xFF10/12 -- 11111111 0002* --> uart 0XFF20/12 -- -- 11111111 1111111* --> Test 0xFFFE/15 -- FEDCBA98 76543210 sc_addr <= mmuio_out.address; sc_sc_selector: process (mmuio_out, sc_addr) begin if((sc_addr and x"FFF0") = x"FF00") then sc_sel <= 0; elsif((sc_addr and x"FFF0") = x"FF10") then sc_sel <= 1; elsif((sc_addr and x"FFF0") = x"FF20") then sc_sel <= 2; elsif((sc_addr and x"FFFE") = x"FFFE") then sc_sel <= 3; else sc_sel <= SC_SLAVE_CNT; end if; end process; --IO devices below cmp_switches: sc_de2_switches port map(clk, reset, mmuio_out.address, mmuio_out.wr_data, mmuio_outa(0).rd, mmuio_outa(0).wr, mmuio_ina(0).rd_data, mmuio_ina(0).rdy_cnt, switch_pins, led_pins); cmp_digits: sc_de2_digits port map(clk, reset, mmuio_out.address, mmuio_out.wr_data, mmuio_outa(1).rd, mmuio_outa(1).wr, mmuio_ina(1).rd_data, mmuio_ina(1).rdy_cnt, digit0_pins, digit1_pins, digit2_pins, digit3_pins, digit4_pins, digit5_pins); cmp_uart: sc_uart generic map(CLK_FREQ, UART_RATE, 4, 2, 4, 2) port map(clk, reset, mmuio_out.address, mmuio_out.wr_data, mmuio_outa(2).rd, mmuio_outa(2).wr, mmuio_ina(2).rd_data, mmuio_ina(2).rdy_cnt, txd, rxd, '0', open); cmp_test: sc_test_slave port map(clk, reset, mmuio_out.address, mmuio_out.wr_data, mmuio_outa(3).rd, mmuio_outa(3).wr, mmuio_ina(3).rd_data, mmuio_ina(3).rdy_cnt); end sat1; use WORK.all; configuration aua_cache of aua is for sat1 for cmp_icache : instr_cache use entity work.instr_cache(cache_null); --~ use entity work.instr_cache(cache_direct); end for; for cmp_ex: ex use entity work.ex(sat1); for sat1 for cmp_alu: alu use entity work.alu(old); --~ use entity work.alu(opt); end for; end for; end for; -- does not work... why? --~ for cmp_mmu: mmu --~ use entity work.mmu(sat1) --~ generic map(1) -- irq_cnt --~ port map(clk, reset, cachemmu_addr, cachemmu_data, cachemmu_valid, exmmu_address, exmmu_result_mmu, exmmu_wr_data, exmmu_enable, exmmu_mmu_opcode, exmmu_valid, --~ mmuio_address, mmuio_wr_data, mmuio_rd, mmuio_wr, mmuio_rd_data, mmuio_rdy_cnt, --~ sram_addr, sram_dq, sram_we, sram_oe, sram_ub, sram_lb, sram_ce); --~ end for; end for; end aua_cache;

-- -- Front-end for SpaceWire Receiver -- -- This entity samples the input signals DataIn and StrobeIn to detect -- valid bit transitions. Received bits are handed to the application. -- -- Inputs are sampled on the rising edge of the system clock, therefore -- the maximum bitrate of the incoming signal must be significantly lower -- than system clock frequency. -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity spwrecvfront_generic is port ( -- System clock. clk: in std_logic; -- High to enable receiver; low to disable and reset receiver. rxen: in std_logic; -- High if there has been recent activity on the input lines. inact: out std_logic; -- High if inbits contains a valid received bit. -- If inbvalid='1', the application must sample inbits on -- the rising edge of clk. inbvalid: out std_logic; -- Received bit inbits: out std_logic_vector(0 downto 0); -- Data In signal from SpaceWire bus. spw_di: in std_logic; -- Strobe In signal from SpaceWire bus. spw_si: in std_logic ); end entity spwrecvfront_generic; architecture spwrecvfront_arch of spwrecvfront_generic is -- input flip-flops signal s_spwdi1: std_ulogic; signal s_spwsi1: std_ulogic; signal s_spwdi2: std_ulogic; signal s_spwsi2: std_ulogic; -- data/strobe decoding signal s_spwsi3: std_ulogic; -- output registers signal s_inbvalid: std_ulogic; signal s_inbit: std_ulogic; begin -- drive outputs inact <= s_inbvalid; inbvalid <= s_inbvalid; inbits(0) <= s_inbit; -- synchronous process process (clk) is begin if rising_edge(clk) then -- sample input signal s_spwdi1 <= spw_di; s_spwsi1 <= spw_si; -- more flip-flops for safe synchronization s_spwdi2 <= s_spwdi1; s_spwsi2 <= s_spwsi1; -- keep strobe signal for data/strobe decoding s_spwsi3 <= s_spwsi2; -- keep data bit for data/strobe decoding s_inbit <= s_spwdi2; if rxen = '1' then -- data/strobe decoding s_inbvalid <= s_spwdi2 xor s_spwsi2 xor s_inbit xor s_spwsi3; else -- reset receiver s_inbvalid <= '0'; end if; end if; end process; end architecture spwrecvfront_arch;

-- ATA interface constant CFG_ATA : integer := CONFIG_ATA_ENABLE; constant CFG_ATAIO : integer := 16#CONFIG_ATAIO#; constant CFG_ATAIRQ : integer := CONFIG_ATAIRQ; constant CFG_ATADMA : integer := CONFIG_ATA_MWDMA; constant CFG_ATAFIFO : integer := CONFIG_ATA_FIFO;

library verilog; use verilog.vl_types.all; entity InstruMemory is generic( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 32 ); port( data : in vl_logic_vector; addr : in vl_logic_vector; we : in vl_logic_vector(3 downto 0); clk : in vl_logic; q : out vl_logic_vector ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of DATA_WIDTH : constant is 1; attribute mti_svvh_generic_type of ADDR_WIDTH : constant is 1; end InstruMemory;

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block IEKs3v1U4ZrGtQ0GJBj1GObroWn7qUtVIk6ehVj6p8tNCmuXfFQoj3MBJ+irsY7fQnr2QERnclSa DTPzAxU7nw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bHXxs0PerrsoqTiziZzG96TBw9FgFyfq3QWTqZzWJZWI61WJwGHGqBZH5euavmse+ICawYH7T8Bu C1kvVj/yUX+nC+pJuS2BLbB2NVDcPRPAS13yOEyRxKnIqRGYF6XRt1dbAPJiKBUg80NJZUdoDQ+P 6xFUSmJ+jaJFMmSR6D0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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library ieee; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; use work.VHDL_lib.all; entity modn is generic( size:integer := 4 ); port ( clk : in std_logic; output : out std_logic_vector(log2(size)-1 downto 0) ); end modn; architecture arch of modn is signal count: std_logic_vector(log2(size)-1 downto 0); begin counter:process(clk) begin if(clk'event and clk = '1')then output <= count; if(count < size-1) then count <= count + 1; else count <= (others=>'0'); end if; end if; end process; end arch;

---------------------------------------------------------------------------------- -- Module Name: tb_aux_test - Behavioral -- -- Description: A testbench for the aux_test -- ---------------------------------------------------------------------------------- -- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort ------------------------------------------------------------------------------------ -- The MIT License (MIT) -- -- Copyright (c) 2015 Michael Alan Field <[email protected]> -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -- THE SOFTWARE. ------------------------------------------------------------------------------------ ----- Want to say thanks? ---------------------------------------------------------- ------------------------------------------------------------------------------------ -- -- This design has taken many hours - 3 months of work. I'm more than happy -- to share it if you can make use of it. It is released under the MIT license, -- so you are not under any onus to say thanks, but.... -- -- If you what to say thanks for this design either drop me an email, or how about -- trying PayPal to my email ([email protected])? -- -- Educational use - Enough for a beer -- Hobbyist use - Enough for a pizza -- Research use - Enough to take the family out to dinner -- Commercial use - A weeks pay for an engineer (I wish!) -------------------------------------------------------------------------------------- -- Ver | Date | Change --------+------------+--------------------------------------------------------------- -- 0.1 | 2015-09-17 | Initial Version ------------------------------------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity tb_aux_test is end entity; architecture arch of tb_aux_test is component aux_test is port ( clk : in std_logic; -- Needs to be a 100 MHz signal debug_pmod : out std_logic_vector(7 downto 0); dp_tx_aux_p : inout std_logic; dp_tx_aux_n : inout std_logic; dp_rx_aux_p : inout std_logic; dp_rx_aux_n : inout std_logic; dp_tx_hpd : in std_logic ); end component; signal clk : std_logic := '0'; signal debug_pmod : std_logic_vector := (others => '0'); signal dp_tx_aux_p : std_logic := '0'; signal dp_tx_aux_n : std_logic := '0'; signal dp_rx_aux_p : std_logic := '0'; signal dp_rx_aux_n : std_logic := '0'; signal dp_tx_hpd : std_logic := '0'; begin uut: aux_test PORT MAP ( clk => clk, debug_pmod => debug_pmod, dp_tx_aux_p => dp_tx_aux_p, dp_tx_aux_n => dp_tx_aux_n, dp_rx_aux_p => dp_rx_aux_p, dp_rx_aux_n => dp_rx_aux_n, dp_tx_hpd => dp_tx_hpd ); process begin wait for 5 ns; clk <= '1'; wait for 5 ns; clk <= '0'; end process; end architecture;

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-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1001.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c06s03b00x00p09n01i01001pkg is type TWO is range 1 to 2; end c06s03b00x00p09n01i01001pkg; use work.c06s03b00x00p09n01i01001pkg.all; ENTITY c06s03b00x00p09n01i01001ent IS END c06s03b00x00p09n01i01001ent; ARCHITECTURE c06s03b00x00p09n01i01001arch OF c06s03b00x00p09n01i01001ent IS BEGIN TESTING: PROCESS subtype ST6 is c06s03b00x00p09n01i01001pkg.UNKNOWN; -- SEMANTIC ERROR: ILLEGAL EXPANDED NAME BEGIN assert FALSE report "***FAILED TEST: c06s03b00x00p09n01i01001 - Expanded name is illegal." severity ERROR; wait; END PROCESS TESTING; END c06s03b00x00p09n01i01001arch;

architecture rtl of fifo is type t_record is record a : std_logic; b : std_logic; end record t_record; type t_record is record a : std_logic; b : std_logic; end record t_record; begin end architecture rtl;

-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1839.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c07s01b00x00p08n01i01839pkg is type small_int is range 0 to 7; type cmd_bus is array (small_int range <>) of small_int; constant bus_width : small_int := 7; end c07s01b00x00p08n01i01839pkg; use work.c07s01b00x00p08n01i01839pkg.all; entity c07s01b00x00p08n01i01839ent_a is port ( signal in_bus : in cmd_bus (0 to bus_width); signal out_bus : out cmd_bus (0 to bus_width)); end c07s01b00x00p08n01i01839ent_a; architecture c07s01b00x00p08n01i01839arch_a of c07s01b00x00p08n01i01839ent_a is begin end c07s01b00x00p08n01i01839arch_a; use work.c07s01b00x00p08n01i01839pkg.all; ENTITY c07s01b00x00p08n01i01839ent IS END c07s01b00x00p08n01i01839ent; ARCHITECTURE c07s01b00x00p08n01i01839arch OF c07s01b00x00p08n01i01839ent IS signal ibus, obus : cmd_bus(small_int); component test port ( signal in_bus : in cmd_bus (0 to small_int(bus_width)); signal out_bus : out cmd_bus (0 to small_int(bus_width))); end component; for err : test use entity work.c07s01b00x00p08n01i01839ent_a(c07s01b00x00p08n01i01839arch_a); BEGIN err : test port map ( ibus, c07s01b00x00p08n01i01839ent ); --entity name illegal here TESTING : PROCESS BEGIN wait for 5 ns; assert FALSE report "***FAILED TEST: c07s01b00x00p08n01i01839 - Entity names are not permitted as primaries in a component instantiation port map statement." severity ERROR; wait; END PROCESS TESTING; ENDc07s01b00x00p08n01i01839arch;

library ieee; use ieee.std_logic_1164.all; entity reg8 is port ( clk : in std_logic; clr : in std_logic; load : in std_logic; D : in std_logic_vector(7 downto 0); Q : out std_logic_vector(7 downto 0) ); end entity; architecture rtlreg8 of reg8 is begin process(clk,clr) begin if (clr = '1') then Q <= "00000000"; elsif rising_edge(clk) then if (load = '1') then Q <= D; end if; end if; end process; end rtlreg8;

entity data_8b10b_tb is end; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.tb_pack.all; use work.codec_8b10b_pack.all; architecture tb of data_8b10b_tb is begin process is variable b8_i : b8_t; variable b10_o : b10_t; variable rd_o : rd_t; begin for i in 0 to 255 loop b8_i := b8_t(to_unsigned(i, 8)); data_8b10b(b8_i, minus1, b10_o, rd_o); report "data_8b10b(0x" & to_hstring(b8_i) & ", minus1) => 0x" & to_hstring(b10_o) & ", " & rd_t'image(rd_o); end loop; wait; end process; end;

-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: fifo_dgen.vhd -- -- Description: -- Used for write interface stimulus generation -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_misc.all; LIBRARY work; USE work.fifo_pkg.ALL; ENTITY fifo_dgen IS GENERIC ( C_DIN_WIDTH : INTEGER := 32; C_DOUT_WIDTH : INTEGER := 32; C_CH_TYPE : INTEGER := 0; TB_SEED : INTEGER := 2 ); PORT ( RESET : IN STD_LOGIC; WR_CLK : IN STD_LOGIC; PRC_WR_EN : IN STD_LOGIC; FULL : IN STD_LOGIC; WR_EN : OUT STD_LOGIC; WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) ); END ENTITY; ARCHITECTURE fg_dg_arch OF fifo_dgen IS CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); SIGNAL pr_w_en : STD_LOGIC := '0'; SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); BEGIN WR_EN <= PRC_WR_EN ; WR_DATA <= wr_data_i AFTER 100 ns; ---------------------------------------------- -- Generation of DATA ---------------------------------------------- gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE rd_gen_inst1:fifo_rng GENERIC MAP( WIDTH => 8, SEED => TB_SEED+N ) PORT MAP( CLK => WR_CLK, RESET => RESET, RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), ENABLE => pr_w_en ); END GENERATE; pr_w_en <= PRC_WR_EN AND NOT FULL; wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0); END ARCHITECTURE;

-- ------------------------------------------------------------- -- -- Entity Declaration for pad_pads_e -- -- Generated -- by: wig -- on: Wed Dec 14 12:20:57 2005 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../padio.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: pad_pads_e-e.vhd,v 1.4 2005/12/14 12:38:04 wig Exp $ -- $Date: 2005/12/14 12:38:04 $ -- $Log: pad_pads_e-e.vhd,v $ -- Revision 1.4 2005/12/14 12:38:04 wig -- Updated some testcases (verilog, padio) -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.72 2005/11/30 14:01:21 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.43 , [email protected] -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity pad_pads_e -- entity pad_pads_e is -- Generics: -- No Generated Generics for Entity pad_pads_e -- Generated Port Declaration: port( -- Generated Port for Entity pad_pads_e p_mix_pad_di_12_go : out std_ulogic; p_mix_pad_di_13_go : out std_ulogic; p_mix_pad_di_14_go : out std_ulogic; p_mix_pad_di_15_go : out std_ulogic; p_mix_pad_di_16_go : out std_ulogic; p_mix_pad_di_17_go : out std_ulogic; p_mix_pad_di_18_go : out std_ulogic; p_mix_pad_di_1_go : out std_ulogic; p_mix_pad_di_31_go : out std_ulogic; p_mix_pad_di_32_go : out std_ulogic; p_mix_pad_di_33_go : out std_ulogic; p_mix_pad_di_34_go : out std_ulogic; p_mix_pad_di_39_go : out std_ulogic; p_mix_pad_di_40_go : out std_ulogic; p_mix_pad_do_12_gi : in std_ulogic; p_mix_pad_do_13_gi : in std_ulogic; p_mix_pad_do_14_gi : in std_ulogic; p_mix_pad_do_15_gi : in std_ulogic; p_mix_pad_do_16_gi : in std_ulogic; p_mix_pad_do_17_gi : in std_ulogic; p_mix_pad_do_18_gi : in std_ulogic; p_mix_pad_do_2_gi : in std_ulogic; p_mix_pad_do_31_gi : in std_ulogic; p_mix_pad_do_32_gi : in std_ulogic; p_mix_pad_do_35_gi : in std_ulogic; p_mix_pad_do_36_gi : in std_ulogic; p_mix_pad_do_39_gi : in std_ulogic; p_mix_pad_do_40_gi : in std_ulogic; p_mix_pad_en_12_gi : in std_ulogic; p_mix_pad_en_13_gi : in std_ulogic; p_mix_pad_en_14_gi : in std_ulogic; p_mix_pad_en_15_gi : in std_ulogic; p_mix_pad_en_16_gi : in std_ulogic; p_mix_pad_en_17_gi : in std_ulogic; p_mix_pad_en_18_gi : in std_ulogic; p_mix_pad_en_2_gi : in std_ulogic; p_mix_pad_en_31_gi : in std_ulogic; p_mix_pad_en_32_gi : in std_ulogic; p_mix_pad_en_35_gi : in std_ulogic; p_mix_pad_en_36_gi : in std_ulogic; p_mix_pad_en_39_gi : in std_ulogic; p_mix_pad_en_40_gi : in std_ulogic; p_mix_pad_pu_31_gi : in std_ulogic; p_mix_pad_pu_32_gi : in std_ulogic -- End of Generated Port for Entity pad_pads_e ); end pad_pads_e; -- -- End of Generated Entity pad_pads_e -- -- --!End of Entity/ies -- --------------------------------------------------------------

-- ######################################################################## -- $Software: busiac -- $section : hardware component -- $Id: rs232out.vhd 322 2015-05-29 06:43:59Z ia $ -- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/rs232out.vhd $ -- $Author : Ivan Auge (Email: [email protected]) -- ######################################################################## -- -- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge. -- -- This program is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at your -- option) any later version. -- -- BUSIAC software is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY ; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General -- Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with the GNU C Library; see the file COPYING. If not, write to the Free -- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -- -- ######################################################################*/ ------------------------------------------------------------------------------- -- ATTENTION: -- Ceci un template, les trous marqués "..." doivent être comblés pour -- pouvoir être compilé, puis fonctionné. ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Ce module sérialise l'entrée DATA de 8 bits sur la sortie TX. -- -- le format écrit est: -- - 1 start bit -- - 8 bit de données -- - 1 stop bits -- -- La sortie BUSY indique que le module est en train de sérialiser. -- -- Pour sérialiser une nouvelle valeur, il faut: -- * attendre que BUSY soit nul. -- * la positionner sur DATA et mettre NDATA à 1 au moins 1 cycle. -- -- Pour fixer le BAUD du composant utilisez les paramètres génériques -- BAUD et FREQ ci dessous. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity rs232out is generic( FREQ : integer := 50000000; -- Frequence de clk BAUD : integer := 9600); -- Baud de Rx port( clk : in STD_LOGIC; reset : in STD_LOGIC; Tx : out STD_LOGIC; Data : in STD_LOGIC_VECTOR(7 downto 0); Ndata : in STD_LOGIC; Busy : out STD_LOGIC); end rs232out; architecture montage of rs232out is ------------------------------------------------------------------------------- -- Partie Opérative ------------------------------------------------------------------------------- type T_CMD_i is (NOOP, COUNT, INIT); signal CMD_i : T_CMD_i ; signal R_i : integer RANGE 0 TO 15; signal VT_endLoop: STD_LOGIC; type T_CMD_baud is (NOOP, COUNT, INIT); signal CMD_baud : T_CMD_baud ; signal R_baud: integer RANGE 0 TO (FREQ)/BAUD; signal VT_endbaud: STD_LOGIC; type T_CMD_data is (NOOP, SHIFT, INIT); signal CMD_data : T_CMD_data ; signal R_data : STD_LOGIC_VECTOR(8 downto 0); -- 0 : 1 start bit -- 8:1 : 8 data bits ------------------------------------------------------------------------------- -- Partie Contrôle ------------------------------------------------------------------------------- --Description des états type STATE_TYPE is (ST_BEGIN, ST_FOR, ST_ATT, ST_ADV); signal state : STATE_TYPE; begin ------------------------------------------------------------------------------- -- Partie Opérative ------------------------------------------------------------------------------- process (clk) begin if clk'event and clk = '1' then -- R_i if ( CMD_i = INIT ) then R_i <= 11 ; elsif ( CMD_i = COUNT ) then R_i <= R_i - 1; else R_i <= R_i; end if; -- R_baud if ( CMD_baud = INIT ) then R_baud <= FREQ/BAUD ; elsif ( CMD_baud = COUNT ) then R_baud <= R_baud - 1; else R_baud <= R_baud; end if; -- R_data if ( CMD_data = INIT ) then -- V = E + '0' R_data(8 downto 1) <= Data; R_data(0) <= '0'; elsif ( CMD_data = SHIFT ) then -- v = '1' + (v >> 1) R_data(7 downto 0) <= R_data(8 downto 1); R_data(8) <= '1'; else R_data <= R_data; end if ; end if; end process; VT_endbaud <= '1' WHEN R_Baud = 0 ELSE '0' ; VT_endLoop <= '1' WHEN R_i = 0 ELSE '0' ; ------------------------------------------------------------------------------- -- Partie Contrôle ------------------------------------------------------------------------------- -- Inputs: Ndata VT_endLoop VT_endBaud -- Outputs: Tx Busy CMD_i CMD_baud CMD_data ------------------------------------------------------------------------------- -- fonction de transitition process (reset,clk) begin if reset = '1' then state <= ST_BEGIN; elsif clk'event and clk = '1' then case state is when ST_BEGIN => -- si go, alors on commence à serialiser if Ndata = '1' then state <= ST_FOR; end if; when ST_FOR => if VT_endLoop = '1' then state <= ST_BEGIN; else state <= ST_ATT; end if; when ST_ATT => if VT_endbaud = '1' then state <= ST_ADV; end if; when ST_ADV => state <= ST_FOR; end case; end if; end process; -- fonction de sortie with state select tx <= '1' when ST_BEGIN, R_Data(0) when others ; with state select busy <= '0' when ST_BEGIN, '1' when others ; with state select CMD_i <= INIT when ST_BEGIN, COUNT when ST_ADV, NOOP when others ; with state select CMD_baud <= COUNT when ST_ATT, INIT when others ; with state select CMD_data <= INIT when ST_BEGIN, SHIFT when ST_ADV, NOOP when others ; end montage;

-------------------------------------------------------------------------------- --! @file width_pulse_sync.vhd --! @brief Produce a pulse of specified width in a different clock domain. --! @author Yuan Mei --! --! Produce a pulse of specified width in a different clock domain --! following a 1-CLKO wide reset pulse. --! Ideally suited to change iodelay taps and iserdes bitslip --! MODE := 0 output one pulse of duration PW --! := 1 a train of 1-clk wide pulses (of number PW) --! PW = 0 will still generate RSTO but no PO. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values USE ieee.numeric_std.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. LIBRARY UNISIM; USE UNISIM.VComponents.ALL; ENTITY width_pulse_sync IS GENERIC ( DATA_WIDTH : positive := 8; MODE : natural := 0 -- 0: output one pulse of duration PW -- 1: a train of 1-clk wide pulses (of number PW) ); PORT ( RESET : IN std_logic; CLK : IN std_logic; PW : IN std_logic_vector(DATA_WIDTH-1 DOWNTO 0); START : IN std_logic; -- should be synchronous to CLK, of any width BUSY : OUT std_logic; -- CLKO : IN std_logic; RSTO : OUT std_logic; PO : OUT std_logic ); END width_pulse_sync; ARCHITECTURE Behavioral OF width_pulse_sync IS SIGNAL prev : std_logic; SIGNAL prevb : std_logic; SIGNAL prevb1 : std_logic; SIGNAL prevo : std_logic; SIGNAL prevo1 : std_logic; SIGNAL busy_buf : std_logic; SIGNAL busy_bufo : std_logic; SIGNAL pw_buf : std_logic_vector(DATA_WIDTH-1 DOWNTO 0); SIGNAL po_buf : std_logic; BEGIN PROCESS (CLK, RESET) IS BEGIN IF RESET = '1' THEN prev <= '0'; busy_buf <= '0'; pw_buf <= (OTHERS => '0'); prevb <= '0'; prevb1 <= '0'; ELSIF rising_edge(CLK) THEN prev <= START; -- Capture the rising edge of START, which is synchronous to CLK, of any width IF (prev = '0' AND START = '1' AND prevb1 = '0') THEN busy_buf <= '1'; pw_buf <= PW; END IF; prevb <= busy_bufo; prevb1 <= prevb; -- Capture the falling edge of busy_bufo IF (prevb = '0' AND prevb1 = '1') THEN busy_buf <= '0'; END IF; END IF; END PROCESS; BUSY <= busy_buf; -- output clock domain PROCESS (CLKO) IS VARIABLE counter : unsigned(DATA_WIDTH DOWNTO 0); BEGIN IF rising_edge(CLKO) THEN prevo <= busy_buf; prevo1 <= prevo; busy_bufo <= '0'; po_buf <= '0'; RSTO <= '0'; -- Capture the rising edge of busy_buf IF (prevo1 = '0' AND prevo = '1') THEN busy_bufo <= '1'; counter := (OTHERS => '0'); RSTO <= '1'; ELSIF counter = 0 THEN busy_bufo <= '1'; counter := counter + 1; ELSIF counter <= unsigned(pw_buf) THEN busy_bufo <= '1'; IF MODE = 0 THEN counter := counter + 1; po_buf <= '1'; ELSIF MODE = 1 THEN IF po_buf = '0' THEN counter := counter + 1; END IF; po_buf <= NOT po_buf; END IF; END IF; END IF; END PROCESS; PO <= po_buf; END Behavioral;

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: ac.uk:user:lms_pcore:1.0 -- IP Revision: 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY lms_pcore_v1_00_a; USE lms_pcore_v1_00_a.lms_pcore; ENTITY ip_design_lms_pcore_0_0 IS PORT ( IPCORE_CLK : IN STD_LOGIC; IPCORE_RESETN : IN STD_LOGIC; AXI4_Lite_ACLK : IN STD_LOGIC; AXI4_Lite_ARESETN : IN STD_LOGIC; AXI4_Lite_AWADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0); AXI4_Lite_AWVALID : IN STD_LOGIC; AXI4_Lite_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); AXI4_Lite_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); AXI4_Lite_WVALID : IN STD_LOGIC; AXI4_Lite_BREADY : IN STD_LOGIC; AXI4_Lite_ARADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0); AXI4_Lite_ARVALID : IN STD_LOGIC; AXI4_Lite_RREADY : IN STD_LOGIC; AXI4_Lite_AWREADY : OUT STD_LOGIC; AXI4_Lite_WREADY : OUT STD_LOGIC; AXI4_Lite_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); AXI4_Lite_BVALID : OUT STD_LOGIC; AXI4_Lite_ARREADY : OUT STD_LOGIC; AXI4_Lite_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); AXI4_Lite_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); AXI4_Lite_RVALID : OUT STD_LOGIC ); END ip_design_lms_pcore_0_0; ARCHITECTURE ip_design_lms_pcore_0_0_arch OF ip_design_lms_pcore_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF ip_design_lms_pcore_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT lms_pcore IS PORT ( IPCORE_CLK : IN STD_LOGIC; IPCORE_RESETN : IN STD_LOGIC; AXI4_Lite_ACLK : IN STD_LOGIC; AXI4_Lite_ARESETN : IN STD_LOGIC; AXI4_Lite_AWADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0); AXI4_Lite_AWVALID : IN STD_LOGIC; AXI4_Lite_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); AXI4_Lite_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); AXI4_Lite_WVALID : IN STD_LOGIC; AXI4_Lite_BREADY : IN STD_LOGIC; AXI4_Lite_ARADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0); AXI4_Lite_ARVALID : IN STD_LOGIC; AXI4_Lite_RREADY : IN STD_LOGIC; AXI4_Lite_AWREADY : OUT STD_LOGIC; AXI4_Lite_WREADY : OUT STD_LOGIC; AXI4_Lite_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); AXI4_Lite_BVALID : OUT STD_LOGIC; AXI4_Lite_ARREADY : OUT STD_LOGIC; AXI4_Lite_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); AXI4_Lite_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); AXI4_Lite_RVALID : OUT STD_LOGIC ); END COMPONENT lms_pcore; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF ip_design_lms_pcore_0_0_arch: ARCHITECTURE IS "lms_pcore,Vivado 2017.3"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF ip_design_lms_pcore_0_0_arch : ARCHITECTURE IS "ip_design_lms_pcore_0_0,lms_pcore,{}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_PARAMETER : STRING; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite RVALID"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite RRESP"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite RDATA"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite BVALID"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite BRESP"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite WREADY"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite RREADY"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite BREADY"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite WVALID"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite WDATA"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite AWVALID"; ATTRIBUTE X_INTERFACE_PARAMETER OF AXI4_Lite_AWADDR: SIGNAL IS "XIL_INTERFACENAME AXI4_Lite, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI4_Lite AWADDR"; ATTRIBUTE X_INTERFACE_PARAMETER OF AXI4_Lite_ARESETN: SIGNAL IS "XIL_INTERFACENAME AXI4_Lite_ARESETN, POLARITY ACTIVE_LOW"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI4_Lite_ARESETN RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF AXI4_Lite_ACLK: SIGNAL IS "XIL_INTERFACENAME AXI4_Lite_ACLK, ASSOCIATED_RESET AXI4_Lite_ARESETN, ASSOCIATED_BUSIF AXI4_Lite, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0"; ATTRIBUTE X_INTERFACE_INFO OF AXI4_Lite_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXI4_Lite_ACLK CLK"; ATTRIBUTE X_INTERFACE_PARAMETER OF IPCORE_RESETN: SIGNAL IS "XIL_INTERFACENAME IPCORE_RESETN, POLARITY ACTIVE_LOW"; ATTRIBUTE X_INTERFACE_INFO OF IPCORE_RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 IPCORE_RESETN RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF IPCORE_CLK: SIGNAL IS "XIL_INTERFACENAME IPCORE_CLK, ASSOCIATED_RESET IPCORE_RESETN, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0"; ATTRIBUTE X_INTERFACE_INFO OF IPCORE_CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 IPCORE_CLK CLK"; BEGIN U0 : lms_pcore PORT MAP ( IPCORE_CLK => IPCORE_CLK, IPCORE_RESETN => IPCORE_RESETN, AXI4_Lite_ACLK => AXI4_Lite_ACLK, AXI4_Lite_ARESETN => AXI4_Lite_ARESETN, AXI4_Lite_AWADDR => AXI4_Lite_AWADDR, AXI4_Lite_AWVALID => AXI4_Lite_AWVALID, AXI4_Lite_WDATA => AXI4_Lite_WDATA, AXI4_Lite_WSTRB => AXI4_Lite_WSTRB, AXI4_Lite_WVALID => AXI4_Lite_WVALID, AXI4_Lite_BREADY => AXI4_Lite_BREADY, AXI4_Lite_ARADDR => AXI4_Lite_ARADDR, AXI4_Lite_ARVALID => AXI4_Lite_ARVALID, AXI4_Lite_RREADY => AXI4_Lite_RREADY, AXI4_Lite_AWREADY => AXI4_Lite_AWREADY, AXI4_Lite_WREADY => AXI4_Lite_WREADY, AXI4_Lite_BRESP => AXI4_Lite_BRESP, AXI4_Lite_BVALID => AXI4_Lite_BVALID, AXI4_Lite_ARREADY => AXI4_Lite_ARREADY, AXI4_Lite_RDATA => AXI4_Lite_RDATA, AXI4_Lite_RRESP => AXI4_Lite_RRESP, AXI4_Lite_RVALID => AXI4_Lite_RVALID ); END ip_design_lms_pcore_0_0_arch;

---------------------------------------------------------------------- -- Project : Invent a Chip -- Authors : Jan Dürre -- Year : 2013 -- Description : This example waits for an uart-command, which is -- then saved and send back to the sender. ---------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.iac_pkg.all; entity invent_a_chip is port ( -- Global Signals clock : in std_ulogic; reset : in std_ulogic; -- Interface Signals -- 7-Seg sevenseg_cs : out std_ulogic; sevenseg_wr : out std_ulogic; sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0); sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0); sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0); -- ADC/DAC adc_dac_cs : out std_ulogic; adc_dac_wr : out std_ulogic; adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0); adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0); adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0); -- AUDIO audio_cs : out std_ulogic; audio_wr : out std_ulogic; audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0); audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0); audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0); audio_irq_left : in std_ulogic; audio_irq_right : in std_ulogic; audio_ack_left : out std_ulogic; audio_ack_right : out std_ulogic; -- Infra-red Receiver ir_cs : out std_ulogic; ir_wr : out std_ulogic; ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0); ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0); ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0); ir_irq_rx : in std_ulogic; ir_ack_rx : out std_ulogic; -- LCD lcd_cs : out std_ulogic; lcd_wr : out std_ulogic; lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0); lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0); lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0); lcd_irq_rdy : in std_ulogic; lcd_ack_rdy : out std_ulogic; -- SRAM sram_cs : out std_ulogic; sram_wr : out std_ulogic; sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0); sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0); sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0); -- UART uart_cs : out std_ulogic; uart_wr : out std_ulogic; uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0); uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0); uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0); uart_irq_rx : in std_ulogic; uart_irq_tx : in std_ulogic; uart_ack_rx : out std_ulogic; uart_ack_tx : out std_ulogic; -- GPIO gp_ctrl : out std_ulogic_vector(15 downto 0); gp_in : in std_ulogic_vector(15 downto 0); gp_out : out std_ulogic_vector(15 downto 0); -- LED/Switches/Keys led_green : out std_ulogic_vector(8 downto 0); led_red : out std_ulogic_vector(17 downto 0); switch : in std_ulogic_vector(17 downto 0); key : in std_ulogic_vector(2 downto 0) ); end invent_a_chip; architecture rtl of invent_a_chip is -- state register type state_t is (RECEIVED_LOOP, SEND_LOOP); signal state, state_nxt : state_t; -- register for received data signal received_data, received_data_nxt : std_ulogic_vector(7 downto 0); begin -- sequential process process (clock, reset) begin -- async reset if reset = '1' then state <= RECEIVED_LOOP; received_data <= (others => '0'); elsif rising_edge(clock) then state <= state_nxt; received_data <= received_data_nxt; end if; end process; -- logic process (state, received_data, uart_irq_rx, uart_irq_tx, uart_din) begin -- standard assignments -- hold values of registers state_nxt <= state; received_data_nxt <= received_data; -- set bus signals to standard values (not in use) uart_cs <= '0'; uart_wr <= '0'; uart_addr <= (others => '0'); uart_dout <= (others => '0'); uart_ack_rx <= '0'; uart_ack_tx <= '0'; -- turn of leds led_green <= (others => '0'); led_red <= (others => '0'); -- state machine case state is -- wait for and save data when RECEIVED_LOOP => led_green(0) <= '1'; -- data is ready in receive-register if uart_irq_rx = '1' then -- select uart-interface uart_cs <= '1'; -- address of send/receive-register uart_addr <= CV_ADDR_UART_DATA_RX; -- write-mode uart_wr <= '0'; -- save data received_data_nxt <= uart_din(7 downto 0); -- next state state_nxt <= SEND_LOOP; end if; -- send back saved data when SEND_LOOP => led_green(1) <= '1'; -- check if send-register is empty if uart_irq_tx = '1' then -- select uart-interface uart_cs <= '1'; -- address of send/receive-register uart_addr <= CV_ADDR_UART_DATA_TX; -- write-mode uart_wr <= '1'; -- select received data uart_dout(7 downto 0) <= received_data; -- next state state_nxt <= RECEIVED_LOOP; end if; end case; end process; -- default assignments for unused signals gp_ctrl <= (others => '0'); gp_out <= (others => '0'); sevenseg_cs <= '0'; sevenseg_wr <= '0'; sevenseg_addr <= (others => '0'); sevenseg_dout <= (others => '0'); adc_dac_cs <= '0'; adc_dac_wr <= '0'; adc_dac_addr <= (others => '0'); adc_dac_dout <= (others => '0'); audio_cs <= '0'; audio_wr <= '0'; audio_addr <= (others => '0'); audio_dout <= (others => '0'); audio_ack_left <= '0'; audio_ack_right <= '0'; ir_cs <= '0'; ir_wr <= '0'; ir_addr <= (others => '0'); ir_dout <= (others => '0'); ir_ack_rx <= '0'; lcd_cs <= '0'; lcd_wr <= '0'; lcd_addr <= (others => '0'); lcd_dout <= (others => '0'); lcd_ack_rdy <= '0'; sram_cs <= '0'; sram_wr <= '0'; sram_addr <= (others => '0'); sram_dout <= (others => '0'); end rtl;

-------------------------------------------------------------------------------- -- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 14.7 -- \ \ Application : xaw2vhdl -- / / Filename : dcm.vhd -- /___/ /\ Timestamp : 03/07/2016 00:14:36 -- \ \ / \ -- \___\/\___\ -- --Command: xaw2vhdl-intstyle C:/Users/Yakov/OneDrive/School/University Stuff/ENEL500/test232/ipcore_dir/dcm.xaw -st dcm.vhd --Design Name: dcm --Device: xc3s250e-4vq100 -- -- Module dcm -- Generated by Xilinx Architecture Wizard -- Written for synthesis tool: XST -- Period Jitter (unit interval) for block DCM_SP_INST = 0.06 UI -- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 2.91 ns library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity dcm is port ( CLKIN_IN : in std_logic; CLKFX_OUT : out std_logic; CLKIN_IBUFG_OUT : out std_logic; CLK0_OUT : out std_logic); end dcm; architecture BEHAVIORAL of dcm is signal CLKFB_IN : std_logic; signal CLKFX_BUF : std_logic; signal CLKIN_IBUFG : std_logic; signal CLK0_BUF : std_logic; signal GND_BIT : std_logic; begin GND_BIT <= '0'; CLKIN_IBUFG_OUT <= CLKIN_IBUFG; CLK0_OUT <= CLKFB_IN; CLKFX_BUFG_INST : BUFG port map (I=>CLKFX_BUF, O=>CLKFX_OUT); CLKIN_IBUFG_INST : IBUFG port map (I=>CLKIN_IN, O=>CLKIN_IBUFG); CLK0_BUFG_INST : BUFG port map (I=>CLK0_BUF, O=>CLKFB_IN); DCM_SP_INST : DCM_SP generic map( CLK_FEEDBACK => "1X", CLKDV_DIVIDE => 2.0, CLKFX_DIVIDE => 32, CLKFX_MULTIPLY => 19, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 31.250, CLKOUT_PHASE_SHIFT => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, FACTORY_JF => x"C080", PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) port map (CLKFB=>CLKFB_IN, CLKIN=>CLKIN_IBUFG, DSSEN=>GND_BIT, PSCLK=>GND_BIT, PSEN=>GND_BIT, PSINCDEC=>GND_BIT, RST=>GND_BIT, CLKDV=>open, CLKFX=>CLKFX_BUF, CLKFX180=>open, CLK0=>CLK0_BUF, CLK2X=>open, CLK2X180=>open, CLK90=>open, CLK180=>open, CLK270=>open, LOCKED=>open, PSDONE=>open, STATUS=>open); end BEHAVIORAL;