content
stringlengths 1
1.04M
⌀ |
|---|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:53:30 08/28/2013
-- Design Name:
-- Module Name: s2_question - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity s2_question is
end s2_question;
architecture Behavioral of s2_question is
begin
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity altera_merlin_arbitrator is
generic(
NUM_REQUESTERS : integer := 8;
SCHEME : string := "round-robin";
PIPELINE : integer := 0
);
port(
clk : in vl_logic;
reset : in vl_logic;
request : in vl_logic_vector;
grant : out vl_logic_vector;
increment_top_priority: in vl_logic;
save_top_priority: in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of NUM_REQUESTERS : constant is 1;
attribute mti_svvh_generic_type of SCHEME : constant is 1;
attribute mti_svvh_generic_type of PIPELINE : constant is 1;
end altera_merlin_arbitrator;
|
library verilog;
use verilog.vl_types.all;
entity altera_merlin_arbitrator is
generic(
NUM_REQUESTERS : integer := 8;
SCHEME : string := "round-robin";
PIPELINE : integer := 0
);
port(
clk : in vl_logic;
reset : in vl_logic;
request : in vl_logic_vector;
grant : out vl_logic_vector;
increment_top_priority: in vl_logic;
save_top_priority: in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of NUM_REQUESTERS : constant is 1;
attribute mti_svvh_generic_type of SCHEME : constant is 1;
attribute mti_svvh_generic_type of PIPELINE : constant is 1;
end altera_merlin_arbitrator;
|
architecture RTL of FIFO is
begin
-- These are passing
a <= b;
a <= when c = '0' else '1';
with z select
a <= b when z = "000",
c when z = "001";
a <= b;
a <= when c = '0' else '1';
-- Failing variations
a <= b;
a <= when c = '0' else '1';
with z select
a <= b when z = "000",
c when z = "001";
a <= b;
a <= when c = '0' else '1';
-- Testing generate breaks
a <= b;
gen : if '1' = '1' generate
anExtraLoooooooooooooooooooongName <= c;
end generate gen;
aSlighltyLongerName <= d;
b <= c;
a <= b;
gen : for i in 0 to 7 generate
anExtraLoooooooooooooooooooongName <= c;
end generate gen;
aSlighltyLongerName <= d;
b <= c;
a <= b;
aSlightlyLooongerName <= c;
LABEL0 : case a & b & c generate
when "000" =>
anExtraLoooooooooooooooooooongName <= c;
anExtraLoooooooooooongName <= c;
when "001" =>
anExtraLoooooooooooooooongName <= c;
anExtraLooooooooooooooooooooooooongName <= c;
end generate LABEL0;
aSlighltyLongerName <= d;
b <= c;
end architecture RTL;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_misc.all;
use work.types.all;
entity alu is
port( op : in alu_op_t;
i0 : in reg_t;
i1 : in reg_t;
q : out reg_t;
flags_in : in reg_t;
flags_out : out reg_t);
end entity;
-- report "res " & integer'image(res);
architecture rtl of alu is
begin
process(op, i0, i1, flags_in)
constant RES_WIDTH : integer := i0'length + 1;
variable res_slv : std_logic_vector(RES_WIDTH - 1 downto 0);
variable res : unsigned(RES_WIDTH - 1 downto 0);
variable i0_int : unsigned(i0'length - 1 downto 0);
variable i1_int : unsigned(i1'length - 1 downto 0);
variable carry : unsigned(0 downto 0);
begin
i0_int := unsigned(i0);
i1_int := unsigned(i1);
carry := unsigned(flags_in(CARRY_BIT downto CARRY_BIT));
flags_out <= flags_in;
case op is
when alu_op_add =>
res := ('0' & i0_int) + i1_int;
res_slv := std_logic_vector(res);
q <= res_slv(7 downto 0);
flags_out(CARRY_BIT) <= res(8);
flags_out(ZERO_BIT) <= nor_reduce(res_slv(7 downto 0));
res(4 downto 0) := ('0' & i0_int(3 downto 0)) + i1_int(3 downto 0);
flags_out(HALF_CARRY_BIT) <= res(4);
when alu_op_adc =>
res := (('0' & i0_int) + i1_int) + carry;
res_slv := std_logic_vector(res);
q <= res_slv(7 downto 0);
flags_out(CARRY_BIT) <= res(8);
flags_out(ZERO_BIT) <= nor_reduce(res_slv(7 downto 0));
res(4 downto 0) := ('0' & i0_int(3 downto 0)) + i1_int(3 downto 0) + carry;
flags_out(HALF_CARRY_BIT) <= res(4);
when alu_op_and =>
q <= i0 and i1;
flags_out(ZERO_BIT) <= nor_reduce(i0 and i1);
flags_out(SUBTRACT_BIT) <= '0';
flags_out(CARRY_BIT) <= '0';
flags_out(HALF_CARRY_BIT) <= '1';
when alu_op_bit => -- bit test, no output at q
flags_out(ZERO_BIT) <= not i0(to_integer(i1_int(2 downto 0)));
flags_out(SUBTRACT_BIT) <= '0';
flags_out(HALF_CARRY_BIT) <= '1';
when alu_op_cp => -- compare op, no output at q
if i0_int < i1_int then
flags_out(CARRY_BIT) <= '1';
else
flags_out(CARRY_BIT) <= '0';
end if;
if i0_int(3 downto 0) < i1_int(3 downto 0) then
flags_out(HALF_CARRY_BIT) <= '1';
else
flags_out(HALF_CARRY_BIT) <= '0';
end if;
flags_out(ZERO_BIT) <= nor_reduce(std_logic_vector(i0_int - i1_int));
flags_out(SUBTRACT_BIT) <= '1';
when alu_op_cpl =>
q <= not i0;
flags_out(HALF_CARRY_BIT) <= '1';
flags_out(SUBTRACT_BIT) <= '1';
when alu_op_daa =>
when alu_op_or =>
q <= i0 or i1;
flags_out(ZERO_BIT) <= nor_reduce(i0 or i1);
flags_out(SUBTRACT_BIT) <= '0';
flags_out(CARRY_BIT) <= '0';
flags_out(HALF_CARRY_BIT) <= '1';
when alu_op_rl =>
q <= i0(6 downto 0) & flags_in(CARRY_BIT);
flags_out(CARRY_BIT) <= i0(7);
flags_out(HALF_CARRY_BIT) <= '0';
flags_out(ZERO_BIT) <= flags_in(CARRY_BIT) nor nor_reduce(i0(6 downto 0));
flags_out(SUBTRACT_BIT) <= '0';
when alu_op_rr =>
q <= flags_in(CARRY_BIT) & i0(7 downto 1);
flags_out(CARRY_BIT) <= i0(0);
flags_out(HALF_CARRY_BIT) <= '0';
flags_out(ZERO_BIT) <= flags_in(CARRY_BIT) nor nor_reduce(i0(7 downto 1));
flags_out(SUBTRACT_BIT) <= '0';
when alu_op_rrc =>
q <= i0(0) & i0(7 downto 1);
flags_out(CARRY_BIT) <= i0(0);
flags_out(HALF_CARRY_BIT) <= '0';
flags_out(ZERO_BIT) <= nor_reduce(i0);
flags_out(SUBTRACT_BIT) <= '0';
when alu_op_sla =>
q <= i0(6 downto 0) & '0';
flags_out(CARRY_BIT) <= i0(7);
flags_out(HALF_CARRY_BIT) <= '0';
flags_out(ZERO_BIT) <= nor_reduce(i0(6 downto 0));
flags_out(SUBTRACT_BIT) <= '0';
when alu_op_sra =>
q <= i0(7) & i0(7 downto 1);
flags_out(CARRY_BIT) <= i0(0);
flags_out(HALF_CARRY_BIT) <= '0';
flags_out(ZERO_BIT) <= nor_reduce(i0(7 downto 1));
flags_out(SUBTRACT_BIT) <= '0';
when alu_op_srl =>
q <= '0' & i0(7 downto 1);
flags_out(CARRY_BIT) <= i0(0);
flags_out(HALF_CARRY_BIT) <= '0';
flags_out(ZERO_BIT) <= nor_reduce(i0(7 downto 1));
flags_out(SUBTRACT_BIT) <= '0';
when alu_op_sub =>
res := '0' & (i0_int - i1_int);
res_slv := std_logic_vector(res);
q <= res_slv(7 downto 0);
if i0_int < i1_int then
flags_out(CARRY_BIT) <= '1';
else
flags_out(CARRY_BIT) <= '0';
end if;
if i0_int(3 downto 0) < i1_int(3 downto 0) then
flags_out(HALF_CARRY_BIT) <= '1';
else
flags_out(HALF_CARRY_BIT) <= '0';
end if;
flags_out(ZERO_BIT) <= nor_reduce(res_slv(7 downto 0));
flags_out(SUBTRACT_BIT) <= '1';
when alu_op_swap =>
q(3 downto 0) <= i0(7 downto 4);
q(7 downto 4) <= i0(3 downto 0);
flags_out(ZERO_BIT) <= nor_reduce(i0);
flags_out(CARRY_BIT) <= '0';
flags_out(SUBTRACT_BIT) <= '0';
flags_out(HALF_CARRY_BIT) <= '0';
when alu_op_xor =>
res_slv(7 downto 0) := i0 xor i1;
flags_out(ZERO_BIT) <= nor_reduce(res_slv(7 downto 0));
flags_out(SUBTRACT_BIT) <= '0';
flags_out(CARRY_BIT) <= '0';
flags_out(HALF_CARRY_BIT) <= '1';
end case;
end process;
end rtl;
|
-------------------------------------------------------------------------------
--
-- SNESpad controller core
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- $Id: snespad-c.vhd,v 1.1 2004-10-05 17:01:27 arniml Exp $
--
-------------------------------------------------------------------------------
configuration snespad_struct_c0 of snespad is
for struct
for ctrl_b : snespad_ctrl
use configuration work.snespad_ctrl_rtl_c0;
end for;
for pads
for pad_b : snespad_pad
use configuration work.snespad_pad_rtl_c0;
end for;
end for;
end for;
end snespad_struct_c0;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ring_counter_tb is
end entity;
architecture ring_counter_tb of ring_counter_tb is
component ring_counter is
port (
clk : in std_logic;
Q, Q2 : out std_logic_vector(3 downto 0)
);
end component;
signal clk : std_logic :='1';
signal Q, Q2 : std_logic_vector(3 downto 0);
constant period : time:= 10 ns;
begin
uut: ring_counter port map (clk=>clk, Q=>Q, Q2=>Q2);
clk_proc:
process
begin
clk<=not clk;
wait for period/2;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: RAM_double_multiple_access
-- Module Name: RAM_double_multiple_access
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavioral of multiple memory RAM that shares the same content.
-- It is useful when you want to access more than one location at the same time, and
-- the locations for each access can be anywhere in the memory, where in banks in most
-- time is one address after another.
-- It can be seen as one single with multiple I/O operating at the same time.
-- In this double version it is possible to read and write at same cycle.
--
-- The circuits parameters
--
-- number_of_memories :
--
-- The total number of memories or the total number of I/O's applied.
--
-- ram_address_size :
--
-- Address size of the RAM used on the circuit.
--
-- ram_word_size :
--
-- The size of internal word of the RAM.
--
-- file_ram_word_size :
--
-- The size of the word used in the file to be loaded on the RAM.(ARCH: FILE_LOAD)
--
-- load_file_name :
--
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
--
-- The name of the file to be used to dump the memory.(ARCH: FILE_LOAD)
--
-- Dependencies:
-- VHDL-93
--
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
entity ram_double_multiple_access is
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR (((ram_address_size)*(number_of_memories) - 1) downto 0);
address_b : in STD_LOGIC_VECTOR (((ram_address_size)*(number_of_memories) - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end ram_double_multiple_access;
architecture simple of ram_double_multiple_access is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
for I in ramtype'range loop
memory_ram(I) <= rst_value;
end loop;
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw_a = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address_a(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index))))) <= data_in_a(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
if rw_b = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address_b(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index))))) <= data_in_b(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
for index in 0 to (number_of_memories - 1) loop
data_out_a(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address_a(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index)))));
data_out_b(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address_b(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index)))));
end loop;
end if;
end process;
end simple;
|
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate for_label;
IF_LABEL : if a = '1' generate
end generate if_label;
CASE_LABEL : case data generate
end generate case_label;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
end generate for_label;
IF_LABEL : if a = '1' generate
end generate if_label1;
CASE_LABEL : case data generate
end generate case_label;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Vrefcapofkplusone is
port (
clock : in std_logic;
Vsigrefofkofzero : in std_logic_vector(31 downto 0);
Vsigrefofkofone : in std_logic_vector(31 downto 0);
Vsigrefofkoftwo : in std_logic_vector(31 downto 0);
Wofmofzero : in std_logic_vector(31 downto 0);
Wofmofone : in std_logic_vector(31 downto 0);
Wofmoftwo : in std_logic_vector(31 downto 0);
Vrefcapofkplusone : out std_logic_vector(31 downto 0)
);
end k_ukf_Vrefcapofkplusone;
architecture struct of k_ukf_Vrefcapofkplusone is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_add IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z4,Z5,Z6,Z7 : std_logic_vector(31 downto 0);
begin
M1 : k_ukf_mult port map
( clock => clock,
dataa => Wofmofzero,
datab => Vsigrefofkofzero,
result => Z4);
M2 : k_ukf_mult port map
( clock => clock,
dataa => Wofmofone,
datab => Vsigrefofkofone,
result => Z5);
M3 : k_ukf_mult port map
( clock => clock,
dataa => Wofmoftwo,
datab => Vsigrefofkoftwo,
result => Z6);
M4 : k_ukf_add port map
( clock => clock,
dataa => Z4,
datab => Z5,
result => Z7);
M5 : k_ukf_add port map
( clock => clock,
dataa => Z7,
datab => Z6,
result => Vrefcapofkplusone);
end struct;
|
-- $Id: rlink_sp1c.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rlink_sp1c - syn
-- Description: rlink_core8 + serport_1clock combo
--
-- Dependencies: rlink_core8
-- serport/serport_1clock
-- rbus/rbd_rbmon
-- rbus/rb_sres_or_2
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 13.1-14.7; viv 2014.4-2019.1; ghdl 0.29-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa
-- 2015-05-02 672 14.7 131013 xc6slx16-2 495 671 56 255 s 8.8 - -
-- 2011-12-09 437 13.1 O40d xc3s1000-4 337 733 64 469 s 9.8 - -
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 4.2.1 use rbaddr_ constants
-- 2015-05-02 672 4.2 add rbd_rbmon (optional via generics)
-- 2015-04-11 666 4.1 rename ENAESC->ESCFILL, rearrange XON handling
-- 2014-08-28 588 4.0 use rlink v4 iface, 4 bit STAT
-- 2011-12-09 437 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.serportlib.all;
entity rlink_sp1c is -- rlink_core8+serport_1clock combo
generic (
BTOWIDTH : positive := 5; -- rbus timeout counter width
RTAWIDTH : positive := 12; -- retransmit buffer address width
SYSID : slv32 := (others=>'0'); -- rlink system id
IFAWIDTH : natural := 5; -- input fifo address width (0=none)
OFAWIDTH : natural := 5; -- output fifo address width (0=none)
ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
RBMON_RBADDR : slv16 := rbaddr_rbmon); -- rbmon: base addr
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ato time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ESCFILL : in slbit; -- enable fill escaping
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv4; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
SER_MONI : out serport_moni_type -- serport: monitor port
);
end entity rlink_sp1c;
architecture syn of rlink_sp1c is
signal RLB_DI : slv8 := (others=>'0');
signal RLB_ENA : slbit := '0';
signal RLB_BUSY : slbit := '0';
signal RLB_DO : slv8 := (others=>'0');
signal RLB_VAL : slbit := '0';
signal RLB_HOLD : slbit := '0';
signal RB_MREQ_M : rb_mreq_type := rb_mreq_init;
signal RB_SRES_M : rb_sres_type := rb_sres_init;
signal RB_SRES_RBMON : rb_sres_type := rb_sres_init;
begin
CORE : rlink_core8 -- rlink master ----------------------
generic map (
BTOWIDTH => BTOWIDTH,
RTAWIDTH => RTAWIDTH,
SYSID => SYSID,
ENAPIN_RLMON => ENAPIN_RLMON,
ENAPIN_RLBMON=> ENAPIN_RLBMON,
ENAPIN_RBMON => ENAPIN_RBMON)
port map (
CLK => CLK,
CE_INT => CE_INT,
RESET => RESET,
ESCXON => ENAXON,
ESCFILL => ESCFILL,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ_M,
RB_SRES => RB_SRES_M,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
SERPORT : serport_1clock -- serport interface -----------------
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT,
RXFAWIDTH => IFAWIDTH,
TXFAWIDTH => OFAWIDTH)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => ENAXON,
ENAESC => '0', -- escaping now in rlink_core8
RXDATA => RLB_DI,
RXVAL => RLB_ENA,
RXHOLD => RLB_BUSY,
TXDATA => RLB_DO,
TXENA => RLB_VAL,
TXBUSY => RLB_HOLD,
MONI => SER_MONI,
RXSD => RXSD,
TXSD => TXSD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
RBMON : if RBMON_AWIDTH > 0 generate -- rbus monitor --------------
begin
I0 : rbd_rbmon
generic map (
RB_ADDR => RBMON_RBADDR,
AWIDTH => RBMON_AWIDTH)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ_M,
RB_SRES => RB_SRES_RBMON,
RB_SRES_SUM => RB_SRES_M
);
end generate RBMON;
RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES,
RB_SRES_2 => RB_SRES_RBMON,
RB_SRES_OR => RB_SRES_M
);
RB_MREQ <= RB_MREQ_M; -- setup output signals
end syn;
|
-------------------------------------------------------------------------------
--
-- The T8243 synchronous toplevel without tri-state signals
--
-- $Id: t8243_sync_notri.vhd,v 1.1 2006-07-13 22:53:56 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t8243_sync_notri is
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
clk_en_i : in std_logic;
reset_n_i : in std_logic;
-- Control Interface ------------------------------------------------------
cs_n_i : in std_logic;
prog_n_i : in std_logic;
-- Port 2 Interface -------------------------------------------------------
p2_i : in std_logic_vector(3 downto 0);
p2_o : out std_logic_vector(3 downto 0);
p2_en_o : out std_logic;
-- Port 4 Interface -------------------------------------------------------
p4_i : in std_logic_vector(3 downto 0);
p4_o : out std_logic_vector(3 downto 0);
p4_en_o : out std_logic;
-- Port 5 Interface -------------------------------------------------------
p5_i : in std_logic_vector(3 downto 0);
p5_o : out std_logic_vector(3 downto 0);
p5_en_o : out std_logic;
-- Port 6 Interface -------------------------------------------------------
p6_i : in std_logic_vector(3 downto 0);
p6_o : out std_logic_vector(3 downto 0);
p6_en_o : out std_logic;
-- Port 7 Interface -------------------------------------------------------
p7_i : in std_logic_vector(3 downto 0);
p7_o : out std_logic_vector(3 downto 0);
p7_en_o : out std_logic
);
end t8243_sync_notri;
use work.t8243_comp_pack.t8243_core;
architecture struct of t8243_sync_notri is
signal prog_n_q : std_logic;
signal clk_rise_en_s,
clk_fall_en_s : std_logic;
begin
-----------------------------------------------------------------------------
-- Process edge_detect
--
-- Purpose:
-- Implements the sequential element required for edge detection
-- on the PROG input.
--
edge_detect: process (clk_i, reset_n_i)
begin
if reset_n_i = '0' then
prog_n_q <= '1';
elsif rising_edge(clk_i) then
if clk_en_i = '1' then
prog_n_q <= prog_n_i;
end if;
end if;
end process edge_detect;
--
-----------------------------------------------------------------------------
-- clock enables to detect rising and falling edges of PROG
clk_rise_en_s <= clk_en_i and
not prog_n_q and prog_n_i;
clk_fall_en_s <= clk_en_i and
prog_n_q and not prog_n_i;
-----------------------------------------------------------------------------
-- The T8243 Core
-----------------------------------------------------------------------------
t8243_core_b : t8243_core
generic map (
clk_fall_level_g => 1
)
port map (
clk_i => clk_i,
clk_rise_en_i => clk_rise_en_s,
clk_fall_en_i => clk_fall_en_s,
reset_n_i => reset_n_i,
cs_n_i => cs_n_i,
prog_n_i => prog_n_i,
p2_i => p2_i,
p2_o => p2_o,
p2_en_o => p2_en_o,
p4_i => p4_i,
p4_o => p4_o,
p4_en_o => p4_en_o,
p5_i => p5_i,
p5_o => p5_o,
p5_en_o => p5_en_o,
p6_i => p6_i,
p6_o => p6_o,
p6_en_o => p6_en_o,
p7_i => p7_i,
p7_o => p7_o,
p7_en_o => p7_en_o
);
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
package test_pkg is
function return_one
return integer;
end test_pkg;
package body test_pkg is
function return_one
return integer is
begin -- return_one
return 1;
end return_one;
end test_pkg;
use work.test_pkg.all;
entity test is
end test;
architecture only of test is
begin -- only
p: process
begin -- process p
assert ( return_one = 1 ) report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
package test_pkg is
function return_one
return integer;
end test_pkg;
package body test_pkg is
function return_one
return integer is
begin -- return_one
return 1;
end return_one;
end test_pkg;
use work.test_pkg.all;
entity test is
end test;
architecture only of test is
begin -- only
p: process
begin -- process p
assert ( return_one = 1 ) report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
package test_pkg is
function return_one
return integer;
end test_pkg;
package body test_pkg is
function return_one
return integer is
begin -- return_one
return 1;
end return_one;
end test_pkg;
use work.test_pkg.all;
entity test is
end test;
architecture only of test is
begin -- only
p: process
begin -- process p
assert ( return_one = 1 ) report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
VMrHUJ7jR2a4on8XaeYhAjIaz4rRbGfwW8VHamgJPReOlpXR5SnSuFHyXpuBXjJtExIdI4sljp69
+hXbGMBP6w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
V60B8mHqwCWcAQivsECFj998ByvDjB+8JeAAOvVLZEni4XD/2U9vfLmYo3cbFA7NMwmRaGCTY/HS
60s+TT01wMgHgujfEF49/mRJ1glpwP7EhB84g1K7xdtpOxYzMggfDKm9YDHGdz17ha5r9njnY1zy
JipFw5giX28n8uHL9G8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
GKYRZjR/TFpnasPz3c3jVHgchRKQZzQmbeBlvkY7oOgwxypd/dr4VwpVMi0c/+LrTgTuOuMQWz2+
vRSLHWdQymehN5n+43A7V/DOnpsZhWNbBZjAAuoAfwm2rYmgABKSNALo8Z848RWnPvSJMnRNGZpC
9BkLlvkk/FGaUYmfKejiN/kDk7F+OC0xZKM06r67ElLn3O2SM3TuNkYTyDXfz95kCBzmkR6aRsXS
coxZYmkVs3Bzvl7yGV7eK4o+z/3pK18wgBXBXKPtKxy0OidDULBiGLl1ZKQMbtBMZsj4eKSkFDOv
DgdJpMEyup8XzH4YzfI4QinCaVxQwuGZ6+xZlQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
pXvJEU59cRATVhmRJ1vsVWJPmFqdKz9UXT5pm7AP0hDS5zf02+kgpTD6arJVkG/T6Lh+I5bkhqT2
BXrjBzlv9yK8zwQamfQphBZUgyovPxbNO/0apAj/dwXgXToNeC8wjGMKOoPVkEAFgLXC9pbMEfXH
q7zz+PYXcMJbejWqEF8=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
r5I5r1xSDgVITJSqT9zg4YQgFLAtqfFW7eaJ/VcLwoK4wHV3PLEhK/YA8kF7MbXjDSnIB1jq/Lbq
d6Uuvb7kijHkFrESXiLB+MGWUasIWXJUZK9t7gT8tA9FiSeXPGQ83fgMtOifSov62C3dAsdSYWXH
CA2noMSeo1xFTmVQKw81KxLnv6RExz75rRcPSDjnLnjq0wC4qY6irtnNTR2Ksvj6OlRXYQSC0Lnn
tUsCjZyHrR7WdazpAChMTAv7/FNpfqV7Vn+ftdwOXXzoTOyvsuJ3L0sdwjtiFmDB7P1LM/g5nIHl
nUJ408y1B08faieNRdh1D4XkCbRg017ZqjwE2w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13392)
`protect data_block
KtAu6lOpfhhiJMKUeQgWfQaqAFeGT6VM8dflx+KL4IWP22gxzGk7dVp3rYdTkOJTcBl3oC1L91cx
/1Cnv0TE5rO1BXSRtTIlnC62+xpU4iNdOsPkWXJt4ImOpV6V3uck6luHN0ec4jQwmhLTx07XSPmD
VO9Uj129zbM2Sf57PVGBpe7nbK79iv9e8bWeo0ekO1kEqLRejlsK9sjxoxM8dcXpXACbpn5xJ6c0
p4i741eSxyKHu0ejKMdlMoTDjvmWAaW4oUQMPKwaRBDj6TdjPcBIMqqdbjh0HoPRYO9MzRXdNoj/
IYQsrXWYPACKFPSWeFyk+SBkA3ZU76pLIhasSm/sttOri9EBG16/6E8Z54aRpnjjYQsutIIM8R2j
Hdlzz3lCRMIXZdEaNnODfv5Bs6PqEBLhpWFiMsLM+i+jlRoyuHJ6xjY76w/GiXXNenaqyYIR+APo
RCcXaYdqFvLDm1p0wJvANDawiBdRVxwj1xLbzveQOt3Ln/s+dgCbbr2ktQx/XYCTkzNrf1DojRQs
DpZ+FCTYDM1W2+XVHrgMCccLMRcH3QgUvZLdMv1UtqmPuzbyaDmLJaGgrNFD2wLdhWv1pPsPiGTV
A+PICqpCnuLCD6dvuuDYfiE41iifFzSWen1OZ92DZLCzdnq+NghuPPdg5jAW/ajyq42scJ783D0a
2K3s93M2B+flxrfpvB9RVAYqDXg7ekpuBg+rPqDicLSOULbmHEr5nEKWoJalwLEvH5fXuLWNfgyb
/Z2xtHnRJTerjPQHd4OdB647tIYVcn+FCg91U5NC3Il+CEKSWYln0HQMvu1gK0vWNaGldZvsJXS1
ER2WR+woHT5+uocyWj/wRPjvHSFPyuE2VzRV1GdPYshxcMkFi5l+kWXpjadQuZVTViigRb8Z29GA
tj1kB67Y2SfrjRLOuOZVTW6PhByEPMnfp4iuupAL6OM9+IYOLkqmytw3hn3TxZz6w1rSojvRQ6V2
JTiFdIevPwCi4kSMf9D0e9+vesa+g0zACQur0GfGrnNtkgn/N65WqV3HQT04C/lc0T8KXRXHotv2
KR0E2S/U8c+YmqfamQ5kFNBnQnwv4mPOU6ETVMiS2YWoDLjCkwUbRTK0nvdVDMItW5PWrGAwqPLk
x8lrqCk1HWsRqqkJr6aNPxPOHvMTOqXgvvaXRnKFWnyc06YpG4Wi7Wz1DkDCFBpCuzSI4K3WJA91
fmSuK10HtfLQzETj6QBCDJM8UHaSi1KBI+lZEX3O8tDiNonS/gJkf0KuLt4Gg6+ZO8/WWsJtd+Yo
Y/MCM6gG10i5qOohsDv16MoM6c91u5uwvXsavqfjuCy4JFa+RdANwf1NmmiYf8yxBi4foKqWBvlu
XQuPggLbGzAo45Z45T/Y4oBUZSpRa1FwunUxJEnY6RjLhxkvUbOf6FFgPa3TVqw752urFFAb+RsH
S8EgIeawlQH2rmTOhEJBfJRb16zQ/3xaLiS/6kLsE5JBqtgrb3mKVqh9PCyWOmseHT1AxBr0+aP0
GBG/PyBaqfgIk+9fIkW2W1BTAaz04eDtv3cF5m45gg+wzKTckS8BNk/+tTEhv+hQgQxbdODlqofx
vrZto4baZaHD+M7V+H59TENSaGnzd0fXJ13MxG29qoXrCaJ5HlPT9n09WE/9WC/sOC60PHos3B6G
v8Egt47JBvrmDcgljBvYHnxOFVmLXwx3V5tFShRUmq0uGpbibXbTMkxyJURlkJCc+sXHp6bh/hNh
XDJCesEXQnuWBUk3lhyc2LdgXhBQDjsl5ezP6s0UqE5VXe0MZS8Xu6Y93WP4ApK4fMUcKBqjfxU7
gx+F0zEXX/tUOTchTPLZXCC/R73+ehq6ZSKjIo/PsVkII7G+G4zC6tLCa8cMFSua1Egi7VaRrv7h
eOX2SgKkjboJK3H6DoqdH5sUsAgsckWtj6EmADCfWgJPJkziQYD2X7hPEpxU69AHBw21bYYCdkE0
L2sbor15Cet6k8wZmU5Qd9AdDa0rzGP2vQwCQZfy8xfOnkCExm4keLdGvOxedFkX6oCou/OZtLC5
seQDxm2qdyV9tmKrUlZUv5c2EE8PiTxhVnCXeU3EA0Fsy7YFXR9KTSqZJVOhSvbu1834E7v65yis
+YgdquOItIB/dujyMKyWMHsxkwtGm3/nNpW7SoYyqf59qTefO8gcOFwjujLMGaX8xLx0bgkG7OKy
qlCAZl02XYrHsXSe7OpYO5NAdu5nKR17+QDG6uqMNdiItPXzZxH5M6fVZA9gdmcwKsI9iE3+a8Vi
/fNq5/wTd0ReYWEsueU0YKFbvNNgLf/dqPdylVuU8PKhJrHalElU62RDyLfr724GuhBdGDBlGjoN
1UdE3fe+UzcUQm+fRi0JDByqI/H/yGZgWAmE7MY4thSx8HkJf6nMRjr8u4SEjwix2IJ7Z5xJpQGF
qximcuXUIk6cX1FjBq5Sd+Ozk2JmWvxLfA5uRjeJwRd109thPcsQ3gEZG6Bm1wfr7W/ZpKD+1BKL
xMSG3jj9cb2pxmn7D3Rah3q1TV98H7T8sKN9h2j2ZaytJNU+ZdHG80ZKkFVMDN3m1jBWo93SkqMn
XnPSsVVBAkvy1NteShwmVUKh1HI03rG8ORyOs4zEcygSe9NWnZs6ytiFaxChj7sjzYdJy8qaVMtf
enFAkp9VtCM/YL5crMVf5858JuM4l7tTXw9DuxuddYI6uuz4Uy5bTymZEASwa1/+QnSGXkFyfjQe
E4SqVO2VcPiZ2TA6CHFTM4gMVoC2w954suZ4YRP2Q4h1X77cZlIo9q7ZESFPneNyg9TteU4+cl0F
+ZuXnhUGRTtWZQKD3mkBQjRBytkgXcZD/AEm+E5kFRQ4gqyK2UjBm3x4ulu4V2+kqZQfUVVXVCPB
pw5EwMMqB6xfbu0N3YZM6Pj8Y9l8zORPdp5AWioiHByEdEnm6K4tGx0Wzd7vCfUoTmZdXlCa7vnA
dCOo4VSrpw3tijA7Otl7JtVe1HcIYzeCGzsYhzWfGgKeO6J3xxJSWqSXJss5c72gctvTkDGJ7L8m
KyfuFVy1BA1Os9QxrRdLPiuptc1EGnHCQB/Z/3t0JXQ2AAJwWWE7EvPIGoBA7C0XSM+IPCC4Rp8u
F5eQyIjJyp/3Xacg+A0M36sZjQ9Tv0ua768/q1xufC7MUYxlPlr/59mxdSXhCZoxQyAzq0ob7YA6
GfG3HhxQ5V0nlJdmdN3rtyQZF/x2Mb4BABO6pXgrP+fyrzlZtVJI7ULGEWRp4O3Cke3A6h6RtVXk
Kal75VSX4fguegatIjvj1QMwLlyr1s0Ehf87ADEE2CiqordMZWZABgbApTrI5MZcSLpV7ixon0BC
z/zpFPcbPPPPzJ1kBSq9f7+POuEpo2qfpnqe4nKMDiCNpJA1XZc9icX0gcNpaMD7pLAFZmYnOZWI
HUxZ31aWnkwzRExkUbngQKPbXhsBqaBiMufzC/cA6iXyNataSvNI475Bx/RdxiTukZezLR056F7H
bkNQ6IiQyhzJMvOc4Fy1Ge2zDtZOffcD4FKL4b9pEPJp2MLZB4c7dwkoK2zFj0/6O6x+uaeCj/51
UnlP9k9K1O/Ek/y4Q3D3xzvuFxLwX1E0hbfe4dDgsMQPfD6LPY5A/0ZLGxTzYC3gxuiP2tnM8BHm
xqFmWmIGL8Nkj5mLtsOwURE8fdksfCw6HGRj4nysOmK/D9tA2LaXMaKu0tvab0hUbxnW/DUm10UI
RR4PyIHO+66KjYapXAalXWBw6bGR9uiOUuzfP0jzD/j7DfUEznFuGpYAkfxtHZbSKERWzVUlQEhi
uwyticDxBg5o7mkEQnHuREykNRAbz9OlqUdtpzk/nbgDtcCNuF0v9FHk/EDe3wzrX/Tj98fcRsRf
aAsyPb6nIG89ioTWL6ZNmxF/Ft0ma6+liPBqGaZ7pG59gyvzMIujhLP27qlbWvqtxwd5IW69yfJc
Rpd/bSGQKYpRJrpHN3hGIdsyYCyuyB8WIGeaElRlgZwBE7eZI5j3GlnYjGiefE4eWJ+CuAkQnvyO
yEQfbERrLSpEEFS9oygelpLIWtIUfa2+bypsEilA4ccH3ALJhnbOFguPlGLpJs7NlexiJa9xttgA
tWUq22F0Vl5Cj1kZvtxGZMIfQCwSiYMS+daS9PHhtkqrylJtsbOTxYEhC6dO+v79rr7LH5UMLuhO
Z3KrJ+IVdwlOA7sexF/1duCreNLBbnYrp+VPnJCK1LpPfgtSlWk+/4wHEwnLmCysbO6TqeMOX6z8
RFYv7o+GN9XC756ctoI4aFVXWhltwJVUrcr5qqK7FZ6xLGhjdVo2VOEQWz/bc9qM1u2teBRzOQIk
ksCQcPrge/Zni8HuaEqtP/8mx44KGlxNUhFJW/eNrich/lIBLOt7JqDRc89+TK60q/W46arZ+BEL
IbOukqGcixAht4NtdA8KBJLac72folUZFyq6uMY5SIpakCk5puD+jLYwzGfciJzGzrLInKiB5lzh
V40TUVUfZMccYoeOXHdk3+T/vHthMO9nZ2UIWApEUdusSYRH27Dqvk0eZXxedBXtHBJPhxxIiZ8p
EbpwXKmGXVGMQIbY75L3EbP9Y0LNK0so9CYZqivll+pUKOpyLOsqDGFdG9ayqwy7w9J6la/W8h/h
fCZmzHsUFLCrHXyF5p9r8AL9GGdc7ReIZ9sNdAlfOxI/ZEx/hbnv7HFDrBz3Xx117NL0DvNzMBcf
Fiazfjgk3tthUkGiFgIyjy25PaA/k52kLIq4MAyIFu7O2dZuiyD77jjAkZG0hK/om08L2Nq9+wpX
wY6m0TnwDLggEqT+ojgeSh6gI72AIZvnRbDRMsR/wlNRQYksbX5yq7cp32CqsYWT+/Rg/jue1Bnc
7wtlBBec9KDMQvgYre0GJ/pZc0wRG0yeOjaUJEgd3Qw9S6jNcGglR73A7TWQ7HCspRJkQYneEdVO
xTls5U3jmqoB/fAJvouUmUEyskQRXzQyPGISIE2ZJLW1HXA9oFQvCcXCJGEuXdixoHU4QJssRgSd
k0OFyC29yVWF8s2LPpjfSi0s2JfrG6tLjN9LkNINfZXe072f3sXdH+XfjwK6erUscc2YxkGiYTWJ
V5E6e22ApEPsEhG7kxspUQi/OB2JDo6Gns+30iUR2y33HJ4ZWy6ttOxrEIlkgKFS05hQn9ooirQL
EbuOeFNbPsGUQ53+Gyz7GZuO3PiWpOEhXvk9U7HfMW0XWV3NEAhnN67vbH7A51I/sgnrkk5W8iL1
PV2vcb6H2TUa3/cFfcnaJSIB3NwP8wvFt5Lu5YUtf59D6mRp/JAutb8FApD+Bz69T22LkrISdxIz
Tk1gern+mDrUuOGu/guIHNnYnR3cY8meDhU1Tw4KgjND8k7bO3XvhUQ4DL8/FERDc3Hu8ZkllG4X
xe+qzUY6Jr4iWjIurCfQQ1yFehXf8AFvO970wYg/W9brH2/tiazw6eMMEH/vGl6pbus4Ydzq+RDa
zRLXrEKb/l0QXkZaK1qr51T+9qoFS1gpQQbwvV3MFfm6oviHkESYHQmr7vBuJMWJgGUYaQYANeuZ
aPFiz8h5lu4j5dDOAGPymmFKy/rjnhRrj1h5dfOfCUjQHkuokoRpfq2hhk8meY1jjT6Mq9KqAhY6
DdGQg+VT7RNE68ZL8/UkxP5QJbpiDVXcMAsEcSdW8g1JLHOazsbJczMEWWrFJFNVG0/QOri3ykni
vNCytio4klf7TBY+JeGNPm8bRifJt5voKJZtACxE8H1cR6+Xi+vvX32+BJ1CjcbUQZlxlBWiopan
2LIXFllhqwR2R4ePyMoCsgsQNqdKPT5rhk4Qu6ZE42DWGKJYijDLKwy6jt2GvX5FvdPC6Zot7QmX
YpaiJxxoVM/KkpBg0ezNJtEyGH0EOOyamVVHtbgyF5+4Fu2rxk+jcwhHxwHneBocmuXt1v/jw/XJ
a/mO+goEY+iV6g7B8wvkF3Gp174s1cm0sIgla4WU8TN1Rhx1K89egoY+NLH88Kr1dLRAaFRI/Ra3
+r/va9E780Z0B6UPXl/wc36fgSfyuwh+0qehPOlsmhyq5CYpVyhfhrTcdfIFwgJh7pQuJpx+wa/C
ZShtqX4+1WA6YtusYrAHStAC8f/COdQvkraoeEaETqrq+k4WQDYNfWFNXxt8N+1/lvi0Q1iOjHSM
Jr+omK7G/y5pgZjmyZQ3Xqv3HhwAX+tJtOBAtywGEwUrzHAKRcD+IGzmwQNE6+Edu8AhclD1jiho
I1TkNUNcr7I8tbN3AgXy9uMN+Xl2576TN51ppNqX5WQBhI6NbdaXvfZojCd9C+n8ZAXaJMXd5Pgk
OHBtILdUfUrXjaIj6UMkdTP1MmRfX2D/IgLUVDoAfa2JURAF+PNoCbNR0/uG2zeuYccRSw9Xxi0T
pm8VimXiGd/w14mqIYtbE9nw52Pe+uuMDavHlP7hMk6ZQasLjI486s8PkkPDvqbvPRi13oWjrA8M
YDoilq7EyDh+krZy49kdeDNRHDOe1YPQFArryMmBEinJsnhvxIc/HKyzbKbz9LYR908id3Aezxmt
c9TXQTAEx3Ju6hvkE2q648++10Yhzsy/9mX8jLrqsVLnKd9M7l23HxkOwgEHAWC6ebjf1pF1ar9d
A60Kq6eX2GkJhcALBa+zzGVAniOrXQYAT9A9w+X6Au4nXovDVo5BMrakexRBEhEzOIyXr3/86qCl
UATvA2qAmEb4RsOHYpUlauWcd2KNBnk+9muZ2Q5X5r9eK2FxTF+1q2RPnP8SCZjgKFsTBQYIDxso
0m9BhxSdWpTK2BOhAPmPYbp02DHkDzyy/0T1TtZCUlwSyGK5P4pNIeWgpaChv67J83mWH/zzxjl2
bRA3BTLW/9UQjo13IMpwxG7fXdjow9M4E0eNXOQJhQapSZbac30rdgJmUsGICbxbsiS0ENB/Sf0w
+/ACabb/y3CUXGHELlWQ9ZjdPISKSPpYhBX4KoiAHo6TECeMADrXPuYQ80mNalKN/OvG1JK0c6Xy
eF02NsfOv4PguZSiZh5zUABkiui/cFvWLD7ZmfTEEQ3Yf4jbBx2jA/j2c2tGo3RjksAjfOIGuOSN
Z9RPfjSpBaya9Nuabbzhax02r7JoGwv7dJBJ/zQb3tx7fPuMAzL/hKoSr+ee9d5ZzAEFpBvMw4Dc
2gqoHCPQ1lJ8Ec/mo+axX3lZrK3WnJ3DRmH/zV217ehNvnAwWag2dzWSeU8WzQ9NUvz/gcw/0Cam
MtKL1yY+TVpxIAIq3RiU6fu4K/Q0k6IHloxasxKwoy+ZiTZTrd6KHQrOZmUc7XC1BeJyzyEnbDUo
ecgDvFCyE/vKUrawJOYM2Wjj9vtidY98UIhgVnewdI0INrcQAm24JmwW+XxaA2VzD63LtPDtGBUn
3NMuSQrLBGvy+XMJU5E4PtA1vSWIct4G/+TPvfxx2Mubv5DQXTIEvVfqSFtQ1exMGhzJbKsTr60V
ETWiyP2quBHeFaevlGfTabbPpu6cmqgAdFCAntS3KHLO2DwW1DvLybrUhBQsPm+b6kDHfFRe0y3J
06Uefsm33g4xCqszeTcuFSz6B75NJsNA7yJZaiVSE8BUFer84bON0fMOc2kaKXw6Khkv+tIHGoCT
t+fzhDK+QposUpIQMZbqOYePQWqB8/uUmqR953z98UjcxwgPeWk2LmTKX5SyMw4WgXRHz8I2TX6k
rhrfZYqy5vuAwsuPxJe/sYxt8PUPf9szN8FUvViRwou/fJErjq/QEVOTEXKRqwE4Z5LPmY/ETzEv
Q+TePW22qr0MnTvD6kk33FAuU9FvvVf9uMwG/izLcM5q1d56WcgMFrEGwS+mqqSFGt7U12AJAASw
Ym/RKudAYH6z9v1c1NOaoRJQlwPm69eJJI7wkAAI6xKOyM+x6/WbddfMS8c8Z3NCDclaimFwvrBT
r5zIs8sBX9M1te7tN7ohb/4Vi/oRilPpbb6BUIC/nyYZOLPn3W6sadcJgTet50R9Ivgum7y2F9nr
qC2aZjqE6MkVTbYA8eJLDsxwsQemYQr3y8beE2xJdPGJurQpirHak0lLatKhYh5j2A6bIrFUA8Sf
baAY2qe5qaEY8Q7fH9LawEW5GjLFGPW/PgfczM0xytXUHmgBRlc9vwKDow1dPtWYKCN2ByrBZQY6
Tb3oAQ565/t8/h1yzwL+HLJp5CXV5gHQyOkXA8DawLgdjaN5Lci5Rr/0BzAOrslDiiuY/j6LoOP+
6LYgR16u8UuSPmpbIGqXpXD6ydxIQ7p51f7v+dg2EMaNwcXBZzvLZIC6sZsgNt9TGkI/2jF22P7X
3XHqTC495EIVuDSowIVkakpnao5uqVJgnhwmziZyZyt/rrBXRa0rZFcOnv/GQlLJQBxZvb9mZbP5
tf9hh5536LpFXnyXsqo6oMDn2biwdRXdKKpc+AZwlhfoCWuzWoGf2c07znwPnyrszVe9quCbirKo
vhd255RWyjLPQG7ZVron0+jNGmqnh5/5384/kpP7u1WIjgCdq7lH5AVjyhnXTBuP7hf4y8e6fGT4
eyhtA6Of/EVP/6pyiikipN41SgrDXJiernEK9l3+P4gR0rLJWQx3QcXEZ3pdo7rIkKpFZMY/6wIT
YPurAqGlKEYR9O54h9NgOmdqUbne/ZzOzfNWAQMZeA+XE/eSLWclD3U6lip75LhN8IVPnfbz+Qb+
aSwAv1ym5mUttYXZ/J9VbKlKCuuJyNE2rlLPJUB4Rhwjwb5tkueu0k2mgw0cAIEy61lNgbntyZ4K
7fAGDpb47IqlqqUqljNBx9m0n9HBNNDpRQTn9a8bTBRALcLyPvXMszwblahQo8HR8gAhKknn+5LV
J2GTKzVFp53GsZ3h63MubwnOq7kurmEjzAJcmfh5gvH/rdGIsn219gZNn/dUNnrmRvRtUmr40eoz
W6diYzOaGHzwUtabGgPrLhQNzQWtmLfIPFBqBHb7trk2FwM38XE2DI6+gEd5wN9GL8mFXXrxoZXU
Wc4+iQjIytprwMm5XcV//J3hUv3GM6zgqPk1e0S9d4L5AVLvsHmTQpGamDGyHBdx93P2X2bi/hCb
HG26sxpiKP7z7koM7gz+2JNXjqjq1lhhlypdztsMpqeK1ymIkzZO9JXJC7W/7h7YHb3Ksdns+GH7
GJXScZDf8SCs/Yb8bUo5581o4fJaItcwdGvZwzqQr1HkvSQwOE/V2bSXXg7vPIv23HZnJibSrMq3
6OBL2OPnaNlFprgIXasrCuesOrJ11E735xQZOLN5YFzy4A0TamHGoTHSpquJ3Pjc1rZ4nJvQU50t
MwRrQYmRPmq7eJ7/zGMgSf2JAc1NTmnJ2NH2qQiY2G/+ofhv17AOk/83tBY6r9wvXz/bZ+2axFui
IsDeWFiB7tRZZ5qsfN7drLVulAFkjnXXLkoedilcAHMQT7pzwTq0KiGStj5cmppNG9rS0VujYXmN
lEH/V/gHtwYhWhCSYBMKzAKgG58riTszrT0hF+C+bmGoLY60ZdFiIIt2qjZX7VUKLSKFGVlmo/e7
pxl0SABnyZ4G2xvVYxvayd/Jnr7dlSi6G1mFJWmcprSoyY6GUhD9MBg5BZ48QaGqvloiUyocE2JH
W8lOE4cf865F0wA9loO4Li7mJEu37cUgGLD1zXqdnrIisNxaigGkJ9PE2ZWMwc6s//8TRLUzM/8T
DDdjcTTG7CZD8wodo3mo6tDjVgXnIPmSArDGUQ0IXLht0M0F5mEogtfGAh7r/lE0lMdjalB4gucG
24u079nF7zZJ3QMflbZ6uRAJTlFeN0BykbP+IcGJ3u6bB4ZNh6E9l6qkZaF1ngNAdeKwtd6aDjgr
Tz6/4fxOj7EUpwu9wfBmZXq8W3aQkozU4r3dXxojXy7RElKYCl9E2Z8JmVJVNqUbp3xBalSw4lGL
WgsBPKzmIFrHR5sp/17fU7A05HYGBqMGzHG6X4DaM7Dw43XBT8M86obHA9oKNEgxqasyXRHkpXRL
P9XBjm0ikBiForWr4wWjr1mMUgjedayKNnswP7RKl7yTMAHuCSp8QWBcv0O5QGxYKMUhmKAAdwKa
6rVQlLA0ycpShEMpHaq4JXeegN5Y0s5/wslzlWd7VWTZNW0UPNYR8jKWHmQ54ul6g3vpotXmQBWE
Fap8RpCzOImagAxXWiu6w51IwhnSh+KRZSfXFmMX7x7x7X8OfnN1lfpSJxusizh9oOg4zbweM+Ek
duOUV1RYYfK8h3ekSyeaIxD3w76zumHRuh93ll97u5irhJ96sQfakmvAaZZbFpoeqGymmof+L3Nh
E0CzucZv0N9ZAzV1dJMz4fpgM+GBsc2Bop+4ukGSyBDF9r7HQd1ykvQf2f7Rhqnb52SbCQKUbYC9
ChG67JsA2Xu8IXrC7NI+ml2UOgsY/+L93o+lJyNojiRh9WZVk5Rq/Zbtof4a3qrmpcIDLGm2fRCD
sXHoh2IQRyIoQtal0hHa7qpje3zVtzhjg4/E9a2Teq31RlsyTaADrvPicr7PAhuczJrrHcSlPL+m
s+0ONCsWcbpNbJJBp8K2i/ynSCqLwcXibJgGTJTN1Ofw3GmLQs9jqLYshfRR05IjYfZRXI63GVNJ
q+0yNYnWfe1JpPhNeJIrcUobcOFRcJwsY/2Y4vteRo+ftk5XyBwT2G5v3xh3mHppyk2w/Tjbr8jB
akTspfi0I8GAMWOQFMGAufEr6Xfq1eQ6XVAEfzjeTD4aklZP3IOqS/XQXu6rb+Qo505z993XUu4O
fjhwhkMgFkspkGXbl3XBQFOKxDz11wmtKRCvj4RE36XFrNK2SEx2y8hp/TzvOKatFsuSeyS+kGx6
q2dFahfNDViA+ClE5lhn2VfkKlkiIrEbvvPOoo1F3DjPnObGqwUkJIfeque0gnNwjXOCN6c5Pu76
pSCtZYzNjb2DQwQhy/Fb4PG8UdDr3xrB03Wsl63+kWschXevY0G9puStYSERw4ayYyFyarcBVY9n
lSuzhMesnDNfHkPTxXcNxt8Z3ryuTrYxETYp0jAsN/ODGLIS5Wr4Bha6QdUeEBHcZRsCdSrFoy01
AhpmWlDsIxVgQKOc+pxkff+rhX+ddDKAnk0Zoq2EuCGgjFFzVaX/LCwuaN6nng1665/yHH9I66pn
RSvM7MdXKNYIXko1COtivHFv7lJvLC18lCTSysSbPI6x8Ld1gFI3wZmKj0PlOgEYUxgDAAy3NdFy
mW2g8oKFJxg8U5ac75GdWE9ook3aUvJX4rb+1vz92HY9wU3SR/3XQGXTyDJeo9iRd9rAS8RY3j7K
zpZ2MNygMUZZhhE1vRjadSAayTRkt9LUgNW2ztdox9yPNL9VCa+2hfya5WvqjXQ2yo2nXZhnNWhI
tHMeSLtDUDfhRxHCgeJfUwlzkBdpaDseRke3BalxinWSTwYjVRirhuQZ+jfU5XZZzxIKz4Wo6OCK
b2MiSMmj1FAHb2R5xnNkKp49jC4X2iv+jSDIOFET8OlmIgXquFsC1AvMJ8403MilqE2owNB7bSAb
1vcPJtt5fc+DMdSTJjj4X2HJzJldgKXz2unLzw0dB/ct4J1pqwc+kBeJESyV//cBKE7aegy1qudR
FohVmw3UtvVMMRc1dcMdaPsA2EoMYgqrjANcyNCiPxYH/1XlYMLmezb65uSBjCYQAqYAawvIOvTe
d0JGkKvOzyJalO5GUjYYQCzTE3vq7j7+gQqEa4yiYx0y7LPzeAn1Z6FEJ0VDb9PY1Q+vTTcQDoTX
vrHPyv3lu+ZhQT1MISgZurCz6eTrIpb1ORRtNnxdIgP8SYFks6FwyzvYZVg7R0GZUpHvPx1x8NF0
VVOCHRSxtwiyjtOG3g2yE7pNq3EMayHqQK2CdtawZT0poUzFtHuHQ3NQZzYDLNTryGKCu10+8Pgb
rzUo6wgy0u4pFiOG3VEeyO9ScdnjPBL+unHGqjRfUlxVIt7hBxexcH9kbXrin2qoq8/eJmJYMqbV
Hc6+uMJohZNssS+N0St1R0Mi6DTZcL/NdEAYSvar8Eq60DcipsouoPtlLq5/yY47E2WxlJpT2uXu
mLOli9Dxcv228mpzKEKK99TDjYwIey/DxMrh9SoQN/s74NbV20Kb2JVe54c/8o2Ml+p5TeCUVQiL
cyzbOCx/bkbYdrTlZhOEj4joVuS2l578uov7UhtiETgHBh4YgxFajCEkgaGx5VvuKkFGYMANuMhk
/nUThEGVwMLI7Bjr8YVE8xqxScKFFF6lRecx2KbELvY2spkFKXKgrkPLkmTZr5rvV1Vp4oKHd+Fu
4t5dEhOQAPOBcmasZNM00Jt79JgAn/uf1ycPmmo2sr9ZpBboFL0hQHk5cYcSC9Q/u2dXUgoeY0Kh
+11b9+4qI5/11HubvsMDGxYLjYGejW5RQfqkkzObfRDuXx1ZRQTYnBFQ6usoiGoJ95xFzxxrg/ir
sO+4X8ytcfn9w7gyM3EucvUUmtvxGeXX+4AHPhmltsvrhC3VyCuY1u56rHUibpMDW7XaAPYshYey
mvD+GLSPyfSkEgRvpYLRA/ZQ3QZuFXpRGE5eBymeoE6zOT8LqELKswR+9/I7RNPXgcPLMsNLkOIX
qB5rLRkzkNzifPfQQYMdhSLlf4D21Ih3SGuLfDMg09BKFvTIWZ3ab+tk1hO7RKtdJVza4vcvL9M5
aFW9W12VmS803EpeRUOeZgBWwJYUWfh0FaJ2vbM6iNVTpv91rOV7eeVF9rKaMSbR7prJjudkhM7L
tQ+aj26ekOjnB676x+Y0p+wBnGX9hEBZ6I+PmY07Q0f8qLE7WgyG42d3OgnDO/4yhTn6Yvk+Fede
EmQl1j+I/LLz/UAuH0QEc/DW623hibsPBLilQDq7wX/hY8S7YU2JehCxtmg1z4vFuqES9fdoI7Kq
Y1TAnXtPuSllLOnHJgWdLPbYEHAh0+QGqN49ScF5xDzC8tuWZWaH50sC4bfKEQPlHLSAFfvdYQ4y
CINNpr5AdBgdtIfTMpsyUMHMjg85PRdWYAiUEpeOi7TgBJSkJRaIO2Q94sk6RviffjzEnQ+RnSLe
Owe+aD5kxhKLH5afl65TnQZfcvH+WKBNhUuQpYN5qdReeTQeq3FiIvl0CE4p5b44ONISt7NictEB
lesqhkuUTpY5ReJ6j4C0Kj7gp7lPWEuLKOA3B2I24tpPOukCrOi0KY9/RpLqWvrTz/x4Moon7+rr
nEtV6FUhd4uFQB05Wzc7w9CAAd6CGdpF00KVGnQxaMRjGvzMEnO2IVPTLz74FFT5tLEUMTauUlmj
jQf4juYyuomuXVRG/y1kv21ZJlDSfhm08LB9Lt/4gl/KcsfTU0zK81hHKc0MkXLvC5zeE7vdKzk/
+xrY1PNmAWYPHa+i/YaEYhRYE0VMOyKpWZHokj1OqVUo4gQa7TV8hDiMqZ0la8csryx1JVhx0u39
lHi+CR8WE8wDde1EK8q7d8p/fvfNSXN16Z0iF+UpayQYtUms03FTZHhrN85296sjdEXE6ZuuQPzY
nvH5yCkGgZBqJoOvP3caqk7i9apKm+0AE4IHCGLdausNBEqduZyMfartesvzzK4rq+7uiqPLLk1b
kT5qGp3+aAHiiWO7oJRMlgdVuFLYbCcDWOllpCoO+XUStIpyC6j2C6PHb4zylWiKQ29T6viOt5oF
D3CjWhcxuUBoNnX7RAJtD255kxVSf4L0viWZE9Mynu/TzHGKPvaezYVx8rCIUNfE7PzzCmUJwxxD
vx4zOLBTeSRgbNPvm4pE8XKCRzJdM6MxrY0mh0b1K3xJnhGGH5dH7Ap5t+iAEeNx9EOnTitWX7y4
r+iHQ+VtqsJOOCOlJ/UZCm2tAVcETx96e47S50XP0RMT8NVVm52sezIFdQ0GpC3gweLVJqWzOY7Y
UeCEwYJE3sHac9DSdHyLxRVhb4H/CUOkKCkW+0KwxrEJAH8QA+B5gmP0BSAIrmlMEbnBV7U+6JTC
gi+9E/S0ZNG5suy4R9vWZgUGMk9eMLKLM8nFTG1/uDxKY/wdsd17pS/+u+IXd1cgp2vi9q8BuAVp
57Uqzbt1jBhAmpnx/0+uRYbN+G9oGUxHhp8jM8UvzQ5kX5vN2R88yzm58ZP1zzjmXYBT9+cfDOqV
+NubtJ/cKHNc61c/9f2zQ1rh6uN6UaPBfhHxJjkBr5XJz/CdxsZi9QydvGZioxGEzCMfARd7wI4F
No/xHuRWtmhG9m9cFIF+0A2PQ3zrVVbdA3fv9n9nt3CPeDiYzFw9qJD84/RJfT0D//YFSEiMzmud
zcsIy8H7hWxTLa9mdh0trPGYzaZX5tdUFz3DdDPEvfwI1mQJfz018dRq1eIaQKKmeMbAxSuCeYdL
lmM5cUJXnEkV1OgxmR2PWgWjuzrDurco/c5BvLJXxEeCVp8MT8mtCKET3g9KHU5z3KZrGoLV3KlR
tzFCehmCjRP7/qmedIa6R61vrt9H90E+Q48vce0Q4XgSmLr2im1ufSqMrLpPP/dejI3sEB7gcwON
uDRT2Ln9X0yFfu0qBAg+rKMDNNgeiInXx4NdZSE5Yqg5sTir0QmS1Rl6lusf/HJFSjx3tQNa9AsI
sJH87wvEbikC9A9QjqLgSv0Bzi2ZQnDfEHM8a0REr9dcGOMlj8C4lnh/vP3jd7fkM6nWT7M/HKzt
dpb2p8VeYEdyocYD1cBy3pv5uvRkViY24TkY5liq/JmAtyAIS4RaPTz0bf19evqcXA6UyDg3ReeK
lhaWn2SeNeqt4otgWrhe85oK7qfjltki1mhkCi5ieKChwJIc7xWc0Cwhjqhszacz1SnFyojlcLqo
4lzuIi2DxoKXuueMZ9bVw4dlfUAbXMw6zfg7g+byAicCnCFuStBznaHSQrQpNSfFW4a40FwBS/I3
+OaUIl9GNGa/frBLjzJWHtkPktwW39e96lbA7+ojFZzaLjLUKvU7M84hYJPem+Tj3w2u1lLk2zVc
5LeQ3QbaWGE0fUKWSaqCLZiyeq8BVQNC4ChmmwhiJU5dFXvF+OGNeecAsSiX5m3+3VSUQUir/+UL
EhGLQc7uhBrtPlANV0oECqHZazsW/RqpOkoddUnd6hxblAGa+QghhJfedzTgTzkflSoUwJkQ0qtQ
QfcQap2AcfUwzzpGWC37cssT3RXms4eWC+BqY+LQnl3rxh7+47RdNGh3c4VdYDKovFuSeKYu5tCI
QOz/6AFOu0lXdIry8DKEZHahrocdkq4YdHSaicurqaW1Zawky87s3Rh/Gz4+NNE/Qii+yBrEk+G4
BLGHj4SX+Ae/lzGqeEplpNmDH0Mz1WBlwSn0IbwqZGBJ3AZhjXSgGK6XSadrloC15slCJdUc8Lmc
3tquRQpDW7w7HMv7BtA93+o46m/HLopQzZCQDtymDrq9DtogHQOIr933uk7hwkA4HxAJq6kpMhFY
r8K46LXLbtB/MfM5TITYP8f7yqt1v4iLwoqY7CcwkVEVoLjqb1D+0tVyhU1L/+mAxgEItELtXhIP
BMjkz4n0PmwqaWLyR16vufaXeBTZ1nvfX4YlaL+nNx3NpmaN5GLiXnIU2o7tAYSDzNtkV5gXgc2J
GlY5lOPw43iH82x2zDOsCgBGiZMXwR7XPA5yk7Mc5CmgXrd7+tXsea6our9orw7KkimoX1bS+8vS
61VEyUwrUDFaG9di6+/z+pYEuGZWnDhF217CEby3QPq/cTZiwBCgCRj8qR5fvuErMWmHPElD/BVB
c9+dogL77HHocVSqE6urXdY4ruVVH8V0I7B+G1KYmxOsySyc8AwFmWcAzhGYCo5fe7iHwq9F8Epw
zeWrEEa7hvDl6eilNRvERnJ0X1d4LEsyq/7Deg7hcL9VfAF+cYG7+tV1aOBJRPngAt7lw/wJeuhE
Rvxii/UyssQ+35HQ4Pnqr+H9pnTbsLP8jCYPeGmXGsYJzD+mxLJyF3DBWQ1XrgxOmF99NNvizLCR
0Y2CxgwGaduANantt60jYQorDZx+4JbCQE6yuy8hIJB7siI1WxTDPpJg1qbV2epgeXMXNyOkzotH
iXqaHpupSqScDQyjtbJYVuys6rvzhbvbvJpiuAYRcxgQsnr1VnG/5kDF6CkX0DOweWd+RsqG9g1u
pNIkVhYvCiB88YkcTPo2l9tkMZRPKyWQ4bgHV+8uVijq1kBz5L5dgc3uRp9gDpC+XZCTdpE79nWx
EEzszvFFj1z6pc4KWzdiLXw0lfEm5AKOhhpwGnTSMf0F13BFWFdWaqx4Jl1gXTny+mO6t2vIYLFP
dPezQUc48hvSGu70A0b7k92tUR8cKkDi3ix5dfaF+kNrH5e/+tZ9ucSbXfID8pu9B6nHY94IWlHG
TuoEESddcDQ8UeMI2doG1f3sUYvRDQhlw4ATWb5jHzGF/2VkOo2FBh6LeDiMN9BQO9nZ4wkeWXEa
BzKjb48bbmXSrfOrOLNY1SGy6bJPRAOXq799/JuI3TWdblnVTpsdLj2xZu+ALQNUHPEtQmCnf7iV
FLIZt7SKlVRl2ut7a2+j+lDi2GXBXgWbvnPFmlcfz4zYysC0Uyq3DMTIKtBEVk51fSUjd2CDlJ+i
s5GrJAEuxFnpwJEgrnH+EMrmKoOP2qwxrtkbaYCijEKgfbnbD11Br/CNF1eLd9DPLepz1mZmSWpy
fQb8e+yUy+PGkL4/j9JOyaKmzB93CFg6tn6EEr0Zfrnd1EZ27nVCcHF1NFEmDpJHeripQEseYI+4
OGkN5cs4ldbMBWInr0JZrYCGf7gQoqkLxsXef+dEJaqX1H9/WTo4Mph8MusECeEcpk+EUQF14aUF
uJrnFdQ4KlyVxz96U62wulMq98JH98/xxifGYGvRgpBQyPJl8U9sT2wEP3kXSustKr2k3ie8asi0
LAI1Pl65vX8KLAlSuAhljxodOdY9/nFoVnc9/irLeuv5sxqFC4/KinqRZoV7PjDl4KwqJ1/t6q/X
YJv93xPSfqq+cjd0JjvY6MrL5PS0E7mugh4Ym4mm4W3g9UZU0FwrswcLyfI19lUA2z8TpA5+ttEP
eFBDuCN0W+Jrv4BNofPQKTMzEFnpExk40LZXtW55jK60lLn75OHCT7pyk+ybbElktUUuVVNtQpwM
+h5CLA6e8zsQxzfjQn5jrXl1do1aHcRzmqaXTPv7zSRpXFITNZHB63ZhOZJJ+AH/5Ta0SijNsEJy
ifwtZgQuEhoKA1nHUlTnFcAqiCxNmxQuIjdtFlwrxnj287ehyR5MY3LPQzKGXwAaAJedHQteMWQv
X0tV3hS/zzFoA6C63cHLC1l2eliJ8zJAFR6/5kEWT3nqzNkTvnXwp+e737psdU9nehVsHg7WAB4e
KDWJQp+eYbY42d+9tDjSvx+nRCVbGMrRIJjbC47R5LaVG0zcASP2ZlebA23CtM3u/Q+LsUH/bp/f
4PQ4rUjY9TamK3cQxmPLumo4FAnzkuK9Uq7sYxTEhoRFP1L+w0ib9M/fcHb7jxTiSQJzzgVo7Sl6
L83NIezjWyGvDEfDaZu01G7bTT0rah4DwqhkPaYynrXOZWXLQfCgEroWQzJtSWE2A/CEq/SY+RXy
qDnO1IYzyReaDt8l3o4meWm5uNpQeoROCCJEGv02qEhWvcN7IvsWgdsy/UVPUE6dgZXc2yLVpC4M
Qy6YVXQNKPRZjIN4a9T93jjvrVddfqG8v3UZhREii++WIk7eISCAHa5F1U+uv4NydHCosTBMl7GA
QNKqcfBhb8K0hgR317uP89aBwxrNRCtQcVmGl3MPHGGWgjb3/utuhcVU4fng905gsh8Mo7xQOxJ5
S0VsVZXk6tIvc8X4pZMEwZ7PoGLwYSDAZAyqRkv0dlS0tv+9vGyzIPf0TsHJme5SljxOLkwYMf6N
60U4XOwJdb6GTUZ2u66NsDiSbm+T7vJFAMh4E/RSlB+wsNugTw91Zk6NQdQlzrBk5v5rAkck
`protect end_protected
|
-------------------------------------------------------------------------------
--
-- File: tb_TestDataPathCalib.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This test bench instantiates the DataPath and ADC_Calibration modules of the
-- ZmodScopeController. A ramp signal is used to simulate the ADC data
-- and a data checker compares the output of the DataPath module against the
-- expected data (generated by CalibDataReference) and generates an error
-- message if a mismatch occurs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.PkgZmodADC.all;
entity tb_TestDataPathCalib is
Generic (
-- ADC number of bits
kADC_Width : integer range 10 to 16 := 14;
-- Sampling Clock Period in ps;
kSamplingPeriod : real range 8.0 to 100.0:= 10.0;
-- kSimTestMode generic allows the test bench to instantiate the
-- ADC_Calibration modules to be instantiated either in test mode
-- or in normal operation.
kSimTestMode : std_logic := '0';
-- ADC dynamic/static calibration
kExtCalibEn : boolean := false;
-- Channel1 low gain multiplicative (gain) compensation coefficient parameter
kCh1LgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010110010";
-- Channel1 low gain additive (offset) compensation coefficient parameter
kCh1LgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111010101";
-- Channel1 high gain multiplicative (gain) compensation coefficient parameter
kCh1HgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010110010";
-- Channel1 high gain additive (offset) compensation coefficient parameter
kCh1HgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111010101";
-- Channel2 low gain multiplicative (gain) compensation coefficient parameter
kCh2LgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010110010";
-- Channel2 low gain additive (offset) compensation coefficient parameter
kCh2LgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111010101";
-- Channel2 high gain multiplicative (gain) compensation coefficient parameter
kCh2HgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- Channel2 high gain additive (offset) compensation coefficient parameter
kCh2HgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111010101"
);
end tb_TestDataPathCalib;
architecture Behavioral of tb_TestDataPathCalib is
constant kNumClockCycles : integer := 3*(2**14);
signal ADC_SamplingClk : std_logic := '0';
signal acRst_n : std_logic := '0';
signal ZmodDcoClk, ZmodDcoClkDly : std_logic := '0';
signal dZmodADC_Data, dZmodADC_DataDly : std_logic_vector(kADC_Width-1 downto 0) := (others => '0');
signal ZmodDataSel : std_logic_vector (2 downto 0);
signal dZmodADC_DataCnt : unsigned (kADC_Width-1 downto 0);
signal cDataValid, cDataCalibValid : std_logic;
signal cChannelA, cChannelB : std_logic_vector(kADC_Width-1 downto 0);
signal cChannel1_Test, cChannel2_Test : std_logic_vector(kADC_Width-1 downto 0);
signal cChA_TestDly, cChB_TestDly : std_logic_vector(kADC_Width-1 downto 0);
signal cDataOverflow : std_logic;
signal cTestMode : std_logic;
signal cCh1Calib, cCh2Calib : std_logic_vector(15 downto 0);
signal cCh1OutInt, cCh2OutInt : integer;
signal cCh1TestInt, cCh2TestInt : integer;
signal cCh1Diff, cCh2Diff : integer;
signal cExtCh1LgMultCoef : std_logic_vector(17 downto 0);
signal cExtCh1LgAddCoef : std_logic_vector(17 downto 0);
signal cExtCh1HgMultCoef : std_logic_vector(17 downto 0);
signal cExtCh1HgAddCoef : std_logic_vector(17 downto 0);
signal cExtCh2LgMultCoef : std_logic_vector(17 downto 0);
signal cExtCh2LgAddCoef : std_logic_vector(17 downto 0);
signal cExtCh2HgMultCoef : std_logic_vector(17 downto 0);
signal cExtCh2HgAddCoef : std_logic_vector(17 downto 0);
signal cCh1GainState : std_logic;
signal cCh2GainState : std_logic;
signal cInitDone, dInitDone : std_logic := '0';
signal dDataGenCntEn, dDataGenRst_n : std_logic;
signal dEnableAcquisition : std_logic;
constant kADC_SamplingClkPeriod : time := 10ns;
constant kVal1 : std_logic_vector (15 downto 0) := x"AAAA";
constant kVal2 : std_logic_vector (15 downto 0) := x"5555";
constant kValMin : std_logic_vector (15 downto 0) := x"8000";
constant kValMax : std_logic_vector (15 downto 0) := x"7FFF";
-- Calibration constants used to test the dynamic calibration behavior
constant kCh1LgMultCoefDynamic : std_logic_vector (17 downto 0) := "010000110101100101";
constant kCh1LgAddCoefDynamic : std_logic_vector (17 downto 0) := "111111101111011011";
constant kCh1HgMultCoefDynamic : std_logic_vector (17 downto 0) := "010001101000010001";
constant kCh1HgAddCoefDynamic : std_logic_vector (17 downto 0) := "111111101110111000";
constant kCh2LgMultCoefDynamic : std_logic_vector (17 downto 0) := "010000101001111010";
constant kCh2LgAddCoefDynamic : std_logic_vector (17 downto 0) := "000000000000010000";
constant kCh2HgMultCoefDynamic : std_logic_vector (17 downto 0) := "010001011010101111";
constant kCh2HgAddCoefDynamic : std_logic_vector (17 downto 0) := "000000001000000111";
begin
InstDataPath : entity work.DataPath
Generic Map(
kSamplingPeriod => kSamplingPeriod,
kADC_Width => kADC_Width
)
Port Map(
ADC_SamplingClk => ADC_SamplingClk,
acRst_n => acRst_n,
DcoClkIn => ZmodDcoClk,
DcoClkOut => open,
dEnableAcquisition => dEnableAcquisition,
dADC_Data => dZmodADC_DataDly,
cChannelA => cChannelA,
cChannelB => cChannelB,
cDataOutValid => cDataValid,
cFIFO_RdEn => '1',
dFIFO_WrRstBusy => open,
dDataOverflow => cDataOverflow,
cInitDone => cInitDone,
dInitDone => dInitDone
);
InstDataPathDlyCh1 : entity work.DataPathLatency
Generic Map (
kNumFIFO_Stages => 2,
kDataWidth => kADC_Width
)
Port Map(
ADC_SamplingClk => ADC_SamplingClk,
ZmodDcoClk => ZmodDcoClkDly,
dDataIn => dZmodADC_DataDly,
cChA_DataOut => cChA_TestDly,
cChB_DataOut => cChB_TestDly);
InstCalibDataRefCh1 : entity work.CalibDataReference
Generic Map (
kWidth => kADC_Width,
kExtCalibEn => kExtCalibEn,
kLgMultCoefStatic => kCh1LgMultCoefStatic,
kLgAddCoefStatic => kCh1LgAddCoefStatic,
kHgMultCoefStatic => kCh1HgMultCoefStatic,
kHgAddCoefStatic => kCh1HgAddCoefStatic,
kInvert => true,
kLatency => 2,
kTestLatency => 1
)
Port Map(
SamplingClk => ADC_SamplingClk,
cTestMode => cTestMode,
cChIn => cChannelA,
cChOut => cChannel1_Test,
cExtLgMultCoef => cExtCh1LgMultCoef,
cExtLgAddCoef => cExtCh1LgAddCoef,
cExtHgMultCoef => cExtCh1HgMultCoef,
cExtHgAddCoef => cExtCh1HgAddCoef,
cGainState => cCh1GainState);
InstCalibDataRefCh2 : entity work.CalibDataReference
Generic Map (
kWidth => kADC_Width,
kExtCalibEn => kExtCalibEn,
kLgMultCoefStatic => kCh2LgMultCoefStatic,
kLgAddCoefStatic => kCh2LgAddCoefStatic,
kHgMultCoefStatic => kCh2HgMultCoefStatic,
kHgAddCoefStatic => kCh2HgAddCoefStatic,
kInvert => false,
kLatency => 2,
kTestLatency => 1
)
Port Map(
SamplingClk => ADC_SamplingClk,
cTestMode => cTestMode,
cChIn => cChannelB,
cChOut => cChannel2_Test,
cExtLgMultCoef => cExtCh2LgMultCoef,
cExtLgAddCoef => cExtCh2LgAddCoef,
cExtHgMultCoef => cExtCh2HgMultCoef,
cExtHgAddCoef => cExtCh2HgAddCoef,
cGainState => cCh2GainState);
InstCh1ADC_Calibration : entity work.GainOffsetCalib
Generic Map(
kWidth => kADC_Width,
kExtCalibEn => kExtCalibEn,
kInvert => true,
kLgMultCoefStatic => kCh1LgMultCoefStatic,
kLgAddCoefStatic => kCh1LgAddCoefStatic,
kHgMultCoefStatic => kCh1HgMultCoefStatic,
kHgAddCoefStatic => kCh1HgAddCoefStatic
)
Port Map
(
SamplingClk => ADC_SamplingClk,
acRst_n => acRst_n,
cTestMode => cTestMode,
cExtLgMultCoef => cExtCh1LgMultCoef,
cExtLgAddCoef => cExtCh1LgAddCoef,
cExtHgMultCoef => cExtCh1HgMultCoef,
cExtHgAddCoef => cExtCh1HgAddCoef,
cGainState => cCh1GainState,
cDataRaw => cChannelA,
cDataInValid => cDataValid,
cCalibDataOut => cCh1Calib,
cDataCalibValid => cDataCalibValid
);
InstCh2ADC_Calibration : entity work.GainOffsetCalib
Generic Map(
kWidth => kADC_Width,
kExtCalibEn => kExtCalibEn,
kInvert => false,
kLgMultCoefStatic => kCh2LgMultCoefStatic,
kLgAddCoefStatic => kCh2LgAddCoefStatic,
kHgMultCoefStatic => kCh2HgMultCoefStatic,
kHgAddCoefStatic => kCh2HgAddCoefStatic
)
Port Map
(
SamplingClk => ADC_SamplingClk,
acRst_n => acRst_n,
cTestMode => cTestMode,
cExtLgMultCoef => cExtCh2LgMultCoef,
cExtLgAddCoef => cExtCh2LgAddCoef,
cExtHgMultCoef => cExtCh2HgMultCoef,
cExtHgAddCoef => cExtCh2HgAddCoef,
cGainState => cCh2GainState,
cDataRaw => cChannelB,
cDataInValid => '0',
cCalibDataOut => cCh2Calib,
cDataCalibValid => open --both channels share the same valid signal
);
cCh1OutInt <= to_integer(signed(cCh1Calib(15 downto 16-kADC_Width)));
cCh2OutInt <= to_integer(signed(cCh2Calib(15 downto 16-kADC_Width)));
cCh1TestInt <= to_integer(signed(cChannel1_Test));
cCh2TestInt <= to_integer(signed(cChannel2_Test));
cCh1Diff <= cCh1OutInt - cCh1TestInt;
cCh2Diff <= cCh2OutInt - cCh2TestInt;
-- Generate ADC Sampling Clock
Clock: process
begin
for i in 0 to kNumClockCycles loop
wait for kADC_SamplingClkPeriod/2;
ADC_SamplingClk <= not ADC_SamplingClk;
wait for kADC_SamplingClkPeriod/2;
ADC_SamplingClk <= not ADC_SamplingClk;
end loop;
wait;
end process;
-- Generate ZmodDcoClk.
DcoClkProc: process
begin
wait for kTdcoMax;
for i in 0 to kNumClockCycles/2 loop
wait for kADC_SamplingClkPeriod/2;
ZmodDcoClk <= not ZmodDcoClk;
wait for kADC_SamplingClkPeriod/2;
ZmodDcoClk <= not ZmodDcoClk;
end loop;
-- Simulate DcoClk loss for 100 samples.
-- 100 is a random choice, it has no particular meaning.
wait for kADC_SamplingClkPeriod * 100;
for i in 0 to (kNumClockCycles/2 - 100) loop
wait for kADC_SamplingClkPeriod/2;
ZmodDcoClk <= not ZmodDcoClk;
wait for kADC_SamplingClkPeriod/2;
ZmodDcoClk <= not ZmodDcoClk;
end loop;
wait;
end process;
ZmodDcoClkDly <= ZmodDcoClk after
(IDDR_ClockPhase(kSamplingPeriod)/360.0)*kADC_SamplingClkPeriod;
-- Ramp signal generator
ProcDataGen: process (ZmodDcoClk)
begin
if ((acRst_n = '0') or (dDataGenRst_n = '0')) then
dZmodADC_DataCnt <= (others => '0');
elsif (falling_edge(ZmodDcoClk) or rising_edge(ZmodDcoClk)) then
if (dDataGenCntEn = '1') then
dZmodADC_DataCnt <= dZmodADC_DataCnt + 1;
end if;
end if;
end process;
-- Mux that allows selecting (simulating )different patters
-- on the ADC data interface.
ProcZmodDataMux: process (dZmodADC_DataCnt, ZmodDataSel)
begin
case (ZmodDataSel) is
when ("000") =>
dZmodADC_Data <= kVal1(kADC_Width-1 downto 0);
when ("001") =>
dZmodADC_Data <= kVal2(kADC_Width-1 downto 0);
when ("010") =>
dZmodADC_Data <= std_logic_vector(dZmodADC_DataCnt);
when ("011") =>
dZmodADC_Data <= kValMin(15 downto 16-kADC_Width);
when ("100") =>
dZmodADC_Data <= kValMax(15 downto 16-kADC_Width);
when others =>
dZmodADC_Data <= std_logic_vector(dZmodADC_DataCnt);
end case;
end process;
-- Delay the simulated ADC data (dZmodADC_Data) by kADC_SamplingClkPeriod/4
-- so that the waveforms are easier to follow in simulation.
dZmodADC_DataDly <= dZmodADC_Data after (kADC_SamplingClkPeriod/4);
ProcSamplingDomainStimuli: process
begin
acRst_n <= '0';
cTestMode <= kSimTestMode;
cCh1GainState <= '1';
cCh2GainState <= '1';
cInitDone <= '0';
cExtCh1LgMultCoef <= kCh1LgMultCoefDynamic;
cExtCh1LgAddCoef <= kCh1LgAddCoefDynamic;
cExtCh1HgMultCoef <= kCh1HgMultCoefDynamic;
cExtCh1HgAddCoef <= kCh1HgAddCoefDynamic;
cExtCh2LgMultCoef <= kCh2LgMultCoefDynamic;
cExtCh2LgAddCoef <= kCh2LgAddCoefDynamic;
cExtCh2HgMultCoef <= kCh2HgMultCoefDynamic;
cExtCh2HgAddCoef <= kCh2HgAddCoefDynamic;
dEnableAcquisition <= '0';
-- Keep the acRst_n reset asserted for 10 clock cycles.
wait for 10 * kADC_SamplingClkPeriod;
-- Modify signals on the falling edge of ADC_SamplingClk.
wait until falling_edge(ADC_SamplingClk);
acRst_n <= '1';
cInitDone <= '1';
-- Wait for 100 clock cycles before enabling actual sample acquisition from the ADC
-- (this number has no specific relevance).
wait for 100 * kADC_SamplingClkPeriod;
dEnableAcquisition <= '1';
-- Optionally the cInitDone signal can be disabled to observe the system behavior.
-- No sort of automatic testing is carried out for this optional test.
-- The effect of ADC or relay initialization on the valid signal is tested
-- at the top level test bench (tb_TestTop) level.
wait until dInitDone = '0';
wait until falling_edge(ADC_SamplingClk);
cInitDone <= '0';
-- Keep dInitDone low for 500 clock cycles (this number has no specific relevance).
wait for (500) * kADC_SamplingClkPeriod;
cInitDone <= '1';
wait;
end process;
ProcDcoDomainStimuli: process
begin
dInitDone <= '0';
dDataGenRst_n <= '0';
dDataGenCntEn <= '0';
ZmodDataSel <= "000";
-- Keep the acRst_n reset asserted for 10 clock cycles.
wait for 10 * kADC_SamplingClkPeriod;
-- Modify signals on the falling edge of ZmodDcoClk.
wait until falling_edge(ZmodDcoClk);
dInitDone <= '1';
dDataGenRst_n <= '1';
dDataGenCntEn <= '1';
ZmodDataSel <= "000";
-- A counter will be used to generate the input test data for the DataPath module.
-- However, since a 1LSB error is tolerated so that the CalibDataReference can work
-- with real (floating point) values, synchronization problems may not be detected.
-- For this reason, at the beginning of the test 2 values that differ by more than
-- 1 LSB will be generated. By this means, the test assures that the DataPath and
-- ADC_Calibration outputs are correctly synchronized with CalibDataReference.
-- To make sure that the synchronization FIFO comes out of reset when the various
-- patterns are applied to the input, the process will wait for the data valid
-- signal to be asserted.
wait until cDataValid = '1';
wait until rising_edge(ZmodDcoClk);
ZmodDataSel <= "000";
wait until rising_edge(ZmodDcoClk);
ZmodDataSel <= "001";
wait until rising_edge(ZmodDcoClk);
-- Test IP response for minimum negative and maximum positive input
-- The value will be hold for 100 clock cycles (no specific relevance
-- for the time this value is held constant).
ZmodDataSel <= "011";
wait for kADC_SamplingClkPeriod*100;
wait until rising_edge(ZmodDcoClk);
ZmodDataSel <= "100";
wait for kADC_SamplingClkPeriod*100;
wait until rising_edge(ZmodDcoClk);
ZmodDataSel <= "010";
-- Optionally the dInitDone signal can be disabled to observe the system behavior.
-- No sort of automatic testing is carried out for this optional test.
-- The effect of ADC or relay initialization on the valid signal is tested
-- at the top level test bench (tb_TestTop) level.
-- Modify signals on the falling edge of ZmodDcoClk.
wait until falling_edge(ZmodDcoClk);
dInitDone <= '0';
-- Keep dInitDone low for 500 clock cycles (this number has no specific relevance).
wait for (500) * kADC_SamplingClkPeriod;
dInitDone <= '1';
wait;
end process;
-- Check the calibration module (ADC_Calbration) outputs against the expected values.
ProcCh1CheckCalibData: process
begin
wait until cCh1TestInt'event or cCh1OutInt'event;
-- cCh1Diff is generated on the rising edge of ADC_SamplingClk
-- and checked on the negative edge of ADC_SamplingClk.
wait until falling_edge(ADC_SamplingClk);
if (cDataCalibValid = '1') then
assert (abs(cCh1Diff) < 2)
report "Calibration error: mismatch between expected data and actual data" & LF & HT & HT &
"Expected: " & integer'image(to_integer(signed(cChannel1_Test))) & LF & HT & HT &
"Actual: " & integer'image(cCh1OutInt) & LF & HT & HT &
"Difference: " & integer'image(cCh1Diff)
severity ERROR;
end if;
end process;
ProcCh2CheckCalibData: process
begin
wait until cCh2TestInt'event or cCh2OutInt'event;
-- cCh2Diff is generated on the rising edge of ADC_SamplingClk
-- and checked on the negative edge of ADC_SamplingClk.
wait until falling_edge(ADC_SamplingClk);
if (cDataCalibValid = '1') then
assert (abs(cCh2Diff) < 2)
report "Calibration error: mismatch between expected data and actual data" & LF & HT & HT &
"Expected: " & integer'image(to_integer(signed(cChannel2_Test))) & LF & HT & HT &
"Actual: " & integer'image(cCh2OutInt) & LF & HT & HT &
"Difference: " & integer'image(cCh2Diff)
severity ERROR;
end if;
end process;
-- Test DataPathLatency module. The data generated by the DataPath module
-- is expected to be identical to the data generated by the DataPathLatency
-- module. This test is used to validate the DataPathLatency used in the top
-- level test bench.
ProcDataPathDlyTest: process
begin
wait until cChannelA'event or cChannelB'event or cChB_TestDly'event or cChA_TestDly'event;
if (cDataValid = '1') then
wait until falling_edge(ADC_SamplingClk);
assert ((cChannelA = cChA_TestDly) and (cChannelB = cChB_TestDly))
report "DataPathLatency synchronization error" & LF & HT & HT
severity ERROR;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1945.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s02b01x00p01n02i01945pkg is
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 4; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Logic types for subelements
--
SUBTYPE st_scl1 IS BIT;
SUBTYPE st_scl2 IS BOOLEAN;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Unconstrained arrays
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
-- ----------------------------------------------------------------------------------------------
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
end;
use work.c07s02b01x00p01n02i01945pkg.all;
ENTITY c07s02b01x00p01n02i01945ent IS
END c07s02b01x00p01n02i01945ent;
ARCHITECTURE c07s02b01x00p01n02i01945arch OF c07s02b01x00p01n02i01945ent IS
--
-- CONSTANT Declarations
--
CONSTANT ARGA_C_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
CONSTANT AND_C_csa1_1 : t_csa1_1 := ( '1', '0', '0', '0' );
CONSTANT AND_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
CONSTANT ARGA_C_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT AND_C_csa1_2 : t_csa1_2 := ( TRUE, FALSE, FALSE, FALSE );
CONSTANT AND_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, FALSE, FALSE );
CONSTANT ARGA_C_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
CONSTANT AND_C_csa1_3 : t_csa1_3 := ( '1', '0', '0', '0' );
CONSTANT AND_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
CONSTANT ARGA_C_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT AND_C_csa1_4 : t_csa1_4 := ( TRUE, FALSE, FALSE, FALSE );
CONSTANT AND_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, FALSE, FALSE );
--
-- SIGNAL Declarations
--
SIGNAL ARGA_S_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
SIGNAL AND_S_csa1_1 : t_csa1_1 := ( '1', '0', '0', '0' );
SIGNAL AND_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
SIGNAL ARGA_S_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL AND_S_csa1_2 : t_csa1_2 := ( TRUE, FALSE, FALSE, FALSE );
SIGNAL AND_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, FALSE, FALSE );
SIGNAL ARGA_S_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
SIGNAL AND_S_csa1_3 : t_csa1_3 := ( '1', '0', '0', '0' );
SIGNAL AND_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
SIGNAL ARGA_S_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL AND_S_csa1_4 : t_csa1_4 := ( TRUE, FALSE, FALSE, FALSE );
SIGNAL AND_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, FALSE, FALSE );
BEGIN
TESTING: PROCESS
--
-- VARIABLE Declarations
--
VARIABLE ARGA_V_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
VARIABLE AND_V_csa1_1 : t_csa1_1 := ( '1', '0', '0', '0' );
VARIABLE AND_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
VARIABLE ARGA_V_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE AND_V_csa1_2 : t_csa1_2 := ( TRUE, FALSE, FALSE, FALSE );
VARIABLE AND_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, FALSE, FALSE );
VARIABLE ARGA_V_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
VARIABLE AND_V_csa1_3 : t_csa1_3 := ( '1', '0', '0', '0' );
VARIABLE AND_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
VARIABLE ARGA_V_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE AND_V_csa1_4 : t_csa1_4 := ( TRUE, FALSE, FALSE, FALSE );
VARIABLE AND_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, FALSE, FALSE );
BEGIN
--
-- Test AND operator on: CONSTANTs
--
ASSERT ( ARGA_C_csa1_1 AND ARGB_C_csa1_1 ) = AND_C_csa1_1
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_2 AND ARGB_C_csa1_2 ) = AND_C_csa1_2
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_3 AND ARGB_C_csa1_3 ) = AND_C_csa1_3
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_4 AND ARGB_C_csa1_4 ) = AND_C_csa1_4
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_1 AND ARGB_C_usa1_1 ) = AND_C_usa1_1
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_2 AND ARGB_C_usa1_2 ) = AND_C_usa1_2
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_3 AND ARGB_C_usa1_3 ) = AND_C_usa1_3
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_4 AND ARGB_C_usa1_4 ) = AND_C_usa1_4
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_4"
SEVERITY FAILURE;
--
-- Test AND operator on: SIGNALs
--
ASSERT ( ARGA_S_csa1_1 AND ARGB_S_csa1_1 ) = AND_S_csa1_1
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_2 AND ARGB_S_csa1_2 ) = AND_S_csa1_2
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_3 AND ARGB_S_csa1_3 ) = AND_S_csa1_3
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_4 AND ARGB_S_csa1_4 ) = AND_S_csa1_4
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_1 AND ARGB_S_usa1_1 ) = AND_S_usa1_1
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_2 AND ARGB_S_usa1_2 ) = AND_S_usa1_2
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_3 AND ARGB_S_usa1_3 ) = AND_S_usa1_3
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_4 AND ARGB_S_usa1_4 ) = AND_S_usa1_4
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_4"
SEVERITY FAILURE;
--
-- Test AND operator on: VARIABLEs
--
ASSERT ( ARGA_V_csa1_1 AND ARGB_V_csa1_1 ) = AND_V_csa1_1
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_2 AND ARGB_V_csa1_2 ) = AND_V_csa1_2
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_3 AND ARGB_V_csa1_3 ) = AND_V_csa1_3
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_4 AND ARGB_V_csa1_4 ) = AND_V_csa1_4
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_1 AND ARGB_V_usa1_1 ) = AND_V_usa1_1
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_2 AND ARGB_V_usa1_2 ) = AND_V_usa1_2
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_3 AND ARGB_V_usa1_3 ) = AND_V_usa1_3
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_4 AND ARGB_V_usa1_4 ) = AND_V_usa1_4
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_4"
SEVERITY FAILURE;
wait for 5 ns;
assert NOT( ( ARGA_C_csa1_1 AND ARGB_C_csa1_1 ) = AND_C_csa1_1 and
( ARGA_C_csa1_2 AND ARGB_C_csa1_2 ) = AND_C_csa1_2 and
( ARGA_C_csa1_3 AND ARGB_C_csa1_3 ) = AND_C_csa1_3 and
( ARGA_C_csa1_4 AND ARGB_C_csa1_4 ) = AND_C_csa1_4 and
( ARGA_C_usa1_1 AND ARGB_C_usa1_1 ) = AND_C_usa1_1 and
( ARGA_C_usa1_2 AND ARGB_C_usa1_2 ) = AND_C_usa1_2 and
( ARGA_C_usa1_3 AND ARGB_C_usa1_3 ) = AND_C_usa1_3 and
( ARGA_C_usa1_4 AND ARGB_C_usa1_4 ) = AND_C_usa1_4 and
( ARGA_S_csa1_1 AND ARGB_S_csa1_1 ) = AND_S_csa1_1 and
( ARGA_S_csa1_2 AND ARGB_S_csa1_2 ) = AND_S_csa1_2 and
( ARGA_S_csa1_3 AND ARGB_S_csa1_3 ) = AND_S_csa1_3 and
( ARGA_S_csa1_4 AND ARGB_S_csa1_4 ) = AND_S_csa1_4 and
( ARGA_S_usa1_1 AND ARGB_S_usa1_1 ) = AND_S_usa1_1 and
( ARGA_S_usa1_2 AND ARGB_S_usa1_2 ) = AND_S_usa1_2 and
( ARGA_S_usa1_3 AND ARGB_S_usa1_3 ) = AND_S_usa1_3 and
( ARGA_S_usa1_4 AND ARGB_S_usa1_4 ) = AND_S_usa1_4 and
( ARGA_V_csa1_1 AND ARGB_V_csa1_1 ) = AND_V_csa1_1 and
( ARGA_V_csa1_2 AND ARGB_V_csa1_2 ) = AND_V_csa1_2 and
( ARGA_V_csa1_3 AND ARGB_V_csa1_3 ) = AND_V_csa1_3 and
( ARGA_V_csa1_4 AND ARGB_V_csa1_4 ) = AND_V_csa1_4 and
( ARGA_V_usa1_1 AND ARGB_V_usa1_1 ) = AND_V_usa1_1 and
( ARGA_V_usa1_2 AND ARGB_V_usa1_2 ) = AND_V_usa1_2 and
( ARGA_V_usa1_3 AND ARGB_V_usa1_3 ) = AND_V_usa1_3 and
( ARGA_V_usa1_4 AND ARGB_V_usa1_4 ) = AND_V_usa1_4 )
report "***PASSED TEST: c07s02b01x00p01n02i01945"
severity NOTE;
assert ( ( ARGA_C_csa1_1 AND ARGB_C_csa1_1 ) = AND_C_csa1_1 and
( ARGA_C_csa1_2 AND ARGB_C_csa1_2 ) = AND_C_csa1_2 and
( ARGA_C_csa1_3 AND ARGB_C_csa1_3 ) = AND_C_csa1_3 and
( ARGA_C_csa1_4 AND ARGB_C_csa1_4 ) = AND_C_csa1_4 and
( ARGA_C_usa1_1 AND ARGB_C_usa1_1 ) = AND_C_usa1_1 and
( ARGA_C_usa1_2 AND ARGB_C_usa1_2 ) = AND_C_usa1_2 and
( ARGA_C_usa1_3 AND ARGB_C_usa1_3 ) = AND_C_usa1_3 and
( ARGA_C_usa1_4 AND ARGB_C_usa1_4 ) = AND_C_usa1_4 and
( ARGA_S_csa1_1 AND ARGB_S_csa1_1 ) = AND_S_csa1_1 and
( ARGA_S_csa1_2 AND ARGB_S_csa1_2 ) = AND_S_csa1_2 and
( ARGA_S_csa1_3 AND ARGB_S_csa1_3 ) = AND_S_csa1_3 and
( ARGA_S_csa1_4 AND ARGB_S_csa1_4 ) = AND_S_csa1_4 and
( ARGA_S_usa1_1 AND ARGB_S_usa1_1 ) = AND_S_usa1_1 and
( ARGA_S_usa1_2 AND ARGB_S_usa1_2 ) = AND_S_usa1_2 and
( ARGA_S_usa1_3 AND ARGB_S_usa1_3 ) = AND_S_usa1_3 and
( ARGA_S_usa1_4 AND ARGB_S_usa1_4 ) = AND_S_usa1_4 and
( ARGA_V_csa1_1 AND ARGB_V_csa1_1 ) = AND_V_csa1_1 and
( ARGA_V_csa1_2 AND ARGB_V_csa1_2 ) = AND_V_csa1_2 and
( ARGA_V_csa1_3 AND ARGB_V_csa1_3 ) = AND_V_csa1_3 and
( ARGA_V_csa1_4 AND ARGB_V_csa1_4 ) = AND_V_csa1_4 and
( ARGA_V_usa1_1 AND ARGB_V_usa1_1 ) = AND_V_usa1_1 and
( ARGA_V_usa1_2 AND ARGB_V_usa1_2 ) = AND_V_usa1_2 and
( ARGA_V_usa1_3 AND ARGB_V_usa1_3 ) = AND_V_usa1_3 and
( ARGA_V_usa1_4 AND ARGB_V_usa1_4 ) = AND_V_usa1_4 )
report "***FAILED TEST: c07s02b01x00p01n02i01945 - Logical operator AND for any user-defined one-dimensional array type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01945arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1945.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s02b01x00p01n02i01945pkg is
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 4; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Logic types for subelements
--
SUBTYPE st_scl1 IS BIT;
SUBTYPE st_scl2 IS BOOLEAN;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Unconstrained arrays
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
-- ----------------------------------------------------------------------------------------------
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
end;
use work.c07s02b01x00p01n02i01945pkg.all;
ENTITY c07s02b01x00p01n02i01945ent IS
END c07s02b01x00p01n02i01945ent;
ARCHITECTURE c07s02b01x00p01n02i01945arch OF c07s02b01x00p01n02i01945ent IS
--
-- CONSTANT Declarations
--
CONSTANT ARGA_C_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
CONSTANT AND_C_csa1_1 : t_csa1_1 := ( '1', '0', '0', '0' );
CONSTANT AND_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
CONSTANT ARGA_C_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT AND_C_csa1_2 : t_csa1_2 := ( TRUE, FALSE, FALSE, FALSE );
CONSTANT AND_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, FALSE, FALSE );
CONSTANT ARGA_C_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
CONSTANT AND_C_csa1_3 : t_csa1_3 := ( '1', '0', '0', '0' );
CONSTANT AND_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
CONSTANT ARGA_C_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT AND_C_csa1_4 : t_csa1_4 := ( TRUE, FALSE, FALSE, FALSE );
CONSTANT AND_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, FALSE, FALSE );
--
-- SIGNAL Declarations
--
SIGNAL ARGA_S_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
SIGNAL AND_S_csa1_1 : t_csa1_1 := ( '1', '0', '0', '0' );
SIGNAL AND_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
SIGNAL ARGA_S_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL AND_S_csa1_2 : t_csa1_2 := ( TRUE, FALSE, FALSE, FALSE );
SIGNAL AND_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, FALSE, FALSE );
SIGNAL ARGA_S_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
SIGNAL AND_S_csa1_3 : t_csa1_3 := ( '1', '0', '0', '0' );
SIGNAL AND_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
SIGNAL ARGA_S_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL AND_S_csa1_4 : t_csa1_4 := ( TRUE, FALSE, FALSE, FALSE );
SIGNAL AND_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, FALSE, FALSE );
BEGIN
TESTING: PROCESS
--
-- VARIABLE Declarations
--
VARIABLE ARGA_V_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
VARIABLE AND_V_csa1_1 : t_csa1_1 := ( '1', '0', '0', '0' );
VARIABLE AND_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
VARIABLE ARGA_V_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE AND_V_csa1_2 : t_csa1_2 := ( TRUE, FALSE, FALSE, FALSE );
VARIABLE AND_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, FALSE, FALSE );
VARIABLE ARGA_V_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
VARIABLE AND_V_csa1_3 : t_csa1_3 := ( '1', '0', '0', '0' );
VARIABLE AND_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
VARIABLE ARGA_V_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE AND_V_csa1_4 : t_csa1_4 := ( TRUE, FALSE, FALSE, FALSE );
VARIABLE AND_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, FALSE, FALSE );
BEGIN
--
-- Test AND operator on: CONSTANTs
--
ASSERT ( ARGA_C_csa1_1 AND ARGB_C_csa1_1 ) = AND_C_csa1_1
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_2 AND ARGB_C_csa1_2 ) = AND_C_csa1_2
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_3 AND ARGB_C_csa1_3 ) = AND_C_csa1_3
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_4 AND ARGB_C_csa1_4 ) = AND_C_csa1_4
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_1 AND ARGB_C_usa1_1 ) = AND_C_usa1_1
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_2 AND ARGB_C_usa1_2 ) = AND_C_usa1_2
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_3 AND ARGB_C_usa1_3 ) = AND_C_usa1_3
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_4 AND ARGB_C_usa1_4 ) = AND_C_usa1_4
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_4"
SEVERITY FAILURE;
--
-- Test AND operator on: SIGNALs
--
ASSERT ( ARGA_S_csa1_1 AND ARGB_S_csa1_1 ) = AND_S_csa1_1
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_2 AND ARGB_S_csa1_2 ) = AND_S_csa1_2
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_3 AND ARGB_S_csa1_3 ) = AND_S_csa1_3
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_4 AND ARGB_S_csa1_4 ) = AND_S_csa1_4
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_1 AND ARGB_S_usa1_1 ) = AND_S_usa1_1
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_2 AND ARGB_S_usa1_2 ) = AND_S_usa1_2
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_3 AND ARGB_S_usa1_3 ) = AND_S_usa1_3
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_4 AND ARGB_S_usa1_4 ) = AND_S_usa1_4
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_4"
SEVERITY FAILURE;
--
-- Test AND operator on: VARIABLEs
--
ASSERT ( ARGA_V_csa1_1 AND ARGB_V_csa1_1 ) = AND_V_csa1_1
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_2 AND ARGB_V_csa1_2 ) = AND_V_csa1_2
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_3 AND ARGB_V_csa1_3 ) = AND_V_csa1_3
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_4 AND ARGB_V_csa1_4 ) = AND_V_csa1_4
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_1 AND ARGB_V_usa1_1 ) = AND_V_usa1_1
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_2 AND ARGB_V_usa1_2 ) = AND_V_usa1_2
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_3 AND ARGB_V_usa1_3 ) = AND_V_usa1_3
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_4 AND ARGB_V_usa1_4 ) = AND_V_usa1_4
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_4"
SEVERITY FAILURE;
wait for 5 ns;
assert NOT( ( ARGA_C_csa1_1 AND ARGB_C_csa1_1 ) = AND_C_csa1_1 and
( ARGA_C_csa1_2 AND ARGB_C_csa1_2 ) = AND_C_csa1_2 and
( ARGA_C_csa1_3 AND ARGB_C_csa1_3 ) = AND_C_csa1_3 and
( ARGA_C_csa1_4 AND ARGB_C_csa1_4 ) = AND_C_csa1_4 and
( ARGA_C_usa1_1 AND ARGB_C_usa1_1 ) = AND_C_usa1_1 and
( ARGA_C_usa1_2 AND ARGB_C_usa1_2 ) = AND_C_usa1_2 and
( ARGA_C_usa1_3 AND ARGB_C_usa1_3 ) = AND_C_usa1_3 and
( ARGA_C_usa1_4 AND ARGB_C_usa1_4 ) = AND_C_usa1_4 and
( ARGA_S_csa1_1 AND ARGB_S_csa1_1 ) = AND_S_csa1_1 and
( ARGA_S_csa1_2 AND ARGB_S_csa1_2 ) = AND_S_csa1_2 and
( ARGA_S_csa1_3 AND ARGB_S_csa1_3 ) = AND_S_csa1_3 and
( ARGA_S_csa1_4 AND ARGB_S_csa1_4 ) = AND_S_csa1_4 and
( ARGA_S_usa1_1 AND ARGB_S_usa1_1 ) = AND_S_usa1_1 and
( ARGA_S_usa1_2 AND ARGB_S_usa1_2 ) = AND_S_usa1_2 and
( ARGA_S_usa1_3 AND ARGB_S_usa1_3 ) = AND_S_usa1_3 and
( ARGA_S_usa1_4 AND ARGB_S_usa1_4 ) = AND_S_usa1_4 and
( ARGA_V_csa1_1 AND ARGB_V_csa1_1 ) = AND_V_csa1_1 and
( ARGA_V_csa1_2 AND ARGB_V_csa1_2 ) = AND_V_csa1_2 and
( ARGA_V_csa1_3 AND ARGB_V_csa1_3 ) = AND_V_csa1_3 and
( ARGA_V_csa1_4 AND ARGB_V_csa1_4 ) = AND_V_csa1_4 and
( ARGA_V_usa1_1 AND ARGB_V_usa1_1 ) = AND_V_usa1_1 and
( ARGA_V_usa1_2 AND ARGB_V_usa1_2 ) = AND_V_usa1_2 and
( ARGA_V_usa1_3 AND ARGB_V_usa1_3 ) = AND_V_usa1_3 and
( ARGA_V_usa1_4 AND ARGB_V_usa1_4 ) = AND_V_usa1_4 )
report "***PASSED TEST: c07s02b01x00p01n02i01945"
severity NOTE;
assert ( ( ARGA_C_csa1_1 AND ARGB_C_csa1_1 ) = AND_C_csa1_1 and
( ARGA_C_csa1_2 AND ARGB_C_csa1_2 ) = AND_C_csa1_2 and
( ARGA_C_csa1_3 AND ARGB_C_csa1_3 ) = AND_C_csa1_3 and
( ARGA_C_csa1_4 AND ARGB_C_csa1_4 ) = AND_C_csa1_4 and
( ARGA_C_usa1_1 AND ARGB_C_usa1_1 ) = AND_C_usa1_1 and
( ARGA_C_usa1_2 AND ARGB_C_usa1_2 ) = AND_C_usa1_2 and
( ARGA_C_usa1_3 AND ARGB_C_usa1_3 ) = AND_C_usa1_3 and
( ARGA_C_usa1_4 AND ARGB_C_usa1_4 ) = AND_C_usa1_4 and
( ARGA_S_csa1_1 AND ARGB_S_csa1_1 ) = AND_S_csa1_1 and
( ARGA_S_csa1_2 AND ARGB_S_csa1_2 ) = AND_S_csa1_2 and
( ARGA_S_csa1_3 AND ARGB_S_csa1_3 ) = AND_S_csa1_3 and
( ARGA_S_csa1_4 AND ARGB_S_csa1_4 ) = AND_S_csa1_4 and
( ARGA_S_usa1_1 AND ARGB_S_usa1_1 ) = AND_S_usa1_1 and
( ARGA_S_usa1_2 AND ARGB_S_usa1_2 ) = AND_S_usa1_2 and
( ARGA_S_usa1_3 AND ARGB_S_usa1_3 ) = AND_S_usa1_3 and
( ARGA_S_usa1_4 AND ARGB_S_usa1_4 ) = AND_S_usa1_4 and
( ARGA_V_csa1_1 AND ARGB_V_csa1_1 ) = AND_V_csa1_1 and
( ARGA_V_csa1_2 AND ARGB_V_csa1_2 ) = AND_V_csa1_2 and
( ARGA_V_csa1_3 AND ARGB_V_csa1_3 ) = AND_V_csa1_3 and
( ARGA_V_csa1_4 AND ARGB_V_csa1_4 ) = AND_V_csa1_4 and
( ARGA_V_usa1_1 AND ARGB_V_usa1_1 ) = AND_V_usa1_1 and
( ARGA_V_usa1_2 AND ARGB_V_usa1_2 ) = AND_V_usa1_2 and
( ARGA_V_usa1_3 AND ARGB_V_usa1_3 ) = AND_V_usa1_3 and
( ARGA_V_usa1_4 AND ARGB_V_usa1_4 ) = AND_V_usa1_4 )
report "***FAILED TEST: c07s02b01x00p01n02i01945 - Logical operator AND for any user-defined one-dimensional array type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01945arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1945.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s02b01x00p01n02i01945pkg is
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 4; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Logic types for subelements
--
SUBTYPE st_scl1 IS BIT;
SUBTYPE st_scl2 IS BOOLEAN;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Unconstrained arrays
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
-- ----------------------------------------------------------------------------------------------
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
end;
use work.c07s02b01x00p01n02i01945pkg.all;
ENTITY c07s02b01x00p01n02i01945ent IS
END c07s02b01x00p01n02i01945ent;
ARCHITECTURE c07s02b01x00p01n02i01945arch OF c07s02b01x00p01n02i01945ent IS
--
-- CONSTANT Declarations
--
CONSTANT ARGA_C_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
CONSTANT AND_C_csa1_1 : t_csa1_1 := ( '1', '0', '0', '0' );
CONSTANT AND_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
CONSTANT ARGA_C_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT AND_C_csa1_2 : t_csa1_2 := ( TRUE, FALSE, FALSE, FALSE );
CONSTANT AND_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, FALSE, FALSE );
CONSTANT ARGA_C_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
CONSTANT AND_C_csa1_3 : t_csa1_3 := ( '1', '0', '0', '0' );
CONSTANT AND_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
CONSTANT ARGA_C_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT AND_C_csa1_4 : t_csa1_4 := ( TRUE, FALSE, FALSE, FALSE );
CONSTANT AND_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, FALSE, FALSE );
--
-- SIGNAL Declarations
--
SIGNAL ARGA_S_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
SIGNAL AND_S_csa1_1 : t_csa1_1 := ( '1', '0', '0', '0' );
SIGNAL AND_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
SIGNAL ARGA_S_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL AND_S_csa1_2 : t_csa1_2 := ( TRUE, FALSE, FALSE, FALSE );
SIGNAL AND_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, FALSE, FALSE );
SIGNAL ARGA_S_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
SIGNAL AND_S_csa1_3 : t_csa1_3 := ( '1', '0', '0', '0' );
SIGNAL AND_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
SIGNAL ARGA_S_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL AND_S_csa1_4 : t_csa1_4 := ( TRUE, FALSE, FALSE, FALSE );
SIGNAL AND_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, FALSE, FALSE );
BEGIN
TESTING: PROCESS
--
-- VARIABLE Declarations
--
VARIABLE ARGA_V_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
VARIABLE AND_V_csa1_1 : t_csa1_1 := ( '1', '0', '0', '0' );
VARIABLE AND_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
VARIABLE ARGA_V_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE AND_V_csa1_2 : t_csa1_2 := ( TRUE, FALSE, FALSE, FALSE );
VARIABLE AND_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, FALSE, FALSE );
VARIABLE ARGA_V_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
VARIABLE AND_V_csa1_3 : t_csa1_3 := ( '1', '0', '0', '0' );
VARIABLE AND_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
VARIABLE ARGA_V_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE AND_V_csa1_4 : t_csa1_4 := ( TRUE, FALSE, FALSE, FALSE );
VARIABLE AND_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, FALSE, FALSE );
BEGIN
--
-- Test AND operator on: CONSTANTs
--
ASSERT ( ARGA_C_csa1_1 AND ARGB_C_csa1_1 ) = AND_C_csa1_1
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_2 AND ARGB_C_csa1_2 ) = AND_C_csa1_2
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_3 AND ARGB_C_csa1_3 ) = AND_C_csa1_3
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_4 AND ARGB_C_csa1_4 ) = AND_C_csa1_4
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_1 AND ARGB_C_usa1_1 ) = AND_C_usa1_1
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_2 AND ARGB_C_usa1_2 ) = AND_C_usa1_2
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_3 AND ARGB_C_usa1_3 ) = AND_C_usa1_3
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_4 AND ARGB_C_usa1_4 ) = AND_C_usa1_4
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_4"
SEVERITY FAILURE;
--
-- Test AND operator on: SIGNALs
--
ASSERT ( ARGA_S_csa1_1 AND ARGB_S_csa1_1 ) = AND_S_csa1_1
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_2 AND ARGB_S_csa1_2 ) = AND_S_csa1_2
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_3 AND ARGB_S_csa1_3 ) = AND_S_csa1_3
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_4 AND ARGB_S_csa1_4 ) = AND_S_csa1_4
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_1 AND ARGB_S_usa1_1 ) = AND_S_usa1_1
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_2 AND ARGB_S_usa1_2 ) = AND_S_usa1_2
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_3 AND ARGB_S_usa1_3 ) = AND_S_usa1_3
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_4 AND ARGB_S_usa1_4 ) = AND_S_usa1_4
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_4"
SEVERITY FAILURE;
--
-- Test AND operator on: VARIABLEs
--
ASSERT ( ARGA_V_csa1_1 AND ARGB_V_csa1_1 ) = AND_V_csa1_1
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_2 AND ARGB_V_csa1_2 ) = AND_V_csa1_2
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_3 AND ARGB_V_csa1_3 ) = AND_V_csa1_3
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_4 AND ARGB_V_csa1_4 ) = AND_V_csa1_4
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_1 AND ARGB_V_usa1_1 ) = AND_V_usa1_1
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_2 AND ARGB_V_usa1_2 ) = AND_V_usa1_2
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_3 AND ARGB_V_usa1_3 ) = AND_V_usa1_3
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_4 AND ARGB_V_usa1_4 ) = AND_V_usa1_4
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_4"
SEVERITY FAILURE;
wait for 5 ns;
assert NOT( ( ARGA_C_csa1_1 AND ARGB_C_csa1_1 ) = AND_C_csa1_1 and
( ARGA_C_csa1_2 AND ARGB_C_csa1_2 ) = AND_C_csa1_2 and
( ARGA_C_csa1_3 AND ARGB_C_csa1_3 ) = AND_C_csa1_3 and
( ARGA_C_csa1_4 AND ARGB_C_csa1_4 ) = AND_C_csa1_4 and
( ARGA_C_usa1_1 AND ARGB_C_usa1_1 ) = AND_C_usa1_1 and
( ARGA_C_usa1_2 AND ARGB_C_usa1_2 ) = AND_C_usa1_2 and
( ARGA_C_usa1_3 AND ARGB_C_usa1_3 ) = AND_C_usa1_3 and
( ARGA_C_usa1_4 AND ARGB_C_usa1_4 ) = AND_C_usa1_4 and
( ARGA_S_csa1_1 AND ARGB_S_csa1_1 ) = AND_S_csa1_1 and
( ARGA_S_csa1_2 AND ARGB_S_csa1_2 ) = AND_S_csa1_2 and
( ARGA_S_csa1_3 AND ARGB_S_csa1_3 ) = AND_S_csa1_3 and
( ARGA_S_csa1_4 AND ARGB_S_csa1_4 ) = AND_S_csa1_4 and
( ARGA_S_usa1_1 AND ARGB_S_usa1_1 ) = AND_S_usa1_1 and
( ARGA_S_usa1_2 AND ARGB_S_usa1_2 ) = AND_S_usa1_2 and
( ARGA_S_usa1_3 AND ARGB_S_usa1_3 ) = AND_S_usa1_3 and
( ARGA_S_usa1_4 AND ARGB_S_usa1_4 ) = AND_S_usa1_4 and
( ARGA_V_csa1_1 AND ARGB_V_csa1_1 ) = AND_V_csa1_1 and
( ARGA_V_csa1_2 AND ARGB_V_csa1_2 ) = AND_V_csa1_2 and
( ARGA_V_csa1_3 AND ARGB_V_csa1_3 ) = AND_V_csa1_3 and
( ARGA_V_csa1_4 AND ARGB_V_csa1_4 ) = AND_V_csa1_4 and
( ARGA_V_usa1_1 AND ARGB_V_usa1_1 ) = AND_V_usa1_1 and
( ARGA_V_usa1_2 AND ARGB_V_usa1_2 ) = AND_V_usa1_2 and
( ARGA_V_usa1_3 AND ARGB_V_usa1_3 ) = AND_V_usa1_3 and
( ARGA_V_usa1_4 AND ARGB_V_usa1_4 ) = AND_V_usa1_4 )
report "***PASSED TEST: c07s02b01x00p01n02i01945"
severity NOTE;
assert ( ( ARGA_C_csa1_1 AND ARGB_C_csa1_1 ) = AND_C_csa1_1 and
( ARGA_C_csa1_2 AND ARGB_C_csa1_2 ) = AND_C_csa1_2 and
( ARGA_C_csa1_3 AND ARGB_C_csa1_3 ) = AND_C_csa1_3 and
( ARGA_C_csa1_4 AND ARGB_C_csa1_4 ) = AND_C_csa1_4 and
( ARGA_C_usa1_1 AND ARGB_C_usa1_1 ) = AND_C_usa1_1 and
( ARGA_C_usa1_2 AND ARGB_C_usa1_2 ) = AND_C_usa1_2 and
( ARGA_C_usa1_3 AND ARGB_C_usa1_3 ) = AND_C_usa1_3 and
( ARGA_C_usa1_4 AND ARGB_C_usa1_4 ) = AND_C_usa1_4 and
( ARGA_S_csa1_1 AND ARGB_S_csa1_1 ) = AND_S_csa1_1 and
( ARGA_S_csa1_2 AND ARGB_S_csa1_2 ) = AND_S_csa1_2 and
( ARGA_S_csa1_3 AND ARGB_S_csa1_3 ) = AND_S_csa1_3 and
( ARGA_S_csa1_4 AND ARGB_S_csa1_4 ) = AND_S_csa1_4 and
( ARGA_S_usa1_1 AND ARGB_S_usa1_1 ) = AND_S_usa1_1 and
( ARGA_S_usa1_2 AND ARGB_S_usa1_2 ) = AND_S_usa1_2 and
( ARGA_S_usa1_3 AND ARGB_S_usa1_3 ) = AND_S_usa1_3 and
( ARGA_S_usa1_4 AND ARGB_S_usa1_4 ) = AND_S_usa1_4 and
( ARGA_V_csa1_1 AND ARGB_V_csa1_1 ) = AND_V_csa1_1 and
( ARGA_V_csa1_2 AND ARGB_V_csa1_2 ) = AND_V_csa1_2 and
( ARGA_V_csa1_3 AND ARGB_V_csa1_3 ) = AND_V_csa1_3 and
( ARGA_V_csa1_4 AND ARGB_V_csa1_4 ) = AND_V_csa1_4 and
( ARGA_V_usa1_1 AND ARGB_V_usa1_1 ) = AND_V_usa1_1 and
( ARGA_V_usa1_2 AND ARGB_V_usa1_2 ) = AND_V_usa1_2 and
( ARGA_V_usa1_3 AND ARGB_V_usa1_3 ) = AND_V_usa1_3 and
( ARGA_V_usa1_4 AND ARGB_V_usa1_4 ) = AND_V_usa1_4 )
report "***FAILED TEST: c07s02b01x00p01n02i01945 - Logical operator AND for any user-defined one-dimensional array type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01945arch;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROME.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (even part)
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use WORK.MDCT_PKG.all;
entity ROME is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROME;
architecture RTL of ROME is
type ROM_TYPE is array (0 to (2**ROMADDR_W)-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP+AP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(BM, ROMDATA_W) ),
std_logic_vector( to_signed(CM, ROMDATA_W) ),
std_logic_vector( to_signed(CM+BM, ROMDATA_W) ),
std_logic_vector( to_signed(CP, ROMDATA_W) ),
std_logic_vector( to_signed(CP+BM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(BM, ROMDATA_W) ),
std_logic_vector( to_signed(BP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(BP+CM, ROMDATA_W) ),
std_logic_vector( to_signed(CM, ROMDATA_W) ),
std_logic_vector( to_signed(BP+CP, ROMDATA_W) ),
std_logic_vector( to_signed(CP, ROMDATA_W) ),
std_logic_vector( to_signed(BP, ROMDATA_W) ),
(others => '0'),
(others => '0'),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(AM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(AM+AM, ROMDATA_W) ),
std_logic_vector( to_signed(AM, ROMDATA_W) ),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AM, ROMDATA_W) ),
(others => '0'),
(others => '0'),
std_logic_vector( to_signed(CM, ROMDATA_W) ),
std_logic_vector( to_signed(BP, ROMDATA_W) ),
std_logic_vector( to_signed(BP+CM, ROMDATA_W) ),
std_logic_vector( to_signed(BM, ROMDATA_W) ),
std_logic_vector( to_signed(BM+CM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(CM, ROMDATA_W) ),
std_logic_vector( to_signed(CP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(CP+BP, ROMDATA_W) ),
std_logic_vector( to_signed(BP, ROMDATA_W) ),
std_logic_vector( to_signed(CP+BM, ROMDATA_W) ),
std_logic_vector( to_signed(BM, ROMDATA_W) ),
std_logic_vector( to_signed(CP, ROMDATA_W) ),
(others => '0')
);
begin
process(clk)
begin
if rising_edge(clk) then
datao <= rom(to_integer(unsigned(addr)) );
end if;
end process;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROME.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (even part)
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use WORK.MDCT_PKG.all;
entity ROME is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROME;
architecture RTL of ROME is
type ROM_TYPE is array (0 to (2**ROMADDR_W)-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP+AP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(BM, ROMDATA_W) ),
std_logic_vector( to_signed(CM, ROMDATA_W) ),
std_logic_vector( to_signed(CM+BM, ROMDATA_W) ),
std_logic_vector( to_signed(CP, ROMDATA_W) ),
std_logic_vector( to_signed(CP+BM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(BM, ROMDATA_W) ),
std_logic_vector( to_signed(BP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(BP+CM, ROMDATA_W) ),
std_logic_vector( to_signed(CM, ROMDATA_W) ),
std_logic_vector( to_signed(BP+CP, ROMDATA_W) ),
std_logic_vector( to_signed(CP, ROMDATA_W) ),
std_logic_vector( to_signed(BP, ROMDATA_W) ),
(others => '0'),
(others => '0'),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(AM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(AM+AM, ROMDATA_W) ),
std_logic_vector( to_signed(AM, ROMDATA_W) ),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AM, ROMDATA_W) ),
(others => '0'),
(others => '0'),
std_logic_vector( to_signed(CM, ROMDATA_W) ),
std_logic_vector( to_signed(BP, ROMDATA_W) ),
std_logic_vector( to_signed(BP+CM, ROMDATA_W) ),
std_logic_vector( to_signed(BM, ROMDATA_W) ),
std_logic_vector( to_signed(BM+CM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(CM, ROMDATA_W) ),
std_logic_vector( to_signed(CP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(CP+BP, ROMDATA_W) ),
std_logic_vector( to_signed(BP, ROMDATA_W) ),
std_logic_vector( to_signed(CP+BM, ROMDATA_W) ),
std_logic_vector( to_signed(BM, ROMDATA_W) ),
std_logic_vector( to_signed(CP, ROMDATA_W) ),
(others => '0')
);
begin
process(clk)
begin
if rising_edge(clk) then
datao <= rom(to_integer(unsigned(addr)) );
end if;
end process;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROME.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (even part)
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use WORK.MDCT_PKG.all;
entity ROME is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROME;
architecture RTL of ROME is
type ROM_TYPE is array (0 to (2**ROMADDR_W)-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP+AP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(BM, ROMDATA_W) ),
std_logic_vector( to_signed(CM, ROMDATA_W) ),
std_logic_vector( to_signed(CM+BM, ROMDATA_W) ),
std_logic_vector( to_signed(CP, ROMDATA_W) ),
std_logic_vector( to_signed(CP+BM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(BM, ROMDATA_W) ),
std_logic_vector( to_signed(BP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(BP+CM, ROMDATA_W) ),
std_logic_vector( to_signed(CM, ROMDATA_W) ),
std_logic_vector( to_signed(BP+CP, ROMDATA_W) ),
std_logic_vector( to_signed(CP, ROMDATA_W) ),
std_logic_vector( to_signed(BP, ROMDATA_W) ),
(others => '0'),
(others => '0'),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(AM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(AM+AM, ROMDATA_W) ),
std_logic_vector( to_signed(AM, ROMDATA_W) ),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AM, ROMDATA_W) ),
(others => '0'),
(others => '0'),
std_logic_vector( to_signed(CM, ROMDATA_W) ),
std_logic_vector( to_signed(BP, ROMDATA_W) ),
std_logic_vector( to_signed(BP+CM, ROMDATA_W) ),
std_logic_vector( to_signed(BM, ROMDATA_W) ),
std_logic_vector( to_signed(BM+CM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(CM, ROMDATA_W) ),
std_logic_vector( to_signed(CP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(CP+BP, ROMDATA_W) ),
std_logic_vector( to_signed(BP, ROMDATA_W) ),
std_logic_vector( to_signed(CP+BM, ROMDATA_W) ),
std_logic_vector( to_signed(BM, ROMDATA_W) ),
std_logic_vector( to_signed(CP, ROMDATA_W) ),
(others => '0')
);
begin
process(clk)
begin
if rising_edge(clk) then
datao <= rom(to_integer(unsigned(addr)) );
end if;
end process;
end RTL;
|
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
--
-- In this HDL repository, there are many different and unique modules, consisting
-- of various HDL (Verilog or VHDL) components. The individual modules are
-- developed independently, and may be accompanied by separate and unique license
-- terms.
--
-- The user should read each of these license terms, and understand the
-- freedoms and responsibilities that he or she has by using this source/core.
--
-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-- A PARTICULAR PURPOSE.
--
-- Redistribution and use of source or resulting binaries, with or without modification
-- of this file, are permitted under one of the following two license terms:
--
-- 1. The GNU General Public License version 2 as published by the
-- Free Software Foundation, which can be found in the top level directory
-- of this repository (LICENSE_GPL2), and also online at:
-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
--
-- OR
--
-- 2. An ADI specific BSD license, which can be found in the top level directory
-- of this repository (LICENSE_ADIBSD), and also on-line at:
-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
-- This will allow to generate bit files and not release the source code,
-- as long as it attaches to an ADI device.
--
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dma_fifo;
entity axi_streaming_dma_tx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
-- Write port
s_axis_aclk : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
s_axis_tlast : in std_logic;
s_axis_tvalid : in std_logic;
-- Read port
out_stb : out std_logic;
out_ack : in std_logic;
out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0)
);
end;
architecture imp of axi_streaming_dma_tx_fifo is
signal in_ack : std_logic;
signal drain_dma : Boolean;
begin
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => s_axis_tvalid,
in_ack => in_ack,
in_data => s_axis_tdata,
out_stb => out_stb,
out_ack => out_ack,
out_data => out_data
);
drain_process: process (s_axis_aclk) is
variable enable_d1 : Boolean;
begin
if rising_edge(s_axis_aclk) then
if resetn = '0' then
drain_dma <= False;
else
if s_axis_tlast = '1' then
drain_dma <= False;
elsif not enable_d1 and enable then
drain_dma <= False;
elsif enable_d1 and not enable then
drain_dma <= True;
end if;
enable_d1 := enable;
end if;
end if;
end process;
s_axis_tready <= '1' when in_ack = '1' or drain_dma else '0';
end;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_sg_wr_status_cntl;
architecture implementation of axi_sg_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
-- coverage off
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
-- coverage on
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_sg_v4_1_3.axi_sg_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_3.axi_sg_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_3.axi_sg_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY SHERPA_tb IS
END SHERPA_tb;
ARCHITECTURE behavior OF SHERPA_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top_level
PORT(
fx2Clk_in : IN std_logic;
fx2Addr_out : OUT std_logic_vector(1 downto 0);
fx2Data_io : INOUT std_logic_vector(7 downto 0);
fx2Read_out : OUT std_logic;
fx2OE_out : OUT std_logic;
fx2GotData_in : IN std_logic;
fx2Write_out : OUT std_logic;
fx2GotRoom_in : IN std_logic;
fx2PktEnd_out : OUT std_logic;
sseg_out : OUT std_logic_vector(7 downto 0);
anode_out : OUT std_logic_vector(3 downto 0);
led_out : OUT std_logic_vector(7 downto 0);
sw_in : IN std_logic_vector(7 downto 0);
ADC_I : IN std_logic_vector(7 downto 0);
ADC_Q : IN std_logic_vector(7 downto 0);
CLOCK : IN std_logic_vector(7 downto 0);
clk : IN std_logic;
CONFIG_SDA : INOUT std_logic;
CONFIG_SCL : INOUT std_logic;
CONFIG_DIN : OUT std_logic;
CONFIG_SCLK : OUT std_logic;
CONFIG_CS : OUT std_logic;
CONFIG_SHDN : OUT std_logic;
CONFIG_RXTX : OUT std_logic;
CONFIG_CW : OUT std_logic
);
END COMPONENT;
--Inputs
signal fx2Clk_in : std_logic := '0';
signal fx2GotData_in : std_logic := '0';
signal fx2GotRoom_in : std_logic := '0';
signal sw_in : std_logic_vector(7 downto 0) := (others => '0');
signal ADC_I : std_logic_vector(7 downto 0) := (others => '0');
signal ADC_Q : std_logic_vector(7 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal CLOCK : std_logic_vector(7 downto 0) := (others => '0');
--BiDirs
signal fx2Data_io : std_logic_vector(7 downto 0);
signal CONFIG_SDA : std_logic;
signal CONFIG_SCL : std_logic;
--Outputs
signal fx2Addr_out : std_logic_vector(1 downto 0);
signal fx2Read_out : std_logic;
signal fx2OE_out : std_logic;
signal fx2Write_out : std_logic;
signal fx2PktEnd_out : std_logic;
signal sseg_out : std_logic_vector(7 downto 0);
signal anode_out : std_logic_vector(3 downto 0);
signal led_out : std_logic_vector(7 downto 0);
signal CONFIG_DIN : std_logic;
signal CONFIG_SCLK : std_logic;
signal CONFIG_CS : std_logic;
signal CONFIG_SHDN : std_logic;
signal CONFIG_RXTX : std_logic;
signal CONFIG_CW : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
constant fx2Clk_period : time := 20.8333333333333 ns;
constant clk0_period : time := 305.185 ns;
constant clk1_period : time := 25 ns;
constant clk2_period : time := 305.194 ns;
constant clk3_period : time := 400000 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top_level PORT MAP (
fx2Clk_in => fx2Clk_in,
fx2Addr_out => fx2Addr_out,
fx2Data_io => fx2Data_io,
fx2Read_out => fx2Read_out,
fx2OE_out => fx2OE_out,
fx2GotData_in => fx2GotData_in,
fx2Write_out => fx2Write_out,
fx2GotRoom_in => fx2GotRoom_in,
fx2PktEnd_out => fx2PktEnd_out,
sseg_out => sseg_out,
anode_out => anode_out,
led_out => led_out,
sw_in => sw_in,
ADC_I => ADC_I,
ADC_Q => ADC_Q,
clk => clk,
CLOCK => CLOCK,
CONFIG_SDA => CONFIG_SDA,
CONFIG_SCL => CONFIG_SCL,
CONFIG_DIN => CONFIG_DIN,
CONFIG_SCLK => CONFIG_SCLK,
CONFIG_CS => CONFIG_CS,
CONFIG_SHDN => CONFIG_SHDN,
CONFIG_RXTX => CONFIG_RXTX,
CONFIG_CW => CONFIG_CW
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
fx2Clk_process :process
begin
fx2Clk_in <= '0';
wait for fx2Clk_period/2;
fx2Clk_in <= '1';
wait for fx2Clk_period/2;
end process;
clk0_process :process
begin
CLOCK(0) <= '1';
wait for clk0_period/2;
CLOCK(0) <= '0';
wait for clk0_period/2;
end process;
clk1_process :process
begin
CLOCK(1) <= '1';
wait for clk1_period/2;
CLOCK(1) <= '0';
wait for clk1_period/2;
end process;
clk2_process :process
begin
CLOCK(2) <= '1';
wait for clk2_period/2;
CLOCK(2) <= '0';
wait for clk2_period/2;
end process;
clk3_process :process
begin
CLOCK(3) <= '1';
wait for clk3_period/2;
CLOCK(3) <= '0';
wait for clk3_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- $Id: genlib.vhd 466 2012-12-30 13:26:55Z mueller $
--
-- Copyright 2007-2012 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: genlib
-- Description: some general purpose components
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 13.3; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-12-29 466 1.0.9 add led_pulse_stretch
-- 2011-11-09 421 1.0.8 add cdc_pulse
-- 2010-04-17 277 1.0.7 timer: no default for START,DONE,BUSY; drop STOP
-- 2010-04-02 273 1.0.6 add timer
-- 2008-01-20 112 1.0.5 rename clkgen->clkdivce
-- 2007-12-26 106 1.0.4 added gray_cnt_(4|5|n|gen) and gray2bin_gen
-- 2007-12-25 105 1.0.3 RESET:='0' defaults
-- 2007-06-17 58 1.0.2 added debounce_gen
-- 2007-06-16 57 1.0.1 added cnt_array_dram, cnt_array_regs
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package genlib is
component clkdivce is -- generate usec/msec ce pulses
generic (
CDUWIDTH : positive := 6; -- usec clock divider width
USECDIV : positive := 50; -- divider ratio for usec pulse
MSECDIV : positive := 1000); -- divider ratio for msec pulse
port (
CLK : in slbit; -- input clock
CE_USEC : out slbit; -- usec pulse
CE_MSEC : out slbit -- msec pulse
);
end component;
component cnt_array_dram is -- counter array, dram based
generic (
AWIDTH : positive := 4; -- address width
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- clear counters
CE : in slv(2**AWIDTH-1 downto 0); -- count enables
ADDR : out slv(AWIDTH-1 downto 0); -- counter address
DATA : out slv(DWIDTH-1 downto 0); -- counter data
ACT : out slbit -- active (not reseting)
);
end component;
component cnt_array_regs is -- counter array, register based
generic (
AWIDTH : positive := 4; -- address width
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- clear counters
CE : in slv(2**AWIDTH-1 downto 0); -- count enables
ADDR : in slv(AWIDTH-1 downto 0); -- address
DATA : out slv(DWIDTH-1 downto 0) -- counter data
);
end component;
component debounce_gen is -- debounce, generic vector
generic (
CWIDTH : positive := 2; -- clock interval counter width
CEDIV : positive := 3; -- clock interval divider
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_INT : in slbit; -- clock interval enable (usec or msec)
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
component gray_cnt_gen is -- gray code counter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
component gray_cnt_4 is -- 4 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv4 -- data out
);
end component;
component gray_cnt_5 is -- 5 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv5 -- data out
);
end component;
component gray_cnt_n is -- n bit gray code counter
generic (
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
component gray2bin_gen is -- gray->bin converter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
DI : in slv(DWIDTH-1 downto 0); -- gray code input
DO : out slv(DWIDTH-1 downto 0) -- binary code output
);
end component;
component timer is -- retriggerable timer
generic (
TWIDTH : positive := 4; -- timer counter width
RETRIG : boolean := true); -- re-triggerable true/false
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DELAY : in slv(TWIDTH-1 downto 0) := (others=>'1'); -- timer delay
START : in slbit; -- start timer
STOP : in slbit := '0'; -- stop timer
DONE : out slbit; -- mark last delay cycle
BUSY : out slbit -- timer running
);
end component;
component cdc_pulse is -- clock domain cross for pulse
generic (
POUT_SINGLE : boolean := false; -- if true: single cycle pout
BUSY_WACK : boolean := false); -- if true: busy waits for ack
port (
CLKM : in slbit; -- clock master
RESET : in slbit := '0'; -- M|reset
CLKS : in slbit; -- clock slave
PIN : in slbit; -- M|pulse in
BUSY : out slbit; -- M|busy
POUT : out slbit -- S|pulse out
);
end component;
component led_pulse_stretch is -- pulse stretcher for leds
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- pulse time unit clock enable
RESET : in slbit := '0'; -- reset
DIN : in slbit; -- data in
POUT : out slbit -- pulse out
);
end component;
end package genlib;
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity bench_dspunit8 is
end bench_dspunit8;
--=----------------------------------------------------------------------------
architecture archi_bench_dspunit of bench_dspunit8 is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component dspunit
port (
clk : in std_logic;
clk_cpu : in std_logic;
reset : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m0 : out std_logic_vector((sig_width - 1) downto 0);
addr_r_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
addr_w_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m0 : out std_logic;
c_en_m0 : out std_logic;
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m1 : out std_logic_vector((sig_width - 1) downto 0);
addr_m1 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m1 : out std_logic;
c_en_m1 : out std_logic;
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m2 : out std_logic_vector((sig_width - 1) downto 0);
addr_m2 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m2 : out std_logic;
c_en_m2 : out std_logic;
addr_cmdreg : in std_logic_vector((cmdreg_addr_width - 1) downto 0);
data_in_cmdreg : in std_logic_vector((cmdreg_data_width - 1) downto 0);
wr_en_cmdreg : in std_logic;
data_out_cmdreg : out std_logic_vector((cmdreg_data_width - 1) downto 0);
irq : out std_logic;
op_done : out std_logic
);
end component;
component gen_memory
generic (
addr_width : natural;
data_width : natural
);
port (
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end component;
component clock_gen
generic (
tpw : time;
tps : time
);
port (
clk : out std_logic;
reset : out std_logic
);
end component;
component regBtoW
generic (
addr_width : integer
);
port (
reset : in std_logic;
clk : in std_logic;
data_in : in std_logic_vector(7 downto 0);
addr_in : in std_logic_vector(addr_width downto 0);
wr_in : in std_logic;
regbank_sel : in std_logic;
data_out : out std_logic_vector(15 downto 0);
addr_out : out std_logic_vector((addr_width - 1) downto 0);
wr_out : out std_logic
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_clk : std_logic;
signal s_reset : std_logic;
signal s_data_in_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_r_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_addr_w_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m0 : std_logic;
signal s_c_en_m0 : std_logic;
signal s_data_in_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m1 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m1 : std_logic;
signal s_c_en_m1 : std_logic;
signal s_data_in_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m2 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m2 : std_logic;
signal s_c_en_m2 : std_logic;
signal s_addr_cmdreg : std_logic_vector((cmdreg_addr_width - 1) downto 0);
signal s_data_in_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_wr_en_cmdreg : std_logic;
signal s_data_out_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_op_done : std_logic;
signal s_data_in_cmdreg8 : std_logic_vector(7 downto 0);
signal s_addr_cmdreg8 : std_logic_vector(cmdreg_addr_width downto 0);
signal s_wr_en_cmdreg8 : std_logic;
signal s_regbank_sel : std_logic;
signal s_irq : std_logic;
begin -- archs_bench_dspunit
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
dspunit_1 : dspunit
port map (
clk => s_clk,
clk_cpu => s_clk,
reset => s_reset,
data_in_m0 => s_data_in_m0,
data_out_m0 => s_data_out_m0,
addr_r_m0 => s_addr_r_m0,
addr_w_m0 => s_addr_w_m0,
wr_en_m0 => s_wr_en_m0,
c_en_m0 => s_c_en_m0,
data_in_m1 => s_data_in_m1,
data_out_m1 => s_data_out_m1,
addr_m1 => s_addr_m1,
wr_en_m1 => s_wr_en_m1,
c_en_m1 => s_c_en_m1,
data_in_m2 => s_data_in_m2,
data_out_m2 => s_data_out_m2,
addr_m2 => s_addr_m2,
wr_en_m2 => s_wr_en_m2,
c_en_m2 => s_c_en_m2,
addr_cmdreg => s_addr_cmdreg,
data_in_cmdreg => s_data_in_cmdreg,
wr_en_cmdreg => s_wr_en_cmdreg,
data_out_cmdreg => s_data_out_cmdreg,
irq => s_irq,
op_done => s_op_done);
gen_memory_1 : gen_memory
generic map (
addr_width => 16,
data_width => 16)
port map (
address_a => s_addr_r_m0,
address_b => s_addr_w_m0,
clock_a => s_clk,
clock_b => s_clk,
data_a => (others => '0'),
data_b => s_data_out_m0,
wren_a => '0',
wren_b => s_wr_en_m0,
q_a => s_data_in_m0,
q_b => open);
gen_memory_2 : gen_memory
generic map (
addr_width => 16,
data_width => 16)
port map (
address_a => s_addr_m1,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m1,
data_b => (others => '0'),
wren_a => s_wr_en_m1,
wren_b => '0',
q_a => s_data_in_m1,
q_b => open);
gen_memory_3 : gen_memory
generic map (
addr_width => 16,
data_width => 16)
port map (
address_a => s_addr_m2,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m2,
data_b => (others => '0'),
wren_a => s_wr_en_m2,
wren_b => '0',
q_a => s_data_in_m2,
q_b => open);
clock_gen_1 : clock_gen
generic map (
tpw => 2.5 ns,
tps => 0 ns)
port map (
clk => s_clk,
reset => s_reset);
regBtoW_1 : regBtoW
generic map (
addr_width => cmdreg_addr_width)
port map (
reset => s_reset,
clk => s_clk,
data_in => s_data_in_cmdreg8,
addr_in => s_addr_cmdreg8,
wr_in => s_wr_en_cmdreg8,
regbank_sel => s_regbank_sel,
data_out => s_data_in_cmdreg,
addr_out => s_addr_cmdreg,
wr_out => s_wr_en_cmdreg);
--=---------------------------------------------------------------------------
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
-- s_addr_cmdreg <= "000000", "000010" after 151 ns, "000111" after 161 ns, "000000" after 171 ns,
-- "000010" after 851 ns, "000111" after 861 ns, "000000" after 871 ns,
-- "000010" after 3651 ns, "000111" after 3661 ns, "000000" after 3671 ns;
-- s_data_in_cmdreg <= x"0000", x"000F" after 151 ns, x"0002" after 161 ns, x"0000" after 171 ns,
-- x"000F" after 851 ns, x"0003" after 861 ns, x"0000" after 871 ns,
-- x"000F" after 3651 ns, x"0002" after 3661 ns, x"0000" after 3671 ns;
-- s_wr_en_cmdreg <= '0', '1' after 151 ns, '0' after 171 ns, '1' after 851 ns, '0' after 871 ns,
-- '1' after 3651 ns, '0' after 3671 ns;
s_addr_cmdreg8 <= "0000000", "0000111" after 141 ns, "0000110" after 146 ns, "0000101" after 151 ns, "0000100" after 156 ns, "0001111" after 161 ns, "0001110" after 166 ns, "0000001" after 171 ns, "0000000" after 176 ns;
-- "0000101" after 851 ns, "0000100" after 856 ns, "0001111" after 861 ns, "0001110" after 861 ns, "000000" after 871 ns,
-- "000010" after 3651 ns, "000111" after 3661 ns, "000000" after 3671 ns;
s_data_in_cmdreg8 <= x"00", x"01" after 141 ns, x"32" after 146 ns, x"01" after 151 ns, x"FF" after 156 ns, x"00" after 161 ns, x"02" after 166 ns, x"00" after 171 ns, x"00" after 176 ns;
-- x"000F" after 851 ns, x"0003" after 861 ns, x"0000" after 871 ns,
-- x"000F" after 3651 ns, x"0002" after 3661 ns, x"0000" after 3671 ns;
s_wr_en_cmdreg8 <= '0', '1' after 141 ns, '0' after 171 ns; -- '1' after 851 ns, '0' after 871 ns,
-- '1' after 3651 ns, '0' after 3671 ns;
s_regbank_sel <= '1';
end archi_bench_dspunit;
-------------------------------------------------------------------------------
-- Simulation parameters
-->SIMSTOPTIME=10000ns
-->SIMSAVFILE=
-------------------------------------------------------------------------------
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity bench_dspunit8 is
end bench_dspunit8;
--=----------------------------------------------------------------------------
architecture archi_bench_dspunit of bench_dspunit8 is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component dspunit
port (
clk : in std_logic;
clk_cpu : in std_logic;
reset : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m0 : out std_logic_vector((sig_width - 1) downto 0);
addr_r_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
addr_w_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m0 : out std_logic;
c_en_m0 : out std_logic;
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m1 : out std_logic_vector((sig_width - 1) downto 0);
addr_m1 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m1 : out std_logic;
c_en_m1 : out std_logic;
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m2 : out std_logic_vector((sig_width - 1) downto 0);
addr_m2 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m2 : out std_logic;
c_en_m2 : out std_logic;
addr_cmdreg : in std_logic_vector((cmdreg_addr_width - 1) downto 0);
data_in_cmdreg : in std_logic_vector((cmdreg_data_width - 1) downto 0);
wr_en_cmdreg : in std_logic;
data_out_cmdreg : out std_logic_vector((cmdreg_data_width - 1) downto 0);
irq : out std_logic;
op_done : out std_logic
);
end component;
component gen_memory
generic (
addr_width : natural;
data_width : natural
);
port (
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end component;
component clock_gen
generic (
tpw : time;
tps : time
);
port (
clk : out std_logic;
reset : out std_logic
);
end component;
component regBtoW
generic (
addr_width : integer
);
port (
reset : in std_logic;
clk : in std_logic;
data_in : in std_logic_vector(7 downto 0);
addr_in : in std_logic_vector(addr_width downto 0);
wr_in : in std_logic;
regbank_sel : in std_logic;
data_out : out std_logic_vector(15 downto 0);
addr_out : out std_logic_vector((addr_width - 1) downto 0);
wr_out : out std_logic
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_clk : std_logic;
signal s_reset : std_logic;
signal s_data_in_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_r_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_addr_w_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m0 : std_logic;
signal s_c_en_m0 : std_logic;
signal s_data_in_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m1 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m1 : std_logic;
signal s_c_en_m1 : std_logic;
signal s_data_in_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m2 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m2 : std_logic;
signal s_c_en_m2 : std_logic;
signal s_addr_cmdreg : std_logic_vector((cmdreg_addr_width - 1) downto 0);
signal s_data_in_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_wr_en_cmdreg : std_logic;
signal s_data_out_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_op_done : std_logic;
signal s_data_in_cmdreg8 : std_logic_vector(7 downto 0);
signal s_addr_cmdreg8 : std_logic_vector(cmdreg_addr_width downto 0);
signal s_wr_en_cmdreg8 : std_logic;
signal s_regbank_sel : std_logic;
signal s_irq : std_logic;
begin -- archs_bench_dspunit
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
dspunit_1 : dspunit
port map (
clk => s_clk,
clk_cpu => s_clk,
reset => s_reset,
data_in_m0 => s_data_in_m0,
data_out_m0 => s_data_out_m0,
addr_r_m0 => s_addr_r_m0,
addr_w_m0 => s_addr_w_m0,
wr_en_m0 => s_wr_en_m0,
c_en_m0 => s_c_en_m0,
data_in_m1 => s_data_in_m1,
data_out_m1 => s_data_out_m1,
addr_m1 => s_addr_m1,
wr_en_m1 => s_wr_en_m1,
c_en_m1 => s_c_en_m1,
data_in_m2 => s_data_in_m2,
data_out_m2 => s_data_out_m2,
addr_m2 => s_addr_m2,
wr_en_m2 => s_wr_en_m2,
c_en_m2 => s_c_en_m2,
addr_cmdreg => s_addr_cmdreg,
data_in_cmdreg => s_data_in_cmdreg,
wr_en_cmdreg => s_wr_en_cmdreg,
data_out_cmdreg => s_data_out_cmdreg,
irq => s_irq,
op_done => s_op_done);
gen_memory_1 : gen_memory
generic map (
addr_width => 16,
data_width => 16)
port map (
address_a => s_addr_r_m0,
address_b => s_addr_w_m0,
clock_a => s_clk,
clock_b => s_clk,
data_a => (others => '0'),
data_b => s_data_out_m0,
wren_a => '0',
wren_b => s_wr_en_m0,
q_a => s_data_in_m0,
q_b => open);
gen_memory_2 : gen_memory
generic map (
addr_width => 16,
data_width => 16)
port map (
address_a => s_addr_m1,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m1,
data_b => (others => '0'),
wren_a => s_wr_en_m1,
wren_b => '0',
q_a => s_data_in_m1,
q_b => open);
gen_memory_3 : gen_memory
generic map (
addr_width => 16,
data_width => 16)
port map (
address_a => s_addr_m2,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m2,
data_b => (others => '0'),
wren_a => s_wr_en_m2,
wren_b => '0',
q_a => s_data_in_m2,
q_b => open);
clock_gen_1 : clock_gen
generic map (
tpw => 2.5 ns,
tps => 0 ns)
port map (
clk => s_clk,
reset => s_reset);
regBtoW_1 : regBtoW
generic map (
addr_width => cmdreg_addr_width)
port map (
reset => s_reset,
clk => s_clk,
data_in => s_data_in_cmdreg8,
addr_in => s_addr_cmdreg8,
wr_in => s_wr_en_cmdreg8,
regbank_sel => s_regbank_sel,
data_out => s_data_in_cmdreg,
addr_out => s_addr_cmdreg,
wr_out => s_wr_en_cmdreg);
--=---------------------------------------------------------------------------
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
-- s_addr_cmdreg <= "000000", "000010" after 151 ns, "000111" after 161 ns, "000000" after 171 ns,
-- "000010" after 851 ns, "000111" after 861 ns, "000000" after 871 ns,
-- "000010" after 3651 ns, "000111" after 3661 ns, "000000" after 3671 ns;
-- s_data_in_cmdreg <= x"0000", x"000F" after 151 ns, x"0002" after 161 ns, x"0000" after 171 ns,
-- x"000F" after 851 ns, x"0003" after 861 ns, x"0000" after 871 ns,
-- x"000F" after 3651 ns, x"0002" after 3661 ns, x"0000" after 3671 ns;
-- s_wr_en_cmdreg <= '0', '1' after 151 ns, '0' after 171 ns, '1' after 851 ns, '0' after 871 ns,
-- '1' after 3651 ns, '0' after 3671 ns;
s_addr_cmdreg8 <= "0000000", "0000111" after 141 ns, "0000110" after 146 ns, "0000101" after 151 ns, "0000100" after 156 ns, "0001111" after 161 ns, "0001110" after 166 ns, "0000001" after 171 ns, "0000000" after 176 ns;
-- "0000101" after 851 ns, "0000100" after 856 ns, "0001111" after 861 ns, "0001110" after 861 ns, "000000" after 871 ns,
-- "000010" after 3651 ns, "000111" after 3661 ns, "000000" after 3671 ns;
s_data_in_cmdreg8 <= x"00", x"01" after 141 ns, x"32" after 146 ns, x"01" after 151 ns, x"FF" after 156 ns, x"00" after 161 ns, x"02" after 166 ns, x"00" after 171 ns, x"00" after 176 ns;
-- x"000F" after 851 ns, x"0003" after 861 ns, x"0000" after 871 ns,
-- x"000F" after 3651 ns, x"0002" after 3661 ns, x"0000" after 3671 ns;
s_wr_en_cmdreg8 <= '0', '1' after 141 ns, '0' after 171 ns; -- '1' after 851 ns, '0' after 871 ns,
-- '1' after 3651 ns, '0' after 3671 ns;
s_regbank_sel <= '1';
end archi_bench_dspunit;
-------------------------------------------------------------------------------
-- Simulation parameters
-->SIMSTOPTIME=10000ns
-->SIMSAVFILE=
-------------------------------------------------------------------------------
|
--
-- Signal edge detect
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_edge_detect is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
RE : out std_logic; -- Rising edge detected
FE : out std_logic -- Falling edge detected
);
end slib_edge_detect;
architecture rtl of slib_edge_detect is
signal iDd : std_logic; -- D register
begin
-- Store D
ED_D: process (RST, CLK)
begin
if (RST = '1') then
iDd <= '0';
elsif (CLK'event and CLK='1') then
iDd <= D;
end if;
end process;
-- Output ports
RE <= '1' when iDd = '0' and D = '1' else '0';
FE <= '1' when iDd = '1' and D = '0' else '0';
end rtl;
|
--
-- Signal edge detect
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_edge_detect is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
RE : out std_logic; -- Rising edge detected
FE : out std_logic -- Falling edge detected
);
end slib_edge_detect;
architecture rtl of slib_edge_detect is
signal iDd : std_logic; -- D register
begin
-- Store D
ED_D: process (RST, CLK)
begin
if (RST = '1') then
iDd <= '0';
elsif (CLK'event and CLK='1') then
iDd <= D;
end if;
end process;
-- Output ports
RE <= '1' when iDd = '0' and D = '1' else '0';
FE <= '1' when iDd = '1' and D = '0' else '0';
end rtl;
|
--
-- Signal edge detect
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_edge_detect is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
RE : out std_logic; -- Rising edge detected
FE : out std_logic -- Falling edge detected
);
end slib_edge_detect;
architecture rtl of slib_edge_detect is
signal iDd : std_logic; -- D register
begin
-- Store D
ED_D: process (RST, CLK)
begin
if (RST = '1') then
iDd <= '0';
elsif (CLK'event and CLK='1') then
iDd <= D;
end if;
end process;
-- Output ports
RE <= '1' when iDd = '0' and D = '1' else '0';
FE <= '1' when iDd = '1' and D = '0' else '0';
end rtl;
|
--
-- Signal edge detect
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_edge_detect is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
RE : out std_logic; -- Rising edge detected
FE : out std_logic -- Falling edge detected
);
end slib_edge_detect;
architecture rtl of slib_edge_detect is
signal iDd : std_logic; -- D register
begin
-- Store D
ED_D: process (RST, CLK)
begin
if (RST = '1') then
iDd <= '0';
elsif (CLK'event and CLK='1') then
iDd <= D;
end if;
end process;
-- Output ports
RE <= '1' when iDd = '0' and D = '1' else '0';
FE <= '1' when iDd = '1' and D = '0' else '0';
end rtl;
|
--
-- Signal edge detect
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_edge_detect is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
RE : out std_logic; -- Rising edge detected
FE : out std_logic -- Falling edge detected
);
end slib_edge_detect;
architecture rtl of slib_edge_detect is
signal iDd : std_logic; -- D register
begin
-- Store D
ED_D: process (RST, CLK)
begin
if (RST = '1') then
iDd <= '0';
elsif (CLK'event and CLK='1') then
iDd <= D;
end if;
end process;
-- Output ports
RE <= '1' when iDd = '0' and D = '1' else '0';
FE <= '1' when iDd = '1' and D = '0' else '0';
end rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_MISC.ALL;
--MIPI CSI-2 word aligner
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This receives aligned bytes and status signals from the 4 byte aligners
--and compensates for up to 2 clock cycles of skew between channels. It also
--controls the packet_done input to the byte aligner, resetting byte aligners'
--sync status if all 4 byte aligners fail to find the sync pattern
--Similar to the byte aligner, this locks the alignment once a valid alignment
--has been found until packet_done is asserted
entity csi_rx_word_align is
Port ( word_clock : in STD_LOGIC; --byte/word clock in
reset : in STD_LOGIC; --active high synchronous reset
enable : in STD_LOGIC; --active high enable
packet_done : in STD_LOGIC; --packet done input from packet handler entity
wait_for_sync : in STD_LOGIC; --whether or not to be looking for an alignment
packet_done_out : out STD_LOGIC; --packet done output to byte aligners
word_in : in STD_LOGIC_VECTOR (31 downto 0); --unaligned word from the 4 byte aligners
valid_in : in STD_LOGIC_VECTOR (3 downto 0); --valid_out from the byte aligners (MSB is index 3, LSB index 0)
word_out : out STD_LOGIC_VECTOR (31 downto 0); --aligned word out to packet handler
valid_out : out STD_LOGIC); --goes high once alignment is valid, such that the first word with it high is the CSI packet header
end csi_rx_word_align;
architecture Behavioral of csi_rx_word_align is
signal word_dly_0 : std_logic_vector(31 downto 0);
signal word_dly_1 : std_logic_vector(31 downto 0);
signal word_dly_2 : std_logic_vector(31 downto 0);
signal valid_dly_0 : std_logic_vector (3 downto 0);
signal valid_dly_1 : std_logic_vector (3 downto 0);
signal valid_dly_2 : std_logic_vector (3 downto 0);
type taps_t is array(0 to 3) of std_logic_vector(1 downto 0);
signal taps : taps_t;
signal next_taps : taps_t;
signal valid : std_logic := '0';
signal next_valid : std_logic;
signal invalid_start : std_logic := '0';
signal aligned_word : std_logic_vector(31 downto 0);
begin
process(word_clock)
begin
if rising_edge(word_clock) then
if reset = '1' then
valid <= '0';
taps <= ("00", "00", "00", "00");
elsif enable = '1' then
word_dly_0 <= word_in;
valid_dly_0 <= valid_in;
word_dly_1 <= word_dly_0;
valid_dly_1 <= valid_dly_0;
word_dly_2 <= word_dly_1;
valid_dly_2 <= valid_dly_1;
valid_out <= valid;
word_out <= aligned_word;
if next_valid = '1' and valid = '0' and wait_for_sync = '1' then
valid <= '1';
taps <= next_taps;
elsif packet_done = '1' then
valid <= '0';
end if;
end if;
end if;
end process;
process(valid_dly_0, valid_dly_1, valid_dly_2)
variable next_valid_int : std_logic;
variable is_triggered : std_logic := '0';
begin
next_valid_int := and_reduce(valid_dly_0);
--Reset if all channels fail to sync
is_triggered := '0';
for i in 0 to 3 loop
if valid_dly_0(i) = '1' and valid_dly_1(i) = '1' and valid_dly_2(i) = '1' then
is_triggered := '1';
end if;
end loop;
invalid_start <= (not next_valid_int) and is_triggered;
next_valid <= next_valid_int;
for i in 0 to 3 loop
if valid_dly_2(i) = '1' then
next_taps(i) <= "10";
elsif valid_dly_1(i) = '1' then
next_taps(i) <= "01";
else
next_taps(i) <= "00";
end if;
end loop;
end process;
packet_done_out <= packet_done or invalid_start;
process(word_dly_0, word_dly_1, word_dly_2, taps)
begin
for i in 0 to 3 loop
if taps(i) = "10" then
aligned_word((8*i) + 7 downto 8 * i) <= word_dly_2((8*i) + 7 downto 8 * i);
elsif taps(i) = "01" then
aligned_word((8*i) + 7 downto 8 * i) <= word_dly_1((8*i) + 7 downto 8 * i);
else
aligned_word((8*i) + 7 downto 8 * i) <= word_dly_0((8*i) + 7 downto 8 * i);
end if;
end loop;
end process;
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2sp64a
-- File: ddr2sp64a.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: 64-bit DDR2 memory controller with asych AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
entity ddr2sp64a is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of ddr2sp64a is
constant REVISION : integer := 0;
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant odtvalue : std_logic_vector(1 downto 0) := conv_std_logic_vector(odten, 2);
constant abuf : integer := 6;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDR2SP, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, ext, leadout);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr0, wr1, wr2, wr3, wr4a, wr4b, wr4, wr5, sidle, ioreg1, ioreg2);
type icycletype is (iidle, pre, ref1, ref2, emode23, emode, lmode, emodeocd, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(4 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
cal_en : std_logic_vector(7 downto 0);
cal_inc : std_logic_vector(7 downto 0);
cal_rst : std_logic;
readdly : std_logic_vector(1 downto 0);
twr : std_logic_vector(4 downto 0);
emr : std_logic_vector(1 downto 0); -- selects EM register
ocd : std_ulogic; -- enable/disable ocd
end record;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
end record;
-- local registers
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
write : std_logic_vector(3 downto 0);
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(1 downto 0);
acc : access_param;
sync : std_logic_vector(2 downto 1);
startsd_ack : std_logic;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
startsdold : std_ulogic;
hready : std_ulogic;
bdrive : std_ulogic;
qdrive : std_ulogic;
nbdrive : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
trfc : std_logic_vector(4 downto 0);
refresh : std_logic_vector(11 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(15 downto 0);
address : std_logic_vector(15 downto 2); -- memory address
ba : std_logic_vector( 1 downto 0);
waddr : std_logic_vector(abuf-1 downto 0);
waddr_d : std_logic_vector(abuf-1 downto 0); -- Same as waddr but delayed to compensate for pipelined output data
cfg : sdram_cfg_type;
hrdata : std_logic_vector(127 downto 0);
readdly : std_logic_vector(1 downto 0); -- added read latency
wdata : std_logic_vector(127 downto 0); -- pipeline register for output data
initnopdly : std_logic_vector(7 downto 0); -- 400 ns delay
sync : std_logic;
odt : std_logic_vector(1 downto 0);
end record;
signal vcc : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rdata, wdata : std_logic_vector(127 downto 0);
signal ddr_rst : std_logic;
signal ddr_rst_gen : std_logic_vector(3 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
vcc <= '1';
ddr_rst <= (ddr_rst_gen(3) and ddr_rst_gen(2) and ddr_rst_gen(1) and rst); -- Reset signal in DDR clock domain
ahb_ctrl : process(rst, ahbsi, r, ra, rdata)
variable v : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dout : std_logic_vector(31 downto 0);
variable ready : std_logic;
begin
v := ra; v.hresp := HRESP_OKAY; v.write := "0000";
case ra.raddr(1 downto 0) is
when "00" => v.hrdata := rdata(127 downto 96);
when "01" => v.hrdata := rdata(95 downto 64);
when "10" => v.hrdata := rdata(63 downto 32);
when others => v.hrdata := rdata(31 downto 0);
end case;
-- Sync ------------------------------------------------
v.sync(1) := r.startsdold; v.sync(2) := ra.sync(1);
ready := ra.startsd_ack xor ra.sync(2);
--------------------------------------------------------
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.htrans := ahbsi.htrans; v.haddr := ahbsi.haddr;
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
if ((v.hsel and v.htrans(1)) = '1') then
if v.hwrite = '0' then
v.state := rhold; v.startsd := not ra.startsd;
else
v.state := dwrite; v.hready := '1';
v.write := decode(v.haddr(3 downto 2));
end if;
end if;
v.raddr := ra.haddr(7 downto 2);
if ahbsi.hready = '1' then
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
when rhold =>
v.raddr := ra.haddr(7 downto 2);
if ready = '1' then
v.state := dread; v.hready := '1'; v.raddr := ra.raddr + 1;
end if;
when dread =>
v.raddr := ra.raddr + 1; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0')
or (ra.raddr(2 downto 0) = "000") then
v.state := midle; v.hready := '0';
v.startsd_ack := ra.startsd;
end if;
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
when dwrite =>
v.raddr := ra.haddr(7 downto 2); v.hready := '1';
v.write := decode(v.haddr(3 downto 2));
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0')
or (ra.haddr(4 downto 2) = "111") then
v.startsd := not ra.startsd; v.state := whold1;
v.write := "0000"; v.hready := '0';
end if;
when whold1 =>
v.state := whold2;
when whold2 =>
if ready = '1' then
v.state := midle; v.acc := (v.haddr, v.size, v.hwrite, v.hio);
v.startsd_ack := ra.startsd;
end if;
end case;
v.hwdata := ahbsi.hwdata;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
dout := ra.hrdata(31 downto 0);
if rst = '0' then
v.hsel := '0';
v.hready := '1';
v.state := midle;
v.startsd := '0';
v.startsd_ack := '0';
v.hio := '0';
end if;
rai <= v;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= dout;
ahbso.hcache <= not ra.hio;
end process;
ddr_ctrl : process(ddr_rst, r, ra, sdi, rbdrive, wdata)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dqm : std_logic_vector(15 downto 0);
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable writecfg : std_ulogic;
variable regsd1 : std_logic_vector(31 downto 0); -- data from registers
variable regsd2 : std_logic_vector(31 downto 0); -- data from registers
variable regsd3 : std_logic_vector(31 downto 0); -- data from registers
begin
-- Variable default settings to avoid latches
v := r; v.hready := '0'; writecfg := '0'; vbdrive := rbdrive;
v.hrdata := sdi.data; v.qdrive :='0';
v.cfg.cal_en := (others => '0'); v.cfg.cal_inc := (others => '0');
v.cfg.cal_rst := '0';
v.wdata := wdata; -- pipeline output data
regsd1 := (others => '0');
regsd1(31 downto 15) := r.cfg.refon & r.cfg.ocd & r.cfg.emr & '0' & r.cfg.trcd &
r.cfg.bsize & r.cfg.csize & r.cfg.command &
r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
regsd1(11 downto 0) := r.cfg.refresh;
regsd2 := (others => '0');
regsd2(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd2(14 downto 12) := conv_std_logic_vector(3, 3);
regsd3 := (others => '0');
regsd3(17 downto 16) := r.cfg.readdly;
regsd3(22 downto 18) := r.cfg.trfc;
regsd3(27 downto 23) := r.cfg.twr;
regsd3(28) := r.cfg.trp;
-- generate DQM from address and write size
case ra.acc.size is
when "00" =>
case ra.acc.haddr(3 downto 0) is
when "0000" => dqm := "0111111111111111";
when "0001" => dqm := "1011111111111111";
when "0010" => dqm := "1101111111111111";
when "0011" => dqm := "1110111111111111";
when "0100" => dqm := "1111011111111111";
when "0101" => dqm := "1111101111111111";
when "0110" => dqm := "1111110111111111";
when "0111" => dqm := "1111111011111111";
when "1000" => dqm := "1111111101111111";
when "1001" => dqm := "1111111110111111";
when "1010" => dqm := "1111111111011111";
when "1011" => dqm := "1111111111101111";
when "1100" => dqm := "1111111111110111";
when "1101" => dqm := "1111111111111011";
when "1110" => dqm := "1111111111111101";
when others => dqm := "1111111111111110";
end case;
when "01" =>
case ra.acc.haddr(3 downto 1) is
when "000" => dqm := "0011111111111111";
when "001" => dqm := "1100111111111111";
when "010" => dqm := "1111001111111111";
when "011" => dqm := "1111110011111111";
when "100" => dqm := "1111111100111111";
when "101" => dqm := "1111111111001111";
when "110" => dqm := "1111111111110011";
when others => dqm := "1111111111111100";
end case;
when others =>
dqm := "0000000000000000";
end case;
-- Sync ------------------------------------------
v.sync := ra.startsd; v.startsd := r.sync;
--------------------------------------------------
--v.startsd := ra.startsd;
---- main FSM
--
-- case r.mstate is
-- when midle =>
-- if r.startsd = '1' then
-- if (r.sdstate = sidle) and (r.cfg.command = "000")
-- and (r.cmstate = midle) then
-- startsd := '1'; v.mstate := active;
-- end if;
-- end if;
-- when others => null;
-- end case;
startsd := r.startsd xor r.startsdold;
-- generate row and column address size
haddr := ra.acc.haddr;
haddr(31 downto 20) := haddr(31 downto 20) and not conv_std_logic_vector(hmask, 12);
case r.cfg.csize is
when "00" => raddr := haddr(25 downto 12);
when "01" => raddr := haddr(26 downto 13);
when "10" => raddr := haddr(27 downto 14);
when others => raddr := haddr(28 downto 15);
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(29 downto 22)) &
genmux(r.cfg.bsize, haddr(28 downto 21));
-- generate chip select
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "00000" then v.trfc := r.trfc - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle)
and (r.istate = finish) then
v.address := raddr; v.ba := ba;
if ra.acc.hio = '0' then
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
else v.sdstate := ioreg1; end if;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act1 =>
v.rasn := '1'; v.trfc := r.cfg.trfc;
if r.cfg.trcd = '1' then v.sdstate := act2;
else v.sdstate := act3;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
v.waddr_d := ra.acc.haddr(7 downto 2);
when act2 =>
v.sdstate := act3;
when act3 =>
v.casn := '0';
v.address := ra.acc.haddr(15 downto 13) & '0' & ra.acc.haddr(12 downto 4) & '0';
v.hready := ra.acc.hwrite;
if ra.acc.hwrite = '1' then
v.sdstate := wr0;
v.sdwen := '0';
v.waddr := r.waddr + 4; v.waddr(1 downto 0) := "00"; -- inc address to memory, needed because data is pipelined
v.trfc := r.cfg.twr;
else v.sdstate := rd1; end if;
when wr0 =>
v.casn := '1'; v.sdwen := '1'; v.bdrive := '0'; v.qdrive := '1';
v.dqm := dqm;
v.waddr_d := r.waddr_d + 4; v.waddr_d(1 downto 0) := "00";
v.waddr := r.waddr + 4;
v.sdstate := wr1;
if (r.waddr_d /= ra.raddr) then v.hready := '1';
if (r.waddr_d(5 downto 2) = ra.raddr(5 downto 2)) then
if r.waddr_d(1) = '1' then v.dqm(15 downto 8) := (others => '1');
else
case ra.raddr(1 downto 0) is
when "01" => v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(3 downto 0) := (others => '1');
v.dqm(15 downto 12) := (others => r.waddr_d(0));
when others => v.dqm(15 downto 12) := (others => r.waddr_d(0));
end case;
end if;
else
case r.waddr_d(1 downto 0) is
when "01" => v.dqm(15 downto 12) := (others => '1');
when "10" => v.dqm(15 downto 8) := (others => '1');
when "11" => v.dqm(15 downto 4) := (others => '1');
when others => null;
end case;
end if;
else
case r.waddr_d(1 downto 0) is
when "00" => v.dqm(11 downto 0) := (others => '1');
when "01" => v.dqm(15 downto 12) := (others => '1'); v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(15 downto 8) := (others => '1'); v.dqm(3 downto 0) := (others => '1');
when others => v.dqm(15 downto 4) := (others => '1');
end case;
end if;
when wr1 =>
v.sdwen := '1'; v.casn := '1'; v.qdrive := '1';
v.waddr_d := r.waddr_d + 4; v.dqm := (others => '0');
v.waddr := r.waddr + 4;
v.address(8 downto 3) := r.waddr_d;
if (r.waddr_d <= ra.raddr) and (r.waddr_d(5 downto 2) /= "0000") and (r.hready = '1') then
v.hready := '1';
if (r.hready = '1') and (r.waddr_d(2 downto 0) = "000") then
v.sdwen := '0'; v.casn := '0';
end if;
if (r.waddr_d(5 downto 2) = ra.raddr(5 downto 2)) and (r.waddr_d /= "000000") then
case ra.raddr(1 downto 0) is
when "00" => v.dqm(11 downto 0) := (others => '1');
when "01" => v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(3 downto 0) := (others => '1');
when others => null;
end case;
end if;
else
v.sdstate := wr2;
v.dqm := (others => '1');
v.startsdold := r.startsd;
end if;
when wr2 =>
v.sdstate := wr3; v.qdrive := '1';
when wr3 =>
v.sdstate := wr4a; v.qdrive := '1';
when wr4a =>
v.bdrive := '1'; v.qdrive := '1';
if r.trfc <= "00000" then -- wait to not violate TWR timing
v.sdstate := wr4b;
end if;
when wr4b =>
v.bdrive := '1';
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; v.qdrive := '1';
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.qdrive := '0';
v.sdstate := wr5;
when wr5 =>
v.sdstate := sidle;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
when rd7 =>
v.casn := '1'; v.sdstate := rd8;
v.readdly := r.cfg.readdly;
when rd8 => -- (CL = 3)
v.casn := '1';
if r.readdly = "00" then -- add read delay
v.sdstate := rd2;
else
v.readdly := r.readdly - 1;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if fast = 0 then v.startsdold := r.startsd; end if;
if v.hready = '1' then v.waddr := r.waddr + 4; end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (r.sdcsn = "11") or (r.waddr(2 downto 2) = "1") then
v.dqm := (others => '1');
if fast /= 0 then v.startsdold := r.startsd; end if;
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
end if;
end if;
if v.hready = '1' then v.waddr := r.waddr + 4; end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
when rd6 =>
v.sdstate := sidle; v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when ioreg1 =>
v.hrdata(127 downto 32) := regsd1 & regsd2 & regsd3; v.sdstate := ioreg2;
if ra.acc.hwrite = '0' then v.hready := '1'; end if;
when ioreg2 =>
writecfg := ra.acc.hwrite; v.startsdold := r.startsd;
v.sdstate := sidle;
when others =>
v.sdstate := sidle;
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when CMD_PRE => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when CMD_REF => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when CMD_EMR => -- load-ext-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := r.cfg.emr; --v.ba select EM register;
--v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd&"0000000";
if r.cfg.emr = "01" then
v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd
& odtvalue(1)&"000"&odtvalue(0)&"00";
else
v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd&"0000000";
end if;
when CMD_LMR => -- load-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "00";
v.address := "00010" & r.cfg.dllrst & "0" & "01" & "10010"; -- CAS = 3 WR = 3
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; v.cfg.command := "000";
v.cmstate := leadout; v.trfc := r.cfg.trfc;
when others =>
if r.trfc = "00000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
if r.cfg.renable = '1' then
v.cfg.cke := '1'; v.cfg.dllrst := '1';
v.ba := "00"; v.cfg.ocd := '0'; v.cfg.emr := "10"; -- EMR(2)
if r.cfg.cke = '1' then
if r.initnopdly = "00000000" then -- 400 ns of NOP and CKE
v.istate := pre; v.cfg.command := CMD_PRE;
else
v.initnopdly := r.initnopdly - 1;
end if;
end if;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "11" & r.cfg.dllrst; -- CMD_LMR/CMD_EMR
if r.cfg.dllrst = '1' then v.istate := emode23; else v.istate := lmode; end if;
end if;
when emode23 =>
if r.cfg.command = "000" then
if r.cfg.emr = "11" then
v.cfg.emr := "01"; -- (EMR(1))
v.istate := emode; v.cfg.command := CMD_EMR;
else
v.cfg.emr := "11"; v.cfg.command := CMD_EMR; -- EMR(3)
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := lmode; v.cfg.command := CMD_LMR;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.dllrst = '1' then
if r.refresh(9 downto 8) = "00" then -- > 200 clocks delay
v.cfg.command := CMD_PRE; v.istate := ref1;
end if;
else
v.istate := emodeocd;
v.cfg.ocd := '1'; v.cfg.command := CMD_EMR;
end if;
end if;
when ref1 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.cfg.dllrst := '0'; v.istate := ref2;
end if;
when ref2 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.istate := pre;
end if;
when emodeocd =>
if r.cfg.command = "000" then
if r.cfg.ocd = '0' then -- Exit OCD
v.istate := finish;
v.cfg.refon := '1'; v.cfg.renable := '0';
else -- Default OCD
v.cfg.ocd := '0';
v.cfg.command := CMD_EMR;
end if;
end if;
v.cfg.cal_rst := '1'; -- reset data bit delay
when others =>
if odten /= 0 then v.odt := (others => '1'); end if;
if r.cfg.renable = '1' then
v.istate := iidle; v.cfg.dllrst := '1';
v.initnopdly := (others => '1');
v.odt := (others => '0');
end if;
end case;
---- second part of main fsm
--
-- case r.mstate is
-- when active =>
-- if v.hready = '1' then
-- v.mstate := midle;
-- end if;
-- when others => null;
-- end case;
-- sdram refresh counter
if ((r.cfg.refon = '1') and (r.istate = finish)) or (r.cfg.dllrst = '1') then
v.refresh := r.refresh - 1;
if (v.refresh(11) and not r.refresh(11)) = '1' then
v.refresh := r.cfg.refresh;
if r.cfg.dllrst = '0' then v.cfg.command := "100"; end if;
end if;
end if;
-- AHB register access
if (ra.acc.hio and ra.acc.hwrite and writecfg) = '1' then
if r.waddr(1 downto 0) = "00" then
v.cfg.refresh := r.wdata(11+96 downto 0+96);
v.cfg.cke := r.wdata(15+96);
v.cfg.renable := r.wdata(16+96);
v.cfg.dllrst := r.wdata(17+96);
v.cfg.command := r.wdata(20+96 downto 18+96);
v.cfg.csize := r.wdata(22+96 downto 21+96);
v.cfg.bsize := r.wdata(25+96 downto 23+96);
v.cfg.trcd := r.wdata(26+96);
v.cfg.emr := r.wdata(29+96 downto 28+96);
v.cfg.ocd := r.wdata(30+96);
v.cfg.refon := r.wdata(31+96);
elsif r.waddr(1 downto 0) = "10" then
v.cfg.cal_en := r.wdata( 7+32 downto 0+32);
v.cfg.cal_inc := r.wdata(15+32 downto 8+32);
v.cfg.readdly := r.wdata(17+32 downto 16+32);
v.cfg.trfc := r.wdata(22+32 downto 18+32);
v.cfg.twr := r.wdata(27+32 downto 23+32);
v.cfg.trp := r.wdata(28+32);
v.cfg.cal_rst := r.wdata(31+32);
end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if ddr_rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := finish;
v.cmstate := midle;
v.cfg.command := "000";
v.cfg.csize := conv_std_logic_vector(col-9, 2);
v.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
v.cfg.refon := '0';
v.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 5);
v.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
v.cfg.twr := conv_std_logic_vector((15)*MHz/1000+3, 5);
v.refresh := (others => '0');
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '0';
v.startsd := '0';
v.startsdold := '0';
v.cfg.dllrst := '0';
v.cfg.cke := '0';
v.cfg.ocd := '0';
v.cfg.readdly := conv_std_logic_vector(readdly, 2);
v.initnopdly := (others => '1');
if MHz > 130 then v.cfg.trcd := '1'; else v.cfg.trcd := '0'; end if;
if MHz > 130 then v.cfg.trp := '1'; else v.cfg.trp := '0'; end if;
if pwron = 1 then v.cfg.renable := '1';
else v.cfg.renable := '0'; end if;
v.odt := (others => '0');
end if;
ri <= v;
ribdrive <= vbdrive;
end process;
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbregs : process(clk_ahb) begin
if rising_edge(clk_ahb) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr, rst, ddr_rst) begin
if rising_edge(clk_ddr) then
r <= ri; rbdrive <= ribdrive;
ddr_rst_gen <= ddr_rst_gen(2 downto 0) & '1';
end if;
if (rst = '0') then
ddr_rst_gen <= "0000";
end if;
if (ddr_rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
r.cfg.cke <= '0';
end if;
end process;
sdo.address <= '0' & ri.address;
sdo.ba <= ri.ba;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.qdrive <= not (ri.qdrive or r.nbdrive);
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= ri.sdcsn;
sdo.sdwen <= ri.sdwen;
sdo.dqm <= r.dqm;
sdo.rasn <= ri.rasn;
sdo.casn <= ri.casn;
--sdo.data <= wdata;
sdo.data <= r.wdata; -- data pipelined
sdo.cal_en <= r.cfg.cal_en;
sdo.cal_inc <= r.cfg.cal_inc;
sdo.cal_rst <= r.cfg.cal_rst;
sdo.odt <= r.odt;
read_buff : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 128, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rai.raddr(5 downto 2),
dataout => rdata, wclk => clk_ddr, write => ri.hready,
waddress => r.waddr(5 downto 2), datain => ri.hrdata);
write_buff1 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(127 downto 96), wclk => clk_ahb, write => ra.write(0),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff2 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(95 downto 64), wclk => clk_ahb, write => ra.write(1),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff3 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(63 downto 32), wclk => clk_ahb, write => ra.write(2),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff4 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(31 downto 0), wclk => clk_ahb, write => ra.write(3),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddr2sp" & tost(hindex) & ": 64-bit DDR2 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2sp64a
-- File: ddr2sp64a.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: 64-bit DDR2 memory controller with asych AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
entity ddr2sp64a is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of ddr2sp64a is
constant REVISION : integer := 0;
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant odtvalue : std_logic_vector(1 downto 0) := conv_std_logic_vector(odten, 2);
constant abuf : integer := 6;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDR2SP, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, ext, leadout);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr0, wr1, wr2, wr3, wr4a, wr4b, wr4, wr5, sidle, ioreg1, ioreg2);
type icycletype is (iidle, pre, ref1, ref2, emode23, emode, lmode, emodeocd, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(4 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
cal_en : std_logic_vector(7 downto 0);
cal_inc : std_logic_vector(7 downto 0);
cal_rst : std_logic;
readdly : std_logic_vector(1 downto 0);
twr : std_logic_vector(4 downto 0);
emr : std_logic_vector(1 downto 0); -- selects EM register
ocd : std_ulogic; -- enable/disable ocd
end record;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
end record;
-- local registers
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
write : std_logic_vector(3 downto 0);
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(1 downto 0);
acc : access_param;
sync : std_logic_vector(2 downto 1);
startsd_ack : std_logic;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
startsdold : std_ulogic;
hready : std_ulogic;
bdrive : std_ulogic;
qdrive : std_ulogic;
nbdrive : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
trfc : std_logic_vector(4 downto 0);
refresh : std_logic_vector(11 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(15 downto 0);
address : std_logic_vector(15 downto 2); -- memory address
ba : std_logic_vector( 1 downto 0);
waddr : std_logic_vector(abuf-1 downto 0);
waddr_d : std_logic_vector(abuf-1 downto 0); -- Same as waddr but delayed to compensate for pipelined output data
cfg : sdram_cfg_type;
hrdata : std_logic_vector(127 downto 0);
readdly : std_logic_vector(1 downto 0); -- added read latency
wdata : std_logic_vector(127 downto 0); -- pipeline register for output data
initnopdly : std_logic_vector(7 downto 0); -- 400 ns delay
sync : std_logic;
odt : std_logic_vector(1 downto 0);
end record;
signal vcc : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rdata, wdata : std_logic_vector(127 downto 0);
signal ddr_rst : std_logic;
signal ddr_rst_gen : std_logic_vector(3 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
vcc <= '1';
ddr_rst <= (ddr_rst_gen(3) and ddr_rst_gen(2) and ddr_rst_gen(1) and rst); -- Reset signal in DDR clock domain
ahb_ctrl : process(rst, ahbsi, r, ra, rdata)
variable v : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dout : std_logic_vector(31 downto 0);
variable ready : std_logic;
begin
v := ra; v.hresp := HRESP_OKAY; v.write := "0000";
case ra.raddr(1 downto 0) is
when "00" => v.hrdata := rdata(127 downto 96);
when "01" => v.hrdata := rdata(95 downto 64);
when "10" => v.hrdata := rdata(63 downto 32);
when others => v.hrdata := rdata(31 downto 0);
end case;
-- Sync ------------------------------------------------
v.sync(1) := r.startsdold; v.sync(2) := ra.sync(1);
ready := ra.startsd_ack xor ra.sync(2);
--------------------------------------------------------
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.htrans := ahbsi.htrans; v.haddr := ahbsi.haddr;
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
if ((v.hsel and v.htrans(1)) = '1') then
if v.hwrite = '0' then
v.state := rhold; v.startsd := not ra.startsd;
else
v.state := dwrite; v.hready := '1';
v.write := decode(v.haddr(3 downto 2));
end if;
end if;
v.raddr := ra.haddr(7 downto 2);
if ahbsi.hready = '1' then
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
when rhold =>
v.raddr := ra.haddr(7 downto 2);
if ready = '1' then
v.state := dread; v.hready := '1'; v.raddr := ra.raddr + 1;
end if;
when dread =>
v.raddr := ra.raddr + 1; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0')
or (ra.raddr(2 downto 0) = "000") then
v.state := midle; v.hready := '0';
v.startsd_ack := ra.startsd;
end if;
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
when dwrite =>
v.raddr := ra.haddr(7 downto 2); v.hready := '1';
v.write := decode(v.haddr(3 downto 2));
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0')
or (ra.haddr(4 downto 2) = "111") then
v.startsd := not ra.startsd; v.state := whold1;
v.write := "0000"; v.hready := '0';
end if;
when whold1 =>
v.state := whold2;
when whold2 =>
if ready = '1' then
v.state := midle; v.acc := (v.haddr, v.size, v.hwrite, v.hio);
v.startsd_ack := ra.startsd;
end if;
end case;
v.hwdata := ahbsi.hwdata;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
dout := ra.hrdata(31 downto 0);
if rst = '0' then
v.hsel := '0';
v.hready := '1';
v.state := midle;
v.startsd := '0';
v.startsd_ack := '0';
v.hio := '0';
end if;
rai <= v;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= dout;
ahbso.hcache <= not ra.hio;
end process;
ddr_ctrl : process(ddr_rst, r, ra, sdi, rbdrive, wdata)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dqm : std_logic_vector(15 downto 0);
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable writecfg : std_ulogic;
variable regsd1 : std_logic_vector(31 downto 0); -- data from registers
variable regsd2 : std_logic_vector(31 downto 0); -- data from registers
variable regsd3 : std_logic_vector(31 downto 0); -- data from registers
begin
-- Variable default settings to avoid latches
v := r; v.hready := '0'; writecfg := '0'; vbdrive := rbdrive;
v.hrdata := sdi.data; v.qdrive :='0';
v.cfg.cal_en := (others => '0'); v.cfg.cal_inc := (others => '0');
v.cfg.cal_rst := '0';
v.wdata := wdata; -- pipeline output data
regsd1 := (others => '0');
regsd1(31 downto 15) := r.cfg.refon & r.cfg.ocd & r.cfg.emr & '0' & r.cfg.trcd &
r.cfg.bsize & r.cfg.csize & r.cfg.command &
r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
regsd1(11 downto 0) := r.cfg.refresh;
regsd2 := (others => '0');
regsd2(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd2(14 downto 12) := conv_std_logic_vector(3, 3);
regsd3 := (others => '0');
regsd3(17 downto 16) := r.cfg.readdly;
regsd3(22 downto 18) := r.cfg.trfc;
regsd3(27 downto 23) := r.cfg.twr;
regsd3(28) := r.cfg.trp;
-- generate DQM from address and write size
case ra.acc.size is
when "00" =>
case ra.acc.haddr(3 downto 0) is
when "0000" => dqm := "0111111111111111";
when "0001" => dqm := "1011111111111111";
when "0010" => dqm := "1101111111111111";
when "0011" => dqm := "1110111111111111";
when "0100" => dqm := "1111011111111111";
when "0101" => dqm := "1111101111111111";
when "0110" => dqm := "1111110111111111";
when "0111" => dqm := "1111111011111111";
when "1000" => dqm := "1111111101111111";
when "1001" => dqm := "1111111110111111";
when "1010" => dqm := "1111111111011111";
when "1011" => dqm := "1111111111101111";
when "1100" => dqm := "1111111111110111";
when "1101" => dqm := "1111111111111011";
when "1110" => dqm := "1111111111111101";
when others => dqm := "1111111111111110";
end case;
when "01" =>
case ra.acc.haddr(3 downto 1) is
when "000" => dqm := "0011111111111111";
when "001" => dqm := "1100111111111111";
when "010" => dqm := "1111001111111111";
when "011" => dqm := "1111110011111111";
when "100" => dqm := "1111111100111111";
when "101" => dqm := "1111111111001111";
when "110" => dqm := "1111111111110011";
when others => dqm := "1111111111111100";
end case;
when others =>
dqm := "0000000000000000";
end case;
-- Sync ------------------------------------------
v.sync := ra.startsd; v.startsd := r.sync;
--------------------------------------------------
--v.startsd := ra.startsd;
---- main FSM
--
-- case r.mstate is
-- when midle =>
-- if r.startsd = '1' then
-- if (r.sdstate = sidle) and (r.cfg.command = "000")
-- and (r.cmstate = midle) then
-- startsd := '1'; v.mstate := active;
-- end if;
-- end if;
-- when others => null;
-- end case;
startsd := r.startsd xor r.startsdold;
-- generate row and column address size
haddr := ra.acc.haddr;
haddr(31 downto 20) := haddr(31 downto 20) and not conv_std_logic_vector(hmask, 12);
case r.cfg.csize is
when "00" => raddr := haddr(25 downto 12);
when "01" => raddr := haddr(26 downto 13);
when "10" => raddr := haddr(27 downto 14);
when others => raddr := haddr(28 downto 15);
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(29 downto 22)) &
genmux(r.cfg.bsize, haddr(28 downto 21));
-- generate chip select
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "00000" then v.trfc := r.trfc - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle)
and (r.istate = finish) then
v.address := raddr; v.ba := ba;
if ra.acc.hio = '0' then
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
else v.sdstate := ioreg1; end if;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act1 =>
v.rasn := '1'; v.trfc := r.cfg.trfc;
if r.cfg.trcd = '1' then v.sdstate := act2;
else v.sdstate := act3;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
v.waddr_d := ra.acc.haddr(7 downto 2);
when act2 =>
v.sdstate := act3;
when act3 =>
v.casn := '0';
v.address := ra.acc.haddr(15 downto 13) & '0' & ra.acc.haddr(12 downto 4) & '0';
v.hready := ra.acc.hwrite;
if ra.acc.hwrite = '1' then
v.sdstate := wr0;
v.sdwen := '0';
v.waddr := r.waddr + 4; v.waddr(1 downto 0) := "00"; -- inc address to memory, needed because data is pipelined
v.trfc := r.cfg.twr;
else v.sdstate := rd1; end if;
when wr0 =>
v.casn := '1'; v.sdwen := '1'; v.bdrive := '0'; v.qdrive := '1';
v.dqm := dqm;
v.waddr_d := r.waddr_d + 4; v.waddr_d(1 downto 0) := "00";
v.waddr := r.waddr + 4;
v.sdstate := wr1;
if (r.waddr_d /= ra.raddr) then v.hready := '1';
if (r.waddr_d(5 downto 2) = ra.raddr(5 downto 2)) then
if r.waddr_d(1) = '1' then v.dqm(15 downto 8) := (others => '1');
else
case ra.raddr(1 downto 0) is
when "01" => v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(3 downto 0) := (others => '1');
v.dqm(15 downto 12) := (others => r.waddr_d(0));
when others => v.dqm(15 downto 12) := (others => r.waddr_d(0));
end case;
end if;
else
case r.waddr_d(1 downto 0) is
when "01" => v.dqm(15 downto 12) := (others => '1');
when "10" => v.dqm(15 downto 8) := (others => '1');
when "11" => v.dqm(15 downto 4) := (others => '1');
when others => null;
end case;
end if;
else
case r.waddr_d(1 downto 0) is
when "00" => v.dqm(11 downto 0) := (others => '1');
when "01" => v.dqm(15 downto 12) := (others => '1'); v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(15 downto 8) := (others => '1'); v.dqm(3 downto 0) := (others => '1');
when others => v.dqm(15 downto 4) := (others => '1');
end case;
end if;
when wr1 =>
v.sdwen := '1'; v.casn := '1'; v.qdrive := '1';
v.waddr_d := r.waddr_d + 4; v.dqm := (others => '0');
v.waddr := r.waddr + 4;
v.address(8 downto 3) := r.waddr_d;
if (r.waddr_d <= ra.raddr) and (r.waddr_d(5 downto 2) /= "0000") and (r.hready = '1') then
v.hready := '1';
if (r.hready = '1') and (r.waddr_d(2 downto 0) = "000") then
v.sdwen := '0'; v.casn := '0';
end if;
if (r.waddr_d(5 downto 2) = ra.raddr(5 downto 2)) and (r.waddr_d /= "000000") then
case ra.raddr(1 downto 0) is
when "00" => v.dqm(11 downto 0) := (others => '1');
when "01" => v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(3 downto 0) := (others => '1');
when others => null;
end case;
end if;
else
v.sdstate := wr2;
v.dqm := (others => '1');
v.startsdold := r.startsd;
end if;
when wr2 =>
v.sdstate := wr3; v.qdrive := '1';
when wr3 =>
v.sdstate := wr4a; v.qdrive := '1';
when wr4a =>
v.bdrive := '1'; v.qdrive := '1';
if r.trfc <= "00000" then -- wait to not violate TWR timing
v.sdstate := wr4b;
end if;
when wr4b =>
v.bdrive := '1';
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; v.qdrive := '1';
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.qdrive := '0';
v.sdstate := wr5;
when wr5 =>
v.sdstate := sidle;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
when rd7 =>
v.casn := '1'; v.sdstate := rd8;
v.readdly := r.cfg.readdly;
when rd8 => -- (CL = 3)
v.casn := '1';
if r.readdly = "00" then -- add read delay
v.sdstate := rd2;
else
v.readdly := r.readdly - 1;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if fast = 0 then v.startsdold := r.startsd; end if;
if v.hready = '1' then v.waddr := r.waddr + 4; end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (r.sdcsn = "11") or (r.waddr(2 downto 2) = "1") then
v.dqm := (others => '1');
if fast /= 0 then v.startsdold := r.startsd; end if;
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
end if;
end if;
if v.hready = '1' then v.waddr := r.waddr + 4; end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
when rd6 =>
v.sdstate := sidle; v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when ioreg1 =>
v.hrdata(127 downto 32) := regsd1 & regsd2 & regsd3; v.sdstate := ioreg2;
if ra.acc.hwrite = '0' then v.hready := '1'; end if;
when ioreg2 =>
writecfg := ra.acc.hwrite; v.startsdold := r.startsd;
v.sdstate := sidle;
when others =>
v.sdstate := sidle;
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when CMD_PRE => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when CMD_REF => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when CMD_EMR => -- load-ext-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := r.cfg.emr; --v.ba select EM register;
--v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd&"0000000";
if r.cfg.emr = "01" then
v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd
& odtvalue(1)&"000"&odtvalue(0)&"00";
else
v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd&"0000000";
end if;
when CMD_LMR => -- load-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "00";
v.address := "00010" & r.cfg.dllrst & "0" & "01" & "10010"; -- CAS = 3 WR = 3
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; v.cfg.command := "000";
v.cmstate := leadout; v.trfc := r.cfg.trfc;
when others =>
if r.trfc = "00000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
if r.cfg.renable = '1' then
v.cfg.cke := '1'; v.cfg.dllrst := '1';
v.ba := "00"; v.cfg.ocd := '0'; v.cfg.emr := "10"; -- EMR(2)
if r.cfg.cke = '1' then
if r.initnopdly = "00000000" then -- 400 ns of NOP and CKE
v.istate := pre; v.cfg.command := CMD_PRE;
else
v.initnopdly := r.initnopdly - 1;
end if;
end if;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "11" & r.cfg.dllrst; -- CMD_LMR/CMD_EMR
if r.cfg.dllrst = '1' then v.istate := emode23; else v.istate := lmode; end if;
end if;
when emode23 =>
if r.cfg.command = "000" then
if r.cfg.emr = "11" then
v.cfg.emr := "01"; -- (EMR(1))
v.istate := emode; v.cfg.command := CMD_EMR;
else
v.cfg.emr := "11"; v.cfg.command := CMD_EMR; -- EMR(3)
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := lmode; v.cfg.command := CMD_LMR;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.dllrst = '1' then
if r.refresh(9 downto 8) = "00" then -- > 200 clocks delay
v.cfg.command := CMD_PRE; v.istate := ref1;
end if;
else
v.istate := emodeocd;
v.cfg.ocd := '1'; v.cfg.command := CMD_EMR;
end if;
end if;
when ref1 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.cfg.dllrst := '0'; v.istate := ref2;
end if;
when ref2 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.istate := pre;
end if;
when emodeocd =>
if r.cfg.command = "000" then
if r.cfg.ocd = '0' then -- Exit OCD
v.istate := finish;
v.cfg.refon := '1'; v.cfg.renable := '0';
else -- Default OCD
v.cfg.ocd := '0';
v.cfg.command := CMD_EMR;
end if;
end if;
v.cfg.cal_rst := '1'; -- reset data bit delay
when others =>
if odten /= 0 then v.odt := (others => '1'); end if;
if r.cfg.renable = '1' then
v.istate := iidle; v.cfg.dllrst := '1';
v.initnopdly := (others => '1');
v.odt := (others => '0');
end if;
end case;
---- second part of main fsm
--
-- case r.mstate is
-- when active =>
-- if v.hready = '1' then
-- v.mstate := midle;
-- end if;
-- when others => null;
-- end case;
-- sdram refresh counter
if ((r.cfg.refon = '1') and (r.istate = finish)) or (r.cfg.dllrst = '1') then
v.refresh := r.refresh - 1;
if (v.refresh(11) and not r.refresh(11)) = '1' then
v.refresh := r.cfg.refresh;
if r.cfg.dllrst = '0' then v.cfg.command := "100"; end if;
end if;
end if;
-- AHB register access
if (ra.acc.hio and ra.acc.hwrite and writecfg) = '1' then
if r.waddr(1 downto 0) = "00" then
v.cfg.refresh := r.wdata(11+96 downto 0+96);
v.cfg.cke := r.wdata(15+96);
v.cfg.renable := r.wdata(16+96);
v.cfg.dllrst := r.wdata(17+96);
v.cfg.command := r.wdata(20+96 downto 18+96);
v.cfg.csize := r.wdata(22+96 downto 21+96);
v.cfg.bsize := r.wdata(25+96 downto 23+96);
v.cfg.trcd := r.wdata(26+96);
v.cfg.emr := r.wdata(29+96 downto 28+96);
v.cfg.ocd := r.wdata(30+96);
v.cfg.refon := r.wdata(31+96);
elsif r.waddr(1 downto 0) = "10" then
v.cfg.cal_en := r.wdata( 7+32 downto 0+32);
v.cfg.cal_inc := r.wdata(15+32 downto 8+32);
v.cfg.readdly := r.wdata(17+32 downto 16+32);
v.cfg.trfc := r.wdata(22+32 downto 18+32);
v.cfg.twr := r.wdata(27+32 downto 23+32);
v.cfg.trp := r.wdata(28+32);
v.cfg.cal_rst := r.wdata(31+32);
end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if ddr_rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := finish;
v.cmstate := midle;
v.cfg.command := "000";
v.cfg.csize := conv_std_logic_vector(col-9, 2);
v.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
v.cfg.refon := '0';
v.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 5);
v.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
v.cfg.twr := conv_std_logic_vector((15)*MHz/1000+3, 5);
v.refresh := (others => '0');
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '0';
v.startsd := '0';
v.startsdold := '0';
v.cfg.dllrst := '0';
v.cfg.cke := '0';
v.cfg.ocd := '0';
v.cfg.readdly := conv_std_logic_vector(readdly, 2);
v.initnopdly := (others => '1');
if MHz > 130 then v.cfg.trcd := '1'; else v.cfg.trcd := '0'; end if;
if MHz > 130 then v.cfg.trp := '1'; else v.cfg.trp := '0'; end if;
if pwron = 1 then v.cfg.renable := '1';
else v.cfg.renable := '0'; end if;
v.odt := (others => '0');
end if;
ri <= v;
ribdrive <= vbdrive;
end process;
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbregs : process(clk_ahb) begin
if rising_edge(clk_ahb) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr, rst, ddr_rst) begin
if rising_edge(clk_ddr) then
r <= ri; rbdrive <= ribdrive;
ddr_rst_gen <= ddr_rst_gen(2 downto 0) & '1';
end if;
if (rst = '0') then
ddr_rst_gen <= "0000";
end if;
if (ddr_rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
r.cfg.cke <= '0';
end if;
end process;
sdo.address <= '0' & ri.address;
sdo.ba <= ri.ba;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.qdrive <= not (ri.qdrive or r.nbdrive);
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= ri.sdcsn;
sdo.sdwen <= ri.sdwen;
sdo.dqm <= r.dqm;
sdo.rasn <= ri.rasn;
sdo.casn <= ri.casn;
--sdo.data <= wdata;
sdo.data <= r.wdata; -- data pipelined
sdo.cal_en <= r.cfg.cal_en;
sdo.cal_inc <= r.cfg.cal_inc;
sdo.cal_rst <= r.cfg.cal_rst;
sdo.odt <= r.odt;
read_buff : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 128, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rai.raddr(5 downto 2),
dataout => rdata, wclk => clk_ddr, write => ri.hready,
waddress => r.waddr(5 downto 2), datain => ri.hrdata);
write_buff1 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(127 downto 96), wclk => clk_ahb, write => ra.write(0),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff2 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(95 downto 64), wclk => clk_ahb, write => ra.write(1),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff3 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(63 downto 32), wclk => clk_ahb, write => ra.write(2),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff4 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(31 downto 0), wclk => clk_ahb, write => ra.write(3),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddr2sp" & tost(hindex) & ": 64-bit DDR2 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:11:17 07/07/2014
-- Design Name:
-- Module Name: /home/qfi/Documents/aeshw/aes-core/aes-core/key_expander_tb.vhd
-- Project Name: aes-core
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: key_expander
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.types.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
entity key_expander_tb is
end key_expander_tb;
architecture behavior of key_expander_tb is
-- Component Declaration for the Unit Under Test (UUT)
component key_expander
port(
clk : in std_logic;
reset : in std_logic;
y : in std_logic_vector(1 downto 0);
rcon_in : in byte;
key_in : in state;
key_out : out state
);
end component;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal y : std_logic_vector(1 downto 0) := "00";
signal rcon_in : byte := (others => '0');
signal key_in : state;
--Outputs
signal key_out : state;
-- Clock period definitions
constant clk_period : time := 10 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut: key_expander port map (
clk => clk,
reset => reset,
y => y,
rcon_in => rcon_in,
key_in => key_in,
key_out => key_out
);
-- clock process definitions
clk_process :process
begin
for i in 0 to 10 loop
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end loop;
wait;
end process;
-- stimulus process
stim_proc: process
begin
-- load initial key into the registers
y <= "00"; -- load new key
key_in <= x"2b7e151628aed2a6abf7158809cf4f3c";
wait for 10 ns;
-- key loaded
y <= "01"; -- feed register with previous values passed through expansion-SN
-- round 1
rcon_in <= x"01";
wait for 10 ns;
assert key_out = x"a0fafe1788542cb123a339392a6c7605" report "key expension round(1) : failure" severity failure;
-- round 2 (use key_out of round 1)
rcon_in <= x"02";
wait for 10 ns;
assert key_out = x"f2c295f27a96b9435935807a7359f67f" report "key expension round(2) : failure" severity failure;
wait;
end process;
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 01:52:06 04/10/2009
-- Design Name:
-- Module Name: Comp_4bitRegister - Behavioral
-- Project Name: 4-bit Register
-- Target Devices:
-- Tool versions:
-- Description: A four-bit register made from D flip-flops. No reset.
--
-- Dependencies: Comp_Dflipflop.vhd, Gate_Nand.vhd, Gate_Inv.chd, Gate_Buf.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Comp_4bitRegister is
Port ( D1 : in STD_LOGIC;
D2 : in STD_LOGIC;
D3 : in STD_LOGIC;
D4 : in STD_LOGIC;
CLK : in STD_LOGIC;
Q1 : out STD_LOGIC;
Q2 : out STD_LOGIC;
Q3 : out STD_LOGIC;
Q4 : out STD_LOGIC);
end Comp_4bitRegister;
architecture Behavioral of Comp_4bitRegister is
component Comp_Dflipflop is
Port ( D : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC;
NQ : out STD_LOGIC);
end component;
begin
G1: Comp_Dflipflop port map (D1, CLK, Q1);
G2: Comp_Dflipflop port map (D2, CLK, Q2);
G3: Comp_Dflipflop port map (D3, CLK, Q3);
G4: Comp_Dflipflop port map (D4, CLK, Q4);
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: tb_pack-p.vhd,v 1.2 2005-03-08 22:06:39 arniml Exp $
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package tb_pack is
function calc_crc(payload : in std_logic_vector) return std_logic_vector;
function calc_crc(payload : in unsigned) return unsigned;
function to_string(value : in integer) return string;
end tb_pack;
package body tb_pack is
function calc_crc(payload : in std_logic_vector) return std_logic_vector is
variable crc_v : std_logic_vector(6 downto 0);
variable temp_v : std_logic;
begin
crc_v := (others => '0');
for i in payload'high downto payload'low loop
temp_v := payload(i) xor crc_v(6);
crc_v(6 downto 4) := crc_v(5 downto 3);
crc_v(3) := crc_v(2) xor temp_v;
crc_v(2 downto 1) := crc_v(1 downto 0);
crc_v(0) := temp_v;
end loop;
return crc_v;
end calc_crc;
function calc_crc(payload : in unsigned) return unsigned is
begin
return unsigned(calc_crc(std_logic_vector(payload)));
end calc_crc;
function to_string(value : in integer) return string is
variable str: string (11 downto 1);
variable val: integer := value;
variable digit: natural;
variable index: natural := 0;
begin
-- Taken from:
-- textio package body. This file is part of GHDL.
-- Copyright (C) 2002 Tristan Gingold.
-- Note: the absolute value of VAL cannot be directly taken, since
-- it may be greather that the maximum value of an INTEGER.
loop
-- LRM93 7.2.6
-- (A rem B) has the sign of A and an absolute value less then
-- the absoulte value of B.
digit := abs (val rem 10);
val := val / 10;
index := index + 1;
str (index) := character'val(48 + digit);
exit when val = 0;
end loop;
if value < 0 then
index := index + 1;
str(index) := '-';
end if;
return str;
end to_string;
end tb_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2005/02/08 21:09:20 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1678.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p08n01i01678ent IS
END c09s01b00x00p08n01i01678ent;
ARCHITECTURE c09s01b00x00p08n01i01678arch OF c09s01b00x00p08n01i01678ent IS
signal S2 : integer := 2;
BEGIN
B: block
generic ( G1 : INTEGER;
G2 : STRING);
generic map ( G1 => 10,
G2 => "Hi");
port ( P1 : INTEGER);
port map ( P1 => S2);
begin
assert NOT( G1 = 10 and G2 = "Hi" and P1 = 2 )
report "***PASSED TEST: c09s01b00x00p08n01i01678"
severity NOTE;
assert ( G1 = 10 and G2 = "Hi" and P1 = 2 )
report "***FAILED TEST: c09s01b00x00p08n01i01678 - Certain values do not be imported from the enclosing enviornment into the block."
severity ERROR;
end block;
END c09s01b00x00p08n01i01678arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1678.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p08n01i01678ent IS
END c09s01b00x00p08n01i01678ent;
ARCHITECTURE c09s01b00x00p08n01i01678arch OF c09s01b00x00p08n01i01678ent IS
signal S2 : integer := 2;
BEGIN
B: block
generic ( G1 : INTEGER;
G2 : STRING);
generic map ( G1 => 10,
G2 => "Hi");
port ( P1 : INTEGER);
port map ( P1 => S2);
begin
assert NOT( G1 = 10 and G2 = "Hi" and P1 = 2 )
report "***PASSED TEST: c09s01b00x00p08n01i01678"
severity NOTE;
assert ( G1 = 10 and G2 = "Hi" and P1 = 2 )
report "***FAILED TEST: c09s01b00x00p08n01i01678 - Certain values do not be imported from the enclosing enviornment into the block."
severity ERROR;
end block;
END c09s01b00x00p08n01i01678arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1678.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p08n01i01678ent IS
END c09s01b00x00p08n01i01678ent;
ARCHITECTURE c09s01b00x00p08n01i01678arch OF c09s01b00x00p08n01i01678ent IS
signal S2 : integer := 2;
BEGIN
B: block
generic ( G1 : INTEGER;
G2 : STRING);
generic map ( G1 => 10,
G2 => "Hi");
port ( P1 : INTEGER);
port map ( P1 => S2);
begin
assert NOT( G1 = 10 and G2 = "Hi" and P1 = 2 )
report "***PASSED TEST: c09s01b00x00p08n01i01678"
severity NOTE;
assert ( G1 = 10 and G2 = "Hi" and P1 = 2 )
report "***FAILED TEST: c09s01b00x00p08n01i01678 - Certain values do not be imported from the enclosing enviornment into the block."
severity ERROR;
end block;
END c09s01b00x00p08n01i01678arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1483.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p04n03i01483ent IS
END c08s08b00x00p04n03i01483ent;
ARCHITECTURE c08s08b00x00p04n03i01483arch OF c08s08b00x00p04n03i01483ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable i : integer := 2;
BEGIN
case i is
when 1 | 2 => k := 5;
when others => NULL;
end case;
assert NOT( k = 5 )
report "***PASSED TEST: c08s08b00x00p04n03i01483"
severity NOTE;
assert ( k = 5 )
report "***FAILED TEST: c08s08b00x00p04n03i01483 - one alternative can consist of serveral choices"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p04n03i01483arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1483.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p04n03i01483ent IS
END c08s08b00x00p04n03i01483ent;
ARCHITECTURE c08s08b00x00p04n03i01483arch OF c08s08b00x00p04n03i01483ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable i : integer := 2;
BEGIN
case i is
when 1 | 2 => k := 5;
when others => NULL;
end case;
assert NOT( k = 5 )
report "***PASSED TEST: c08s08b00x00p04n03i01483"
severity NOTE;
assert ( k = 5 )
report "***FAILED TEST: c08s08b00x00p04n03i01483 - one alternative can consist of serveral choices"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p04n03i01483arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1483.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p04n03i01483ent IS
END c08s08b00x00p04n03i01483ent;
ARCHITECTURE c08s08b00x00p04n03i01483arch OF c08s08b00x00p04n03i01483ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable i : integer := 2;
BEGIN
case i is
when 1 | 2 => k := 5;
when others => NULL;
end case;
assert NOT( k = 5 )
report "***PASSED TEST: c08s08b00x00p04n03i01483"
severity NOTE;
assert ( k = 5 )
report "***FAILED TEST: c08s08b00x00p04n03i01483 - one alternative can consist of serveral choices"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p04n03i01483arch;
|
-------------------------------------------------------------------------------
--
-- Module : ll_fifo_tb.vhd
--
-- Version : 1.2
--
-- Last Update : 2005-06-29
--
-- Project : Parameterizable LocalLink FIFO
--
-- Description : Testbench of LocalLink FIFO
--
-- Designer : Wen Ying Wei, Davy Huang
--
-- Company : Xilinx, Inc.
--
-- Disclaimer : XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2005 Xilinx, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- Testbench Block Diagram:
--
--
-- +---------+ +---------+
-- | | | |
-- | Tester | ==> | Egress | ====+
-- | (TX) | | LL_FIFO | |
-- | | | | +----------+
-- +---------+ +---------+ |Pipeline/ |
-- +---------+ +---------+ |Throttle |
-- | | | | +----------+
-- | Tester | <== | Ingress | |
-- | (RX) | | LL_FIFO |<====+
-- | | | |
-- +---------+ +---------+
-- ^ ^
-- | |
-- TESTER I/F LOOPBACK I/F
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.TESTER_pkg.all;
use work.ll_fifo_pkg.all;
entity ll_fifo_tb is
generic (
-- Set memory type and depth
MEM_TYPE : integer :=0; -- Select memory type(0: BRAM, 1: Distributed RAM)
BRAM_MACRO_NUM : integer :=16; -- Set memory depth if use BRAM
DRAM_DEPTH : integer :=16; -- Set memory depth if use Distributed RAM
-- Set clock rate, data width at the tester interface
TESTER_CLK_HALF_PERIOD : time :=12.50 ns; -- Set Tester clock speed
TESTER_DWIDTH : integer :=64; -- Set Tester data width:8, 16, 32, 64, 128
TESTER_REM_WIDTH : integer :=3; -- Set Tester remainder width:1, 1, 2, 3, 4
TESTER_REM_VECTOR_WIDTH : integer :=3; -- Set rem width in test vector file
-- Use 3 if TESTER_DWIDTH <= 64
-- Use 7 if TESTER_DWIDTH = 128
TESTER_FIFO_DEPTH : integer :=8192; -- Set Tester FIFO depth (FIFO to buffer the traffic data)
-- Set clock rate, data width at the loopback interface
LOOPBACK_CLK_HALF_PERIOD: time :=12.50 ns; -- Set Loopback clock speed
LOOPBACK_DWIDTH : integer :=8; -- Set Tester data width:8, 16, 32, 64, 128
LOOPBACK_REM_WIDTH : integer :=1; -- Set Loopback remainder width:1, 1, 2, 3, 4
-- Other LocalLink FIFO options
EGRESS_USE_LENGTH : boolean :=true; -- Set if use Length Option on Egress FIFO
INGRESS_USE_LENGTH : boolean :=true; -- Set if use Length Option on Ingress FIFO
-- Global timing delay
glbtm : time :=0.5 ns );-- Set global timing delay
end ll_fifo_tb;
architecture ll_fifo_tb_arch of ll_fifo_tb is
signal rst : std_logic;
signal tester_clk : std_logic;
-- Loopback Interface signals
signal loopback_clk : std_logic;
signal Eloopback_data : std_logic_vector(0 to LOOPBACK_DWIDTH-1);
signal Eloopback_rem : std_logic_vector(0 to LOOPBACK_REM_WIDTH-1);
signal Eloopback_sof_n : std_logic;
signal Eloopback_eof_n : std_logic;
signal Eloopback_src_rdy_n : std_logic;
signal Eloopback_dst_rdy_n : std_logic;
signal Iloopback_data : std_logic_vector(0 to LOOPBACK_DWIDTH-1);
signal Iloopback_rem : std_logic_vector(0 to LOOPBACK_REM_WIDTH-1);
signal Iloopback_sof_n : std_logic;
signal Iloopback_eof_n : std_logic;
signal Iloopback_src_rdy_n : std_logic;
signal Iloopback_dst_rdy_n : std_logic;
signal loopback_throttle_cnt : std_logic_vector(10 downto 0);
signal loopback_throttle_th : std_logic_vector(13 downto 0);
signal loopback_throttle : std_logic;
signal Sloopback : std_logic;
-- Tester interface signals
signal tx_d : std_logic_vector(0 to TESTER_DWIDTH-1);
signal tx_rem : std_logic_vector(0 to TESTER_REM_WIDTH-1);
signal tx_sof_n : std_logic;
signal tx_eof_n : std_logic;
signal tx_src_rdy_n : std_logic;
signal tx_dst_rdy_n : std_logic;
signal tx_dst_rdy_n_i : std_logic;
signal rx_d : std_logic_vector(0 to TESTER_DWIDTH-1);
signal rx_rem : std_logic_vector(0 to TESTER_REM_WIDTH-1);
signal rx_sof_n : std_logic;
signal rx_eof_n : std_logic;
signal rx_src_rdy_n : std_logic;
-- Other LocalLink FIFO signals
signal egress_fifostatus : std_logic_vector(0 to 3);
signal egress_len_rdy_out: std_logic;
signal egress_len_out: std_logic_vector(15 downto 0);
signal egress_len_err_out: std_logic;
signal ingress_fifostatus : std_logic_vector(0 to 3);
signal ingress_len_rdy_out: std_logic;
signal ingress_len_out: std_logic_vector(15 downto 0);
signal ingress_len_err_out: std_logic;
--Reference Signals
signal src_rdy_n_ref_i : std_logic;
-- Tester signals
signal WORKING: std_logic;
signal COMPARING: std_logic;
signal OVERFLOW: std_logic;
signal RESULT_GOOD: std_logic;
signal RESULT_GOOD_PDU: std_logic;
signal TV: std_logic_vector(0 to 7);
-- Other signals
signal GND: std_logic;
signal VCC: std_logic;
signal ufc_rx_d : std_logic_vector(0 to TESTER_DWIDTH-1);
signal ufc_rx_rem : std_logic_vector(0 to TESTER_REM_WIDTH-1);
begin
GND <= '0';
VCC <= '1';
ufc_rx_d <= (others => '0');
ufc_rx_rem <= (others => '0');
TV(0) <= not rst; -- first test vector is reset
TV(1) <= not tx_dst_rdy_n;
tx_dst_rdy_n <= tx_dst_rdy_n_i when tx_src_rdy_n = '0'
else '1' when egress_fifostatus >= "0000" and loopback_throttle_th(11 downto 9) = "111" and loopback_throttle_th(4) = '1'
else tx_dst_rdy_n_i;
-- second test vector is the destination ready signal
-- from the Egress FIFO to the Tester
TV(2 to 7) <= (others => '0'); -- other test vectors not used
---------------------------------------------------------------------------
-- Instantiate the DUT : Egress FIFO and Ingress FIFO
---------------------------------------------------------------------------
Egress_FIFO: ll_fifo
generic map (
MEM_TYPE => MEM_TYPE,
BRAM_MACRO_NUM => BRAM_MACRO_NUM,
DRAM_DEPTH => DRAM_DEPTH,
WR_DWIDTH => TESTER_DWIDTH,
WR_REM_WIDTH => TESTER_REM_WIDTH,
RD_DWIDTH => LOOPBACK_DWIDTH,
RD_REM_WIDTH => LOOPBACK_REM_WIDTH,
USE_LENGTH => EGRESS_USE_LENGTH,
glbtm => glbtm )
port map (
-- Reset
areset_in => rst,
-- clocks
write_clock_in => tester_clk,
read_clock_in => loopback_clk,
-- Tester Interface
data_in => tx_d,
rem_in => tx_rem,
sof_in_n => tx_sof_n,
eof_in_n => tx_eof_n,
src_rdy_in_n => tx_src_rdy_n,
dst_rdy_out_n => tx_dst_rdy_n_i,
-- Loopback Interface
data_out => Eloopback_data,
rem_out => Eloopback_rem,
sof_out_n => Eloopback_sof_n,
eof_out_n => Eloopback_eof_n,
src_rdy_out_n => Eloopback_src_rdy_n,
dst_rdy_in_n => Eloopback_dst_rdy_n,
-- FIFO status signals
fifostatus_out => egress_fifostatus,
-- Length Status
len_rdy_out => egress_len_rdy_out,
len_out => egress_len_out,
len_err_out => egress_len_err_out);
Ingress_FIFO: ll_fifo
generic map (
MEM_TYPE => MEM_TYPE,
BRAM_MACRO_NUM => BRAM_MACRO_NUM,
DRAM_DEPTH => DRAM_DEPTH,
WR_DWIDTH => LOOPBACK_DWIDTH,
WR_REM_WIDTH => LOOPBACK_REM_WIDTH,
RD_DWIDTH => TESTER_DWIDTH,
RD_REM_WIDTH => TESTER_REM_WIDTH,
USE_LENGTH => INGRESS_USE_LENGTH,
glbtm => glbtm )
port map (
-- Reset
areset_in => rst,
-- clocks
write_clock_in => loopback_clk,
read_clock_in => tester_clk,
-- Loopback Interface
data_in => Iloopback_data,
rem_in => Iloopback_rem,
sof_in_n => Iloopback_sof_n,
eof_in_n => Iloopback_eof_n,
src_rdy_in_n => Iloopback_src_rdy_n,
dst_rdy_out_n => Iloopback_dst_rdy_n,
-- Tester Interface
data_out => rx_d,
rem_out => rx_rem,
sof_out_n => rx_sof_n,
eof_out_n => rx_eof_n,
src_rdy_out_n => rx_src_rdy_n,
dst_rdy_in_n => GND, -- Tester always ready to accept data
-- FIFO status signals
fifostatus_out => ingress_fifostatus,
-- Length Status
len_rdy_out => ingress_len_rdy_out,
len_out => ingress_len_out,
len_err_out => ingress_len_err_out);
---------------------------------------------------------------------------
-- Loopback I/F
---------------------------------------------------------------------------
loopback_throttle_cnt_proc: process (rst, loopback_clk)
begin
if rst = '1' then
loopback_throttle_cnt <= (others => '0') after glbtm;
elsif loopback_clk'event and loopback_clk = '1' then
if loopback_throttle_cnt = loopback_throttle_th(13 downto 3) then
loopback_throttle_cnt <= (others => '0') after glbtm;
else
loopback_throttle_cnt <= loopback_throttle_cnt + 1 after glbtm;
end if;
end if;
end process;
loopback_throttle_proc : process (rst, loopback_clk)
begin
if rst = '1' then
loopback_throttle <= '0' after glbtm;
loopback_throttle_th <= "00011000000000" after glbtm;
elsif loopback_clk'event and loopback_clk = '1' then
if loopback_throttle_cnt = loopback_throttle_th(13 downto 3) then
loopback_throttle <= not loopback_throttle after glbtm;
end if;
if loopback_throttle_cnt = loopback_throttle_th(13 downto 3) and loopback_throttle = '0' then
loopback_throttle_th <= loopback_throttle_th - 73 after glbtm;
end if;
end if;
end process;
loopback_if_proc: process (rst, loopback_clk)
begin
if rst = '1' then
Iloopback_data <= (others => '0') after glbtm;
Iloopback_rem <= (others => '0') after glbtm;
Iloopback_sof_n <= '1' after glbtm;
Iloopback_eof_n <= '1' after glbtm;
Iloopback_src_rdy_n <= '1' after glbtm;
Eloopback_dst_rdy_n <= '1' after glbtm;
Sloopback <= '0' after glbtm;
elsif loopback_clk'event and loopback_clk = '1' then
if Iloopback_dst_rdy_n = '1' and Sloopback = '1' then -- Ingress FIFO not ready, storage is occupied
-- latch the data, do nothing else
else
Iloopback_data <= Eloopback_data after glbtm;
Iloopback_rem <= Eloopback_rem after glbtm;
Iloopback_sof_n <= Eloopback_sof_n after glbtm;
Iloopback_eof_n <= Eloopback_eof_n after glbtm;
Iloopback_src_rdy_n <= Eloopback_src_rdy_n or Eloopback_dst_rdy_n after glbtm;
Sloopback <= not (Eloopback_src_rdy_n or Eloopback_dst_rdy_n) after glbtm;
end if;
if loopback_throttle = '0' then
Eloopback_dst_rdy_n <= Iloopback_dst_rdy_n or Sloopback after glbtm; -- hold off Egress FIFO when
-- there's data in the storage.
else
Eloopback_dst_rdy_n <= '1' after glbtm;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Instantiate the Tester TX: FILEREAD_TESTER
---------------------------------------------------------------------------
src_rdy_n_ref_i <= not (not tx_src_rdy_n and not tx_dst_rdy_n);
fileread_tester_i: FILEREAD_TESTER
generic map
( GLOBALDLY => 1,
TV_WIDTH => 8,
CV_WIDTH => 4,
LL_DAT_BIT_WIDTH => TESTER_DWIDTH,
LL_REM_BIT_WIDTH => TESTER_REM_WIDTH,
REM_VECTOR_WIDTH => TESTER_REM_VECTOR_WIDTH)
port map
(
--Global Signals
CLK => tester_clk,
TV => TV,
--LocalLink Interface
TX_SOF_N => tx_sof_n, --O
TX_EOF_N => tx_eof_n, --O
TX_D => tx_d, --O
TX_REM => tx_rem, --O
TX_SRC_RDY_N => tx_src_rdy_n, --O
--Native Flow Control Interface (Not used)
NFC_NB => open, --O
NFC_REQ_N => open, --O
--User Flow Control Interface (Not used)
UFC_TX_REQ_N => open, --O
UFC_TX_MS => open, --O
--Other User Signals
CTRL => open
);
---------------------------------------------------------------------------
-- Instantiate the Tester RX: OUTPUT_TESTER
---------------------------------------------------------------------------
err_det_proc: process (rst, tester_clk)
begin
if rst = '1' then
elsif tester_clk'event and tester_clk = '1' then
assert (RESULT_GOOD = '1' or OVERFLOW = '1' )
report "ERROR DETECTED!" severity Error;
assert (OVERFLOW = '0')
report "TESTER OVERFLOW DETECTED!" severity Error;
end if;
end process;
DW_Sel_gen1: if TESTER_DWIDTH > 8 generate
output_tester_i: OUTPUT_TESTER
generic map
( GLOBALDLY => 1,
LL_DAT_BIT_WIDTH => TESTER_DWIDTH,
LL_REM_BIT_WIDTH => TESTER_REM_WIDTH,
FIFO_DEPTH => TESTER_FIFO_DEPTH)
port map
(
CLK => tester_clk, --I
RST => rst, --I
--Dut LocalLink Interface
RX_D => rx_d, --I --0:63
RX_REM => rx_rem, --I --0:2
RX_SOF_N => rx_sof_n, --I
RX_EOF_N => rx_eof_n, --I
RX_SRC_RDY_N => rx_src_rdy_n, --I
--Dut UFC Interface (not used)
UFC_RX_DATA => ufc_rx_d, --I
UFC_RX_REM => ufc_rx_rem, --I
UFC_RX_SOF_N => VCC, --I
UFC_RX_EOF_N => VCC, --I
UFC_RX_SRC_RDY_N => VCC, --I
--Reference LocalLink Interface
RX_SOF_N_REF => tx_sof_n, --I
RX_EOF_N_REF => tx_eof_n, --I
RX_REM_REF => tx_rem, --I
RX_DATA_REF => tx_d, --I
RX_SRC_RDY_N_REF => src_rdy_n_ref_i, --I
--Reference UFC Interface (not used)
UFC_RX_DATA_REF => ufc_rx_d, --I
UFC_RX_REM_REF => ufc_rx_rem, --I
UFC_RX_SOF_N_REF => VCC, --I
UFC_RX_EOF_N_REF => VCC, --I
UFC_RX_SRC_RDY_N_REF => VCC, --I
--Comparison result
WORKING => WORKING, --O
COMPARING => COMPARING,
OVERFLOW => OVERFLOW,
RESULT_GOOD => RESULT_GOOD, --O
RESULT_GOOD_PDU => RESULT_GOOD_PDU, --O
RESULT_GOOD_UFC => open --O
);
end generate DW_Sel_gen1;
DW_Sel_gen2: if TESTER_DWIDTH = 8 generate
output_tester_i: OUTPUT_TESTER_8_BIT
generic map
( GLOBALDLY => 1,
LL_DAT_BIT_WIDTH => TESTER_DWIDTH,
LL_REM_BIT_WIDTH => 0,
FIFO_DEPTH => TESTER_FIFO_DEPTH)
port map
(
CLK => tester_clk, --I
RST => rst, --I
--Dut LocalLink Interface
RX_D => rx_d, --I --0:63
RX_REM => rx_rem(0), --I --0:2
RX_SOF_N => rx_sof_n, --I
RX_EOF_N => rx_eof_n, --I
RX_SRC_RDY_N => rx_src_rdy_n, --I
--Dut UFC Interface (to tie)
UFC_RX_DATA => ufc_rx_d, --I
UFC_RX_REM => ufc_rx_rem(0), --I
UFC_RX_SOF_N => VCC, --I
UFC_RX_EOF_N => VCC, --I
UFC_RX_SRC_RDY_N => VCC, --I
--Reference LocalLink Interface (don't touch)
RX_SOF_N_REF => tx_sof_n, --I
RX_EOF_N_REF => tx_eof_n, --I
RX_REM_REF => tx_rem(0), --I
RX_DATA_REF => tx_d, --I
RX_SRC_RDY_N_REF => src_rdy_n_ref_i, --I
--Reference UFC Interface (to tie)
UFC_RX_DATA_REF => ufc_rx_d, --I
UFC_RX_REM_REF => ufc_rx_rem(0), --I
UFC_RX_SOF_N_REF => VCC, --I
UFC_RX_EOF_N_REF => VCC, --I
UFC_RX_SRC_RDY_N_REF => VCC, --I
--Comparison result
WORKING => WORKING, --O
COMPARING => COMPARING,
OVERFLOW => OVERFLOW,
RESULT_GOOD => RESULT_GOOD, --O
RESULT_GOOD_PDU => RESULT_GOOD_PDU, --O
RESULT_GOOD_UFC => open --O
);
end generate DW_Sel_gen2;
---------------------------------------------------------------------------
-- Generate Tester clock and Loopback clock
---------------------------------------------------------------------------
loopback_clkgen: process
begin
loopback_clk <= '0';
wait for LOOPBACK_CLK_HALF_PERIOD;
loopback_clk <= '1';
wait for LOOPBACK_CLK_HALF_PERIOD;
end process loopback_clkgen;
tester_clkgen: process
begin
tester_clk <= '0';
wait for TESTER_CLK_HALF_PERIOD;
tester_clk <= '1';
wait for TESTER_CLK_HALF_PERIOD;
end process tester_clkgen;
---------------------------------------------------------------------------
-- Generate Global Reset
---------------------------------------------------------------------------
reset_gen : process
begin
rst <= '1';
wait for 55 ns;
rst <= '0';
wait; -- will wait forever
end process reset_gen;
END ll_fifo_tb_arch; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmuiface
-- File: mmuiface.vhd
-- Author: Konrad Eisele, Jiri Gaisler - Gaisler Research
-- Description: MMU interface types
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
package mmuiface is
type mmutlbcam_in_type is record
tagin : tlbcam_tfp;
tagwrite : tlbcam_reg;
trans_op : std_logic;
flush_op : std_logic;
write_op : std_logic;
wb_op : std_logic;
mmuen : std_logic;
mset : std_logic;
end record;
type mmutlbcami_a is array (natural range <>) of mmutlbcam_in_type;
constant mmutlbcam_in_type_none : mmutlbcam_in_type := (tlbcam_tfp_none,
tlbcam_reg_none, '0', '0', '0', '0', '0', '0');
type mmutlbcam_out_type is record
pteout : std_logic_vector(31 downto 0);
LVL : std_logic_vector(1 downto 0); -- level in pth
hit : std_logic;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0); -- for diagnostic access
valid : std_logic; -- for diagnostic access
vaddr : std_logic_vector(31 downto 0); -- for diagnostic access
NEEDSYNC : std_logic;
WBNEEDSYNC : std_logic;
end record;
type mmutlbcamo_a is array (natural range <>) of mmutlbcam_out_type;
constant mmutlbcam_out_none : mmutlbcam_out_type := (zero32, "00",
'0', "00000000", '0', zero32, '0', '0');
-- mmu i/o
type mmuidc_data_in_type is record
data : std_logic_vector(31 downto 0);
su : std_logic;
read : std_logic;
isid : mmu_idcache;
wb_data : std_logic_vector(31 downto 0);
end record;
type mmuidc_data_out_type is record
finish : std_logic;
data : std_logic_vector(31 downto 0);
cache : std_logic;
accexc : std_logic;
end record;
type mmudc_in_type is record
trans_op : std_logic;
transdata : mmuidc_data_in_type;
-- dcache extra signals
flush_op : std_logic;
diag_op : std_logic;
wb_op : std_logic;
fsread : std_logic;
mmctrl1 : mmctrl_type1;
end record;
type mmudc_out_type is record
grant : std_logic;
transdata : mmuidc_data_out_type;
-- dcache extra signals
mmctrl2 : mmctrl_type2;
-- writebuffer out
wbtransdata : mmuidc_data_out_type;
end record;
type mmuic_in_type is record
trans_op : std_logic;
transdata : mmuidc_data_in_type;
end record;
type mmuic_out_type is record
grant : std_logic;
transdata : mmuidc_data_out_type;
end record;
--#lrue i/o
type mmulrue_in_type is record
touch : std_logic;
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
clear : std_logic;
flush : std_logic;
left : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
fromleft : std_logic;
right : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
fromright : std_logic;
end record;
type mmulruei_a is array (natural range <>) of mmulrue_in_type;
type mmulrue_out_type is record
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
movetop : std_logic;
end record;
constant mmulrue_out_none : mmulrue_out_type := (zero32(M_ENT_MAX_LOG-1 downto 0), '0');
type mmulrueo_a is array (natural range <>) of mmulrue_out_type;
--#lru i/o
type mmulru_in_type is record
touch : std_logic;
touchmin : std_logic;
flush : std_logic;
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
mmctrl1 : mmctrl_type1;
end record;
type mmulru_out_type is record
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
end record;
--#mmu: tw i/o
type memory_mm_in_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
burst : std_logic;
read : std_logic;
req : std_logic;
lock : std_logic;
end record;
type memory_mm_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_logic; -- cycle ready
grant : std_logic; --
retry : std_logic; --
mexc : std_logic; -- memory exception
werr : std_logic; -- memory write error
cache : std_logic; -- cacheable data
end record;
type mmutw_in_type is record
walk_op_ur : std_logic;
areq_ur : std_logic;
data : std_logic_vector(31 downto 0);
adata : std_logic_vector(31 downto 0);
aaddr : std_logic_vector(31 downto 0);
end record;
type mmutwi_a is array (natural range <>) of mmutw_in_type;
type mmutw_out_type is record
finish : std_logic;
data : std_logic_vector(31 downto 0);
addr : std_logic_vector(31 downto 0);
lvl : std_logic_vector(1 downto 0);
fault_mexc : std_logic;
fault_trans : std_logic;
fault_inv : std_logic;
fault_lvl : std_logic_vector(1 downto 0);
end record;
type mmutwo_a is array (natural range <>) of mmutw_out_type;
-- mmu tlb i/o
type mmutlb_in_type is record
flush_op : std_logic;
diag_op_ur : std_logic;
wb_op : std_logic;
trans_op : std_logic;
transdata : mmuidc_data_in_type;
s2valid : std_logic;
annul : std_logic;
mmctrl1 : mmctrl_type1;
-- fast writebuffer signals
tlbcami : mmutlbcami_a (M_ENT_MAX-1 downto 0);
end record;
type mmutlbi_a is array (natural range <>) of mmutlb_in_type;
type mmutlbfault_out_type is record
fault_pro : std_logic;
fault_pri : std_logic;
fault_access : std_logic;
fault_mexc : std_logic;
fault_trans : std_logic;
fault_inv : std_logic;
fault_lvl : std_logic_vector(1 downto 0);
fault_su : std_logic;
fault_read : std_logic;
fault_isid : mmu_idcache;
fault_addr : std_logic_vector(31 downto 0);
end record;
type mmutlb_out_type is record
transdata : mmuidc_data_out_type;
fault : mmutlbfault_out_type;
nexttrans : std_logic;
s1finished : std_logic;
-- fast writebuffer signals
tlbcamo : mmutlbcamo_a (M_ENT_MAX-1 downto 0);
-- writebuffer out
wbtransdata : mmuidc_data_out_type;
end record;
type mmutlbo_a is array (natural range <>) of mmutlb_out_type;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmuiface
-- File: mmuiface.vhd
-- Author: Konrad Eisele, Jiri Gaisler - Gaisler Research
-- Description: MMU interface types
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
package mmuiface is
type mmutlbcam_in_type is record
tagin : tlbcam_tfp;
tagwrite : tlbcam_reg;
trans_op : std_logic;
flush_op : std_logic;
write_op : std_logic;
wb_op : std_logic;
mmuen : std_logic;
mset : std_logic;
end record;
type mmutlbcami_a is array (natural range <>) of mmutlbcam_in_type;
constant mmutlbcam_in_type_none : mmutlbcam_in_type := (tlbcam_tfp_none,
tlbcam_reg_none, '0', '0', '0', '0', '0', '0');
type mmutlbcam_out_type is record
pteout : std_logic_vector(31 downto 0);
LVL : std_logic_vector(1 downto 0); -- level in pth
hit : std_logic;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0); -- for diagnostic access
valid : std_logic; -- for diagnostic access
vaddr : std_logic_vector(31 downto 0); -- for diagnostic access
NEEDSYNC : std_logic;
WBNEEDSYNC : std_logic;
end record;
type mmutlbcamo_a is array (natural range <>) of mmutlbcam_out_type;
constant mmutlbcam_out_none : mmutlbcam_out_type := (zero32, "00",
'0', "00000000", '0', zero32, '0', '0');
-- mmu i/o
type mmuidc_data_in_type is record
data : std_logic_vector(31 downto 0);
su : std_logic;
read : std_logic;
isid : mmu_idcache;
wb_data : std_logic_vector(31 downto 0);
end record;
type mmuidc_data_out_type is record
finish : std_logic;
data : std_logic_vector(31 downto 0);
cache : std_logic;
accexc : std_logic;
end record;
type mmudc_in_type is record
trans_op : std_logic;
transdata : mmuidc_data_in_type;
-- dcache extra signals
flush_op : std_logic;
diag_op : std_logic;
wb_op : std_logic;
fsread : std_logic;
mmctrl1 : mmctrl_type1;
end record;
type mmudc_out_type is record
grant : std_logic;
transdata : mmuidc_data_out_type;
-- dcache extra signals
mmctrl2 : mmctrl_type2;
-- writebuffer out
wbtransdata : mmuidc_data_out_type;
end record;
type mmuic_in_type is record
trans_op : std_logic;
transdata : mmuidc_data_in_type;
end record;
type mmuic_out_type is record
grant : std_logic;
transdata : mmuidc_data_out_type;
end record;
--#lrue i/o
type mmulrue_in_type is record
touch : std_logic;
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
clear : std_logic;
flush : std_logic;
left : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
fromleft : std_logic;
right : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
fromright : std_logic;
end record;
type mmulruei_a is array (natural range <>) of mmulrue_in_type;
type mmulrue_out_type is record
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
movetop : std_logic;
end record;
constant mmulrue_out_none : mmulrue_out_type := (zero32(M_ENT_MAX_LOG-1 downto 0), '0');
type mmulrueo_a is array (natural range <>) of mmulrue_out_type;
--#lru i/o
type mmulru_in_type is record
touch : std_logic;
touchmin : std_logic;
flush : std_logic;
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
mmctrl1 : mmctrl_type1;
end record;
type mmulru_out_type is record
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
end record;
--#mmu: tw i/o
type memory_mm_in_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
burst : std_logic;
read : std_logic;
req : std_logic;
lock : std_logic;
end record;
type memory_mm_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_logic; -- cycle ready
grant : std_logic; --
retry : std_logic; --
mexc : std_logic; -- memory exception
werr : std_logic; -- memory write error
cache : std_logic; -- cacheable data
end record;
type mmutw_in_type is record
walk_op_ur : std_logic;
areq_ur : std_logic;
data : std_logic_vector(31 downto 0);
adata : std_logic_vector(31 downto 0);
aaddr : std_logic_vector(31 downto 0);
end record;
type mmutwi_a is array (natural range <>) of mmutw_in_type;
type mmutw_out_type is record
finish : std_logic;
data : std_logic_vector(31 downto 0);
addr : std_logic_vector(31 downto 0);
lvl : std_logic_vector(1 downto 0);
fault_mexc : std_logic;
fault_trans : std_logic;
fault_inv : std_logic;
fault_lvl : std_logic_vector(1 downto 0);
end record;
type mmutwo_a is array (natural range <>) of mmutw_out_type;
-- mmu tlb i/o
type mmutlb_in_type is record
flush_op : std_logic;
diag_op_ur : std_logic;
wb_op : std_logic;
trans_op : std_logic;
transdata : mmuidc_data_in_type;
s2valid : std_logic;
annul : std_logic;
mmctrl1 : mmctrl_type1;
-- fast writebuffer signals
tlbcami : mmutlbcami_a (M_ENT_MAX-1 downto 0);
end record;
type mmutlbi_a is array (natural range <>) of mmutlb_in_type;
type mmutlbfault_out_type is record
fault_pro : std_logic;
fault_pri : std_logic;
fault_access : std_logic;
fault_mexc : std_logic;
fault_trans : std_logic;
fault_inv : std_logic;
fault_lvl : std_logic_vector(1 downto 0);
fault_su : std_logic;
fault_read : std_logic;
fault_isid : mmu_idcache;
fault_addr : std_logic_vector(31 downto 0);
end record;
type mmutlb_out_type is record
transdata : mmuidc_data_out_type;
fault : mmutlbfault_out_type;
nexttrans : std_logic;
s1finished : std_logic;
-- fast writebuffer signals
tlbcamo : mmutlbcamo_a (M_ENT_MAX-1 downto 0);
-- writebuffer out
wbtransdata : mmuidc_data_out_type;
end record;
type mmutlbo_a is array (natural range <>) of mmutlb_out_type;
end;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : example_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity example_top is
generic
(
C1_P0_MASK_SIZE : integer := 4;
C1_P0_DATA_PORT_SIZE : integer := 32;
C1_P1_MASK_SIZE : integer := 4;
C1_P1_DATA_PORT_SIZE : integer := 32;
C1_MEMCLK_PERIOD : integer := 2500;
-- Memory data transfer clock period.
C1_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C1_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C1_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C1_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
C1_HW_TESTING : string := "FALSE";
-- Determines the address space accessed by the traffic generator,
-- # = FALSE, Smaller address space,
-- # = TRUE, Large address space.
DEBUG_EN : integer := 0;
-- # = 1, Enable debug signals/controls,
-- = 0, Disable debug signals/controls.
C1_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C1_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C1_MEM_ADDR_WIDTH : integer := 14;
-- External memory address width.
C1_MEM_BANKADDR_WIDTH : integer := 3;
-- External memory bank address width.
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 2500;
-- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
C3_HW_TESTING : string := "FALSE";
-- Determines the address space accessed by the traffic generator,
-- # = FALSE, Smaller address space,
-- # = TRUE, Large address space.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 14;
-- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3
-- External memory bank address width.
);
port
(
calib_done : out std_logic;
error : out std_logic;
mcb1_dram_dq : inout std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
mcb1_dram_a : out std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_odt : out std_logic;
mcb1_dram_reset_n : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udqs_n : inout std_logic;
mcb1_rzq : inout std_logic;
mcb1_zio : inout std_logic;
mcb1_dram_udm : out std_logic;
c1_sys_clk_p : in std_logic;
c1_sys_clk_n : in std_logic;
c1_sys_rst_i : in std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_dqs_n : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk_p : in std_logic;
c3_sys_clk_n : in std_logic;
c3_sys_rst_i : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end example_top;
architecture arc of example_top is
component memc1_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc3_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc1_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(2 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb1_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb1_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb1_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_odt : out std_logic;
mcb1_dram_reset_n : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udqs_n : inout std_logic;
mcb1_rzq : inout std_logic;
mcb1_zio : inout std_logic;
mcb1_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_dqs_n : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
component memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(2 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
component memc1_tb_top is
generic (
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_NUM_DQ_PINS : integer;
C_MEM_BURST_LEN : integer;
C_MEM_NUM_COL_BITS : integer;
C_SMALL_DEVICE : string;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0);
C_p0_DATA_MODE : std_logic_vector(3 downto 0);
C_p0_END_ADDRESS : std_logic_vector(31 downto 0);
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0)
);
port (
error : out std_logic;
calib_done : in std_logic;
clk0 : in std_logic;
rst0 : in std_logic;
cmp_error : out std_logic;
cmp_data_valid : out std_logic;
vio_modify_enable : in std_logic;
error_status : out std_logic_vector(127 downto 0);
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_data : out std_logic_vector(31 downto 0);
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0)
);
end component;
component memc3_tb_top is
generic (
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_NUM_DQ_PINS : integer;
C_MEM_BURST_LEN : integer;
C_MEM_NUM_COL_BITS : integer;
C_SMALL_DEVICE : string;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0);
C_p0_DATA_MODE : std_logic_vector(3 downto 0);
C_p0_END_ADDRESS : std_logic_vector(31 downto 0);
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0)
);
port (
error : out std_logic;
calib_done : in std_logic;
clk0 : in std_logic;
rst0 : in std_logic;
cmp_error : out std_logic;
cmp_data_valid : out std_logic;
vio_modify_enable : in std_logic;
error_status : out std_logic_vector(127 downto 0);
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_data : out std_logic_vector(31 downto 0);
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0)
);
end component;
function c1_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C1_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C1_CLKOUT0_DIVIDE : integer := 1;
constant C1_CLKOUT1_DIVIDE : integer := 1;
constant C1_CLKOUT2_DIVIDE : integer := 16;
constant C1_CLKOUT3_DIVIDE : integer := 8;
constant C1_CLKFBOUT_MULT : integer := 2;
constant C1_DIVCLK_DIVIDE : integer := 1;
constant C1_INCLK_PERIOD : integer := ((C1_MEMCLK_PERIOD * C1_CLKFBOUT_MULT) / (C1_DIVCLK_DIVIDE * C1_CLKOUT0_DIVIDE * 2));
constant C1_ARB_NUM_TIME_SLOTS : integer := 12;
constant C1_ARB_TIME_SLOT_0 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_1 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_2 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_3 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_4 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_5 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_6 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_7 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_8 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_9 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_10 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_11 : bit_vector(2 downto 0) := o"0";
constant C1_MEM_TRAS : integer := 36000;
constant C1_MEM_TRCD : integer := 13500;
constant C1_MEM_TREFI : integer := 7800000;
constant C1_MEM_TRFC : integer := 160000;
constant C1_MEM_TRP : integer := 13500;
constant C1_MEM_TWR : integer := 15000;
constant C1_MEM_TRTP : integer := 7500;
constant C1_MEM_TWTR : integer := 7500;
constant C1_MEM_TYPE : string := "DDR3";
constant C1_MEM_DENSITY : string := "2Gb";
constant C1_MEM_BURST_LEN : integer := 8;
constant C1_MEM_CAS_LATENCY : integer := 6;
constant C1_MEM_NUM_COL_BITS : integer := 10;
constant C1_MEM_DDR1_2_ODS : string := "FULL";
constant C1_MEM_DDR2_RTT : string := "50OHMS";
constant C1_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C1_MEM_DDR2_3_PA_SR : string := "FULL";
constant C1_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C1_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C1_MEM_DDR3_ODS : string := "DIV6";
constant C1_MEM_DDR3_RTT : string := "DIV4";
constant C1_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C1_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C1_MEM_MOBILE_PA_SR : string := "FULL";
constant C1_MEM_MDDR_ODS : string := "FULL";
constant C1_MC_CALIB_BYPASS : string := "NO";
constant C1_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C1_MC_CALIBRATION_DELAY : string := "HALF";
constant C1_SKIP_IN_TERM_CAL : integer := 0;
constant C1_SKIP_DYNAMIC_CAL : integer := 0;
constant C1_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C1_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C1_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C1_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C1_DQ0_TAP_DELAY_VAL : integer := 0;
constant C1_DQ1_TAP_DELAY_VAL : integer := 0;
constant C1_DQ2_TAP_DELAY_VAL : integer := 0;
constant C1_DQ3_TAP_DELAY_VAL : integer := 0;
constant C1_DQ4_TAP_DELAY_VAL : integer := 0;
constant C1_DQ5_TAP_DELAY_VAL : integer := 0;
constant C1_DQ6_TAP_DELAY_VAL : integer := 0;
constant C1_DQ7_TAP_DELAY_VAL : integer := 0;
constant C1_DQ8_TAP_DELAY_VAL : integer := 0;
constant C1_DQ9_TAP_DELAY_VAL : integer := 0;
constant C1_DQ10_TAP_DELAY_VAL : integer := 0;
constant C1_DQ11_TAP_DELAY_VAL : integer := 0;
constant C1_DQ12_TAP_DELAY_VAL : integer := 0;
constant C1_DQ13_TAP_DELAY_VAL : integer := 0;
constant C1_DQ14_TAP_DELAY_VAL : integer := 0;
constant C1_DQ15_TAP_DELAY_VAL : integer := 0;
constant C1_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
constant C3_CLKOUT0_DIVIDE : integer := 1;
constant C3_CLKOUT1_DIVIDE : integer := 1;
constant C3_CLKOUT2_DIVIDE : integer := 16;
constant C3_CLKOUT3_DIVIDE : integer := 8;
constant C3_CLKFBOUT_MULT : integer := 2;
constant C3_DIVCLK_DIVIDE : integer := 1;
constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));
constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
constant C3_ARB_TIME_SLOT_0 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_1 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_2 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_3 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_4 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_5 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_6 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_7 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_8 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_9 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_10 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_11 : bit_vector(2 downto 0) := o"0";
constant C3_MEM_TRAS : integer := 36000;
constant C3_MEM_TRCD : integer := 13500;
constant C3_MEM_TREFI : integer := 7800000;
constant C3_MEM_TRFC : integer := 160000;
constant C3_MEM_TRP : integer := 13500;
constant C3_MEM_TWR : integer := 15000;
constant C3_MEM_TRTP : integer := 7500;
constant C3_MEM_TWTR : integer := 7500;
constant C3_MEM_TYPE : string := "DDR3";
constant C3_MEM_DENSITY : string := "2Gb";
constant C3_MEM_BURST_LEN : integer := 8;
constant C3_MEM_CAS_LATENCY : integer := 6;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_MEM_DDR1_2_ODS : string := "FULL";
constant C3_MEM_DDR2_RTT : string := "50OHMS";
constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C3_MEM_DDR2_3_PA_SR : string := "FULL";
constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C3_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C3_MEM_DDR3_ODS : string := "DIV6";
constant C3_MEM_DDR3_RTT : string := "DIV4";
constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C3_MEM_MOBILE_PA_SR : string := "FULL";
constant C3_MEM_MDDR_ODS : string := "FULL";
constant C3_MC_CALIB_BYPASS : string := "NO";
constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C3_MC_CALIBRATION_DELAY : string := "HALF";
constant C3_SKIP_IN_TERM_CAL : integer := 0;
constant C3_SKIP_DYNAMIC_CAL : integer := 0;
constant C3_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_DQ0_TAP_DELAY_VAL : integer := 0;
constant C3_DQ1_TAP_DELAY_VAL : integer := 0;
constant C3_DQ2_TAP_DELAY_VAL : integer := 0;
constant C3_DQ3_TAP_DELAY_VAL : integer := 0;
constant C3_DQ4_TAP_DELAY_VAL : integer := 0;
constant C3_DQ5_TAP_DELAY_VAL : integer := 0;
constant C3_DQ6_TAP_DELAY_VAL : integer := 0;
constant C3_DQ7_TAP_DELAY_VAL : integer := 0;
constant C3_DQ8_TAP_DELAY_VAL : integer := 0;
constant C3_DQ9_TAP_DELAY_VAL : integer := 0;
constant C3_DQ10_TAP_DELAY_VAL : integer := 0;
constant C3_DQ11_TAP_DELAY_VAL : integer := 0;
constant C3_DQ12_TAP_DELAY_VAL : integer := 0;
constant C3_DQ13_TAP_DELAY_VAL : integer := 0;
constant C3_DQ14_TAP_DELAY_VAL : integer := 0;
constant C3_DQ15_TAP_DELAY_VAL : integer := 0;
constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
constant C1_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c1_sim_hw (x"00000100", x"01000000");
constant C1_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C1_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c1_sim_hw (x"000002ff", x"02ffffff");
constant C1_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c1_sim_hw (x"fffffc00", x"fc000000");
constant C1_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c1_sim_hw (x"00000100", x"01000000");
constant C3_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
signal c1_sys_clk : std_logic;
signal c1_error : std_logic;
signal c1_calib_done : std_logic;
signal c1_clk0 : std_logic;
signal c1_rst0 : std_logic;
signal c1_async_rst : std_logic;
signal c1_sysclk_2x : std_logic;
signal c1_sysclk_2x_180 : std_logic;
signal c1_pll_ce_0 : std_logic;
signal c1_pll_ce_90 : std_logic;
signal c1_pll_lock : std_logic;
signal c1_mcb_drp_clk : std_logic;
signal c1_cmp_error : std_logic;
signal c1_cmp_data_valid : std_logic;
signal c1_vio_modify_enable : std_logic;
signal c1_error_status : std_logic_vector(127 downto 0);
signal c1_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c1_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c1_cmp_data : std_logic_vector(31 downto 0);
signal c3_sys_clk : std_logic;
signal c3_error : std_logic;
signal c3_calib_done : std_logic;
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_async_rst : std_logic;
signal c3_sysclk_2x : std_logic;
signal c3_sysclk_2x_180 : std_logic;
signal c3_pll_ce_0 : std_logic;
signal c3_pll_ce_90 : std_logic;
signal c3_pll_lock : std_logic;
signal c3_mcb_drp_clk : std_logic;
signal c3_cmp_error : std_logic;
signal c3_cmp_data_valid : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c3_cmp_data : std_logic_vector(31 downto 0);
signal c1_p0_cmd_en : std_logic;
signal c1_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c1_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c1_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c1_p0_cmd_empty : std_logic;
signal c1_p0_cmd_full : std_logic;
signal c1_p0_wr_en : std_logic;
signal c1_p0_wr_mask : std_logic_vector(C1_P0_MASK_SIZE - 1 downto 0);
signal c1_p0_wr_data : std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
signal c1_p0_wr_full : std_logic;
signal c1_p0_wr_empty : std_logic;
signal c1_p0_wr_count : std_logic_vector(6 downto 0);
signal c1_p0_wr_underrun : std_logic;
signal c1_p0_wr_error : std_logic;
signal c1_p0_rd_en : std_logic;
signal c1_p0_rd_data : std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
signal c1_p0_rd_full : std_logic;
signal c1_p0_rd_empty : std_logic;
signal c1_p0_rd_count : std_logic_vector(6 downto 0);
signal c1_p0_rd_overflow : std_logic;
signal c1_p0_rd_error : std_logic;
signal c1_selfrefresh_enter : std_logic;
signal c1_selfrefresh_mode : std_logic;
signal c3_p0_cmd_en : std_logic;
signal c3_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p0_cmd_empty : std_logic;
signal c3_p0_cmd_full : std_logic;
signal c3_p0_wr_en : std_logic;
signal c3_p0_wr_mask : std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
signal c3_p0_wr_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_wr_full : std_logic;
signal c3_p0_wr_empty : std_logic;
signal c3_p0_wr_count : std_logic_vector(6 downto 0);
signal c3_p0_wr_underrun : std_logic;
signal c3_p0_wr_error : std_logic;
signal c3_p0_rd_en : std_logic;
signal c3_p0_rd_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_rd_full : std_logic;
signal c3_p0_rd_empty : std_logic;
signal c3_p0_rd_count : std_logic_vector(6 downto 0);
signal c3_p0_rd_overflow : std_logic;
signal c3_p0_rd_error : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
begin
error <= c1_error or c3_error;
calib_done <= c1_calib_done and c3_calib_done;
c1_sys_clk <= '0';
c3_sys_clk <= '0';
c1_selfrefresh_enter <= '0';
c3_selfrefresh_enter <= '0';
memc1_infrastructure_inst : memc1_infrastructure
generic map
(
C_RST_ACT_LOW => C1_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C1_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C1_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C1_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C1_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C1_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C1_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C1_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C1_INCLK_PERIOD
)
port map
(
sys_clk_p => c1_sys_clk_p,
sys_clk_n => c1_sys_clk_n,
sys_clk => c1_sys_clk,
sys_rst_i => c1_sys_rst_i,
clk0 => c1_clk0,
rst0 => c1_rst0,
async_rst => c1_async_rst,
sysclk_2x => c1_sysclk_2x,
sysclk_2x_180 => c1_sysclk_2x_180,
pll_ce_0 => c1_pll_ce_0,
pll_ce_90 => c1_pll_ce_90,
pll_lock => c1_pll_lock,
mcb_drp_clk => c1_mcb_drp_clk
);
memc3_infrastructure_inst : memc3_infrastructure
generic map
(
C_RST_ACT_LOW => C3_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C3_INCLK_PERIOD
)
port map
(
sys_clk_p => c3_sys_clk_p,
sys_clk_n => c3_sys_clk_n,
sys_clk => c3_sys_clk,
sys_rst_i => c3_sys_rst_i,
clk0 => c3_clk0,
rst0 => c3_rst0,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk
);
-- wrapper instantiation
memc1_wrapper_inst : memc1_wrapper
generic map
(
C_MEMCLK_PERIOD => C1_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C1_CALIB_SOFT_IP,
C_SIMULATION => C1_SIMULATION,
C_P0_MASK_SIZE => C1_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C1_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C1_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C1_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C1_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C1_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C1_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C1_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C1_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C1_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C1_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C1_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C1_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C1_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C1_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C1_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C1_ARB_TIME_SLOT_11,
C_MEM_TRAS => C1_MEM_TRAS,
C_MEM_TRCD => C1_MEM_TRCD,
C_MEM_TREFI => C1_MEM_TREFI,
C_MEM_TRFC => C1_MEM_TRFC,
C_MEM_TRP => C1_MEM_TRP,
C_MEM_TWR => C1_MEM_TWR,
C_MEM_TRTP => C1_MEM_TRTP,
C_MEM_TWTR => C1_MEM_TWTR,
C_MEM_ADDR_ORDER => C1_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C1_NUM_DQ_PINS,
C_MEM_TYPE => C1_MEM_TYPE,
C_MEM_DENSITY => C1_MEM_DENSITY,
C_MEM_BURST_LEN => C1_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C1_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C1_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C1_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C1_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C1_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C1_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C1_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C1_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C1_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C1_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C1_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C1_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C1_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C1_MEM_DDR3_AUTO_SR,
C_MEM_MOBILE_PA_SR => C1_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C1_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C1_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C1_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C1_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C1_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C1_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C1_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C1_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C1_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C1_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C1_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C1_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C1_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C1_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C1_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C1_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C1_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C1_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C1_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C1_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C1_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C1_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C1_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C1_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C1_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C1_DQ15_TAP_DELAY_VAL
)
port map
(
mcb1_dram_dq => mcb1_dram_dq,
mcb1_dram_a => mcb1_dram_a,
mcb1_dram_ba => mcb1_dram_ba,
mcb1_dram_ras_n => mcb1_dram_ras_n,
mcb1_dram_cas_n => mcb1_dram_cas_n,
mcb1_dram_we_n => mcb1_dram_we_n,
mcb1_dram_odt => mcb1_dram_odt,
mcb1_dram_reset_n => mcb1_dram_reset_n,
mcb1_dram_cke => mcb1_dram_cke,
mcb1_dram_dm => mcb1_dram_dm,
mcb1_dram_udqs => mcb1_dram_udqs,
mcb1_dram_udqs_n => mcb1_dram_udqs_n,
mcb1_rzq => mcb1_rzq,
mcb1_zio => mcb1_zio,
mcb1_dram_udm => mcb1_dram_udm,
calib_done => c1_calib_done,
async_rst => c1_async_rst,
sysclk_2x => c1_sysclk_2x,
sysclk_2x_180 => c1_sysclk_2x_180,
pll_ce_0 => c1_pll_ce_0,
pll_ce_90 => c1_pll_ce_90,
pll_lock => c1_pll_lock,
mcb_drp_clk => c1_mcb_drp_clk,
mcb1_dram_dqs => mcb1_dram_dqs,
mcb1_dram_dqs_n => mcb1_dram_dqs_n,
mcb1_dram_ck => mcb1_dram_ck,
mcb1_dram_ck_n => mcb1_dram_ck_n,
p0_cmd_clk => c1_clk0,
p0_cmd_en => c1_p0_cmd_en,
p0_cmd_instr => c1_p0_cmd_instr,
p0_cmd_bl => c1_p0_cmd_bl,
p0_cmd_byte_addr => c1_p0_cmd_byte_addr,
p0_cmd_empty => c1_p0_cmd_empty,
p0_cmd_full => c1_p0_cmd_full,
p0_wr_clk => c1_clk0,
p0_wr_en => c1_p0_wr_en,
p0_wr_mask => c1_p0_wr_mask,
p0_wr_data => c1_p0_wr_data,
p0_wr_full => c1_p0_wr_full,
p0_wr_empty => c1_p0_wr_empty,
p0_wr_count => c1_p0_wr_count,
p0_wr_underrun => c1_p0_wr_underrun,
p0_wr_error => c1_p0_wr_error,
p0_rd_clk => c1_clk0,
p0_rd_en => c1_p0_rd_en,
p0_rd_data => c1_p0_rd_data,
p0_rd_full => c1_p0_rd_full,
p0_rd_empty => c1_p0_rd_empty,
p0_rd_count => c1_p0_rd_count,
p0_rd_overflow => c1_p0_rd_overflow,
p0_rd_error => c1_p0_rd_error,
selfrefresh_enter => c1_selfrefresh_enter,
selfrefresh_mode => c1_selfrefresh_mode
);
memc3_wrapper_inst : memc3_wrapper
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11,
C_MEM_TRAS => C3_MEM_TRAS,
C_MEM_TRCD => C3_MEM_TRCD,
C_MEM_TREFI => C3_MEM_TREFI,
C_MEM_TRFC => C3_MEM_TRFC,
C_MEM_TRP => C3_MEM_TRP,
C_MEM_TWR => C3_MEM_TWR,
C_MEM_TRTP => C3_MEM_TRTP,
C_MEM_TWTR => C3_MEM_TWTR,
C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_TYPE => C3_MEM_TYPE,
C_MEM_DENSITY => C3_MEM_DENSITY,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR,
C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL
)
port map
(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
calib_done => c3_calib_done,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
p0_cmd_clk => c3_clk0,
p0_cmd_en => c3_p0_cmd_en,
p0_cmd_instr => c3_p0_cmd_instr,
p0_cmd_bl => c3_p0_cmd_bl,
p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
p0_cmd_empty => c3_p0_cmd_empty,
p0_cmd_full => c3_p0_cmd_full,
p0_wr_clk => c3_clk0,
p0_wr_en => c3_p0_wr_en,
p0_wr_mask => c3_p0_wr_mask,
p0_wr_data => c3_p0_wr_data,
p0_wr_full => c3_p0_wr_full,
p0_wr_empty => c3_p0_wr_empty,
p0_wr_count => c3_p0_wr_count,
p0_wr_underrun => c3_p0_wr_underrun,
p0_wr_error => c3_p0_wr_error,
p0_rd_clk => c3_clk0,
p0_rd_en => c3_p0_rd_en,
p0_rd_data => c3_p0_rd_data,
p0_rd_full => c3_p0_rd_full,
p0_rd_empty => c3_p0_rd_empty,
p0_rd_count => c3_p0_rd_count,
p0_rd_overflow => c3_p0_rd_overflow,
p0_rd_error => c3_p0_rd_error,
selfrefresh_enter => c3_selfrefresh_enter,
selfrefresh_mode => c3_selfrefresh_mode
);
memc1_tb_top_inst : memc1_tb_top
generic map
(
C_SIMULATION => C1_SIMULATION,
C_P0_MASK_SIZE => C1_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C1_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C1_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C1_P1_DATA_PORT_SIZE,
C_NUM_DQ_PINS => C1_NUM_DQ_PINS,
C_MEM_BURST_LEN => C1_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C1_MEM_NUM_COL_BITS,
C_SMALL_DEVICE => C1_SMALL_DEVICE,
C_p0_BEGIN_ADDRESS => C1_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C1_p0_DATA_MODE,
C_p0_END_ADDRESS => C1_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C1_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C1_p0_PRBS_SADDR_MASK_POS
)
port map
(
error => c1_error,
calib_done => c1_calib_done,
clk0 => c1_clk0,
rst0 => c1_rst0,
cmp_error => c1_cmp_error,
cmp_data_valid => c1_cmp_data_valid,
vio_modify_enable => c1_vio_modify_enable,
error_status => c1_error_status,
vio_data_mode_value => c1_vio_data_mode_value,
vio_addr_mode_value => c1_vio_addr_mode_value,
cmp_data => c1_cmp_data,
p0_mcb_cmd_en_o => c1_p0_cmd_en,
p0_mcb_cmd_instr_o => c1_p0_cmd_instr,
p0_mcb_cmd_bl_o => c1_p0_cmd_bl,
p0_mcb_cmd_addr_o => c1_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c1_p0_cmd_full,
p0_mcb_wr_en_o => c1_p0_wr_en,
p0_mcb_wr_mask_o => c1_p0_wr_mask,
p0_mcb_wr_data_o => c1_p0_wr_data,
p0_mcb_wr_full_i => c1_p0_wr_full,
p0_mcb_wr_fifo_counts => c1_p0_wr_count,
p0_mcb_rd_en_o => c1_p0_rd_en,
p0_mcb_rd_data_i => c1_p0_rd_data,
p0_mcb_rd_empty_i => c1_p0_rd_empty,
p0_mcb_rd_fifo_counts => c1_p0_rd_count
);
memc3_tb_top_inst : memc3_tb_top
generic map
(
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_SMALL_DEVICE => C3_SMALL_DEVICE,
C_p0_BEGIN_ADDRESS => C3_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C3_p0_DATA_MODE,
C_p0_END_ADDRESS => C3_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C3_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C3_p0_PRBS_SADDR_MASK_POS
)
port map
(
error => c3_error,
calib_done => c3_calib_done,
clk0 => c3_clk0,
rst0 => c3_rst0,
cmp_error => c3_cmp_error,
cmp_data_valid => c3_cmp_data_valid,
vio_modify_enable => c3_vio_modify_enable,
error_status => c3_error_status,
vio_data_mode_value => c3_vio_data_mode_value,
vio_addr_mode_value => c3_vio_addr_mode_value,
cmp_data => c3_cmp_data,
p0_mcb_cmd_en_o => c3_p0_cmd_en,
p0_mcb_cmd_instr_o => c3_p0_cmd_instr,
p0_mcb_cmd_bl_o => c3_p0_cmd_bl,
p0_mcb_cmd_addr_o => c3_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c3_p0_cmd_full,
p0_mcb_wr_en_o => c3_p0_wr_en,
p0_mcb_wr_mask_o => c3_p0_wr_mask,
p0_mcb_wr_data_o => c3_p0_wr_data,
p0_mcb_wr_full_i => c3_p0_wr_full,
p0_mcb_wr_fifo_counts => c3_p0_wr_count,
p0_mcb_rd_en_o => c3_p0_rd_en,
p0_mcb_rd_data_i => c3_p0_rd_data,
p0_mcb_rd_empty_i => c3_p0_rd_empty,
p0_mcb_rd_fifo_counts => c3_p0_rd_count
);
end arc;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gptimer
-- File: gptimer.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implemets a set of general-purpose timers with a
-- common prescaler. Then number of timers and the width of
-- the timers is propgrammable through generics
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity gptimer is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
sepirq : integer := 0; -- use separate interrupts for each timer
sbits : integer := 16; -- scaler bits
ntimers : integer range 1 to 7 := 1; -- number of timers
nbits : integer := 32; -- timer bits
wdog : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpti : in gptimer_in_type;
gpto : out gptimer_out_type
);
end;
architecture rtl of gptimer is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GPTIMER, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type timer_reg is record
enable : std_ulogic; -- enable counter
load : std_ulogic; -- load counter
restart : std_ulogic; -- restart counter
irqpen : std_ulogic; -- interrupt pending
irqen : std_ulogic; -- interrupt enable
irq : std_ulogic; -- interrupt pulse
chain : std_ulogic; -- chain with previous timer
value : std_logic_vector(nbits-1 downto 0);
reload : std_logic_vector(nbits-1 downto 0);
end record;
type timer_reg_vector is array (Natural range <> ) of timer_reg;
constant TBITS : integer := log2x(ntimers+1);
type registers is record
scaler : std_logic_vector(sbits-1 downto 0);
reload : std_logic_vector(sbits-1 downto 0);
tick : std_ulogic;
tsel : integer range 0 to ntimers;
timers : timer_reg_vector(1 to ntimers);
dishlt : std_ulogic;
wdogn : std_ulogic;
wdog : std_ulogic;
end record;
signal r, rin : registers;
begin
comb : process(rst, r, apbi, gpti)
variable scaler : std_logic_vector(sbits downto 0);
variable readdata, timer1 : std_logic_vector(31 downto 0);
variable res, addin : std_logic_vector(nbits-1 downto 0);
variable v : registers;
variable z : std_ulogic;
variable vtimers : timer_reg_vector(0 to ntimers);
variable xirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable nirq : std_logic_vector(0 to ntimers-1);
variable tick : std_logic_vector(1 to 7);
begin
v := r; v.tick := '0'; tick := (others => '0');
vtimers(0) := ('0', '0', '0', '0', '0', '0', '0',
zero32(nbits-1 downto 0), zero32(nbits-1 downto 0) );
vtimers(1 to ntimers) := r.timers; xirq := (others => '0');
for i in 1 to ntimers loop
v.timers(i).irq := '0'; v.timers(i).load := '0';
tick(i) := r.timers(i).irq;
end loop;
v.wdogn := not r.timers(ntimers).irqpen; v.wdog := r.timers(ntimers).irqpen;
-- scaler operation
scaler := ('0' & r.scaler) - 1; -- decrement scaler
if (not gpti.dhalt or r.dishlt) = '1' then -- halt timers in debug mode
if (scaler(sbits) = '1') then
v.scaler := r.reload; v.tick := '1'; -- reload scaler
else v.scaler := scaler(sbits-1 downto 0); end if;
end if;
-- timer operation
if (r.tick = '1') or (r.tsel /= 0) then
if r.tsel = ntimers then v.tsel := 0;
else v.tsel := r.tsel + 1; end if;
end if;
res := vtimers(r.tsel).value - 1; -- decrement selected timer
if (res(nbits-1) = '1') and ((vtimers(r.tsel).value(nbits-1) = '0'))
then z := '1'; else z := '0'; end if; -- undeflow detect
-- update corresponding register and generate irq
for i in 1 to ntimers-1 loop nirq(i) := r.timers(i).irq; end loop;
nirq(0) := r.timers(ntimers).irq;
for i in 1 to ntimers loop
if i = r.tsel then
if (r.timers(i).enable = '1') and
(((r.timers(i).chain and nirq(i-1)) or not (r.timers(i).chain)) = '1')
then
v.timers(i).irq := z and not r.timers(i).load;
if (v.timers(i).irq and r.timers(i).irqen) = '1' then
v.timers(i).irqpen := '1';
end if;
v.timers(i).value := res;
if (z and not r.timers(i).load) = '1' then
v.timers(i).enable := r.timers(i).restart;
if r.timers(i).restart = '1' then
v.timers(i).value := r.timers(i).reload;
end if;
end if;
end if;
end if;
if r.timers(i).load = '1' then
v.timers(i).value := r.timers(i).reload;
end if;
end loop;
if sepirq /= 0 then
for i in 1 to ntimers loop
xirq(i-1+pirq) := r.timers(i).irq and r.timers(i).irqen;
end loop;
else
for i in 1 to ntimers loop
xirq(pirq) := xirq(pirq) or (r.timers(i).irq and r.timers(i).irqen);
end loop;
end if;
-- read registers
readdata := (others => '0');
case apbi.paddr(6 downto 2) is
when "00000" => readdata(sbits-1 downto 0) := r.scaler;
when "00001" => readdata(sbits-1 downto 0) := r.reload;
when "00010" =>
readdata(2 downto 0) := conv_std_logic_vector(ntimers, 3) ;
readdata(7 downto 3) := conv_std_logic_vector(pirq, 5) ;
if (sepirq /= 0) then readdata(8) := '1'; end if;
readdata(9) := r.dishlt;
when others =>
for i in 1 to ntimers loop
if conv_integer(apbi.paddr(6 downto 4)) = i then
case apbi.paddr(3 downto 2) is
when "00" => readdata(nbits-1 downto 0) := r.timers(i).value;
when "01" => readdata(nbits-1 downto 0) := r.timers(i).reload;
when "10" => readdata(6 downto 0) :=
gpti.dhalt & r.timers(i).chain &
r.timers(i).irqpen & r.timers(i).irqen & r.timers(i).load &
r.timers(i).restart & r.timers(i).enable;
when others =>
end case;
end if;
end loop;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(6 downto 2) is
when "00000" => v.scaler := apbi.pwdata(sbits-1 downto 0);
when "00001" => v.reload := apbi.pwdata(sbits-1 downto 0);
v.scaler := apbi.pwdata(sbits-1 downto 0);
when "00010" => v.dishlt := apbi.pwdata(9);
when others =>
for i in 1 to ntimers loop
if conv_integer(apbi.paddr(6 downto 4)) = i then
case apbi.paddr(3 downto 2) is
when "00" => v.timers(i).value := apbi.pwdata(nbits-1 downto 0);
when "01" => v.timers(i).reload := apbi.pwdata(nbits-1 downto 0);
when "10" => v.timers(i).chain := apbi.pwdata(5);
v.timers(i).irqpen := apbi.pwdata(4);
v.timers(i).irqen := apbi.pwdata(3);
v.timers(i).load := apbi.pwdata(2);
v.timers(i).restart := apbi.pwdata(1);
v.timers(i).enable := apbi.pwdata(0);
when others =>
end case;
end if;
end loop;
end case;
end if;
-- reset operation
if rst = '0' then
for i in 1 to ntimers loop
v.timers(i).enable := '0'; v.timers(i).irqen := '0';
end loop;
v.scaler := (others => '1'); v.reload := (others => '1');
v.tsel := 0; v.dishlt := '0'; v.timers(ntimers).irq := '0';
if (wdog /= 0) then
v.timers(ntimers).enable := '1'; v.timers(ntimers).load := '1';
v.timers(ntimers).reload := conv_std_logic_vector(wdog, nbits);
v.timers(ntimers).chain := '0'; v.timers(ntimers).irqen := '1';
v.timers(ntimers).irqpen := '0'; v.timers(ntimers).restart := '0';
end if;
end if;
timer1 := (others => '0'); timer1(nbits-1 downto 0) := r.timers(1).value;
rin <= v;
apbo.prdata <= readdata; -- drive apb read bus
apbo.pirq <= xirq;
apbo.pindex <= pindex;
gpto.tick <= r.tick & tick;
gpto.timer1 <= timer1; -- output timer1 value for debugging
gpto.wdogn <= r.wdogn;
gpto.wdog <= r.wdog;
end process;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("gptimer" & tost(pindex) &
": GR Timer Unit rev " & tost(REVISION) &
", " & tost(sbits) & "-bit scaler, " & tost(ntimers) &
" " & tost(nbits) & "-bit timers" & ", irq " & tost(pirq));
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gptimer
-- File: gptimer.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implemets a set of general-purpose timers with a
-- common prescaler. Then number of timers and the width of
-- the timers is propgrammable through generics
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity gptimer is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
sepirq : integer := 0; -- use separate interrupts for each timer
sbits : integer := 16; -- scaler bits
ntimers : integer range 1 to 7 := 1; -- number of timers
nbits : integer := 32; -- timer bits
wdog : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpti : in gptimer_in_type;
gpto : out gptimer_out_type
);
end;
architecture rtl of gptimer is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GPTIMER, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type timer_reg is record
enable : std_ulogic; -- enable counter
load : std_ulogic; -- load counter
restart : std_ulogic; -- restart counter
irqpen : std_ulogic; -- interrupt pending
irqen : std_ulogic; -- interrupt enable
irq : std_ulogic; -- interrupt pulse
chain : std_ulogic; -- chain with previous timer
value : std_logic_vector(nbits-1 downto 0);
reload : std_logic_vector(nbits-1 downto 0);
end record;
type timer_reg_vector is array (Natural range <> ) of timer_reg;
constant TBITS : integer := log2x(ntimers+1);
type registers is record
scaler : std_logic_vector(sbits-1 downto 0);
reload : std_logic_vector(sbits-1 downto 0);
tick : std_ulogic;
tsel : integer range 0 to ntimers;
timers : timer_reg_vector(1 to ntimers);
dishlt : std_ulogic;
wdogn : std_ulogic;
wdog : std_ulogic;
end record;
signal r, rin : registers;
begin
comb : process(rst, r, apbi, gpti)
variable scaler : std_logic_vector(sbits downto 0);
variable readdata, timer1 : std_logic_vector(31 downto 0);
variable res, addin : std_logic_vector(nbits-1 downto 0);
variable v : registers;
variable z : std_ulogic;
variable vtimers : timer_reg_vector(0 to ntimers);
variable xirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable nirq : std_logic_vector(0 to ntimers-1);
variable tick : std_logic_vector(1 to 7);
begin
v := r; v.tick := '0'; tick := (others => '0');
vtimers(0) := ('0', '0', '0', '0', '0', '0', '0',
zero32(nbits-1 downto 0), zero32(nbits-1 downto 0) );
vtimers(1 to ntimers) := r.timers; xirq := (others => '0');
for i in 1 to ntimers loop
v.timers(i).irq := '0'; v.timers(i).load := '0';
tick(i) := r.timers(i).irq;
end loop;
v.wdogn := not r.timers(ntimers).irqpen; v.wdog := r.timers(ntimers).irqpen;
-- scaler operation
scaler := ('0' & r.scaler) - 1; -- decrement scaler
if (not gpti.dhalt or r.dishlt) = '1' then -- halt timers in debug mode
if (scaler(sbits) = '1') then
v.scaler := r.reload; v.tick := '1'; -- reload scaler
else v.scaler := scaler(sbits-1 downto 0); end if;
end if;
-- timer operation
if (r.tick = '1') or (r.tsel /= 0) then
if r.tsel = ntimers then v.tsel := 0;
else v.tsel := r.tsel + 1; end if;
end if;
res := vtimers(r.tsel).value - 1; -- decrement selected timer
if (res(nbits-1) = '1') and ((vtimers(r.tsel).value(nbits-1) = '0'))
then z := '1'; else z := '0'; end if; -- undeflow detect
-- update corresponding register and generate irq
for i in 1 to ntimers-1 loop nirq(i) := r.timers(i).irq; end loop;
nirq(0) := r.timers(ntimers).irq;
for i in 1 to ntimers loop
if i = r.tsel then
if (r.timers(i).enable = '1') and
(((r.timers(i).chain and nirq(i-1)) or not (r.timers(i).chain)) = '1')
then
v.timers(i).irq := z and not r.timers(i).load;
if (v.timers(i).irq and r.timers(i).irqen) = '1' then
v.timers(i).irqpen := '1';
end if;
v.timers(i).value := res;
if (z and not r.timers(i).load) = '1' then
v.timers(i).enable := r.timers(i).restart;
if r.timers(i).restart = '1' then
v.timers(i).value := r.timers(i).reload;
end if;
end if;
end if;
end if;
if r.timers(i).load = '1' then
v.timers(i).value := r.timers(i).reload;
end if;
end loop;
if sepirq /= 0 then
for i in 1 to ntimers loop
xirq(i-1+pirq) := r.timers(i).irq and r.timers(i).irqen;
end loop;
else
for i in 1 to ntimers loop
xirq(pirq) := xirq(pirq) or (r.timers(i).irq and r.timers(i).irqen);
end loop;
end if;
-- read registers
readdata := (others => '0');
case apbi.paddr(6 downto 2) is
when "00000" => readdata(sbits-1 downto 0) := r.scaler;
when "00001" => readdata(sbits-1 downto 0) := r.reload;
when "00010" =>
readdata(2 downto 0) := conv_std_logic_vector(ntimers, 3) ;
readdata(7 downto 3) := conv_std_logic_vector(pirq, 5) ;
if (sepirq /= 0) then readdata(8) := '1'; end if;
readdata(9) := r.dishlt;
when others =>
for i in 1 to ntimers loop
if conv_integer(apbi.paddr(6 downto 4)) = i then
case apbi.paddr(3 downto 2) is
when "00" => readdata(nbits-1 downto 0) := r.timers(i).value;
when "01" => readdata(nbits-1 downto 0) := r.timers(i).reload;
when "10" => readdata(6 downto 0) :=
gpti.dhalt & r.timers(i).chain &
r.timers(i).irqpen & r.timers(i).irqen & r.timers(i).load &
r.timers(i).restart & r.timers(i).enable;
when others =>
end case;
end if;
end loop;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(6 downto 2) is
when "00000" => v.scaler := apbi.pwdata(sbits-1 downto 0);
when "00001" => v.reload := apbi.pwdata(sbits-1 downto 0);
v.scaler := apbi.pwdata(sbits-1 downto 0);
when "00010" => v.dishlt := apbi.pwdata(9);
when others =>
for i in 1 to ntimers loop
if conv_integer(apbi.paddr(6 downto 4)) = i then
case apbi.paddr(3 downto 2) is
when "00" => v.timers(i).value := apbi.pwdata(nbits-1 downto 0);
when "01" => v.timers(i).reload := apbi.pwdata(nbits-1 downto 0);
when "10" => v.timers(i).chain := apbi.pwdata(5);
v.timers(i).irqpen := apbi.pwdata(4);
v.timers(i).irqen := apbi.pwdata(3);
v.timers(i).load := apbi.pwdata(2);
v.timers(i).restart := apbi.pwdata(1);
v.timers(i).enable := apbi.pwdata(0);
when others =>
end case;
end if;
end loop;
end case;
end if;
-- reset operation
if rst = '0' then
for i in 1 to ntimers loop
v.timers(i).enable := '0'; v.timers(i).irqen := '0';
end loop;
v.scaler := (others => '1'); v.reload := (others => '1');
v.tsel := 0; v.dishlt := '0'; v.timers(ntimers).irq := '0';
if (wdog /= 0) then
v.timers(ntimers).enable := '1'; v.timers(ntimers).load := '1';
v.timers(ntimers).reload := conv_std_logic_vector(wdog, nbits);
v.timers(ntimers).chain := '0'; v.timers(ntimers).irqen := '1';
v.timers(ntimers).irqpen := '0'; v.timers(ntimers).restart := '0';
end if;
end if;
timer1 := (others => '0'); timer1(nbits-1 downto 0) := r.timers(1).value;
rin <= v;
apbo.prdata <= readdata; -- drive apb read bus
apbo.pirq <= xirq;
apbo.pindex <= pindex;
gpto.tick <= r.tick & tick;
gpto.timer1 <= timer1; -- output timer1 value for debugging
gpto.wdogn <= r.wdogn;
gpto.wdog <= r.wdog;
end process;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("gptimer" & tost(pindex) &
": GR Timer Unit rev " & tost(REVISION) &
", " & tost(sbits) & "-bit scaler, " & tost(ntimers) &
" " & tost(nbits) & "-bit timers" & ", irq " & tost(pirq));
-- pragma translate_on
end;
|
----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 02.04.2017
-- Design Name: Ping Reply Processor
-- Module Name: ping_reply_processor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions: Vivado 2016.2
-- Description: This module receives a ping/echo request packet from ICMP_RX and
-- forwards an appropriate echo reply to ICMP_TX.
--
-- Dependencies: Xilinx FIFO IP
--
-- Changelog:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
entity ping_reply_processor is
Port(
-- ICMP RX interface
icmp_rx_start : in std_logic;
icmp_rxi : in icmp_rx_type;
-- system signals
tx_clk : in std_logic;
rx_clk : in std_logic;
reset : in std_logic;
fifo_init : in std_logic;
-- ICMP/UDP mux interface
sel_icmp : out std_logic;
-- ICMP TX interface
icmp_tx_start : out std_logic;
icmp_tx_ready : in std_logic;
icmp_txo : out icmp_tx_type;
icmp_tx_is_idle : in std_logic
);
end ping_reply_processor;
architecture Behavioral of ping_reply_processor is
COMPONENT icmp_payload_buffer
PORT(
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
type rx_state_type is (IDLE, CNT_LEN, CHK_TYPE_CODE, WAIT_FOR_TX);
type tx_state_type is (IDLE, SET_HDR, START, WAIT_FOR_EMPTY, DELAY);
signal ping_rx_state : rx_state_type := IDLE;
signal ping_tx_state : tx_state_type := IDLE;
signal payLen_count_ug : unsigned (15 downto 0) := (others => '0');
signal chksum_out_ug : unsigned (15 downto 0) := (others => '0');
signal tx_ena : std_logic := '0';
signal rd_ena : std_logic := '0';
signal rst_fifo_fsm : std_logic := '0';
signal rst_fifo : std_logic := '0';
signal fifo_empty : std_logic := '0';
signal fifo_full : std_logic := '0';
signal data_last : std_logic := '0';
signal data_valid : std_logic := '0';
signal data_valid_reg : std_logic := '0';
begin
--------------------------------------------------------------------------
-- combinatorial process to implement FSM RX and determine control signals
--------------------------------------------------------------------------
ping_FSM_RX: process(rx_clk)
begin
if(rising_edge(rx_clk))then
if(reset = '1')then
payLen_count_ug <= (others => '0');
chksum_out_ug <= (others => '0');
tx_ena <= '0';
ping_rx_state <= IDLE;
else
case ping_rx_state is
when IDLE =>
if(icmp_rx_start = '1' and icmp_rxi.hdr.icmp_type = x"08")then
if(icmp_rxi.payload.data_in_valid = '1' and icmp_rxi.payload.data_in_last = '0')then
payLen_count_ug <= payLen_count_ug + 1;
ping_rx_state <= CNT_LEN;
elsif(icmp_rx_start = '1' and icmp_rxi.payload.data_in_valid = '1' and icmp_rxi.payload.data_in_last = '1')then
-- payload is only one-byte long
payLen_count_ug <= payLen_count_ug + 1;
ping_rx_state <= CHK_TYPE_CODE;
else
ping_rx_state <= IDLE;
end if;
else
payLen_count_ug <= (others => '0');
chksum_out_ug <= (others => '0');
tx_ena <= '0';
ping_rx_state <= IDLE;
end if;
when CNT_LEN =>
payLen_count_ug <= payLen_count_ug + 1;
if(icmp_rxi.payload.data_in_last = '1')then
chksum_out_ug <= unsigned(icmp_rxi.hdr.icmp_chksum);
ping_rx_state <= CHK_TYPE_CODE;
else
ping_rx_state <= CNT_LEN;
end if;
when CHK_TYPE_CODE =>
if(icmp_rxi.hdr.icmp_type = x"08" and icmp_rxi.hdr.icmp_code = x"00")then -- echo request
chksum_out_ug <= chksum_out_ug + "0000100000000000"; -- plus 2048 in dec
payLen_count_ug <= payLen_count_ug;
tx_ena <= '1';
ping_rx_state <= WAIT_FOR_TX;
else
chksum_out_ug <= (others => '0');
payLen_count_ug <= (others => '0');
tx_ena <= '0';
ping_rx_state <= IDLE;
end if;
when WAIT_FOR_TX =>
chksum_out_ug <= chksum_out_ug;
if(fifo_empty = '1')then
tx_ena <= '0';
ping_rx_state <= IDLE;
else
tx_ena <= '1';
ping_rx_state <= WAIT_FOR_TX;
end if;
when others =>
ping_rx_state <= IDLE;
end case;
end if;
end if;
end process;
ping_FSM_TX: process(tx_clk)
begin
if(rising_edge(tx_clk))then
if(reset = '1')then
rd_ena <= '0';
rst_fifo_fsm <= '0';
data_last <= '0';
data_valid <= '0';
icmp_tx_start <= '0';
sel_icmp <= '0';
ping_tx_state <= IDLE;
else
case ping_tx_state is
when IDLE =>
rst_fifo_fsm <= '0';
if(tx_ena = '1')then
sel_icmp <= '1';
ping_tx_state <= SET_HDR;
else
sel_icmp <= '0';
ping_tx_state <= IDLE;
end if;
when SET_HDR =>
icmp_txo.hdr.dst_ip_addr <= icmp_rxi.hdr.src_ip_addr;
icmp_txo.hdr.icmp_pay_len <= std_logic_vector(payLen_count_ug); -- payload length in bytes
------------------------
icmp_txo.hdr.icmp_type <= x"00"; -- reply
icmp_txo.hdr.icmp_code <= x"00"; -- reply
icmp_txo.hdr.icmp_chksum <= std_logic_vector(chksum_out_ug); -- old checksum + 2048(in dec)
icmp_txo.hdr.icmp_ident <= icmp_rxi.hdr.icmp_ident; -- CC
icmp_txo.hdr.icmp_seqNum <= icmp_rxi.hdr.icmp_seqNum; -- CC
icmp_tx_start <= '1';
ping_tx_state <= START;
when START =>
if(icmp_tx_ready = '1')then
rd_ena <= '1';
data_valid <= '1';
icmp_tx_start <= '0';
ping_tx_state <= WAIT_FOR_EMPTY;
else
rd_ena <= '0';
data_valid <= '0';
icmp_tx_start <= '1';
ping_tx_state <= START;
end if;
when WAIT_FOR_EMPTY =>
if(fifo_empty = '1')then
rd_ena <= '0';
data_valid <= '0';
data_last <= '1';
rst_fifo_fsm <= '1';
ping_tx_state <= DELAY;
else
rd_ena <= '1';
data_valid <= '1';
data_last <= '0';
ping_tx_state <= WAIT_FOR_EMPTY;
end if;
when DELAY =>
data_last <= '0';
rst_fifo_fsm <= '1';
if(icmp_tx_is_idle = '1')then
ping_tx_state <= IDLE;
else
ping_tx_state <= DELAY;
end if;
when others =>
ping_tx_state <= IDLE;
end case;
end if;
end if;
end process;
fdre_valid_0 : process(tx_clk)
begin
if(rising_edge(tx_clk))then
if(reset = '1')then
data_valid_reg <= '0';
else
data_valid_reg <= data_valid;
end if;
end if;
end process;
fdre_valid_1 : process(tx_clk)
begin
if(rising_edge(tx_clk))then
if(reset = '1')then
icmp_txo.payload.data_out_valid <= '0';
else
icmp_txo.payload.data_out_valid <= data_valid_reg;
end if;
end if;
end process;
fifo_payload_buffer: icmp_payload_buffer
PORT MAP (
rst => rst_fifo,
wr_clk => rx_clk,
rd_clk => tx_clk,
din => icmp_rxi.payload.data_in,
wr_en => icmp_rxi.payload.data_in_valid,
rd_en => rd_ena,
dout => icmp_txo.payload.data_out,
full => fifo_full,
empty => fifo_empty
);
icmp_txo.payload.data_out_last <= data_last;
rst_fifo <= rst_fifo_fsm or fifo_init;
end Behavioral;
|
------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------
entity mux2x1 is
--generic declarations
port (
a, b, sel: in std_logic;
x: out std_logic);
end entity;
------------------------------
architecture mux2x1 of mux2x1 is
--signals and declarations
begin
x <= a when sel = '0' else b;
end architecture;
------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity mux2x3 is
--generic declarations
port (
a, b: in std_logic(3 downto 0);
sel: in std_logic;
x: out std_logic(3 downto 0));
end entity;
------------------------------
architecture mux2x3 of mux2x3 is
--signals and declarations
--component declaration
component mux2x1 is
port (
a, b, sel: in std_logic;
x: out std_logic);
end component;
begin
--component instantiation
generate_mux2x3: for i in 0 to 2 generate
-- declarative part
comp: mux2x1 port map (a(i), b(i), sel, x(i));
end generate;
end architecture;
------------------------------
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex4;
constant CFG_MEMTECH : integer := virtex4;
constant CFG_PADTECH : integer := virtex4;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex4;
constant CFG_CLKMUL : integer := (7);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 16;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 1;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 16;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 1;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0045#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000014#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (32);
constant CFG_DDRSP_RSKEW : integer := (0);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lpus1be/izS2SWuhW2viTzHic4OhttyY+Jdb81qB5ajLJqJXDiL6kyGzbXxxLrrZBEdUV4aq/yym
DXvoUEdYvQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
APY8DyV9ShNbxKwCQSNZjqz6M4v3vfodQOwTxDKk3VxhnJr/6POXSEqElEiRQqEvyiihWl740HgU
DQS0R/ozVuXCpesdC1iTsodlldVEMOykBYdK8oUb/4EWAlDHC8Z3SsY/DCHgSsgwrlGU1xH2HZml
bL+fKRYSZs6SN2bNS3I=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
0KMeBUgxOJiQo5P2QXuYP0gVmnMKwmU+7214YIJGLLUVdvlk345NyaO+ANKFzoHcX6R9rdfDjkfK
gqxxMCg4jB2VWvxGLGlobrSjw7negNGlsSEjYi3df2Z96MBNdNyEd4p0+OzsjmLqbVsv9MIWD28p
ncMAo2yQ/OqmBDZO3XqCkoBnYnSqJXTTEdZa/jxSRZ9Zc3rpofSo5o96+8byUVyFBTazvfaezIVZ
3FVnZjRL42FBIdVn3xIqpPl4M0MVyKffE+TUQ6zvG8X3UNS5qT3uhLvUvWTHcyPuk9UZpUNL0AxO
tO0i0fK0kQr16TqvqlaJb5dV7CL/k6e+8Pemcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
IkI15iXqgW1YJbows4JJ8MgHkFBSSIXgr6rr2vKHFb11cDtYARZZfMaQMI+tpciDbEuIu1YJ8SMX
w1p4QjFpdgKaN4ceQY/0WmIEdXvsyFl0JGQWPPnw0CYo6x6H4kDZz76kahhV3o8rQc581/8m3jiA
esmrY9xM49ZhQxF59Mk=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cp6qy6HwUEre2knmw+Ykeo7Nr4bbGqj7VqV1jxVxv8yZCj8X5XzXAwkVv+MWG6oqMy9mN7ZgZ/Oy
i5g6nTreLqDqF3rpB0+2hK4gFPtpfJYmMClli5O1qYVjSxOxXAE2+Hv8WRNSO/V53uB6v4F+kn1I
IByiiCOXlSnGqXNa1WdGYWecSADVc+hV0St7lZQ8pS4I/dcegjGROjcQI6HXJqw0EryJJJGjQ+R6
xp1Nye4xSZ5FYTgeVQIGe0s/vebLO4tAR9y2w6vDUVcZakCEzsuBvxQUGzcwKTRcU9Vfmu31EwQm
uVzW58tvC9q5ulxFWU5gPHtHlE5OVnYBmhxSaw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5904)
`protect data_block
BxZ0FlUCd31XvU4dQIavgwnYuOmr0lBk8ToycaCJMMd8iPYP+MczwQa8aHGGAxdsbWWGMpAMB/k7
gbR2iElehbuILIsrnBBrPcr/3FxGf5EYp+Jxx7NYCEXlSQ9lEPZQf62lPbG0W/Kv4Fix8CcdR9ix
/ApcuXJ7FQTX5wHPHLRZfW8HPz220Nd56ryJ+XXA+ziGv8ZxoXVqeS5Wb42RRq3FMsoUviZV+hLs
zHIFi9VIg6Yn+LgTrOnWR2fInxJQXQLXWz3EHeF4q9tVq8CSmiukTxLGuFAyttkpf7zUiIThip4M
v40hq4JXkL4Nt+jhh6ucjmVXVy+mf0JZVfppMWBFFIJdewI2Nvjt43HklQJN/a6w7ghmRBZOX8sy
sO4jbYkIMuOLLxEdLh28wu1IfRGdwp7aYILweY4cwt1sbLcD6tvHElGRoqYaGVgFODN1KxysFlnK
OC7iXwcFYArXlNSuEmHxP5TV2JRbOHJG6Ovl24pUwCCmMelld98/ETVHXb0kSd3xjVRe9KfoM24s
7r1X3IOutOTArqwEiZzPUvvEXKpFt7x6oLeFt/DwgAwPp7sKmlJlI6/f1Ucq9milp/MfpmjcI1L0
GBgiiW9i98IgKhxYEAR/gNmfrFnJxvgEMe8oJntLFJBMVWO07IfssADmu5MkTJDnrV5z0S23QRSl
zq5r4cvDXa7xCPLrDDb+035W+IZW4rYK5V524HAQ62aNw0YYRncUXb6YT2UaHfncXnH/a3l0DIxh
Plun9gBkq+K3iOvipYS+pTH3N6+hXv5hytNYRDSjG+DkAscLr8G4A4y21ynHERNu9afYpxHKphDi
kdNAYG2SAZe7aKuPu8+xVsV6FD8f98sntKPXTdE0dMMOeDtRptviWrxHvWFRsqbRxSkuZVBoKAgn
iVE4iUDmUpxva+DCqfnTSyQlAC74SfVkof9kqj/16AnlxxMA23K0INkwZsczezj6L2KUeFRrEC9U
nJCI2hWUectq65HRTXC+fv75F95namWDdKFU+VisL42JbKUHuRx6oPz3x1wSQrHPZ9POiJmtxz6D
/+rGBPT82nQeORjkEX/KqVB/05pLHx0IGlrUsw+nmDa+5Be/w3TO1qOQ8So5j2O7uIUaHI29W12x
VTnXoGpTITPp3AV/iktw9NOEEQDSstlwXhn6tD2jL9qKpPW0mSZS+GU9Sy5oMV4L/2cikonf7FL+
VHuHAnMtAQpXSK531p4kxszitakLfXbB50PwmMG2JgBG7u44DLosdyDHIYNoUSDFW3tfDr0NctVu
Xf9aFOh/knWDEAOs3++tvPOhZu9spAKJQi2smt0H82VjpHzujFkAQCoRV2kBbu6AAvgky2315sny
9jmT6kbIrMB9Vj+PIffETp83lrREt8KQTEVQeqoOa0ydmqnJquT7UnzOrxmCqd3zjh4JMeCbEX2J
xgBsDoTVM6bC2S1aWEnfc9m6+HmuCTGbplTRY8qxlmjSnyQUUxgiHWpGkQIYTUZaS/12aTgQoiRO
W+WkpElTeRlWXbGRLHIGVcli3UwjD2K3n59G+MQD4qwvh/yGT6AY3mIqI+WUKom8AICYwsze6KLz
dpeHbLXA/otOmp2A/2qVbgcE/tv94lQ1Fhj1PuK+rYL8sL0v4lUKtutd2qNWEo2A5sz3Rs2ahBYN
nEen/x1BuiWOpQPcYEZBYck5S6FlUrscwJL8dfReP5QLp8t4azboDbNJnSzeiHQINya8Cb1gI0Hn
H8nC/gFYPDW3zoG1fSueZihwX9bp0oQWkwQ7JYOkKJ5HF0YHK+TIRuSKXToxac8KakIG1UTMo2LM
lPXcoVGcdmtcLoaxmRoTqIka5a3v4Y5+a8uSeWZyQv9a4Xb5NGsNdB5qCfqN/OgUUR0Ba7eQ/GiQ
0JwP7A0cwzBxYnLee2kBexBGQrwOo/jOVpS4MtnXCEkXKSfg+QaYj8AvjcXwHGU+d6NdTJ98HmbX
Y2wHkQeuZY+8iIZDR5uZaUABhFbGDSvb1hO7JIlU7KlYYpcUfgsTWSnnrdmiGD/XTvPYvi9h3Q7E
KNSVfmpYezS9cNyaHXMPVqmx7WYi9iPBZpGU3gHjA60e9fhAH2BETBF5dtVk0pYJejy5DOxuqTs2
fx1YRELHws/xWUxzlZ1smt1G3p61FW55yvfVB84Pq4kJFXcj/caTKQGJKsqG+2oLhxs0wgn45oI0
hpQ1WSCtXhcxPm1vRyx9OrgxeUqbzrCwdAVU1jMejGfVrcY3gl/6WKpmYeKaf2hDgNaxNJJaz+Y3
YGoHb9E4KA+MbH6oCO2mf9azI6ErIdmLKQT+5puImzUGQE2bTZtB2c/KIT9lbpTMpy6qPIWXGWlW
qTO5dN07I/OTpZ69mt0CMC3/L62TcWCx6vCdVjJfgQnuNOTMBL9a8+hw3U3TveA+EzknI537rM+9
6lJFfiFxxHWAZjQ2/tez+67Tks3AKwFoRooQ6z232KIgp9zOvFxm5/A6G/MTOWOlO9sUhOcW3h7h
HLxmUc4N9OFmNBcpZFOZc9QEsFHixx/jucx0ACuYiaPw8x+8/ei4bLbE5Oj9H8xgdsbhEjVXuUKA
WoEh6JpUJus1dMc3jt/1dKH+4peNWIbe8CvxUHnPkHuLVKXLRMtYz1b4TakkPUk3cOmC7QvMq8wh
ewZqYo7f08wG4bmN/dKX5EwTZJgofRJC6HkGrWtbQms+kHnFaEq1nQtm05RFOHPRvEQ6pVHxtEO3
k0rTAOqg6flaGVuLpgmOnB3K5gKz7X1W7FpAbA4fiq30Fm0hfWZjtj4pZUgY7Y4DDo20gPcUu3ix
Y5AqTTkhEQGZPllIwpXpSYU2p5fzC80Le3mA8bVz3GKMDktbeZ26v4AX3Cdh3xyJQl+lr+VB0aB4
nvJxsrt+WUzGA/KOZ3pWXF8WHwuID+hCNDbhlXYLez4CMqPlU4dYj86+p7jzaTc7gHa8svVd67JS
fhpqMTGzMnYqtKieRF3GqSkpQgIUPJNpEIoHKSfv5+W5sabZ2KWvsOX/iEczXqnY0PgQ32KVtjk+
m8SaQvcwu4mcRksykPzyJL55OcYJI5B5Lmxos1nkEaAeiviEIhK/ERkyTkA/2cBIVN338Ur/b92n
oWq+kxUaS/4aS65MyfaHsP2Vnm+reBP8IDhyTYWvA9mI8XlCEcmR5SLf9NWJ7Qv8yA0e2Koy8MHR
QHMrxtQx8Rsd5SZqRtUJxF7MOxmdbjdoNzS+7jviNG9oC3C3mDpYsF01ikzOSOd4OwN44cmhd4dB
uiZhIBLFuZti6EA2Fq32DCFlb+GBRSQXYisgKC3IMiFVclVao01ktUJh6HFH2+/yUhLNQusdsYFi
qttikVHtEMD6TLIOwJyRhtewTu4gCWZzL1BZUbV7+IRE23Y+ZDGMQsivRpt3n87FcYJDFUkTJSh7
eTXtDoxKMvenuY4sBs9zEIP8kZJgzg6UJVPmrsnpF2xx5UTVwVLV513FOOYlkFa0XuoRFlSz0nJG
PChE5s3W926O1rZVxxCiutbXzodcmY2kUzsv0UKGruAOlYaGAmos7BMK1cu/cK6QHNGtNqeYXHE2
qgAsx8xCqEh1yBNrZRvtGyZMGt3pZuxkLqZHqhQSjuosjErGqgor/b0cFzuhYm9rp6e8DnyYSHP7
Wfu8N8WtkRYkJksMpy1uE1msJzDQXGfGtR4ydYN8QRt61568zW/eIP2D6Skrdijfegat7ojzzFn4
4wLZjE++OiRs6bhPuqV7AaX+Kctl/ZEWleowvQ06sOgM2O2mrayRh3/4rTng+P6YO+usA3J+Ki+y
irLIyoXPbJZJImAAvSc5bqd9dUigwAEJGr4/Fv8QnpHKbcCa3DXOLfEKBgm/+tdAxHEuzEBvBnQa
h1Hd6rMD85koLXvnbAcFPsmQtJ/GNihkgsItH0SHAiLL/sN5Bzg7M649ovpmAHHT2YD5UMkr2CBY
5Y3nY+CK8FmAW2NgQZOZ5zzdsI4fwA1ZEuDrdH1cHkOkw1PETrv1T17gvVl2tHeZUK0Lod5AYNeu
SoT+dnw/4GQlEdlhATA/nk7Zfj6sSCLou5auDKMjJFmjUXShh1QQ55+4uNRRoPrwuiKd2tdDPpgi
DRDl/IyN6BDnq7aJsElSZ2gAEzFyjccZ59IB6xEeYatin778JpPJWZFAidkIBiqAGkEamQBPT0bn
BZr6WIQuxcpvHgxEeBoMLrWJgpGOQ9StoGRARTMXonAaSyEhemDsEzjYeuREoC4KC4WNK+8aHU+o
FvnSsEGtSIxyfdrV4HyNL+L+gtXRTy+IDHsqT8Yx0ibskrXxV6/L6KGm62grL4e+ZUnMF7yWAs/Y
m5SdY6ds0jhDK59iW2LYba5DYRvNXvgWfiHbOiE9ECzOZoggofsTpzz2iGeofSN93zV/EqBJ2LZs
nir3MLUNumdsXHQf6lyO4vCEpJVclob9sTx8/6z34waJkslQvHOVzdBkHXMdM6ZFdiY2GzQ4Wt87
rLE42mMbAkNqN5qFYUxyV5Pt3BHDctNWKeVWvbCo8khn9U/jadI/B8FqjYfE8Gw9I3OQjp/xRESI
Hwm9v41Je+qGL0fFmgda+GWhl3vK9bpzZPttmJ8Pd0ZKIjyGVCPVsOznEd2DNWuBcphj6LsX4d11
1SOfLherfUiMQGen3qgjDtr9/2tQTQOPJsqI+hnVFHe9ffONi39kRTHbMjkR+PSzlGHYSUaw93W/
BymyMLuaISQ+SRnj3KXQ8jK28XJEPLJLBXDN7XFj8HskvGvMEypWfov15UQVogdcDEUyRiG/mGqo
/Sc/vOVe4YJxW93PcVs510SNYoSZqu80MDEbqinQDFBjSJ6v/2W1slrh/L6ItCbCV1OXirNs5+kh
51BgNEr4/gZUVfKkLBJseD5xoGqUjo08ft6N5oTeXTIhc8Jb/GnCGb/a9SeFfkIL9SFrDPhg/9zW
XGyV2m3ZuU2QKiZaUpVQTmU1AvLJp44jTXkfvGNx1CkyCmj0W6+zW+JSbZckqo/6FUw9G655TS7I
Q7ROHWMu33k9vohJK/eIkrveTFK79wBk1o+nvBZvaS7AnxJ1ftOcn1yLAs+TdIp876GFK0eubZQB
T+ZjSlG0RibGq0ibaJsUM3yWW1AuHKGV0uBudxyrboLE47T2STSZgjwZGdnSZWCaKVuC5l18vyI/
A8RSSWAAcCWO0BeRCO14/lZKfmS/InUiDgIn9FsutI9IF2eoq5F4ikkneaHMDwMrkg5cxv+c4orz
8/n9M8NjVYSvNfRWYFEmA9BdTo+10/yqfus07fFyRmOSU9zwqoxEYN6tJ1PNyeMcBEOm7vvOcG60
QZ42D7LjAUnH8wbr9Cf0ODo84bPp+wx+/GL2VtqENL9zZQQ1ntmOZkUleJleZjoclbJBGp1+K0bJ
22XR03OSBJ65i+LQvym+pYuFy8QDFQipMt8/w3ZfxYofgaQoPdP1wijupVeHWO0rTg9SJ4Pt7QT7
UrQx18m5dc2Cn+JYTSDN6qXlhQk8V0090FjiRLmZKatQuBhrluvWqfIjtV7+MRB/T97nfOUwApDF
0402WfGHbfXAYA7jLpBjZi9PtBnWBADhrElTeLQNDuexXaXYV5L15B+nocZEY1SCDJG8odkNdnzV
8DH+wjTAwdVizCPTlvgVidq7jAsWJ48qEmjznaith9CRdLuIzZbsaY7oJVQS1TC3+l1CIZdkJ1BS
n3TuWgbc4B5HMU9MtrP7QGvffmATuFTf1F95N5Wef1i+QGh1ZL2gEF4jacfaGTAYLR7m69BAYu4T
LwuviMoJoYoMjvhDpogtNkYUJYOiWl4hV8ajzaZwAlzLv9DdkF/PvgC2SyKGpwbmzq5ldwVULbUs
hqD/q/q1mHX2Bks91sm52ebS+FoZlfE45U+ZU2OKrHUp4KnzFwRVbcIL5kqgcddLa/uQ+Lru60Jg
vV81YQTKbuKIEQi/ri/hu+tF5YCwC2JnvrYhX5EcgWK2br0us6Rpjn/kw3QCWsz3orJLVRj35kBL
iz9tn9ZcIsPzWflStzuQdkZNxfB6aC53NIhHol/sV33ITS7pCfnyr8ZLeb/dE2Ia5TDUivS5uWP8
evAuRbR5LpBWSE8ETWln5SXLpT1V90+mhRbmzqJ2ms4PJY1N0y9D2Nlj/bFK7Z4jjoy+zWTZSv2I
UckPCN6jAWXNyifMtKxXZ47+hj13U1eCaiy3OYstkHWSfSxk4rdjqGoDxMItRwwrPjxOEhEtFetJ
JVBAlbKNs1QmBl6N3oZvi5IcCniijhSVcDITPoB5m698mfKIXvBORfZ+WGGHwaGDl7vM1QOaZ00F
OzSPVZWI2KoLNbY5eG8v52O1VEM2Caud+E6ysd+Oc88pk6bs5yahy38Nay3xLOV0Xv8IPsW6dwC9
o7sPhKBSqP3RHeKE4iviBYIFHiOrVe8+zvxEYsX8qJAfkABFK0TBVswkCKb3wLev4crChb5Ab8Lj
Cji8PRoC7NkXfG68ozv85e9ZO0I6YAf0ZnBquQALpOpg2om+9iw3iKxRwhAKREYM80dYRtDaLpHZ
I85bJyWPBcnC8QCYgiW/XQ9tNtRrOkyzzfd4MbEqtU/DyI5C4nMA1K+v+UEVWla/VBme4UPJGkK8
7hZ8OtYOoADmV2XwNGEFtViUhGdE1Npo/PYwF37QeEMyK8lxQbggnRRwyz8R5msEGr2CrLyohzD0
ZmAxhKX/laTM7paFB6kvurKO7sufIHjMb6MWIBDLVO1kDPRNxB4wwVusO8nk+dZ1PO3iaZSTvBM1
ZmW6GrJSfymVSPZP/0rxlZwoEWa/lC5hEMPw9SR+z0ZCZMK72OlToQ7moeBX2dlGJ8gMSCB4BrHD
wCALbv5OKc5ujkzY7+HcSMWwCAa1/LxI6VB2vlxLhhfNznwsSZ8X+mJZuDIGnK3oj85++rpi0QGe
0w+gpPtOgxwkVGwSGU1icFwRvLkr3QHLZ8jLfOyIo7aezlxPx1BJAHCumXnLXhdqDLBba5WIIH0e
eqtMRBIpNKOIIkcurGidJG9gyC+rB95PEcGnpfR5G9EXITYDphGYa5Dzp7nURBJdMAWFF+uIO3r4
EJmgCZbPiHi3WsSv1H2Aj82KXEmZPL/3aHwas59p0gHgu7ePSpSKB8NQmGEAKSJdO0YLYWadeFXy
JDDpmyxC0K3Bv3LxFuylRTGM3Z+f0jRPik5SkHSmirhVUiszUIQtBCXcwHolbWxsCW43fluQJiwh
G1ZgT5iwXfPYurZnMu0rq6WmCegVeuFwbnfQTtiptwZC+zAkz1O1YSNdOtYaeNrJ9cIh8TfdujL1
y11WxOty8a+fB1OFmfg1cCaHaUGswsMSBjK68ys8OoxdUZnd9gMYL5BjqCrug0VjEDUydhp714HP
IThLO/pg/o2NlPNe8fy3W7K/E5XZQgxtcy0Pu8rA4pX+o95np55wCIbikA+r8VsUBb/Bl+Y2t4S6
ViQYk2BEJSOTbzAShpD7q0owTa0CoqiqOJ4mMfOX7WHGZ3OGZoPHaM0YtVh+nrCgRkCh/WMTmKeM
kmB3X1W551aO2OFHZWZKo+SVGRb0s9MQ/DTMhF5Q+Tby2phOhtB/3q4QhMi17ZXCkQMq893ljibm
hdaZmm3BwHv501EeIiLRM+i34YzkY2rk3cH4bq7eGi/fjhsmc/4FFwbaabfssLX1SqJJ7m7CIGNK
A0MMuVBdnLmIeBTwA7cL1GsJv5TGDkjQGYPnG4i6nlnXPzpUGuel0yQ+zpN3CbyHHqrT4/G8TcQA
ASOh4BHtupyUVWguNBhEszHiwrujHnISIXtuJlsF9GyxtwvsDRSRb7tMmwptv3HHDUHCNhpyUHsV
v7Xbl2p/6kpeqDzV4FwPTALVlYLdekE+rMQYnm7Gb3i2
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lpus1be/izS2SWuhW2viTzHic4OhttyY+Jdb81qB5ajLJqJXDiL6kyGzbXxxLrrZBEdUV4aq/yym
DXvoUEdYvQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
APY8DyV9ShNbxKwCQSNZjqz6M4v3vfodQOwTxDKk3VxhnJr/6POXSEqElEiRQqEvyiihWl740HgU
DQS0R/ozVuXCpesdC1iTsodlldVEMOykBYdK8oUb/4EWAlDHC8Z3SsY/DCHgSsgwrlGU1xH2HZml
bL+fKRYSZs6SN2bNS3I=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
0KMeBUgxOJiQo5P2QXuYP0gVmnMKwmU+7214YIJGLLUVdvlk345NyaO+ANKFzoHcX6R9rdfDjkfK
gqxxMCg4jB2VWvxGLGlobrSjw7negNGlsSEjYi3df2Z96MBNdNyEd4p0+OzsjmLqbVsv9MIWD28p
ncMAo2yQ/OqmBDZO3XqCkoBnYnSqJXTTEdZa/jxSRZ9Zc3rpofSo5o96+8byUVyFBTazvfaezIVZ
3FVnZjRL42FBIdVn3xIqpPl4M0MVyKffE+TUQ6zvG8X3UNS5qT3uhLvUvWTHcyPuk9UZpUNL0AxO
tO0i0fK0kQr16TqvqlaJb5dV7CL/k6e+8Pemcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
IkI15iXqgW1YJbows4JJ8MgHkFBSSIXgr6rr2vKHFb11cDtYARZZfMaQMI+tpciDbEuIu1YJ8SMX
w1p4QjFpdgKaN4ceQY/0WmIEdXvsyFl0JGQWPPnw0CYo6x6H4kDZz76kahhV3o8rQc581/8m3jiA
esmrY9xM49ZhQxF59Mk=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cp6qy6HwUEre2knmw+Ykeo7Nr4bbGqj7VqV1jxVxv8yZCj8X5XzXAwkVv+MWG6oqMy9mN7ZgZ/Oy
i5g6nTreLqDqF3rpB0+2hK4gFPtpfJYmMClli5O1qYVjSxOxXAE2+Hv8WRNSO/V53uB6v4F+kn1I
IByiiCOXlSnGqXNa1WdGYWecSADVc+hV0St7lZQ8pS4I/dcegjGROjcQI6HXJqw0EryJJJGjQ+R6
xp1Nye4xSZ5FYTgeVQIGe0s/vebLO4tAR9y2w6vDUVcZakCEzsuBvxQUGzcwKTRcU9Vfmu31EwQm
uVzW58tvC9q5ulxFWU5gPHtHlE5OVnYBmhxSaw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5904)
`protect data_block
BxZ0FlUCd31XvU4dQIavgwnYuOmr0lBk8ToycaCJMMd8iPYP+MczwQa8aHGGAxdsbWWGMpAMB/k7
gbR2iElehbuILIsrnBBrPcr/3FxGf5EYp+Jxx7NYCEXlSQ9lEPZQf62lPbG0W/Kv4Fix8CcdR9ix
/ApcuXJ7FQTX5wHPHLRZfW8HPz220Nd56ryJ+XXA+ziGv8ZxoXVqeS5Wb42RRq3FMsoUviZV+hLs
zHIFi9VIg6Yn+LgTrOnWR2fInxJQXQLXWz3EHeF4q9tVq8CSmiukTxLGuFAyttkpf7zUiIThip4M
v40hq4JXkL4Nt+jhh6ucjmVXVy+mf0JZVfppMWBFFIJdewI2Nvjt43HklQJN/a6w7ghmRBZOX8sy
sO4jbYkIMuOLLxEdLh28wu1IfRGdwp7aYILweY4cwt1sbLcD6tvHElGRoqYaGVgFODN1KxysFlnK
OC7iXwcFYArXlNSuEmHxP5TV2JRbOHJG6Ovl24pUwCCmMelld98/ETVHXb0kSd3xjVRe9KfoM24s
7r1X3IOutOTArqwEiZzPUvvEXKpFt7x6oLeFt/DwgAwPp7sKmlJlI6/f1Ucq9milp/MfpmjcI1L0
GBgiiW9i98IgKhxYEAR/gNmfrFnJxvgEMe8oJntLFJBMVWO07IfssADmu5MkTJDnrV5z0S23QRSl
zq5r4cvDXa7xCPLrDDb+035W+IZW4rYK5V524HAQ62aNw0YYRncUXb6YT2UaHfncXnH/a3l0DIxh
Plun9gBkq+K3iOvipYS+pTH3N6+hXv5hytNYRDSjG+DkAscLr8G4A4y21ynHERNu9afYpxHKphDi
kdNAYG2SAZe7aKuPu8+xVsV6FD8f98sntKPXTdE0dMMOeDtRptviWrxHvWFRsqbRxSkuZVBoKAgn
iVE4iUDmUpxva+DCqfnTSyQlAC74SfVkof9kqj/16AnlxxMA23K0INkwZsczezj6L2KUeFRrEC9U
nJCI2hWUectq65HRTXC+fv75F95namWDdKFU+VisL42JbKUHuRx6oPz3x1wSQrHPZ9POiJmtxz6D
/+rGBPT82nQeORjkEX/KqVB/05pLHx0IGlrUsw+nmDa+5Be/w3TO1qOQ8So5j2O7uIUaHI29W12x
VTnXoGpTITPp3AV/iktw9NOEEQDSstlwXhn6tD2jL9qKpPW0mSZS+GU9Sy5oMV4L/2cikonf7FL+
VHuHAnMtAQpXSK531p4kxszitakLfXbB50PwmMG2JgBG7u44DLosdyDHIYNoUSDFW3tfDr0NctVu
Xf9aFOh/knWDEAOs3++tvPOhZu9spAKJQi2smt0H82VjpHzujFkAQCoRV2kBbu6AAvgky2315sny
9jmT6kbIrMB9Vj+PIffETp83lrREt8KQTEVQeqoOa0ydmqnJquT7UnzOrxmCqd3zjh4JMeCbEX2J
xgBsDoTVM6bC2S1aWEnfc9m6+HmuCTGbplTRY8qxlmjSnyQUUxgiHWpGkQIYTUZaS/12aTgQoiRO
W+WkpElTeRlWXbGRLHIGVcli3UwjD2K3n59G+MQD4qwvh/yGT6AY3mIqI+WUKom8AICYwsze6KLz
dpeHbLXA/otOmp2A/2qVbgcE/tv94lQ1Fhj1PuK+rYL8sL0v4lUKtutd2qNWEo2A5sz3Rs2ahBYN
nEen/x1BuiWOpQPcYEZBYck5S6FlUrscwJL8dfReP5QLp8t4azboDbNJnSzeiHQINya8Cb1gI0Hn
H8nC/gFYPDW3zoG1fSueZihwX9bp0oQWkwQ7JYOkKJ5HF0YHK+TIRuSKXToxac8KakIG1UTMo2LM
lPXcoVGcdmtcLoaxmRoTqIka5a3v4Y5+a8uSeWZyQv9a4Xb5NGsNdB5qCfqN/OgUUR0Ba7eQ/GiQ
0JwP7A0cwzBxYnLee2kBexBGQrwOo/jOVpS4MtnXCEkXKSfg+QaYj8AvjcXwHGU+d6NdTJ98HmbX
Y2wHkQeuZY+8iIZDR5uZaUABhFbGDSvb1hO7JIlU7KlYYpcUfgsTWSnnrdmiGD/XTvPYvi9h3Q7E
KNSVfmpYezS9cNyaHXMPVqmx7WYi9iPBZpGU3gHjA60e9fhAH2BETBF5dtVk0pYJejy5DOxuqTs2
fx1YRELHws/xWUxzlZ1smt1G3p61FW55yvfVB84Pq4kJFXcj/caTKQGJKsqG+2oLhxs0wgn45oI0
hpQ1WSCtXhcxPm1vRyx9OrgxeUqbzrCwdAVU1jMejGfVrcY3gl/6WKpmYeKaf2hDgNaxNJJaz+Y3
YGoHb9E4KA+MbH6oCO2mf9azI6ErIdmLKQT+5puImzUGQE2bTZtB2c/KIT9lbpTMpy6qPIWXGWlW
qTO5dN07I/OTpZ69mt0CMC3/L62TcWCx6vCdVjJfgQnuNOTMBL9a8+hw3U3TveA+EzknI537rM+9
6lJFfiFxxHWAZjQ2/tez+67Tks3AKwFoRooQ6z232KIgp9zOvFxm5/A6G/MTOWOlO9sUhOcW3h7h
HLxmUc4N9OFmNBcpZFOZc9QEsFHixx/jucx0ACuYiaPw8x+8/ei4bLbE5Oj9H8xgdsbhEjVXuUKA
WoEh6JpUJus1dMc3jt/1dKH+4peNWIbe8CvxUHnPkHuLVKXLRMtYz1b4TakkPUk3cOmC7QvMq8wh
ewZqYo7f08wG4bmN/dKX5EwTZJgofRJC6HkGrWtbQms+kHnFaEq1nQtm05RFOHPRvEQ6pVHxtEO3
k0rTAOqg6flaGVuLpgmOnB3K5gKz7X1W7FpAbA4fiq30Fm0hfWZjtj4pZUgY7Y4DDo20gPcUu3ix
Y5AqTTkhEQGZPllIwpXpSYU2p5fzC80Le3mA8bVz3GKMDktbeZ26v4AX3Cdh3xyJQl+lr+VB0aB4
nvJxsrt+WUzGA/KOZ3pWXF8WHwuID+hCNDbhlXYLez4CMqPlU4dYj86+p7jzaTc7gHa8svVd67JS
fhpqMTGzMnYqtKieRF3GqSkpQgIUPJNpEIoHKSfv5+W5sabZ2KWvsOX/iEczXqnY0PgQ32KVtjk+
m8SaQvcwu4mcRksykPzyJL55OcYJI5B5Lmxos1nkEaAeiviEIhK/ERkyTkA/2cBIVN338Ur/b92n
oWq+kxUaS/4aS65MyfaHsP2Vnm+reBP8IDhyTYWvA9mI8XlCEcmR5SLf9NWJ7Qv8yA0e2Koy8MHR
QHMrxtQx8Rsd5SZqRtUJxF7MOxmdbjdoNzS+7jviNG9oC3C3mDpYsF01ikzOSOd4OwN44cmhd4dB
uiZhIBLFuZti6EA2Fq32DCFlb+GBRSQXYisgKC3IMiFVclVao01ktUJh6HFH2+/yUhLNQusdsYFi
qttikVHtEMD6TLIOwJyRhtewTu4gCWZzL1BZUbV7+IRE23Y+ZDGMQsivRpt3n87FcYJDFUkTJSh7
eTXtDoxKMvenuY4sBs9zEIP8kZJgzg6UJVPmrsnpF2xx5UTVwVLV513FOOYlkFa0XuoRFlSz0nJG
PChE5s3W926O1rZVxxCiutbXzodcmY2kUzsv0UKGruAOlYaGAmos7BMK1cu/cK6QHNGtNqeYXHE2
qgAsx8xCqEh1yBNrZRvtGyZMGt3pZuxkLqZHqhQSjuosjErGqgor/b0cFzuhYm9rp6e8DnyYSHP7
Wfu8N8WtkRYkJksMpy1uE1msJzDQXGfGtR4ydYN8QRt61568zW/eIP2D6Skrdijfegat7ojzzFn4
4wLZjE++OiRs6bhPuqV7AaX+Kctl/ZEWleowvQ06sOgM2O2mrayRh3/4rTng+P6YO+usA3J+Ki+y
irLIyoXPbJZJImAAvSc5bqd9dUigwAEJGr4/Fv8QnpHKbcCa3DXOLfEKBgm/+tdAxHEuzEBvBnQa
h1Hd6rMD85koLXvnbAcFPsmQtJ/GNihkgsItH0SHAiLL/sN5Bzg7M649ovpmAHHT2YD5UMkr2CBY
5Y3nY+CK8FmAW2NgQZOZ5zzdsI4fwA1ZEuDrdH1cHkOkw1PETrv1T17gvVl2tHeZUK0Lod5AYNeu
SoT+dnw/4GQlEdlhATA/nk7Zfj6sSCLou5auDKMjJFmjUXShh1QQ55+4uNRRoPrwuiKd2tdDPpgi
DRDl/IyN6BDnq7aJsElSZ2gAEzFyjccZ59IB6xEeYatin778JpPJWZFAidkIBiqAGkEamQBPT0bn
BZr6WIQuxcpvHgxEeBoMLrWJgpGOQ9StoGRARTMXonAaSyEhemDsEzjYeuREoC4KC4WNK+8aHU+o
FvnSsEGtSIxyfdrV4HyNL+L+gtXRTy+IDHsqT8Yx0ibskrXxV6/L6KGm62grL4e+ZUnMF7yWAs/Y
m5SdY6ds0jhDK59iW2LYba5DYRvNXvgWfiHbOiE9ECzOZoggofsTpzz2iGeofSN93zV/EqBJ2LZs
nir3MLUNumdsXHQf6lyO4vCEpJVclob9sTx8/6z34waJkslQvHOVzdBkHXMdM6ZFdiY2GzQ4Wt87
rLE42mMbAkNqN5qFYUxyV5Pt3BHDctNWKeVWvbCo8khn9U/jadI/B8FqjYfE8Gw9I3OQjp/xRESI
Hwm9v41Je+qGL0fFmgda+GWhl3vK9bpzZPttmJ8Pd0ZKIjyGVCPVsOznEd2DNWuBcphj6LsX4d11
1SOfLherfUiMQGen3qgjDtr9/2tQTQOPJsqI+hnVFHe9ffONi39kRTHbMjkR+PSzlGHYSUaw93W/
BymyMLuaISQ+SRnj3KXQ8jK28XJEPLJLBXDN7XFj8HskvGvMEypWfov15UQVogdcDEUyRiG/mGqo
/Sc/vOVe4YJxW93PcVs510SNYoSZqu80MDEbqinQDFBjSJ6v/2W1slrh/L6ItCbCV1OXirNs5+kh
51BgNEr4/gZUVfKkLBJseD5xoGqUjo08ft6N5oTeXTIhc8Jb/GnCGb/a9SeFfkIL9SFrDPhg/9zW
XGyV2m3ZuU2QKiZaUpVQTmU1AvLJp44jTXkfvGNx1CkyCmj0W6+zW+JSbZckqo/6FUw9G655TS7I
Q7ROHWMu33k9vohJK/eIkrveTFK79wBk1o+nvBZvaS7AnxJ1ftOcn1yLAs+TdIp876GFK0eubZQB
T+ZjSlG0RibGq0ibaJsUM3yWW1AuHKGV0uBudxyrboLE47T2STSZgjwZGdnSZWCaKVuC5l18vyI/
A8RSSWAAcCWO0BeRCO14/lZKfmS/InUiDgIn9FsutI9IF2eoq5F4ikkneaHMDwMrkg5cxv+c4orz
8/n9M8NjVYSvNfRWYFEmA9BdTo+10/yqfus07fFyRmOSU9zwqoxEYN6tJ1PNyeMcBEOm7vvOcG60
QZ42D7LjAUnH8wbr9Cf0ODo84bPp+wx+/GL2VtqENL9zZQQ1ntmOZkUleJleZjoclbJBGp1+K0bJ
22XR03OSBJ65i+LQvym+pYuFy8QDFQipMt8/w3ZfxYofgaQoPdP1wijupVeHWO0rTg9SJ4Pt7QT7
UrQx18m5dc2Cn+JYTSDN6qXlhQk8V0090FjiRLmZKatQuBhrluvWqfIjtV7+MRB/T97nfOUwApDF
0402WfGHbfXAYA7jLpBjZi9PtBnWBADhrElTeLQNDuexXaXYV5L15B+nocZEY1SCDJG8odkNdnzV
8DH+wjTAwdVizCPTlvgVidq7jAsWJ48qEmjznaith9CRdLuIzZbsaY7oJVQS1TC3+l1CIZdkJ1BS
n3TuWgbc4B5HMU9MtrP7QGvffmATuFTf1F95N5Wef1i+QGh1ZL2gEF4jacfaGTAYLR7m69BAYu4T
LwuviMoJoYoMjvhDpogtNkYUJYOiWl4hV8ajzaZwAlzLv9DdkF/PvgC2SyKGpwbmzq5ldwVULbUs
hqD/q/q1mHX2Bks91sm52ebS+FoZlfE45U+ZU2OKrHUp4KnzFwRVbcIL5kqgcddLa/uQ+Lru60Jg
vV81YQTKbuKIEQi/ri/hu+tF5YCwC2JnvrYhX5EcgWK2br0us6Rpjn/kw3QCWsz3orJLVRj35kBL
iz9tn9ZcIsPzWflStzuQdkZNxfB6aC53NIhHol/sV33ITS7pCfnyr8ZLeb/dE2Ia5TDUivS5uWP8
evAuRbR5LpBWSE8ETWln5SXLpT1V90+mhRbmzqJ2ms4PJY1N0y9D2Nlj/bFK7Z4jjoy+zWTZSv2I
UckPCN6jAWXNyifMtKxXZ47+hj13U1eCaiy3OYstkHWSfSxk4rdjqGoDxMItRwwrPjxOEhEtFetJ
JVBAlbKNs1QmBl6N3oZvi5IcCniijhSVcDITPoB5m698mfKIXvBORfZ+WGGHwaGDl7vM1QOaZ00F
OzSPVZWI2KoLNbY5eG8v52O1VEM2Caud+E6ysd+Oc88pk6bs5yahy38Nay3xLOV0Xv8IPsW6dwC9
o7sPhKBSqP3RHeKE4iviBYIFHiOrVe8+zvxEYsX8qJAfkABFK0TBVswkCKb3wLev4crChb5Ab8Lj
Cji8PRoC7NkXfG68ozv85e9ZO0I6YAf0ZnBquQALpOpg2om+9iw3iKxRwhAKREYM80dYRtDaLpHZ
I85bJyWPBcnC8QCYgiW/XQ9tNtRrOkyzzfd4MbEqtU/DyI5C4nMA1K+v+UEVWla/VBme4UPJGkK8
7hZ8OtYOoADmV2XwNGEFtViUhGdE1Npo/PYwF37QeEMyK8lxQbggnRRwyz8R5msEGr2CrLyohzD0
ZmAxhKX/laTM7paFB6kvurKO7sufIHjMb6MWIBDLVO1kDPRNxB4wwVusO8nk+dZ1PO3iaZSTvBM1
ZmW6GrJSfymVSPZP/0rxlZwoEWa/lC5hEMPw9SR+z0ZCZMK72OlToQ7moeBX2dlGJ8gMSCB4BrHD
wCALbv5OKc5ujkzY7+HcSMWwCAa1/LxI6VB2vlxLhhfNznwsSZ8X+mJZuDIGnK3oj85++rpi0QGe
0w+gpPtOgxwkVGwSGU1icFwRvLkr3QHLZ8jLfOyIo7aezlxPx1BJAHCumXnLXhdqDLBba5WIIH0e
eqtMRBIpNKOIIkcurGidJG9gyC+rB95PEcGnpfR5G9EXITYDphGYa5Dzp7nURBJdMAWFF+uIO3r4
EJmgCZbPiHi3WsSv1H2Aj82KXEmZPL/3aHwas59p0gHgu7ePSpSKB8NQmGEAKSJdO0YLYWadeFXy
JDDpmyxC0K3Bv3LxFuylRTGM3Z+f0jRPik5SkHSmirhVUiszUIQtBCXcwHolbWxsCW43fluQJiwh
G1ZgT5iwXfPYurZnMu0rq6WmCegVeuFwbnfQTtiptwZC+zAkz1O1YSNdOtYaeNrJ9cIh8TfdujL1
y11WxOty8a+fB1OFmfg1cCaHaUGswsMSBjK68ys8OoxdUZnd9gMYL5BjqCrug0VjEDUydhp714HP
IThLO/pg/o2NlPNe8fy3W7K/E5XZQgxtcy0Pu8rA4pX+o95np55wCIbikA+r8VsUBb/Bl+Y2t4S6
ViQYk2BEJSOTbzAShpD7q0owTa0CoqiqOJ4mMfOX7WHGZ3OGZoPHaM0YtVh+nrCgRkCh/WMTmKeM
kmB3X1W551aO2OFHZWZKo+SVGRb0s9MQ/DTMhF5Q+Tby2phOhtB/3q4QhMi17ZXCkQMq893ljibm
hdaZmm3BwHv501EeIiLRM+i34YzkY2rk3cH4bq7eGi/fjhsmc/4FFwbaabfssLX1SqJJ7m7CIGNK
A0MMuVBdnLmIeBTwA7cL1GsJv5TGDkjQGYPnG4i6nlnXPzpUGuel0yQ+zpN3CbyHHqrT4/G8TcQA
ASOh4BHtupyUVWguNBhEszHiwrujHnISIXtuJlsF9GyxtwvsDRSRb7tMmwptv3HHDUHCNhpyUHsV
v7Xbl2p/6kpeqDzV4FwPTALVlYLdekE+rMQYnm7Gb3i2
`protect end_protected
|
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Provides an SPI slave transmitter consisting of an input selector, a single
-- transmitter buffer, and a transmitter serializer. The data width is fixed (see
-- data_width constant value in the Globals package).
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.globals.all;
-- Note: It's not possible to use generics for both the data width and the number
-- of buffers to be generated. This would need a signal that is an array of
-- unconstrained arrays which is not yet supported by VHDL. Thus, the data width
-- is fixed (see Globals package).
entity SPI_SlaveTransmitter is
generic
(
-- The width of the address.
address_width: positive
);
port
(
-- The system clock.
clk: in std_logic;
-- Controls when the data to be transmitted are read (input is passed
-- when enable is '1', synchronous to CLK).
buffer_enable: in std_logic;
-- The clock controlling the serial data transmission.
sclk: in std_logic;
-- The (active low) slave select.
ss: in std_logic;
-- The selected address to read the data to be transmitted from.
address: in unsigned(address_width-1 downto 0);
-- The parallel inputs used to get the data to be sent from.
data_x: in data_buffer_vector((2**address_width)-1 downto 0);
-- The serial output.
miso: out std_logic
);
end entity;
architecture stdarch of SPI_SlaveTransmitter is
constant number_of_data_buffers: positive := 2**address_width;
signal selected_data, transmitter_data: data_buffer;
begin
--------------------------------------------------------------------------------
-- Instantiate components.
--------------------------------------------------------------------------------
-- The input data buffer (transparent if the enable signal is '1'; synchronous
-- to clk).
data_buffer: entity work.SPI_SlaveDataBuffer
generic map
(
width => data_width,
edge_triggered => false
)
port map
(
clk => clk,
buffer_enable => buffer_enable,
data => selected_data,
buffered_data => transmitter_data,
ready => open
);
-- The slave transmitter serializer.
serializer: entity work.SPI_SlaveTransmitterSerializer
generic map
(
width => data_width
)
port map
(
sclk => sclk,
ss => ss,
data => transmitter_data,
miso => miso
);
--------------------------------------------------------------------------------
-- Input selection logic.
--------------------------------------------------------------------------------
-- The data buffer.
input_selector: process(address, data_x) is
begin
selected_data <= (others => '1');
for i in number_of_data_buffers-1 downto 0 loop
if (address = to_unsigned(i, address_width)) then
selected_data <= data_x(i);
end if;
end loop;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1902.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s01b00x00p08n01i01902pkg is
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
constant bus_width : small_int := 7;
end c07s01b00x00p08n01i01902pkg;
use work.c07s01b00x00p08n01i01902pkg.all;
ENTITY c07s01b00x00p08n01i01902ent_a IS
port ( signal in_bus : in cmd_bus (0 to bus_width);
signal out_bus : out cmd_bus (0 to bus_width));
END c07s01b00x00p08n01i01902ent_a;
ARCHITECTURE c07s01b00x00p08n01i01902arch_a OF c07s01b00x00p08n01i01902ent_a IS
BEGIN
assert true;
END c07s01b00x00p08n01i01902arch_a;
use work.c07s01b00x00p08n01i01902pkg.all;
ENTITY c07s01b00x00p08n01i01902ent IS
END c07s01b00x00p08n01i01902ent;
ARCHITECTURE c07s01b00x00p08n01i01902arch OF c07s01b00x00p08n01i01902ent IS
constant bus_width : natural := 7;
signal s_int : small_int := 0;
signal ibus, obus, obus2 : cmd_bus(small_int);
component test
port ( signal in_bus : in cmd_bus (0 to small_int(bus_width));
signal out_bus : out cmd_bus (0 to small_int(bus_width)));
end component;
BEGIN
b: block ( s_int = 0 )
signal bool : boolean := false;
function value return small_int is
variable tmp : small_int := 0;
begin
case tmp is
when 0 =>
tmp := 0;
when others =>
tmp := 1;
end case;
return tmp;
end value;
for c : test use entity work.c07s01b00x00p08n01i01902ent_a(c07s01b00x00p08n01i0190293_arch_a);
begin
obus <= (0 => 1, others => value) after 5 ns;
s: bool <= s_int = ibus'right(1) after 5 ns;
c : test port map ( ibus, b ); -- block label illegal here
p: process ( s_int )
begin
l: for i in small_int loop
assert false
report "block label accepted as primary in a component instantiation port map expression."
severity note ;
exit l;
end loop l;
end process p;
end block b;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01902 - Block labels are not permitted as primaries in a component instantiation port map expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01902arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1902.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s01b00x00p08n01i01902pkg is
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
constant bus_width : small_int := 7;
end c07s01b00x00p08n01i01902pkg;
use work.c07s01b00x00p08n01i01902pkg.all;
ENTITY c07s01b00x00p08n01i01902ent_a IS
port ( signal in_bus : in cmd_bus (0 to bus_width);
signal out_bus : out cmd_bus (0 to bus_width));
END c07s01b00x00p08n01i01902ent_a;
ARCHITECTURE c07s01b00x00p08n01i01902arch_a OF c07s01b00x00p08n01i01902ent_a IS
BEGIN
assert true;
END c07s01b00x00p08n01i01902arch_a;
use work.c07s01b00x00p08n01i01902pkg.all;
ENTITY c07s01b00x00p08n01i01902ent IS
END c07s01b00x00p08n01i01902ent;
ARCHITECTURE c07s01b00x00p08n01i01902arch OF c07s01b00x00p08n01i01902ent IS
constant bus_width : natural := 7;
signal s_int : small_int := 0;
signal ibus, obus, obus2 : cmd_bus(small_int);
component test
port ( signal in_bus : in cmd_bus (0 to small_int(bus_width));
signal out_bus : out cmd_bus (0 to small_int(bus_width)));
end component;
BEGIN
b: block ( s_int = 0 )
signal bool : boolean := false;
function value return small_int is
variable tmp : small_int := 0;
begin
case tmp is
when 0 =>
tmp := 0;
when others =>
tmp := 1;
end case;
return tmp;
end value;
for c : test use entity work.c07s01b00x00p08n01i01902ent_a(c07s01b00x00p08n01i0190293_arch_a);
begin
obus <= (0 => 1, others => value) after 5 ns;
s: bool <= s_int = ibus'right(1) after 5 ns;
c : test port map ( ibus, b ); -- block label illegal here
p: process ( s_int )
begin
l: for i in small_int loop
assert false
report "block label accepted as primary in a component instantiation port map expression."
severity note ;
exit l;
end loop l;
end process p;
end block b;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01902 - Block labels are not permitted as primaries in a component instantiation port map expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01902arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1902.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s01b00x00p08n01i01902pkg is
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
constant bus_width : small_int := 7;
end c07s01b00x00p08n01i01902pkg;
use work.c07s01b00x00p08n01i01902pkg.all;
ENTITY c07s01b00x00p08n01i01902ent_a IS
port ( signal in_bus : in cmd_bus (0 to bus_width);
signal out_bus : out cmd_bus (0 to bus_width));
END c07s01b00x00p08n01i01902ent_a;
ARCHITECTURE c07s01b00x00p08n01i01902arch_a OF c07s01b00x00p08n01i01902ent_a IS
BEGIN
assert true;
END c07s01b00x00p08n01i01902arch_a;
use work.c07s01b00x00p08n01i01902pkg.all;
ENTITY c07s01b00x00p08n01i01902ent IS
END c07s01b00x00p08n01i01902ent;
ARCHITECTURE c07s01b00x00p08n01i01902arch OF c07s01b00x00p08n01i01902ent IS
constant bus_width : natural := 7;
signal s_int : small_int := 0;
signal ibus, obus, obus2 : cmd_bus(small_int);
component test
port ( signal in_bus : in cmd_bus (0 to small_int(bus_width));
signal out_bus : out cmd_bus (0 to small_int(bus_width)));
end component;
BEGIN
b: block ( s_int = 0 )
signal bool : boolean := false;
function value return small_int is
variable tmp : small_int := 0;
begin
case tmp is
when 0 =>
tmp := 0;
when others =>
tmp := 1;
end case;
return tmp;
end value;
for c : test use entity work.c07s01b00x00p08n01i01902ent_a(c07s01b00x00p08n01i0190293_arch_a);
begin
obus <= (0 => 1, others => value) after 5 ns;
s: bool <= s_int = ibus'right(1) after 5 ns;
c : test port map ( ibus, b ); -- block label illegal here
p: process ( s_int )
begin
l: for i in small_int loop
assert false
report "block label accepted as primary in a component instantiation port map expression."
severity note ;
exit l;
end loop l;
end process p;
end block b;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01902 - Block labels are not permitted as primaries in a component instantiation port map expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01902arch;
|
--
-- implementation of registered bool property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity bool_property is
generic(worker : worker_t; property : property_t; default : bool_t := bfalse);
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(0 downto 0);
value : out bool_t;
written : out bool_t
);
end entity;
architecture rtl of bool_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
value <= to_bool(data);
written <= btrue;
else
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- implementation of registered bool property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity bool_array_property is
generic(worker : worker_t; property : property_t; default : bool_t := bfalse);
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out bool_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of bool_array_property is
signal base : natural;begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
value(base) <= to_bool(data(0));
if nbytes_1 > 0 and property.nitems > 1 then
value(base+1) <= to_bool(data(8));
if nbytes_1 > 1 and property.nitems > 2 then
value(base+2) <= to_bool(data(16));
if nbytes_1 > 2 and property.nitems > 3 then
value(base+3) <= to_bool(data(24));
end if;
end if;
end if;
any_written <= btrue;
if base = 0 then written <= btrue; end if;
else
any_written <= bfalse;
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar <=32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_bool_property is
generic (worker : worker_t; property : property_t);
port (value : in bool_t;
data_out : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of read_bool_property is begin
data_out <= std_logic_vector(resize(shift_left(unsigned(from_bool(value)),
(property.offset rem 4)*8),
32));
end rtl;
--v
-- readback 1 bit property array
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_bool_array_property is
generic (worker : worker_t; property : property_t);
port (value : in bool_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of read_bool_array_property is
signal byte_offset : byte_offset_t;
begin
byte_offset <= resize(property.offset + index, byte_offset_t'length);
data_out <= from_bool_array(value,index,nbytes_1,byte_offset);
end rtl;
--
-- implementation of registered char property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity char_property is
generic(worker : worker_t; property : property_t; default : char_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(char_t'range);
value : out char_t;
written : out bool_t
);
end entity;
architecture rtl of char_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
value <= char_t(data);
written <= btrue;
else
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- implementation of registered char property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity char_array_property is
generic(worker : worker_t; property : property_t; default : char_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out char_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of char_array_property is
signal base : natural;
begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
value(base) <= char_t(data(7 downto 0));
if nbytes_1 > 0 and property.nitems > 1 then
value(base+1) <= char_t(data(15 downto 8));
if nbytes_1 > 1 and property.nitems > 2 then
value(base+2) <= char_t(data(23 downto 16));
if nbytes_1 > 2 and property.nitems > 3 then
value(base+3) <= char_t(data(31 downto 24));
end if;
end if;
end if;
any_written <= btrue;
if base = 0 then written <= btrue; end if;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar <=32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_char_property is
generic (worker : worker_t; property : property_t);
port (value : in char_t;
data_out : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of read_char_property is begin
data_out <= std_logic_vector(resize(shift_left(unsigned((value)),
(property.offset rem 4)*8),
32));
end rtl;
--
-- readback scalar 8 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_char_array_property is
generic (worker : worker_t; property : property_t);
port (value : in char_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of read_char_array_property is
signal i : natural;
signal word : word_t;
begin
i <= to_integer(index);
word <=
x"000000" & std_logic_vector(value(i)) when nbytes_1 = 0 else
x"0000" & std_logic_vector(value(i+1)) & std_logic_vector(value(i)) when nbytes_1 = 1 else
x"00" & std_logic_vector(value(i+2)) &
std_logic_vector(value(i+1)) & std_logic_vector(value(i)) when nbytes_1 = 2 else
std_logic_vector(value(i+3)) & std_logic_vector(value(i+2)) &
std_logic_vector(value(i+1)) & std_logic_vector(value(i));
data_out <= word_t(shift_left(unsigned(word),
((property.offset+to_integer(index)) rem 4) *8));
end rtl;
--
-- implementation of registered double property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity double_property is
generic(worker : worker_t; property : property_t; default : double_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out double_t;
written : out bool_t;
hi32 : in bool_t);
end entity;
architecture rtl of double_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
if its(hi32) then
value(63 downto 32) <= (data);
written <= btrue;
else
value(31 downto 0) <= (data);
end if;
else
written <= bfalse;
end if;
end if;
end process; end rtl;
--
-- implementation of registered double property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity double_array_property is
generic(worker : worker_t; property : property_t; default : double_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out double_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
hi32 : in bool_t);
end entity;
architecture rtl of double_array_property is
signal base : natural;begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
if its(hi32) then
value(base)(63 downto 32) <= (data);
-- for little endian machines that do a store64
if base = 0 then written <= btrue; end if;
else
value(base)(31 downto 0) <= (data);
end if;
any_written <= btrue;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar >32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_double_property is
generic (worker : worker_t; property : property_t);
port (value : in double_t;
hi32 : in bool_t;
data_out : out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of read_double_property is begin
data_out <= std_logic_vector(value(63 downto 32)) when its(hi32)
else std_logic_vector(value(31 downto 0));
end rtl;
--
-- readback scalar 64 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_double_array_property is
generic (worker : worker_t; property : property_t);
port (value : in double_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
hi32 : in bool_t);
end entity;
architecture rtl of read_double_array_property is
signal i : natural;
begin
i <= to_integer(index);
data_out <= std_logic_vector(value(i)(63 downto 32)) when its(hi32) else
std_logic_vector(value(i)(31 downto 0));
end rtl;
--
-- implementation of registered float property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity float_property is
generic(worker : worker_t; property : property_t; default : float_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(float_t'range);
value : out float_t;
written : out bool_t
);
end entity;
architecture rtl of float_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
value <= float_t(data);
written <= btrue;
else
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- implementation of registered float property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity float_array_property is
generic(worker : worker_t; property : property_t; default : float_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out float_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of float_array_property is
signal base : natural;
begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
value(base) <= float_t(data);
any_written <= btrue;
if base = 0 then written <= btrue; end if;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar <=32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_float_property is
generic (worker : worker_t; property : property_t);
port (value : in float_t;
data_out : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of read_float_property is begin
data_out <= std_logic_vector(resize(shift_left(unsigned((value)),
(property.offset rem 4)*8),
32));
end rtl;
--
-- readback scalar 16 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_float_array_property is
generic (worker : worker_t; property : property_t);
port (value : in float_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of read_float_array_property is
begin
data_out <= std_logic_vector(value(to_integer(index)));
end rtl;
--
-- implementation of registered short property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity short_property is
generic(worker : worker_t; property : property_t; default : short_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(short_t'range);
value : out short_t;
written : out bool_t
);
end entity;
architecture rtl of short_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
value <= short_t(data);
written <= btrue;
else
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- implementation of registered short property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity short_array_property is
generic(worker : worker_t; property : property_t; default : short_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out short_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of short_array_property is
signal base : natural;
begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
value(base) <= short_t(data(15 downto 0));
if nbytes_1 > 1 and property.nitems > 1 then
value(base+1) <= short_t(data(31 downto 16));
end if;
any_written <= btrue;
if base = 0 then written <= btrue; end if;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar <=32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_short_property is
generic (worker : worker_t; property : property_t);
port (value : in short_t;
data_out : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of read_short_property is begin
data_out <= std_logic_vector(resize(shift_left(unsigned((value)),
(property.offset rem 4)*8),
32));
end rtl;
--
-- readback scalar 16 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_short_array_property is
generic (worker : worker_t; property : property_t);
port (value : in short_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of read_short_array_property is
signal i : natural;
begin
i <= to_integer(index);
data_out <=
std_logic_vector(value(i)) & x"0000" when (to_integer(index) + property.offset/2) rem 2 = 1 else
x"0000" & std_logic_vector(value(i)) when nbytes_1 = 1 else
std_logic_vector(value(i+1)) & std_logic_vector(value(i));
end rtl;
--
-- implementation of registered long property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity long_property is
generic(worker : worker_t; property : property_t; default : long_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(long_t'range);
value : out long_t;
written : out bool_t
);
end entity;
architecture rtl of long_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
value <= long_t(data);
written <= btrue;
else
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- implementation of registered long property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity long_array_property is
generic(worker : worker_t; property : property_t; default : long_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out long_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of long_array_property is
signal base : natural;
begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
value(base) <= long_t(data);
any_written <= btrue;
if base = 0 then written <= btrue; end if;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar <=32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_long_property is
generic (worker : worker_t; property : property_t);
port (value : in long_t;
data_out : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of read_long_property is begin
data_out <= std_logic_vector(resize(shift_left(unsigned((value)),
(property.offset rem 4)*8),
32));
end rtl;
--
-- readback scalar 16 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_long_array_property is
generic (worker : worker_t; property : property_t);
port (value : in long_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of read_long_array_property is
begin
data_out <= std_logic_vector(value(to_integer(index)));
end rtl;
--
-- implementation of registered uchar property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity uchar_property is
generic(worker : worker_t; property : property_t; default : uchar_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(uchar_t'range);
value : out uchar_t;
written : out bool_t
);
end entity;
architecture rtl of uchar_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
value <= uchar_t(data);
written <= btrue;
else
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- implementation of registered uchar property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity uchar_array_property is
generic(worker : worker_t; property : property_t; default : uchar_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out uchar_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of uchar_array_property is
signal base : natural;
begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
value(base) <= uchar_t(data(7 downto 0));
if nbytes_1 > 0 and property.nitems > 1 then
value(base+1) <= uchar_t(data(15 downto 8));
if nbytes_1 > 1 and property.nitems > 2 then
value(base+2) <= uchar_t(data(23 downto 16));
if nbytes_1 > 2 and property.nitems > 3 then
value(base+3) <= uchar_t(data(31 downto 24));
end if;
end if;
end if;
any_written <= btrue;
if base = 0 then written <= btrue; end if;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar <=32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_uchar_property is
generic (worker : worker_t; property : property_t);
port (value : in uchar_t;
data_out : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of read_uchar_property is begin
data_out <= std_logic_vector(resize(shift_left(unsigned((value)),
(property.offset rem 4)*8),
32));
end rtl;
--
-- readback scalar 8 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_uchar_array_property is
generic (worker : worker_t; property : property_t);
port (value : in uchar_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of read_uchar_array_property is
signal i : natural;
signal word : word_t;
begin
i <= to_integer(index);
word <=
x"000000" & std_logic_vector(value(i)) when nbytes_1 = 0 else
x"0000" & std_logic_vector(value(i+1)) & std_logic_vector(value(i)) when nbytes_1 = 1 else
x"00" & std_logic_vector(value(i+2)) &
std_logic_vector(value(i+1)) & std_logic_vector(value(i)) when nbytes_1 = 2 else
std_logic_vector(value(i+3)) & std_logic_vector(value(i+2)) &
std_logic_vector(value(i+1)) & std_logic_vector(value(i));
data_out <= word_t(shift_left(unsigned(word),
((property.offset+to_integer(index)) rem 4) *8));
end rtl;
--
-- implementation of registered ulong property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity ulong_property is
generic(worker : worker_t; property : property_t; default : ulong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(ulong_t'range);
value : out ulong_t;
written : out bool_t
);
end entity;
architecture rtl of ulong_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
value <= ulong_t(data);
written <= btrue;
else
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- implementation of registered ulong property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity ulong_array_property is
generic(worker : worker_t; property : property_t; default : ulong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out ulong_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of ulong_array_property is
signal base : natural;
begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
value(base) <= ulong_t(data);
any_written <= btrue;
if base = 0 then written <= btrue; end if;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar <=32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_ulong_property is
generic (worker : worker_t; property : property_t);
port (value : in ulong_t;
data_out : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of read_ulong_property is begin
data_out <= std_logic_vector(resize(shift_left(unsigned((value)),
(property.offset rem 4)*8),
32));
end rtl;
--
-- readback scalar 16 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_ulong_array_property is
generic (worker : worker_t; property : property_t);
port (value : in ulong_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of read_ulong_array_property is
begin
data_out <= std_logic_vector(value(to_integer(index)));
end rtl;
--
-- implementation of registered ushort property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity ushort_property is
generic(worker : worker_t; property : property_t; default : ushort_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(ushort_t'range);
value : out ushort_t;
written : out bool_t
);
end entity;
architecture rtl of ushort_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
value <= ushort_t(data);
written <= btrue;
else
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- implementation of registered ushort property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity ushort_array_property is
generic(worker : worker_t; property : property_t; default : ushort_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out ushort_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of ushort_array_property is
signal base : natural;
begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
value(base) <= ushort_t(data(15 downto 0));
if nbytes_1 > 1 and property.nitems > 1 then
value(base+1) <= ushort_t(data(31 downto 16));
end if;
any_written <= btrue;
if base = 0 then written <= btrue; end if;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar <=32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_ushort_property is
generic (worker : worker_t; property : property_t);
port (value : in ushort_t;
data_out : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of read_ushort_property is begin
data_out <= std_logic_vector(resize(shift_left(unsigned((value)),
(property.offset rem 4)*8),
32));
end rtl;
--
-- readback scalar 16 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_ushort_array_property is
generic (worker : worker_t; property : property_t);
port (value : in ushort_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of read_ushort_array_property is
signal i : natural;
begin
i <= to_integer(index);
data_out <=
std_logic_vector(value(i)) & x"0000" when (to_integer(index) + property.offset/2) rem 2 = 1 else
x"0000" & std_logic_vector(value(i)) when nbytes_1 = 1 else
std_logic_vector(value(i+1)) & std_logic_vector(value(i));
end rtl;
--
-- implementation of registered longlong property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity longlong_property is
generic(worker : worker_t; property : property_t; default : longlong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out longlong_t;
written : out bool_t;
hi32 : in bool_t);
end entity;
architecture rtl of longlong_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
if its(hi32) then
value(63 downto 32) <= signed(data);
written <= btrue;
else
value(31 downto 0) <= signed(data);
end if;
else
written <= bfalse;
end if;
end if;
end process; end rtl;
--
-- implementation of registered longlong property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity longlong_array_property is
generic(worker : worker_t; property : property_t; default : longlong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out longlong_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
hi32 : in bool_t);
end entity;
architecture rtl of longlong_array_property is
signal base : natural;begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
if its(hi32) then
value(base)(63 downto 32) <= signed(data);
-- for little endian machines that do a store64
if base = 0 then written <= btrue; end if;
else
value(base)(31 downto 0) <= signed(data);
end if;
any_written <= btrue;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar >32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_longlong_property is
generic (worker : worker_t; property : property_t);
port (value : in longlong_t;
hi32 : in bool_t;
data_out : out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of read_longlong_property is begin
data_out <= std_logic_vector(value(63 downto 32)) when its(hi32)
else std_logic_vector(value(31 downto 0));
end rtl;
--
-- readback scalar 64 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_longlong_array_property is
generic (worker : worker_t; property : property_t);
port (value : in longlong_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
hi32 : in bool_t);
end entity;
architecture rtl of read_longlong_array_property is
signal i : natural;
begin
i <= to_integer(index);
data_out <= std_logic_vector(value(i)(63 downto 32)) when its(hi32) else
std_logic_vector(value(i)(31 downto 0));
end rtl;
--
-- implementation of registered ulonglong property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity ulonglong_property is
generic(worker : worker_t; property : property_t; default : ulonglong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out ulonglong_t;
written : out bool_t;
hi32 : in bool_t);
end entity;
architecture rtl of ulonglong_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
if its(hi32) then
value(63 downto 32) <= unsigned(data);
written <= btrue;
else
value(31 downto 0) <= unsigned(data);
end if;
else
written <= bfalse;
end if;
end if;
end process; end rtl;
--
-- implementation of registered ulonglong property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity ulonglong_array_property is
generic(worker : worker_t; property : property_t; default : ulonglong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out ulonglong_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
hi32 : in bool_t);
end entity;
architecture rtl of ulonglong_array_property is
signal base : natural;begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
if its(hi32) then
value(base)(63 downto 32) <= unsigned(data);
-- for little endian machines that do a store64
if base = 0 then written <= btrue; end if;
else
value(base)(31 downto 0) <= unsigned(data);
end if;
any_written <= btrue;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar >32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_ulonglong_property is
generic (worker : worker_t; property : property_t);
port (value : in ulonglong_t;
hi32 : in bool_t;
data_out : out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of read_ulonglong_property is begin
data_out <= std_logic_vector(value(63 downto 32)) when its(hi32)
else std_logic_vector(value(31 downto 0));
end rtl;
--
-- readback scalar 64 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_ulonglong_array_property is
generic (worker : worker_t; property : property_t);
port (value : in ulonglong_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
hi32 : in bool_t);
end entity;
architecture rtl of read_ulonglong_array_property is
signal i : natural;
begin
i <= to_integer(index);
data_out <= std_logic_vector(value(i)(63 downto 32)) when its(hi32) else
std_logic_vector(value(i)(31 downto 0));
end rtl;
--
-- implementation of registered string property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity string_property is
generic(worker : worker_t; property : property_t; default : string_t := ("00000000","00000000"));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out string_t(0 to property.string_length);
written : out bool_t;
offset : in unsigned(worker.decode_width-1 downto 0));
end entity;
architecture rtl of string_property is
signal base : natural;begin
base <= to_integer(offset);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => to_signed(0,char_t'length));
written <= bfalse;
elsif its(write_enable) then
value (base to base + 3) <= to_string(data);
written <= btrue;
else
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- implementation of registered string property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity string_array_property is
generic(worker : worker_t; property : property_t; default : string_array_t := (("00000000","00000000"),("00000000","00000000")));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out string_array_t(0 to property.nitems-1,
0 to (property.string_length+4)/4*4-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
offset : in unsigned(worker.decode_width-1 downto 0));
end entity;
--
-- readback string property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_string_property is
generic (worker : worker_t; property : property_t);
port (value : in string_t;
data_out : out std_logic_vector(31 downto 0);
offset : in unsigned(worker.decode_width-1 downto 0));
end entity;
architecture rtl of read_string_property is begin
data_out <= from_string(value, offset);
end rtl;
--
-- readback scalar string property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_string_array_property is
generic (worker : worker_t; property : property_t);
port (value : in string_array_t(0 to property.nitems-1,
0 to (property.string_length+4)/4*4-1);
data_out : out std_logic_vector(31 downto 0);
offset : in unsigned(worker.decode_width-1 downto 0));
end entity;
architecture rtl of string_array_property is
constant nwords : natural := (property.string_length+4)/4;
subtype string_words_t is data_a_t(0 to nwords * property.nitems-1);
signal string_words : string_words_t;
begin
gen: for i in 0 to property.nitems-1 generate -- properties'left to 0 generate
gen1: for j in 0 to nwords-1 generate
gen2: for k in 0 to 3 generate
value(i,j*4+k) <= signed(string_words(i*nwords + j)(k*8+7 downto k*8));
end generate gen2;
end generate gen1;
end generate gen;
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
string_words(0) <= (others => '0');
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
string_words(to_integer(offset) / 4) <= data;
written <= btrue;
if to_integer(offset) = 0 then
any_written <= btrue;
end if;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
architecture rtl of read_string_array_property is
constant nwords : natural := (property.string_length+4)/4;
subtype string_words_t is data_a_t(0 to nwords * property.nitems-1);
signal string_words : string_words_t;
begin
gen: for i in 0 to property.nitems-1 generate -- properties'left to 0 generate
gen1: for j in 0 to nwords-1 generate
gen2: for k in 0 to 3 generate
string_words(i*nwords + j)(k*8+7 downto k*8) <= std_logic_vector(value(i,j*4+k));
end generate gen2;
end generate gen1;
end generate gen;
data_out <= string_words(to_integer(offset)/4);
end rtl;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Product_Generator_GF_2_M
-- Module Name: Product_Generator_GF_2_M
-- Project Name: GF_2_M Arithmetic
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This circuit is part of the GF(2^m) multiplier.
-- This circuit generates the partial product to be latter used in the multiplier.
-- This version is for primitive polynomials present on IEEE 13009 cryptographic standard.
--
-- The circuits parameters
--
-- m :
--
-- The size of the field used in this circuit.
--
-- value :
--
-- Used to select the partial product generated by this circuit of
-- o = a * x^(value)
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity product_generator_gf_2_m is
Generic(
value : integer;
m : integer range 2 to 20
);
Port (
a : in STD_LOGIC_VECTOR ((m - 1) downto 0);
o : out STD_LOGIC_VECTOR ((m - 1) downto 0)
);
end product_generator_gf_2_m;
architecture IEEE_POLYNOMIALS of product_generator_gf_2_m is
constant final_value : integer := value mod m;
begin
GF_2_2 : if m = 2 generate -- x^2 + x^1 + 1
GF_2_2_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_2_P_1 : if final_value = 1 generate
o <= ( (a(0) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_3 : if m = 3 generate -- x^3 + x^1 + 1
GF_2_3_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_3_P_1 : if final_value = 1 generate
o <= ( a(1) & (a(0) xor a(2)) & a(2) );
end generate;
GF_2_3_P_2 : if final_value = 2 generate
o <= ( (a(0) xor a(2)) & (a(2) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_4 : if m = 4 generate -- x^4 + x^1 + 1
GF_2_4_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_4_P_1 : if final_value = 1 generate
o <= ( a(2 downto 1) & (a(0) xor a(3)) & a(3) );
end generate;
GF_2_4_P_2 : if final_value = 2 generate
o <= ( a(1) & (a(0) xor a(3)) & (a(3) xor a(2)) & a(2) );
end generate;
GF_2_4_P_3 : if final_value = 3 generate
o <= ( (a(0) xor a(3)) & (a(3) xor a(2)) & (a(2) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_5 : if m = 5 generate -- x^5 + x^2 + 1
GF_2_5_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_5_P_1 : if final_value = 1 generate
o <= ( a(3) & a(2) & (a(1) xor a(4)) & a(0) & a(4) );
end generate;
GF_2_5_P_2 : if final_value = 2 generate
o <= ( a(2) & (a(1) xor a(4)) & (a(0) xor a(3)) & a(4) & a(3) );
end generate;
GF_2_5_P_3 : if final_value = 3 generate
o <= ( (a(1) xor a(4)) & (a(0) xor a(3)) & (a(4) xor a(2)) & a(3) & a(2) );
end generate;
GF_2_5_P_4 : if final_value = 4 generate
o <= ( (a(0) xor a(3)) & (a(4) xor a(2)) & (a(3) xor a(1) xor a(4)) & a(2) & (a(1) xor a(4)) );
end generate;
end generate;
GF_2_6 : if m = 6 generate -- x^6 + x^1 + 1
GF_2_6_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_6_P_1 : if final_value = 1 generate
o <= ( a(4) & a(3) & a(2) & a(1) & (a(0) xor a(5)) & a(5) );
end generate;
GF_2_6_P_2 : if final_value = 2 generate
o <= ( a(3) & a(2) & a(1) & (a(0) xor a(5)) & (a(5) xor a(4)) & a(4) );
end generate;
GF_2_6_P_3 : if final_value = 3 generate
o <= ( a(2) & a(1) & (a(0) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & a(3) );
end generate;
GF_2_6_P_4 : if final_value = 4 generate
o <= ( a(1) & (a(0) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & a(2) );
end generate;
GF_2_6_P_5 : if final_value = 5 generate
o <= ( (a(0) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & (a(2) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_7 : if m = 7 generate -- x^7 + x^1 + 1
GF_2_7_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_7_P_1 : if final_value = 1 generate
o <= ( a(5) & a(4) & a(3) & a(2) & a(1) & (a(0) xor a(6)) & a(6) );
end generate;
GF_2_7_P_2 : if final_value = 2 generate
o <= ( a(4) & a(3) & a(2) & a(1) & (a(0) xor a(6)) & (a(6) xor a(5)) & a(5) );
end generate;
GF_2_7_P_3 : if final_value = 3 generate
o <= ( a(3) & a(2) & a(1) & (a(0) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & a(4) );
end generate;
GF_2_7_P_4 : if final_value = 4 generate
o <= ( a(2) & a(1) & (a(0) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & a(3) );
end generate;
GF_2_7_P_5 : if final_value = 5 generate
o <= ( a(1) & (a(0) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & a(2) );
end generate;
GF_2_7_P_6 : if final_value = 6 generate
o <= ( (a(0) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & (a(2) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_8 : if m = 8 generate -- x^8 + x^4 + x^3 + x^1 + 1
GF_2_8_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_8_P_1 : if final_value = 1 generate
o <= ( a(6) & a(5) & a(4) & (a(3) xor a(7)) & (a(2) xor a(7)) & a(1) & (a(0) xor a(7)) & a(7) );
end generate;
GF_2_8_P_2 : if final_value = 2 generate
o <= ( a(5) & a(4) & (a(3) xor a(7)) & ((a(2) xor a(7)) xor a(6)) & (a(1) xor a(6)) & (a(0) xor a(7)) & (a(7) xor a(6)) & a(6) );
end generate;
GF_2_8_P_3 : if final_value = 3 generate
o <= ( a(4) & (a(3) xor a(7)) & (a(2) xor a(7) xor a(6)) & (a(1) xor a(6) xor a(5)) & (a(0) xor a(7) xor a(5)) & (a(7) xor a(6)) & (a(6) xor a(5)) & a(5) );
end generate;
GF_2_8_P_4 : if final_value = 4 generate
o <= ( (a(3) xor a(7)) & (a(2) xor a(7) xor a(6)) & (a(1) xor a(6) xor a(5)) & (a(0) xor a(7) xor a(5) xor a(4)) & (a(7) xor a(6) xor a(4)) & (a(6) xor a(5)) & (a(5) xor a(4)) & a(4) );
end generate;
GF_2_8_P_5 : if final_value = 5 generate
o <= ( (a(2) xor a(7) xor a(6)) & (a(1) xor a(6) xor a(5)) & (a(0) xor a(7) xor a(5) xor a(4)) & (a(6) xor a(4) xor a(3)) & (a(6) xor a(5) xor a(3) xor a(7)) & (a(5) xor a(4)) & (a(4) xor a(3) xor a(7)) & (a(3) xor a(7)) );
end generate;
GF_2_8_P_6 : if final_value = 6 generate
o <= ( (a(1) xor a(6) xor a(5)) & (a(0) xor a(7) xor a(5) xor a(4)) & (a(6) xor a(4) xor a(3)) & (a(5) xor a(3) xor a(2)) & (a(5) xor a(4) xor a(2) xor a(7) xor a(6)) & (a(4) xor a(3) xor a(7)) & (a(3) xor a(2) xor a(6)) & (a(2) xor a(7) xor a(6)) );
end generate;
GF_2_8_P_7 : if final_value = 7 generate
o <= ( (a(0) xor a(7) xor a(5) xor a(4)) & (a(6) xor a(4) xor a(3)) & (a(5) xor a(3) xor a(2)) & (a(4) xor a(2) xor a(7) xor a(1)) & (a(4) xor a(3) xor a(7) xor a(1) xor a(6) xor a(5)) & (a(3) xor a(2) xor a(6)) & (a(2) xor a(7) xor a(1) xor a(5)) & (a(1) xor a(6) xor a(5)) );
end generate;
end generate;
GF_2_9 : if m = 9 generate -- x^9 + x^1 + 1
GF_2_9_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_9_P_1 : if final_value = 1 generate
o <= ( a(7) & a(6) & a(5) & a(4) & a(3) & a(2) & a(1) & (a(0) xor a(8)) & a(8) );
end generate;
GF_2_9_P_2 : if final_value = 2 generate
o <= ( a(6) & a(5) & a(4) & a(3) & a(2) & a(1) & (a(0) xor a(8)) & (a(8) xor a(7)) & a(7) );
end generate;
GF_2_9_P_3 : if final_value = 3 generate
o <= ( a(5) & a(4) & a(3) & a(2) & a(1) & (a(0) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & a(6) );
end generate;
GF_2_9_P_4 : if final_value = 4 generate
o <= ( a(4) & a(3) & a(2) & a(1) & (a(0) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & a(5) );
end generate;
GF_2_9_P_5 : if final_value = 5 generate
o <= ( a(3) & a(2) & a(1) & (a(0) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & a(4) );
end generate;
GF_2_9_P_6 : if final_value = 6 generate
o <= ( a(2) & a(1) & (a(0) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & a(3) );
end generate;
GF_2_9_P_7 : if final_value = 7 generate
o <= ( a(1) & (a(0) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & a(2) );
end generate;
GF_2_9_P_8 : if final_value = 8 generate
o <= ( (a(0) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & (a(2) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_10 : if m = 10 generate -- x^10 + x^3 + 1
GF_2_10_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_10_P_1 : if final_value = 1 generate
o <= ( a(8) & a(7) & a(6) & a(5) & a(4) & a(3) & (a(2) xor a(9)) & a(1) & a(0) & a(9) );
end generate;
GF_2_10_P_2 : if final_value = 2 generate
o <= ( a(7) & a(6) & a(5) & a(4) & a(3) & (a(2) xor a(9)) & (a(1) xor a(8)) & a(0) & a(9) & a(8) );
end generate;
GF_2_10_P_3 : if final_value = 3 generate
o <= ( a(6) & a(5) & a(4) & a(3) & (a(2) xor a(9)) & (a(1) xor a(8)) & (a(0) xor a(7)) & a(9) & a(8) & a(7) );
end generate;
GF_2_10_P_4 : if final_value = 4 generate
o <= ( a(5) & a(4) & a(3) & (a(2) xor a(9)) & (a(1) xor a(8)) & (a(0) xor a(7)) & (a(9) xor a(6)) & a(8) & a(7) & a(6) );
end generate;
GF_2_10_P_5 : if final_value = 5 generate
o <= ( a(4) & a(3) & (a(2) xor a(9)) & (a(1) xor a(8)) & (a(0) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & a(7) & a(6) & a(5) );
end generate;
GF_2_10_P_6 : if final_value = 6 generate
o <= ( a(3) & (a(2) xor a(9)) & (a(1) xor a(8)) & (a(0) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & a(6) & a(5) & a(4) );
end generate;
GF_2_10_P_7 : if final_value = 7 generate
o <= ( (a(2) xor a(9)) & (a(1) xor a(8)) & (a(0) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & a(5) & a(4) & a(3) );
end generate;
GF_2_10_P_8 : if final_value = 8 generate
o <= ( (a(1) xor a(8)) & (a(0) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(9)) & a(4) & a(3) & (a(2) xor a(9)) );
end generate;
GF_2_10_P_9 : if final_value = 9 generate
o <= ( (a(0) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(9)) & (a(4) xor a(1) xor a(8)) & a(3) & (a(2) xor a(9)) & (a(1) xor a(8)) );
end generate;
end generate;
GF_2_11 : if m = 11 generate -- x^11 + x^2 + 1
GF_2_11_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_11_P_1 : if final_value = 1 generate
o <= ( a(9 downto 2) & (a(1) xor a(10)) & a(0) & a(10) );
end generate;
GF_2_11_P_2 : if final_value = 2 generate
o <= ( a(8 downto 2) & (a(1) xor a(10)) & (a(0) xor a(9)) & a(10) & a(9) );
end generate;
GF_2_11_P_3 : if final_value = 3 generate
o <= ( a(7 downto 2) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & a(9) & a(8) );
end generate;
GF_2_11_P_4 : if final_value = 4 generate
o <= ( a(6 downto 2) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & a(8) & a(7) );
end generate;
GF_2_11_P_5 : if final_value = 5 generate
o <= ( a(5 downto 2) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & (a(8) xor a(6)) & a(7) & a(6) );
end generate;
GF_2_11_P_6 : if final_value = 6 generate
o <= ( a(4 downto 2) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & (a(8) xor a(6)) & (a(7) xor a(5)) & a(6) & a(5) );
end generate;
GF_2_11_P_7 : if final_value = 7 generate
o <= ( a(3 downto 2) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & (a(8) xor a(6)) & (a(7) xor a(5)) & (a(6) xor a(4)) & a(5) & a(4) );
end generate;
GF_2_11_P_8 : if final_value = 8 generate
o <= ( a(2) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & (a(8) xor a(6)) & (a(7) xor a(5)) & (a(6) xor a(4)) & (a(5) xor a(3)) & a(4) & a(3) );
end generate;
GF_2_11_P_9 : if final_value = 9 generate
o <= ( (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & (a(8) xor a(6)) & (a(7) xor a(5)) & (a(6) xor a(4)) & (a(5) xor a(3)) & (a(4) xor a(2)) & a(3) & a(2) );
end generate;
GF_2_11_P_10 : if final_value = 10 generate
o <= ( (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & (a(8) xor a(6)) & (a(7) xor a(5)) & (a(6) xor a(4)) & (a(5) xor a(3)) & (a(4) xor a(2)) & (a(3) xor a(1) xor a(10)) & a(2) & (a(1) xor a(10)) );
end generate;
end generate;
GF_2_12 : if m = 12 generate -- x^12 + x^3 + 1
GF_2_12_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_12_P_1 : if final_value = 1 generate
o <= ( a(10 downto 3) & (a(2) xor a(11)) & a(1) & a(0) & a(11) );
end generate;
GF_2_12_P_2 : if final_value = 2 generate
o <= ( a(9 downto 3) & (a(2) xor a(11)) & (a(1) xor a(10)) & a(0) & a(11) & a(10) );
end generate;
GF_2_12_P_3 : if final_value = 3 generate
o <= ( a(8 downto 3) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & a(11) & a(10) & a(9) );
end generate;
GF_2_12_P_4 : if final_value = 4 generate
o <= ( a(7 downto 3) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(11) xor a(8)) & a(10) & a(9) & a(8) );
end generate;
GF_2_12_P_5 : if final_value = 5 generate
o <= ( a(6 downto 3) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & a(9) & a(8) & a(7) );
end generate;
GF_2_12_P_6 : if final_value = 6 generate
o <= ( a(5 downto 3) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & a(8) & a(7) & a(6) );
end generate;
GF_2_12_P_7 : if final_value = 7 generate
o <= ( a(4 downto 3) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & a(7) & a(6) & a(5) );
end generate;
GF_2_12_P_8 : if final_value = 8 generate
o <= ( a(3) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & a(6) & a(5) & a(4) );
end generate;
GF_2_12_P_9 : if final_value = 9 generate
o <= ( (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & a(5) & a(4) & a(3) );
end generate;
GF_2_12_P_10 : if final_value = 10 generate
o <= ( (a(1) xor a(10)) & (a(0) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(11)) & a(4) & a(3) & (a(2) xor a(11)) );
end generate;
GF_2_12_P_11 : if final_value = 11 generate
o <= ( (a(0) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(11)) & (a(4) xor a(1) xor a(10)) & a(3) & (a(2) xor a(11)) & (a(1) xor a(10)) );
end generate;
end generate;
GF_2_13 : if m = 13 generate -- x^13 + x^4 + x^3 + x^1 + 1
GF_2_13_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_13_P_1 : if final_value = 1 generate
o <= ( a(11 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12)) & a(1) & (a(0) xor a(12)) & a(12) );
end generate;
GF_2_13_P_2 : if final_value = 2 generate
o <= ( a(10 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11)) & (a(0) xor a(12)) & (a(12) xor a(11)) & a(11) );
end generate;
GF_2_13_P_3 : if final_value = 3 generate
o <= ( a(9 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10)) & (a(12) xor a(11)) & (a(11) xor a(10)) & a(10) );
end generate;
GF_2_13_P_4 : if final_value = 4 generate
o <= ( a(8 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9)) & (a(11) xor a(10)) & (a(10) xor a(9)) & a(9) );
end generate;
GF_2_13_P_5 : if final_value = 5 generate
o <= ( a(7 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8)) & (a(10) xor a(9)) & (a(9) xor a(8)) & a(8) );
end generate;
GF_2_13_P_6 : if final_value = 6 generate
o <= ( a(6 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7)) & (a(9) xor a(8)) & (a(8) xor a(7)) & a(7) );
end generate;
GF_2_13_P_7 : if final_value = 7 generate
o <= ( a(5 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7) xor a(6)) & (a(9) xor a(8) xor a(6)) & (a(8) xor a(7)) & (a(7) xor a(6)) & a(6) );
end generate;
GF_2_13_P_8 : if final_value = 8 generate
o <= ( a(4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7) xor a(6)) & (a(9) xor a(8) xor a(6) xor a(5)) & (a(8) xor a(7) xor a(5)) & (a(7) xor a(6)) & (a(6) xor a(5)) & a(5) );
end generate;
GF_2_13_P_9 : if final_value = 9 generate
o <= ( (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7) xor a(6)) & (a(9) xor a(8) xor a(6) xor a(5)) & (a(8) xor a(7) xor a(5) xor a(4)) & (a(7) xor a(6) xor a(4)) & (a(6) xor a(5)) & (a(5) xor a(4)) & a(4) );
end generate;
GF_2_13_P_10 : if final_value = 10 generate
o <= ( (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7) xor a(6)) & (a(9) xor a(8) xor a(6) xor a(5)) & (a(8) xor a(7) xor a(5) xor a(4)) & (a(7) xor a(6) xor a(4) xor a(3) xor a(12)) & (a(6) xor a(5) xor a(3) xor a(12)) & (a(5) xor a(4)) & (a(4) xor a(3) xor a(12)) & (a(3) xor a(12)) );
end generate;
GF_2_13_P_11 : if final_value = 11 generate
o <= ( (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7) xor a(6)) & (a(9) xor a(8) xor a(6) xor a(5)) & (a(8) xor a(7) xor a(5) xor a(4)) & (a(7) xor a(6) xor a(4) xor a(3) xor a(12)) & (a(6) xor a(5) xor a(3) xor a(2) xor a(11)) & (a(5) xor a(4) xor a(2) xor a(12) xor a(11)) & (a(4) xor a(3) xor a(12)) & (a(3) xor a(2) xor a(11)) & (a(2) xor a(12) xor a(11)) );
end generate;
GF_2_13_P_12 : if final_value = 12 generate
o <= ( (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7) xor a(6)) & (a(9) xor a(8) xor a(6) xor a(5)) & (a(8) xor a(7) xor a(5) xor a(4)) & (a(7) xor a(6) xor a(4) xor a(3) xor a(12)) & (a(6) xor a(5) xor a(3) xor a(2) xor a(11)) & (a(5) xor a(4) xor a(2) xor a(12) xor a(1) xor a(10)) & (a(4) xor a(3) xor a(12) xor a(1) xor a(11) xor a(10)) & (a(3) xor a(2) xor a(11)) & (a(2) xor a(12) xor a(1) xor a(10)) & (a(1) xor a(11) xor a(10)) );
end generate;
end generate;
GF_2_14 : if m = 14 generate -- x^14 + x^5 + 1
GF_2_14_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_14_P_1 : if final_value = 1 generate
o <= ( a(12 downto 5) & (a(4) xor a(13)) & a(3) & a(2) & a(1) & a(0) & a(13) );
end generate;
GF_2_14_P_2 : if final_value = 2 generate
o <= ( a(11 downto 5) & (a(4) xor a(13)) & (a(3) xor a(12)) & a(2) & a(1) & a(0) & a(13) & a(12) );
end generate;
GF_2_14_P_3 : if final_value = 3 generate
o <= ( a(10 downto 5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(11)) & a(1) & a(0) & a(13) & a(12) & a(11) );
end generate;
GF_2_14_P_4 : if final_value = 4 generate
o <= ( a(9 downto 5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(11)) & (a(1) xor a(10)) & a(0) & a(13) & a(12) & a(11) & a(10) );
end generate;
GF_2_14_P_5 : if final_value = 5 generate
o <= ( a(8 downto 5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & a(13) & a(12) & a(11) & a(10) & a(9) );
end generate;
GF_2_14_P_6 : if final_value = 6 generate
o <= ( a(7 downto 5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(13) xor a(8)) & a(12) & a(11) & a(10) & a(9) & a(8) );
end generate;
GF_2_14_P_7 : if final_value = 7 generate
o <= ( a(6 downto 5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(13) xor a(8)) & (a(12) xor a(7)) & a(11) & a(10) & a(9) & a(8) & a(7) );
end generate;
GF_2_14_P_8 : if final_value = 8 generate
o <= ( a(5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(13) xor a(8)) & (a(12) xor a(7)) & (a(11) xor a(6)) & a(10) & a(9) & a(8) & a(7) & a(6) );
end generate;
GF_2_14_P_9 : if final_value = 9 generate
o <= ( (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(13) xor a(8)) & (a(12) xor a(7)) & (a(11) xor a(6)) & (a(10) xor a(5)) & a(9) & a(8) & a(7) & a(6) & a(5) );
end generate;
GF_2_14_P_10 : if final_value = 10 generate
o <= ( (a(3) xor a(12)) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(13) xor a(8)) & (a(12) xor a(7)) & (a(11) xor a(6)) & (a(10) xor a(5)) & (a(9) xor a(4) xor a(13)) & a(8) & a(7) & a(6) & a(5) & (a(4) xor a(13)) );
end generate;
GF_2_14_P_11 : if final_value = 11 generate
o <= ( (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(13) xor a(8)) & (a(12) xor a(7)) & (a(11) xor a(6)) & (a(10) xor a(5)) & (a(9) xor a(4) xor a(13)) & (a(8) xor a(3) xor a(12)) & a(7) & a(6) & a(5) & (a(4) xor a(13)) & (a(3) xor a(12)) );
end generate;
GF_2_14_P_12 : if final_value = 12 generate
o <= ( (a(1) xor a(10)) & (a(0) xor a(9)) & (a(13) xor a(8)) & (a(12) xor a(7)) & (a(11) xor a(6)) & (a(10) xor a(5)) & (a(9) xor a(4) xor a(13)) & (a(8) xor a(3) xor a(12)) & (a(7) xor a(2) xor a(11)) & a(6) & a(5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(11)) );
end generate;
GF_2_14_P_13 : if final_value = 13 generate
o <= ( (a(0) xor a(9)) & (a(13) xor a(8)) & (a(12) xor a(7)) & (a(11) xor a(6)) & (a(10) xor a(5)) & (a(9) xor a(4) xor a(13)) & (a(8) xor a(3) xor a(12)) & (a(7) xor a(2) xor a(11)) & (a(6) xor a(1) xor a(10)) & a(5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(11)) & (a(1) xor a(10)) );
end generate;
end generate;
GF_2_15 : if m = 15 generate -- x^15 + x^1 + 1
GF_2_15_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_15_P_1 : if final_value = 1 generate
o <= ( a(13 downto 1) & (a(0) xor a(14)) & a(14) );
end generate;
GF_2_15_P_2 : if final_value = 2 generate
o <= ( a(12 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & a(13) );
end generate;
GF_2_15_P_3 : if final_value = 3 generate
o <= ( a(11 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & a(12) );
end generate;
GF_2_15_P_4 : if final_value = 4 generate
o <= ( a(10 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & a(11) );
end generate;
GF_2_15_P_5 : if final_value = 5 generate
o <= ( a(9 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & a(10) );
end generate;
GF_2_15_P_6 : if final_value = 6 generate
o <= ( a(8 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & a(9) );
end generate;
GF_2_15_P_7 : if final_value = 7 generate
o <= ( a(7 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & a(8) );
end generate;
GF_2_15_P_8 : if final_value = 8 generate
o <= ( a(6 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & a(7) );
end generate;
GF_2_15_P_9 : if final_value = 9 generate
o <= ( a(5 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & a(6) );
end generate;
GF_2_15_P_10 : if final_value = 10 generate
o <= ( a(4 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & a(5) );
end generate;
GF_2_15_P_11 : if final_value = 11 generate
o <= ( a(3 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & a(4) );
end generate;
GF_2_15_P_12 : if final_value = 12 generate
o <= ( a(2 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & a(3) );
end generate;
GF_2_15_P_13 : if final_value = 13 generate
o <= ( a(1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & a(2) );
end generate;
GF_2_15_P_14 : if final_value = 14 generate
o <= ( (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & (a(2) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_16 : if m = 16 generate -- x^16 + x^5 + x^3 + x^1 + 1
GF_2_16_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_16_P_1 : if final_value = 1 generate
o <= ( a(14 downto 5) & (a(4) xor a(15)) & a(3) & (a(2) xor a(15)) & a(1) & (a(0) xor a(15)) & a(15) );
end generate;
GF_2_16_P_2 : if final_value = 2 generate
o <= ( a(13 downto 5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15)) & (a(1) xor a(14)) & (a(0) xor a(15)) & (a(15) xor a(14)) & a(14) );
end generate;
GF_2_16_P_3 : if final_value = 3 generate
o <= ( a(12 downto 5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14)) & (a(0) xor a(15) xor a(13)) & (a(15) xor a(14)) & (a(14) xor a(13)) & a(13) );
end generate;
GF_2_16_P_4 : if final_value = 4 generate
o <= ( a(11 downto 5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13)) & (a(15) xor a(14) xor a(12)) & (a(14) xor a(13)) & (a(13) xor a(12)) & a(12) );
end generate;
GF_2_16_P_5 : if final_value = 5 generate
o <= ( a(10 downto 5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12)) & (a(14) xor a(13) xor a(11)) & (a(13) xor a(12)) & (a(12) xor a(11)) & a(11) );
end generate;
GF_2_16_P_6 : if final_value = 6 generate
o <= ( a(9 downto 5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11)) & (a(13) xor a(12) xor a(10)) & (a(12) xor a(11)) & (a(11) xor a(10)) & a(10) );
end generate;
GF_2_16_P_7 : if final_value = 7 generate
o <= ( a(8 downto 5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10)) & (a(12) xor a(11) xor a(9)) & (a(11) xor a(10)) & (a(10) xor a(9)) & a(9) );
end generate;
GF_2_16_P_8 : if final_value = 8 generate
o <= ( a(7 downto 5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9)) & (a(11) xor a(10) xor a(8)) & (a(10) xor a(9)) & (a(9) xor a(8)) & a(8) );
end generate;
GF_2_16_P_9 : if final_value = 9 generate
o <= ( a(6 downto 5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8)) & (a(10) xor a(9) xor a(7)) & (a(9) xor a(8)) & (a(8) xor a(7)) & a(7) );
end generate;
GF_2_16_P_10 : if final_value = 10 generate
o <= ( a(5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8) xor a(6)) & (a(10) xor a(9) xor a(7)) & (a(9) xor a(8) xor a(6)) & (a(8) xor a(7)) & (a(7) xor a(6)) & a(6) );
end generate;
GF_2_16_P_11 : if final_value = 11 generate
o <= ( (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8) xor a(6)) & (a(10) xor a(9) xor a(7) xor a(5)) & (a(9) xor a(8) xor a(6)) & (a(8) xor a(7) xor a(5)) & (a(7) xor a(6)) & (a(6) xor a(5)) & a(5) );
end generate;
GF_2_16_P_12 : if final_value = 12 generate
o <= ( (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8) xor a(6)) & (a(10) xor a(9) xor a(7) xor a(5)) & (a(9) xor a(8) xor a(6) xor a(4) xor a(15)) & (a(8) xor a(7) xor a(5)) & (a(7) xor a(6) xor a(4) xor a(15)) & (a(6) xor a(5)) & (a(5) xor a(4) xor a(15)) & (a(4) xor a(15)) );
end generate;
GF_2_16_P_13 : if final_value = 13 generate
o <= ( (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8) xor a(6)) & (a(10) xor a(9) xor a(7) xor a(5)) & (a(9) xor a(8) xor a(6) xor a(4) xor a(15)) & (a(8) xor a(7) xor a(5) xor a(3) xor a(14)) & (a(7) xor a(6) xor a(4) xor a(15)) & (a(6) xor a(5) xor a(3) xor a(14)) & (a(5) xor a(4) xor a(15)) & (a(4) xor a(15) xor a(3) xor a(14)) & (a(3) xor a(14)) );
end generate;
GF_2_16_P_14 : if final_value = 14 generate
o <= ( (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8) xor a(6)) & (a(10) xor a(9) xor a(7) xor a(5)) & (a(9) xor a(8) xor a(6) xor a(4) xor a(15)) & (a(8) xor a(7) xor a(5) xor a(3) xor a(14)) & (a(7) xor a(6) xor a(4) xor a(2) xor a(13)) & (a(6) xor a(5) xor a(3) xor a(14)) & (a(5) xor a(4) xor a(2) xor a(13)) & (a(4) xor a(15) xor a(3) xor a(14)) & (a(3) xor a(14) xor a(2) xor a(15) xor a(13)) & (a(2) xor a(15) xor a(13)) );
end generate;
GF_2_16_P_15 : if final_value = 15 generate
o <= ( (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8) xor a(6)) & (a(10) xor a(9) xor a(7) xor a(5)) & (a(9) xor a(8) xor a(6) xor a(4) xor a(15)) & (a(8) xor a(7) xor a(5) xor a(3) xor a(14)) & (a(7) xor a(6) xor a(4) xor a(2) xor a(13)) & (a(6) xor a(5) xor a(3) xor a(1) xor a(12)) & (a(5) xor a(4) xor a(2) xor a(13)) & (a(4) xor a(15) xor a(3) xor a(1) xor a(12)) & (a(3) xor a(14) xor a(2) xor a(15) xor a(13)) & (a(2) xor a(15) xor a(13) xor a(1) xor a(14) xor a(12)) & (a(1) xor a(14) xor a(12)) );
end generate;
end generate;
GF_2_17 : if m = 17 generate -- x^17 + x^3 + 1
GF_2_17_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_17_P_1 : if final_value = 1 generate
o <= ( a(15 downto 3) & (a(2) xor a(16)) & a(1) & a(0) & a(16) );
end generate;
GF_2_17_P_2 : if final_value = 2 generate
o <= ( a(14 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & a(0) & a(16) & a(15) );
end generate;
GF_2_17_P_3 : if final_value = 3 generate
o <= ( a(13 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & a(16) & a(15) & a(14) );
end generate;
GF_2_17_P_4 : if final_value = 4 generate
o <= ( a(12 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & a(15) & a(14) & a(13) );
end generate;
GF_2_17_P_5 : if final_value = 5 generate
o <= ( a(11 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & a(14) & a(13) & a(12) );
end generate;
GF_2_17_P_6 : if final_value = 6 generate
o <= ( a(10 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & a(13) & a(12) & a(11) );
end generate;
GF_2_17_P_7 : if final_value = 7 generate
o <= ( a(9 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & a(12) & a(11) & a(10) );
end generate;
GF_2_17_P_8 : if final_value = 8 generate
o <= ( a(8 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & a(11) & a(10) & a(9) );
end generate;
GF_2_17_P_9 : if final_value = 9 generate
o <= ( a(7 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & a(10) & a(9) & a(8) );
end generate;
GF_2_17_P_10 : if final_value = 10 generate
o <= ( a(6 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & a(9) & a(8) & a(7) );
end generate;
GF_2_17_P_11 : if final_value = 11 generate
o <= ( a(5 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & a(8) & a(7) & a(6) );
end generate;
GF_2_17_P_12 : if final_value = 12 generate
o <= ( a(4 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & a(7) & a(6) & a(5) );
end generate;
GF_2_17_P_13 : if final_value = 13 generate
o <= ( a(3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & a(6) & a(5) & a(4) );
end generate;
GF_2_17_P_14 : if final_value = 14 generate
o <= ( (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & a(5) & a(4) & a(3) );
end generate;
GF_2_17_P_15 : if final_value = 15 generate
o <= ( (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(16)) & a(4) & a(3) & (a(2) xor a(16)) );
end generate;
GF_2_17_P_16 : if final_value = 16 generate
o <= ( (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(16)) & (a(4) xor a(1) xor a(15)) & a(3) & (a(2) xor a(16)) & (a(1) xor a(15)) );
end generate;
end generate;
GF_2_18 : if m = 18 generate -- x^18 + x^3 + 1
GF_2_18_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_18_P_1 : if final_value = 1 generate
o <= ( a(16 downto 3) & (a(2) xor a(17)) & a(1) & a(0) & a(17) );
end generate;
GF_2_18_P_2 : if final_value = 2 generate
o <= ( a(15 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & a(0) & a(17) & a(16) );
end generate;
GF_2_18_P_3 : if final_value = 3 generate
o <= ( a(14 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & a(17) & a(16) & a(15) );
end generate;
GF_2_18_P_4 : if final_value = 4 generate
o <= ( a(13 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & a(16) & a(15) & a(14) );
end generate;
GF_2_18_P_5 : if final_value = 5 generate
o <= ( a(12 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & a(15) & a(14) & a(13) );
end generate;
GF_2_18_P_6 : if final_value = 6 generate
o <= ( a(11 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & a(14) & a(13) & a(12) );
end generate;
GF_2_18_P_7 : if final_value = 7 generate
o <= ( a(10 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & a(13) & a(12) & a(11) );
end generate;
GF_2_18_P_8 : if final_value = 8 generate
o <= ( a(9 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & a(12) & a(11) & a(10) );
end generate;
GF_2_18_P_9 : if final_value = 9 generate
o <= ( a(8 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & a(11) & a(10) & a(9) );
end generate;
GF_2_18_P_10 : if final_value = 10 generate
o <= ( a(7 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & a(10) & a(9) & a(8) );
end generate;
GF_2_18_P_11 : if final_value = 11 generate
o <= ( a(6 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & a(9) & a(8) & a(7) );
end generate;
GF_2_18_P_12 : if final_value = 12 generate
o <= ( a(5 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & a(8) & a(7) & a(6) );
end generate;
GF_2_18_P_13 : if final_value = 13 generate
o <= ( a(4 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & a(7) & a(6) & a(5) );
end generate;
GF_2_18_P_14 : if final_value = 14 generate
o <= ( a(3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & a(6) & a(5) & a(4) );
end generate;
GF_2_18_P_15 : if final_value = 15 generate
o <= ( (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & a(5) & a(4) & a(3) );
end generate;
GF_2_18_P_16 : if final_value = 16 generate
o <= ( (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(17)) & a(4) & a(3) & (a(2) xor a(17)) );
end generate;
GF_2_18_P_17 : if final_value = 17 generate
o <= ( (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(17)) & (a(4) xor a(1) xor a(16)) & a(3) & (a(2) xor a(17)) & (a(1) xor a(16)) );
end generate;
end generate;
GF_2_19 : if m = 19 generate -- x^19 + x^5 + x^2 + x^1 + 1
GF_2_19_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_19_P_1 : if final_value = 1 generate
o <= ( a(17 downto 5) & (a(4) xor a(18)) & a(3) & a(2) & (a(1) xor a(18)) & (a(0) xor a(18)) & a(18) );
end generate;
GF_2_19_P_2 : if final_value = 2 generate
o <= ( a(16 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & a(2) & (a(1) xor a(18)) & (a(0) xor a(18) xor a(17)) & (a(18) xor a(17)) & a(17) );
end generate;
GF_2_19_P_3 : if final_value = 3 generate
o <= ( a(15 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18)) & (a(0) xor a(18) xor a(17)) & (a(18) xor a(17) xor a(16)) & (a(17) xor a(16)) & a(16) );
end generate;
GF_2_19_P_4 : if final_value = 4 generate
o <= ( a(14 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17)) & (a(18) xor a(17) xor a(16)) & (a(17) xor a(16) xor a(15)) & (a(16) xor a(15)) & a(15) );
end generate;
GF_2_19_P_5 : if final_value = 5 generate
o <= ( a(13 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16)) & (a(17) xor a(16) xor a(15)) & (a(16) xor a(15) xor a(14)) & (a(15) xor a(14)) & a(14) );
end generate;
GF_2_19_P_6 : if final_value = 6 generate
o <= ( a(12 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15)) & (a(16) xor a(15) xor a(14)) & (a(15) xor a(14) xor a(13)) & (a(14) xor a(13)) & a(13) );
end generate;
GF_2_19_P_7 : if final_value = 7 generate
o <= ( a(11 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14)) & (a(15) xor a(14) xor a(13)) & (a(14) xor a(13) xor a(12)) & (a(13) xor a(12)) & a(12) );
end generate;
GF_2_19_P_8 : if final_value = 8 generate
o <= ( a(10 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13)) & (a(14) xor a(13) xor a(12)) & (a(13) xor a(12) xor a(11)) & (a(12) xor a(11)) & a(11) );
end generate;
GF_2_19_P_9 : if final_value = 9 generate
o <= ( a(9 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12)) & (a(13) xor a(12) xor a(11)) & (a(12) xor a(11) xor a(10)) & (a(11) xor a(10)) & a(10) );
end generate;
GF_2_19_P_10 : if final_value = 10 generate
o <= ( a(8 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11)) & (a(12) xor a(11) xor a(10)) & (a(11) xor a(10) xor a(9)) & (a(10) xor a(9)) & a(9) );
end generate;
GF_2_19_P_11 : if final_value = 11 generate
o <= ( a(7 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10)) & (a(11) xor a(10) xor a(9)) & (a(10) xor a(9) xor a(8)) & (a(9) xor a(8)) & a(8) );
end generate;
GF_2_19_P_12 : if final_value = 12 generate
o <= ( a(6 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9)) & (a(10) xor a(9) xor a(8)) & (a(9) xor a(8) xor a(7)) & (a(8) xor a(7)) & a(7) );
end generate;
GF_2_19_P_13 : if final_value = 13 generate
o <= ( a(5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9) xor a(6)) & (a(10) xor a(9) xor a(8)) & (a(9) xor a(8) xor a(7)) & (a(8) xor a(7) xor a(6)) & (a(7) xor a(6)) & a(6) );
end generate;
GF_2_19_P_14 : if final_value = 14 generate
o <= ( (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9) xor a(6)) & (a(10) xor a(9) xor a(8) xor a(5)) & (a(9) xor a(8) xor a(7)) & (a(8) xor a(7) xor a(6)) & (a(7) xor a(6) xor a(5)) & (a(6) xor a(5)) & a(5) );
end generate;
GF_2_19_P_15 : if final_value = 15 generate
o <= ( (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9) xor a(6)) & (a(10) xor a(9) xor a(8) xor a(5)) & (a(9) xor a(8) xor a(7) xor a(4) xor a(18)) & (a(8) xor a(7) xor a(6)) & (a(7) xor a(6) xor a(5)) & (a(6) xor a(5) xor a(4) xor a(18)) & (a(5) xor a(4) xor a(18)) & (a(4) xor a(18)) );
end generate;
GF_2_19_P_16 : if final_value = 16 generate
o <= ( (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9) xor a(6)) & (a(10) xor a(9) xor a(8) xor a(5)) & (a(9) xor a(8) xor a(7) xor a(4) xor a(18)) & (a(8) xor a(7) xor a(6) xor a(3) xor a(17)) & (a(7) xor a(6) xor a(5)) & (a(6) xor a(5) xor a(4) xor a(18)) & (a(5) xor a(4) xor a(18) xor a(3) xor a(17)) & (a(4) xor a(18) xor a(3) xor a(17)) & (a(3) xor a(17)) );
end generate;
GF_2_19_P_17 : if final_value = 17 generate
o <= ( (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9) xor a(6)) & (a(10) xor a(9) xor a(8) xor a(5)) & (a(9) xor a(8) xor a(7) xor a(4) xor a(18)) & (a(8) xor a(7) xor a(6) xor a(3) xor a(17)) & (a(7) xor a(6) xor a(5) xor a(2) xor a(16)) & (a(6) xor a(5) xor a(4) xor a(18)) & (a(5) xor a(4) xor a(18) xor a(3) xor a(17)) & (a(4) xor a(18) xor a(3) xor a(17) xor a(2) xor a(16)) & (a(3) xor a(17) xor a(2) xor a(16)) & (a(2) xor a(16)) );
end generate;
GF_2_19_P_18 : if final_value = 18 generate
o <= ( (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9) xor a(6)) & (a(10) xor a(9) xor a(8) xor a(5)) & (a(9) xor a(8) xor a(7) xor a(4) xor a(18)) & (a(8) xor a(7) xor a(6) xor a(3) xor a(17)) & (a(7) xor a(6) xor a(5) xor a(2) xor a(16)) & (a(6) xor a(5) xor a(4) xor a(1) xor a(15)) & (a(5) xor a(4) xor a(18) xor a(3) xor a(17)) & (a(4) xor a(18) xor a(3) xor a(17) xor a(2) xor a(16)) & (a(3) xor a(17) xor a(2) xor a(16) xor a(1) xor a(18) xor a(15)) & (a(2) xor a(16) xor a(1) xor a(18) xor a(15)) & (a(1) xor a(18) xor a(15)) );
end generate;
end generate;
GF_2_20 : if m = 20 generate -- x^20 + x^3 + 1
GF_2_20_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_20_P_1 : if final_value = 1 generate
o <= ( a(18 downto 3) & (a(2) xor a(19)) & a(1) & a(0) & a(19) );
end generate;
GF_2_20_P_2 : if final_value = 2 generate
o <= ( a(17 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & a(0) & a(19) & a(18) );
end generate;
GF_2_20_P_3 : if final_value = 3 generate
o <= ( a(16 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & a(19) & a(18) & a(17) );
end generate;
GF_2_20_P_4 : if final_value = 4 generate
o <= ( a(15 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & a(18) & a(17) & a(16) );
end generate;
GF_2_20_P_5 : if final_value = 5 generate
o <= ( a(14 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & a(17) & a(16) & a(15) );
end generate;
GF_2_20_P_6 : if final_value = 6 generate
o <= ( a(13 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & a(16) & a(15) & a(14) );
end generate;
GF_2_20_P_7 : if final_value = 7 generate
o <= ( a(12 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & a(15) & a(14) & a(13) );
end generate;
GF_2_20_P_8 : if final_value = 8 generate
o <= ( a(11 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & a(14) & a(13) & a(12) );
end generate;
GF_2_20_P_9 : if final_value = 9 generate
o <= ( a(10 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & a(13) & a(12) & a(11) );
end generate;
GF_2_20_P_10 : if final_value = 10 generate
o <= ( a(9 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & a(12) & a(11) & a(10) );
end generate;
GF_2_20_P_11 : if final_value = 11 generate
o <= ( a(8 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & a(11) & a(10) & a(9) );
end generate;
GF_2_20_P_12 : if final_value = 12 generate
o <= ( a(7 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & a(10) & a(9) & a(8) );
end generate;
GF_2_20_P_13 : if final_value = 13 generate
o <= ( a(6 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & a(9) & a(8) & a(7) );
end generate;
GF_2_20_P_14 : if final_value = 14 generate
o <= ( a(5 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & a(8) & a(7) & a(6) );
end generate;
GF_2_20_P_15 : if final_value = 15 generate
o <= ( a(4 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & a(7) & a(6) & a(5) );
end generate;
GF_2_20_P_16 : if final_value = 16 generate
o <= ( a(3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & a(6) & a(5) & a(4) );
end generate;
GF_2_20_P_17 : if final_value = 17 generate
o <= ( (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & a(5) & a(4) & a(3) );
end generate;
GF_2_20_P_18 : if final_value = 18 generate
o <= ( (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(19)) & a(4) & a(3) & (a(2) xor a(19)) );
end generate;
GF_2_20_P_19 : if final_value = 19 generate
o <= ( (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(19)) & (a(4) xor a(1) xor a(18)) & a(3) & (a(2) xor a(19)) & (a(1) xor a(18)) );
end generate;
end generate;
end IEEE_POLYNOMIALS;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2270.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02270ent IS
END c07s02b06x00p14n01i02270ent;
ARCHITECTURE c07s02b06x00p14n01i02270arch OF c07s02b06x00p14n01i02270ent IS
BEGIN
TESTING: PROCESS
type phys is range -10 to 100
units
p1;
p2 = 10 p1;
p3 = 5 p2;
end units;
variable k : phys := 10 p2;
BEGIN
assert NOT(k = 2 p3)
report "***PASSED TEST: c07s02b06x00p14n01i02270"
severity NOTE;
assert (k = 2 p3)
report "***FAILED TEST: c07s02b06x00p14n01i02270 - The left operand of the multiplication operation can be an integer type and the right operand of physical type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02270arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2270.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02270ent IS
END c07s02b06x00p14n01i02270ent;
ARCHITECTURE c07s02b06x00p14n01i02270arch OF c07s02b06x00p14n01i02270ent IS
BEGIN
TESTING: PROCESS
type phys is range -10 to 100
units
p1;
p2 = 10 p1;
p3 = 5 p2;
end units;
variable k : phys := 10 p2;
BEGIN
assert NOT(k = 2 p3)
report "***PASSED TEST: c07s02b06x00p14n01i02270"
severity NOTE;
assert (k = 2 p3)
report "***FAILED TEST: c07s02b06x00p14n01i02270 - The left operand of the multiplication operation can be an integer type and the right operand of physical type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02270arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2270.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02270ent IS
END c07s02b06x00p14n01i02270ent;
ARCHITECTURE c07s02b06x00p14n01i02270arch OF c07s02b06x00p14n01i02270ent IS
BEGIN
TESTING: PROCESS
type phys is range -10 to 100
units
p1;
p2 = 10 p1;
p3 = 5 p2;
end units;
variable k : phys := 10 p2;
BEGIN
assert NOT(k = 2 p3)
report "***PASSED TEST: c07s02b06x00p14n01i02270"
severity NOTE;
assert (k = 2 p3)
report "***FAILED TEST: c07s02b06x00p14n01i02270 - The left operand of the multiplication operation can be an integer type and the right operand of physical type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02270arch;
|
architecture RTL of FIFO is
begin
process
begin
FOR_LABEL : for index in 4 to 23 loop
end loop;
for index in 4 to 23 loop
end loop;
for index in 4 to 23 loop
for j in 0 to 127 loop
end loop;
end loop;
-- Violations below
FOR_LABEL : for index in 4 to 23 loop
end loop;
for index in 4 to 23 loop
end loop;
for index in 4 to 23 loop
for j in 0 to 127 loop
end loop;
end loop;
end process;
end;
|
architecture RTL of FIFO is
begin
process
begin
FOR_LABEL : for index in 4 to 23 loop
end loop;
for index in 4 to 23 loop
end loop;
for index in 4 to 23 loop
for j in 0 to 127 loop
end loop;
end loop;
-- Violations below
FOR_LABEL : for index in 4 to 23 loop
end loop;
for index in 4 to 23 loop
end loop;
for index in 4 to 23 loop
for j in 0 to 127 loop
end loop;
end loop;
end process;
end;
|
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: RX lane
-- # Aurora style single rx lane
-- ####################################
-- # RX STATUS:
-- # [0] -> Sync
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim ;
use unisim.vcomponents.all ;
library work;
use work.board_pkg.all;
entity aurora_rx_lane is
port (
-- Sys connect
rst_n_i : in std_logic;
clk_rx_i : in std_logic;
clk_serdes_i : in std_logic;
-- Input
rx_data_i_p : in std_logic;
rx_data_i_n : in std_logic;
rx_polarity_i : in std_logic;
-- Output
rx_data_o : out std_logic_vector(63 downto 0);
rx_header_o : out std_logic_vector(1 downto 0);
rx_valid_o : out std_logic;
rx_stat_o : out std_logic_vector(7 downto 0)
);
end aurora_rx_lane;
architecture behavioral of aurora_rx_lane is
component serdes_1_to_468_idelay_ddr
generic (
S : integer := 8 ; -- Set the serdes factor to 4, 6 or 8
D : integer := 1 ; -- Set the number of inputs
CLKIN_PERIOD : real := 3.2 ; -- clock period (ns) of input clock on clkin_p
REF_FREQ : real := 300.0 ; -- Parameter to set reference frequency used by idelay controller
HIGH_PERFORMANCE_MODE : string := "TRUE" ; -- Parameter to set HIGH_PERFORMANCE_MODE of input delays to reduce jitter
DATA_FORMAT : string := "PER_CLOCK" -- Used to determine method for mapping input parallel word to output serial words
);
port (
datain_p : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
datain_n : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
enable_phase_detector : in std_logic ; -- Enables the phase detector logic when high
enable_monitor : in std_logic ; -- Enables the monitor logic when high, note time-shared with phase detector function
reset : in std_logic ; -- Reset line
bitslip : in std_logic ; -- bitslip
idelay_rdy : in std_logic ; -- input delays are ready
rxclk : in std_logic ; -- Global/BUFIO rx clock network
system_clk : in std_logic ; -- Global/Regional clock output
rx_lckd : out std_logic ; --
rx_data : out std_logic_vector((S*D)-1 downto 0) ; -- Output data
bit_rate_value : in std_logic_vector(15 downto 0) ; -- Bit rate in Mbps, eg X"0585
dcd_correct : in std_logic ; -- '0' = square, '1' = assume 10% DCD
bit_time_value : out std_logic_vector(4 downto 0) ; -- Calculated bit time value for slave devices
debug : out std_logic_vector(10*D+18 downto 0) ; -- Debug bus
eye_info : out std_logic_vector(32*D-1 downto 0) ; -- Eye info
m_delay_1hot : out std_logic_vector(32*D-1 downto 0) ; -- Master delay control value as a one-hot vector
clock_sweep : out std_logic_vector(31 downto 0) -- clock Eye info
);
end component serdes_1_to_468_idelay_ddr;
component cdr_serdes
port (
clk160 : in std_logic;
clk640 : in std_logic;
reset : in std_logic;
din : in std_logic;
slip : in std_logic;
data_value : out std_logic_vector(1 downto 0);
data_valid : out std_logic_vector(1 downto 0);
data_lock : out std_logic
);
end component cdr_serdes;
component gearbox32to66
port (
-- Sys connect
rst_i : in std_logic;
clk_i : in std_logic;
-- Input
data32_i : in std_logic_vector(31 downto 0);
data32_valid_i : in std_logic;
slip_i : in std_logic;
-- Outoput
data66_o : out std_logic_vector(65 downto 0);
data66_valid_o : out std_logic
);
end component gearbox32to66;
component descrambler
port (
data_in : in std_logic_vector(0 to 65);
data_out : out std_logic_vector(63 downto 0);
enable : in std_logic;
sync_info : out std_logic_vector(1 downto 0);
clk : in std_logic;
rst : in std_logic
);
end component descrambler;
signal c_SLIP_SERDES_MAX : unsigned(7 downto 0);
signal c_SERDES8_CYCLE : unsigned(3 downto 0);
-- constant g_SERDES_TYPE : string := "CUSTOM";
-- constant c_SLIP_SERDES_MAX : unsigned(7 downto 0) := to_unsigned(1, 8);
-- constant c_SERDES8_CYCLE : unsigned(3 downto 0) := to_unsigned(0, 4);
-- constant g_SERDES_TYPE : string := "XAPP1017";
-- constant c_SLIP_SERDES_MAX : unsigned(7 downto 0) := to_unsigned(8, 8);
-- constant c_SERDES8_CYCLE : unsigned(3 downto 0) := to_unsigned(1, 4);
constant c_DATA_HEADER : std_logic_vector(1 downto 0) := "01";
constant c_CMD_HEADER : std_logic_vector(1 downto 0) := "10";
constant c_SYNC_MAX : unsigned(7 downto 0) := to_unsigned(32, 8);
constant c_VALID_WAIT : unsigned(7 downto 0) := to_unsigned(16, 8);
signal rst : std_logic;
-- Serdes
signal serdes_slip : std_logic;
signal serdes_idelay_rdy : std_logic;
signal serdes_data8 : std_logic_vector(7 downto 0);
signal serdes_data8_s : std_logic_vector(7 downto 0);
signal serdes_data8_d : std_logic_vector(7 downto 0);
signal datain_p : std_logic;
signal datain_n : std_logic;
signal serdes_data2 : std_logic_vector(1 downto 0);
signal serdes_data2_s : std_logic_vector(1 downto 0);
signal serdes_data2_d : std_logic_vector(1 downto 0);
signal serdes_data2_valid : std_logic_vector(1 downto 0);
signal serdes_data2_valid_s : std_logic_vector(1 downto 0);
signal serdes_data2_sel : std_logic;
signal serdes_lock : std_logic;
-- 8 to 32
signal serdes_data32_shift : std_logic_vector(32 downto 0);
signal serdes_data32 : std_logic_vector(31 downto 0);
signal serdes_data32_valid : std_logic;
signal serdes8_cnt : unsigned(3 downto 0);
signal serdes_cnt : unsigned(5 downto 0);
-- Gearbox
signal gearbox_data66 : std_logic_vector(65 downto 0);
signal gearbox_data66_valid : std_logic;
signal gearbox_data66_valid_d : std_logic;
signal gearbox_slip : std_logic;
-- Scrambler
signal scrambled_data66 : std_logic_vector(65 downto 0);
signal scrambled_data_valid : std_logic;
signal scrambled_data_valid_d : std_logic;
signal descrambled_data : std_logic_vector(63 downto 0);
signal descrambled_header : std_logic_vector(1 downto 0);
signal descrambled_data_valid : std_logic;
-- Block Sync
signal sync_cnt : unsigned(7 downto 0);
signal slip_cnt : unsigned(3 downto 0);
signal valid_cnt : unsigned(7 downto 0);
-- SERDES debug
signal bit_time_value : std_logic_vector(4 downto 0);
signal eye_info : std_logic_vector(31 downto 0);
signal m_delay_1hot : std_logic_vector(31 downto 0);
-- DEBUG
-- DEBUG
COMPONENT ila_rx_dma_wb
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT ;
begin
rst <= not rst_n_i;
-- aurora_lane_debug : ila_rx_dma_wb
-- PORT MAP (
-- clk => clk_rx_i,
-- probe0 => serdes_data32,
-- probe1 => m_delay_1hot & eye_info,
-- probe2 => descrambled_data(63 downto 0),
-- probe3(0) => serdes_data32_valid,
-- probe4(0) => gearbox_data66_valid,
-- probe5(0) => gearbox_slip,
-- probe6(0) => serdes_slip,
-- probe7(0) => descrambled_data_valid,
-- probe8 => x"00" & std_logic_vector(sync_cnt) & "00" & serdes_data2_valid & serdes_lock & std_logic_vector(slip_cnt) & bit_time_value & descrambled_header,
-- probe9(0) => '0',
-- probe10(0) => '0',
-- probe11(0) => '0'
-- );
-- XAPP1017 style SERDES with auto-phase detection up to 1.6Gbps
xapp1017_serdes_1280: if c_RX_SPEED = "1280" generate
c_SLIP_SERDES_MAX <= to_unsigned(8, 8);
c_SERDES8_CYCLE <= to_unsigned(0, 4);
serdes_idelay_rdy <= rst_n_i;
serdes_cmp: serdes_1_to_468_idelay_ddr generic map (
S => 8,
D => 1,
CLKIN_PERIOD => 1.5625,
REF_FREQ => 310.0,
HIGH_PERFORMANCE_MODE => "TRUE",
DATA_FORMAT => "PER_CLOCK")
port map (
datain_p(0) => rx_data_i_p,
datain_n(0) => rx_data_i_n,
enable_phase_detector => '1',
enable_monitor => '1',
reset => rst,
--bitslip => '0',
bitslip => serdes_slip,
idelay_rdy => serdes_idelay_rdy,
rxclk => clk_serdes_i,
system_clk => clk_rx_i,
rx_lckd => serdes_lock,
--rx_data => serdes_data8,
rx_data(0) => serdes_data8(7),
rx_data(1) => serdes_data8(6),
rx_data(2) => serdes_data8(5),
rx_data(3) => serdes_data8(4),
rx_data(4) => serdes_data8(3),
rx_data(5) => serdes_data8(2),
rx_data(6) => serdes_data8(1),
rx_data(7) => serdes_data8(0),
bit_rate_value => x"1280", -- TODO make generic
dcd_correct => '0',
bit_time_value => bit_time_value,
debug => open,
eye_info => eye_info,
m_delay_1hot => m_delay_1hot,
clock_sweep => open
);
pol_loop: for I in 0 to 7 generate
serdes_data8_s(I) <= serdes_data8(I) xor rx_polarity_i;
end generate pol_loop;
serdes_8to32_proc : process(clk_rx_i, rst_n_i)
begin
if (rst_n_i = '0') then
serdes_data32 <= (others => '0');
serdes_data32_shift <= (others => '0');
serdes_data32_valid <= '0';
serdes_cnt <= (others => '0');
serdes8_cnt <= (others => '0');
serdes_data8_d <= (others => '0');
elsif rising_edge(clk_rx_i) then
serdes8_cnt <= serdes8_cnt + 1;
serdes_data32_valid <= '0';
if (serdes8_cnt = c_SERDES8_CYCLE) then
serdes_cnt <= serdes_cnt + 1;
--serdes_data8_d <= serdes_data8_s;
serdes_data32_shift(31 downto 8) <= serdes_data32_shift(23 downto 0);
serdes_data32_shift(7 downto 0) <= serdes_data8_s;
if (serdes_cnt = to_unsigned(3, 6)) then
serdes_data32 <= serdes_data32_shift(31 downto 0);
serdes_data32_valid <= '1';
serdes_cnt <= (others => '0');
end if;
serdes8_cnt <= (others => '0');
end if;
end if;
end process serdes_8to32_proc;
end generate xapp1017_serdes_1280;
xapp1017_serdes_640: if c_RX_SPEED = "0640" generate
c_SLIP_SERDES_MAX <= to_unsigned(8, 8);
c_SERDES8_CYCLE <= to_unsigned(1, 4);
serdes_idelay_rdy <= rst_n_i;
serdes_cmp: serdes_1_to_468_idelay_ddr generic map (
S => 8,
D => 1,
CLKIN_PERIOD => 3.125,
REF_FREQ => 310.0,
HIGH_PERFORMANCE_MODE => "TRUE",
DATA_FORMAT => "PER_CLOCK")
port map (
datain_p(0) => rx_data_i_p,
datain_n(0) => rx_data_i_n,
enable_phase_detector => '1',
enable_monitor => '1',
reset => rst,
--bitslip => '0',
bitslip => serdes_slip,
idelay_rdy => serdes_idelay_rdy,
rxclk => clk_serdes_i,
system_clk => clk_rx_i,
rx_lckd => serdes_lock,
--rx_data => serdes_data8,
rx_data(0) => serdes_data8(7),
rx_data(1) => serdes_data8(6),
rx_data(2) => serdes_data8(5),
rx_data(3) => serdes_data8(4),
rx_data(4) => serdes_data8(3),
rx_data(5) => serdes_data8(2),
rx_data(6) => serdes_data8(1),
rx_data(7) => serdes_data8(0),
bit_rate_value => x"0640", -- TODO make generic
dcd_correct => '0',
bit_time_value => bit_time_value,
debug => open,
eye_info => eye_info,
m_delay_1hot => m_delay_1hot,
clock_sweep => open
);
pol_loop: for I in 0 to 7 generate
serdes_data8_s(I) <= serdes_data8(I) xor rx_polarity_i;
end generate pol_loop;
serdes_8to32_proc : process(clk_rx_i, rst_n_i)
begin
if (rst_n_i = '0') then
serdes_data32 <= (others => '0');
serdes_data32_shift <= (others => '0');
serdes_data32_valid <= '0';
serdes_cnt <= (others => '0');
serdes8_cnt <= (others => '0');
serdes_data8_d <= (others => '0');
elsif rising_edge(clk_rx_i) then
serdes8_cnt <= serdes8_cnt + 1;
serdes_data32_valid <= '0';
if (serdes8_cnt = c_SERDES8_CYCLE) then
serdes_cnt <= serdes_cnt + 1;
--serdes_data8_d <= serdes_data8_s;
serdes_data32_shift(31 downto 8) <= serdes_data32_shift(23 downto 0);
serdes_data32_shift(7 downto 0) <= serdes_data8_s;
if (serdes_cnt = to_unsigned(3, 6)) then
serdes_data32 <= serdes_data32_shift(31 downto 0);
serdes_data32_valid <= '1';
serdes_cnt <= (others => '0');
end if;
serdes8_cnt <= (others => '0');
end if;
end if;
end process serdes_8to32_proc;
end generate xapp1017_serdes_640;
-- Quad-Oversampling style SERDES with auto-phase detection up to 160Mpbs
custom_serdes: if c_RX_SPEED = "0160" generate
c_SLIP_SERDES_MAX <= to_unsigned(1, 8);
c_SERDES8_CYCLE <= to_unsigned(0, 4);
-- data_in : IBUFDS_DIFF_OUT generic map(
-- IBUF_LOW_PWR => FALSE)
-- port map (
-- I => rx_data_i_p,
-- IB => rx_data_i_n,
-- O => datain_p,
-- OB => datain_n
-- );
datain_p <= rx_data_i_p;
datain_n <= rx_data_i_n;
cmp_cdr_serdes: cdr_serdes port map (
clk160 => clk_rx_i,
clk640 => clk_serdes_i,
reset => rst,
din => datain_p,
slip => '0',
data_value => serdes_data2_s,
data_valid => serdes_data2_valid_s,
data_lock => serdes_lock
);
pol_loop: for I in 0 to 1 generate
serdes_data2(I) <= serdes_data2_s(I) xor rx_polarity_i;
end generate pol_loop;
serdes_data2_valid <= serdes_data2_valid_s;
serdes_2to32_proc : process(clk_rx_i, rst_n_i)
begin
if (rst_n_i = '0') then
serdes_data32 <= (others => '0');
serdes_data32_shift <= (others => '0');
serdes_data32_valid <= '0';
serdes_cnt <= (others => '0');
elsif rising_edge(clk_rx_i) then
serdes_data32_valid <= '0';
if (serdes_data2_valid = "01") then
serdes_data32_shift <= serdes_data32_shift(31 downto 0) & serdes_data2(0);
serdes_cnt <= serdes_cnt + 1;
-- elsif (serdes_data2_valid = "10") then
-- serdes_data32_shift <= serdes_data32_shift(31 downto 0) & serdes_data2(1);
-- serdes_cnt <= serdes_cnt + 1;
elsif (serdes_data2_valid = "11") then
serdes_data32_shift <= serdes_data32_shift(30 downto 0) & serdes_data2(0) & serdes_data2(1);
serdes_cnt <= serdes_cnt + 2;
end if;
if (serdes_cnt = to_unsigned(31, 6)) then
serdes_data32 <= serdes_data32_shift(31 downto 0);
serdes_data32_valid <= '1';
serdes_cnt <= (others => '0');
if (serdes_data2_valid = "11") then
serdes_cnt <= to_unsigned(1, 6);
else
serdes_cnt <= to_unsigned(0, 6);
end if;
elsif (serdes_cnt = to_unsigned(32, 6)) then
serdes_data32 <= serdes_data32_shift(32 downto 1);
serdes_data32_valid <= '1';
if (serdes_data2_valid = "11") then
serdes_cnt <= to_unsigned(2, 6);
else
serdes_cnt <= to_unsigned(1, 6);
end if;
end if;
if (serdes_slip = '1') then
serdes_cnt <= serdes_cnt;
end if;
end if;
end process serdes_2to32_proc;
end generate custom_serdes;
gearbox32to66_cmp : gearbox32to66 port map (
rst_i => rst,
clk_i => clk_rx_i,
data32_i => serdes_data32,
data32_valid_i => serdes_data32_valid,
slip_i => gearbox_slip,
data66_o => gearbox_data66,
data66_valid_o => gearbox_data66_valid
);
block_sync_proc: process(clk_rx_i, rst_n_i)
begin
if (rst_n_i = '0') then
sync_cnt <= (others => '0');
slip_cnt <= (others => '0');
serdes_slip <= '0';
valid_cnt <= (others => '0');
scrambled_data66 <= (others => '0');
scrambled_data_valid <= '0';
gearbox_slip <= '0';
elsif rising_edge(clk_rx_i) then
serdes_slip <= '0';
scrambled_data_valid <= '0';
if (gearbox_data66_valid = '1') then
gearbox_slip <= '0'; -- Keep high until next valid so gearbox sees it
if (valid_cnt < c_VALID_WAIT) then
valid_cnt <= valid_cnt + 1;
end if;
if ((gearbox_data66(65 downto 64) = c_DATA_HEADER) or
(gearbox_data66(65 downto 64) = c_CMD_HEADER)) then
if (sync_cnt < c_SYNC_MAX) then
sync_cnt <= sync_cnt + 1;
end if;
elsif (valid_cnt = c_VALID_WAIT) then
sync_cnt <= (others => '0');
if (slip_cnt = c_SLIP_SERDES_MAX) then
gearbox_slip <= '1';
serdes_slip <= '0';
slip_cnt <= (others => '0');
else
serdes_slip <= '1';
slip_cnt <= slip_cnt + 1;
end if;
valid_cnt <= (others => '0');
end if;
-- Output proc
if (sync_cnt = c_SYNC_MAX) then
scrambled_data66 <= gearbox_data66(65 downto 0);
scrambled_data_valid <= '1';
end if;
end if;
end if;
end process block_sync_proc;
descrambler_cmp : descrambler port map (
data_in => scrambled_data66,
data_out => descrambled_data,
enable => scrambled_data_valid,
sync_info => descrambled_header,
clk => clk_rx_i,
rst => rst
);
descrambler_proc: process(clk_rx_i, rst_n_i)
begin
if (rst_n_i = '0') then
descrambled_data_valid <= '0';
scrambled_data_valid_d <= '0';
gearbox_data66_valid_d <= '0';
rx_data_o <= (others => '0');
rx_header_o <= "00";
rx_valid_o <= '0';
elsif rising_edge(clk_rx_i) then
gearbox_data66_valid_d <= gearbox_data66_valid;
if (gearbox_data66_valid_d = '1') then
scrambled_data_valid_d <= scrambled_data_valid;
end if;
descrambled_data_valid <= scrambled_data_valid and scrambled_data_valid_d; -- Only valid after two valid descrambles
-- Output
if (descrambled_data_valid = '1') then
rx_data_o <= descrambled_data;
rx_header_o <= descrambled_header;
end if;
rx_valid_o <= descrambled_data_valid;
end if;
end process descrambler_proc;
stat_out_proc: process(clk_rx_i, rst_n_i)
begin
if (rst_n_i = '0') then
rx_stat_o <= (others => '0');
elsif rising_edge(clk_rx_i) then
rx_stat_o <= (others => '0');
rx_stat_o(0) <= serdes_lock; -- SERDES Sync Out
if (sync_cnt = c_SYNC_MAX) then
rx_stat_o(1) <= '1'; -- Gearbox Sync Out
end if;
end if;
end process stat_out_proc;
end behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity reg_bank is
port ( clock: in std_logic;
read_reg1: in std_logic_vector(3 downto 0);
read_reg2: in std_logic_vector(3 downto 0);
write_reg: in std_logic_vector(3 downto 0);
wreg: in std_logic;
write_data: in std_logic_vector(31 downto 0);
read_data1: out std_logic_vector(31 downto 0);
read_data2: out std_logic_vector(31 downto 0)
);
end reg_bank;
architecture arch_reg_bank of reg_bank is
type bank is array(0 to 15) of std_logic_vector(31 downto 0);
signal registers: bank := (others => (others => '0'));
begin
process(clock, write_reg, wreg, write_data, read_reg1, read_reg2, registers)
begin
if clock'event and clock = '1' then
if write_reg /= "00000" and wreg = '1' then
registers(conv_integer(write_reg)) <= write_data;
end if;
end if;
end process;
read_data1 <= registers(conv_integer(read_reg1)) when read_reg1 /= "00000" else (others => '0');
read_data2 <= registers(conv_integer(read_reg2)) when read_reg2 /= "00000" else (others => '0');
end arch_reg_bank;
|
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL; -- Import to_integer, to_signed
entity carry_ripple_adder_testbench is
end carry_ripple_adder_testbench;
architecture behavior of carry_ripple_adder_testbench is
component carry_ripple_adder is
generic (
WIDTH : integer := 8);
port (
a : in std_logic_vector (7 downto 0);
b : in std_logic_vector (7 downto 0);
ci : in std_logic;
s : out std_logic_vector (7 downto 0);
co : out std_logic);
end component;
signal a : std_logic_vector(7 downto 0);
signal b : std_logic_vector(7 downto 0);
signal s : std_logic_vector(7 downto 0);
signal ci : std_logic;
signal co : std_logic;
begin
uut: carry_ripple_adder port map (
a => a,
b => b,
ci => ci,
s => s,
co => co
);
stim_proc: process
begin
for i in -63 to 63 loop
for j in -63 to 63 loop
ci <= '0';
a <= std_logic_vector(to_signed(i, 8));
b <= std_logic_vector(to_signed(j, 8));
wait for 10 ns;
assert i + j = to_integer(signed(s))
report integer'image(i) & " + " & integer'image(j) & " was " & integer'image(to_integer(signed(s)));
-- TODO: Check carry out
-- assert i < 0 and j < 0 and to_integer(signed(s)) > 0 and (co = '0');
-- report integer'image(i) & " + " & integer'image(j) & " had carry out";
end loop;
end loop;
for i in -63 to 63 loop
for j in -63 to 63 loop
ci <= '1';
a <= std_logic_vector(to_signed(i, 8));
b <= std_logic_vector(to_signed(j, 8));
wait for 10 ns;
assert i + j + 1 = to_integer(signed(s))
report integer'image(i) & " + " & integer'image(j) & " was " & integer'image(to_integer(signed(s)));
-- TODO: Check carry out
end loop;
end loop;
report "Carry ripple added tested summation of all 8-bit signed numbers";
wait;
end process;
end;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
architecture test of inline_06 is
type integer_file is file of integer;
begin
process is
-- code from book:
file lookup_table_file, result_file : integer_file;
-- end of code from book
begin
wait;
end process;
process is
type element_type is (t1, t2, t3);
-- code from book:
type file_type is file of element_type;
procedure file_open ( file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode );
-- end of code from book
procedure file_open ( file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode ) is
begin
end;
begin
wait;
end process;
process is
-- code from book:
file lookup_table_file : integer_file open read_mode is "lookup-values";
-- end of code from book
begin
wait;
end process;
process is
-- code from book:
file lookup_table_file : integer_file;
-- . . .
-- end of code from book
begin
-- code from book:
file_open ( lookup_table_file,
external_name => "lookup-values", open_kind => read_mode );
-- end of code from book
wait;
end process;
process is
type element_type is (t1, t2, t3);
type file_type is file of element_type;
-- code from book:
type file_open_status is (open_ok, status_error, name_error, mode_error);
procedure file_open ( status : out file_open_status;
file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode );
procedure file_close ( file f : file_type );
-- end of code from book
procedure file_open ( status : out file_open_status;
file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode ) is
begin
end;
procedure file_close ( file f : file_type ) is
begin
end;
begin
wait;
end process;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
architecture test of inline_06 is
type integer_file is file of integer;
begin
process is
-- code from book:
file lookup_table_file, result_file : integer_file;
-- end of code from book
begin
wait;
end process;
process is
type element_type is (t1, t2, t3);
-- code from book:
type file_type is file of element_type;
procedure file_open ( file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode );
-- end of code from book
procedure file_open ( file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode ) is
begin
end;
begin
wait;
end process;
process is
-- code from book:
file lookup_table_file : integer_file open read_mode is "lookup-values";
-- end of code from book
begin
wait;
end process;
process is
-- code from book:
file lookup_table_file : integer_file;
-- . . .
-- end of code from book
begin
-- code from book:
file_open ( lookup_table_file,
external_name => "lookup-values", open_kind => read_mode );
-- end of code from book
wait;
end process;
process is
type element_type is (t1, t2, t3);
type file_type is file of element_type;
-- code from book:
type file_open_status is (open_ok, status_error, name_error, mode_error);
procedure file_open ( status : out file_open_status;
file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode );
procedure file_close ( file f : file_type );
-- end of code from book
procedure file_open ( status : out file_open_status;
file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode ) is
begin
end;
procedure file_close ( file f : file_type ) is
begin
end;
begin
wait;
end process;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
architecture test of inline_06 is
type integer_file is file of integer;
begin
process is
-- code from book:
file lookup_table_file, result_file : integer_file;
-- end of code from book
begin
wait;
end process;
process is
type element_type is (t1, t2, t3);
-- code from book:
type file_type is file of element_type;
procedure file_open ( file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode );
-- end of code from book
procedure file_open ( file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode ) is
begin
end;
begin
wait;
end process;
process is
-- code from book:
file lookup_table_file : integer_file open read_mode is "lookup-values";
-- end of code from book
begin
wait;
end process;
process is
-- code from book:
file lookup_table_file : integer_file;
-- . . .
-- end of code from book
begin
-- code from book:
file_open ( lookup_table_file,
external_name => "lookup-values", open_kind => read_mode );
-- end of code from book
wait;
end process;
process is
type element_type is (t1, t2, t3);
type file_type is file of element_type;
-- code from book:
type file_open_status is (open_ok, status_error, name_error, mode_error);
procedure file_open ( status : out file_open_status;
file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode );
procedure file_close ( file f : file_type );
-- end of code from book
procedure file_open ( status : out file_open_status;
file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode ) is
begin
end;
procedure file_close ( file f : file_type ) is
begin
end;
begin
wait;
end process;
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_176 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_176;
architecture augh of add_176 is
signal carry_inA : std_logic_vector(21 downto 0);
signal carry_inB : std_logic_vector(21 downto 0);
signal carry_res : std_logic_vector(21 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(20 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_176 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_176;
architecture augh of add_176 is
signal carry_inA : std_logic_vector(21 downto 0);
signal carry_inB : std_logic_vector(21 downto 0);
signal carry_res : std_logic_vector(21 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(20 downto 1);
end architecture;
|
-- --------------------------------------------------------------
-- Title : Testbench for design "BCD driver"
-- Project :
-- --------------------------------------------------------------
-- File : tb_bcd_driver.vhd
-- Author : Martin Angermair
-- Company : FH Technikum Wien
-- Last update : 2017-10-28
-- Standard : VHDL'87
-- --------------------------------------------------------------
-- Description :
-- --------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 28.10.2017 1.0 Martin Angerair init
-- --------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity tb_bcd_driver is
end tb_bcd_driver;
-------------------------------------------------------------------------------
architecture sim of tb_bcd_driver is
component seven_segment_driver
generic (g_refresh_rate : positive);
port ( clk_i : in std_logic; -- 100Mhz clock on Basys 3 FPGA board
reset_i : in std_logic; -- reset_i
dig0_i : in std_logic_vector(7 downto 0); -- first digit value
dig1_i : in std_logic_vector(7 downto 0); -- second digit value
dig2_i : in std_logic_vector(7 downto 0); -- third digit value
dig3_i : in std_logic_vector(7 downto 0); -- fourth digit value
ss_sel_o : out std_logic_vector(3 downto 0); -- 4 anode signals
ss_o : out std_logic_vector(7 downto 0));
end component;
-- component ports
signal clk_i : std_logic := '0';
signal reset_i : std_logic := '0';
signal dig0_i : std_logic_vector(7 downto 0) := "00001111";
signal dig1_i : std_logic_vector(7 downto 0) := "00110011";
signal dig2_i : std_logic_vector(7 downto 0) := "11001100";
signal dig3_i : std_logic_vector(7 downto 0) := "11110000";
signal ss_sel_o : std_logic_vector(3 downto 0);
signal ss_o : std_logic_vector(7 downto 0);
begin -- sim
-- component instantiation
DUT: seven_segment_driver generic map (
g_refresh_rate => 3)
port map (
clk_i => clk_i,
reset_i => reset_i,
dig0_i => dig0_i,
dig1_i => dig1_i,
dig2_i => dig2_i,
dig3_i => dig3_i,
ss_sel_o => ss_sel_o,
ss_o => ss_o);
-- clock generation
clk_i <= not clk_i after 5 ns;
reset_i <= '1' after 10 ns;
-- compare enable signals
-- a_en1_check: assert s_en_1_check = s_en_1_o report "Wrong enable generation by DUT_8" severity error;
-- a_en2_check: assert s_en_2_check = s_en_2_o report "Wrong enable generation by DUT_32" severity error;
end sim;
-------------------------------------------------------------------------------
configuration tb_bcd_driver_sim_cfg of tb_bcd_driver is
for sim
end for;
end tb_bcd_driver_sim_cfg;
-------------------------------------------------------------------------------
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlut8 IS
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlut8;
ARCHITECTURE rtl OF fp_lnlut8 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "00000000" =>
inv <= conv_std_logic_vector(1024,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "00000001" =>
inv <= conv_std_logic_vector(2041,11);
logman <= conv_std_logic_vector(6316601,23);
logexp <= conv_std_logic_vector(118,8);
WHEN "00000010" =>
inv <= conv_std_logic_vector(2033,11);
logman <= conv_std_logic_vector(7397915,23);
logexp <= conv_std_logic_vector(119,8);
WHEN "00000011" =>
inv <= conv_std_logic_vector(2025,11);
logman <= conv_std_logic_vector(3738239,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000100" =>
inv <= conv_std_logic_vector(2017,11);
logman <= conv_std_logic_vector(7988584,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000101" =>
inv <= conv_std_logic_vector(2009,11);
logman <= conv_std_logic_vector(1933606,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000110" =>
inv <= conv_std_logic_vector(2002,11);
logman <= conv_std_logic_vector(3807503,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000111" =>
inv <= conv_std_logic_vector(1994,11);
logman <= conv_std_logic_vector(5957139,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001000" =>
inv <= conv_std_logic_vector(1986,11);
logman <= conv_std_logic_vector(8115417,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001001" =>
inv <= conv_std_logic_vector(1979,11);
logman <= conv_std_logic_vector(811223,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001010" =>
inv <= conv_std_logic_vector(1972,11);
logman <= conv_std_logic_vector(1762400,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001011" =>
inv <= conv_std_logic_vector(1964,11);
logman <= conv_std_logic_vector(2853602,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001100" =>
inv <= conv_std_logic_vector(1957,11);
logman <= conv_std_logic_vector(3812057,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001101" =>
inv <= conv_std_logic_vector(1950,11);
logman <= conv_std_logic_vector(4773946,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001110" =>
inv <= conv_std_logic_vector(1942,11);
logman <= conv_std_logic_vector(5877485,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001111" =>
inv <= conv_std_logic_vector(1935,11);
logman <= conv_std_logic_vector(6846817,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010000" =>
inv <= conv_std_logic_vector(1928,11);
logman <= conv_std_logic_vector(7819662,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010001" =>
inv <= conv_std_logic_vector(1921,11);
logman <= conv_std_logic_vector(203719,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010010" =>
inv <= conv_std_logic_vector(1914,11);
logman <= conv_std_logic_vector(693693,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010011" =>
inv <= conv_std_logic_vector(1907,11);
logman <= conv_std_logic_vector(1185462,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010100" =>
inv <= conv_std_logic_vector(1900,11);
logman <= conv_std_logic_vector(1679040,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010101" =>
inv <= conv_std_logic_vector(1893,11);
logman <= conv_std_logic_vector(2174439,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010110" =>
inv <= conv_std_logic_vector(1886,11);
logman <= conv_std_logic_vector(2671674,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010111" =>
inv <= conv_std_logic_vector(1880,11);
logman <= conv_std_logic_vector(3099346,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011000" =>
inv <= conv_std_logic_vector(1873,11);
logman <= conv_std_logic_vector(3600026,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011001" =>
inv <= conv_std_logic_vector(1866,11);
logman <= conv_std_logic_vector(4102580,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011010" =>
inv <= conv_std_logic_vector(1860,11);
logman <= conv_std_logic_vector(4534844,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011011" =>
inv <= conv_std_logic_vector(1853,11);
logman <= conv_std_logic_vector(5040917,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011100" =>
inv <= conv_std_logic_vector(1847,11);
logman <= conv_std_logic_vector(5476218,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011101" =>
inv <= conv_std_logic_vector(1840,11);
logman <= conv_std_logic_vector(5985860,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011110" =>
inv <= conv_std_logic_vector(1834,11);
logman <= conv_std_logic_vector(6424242,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011111" =>
inv <= conv_std_logic_vector(1827,11);
logman <= conv_std_logic_vector(6937504,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100000" =>
inv <= conv_std_logic_vector(1821,11);
logman <= conv_std_logic_vector(7379010,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100001" =>
inv <= conv_std_logic_vector(1815,11);
logman <= conv_std_logic_vector(7821973,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100010" =>
inv <= conv_std_logic_vector(1808,11);
logman <= conv_std_logic_vector(8340618,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100011" =>
inv <= conv_std_logic_vector(1802,11);
logman <= conv_std_logic_vector(199082,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100100" =>
inv <= conv_std_logic_vector(1796,11);
logman <= conv_std_logic_vector(422902,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100101" =>
inv <= conv_std_logic_vector(1790,11);
logman <= conv_std_logic_vector(647472,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100110" =>
inv <= conv_std_logic_vector(1784,11);
logman <= conv_std_logic_vector(872796,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100111" =>
inv <= conv_std_logic_vector(1778,11);
logman <= conv_std_logic_vector(1098879,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101000" =>
inv <= conv_std_logic_vector(1772,11);
logman <= conv_std_logic_vector(1325726,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101001" =>
inv <= conv_std_logic_vector(1766,11);
logman <= conv_std_logic_vector(1553342,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101010" =>
inv <= conv_std_logic_vector(1760,11);
logman <= conv_std_logic_vector(1781734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101011" =>
inv <= conv_std_logic_vector(1754,11);
logman <= conv_std_logic_vector(2010905,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101100" =>
inv <= conv_std_logic_vector(1748,11);
logman <= conv_std_logic_vector(2240861,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101101" =>
inv <= conv_std_logic_vector(1742,11);
logman <= conv_std_logic_vector(2471608,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101110" =>
inv <= conv_std_logic_vector(1737,11);
logman <= conv_std_logic_vector(2664505,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101111" =>
inv <= conv_std_logic_vector(1731,11);
logman <= conv_std_logic_vector(2896716,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110000" =>
inv <= conv_std_logic_vector(1725,11);
logman <= conv_std_logic_vector(3129733,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110001" =>
inv <= conv_std_logic_vector(1719,11);
logman <= conv_std_logic_vector(3363562,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110010" =>
inv <= conv_std_logic_vector(1714,11);
logman <= conv_std_logic_vector(3559044,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110011" =>
inv <= conv_std_logic_vector(1708,11);
logman <= conv_std_logic_vector(3794376,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110100" =>
inv <= conv_std_logic_vector(1703,11);
logman <= conv_std_logic_vector(3991119,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110101" =>
inv <= conv_std_logic_vector(1697,11);
logman <= conv_std_logic_vector(4227974,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110110" =>
inv <= conv_std_logic_vector(1692,11);
logman <= conv_std_logic_vector(4425994,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110111" =>
inv <= conv_std_logic_vector(1686,11);
logman <= conv_std_logic_vector(4664391,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111000" =>
inv <= conv_std_logic_vector(1681,11);
logman <= conv_std_logic_vector(4863705,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111001" =>
inv <= conv_std_logic_vector(1676,11);
logman <= conv_std_logic_vector(5063612,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111010" =>
inv <= conv_std_logic_vector(1670,11);
logman <= conv_std_logic_vector(5304290,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111011" =>
inv <= conv_std_logic_vector(1665,11);
logman <= conv_std_logic_vector(5505516,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111100" =>
inv <= conv_std_logic_vector(1660,11);
logman <= conv_std_logic_vector(5707347,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111101" =>
inv <= conv_std_logic_vector(1654,11);
logman <= conv_std_logic_vector(5950349,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111110" =>
inv <= conv_std_logic_vector(1649,11);
logman <= conv_std_logic_vector(6153525,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111111" =>
inv <= conv_std_logic_vector(1644,11);
logman <= conv_std_logic_vector(6357317,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000000" =>
inv <= conv_std_logic_vector(1639,11);
logman <= conv_std_logic_vector(6561731,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000001" =>
inv <= conv_std_logic_vector(1634,11);
logman <= conv_std_logic_vector(6766769,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000010" =>
inv <= conv_std_logic_vector(1629,11);
logman <= conv_std_logic_vector(6972435,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000011" =>
inv <= conv_std_logic_vector(1624,11);
logman <= conv_std_logic_vector(7178734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000100" =>
inv <= conv_std_logic_vector(1619,11);
logman <= conv_std_logic_vector(7385668,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000101" =>
inv <= conv_std_logic_vector(1614,11);
logman <= conv_std_logic_vector(7593243,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000110" =>
inv <= conv_std_logic_vector(1609,11);
logman <= conv_std_logic_vector(7801462,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000111" =>
inv <= conv_std_logic_vector(1604,11);
logman <= conv_std_logic_vector(8010329,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001000" =>
inv <= conv_std_logic_vector(1599,11);
logman <= conv_std_logic_vector(8219848,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001001" =>
inv <= conv_std_logic_vector(1594,11);
logman <= conv_std_logic_vector(20707,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001010" =>
inv <= conv_std_logic_vector(1589,11);
logman <= conv_std_logic_vector(126125,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001011" =>
inv <= conv_std_logic_vector(1584,11);
logman <= conv_std_logic_vector(231875,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001100" =>
inv <= conv_std_logic_vector(1580,11);
logman <= conv_std_logic_vector(316716,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001101" =>
inv <= conv_std_logic_vector(1575,11);
logman <= conv_std_logic_vector(423069,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001110" =>
inv <= conv_std_logic_vector(1570,11);
logman <= conv_std_logic_vector(529760,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001111" =>
inv <= conv_std_logic_vector(1566,11);
logman <= conv_std_logic_vector(615358,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010000" =>
inv <= conv_std_logic_vector(1561,11);
logman <= conv_std_logic_vector(722664,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010001" =>
inv <= conv_std_logic_vector(1556,11);
logman <= conv_std_logic_vector(830314,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010010" =>
inv <= conv_std_logic_vector(1552,11);
logman <= conv_std_logic_vector(916683,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010011" =>
inv <= conv_std_logic_vector(1547,11);
logman <= conv_std_logic_vector(1024958,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010100" =>
inv <= conv_std_logic_vector(1543,11);
logman <= conv_std_logic_vector(1111831,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010101" =>
inv <= conv_std_logic_vector(1538,11);
logman <= conv_std_logic_vector(1220738,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010110" =>
inv <= conv_std_logic_vector(1534,11);
logman <= conv_std_logic_vector(1308120,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010111" =>
inv <= conv_std_logic_vector(1529,11);
logman <= conv_std_logic_vector(1417667,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011000" =>
inv <= conv_std_logic_vector(1525,11);
logman <= conv_std_logic_vector(1505564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011001" =>
inv <= conv_std_logic_vector(1520,11);
logman <= conv_std_logic_vector(1615759,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011010" =>
inv <= conv_std_logic_vector(1516,11);
logman <= conv_std_logic_vector(1704177,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011011" =>
inv <= conv_std_logic_vector(1511,11);
logman <= conv_std_logic_vector(1815027,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011100" =>
inv <= conv_std_logic_vector(1507,11);
logman <= conv_std_logic_vector(1903972,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011101" =>
inv <= conv_std_logic_vector(1503,11);
logman <= conv_std_logic_vector(1993153,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011110" =>
inv <= conv_std_logic_vector(1498,11);
logman <= conv_std_logic_vector(2104964,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011111" =>
inv <= conv_std_logic_vector(1494,11);
logman <= conv_std_logic_vector(2194682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100000" =>
inv <= conv_std_logic_vector(1490,11);
logman <= conv_std_logic_vector(2284640,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100001" =>
inv <= conv_std_logic_vector(1486,11);
logman <= conv_std_logic_vector(2374840,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100010" =>
inv <= conv_std_logic_vector(1482,11);
logman <= conv_std_logic_vector(2465284,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100011" =>
inv <= conv_std_logic_vector(1477,11);
logman <= conv_std_logic_vector(2578682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100100" =>
inv <= conv_std_logic_vector(1473,11);
logman <= conv_std_logic_vector(2669677,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100101" =>
inv <= conv_std_logic_vector(1469,11);
logman <= conv_std_logic_vector(2760919,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100110" =>
inv <= conv_std_logic_vector(1465,11);
logman <= conv_std_logic_vector(2852411,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100111" =>
inv <= conv_std_logic_vector(1461,11);
logman <= conv_std_logic_vector(2944152,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101000" =>
inv <= conv_std_logic_vector(1457,11);
logman <= conv_std_logic_vector(3036145,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101001" =>
inv <= conv_std_logic_vector(1453,11);
logman <= conv_std_logic_vector(3128391,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101010" =>
inv <= conv_std_logic_vector(1449,11);
logman <= conv_std_logic_vector(3220891,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101011" =>
inv <= conv_std_logic_vector(1445,11);
logman <= conv_std_logic_vector(3313647,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101100" =>
inv <= conv_std_logic_vector(1441,11);
logman <= conv_std_logic_vector(3406660,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101101" =>
inv <= conv_std_logic_vector(1437,11);
logman <= conv_std_logic_vector(3499932,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101110" =>
inv <= conv_std_logic_vector(1433,11);
logman <= conv_std_logic_vector(3593464,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101111" =>
inv <= conv_std_logic_vector(1429,11);
logman <= conv_std_logic_vector(3687257,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110000" =>
inv <= conv_std_logic_vector(1425,11);
logman <= conv_std_logic_vector(3781312,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110001" =>
inv <= conv_std_logic_vector(1421,11);
logman <= conv_std_logic_vector(3875633,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110010" =>
inv <= conv_std_logic_vector(1417,11);
logman <= conv_std_logic_vector(3970219,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110011" =>
inv <= conv_std_logic_vector(1414,11);
logman <= conv_std_logic_vector(4041334,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110100" =>
inv <= conv_std_logic_vector(1410,11);
logman <= conv_std_logic_vector(4136389,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110101" =>
inv <= conv_std_logic_vector(1406,11);
logman <= conv_std_logic_vector(4231714,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110110" =>
inv <= conv_std_logic_vector(1402,11);
logman <= conv_std_logic_vector(4327311,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110111" =>
inv <= conv_std_logic_vector(1399,11);
logman <= conv_std_logic_vector(4399188,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111000" =>
inv <= conv_std_logic_vector(1395,11);
logman <= conv_std_logic_vector(4495263,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111001" =>
inv <= conv_std_logic_vector(1391,11);
logman <= conv_std_logic_vector(4591615,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111010" =>
inv <= conv_std_logic_vector(1388,11);
logman <= conv_std_logic_vector(4664061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111011" =>
inv <= conv_std_logic_vector(1384,11);
logman <= conv_std_logic_vector(4760899,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111100" =>
inv <= conv_std_logic_vector(1380,11);
logman <= conv_std_logic_vector(4858018,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111101" =>
inv <= conv_std_logic_vector(1377,11);
logman <= conv_std_logic_vector(4931041,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111110" =>
inv <= conv_std_logic_vector(1373,11);
logman <= conv_std_logic_vector(5028654,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111111" =>
inv <= conv_std_logic_vector(1369,11);
logman <= conv_std_logic_vector(5126552,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000000" =>
inv <= conv_std_logic_vector(1366,11);
logman <= conv_std_logic_vector(5200163,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000001" =>
inv <= conv_std_logic_vector(1362,11);
logman <= conv_std_logic_vector(5298564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000010" =>
inv <= conv_std_logic_vector(1359,11);
logman <= conv_std_logic_vector(5372554,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000011" =>
inv <= conv_std_logic_vector(1355,11);
logman <= conv_std_logic_vector(5471461,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000100" =>
inv <= conv_std_logic_vector(1352,11);
logman <= conv_std_logic_vector(5545834,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000101" =>
inv <= conv_std_logic_vector(1348,11);
logman <= conv_std_logic_vector(5645255,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000110" =>
inv <= conv_std_logic_vector(1345,11);
logman <= conv_std_logic_vector(5720014,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000111" =>
inv <= conv_std_logic_vector(1341,11);
logman <= conv_std_logic_vector(5819953,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001000" =>
inv <= conv_std_logic_vector(1338,11);
logman <= conv_std_logic_vector(5895103,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001001" =>
inv <= conv_std_logic_vector(1335,11);
logman <= conv_std_logic_vector(5970421,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001010" =>
inv <= conv_std_logic_vector(1331,11);
logman <= conv_std_logic_vector(6071110,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001011" =>
inv <= conv_std_logic_vector(1328,11);
logman <= conv_std_logic_vector(6146825,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001100" =>
inv <= conv_std_logic_vector(1324,11);
logman <= conv_std_logic_vector(6248045,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001101" =>
inv <= conv_std_logic_vector(1321,11);
logman <= conv_std_logic_vector(6324161,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001110" =>
inv <= conv_std_logic_vector(1318,11);
logman <= conv_std_logic_vector(6400450,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001111" =>
inv <= conv_std_logic_vector(1315,11);
logman <= conv_std_logic_vector(6476913,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010000" =>
inv <= conv_std_logic_vector(1311,11);
logman <= conv_std_logic_vector(6579135,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010001" =>
inv <= conv_std_logic_vector(1308,11);
logman <= conv_std_logic_vector(6656007,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010010" =>
inv <= conv_std_logic_vector(1305,11);
logman <= conv_std_logic_vector(6733055,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010011" =>
inv <= conv_std_logic_vector(1301,11);
logman <= conv_std_logic_vector(6836061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010100" =>
inv <= conv_std_logic_vector(1298,11);
logman <= conv_std_logic_vector(6913525,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010101" =>
inv <= conv_std_logic_vector(1295,11);
logman <= conv_std_logic_vector(6991167,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010110" =>
inv <= conv_std_logic_vector(1292,11);
logman <= conv_std_logic_vector(7068989,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010111" =>
inv <= conv_std_logic_vector(1289,11);
logman <= conv_std_logic_vector(7146993,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011000" =>
inv <= conv_std_logic_vector(1286,11);
logman <= conv_std_logic_vector(7225178,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011001" =>
inv <= conv_std_logic_vector(1282,11);
logman <= conv_std_logic_vector(7329709,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011010" =>
inv <= conv_std_logic_vector(1279,11);
logman <= conv_std_logic_vector(7408321,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011011" =>
inv <= conv_std_logic_vector(1276,11);
logman <= conv_std_logic_vector(7487119,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011100" =>
inv <= conv_std_logic_vector(1273,11);
logman <= conv_std_logic_vector(7566101,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011101" =>
inv <= conv_std_logic_vector(1270,11);
logman <= conv_std_logic_vector(7645270,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011110" =>
inv <= conv_std_logic_vector(1267,11);
logman <= conv_std_logic_vector(7724626,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011111" =>
inv <= conv_std_logic_vector(1264,11);
logman <= conv_std_logic_vector(7804171,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100000" =>
inv <= conv_std_logic_vector(1261,11);
logman <= conv_std_logic_vector(7883904,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100001" =>
inv <= conv_std_logic_vector(1258,11);
logman <= conv_std_logic_vector(7963827,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100010" =>
inv <= conv_std_logic_vector(1255,11);
logman <= conv_std_logic_vector(8043941,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100011" =>
inv <= conv_std_logic_vector(1252,11);
logman <= conv_std_logic_vector(8124247,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100100" =>
inv <= conv_std_logic_vector(1249,11);
logman <= conv_std_logic_vector(8204746,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100101" =>
inv <= conv_std_logic_vector(1246,11);
logman <= conv_std_logic_vector(8285438,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100110" =>
inv <= conv_std_logic_vector(1243,11);
logman <= conv_std_logic_vector(8366324,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100111" =>
inv <= conv_std_logic_vector(1240,11);
logman <= conv_std_logic_vector(29399,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101000" =>
inv <= conv_std_logic_vector(1237,11);
logman <= conv_std_logic_vector(70038,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101001" =>
inv <= conv_std_logic_vector(1234,11);
logman <= conv_std_logic_vector(110776,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101010" =>
inv <= conv_std_logic_vector(1231,11);
logman <= conv_std_logic_vector(151613,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101011" =>
inv <= conv_std_logic_vector(1228,11);
logman <= conv_std_logic_vector(192550,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101100" =>
inv <= conv_std_logic_vector(1225,11);
logman <= conv_std_logic_vector(233587,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101101" =>
inv <= conv_std_logic_vector(1223,11);
logman <= conv_std_logic_vector(261001,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101110" =>
inv <= conv_std_logic_vector(1220,11);
logman <= conv_std_logic_vector(302205,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101111" =>
inv <= conv_std_logic_vector(1217,11);
logman <= conv_std_logic_vector(343512,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110000" =>
inv <= conv_std_logic_vector(1214,11);
logman <= conv_std_logic_vector(384920,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110001" =>
inv <= conv_std_logic_vector(1211,11);
logman <= conv_std_logic_vector(426431,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110010" =>
inv <= conv_std_logic_vector(1209,11);
logman <= conv_std_logic_vector(454162,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110011" =>
inv <= conv_std_logic_vector(1206,11);
logman <= conv_std_logic_vector(495844,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110100" =>
inv <= conv_std_logic_vector(1203,11);
logman <= conv_std_logic_vector(537630,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110101" =>
inv <= conv_std_logic_vector(1200,11);
logman <= conv_std_logic_vector(579521,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110110" =>
inv <= conv_std_logic_vector(1198,11);
logman <= conv_std_logic_vector(607506,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110111" =>
inv <= conv_std_logic_vector(1195,11);
logman <= conv_std_logic_vector(649572,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111000" =>
inv <= conv_std_logic_vector(1192,11);
logman <= conv_std_logic_vector(691744,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111001" =>
inv <= conv_std_logic_vector(1189,11);
logman <= conv_std_logic_vector(734021,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111010" =>
inv <= conv_std_logic_vector(1187,11);
logman <= conv_std_logic_vector(762266,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111011" =>
inv <= conv_std_logic_vector(1184,11);
logman <= conv_std_logic_vector(804722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111100" =>
inv <= conv_std_logic_vector(1181,11);
logman <= conv_std_logic_vector(847286,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111101" =>
inv <= conv_std_logic_vector(1179,11);
logman <= conv_std_logic_vector(875722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111110" =>
inv <= conv_std_logic_vector(1176,11);
logman <= conv_std_logic_vector(918466,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111111" =>
inv <= conv_std_logic_vector(1173,11);
logman <= conv_std_logic_vector(961320,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000000" =>
inv <= conv_std_logic_vector(1171,11);
logman <= conv_std_logic_vector(989950,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000001" =>
inv <= conv_std_logic_vector(1168,11);
logman <= conv_std_logic_vector(1032987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000010" =>
inv <= conv_std_logic_vector(1166,11);
logman <= conv_std_logic_vector(1061740,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000011" =>
inv <= conv_std_logic_vector(1163,11);
logman <= conv_std_logic_vector(1104961,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000100" =>
inv <= conv_std_logic_vector(1160,11);
logman <= conv_std_logic_vector(1148295,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000101" =>
inv <= conv_std_logic_vector(1158,11);
logman <= conv_std_logic_vector(1177246,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000110" =>
inv <= conv_std_logic_vector(1155,11);
logman <= conv_std_logic_vector(1220767,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000111" =>
inv <= conv_std_logic_vector(1153,11);
logman <= conv_std_logic_vector(1249843,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001000" =>
inv <= conv_std_logic_vector(1150,11);
logman <= conv_std_logic_vector(1293553,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001001" =>
inv <= conv_std_logic_vector(1148,11);
logman <= conv_std_logic_vector(1322756,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001010" =>
inv <= conv_std_logic_vector(1145,11);
logman <= conv_std_logic_vector(1366656,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001011" =>
inv <= conv_std_logic_vector(1143,11);
logman <= conv_std_logic_vector(1395987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001100" =>
inv <= conv_std_logic_vector(1140,11);
logman <= conv_std_logic_vector(1440080,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001101" =>
inv <= conv_std_logic_vector(1138,11);
logman <= conv_std_logic_vector(1469539,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001110" =>
inv <= conv_std_logic_vector(1135,11);
logman <= conv_std_logic_vector(1513826,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001111" =>
inv <= conv_std_logic_vector(1133,11);
logman <= conv_std_logic_vector(1543415,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010000" =>
inv <= conv_std_logic_vector(1130,11);
logman <= conv_std_logic_vector(1587898,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010001" =>
inv <= conv_std_logic_vector(1128,11);
logman <= conv_std_logic_vector(1617618,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010010" =>
inv <= conv_std_logic_vector(1126,11);
logman <= conv_std_logic_vector(1647391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010011" =>
inv <= conv_std_logic_vector(1123,11);
logman <= conv_std_logic_vector(1692151,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010100" =>
inv <= conv_std_logic_vector(1121,11);
logman <= conv_std_logic_vector(1722056,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010101" =>
inv <= conv_std_logic_vector(1118,11);
logman <= conv_std_logic_vector(1767016,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010110" =>
inv <= conv_std_logic_vector(1116,11);
logman <= conv_std_logic_vector(1797055,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010111" =>
inv <= conv_std_logic_vector(1114,11);
logman <= conv_std_logic_vector(1827149,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011000" =>
inv <= conv_std_logic_vector(1111,11);
logman <= conv_std_logic_vector(1872391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011001" =>
inv <= conv_std_logic_vector(1109,11);
logman <= conv_std_logic_vector(1902620,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011010" =>
inv <= conv_std_logic_vector(1107,11);
logman <= conv_std_logic_vector(1932904,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011011" =>
inv <= conv_std_logic_vector(1104,11);
logman <= conv_std_logic_vector(1978432,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011100" =>
inv <= conv_std_logic_vector(1102,11);
logman <= conv_std_logic_vector(2008853,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011101" =>
inv <= conv_std_logic_vector(1100,11);
logman <= conv_std_logic_vector(2039330,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011110" =>
inv <= conv_std_logic_vector(1097,11);
logman <= conv_std_logic_vector(2085148,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011111" =>
inv <= conv_std_logic_vector(1095,11);
logman <= conv_std_logic_vector(2115764,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100000" =>
inv <= conv_std_logic_vector(1093,11);
logman <= conv_std_logic_vector(2146435,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100001" =>
inv <= conv_std_logic_vector(1090,11);
logman <= conv_std_logic_vector(2192547,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100010" =>
inv <= conv_std_logic_vector(1088,11);
logman <= conv_std_logic_vector(2223360,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100011" =>
inv <= conv_std_logic_vector(1086,11);
logman <= conv_std_logic_vector(2254228,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100100" =>
inv <= conv_std_logic_vector(1084,11);
logman <= conv_std_logic_vector(2285154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100101" =>
inv <= conv_std_logic_vector(1082,11);
logman <= conv_std_logic_vector(2316137,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100110" =>
inv <= conv_std_logic_vector(1079,11);
logman <= conv_std_logic_vector(2362719,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100111" =>
inv <= conv_std_logic_vector(1077,11);
logman <= conv_std_logic_vector(2393845,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101000" =>
inv <= conv_std_logic_vector(1075,11);
logman <= conv_std_logic_vector(2425030,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101001" =>
inv <= conv_std_logic_vector(1073,11);
logman <= conv_std_logic_vector(2456272,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101010" =>
inv <= conv_std_logic_vector(1070,11);
logman <= conv_std_logic_vector(2503245,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101011" =>
inv <= conv_std_logic_vector(1068,11);
logman <= conv_std_logic_vector(2534634,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101100" =>
inv <= conv_std_logic_vector(1066,11);
logman <= conv_std_logic_vector(2566082,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101101" =>
inv <= conv_std_logic_vector(1064,11);
logman <= conv_std_logic_vector(2597588,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101110" =>
inv <= conv_std_logic_vector(1062,11);
logman <= conv_std_logic_vector(2629154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101111" =>
inv <= conv_std_logic_vector(1060,11);
logman <= conv_std_logic_vector(2660779,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110000" =>
inv <= conv_std_logic_vector(1058,11);
logman <= conv_std_logic_vector(2692464,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110001" =>
inv <= conv_std_logic_vector(1055,11);
logman <= conv_std_logic_vector(2740104,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110010" =>
inv <= conv_std_logic_vector(1053,11);
logman <= conv_std_logic_vector(2771940,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110011" =>
inv <= conv_std_logic_vector(1051,11);
logman <= conv_std_logic_vector(2803835,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110100" =>
inv <= conv_std_logic_vector(1049,11);
logman <= conv_std_logic_vector(2835792,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110101" =>
inv <= conv_std_logic_vector(1047,11);
logman <= conv_std_logic_vector(2867810,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110110" =>
inv <= conv_std_logic_vector(1045,11);
logman <= conv_std_logic_vector(2899888,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110111" =>
inv <= conv_std_logic_vector(1043,11);
logman <= conv_std_logic_vector(2932029,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111000" =>
inv <= conv_std_logic_vector(1041,11);
logman <= conv_std_logic_vector(2964231,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111001" =>
inv <= conv_std_logic_vector(1039,11);
logman <= conv_std_logic_vector(2996495,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111010" =>
inv <= conv_std_logic_vector(1037,11);
logman <= conv_std_logic_vector(3028821,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111011" =>
inv <= conv_std_logic_vector(1035,11);
logman <= conv_std_logic_vector(3061209,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111100" =>
inv <= conv_std_logic_vector(1033,11);
logman <= conv_std_logic_vector(3093660,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111101" =>
inv <= conv_std_logic_vector(1031,11);
logman <= conv_std_logic_vector(3126174,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111110" =>
inv <= conv_std_logic_vector(1029,11);
logman <= conv_std_logic_vector(3158751,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111111" =>
inv <= conv_std_logic_vector(1027,11);
logman <= conv_std_logic_vector(3191392,23);
logexp <= conv_std_logic_vector(126,8);
WHEN others =>
inv <= conv_std_logic_vector(0,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlut8 IS
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlut8;
ARCHITECTURE rtl OF fp_lnlut8 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "00000000" =>
inv <= conv_std_logic_vector(1024,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "00000001" =>
inv <= conv_std_logic_vector(2041,11);
logman <= conv_std_logic_vector(6316601,23);
logexp <= conv_std_logic_vector(118,8);
WHEN "00000010" =>
inv <= conv_std_logic_vector(2033,11);
logman <= conv_std_logic_vector(7397915,23);
logexp <= conv_std_logic_vector(119,8);
WHEN "00000011" =>
inv <= conv_std_logic_vector(2025,11);
logman <= conv_std_logic_vector(3738239,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000100" =>
inv <= conv_std_logic_vector(2017,11);
logman <= conv_std_logic_vector(7988584,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000101" =>
inv <= conv_std_logic_vector(2009,11);
logman <= conv_std_logic_vector(1933606,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000110" =>
inv <= conv_std_logic_vector(2002,11);
logman <= conv_std_logic_vector(3807503,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000111" =>
inv <= conv_std_logic_vector(1994,11);
logman <= conv_std_logic_vector(5957139,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001000" =>
inv <= conv_std_logic_vector(1986,11);
logman <= conv_std_logic_vector(8115417,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001001" =>
inv <= conv_std_logic_vector(1979,11);
logman <= conv_std_logic_vector(811223,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001010" =>
inv <= conv_std_logic_vector(1972,11);
logman <= conv_std_logic_vector(1762400,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001011" =>
inv <= conv_std_logic_vector(1964,11);
logman <= conv_std_logic_vector(2853602,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001100" =>
inv <= conv_std_logic_vector(1957,11);
logman <= conv_std_logic_vector(3812057,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001101" =>
inv <= conv_std_logic_vector(1950,11);
logman <= conv_std_logic_vector(4773946,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001110" =>
inv <= conv_std_logic_vector(1942,11);
logman <= conv_std_logic_vector(5877485,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001111" =>
inv <= conv_std_logic_vector(1935,11);
logman <= conv_std_logic_vector(6846817,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010000" =>
inv <= conv_std_logic_vector(1928,11);
logman <= conv_std_logic_vector(7819662,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010001" =>
inv <= conv_std_logic_vector(1921,11);
logman <= conv_std_logic_vector(203719,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010010" =>
inv <= conv_std_logic_vector(1914,11);
logman <= conv_std_logic_vector(693693,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010011" =>
inv <= conv_std_logic_vector(1907,11);
logman <= conv_std_logic_vector(1185462,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010100" =>
inv <= conv_std_logic_vector(1900,11);
logman <= conv_std_logic_vector(1679040,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010101" =>
inv <= conv_std_logic_vector(1893,11);
logman <= conv_std_logic_vector(2174439,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010110" =>
inv <= conv_std_logic_vector(1886,11);
logman <= conv_std_logic_vector(2671674,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010111" =>
inv <= conv_std_logic_vector(1880,11);
logman <= conv_std_logic_vector(3099346,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011000" =>
inv <= conv_std_logic_vector(1873,11);
logman <= conv_std_logic_vector(3600026,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011001" =>
inv <= conv_std_logic_vector(1866,11);
logman <= conv_std_logic_vector(4102580,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011010" =>
inv <= conv_std_logic_vector(1860,11);
logman <= conv_std_logic_vector(4534844,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011011" =>
inv <= conv_std_logic_vector(1853,11);
logman <= conv_std_logic_vector(5040917,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011100" =>
inv <= conv_std_logic_vector(1847,11);
logman <= conv_std_logic_vector(5476218,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011101" =>
inv <= conv_std_logic_vector(1840,11);
logman <= conv_std_logic_vector(5985860,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011110" =>
inv <= conv_std_logic_vector(1834,11);
logman <= conv_std_logic_vector(6424242,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011111" =>
inv <= conv_std_logic_vector(1827,11);
logman <= conv_std_logic_vector(6937504,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100000" =>
inv <= conv_std_logic_vector(1821,11);
logman <= conv_std_logic_vector(7379010,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100001" =>
inv <= conv_std_logic_vector(1815,11);
logman <= conv_std_logic_vector(7821973,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100010" =>
inv <= conv_std_logic_vector(1808,11);
logman <= conv_std_logic_vector(8340618,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100011" =>
inv <= conv_std_logic_vector(1802,11);
logman <= conv_std_logic_vector(199082,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100100" =>
inv <= conv_std_logic_vector(1796,11);
logman <= conv_std_logic_vector(422902,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100101" =>
inv <= conv_std_logic_vector(1790,11);
logman <= conv_std_logic_vector(647472,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100110" =>
inv <= conv_std_logic_vector(1784,11);
logman <= conv_std_logic_vector(872796,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100111" =>
inv <= conv_std_logic_vector(1778,11);
logman <= conv_std_logic_vector(1098879,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101000" =>
inv <= conv_std_logic_vector(1772,11);
logman <= conv_std_logic_vector(1325726,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101001" =>
inv <= conv_std_logic_vector(1766,11);
logman <= conv_std_logic_vector(1553342,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101010" =>
inv <= conv_std_logic_vector(1760,11);
logman <= conv_std_logic_vector(1781734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101011" =>
inv <= conv_std_logic_vector(1754,11);
logman <= conv_std_logic_vector(2010905,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101100" =>
inv <= conv_std_logic_vector(1748,11);
logman <= conv_std_logic_vector(2240861,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101101" =>
inv <= conv_std_logic_vector(1742,11);
logman <= conv_std_logic_vector(2471608,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101110" =>
inv <= conv_std_logic_vector(1737,11);
logman <= conv_std_logic_vector(2664505,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101111" =>
inv <= conv_std_logic_vector(1731,11);
logman <= conv_std_logic_vector(2896716,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110000" =>
inv <= conv_std_logic_vector(1725,11);
logman <= conv_std_logic_vector(3129733,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110001" =>
inv <= conv_std_logic_vector(1719,11);
logman <= conv_std_logic_vector(3363562,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110010" =>
inv <= conv_std_logic_vector(1714,11);
logman <= conv_std_logic_vector(3559044,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110011" =>
inv <= conv_std_logic_vector(1708,11);
logman <= conv_std_logic_vector(3794376,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110100" =>
inv <= conv_std_logic_vector(1703,11);
logman <= conv_std_logic_vector(3991119,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110101" =>
inv <= conv_std_logic_vector(1697,11);
logman <= conv_std_logic_vector(4227974,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110110" =>
inv <= conv_std_logic_vector(1692,11);
logman <= conv_std_logic_vector(4425994,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110111" =>
inv <= conv_std_logic_vector(1686,11);
logman <= conv_std_logic_vector(4664391,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111000" =>
inv <= conv_std_logic_vector(1681,11);
logman <= conv_std_logic_vector(4863705,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111001" =>
inv <= conv_std_logic_vector(1676,11);
logman <= conv_std_logic_vector(5063612,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111010" =>
inv <= conv_std_logic_vector(1670,11);
logman <= conv_std_logic_vector(5304290,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111011" =>
inv <= conv_std_logic_vector(1665,11);
logman <= conv_std_logic_vector(5505516,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111100" =>
inv <= conv_std_logic_vector(1660,11);
logman <= conv_std_logic_vector(5707347,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111101" =>
inv <= conv_std_logic_vector(1654,11);
logman <= conv_std_logic_vector(5950349,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111110" =>
inv <= conv_std_logic_vector(1649,11);
logman <= conv_std_logic_vector(6153525,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111111" =>
inv <= conv_std_logic_vector(1644,11);
logman <= conv_std_logic_vector(6357317,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000000" =>
inv <= conv_std_logic_vector(1639,11);
logman <= conv_std_logic_vector(6561731,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000001" =>
inv <= conv_std_logic_vector(1634,11);
logman <= conv_std_logic_vector(6766769,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000010" =>
inv <= conv_std_logic_vector(1629,11);
logman <= conv_std_logic_vector(6972435,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000011" =>
inv <= conv_std_logic_vector(1624,11);
logman <= conv_std_logic_vector(7178734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000100" =>
inv <= conv_std_logic_vector(1619,11);
logman <= conv_std_logic_vector(7385668,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000101" =>
inv <= conv_std_logic_vector(1614,11);
logman <= conv_std_logic_vector(7593243,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000110" =>
inv <= conv_std_logic_vector(1609,11);
logman <= conv_std_logic_vector(7801462,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000111" =>
inv <= conv_std_logic_vector(1604,11);
logman <= conv_std_logic_vector(8010329,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001000" =>
inv <= conv_std_logic_vector(1599,11);
logman <= conv_std_logic_vector(8219848,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001001" =>
inv <= conv_std_logic_vector(1594,11);
logman <= conv_std_logic_vector(20707,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001010" =>
inv <= conv_std_logic_vector(1589,11);
logman <= conv_std_logic_vector(126125,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001011" =>
inv <= conv_std_logic_vector(1584,11);
logman <= conv_std_logic_vector(231875,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001100" =>
inv <= conv_std_logic_vector(1580,11);
logman <= conv_std_logic_vector(316716,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001101" =>
inv <= conv_std_logic_vector(1575,11);
logman <= conv_std_logic_vector(423069,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001110" =>
inv <= conv_std_logic_vector(1570,11);
logman <= conv_std_logic_vector(529760,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001111" =>
inv <= conv_std_logic_vector(1566,11);
logman <= conv_std_logic_vector(615358,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010000" =>
inv <= conv_std_logic_vector(1561,11);
logman <= conv_std_logic_vector(722664,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010001" =>
inv <= conv_std_logic_vector(1556,11);
logman <= conv_std_logic_vector(830314,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010010" =>
inv <= conv_std_logic_vector(1552,11);
logman <= conv_std_logic_vector(916683,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010011" =>
inv <= conv_std_logic_vector(1547,11);
logman <= conv_std_logic_vector(1024958,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010100" =>
inv <= conv_std_logic_vector(1543,11);
logman <= conv_std_logic_vector(1111831,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010101" =>
inv <= conv_std_logic_vector(1538,11);
logman <= conv_std_logic_vector(1220738,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010110" =>
inv <= conv_std_logic_vector(1534,11);
logman <= conv_std_logic_vector(1308120,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010111" =>
inv <= conv_std_logic_vector(1529,11);
logman <= conv_std_logic_vector(1417667,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011000" =>
inv <= conv_std_logic_vector(1525,11);
logman <= conv_std_logic_vector(1505564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011001" =>
inv <= conv_std_logic_vector(1520,11);
logman <= conv_std_logic_vector(1615759,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011010" =>
inv <= conv_std_logic_vector(1516,11);
logman <= conv_std_logic_vector(1704177,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011011" =>
inv <= conv_std_logic_vector(1511,11);
logman <= conv_std_logic_vector(1815027,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011100" =>
inv <= conv_std_logic_vector(1507,11);
logman <= conv_std_logic_vector(1903972,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011101" =>
inv <= conv_std_logic_vector(1503,11);
logman <= conv_std_logic_vector(1993153,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011110" =>
inv <= conv_std_logic_vector(1498,11);
logman <= conv_std_logic_vector(2104964,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011111" =>
inv <= conv_std_logic_vector(1494,11);
logman <= conv_std_logic_vector(2194682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100000" =>
inv <= conv_std_logic_vector(1490,11);
logman <= conv_std_logic_vector(2284640,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100001" =>
inv <= conv_std_logic_vector(1486,11);
logman <= conv_std_logic_vector(2374840,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100010" =>
inv <= conv_std_logic_vector(1482,11);
logman <= conv_std_logic_vector(2465284,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100011" =>
inv <= conv_std_logic_vector(1477,11);
logman <= conv_std_logic_vector(2578682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100100" =>
inv <= conv_std_logic_vector(1473,11);
logman <= conv_std_logic_vector(2669677,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100101" =>
inv <= conv_std_logic_vector(1469,11);
logman <= conv_std_logic_vector(2760919,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100110" =>
inv <= conv_std_logic_vector(1465,11);
logman <= conv_std_logic_vector(2852411,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100111" =>
inv <= conv_std_logic_vector(1461,11);
logman <= conv_std_logic_vector(2944152,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101000" =>
inv <= conv_std_logic_vector(1457,11);
logman <= conv_std_logic_vector(3036145,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101001" =>
inv <= conv_std_logic_vector(1453,11);
logman <= conv_std_logic_vector(3128391,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101010" =>
inv <= conv_std_logic_vector(1449,11);
logman <= conv_std_logic_vector(3220891,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101011" =>
inv <= conv_std_logic_vector(1445,11);
logman <= conv_std_logic_vector(3313647,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101100" =>
inv <= conv_std_logic_vector(1441,11);
logman <= conv_std_logic_vector(3406660,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101101" =>
inv <= conv_std_logic_vector(1437,11);
logman <= conv_std_logic_vector(3499932,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101110" =>
inv <= conv_std_logic_vector(1433,11);
logman <= conv_std_logic_vector(3593464,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101111" =>
inv <= conv_std_logic_vector(1429,11);
logman <= conv_std_logic_vector(3687257,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110000" =>
inv <= conv_std_logic_vector(1425,11);
logman <= conv_std_logic_vector(3781312,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110001" =>
inv <= conv_std_logic_vector(1421,11);
logman <= conv_std_logic_vector(3875633,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110010" =>
inv <= conv_std_logic_vector(1417,11);
logman <= conv_std_logic_vector(3970219,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110011" =>
inv <= conv_std_logic_vector(1414,11);
logman <= conv_std_logic_vector(4041334,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110100" =>
inv <= conv_std_logic_vector(1410,11);
logman <= conv_std_logic_vector(4136389,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110101" =>
inv <= conv_std_logic_vector(1406,11);
logman <= conv_std_logic_vector(4231714,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110110" =>
inv <= conv_std_logic_vector(1402,11);
logman <= conv_std_logic_vector(4327311,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110111" =>
inv <= conv_std_logic_vector(1399,11);
logman <= conv_std_logic_vector(4399188,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111000" =>
inv <= conv_std_logic_vector(1395,11);
logman <= conv_std_logic_vector(4495263,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111001" =>
inv <= conv_std_logic_vector(1391,11);
logman <= conv_std_logic_vector(4591615,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111010" =>
inv <= conv_std_logic_vector(1388,11);
logman <= conv_std_logic_vector(4664061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111011" =>
inv <= conv_std_logic_vector(1384,11);
logman <= conv_std_logic_vector(4760899,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111100" =>
inv <= conv_std_logic_vector(1380,11);
logman <= conv_std_logic_vector(4858018,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111101" =>
inv <= conv_std_logic_vector(1377,11);
logman <= conv_std_logic_vector(4931041,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111110" =>
inv <= conv_std_logic_vector(1373,11);
logman <= conv_std_logic_vector(5028654,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111111" =>
inv <= conv_std_logic_vector(1369,11);
logman <= conv_std_logic_vector(5126552,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000000" =>
inv <= conv_std_logic_vector(1366,11);
logman <= conv_std_logic_vector(5200163,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000001" =>
inv <= conv_std_logic_vector(1362,11);
logman <= conv_std_logic_vector(5298564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000010" =>
inv <= conv_std_logic_vector(1359,11);
logman <= conv_std_logic_vector(5372554,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000011" =>
inv <= conv_std_logic_vector(1355,11);
logman <= conv_std_logic_vector(5471461,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000100" =>
inv <= conv_std_logic_vector(1352,11);
logman <= conv_std_logic_vector(5545834,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000101" =>
inv <= conv_std_logic_vector(1348,11);
logman <= conv_std_logic_vector(5645255,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000110" =>
inv <= conv_std_logic_vector(1345,11);
logman <= conv_std_logic_vector(5720014,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000111" =>
inv <= conv_std_logic_vector(1341,11);
logman <= conv_std_logic_vector(5819953,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001000" =>
inv <= conv_std_logic_vector(1338,11);
logman <= conv_std_logic_vector(5895103,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001001" =>
inv <= conv_std_logic_vector(1335,11);
logman <= conv_std_logic_vector(5970421,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001010" =>
inv <= conv_std_logic_vector(1331,11);
logman <= conv_std_logic_vector(6071110,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001011" =>
inv <= conv_std_logic_vector(1328,11);
logman <= conv_std_logic_vector(6146825,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001100" =>
inv <= conv_std_logic_vector(1324,11);
logman <= conv_std_logic_vector(6248045,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001101" =>
inv <= conv_std_logic_vector(1321,11);
logman <= conv_std_logic_vector(6324161,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001110" =>
inv <= conv_std_logic_vector(1318,11);
logman <= conv_std_logic_vector(6400450,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001111" =>
inv <= conv_std_logic_vector(1315,11);
logman <= conv_std_logic_vector(6476913,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010000" =>
inv <= conv_std_logic_vector(1311,11);
logman <= conv_std_logic_vector(6579135,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010001" =>
inv <= conv_std_logic_vector(1308,11);
logman <= conv_std_logic_vector(6656007,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010010" =>
inv <= conv_std_logic_vector(1305,11);
logman <= conv_std_logic_vector(6733055,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010011" =>
inv <= conv_std_logic_vector(1301,11);
logman <= conv_std_logic_vector(6836061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010100" =>
inv <= conv_std_logic_vector(1298,11);
logman <= conv_std_logic_vector(6913525,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010101" =>
inv <= conv_std_logic_vector(1295,11);
logman <= conv_std_logic_vector(6991167,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010110" =>
inv <= conv_std_logic_vector(1292,11);
logman <= conv_std_logic_vector(7068989,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010111" =>
inv <= conv_std_logic_vector(1289,11);
logman <= conv_std_logic_vector(7146993,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011000" =>
inv <= conv_std_logic_vector(1286,11);
logman <= conv_std_logic_vector(7225178,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011001" =>
inv <= conv_std_logic_vector(1282,11);
logman <= conv_std_logic_vector(7329709,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011010" =>
inv <= conv_std_logic_vector(1279,11);
logman <= conv_std_logic_vector(7408321,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011011" =>
inv <= conv_std_logic_vector(1276,11);
logman <= conv_std_logic_vector(7487119,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011100" =>
inv <= conv_std_logic_vector(1273,11);
logman <= conv_std_logic_vector(7566101,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011101" =>
inv <= conv_std_logic_vector(1270,11);
logman <= conv_std_logic_vector(7645270,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011110" =>
inv <= conv_std_logic_vector(1267,11);
logman <= conv_std_logic_vector(7724626,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011111" =>
inv <= conv_std_logic_vector(1264,11);
logman <= conv_std_logic_vector(7804171,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100000" =>
inv <= conv_std_logic_vector(1261,11);
logman <= conv_std_logic_vector(7883904,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100001" =>
inv <= conv_std_logic_vector(1258,11);
logman <= conv_std_logic_vector(7963827,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100010" =>
inv <= conv_std_logic_vector(1255,11);
logman <= conv_std_logic_vector(8043941,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100011" =>
inv <= conv_std_logic_vector(1252,11);
logman <= conv_std_logic_vector(8124247,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100100" =>
inv <= conv_std_logic_vector(1249,11);
logman <= conv_std_logic_vector(8204746,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100101" =>
inv <= conv_std_logic_vector(1246,11);
logman <= conv_std_logic_vector(8285438,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100110" =>
inv <= conv_std_logic_vector(1243,11);
logman <= conv_std_logic_vector(8366324,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100111" =>
inv <= conv_std_logic_vector(1240,11);
logman <= conv_std_logic_vector(29399,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101000" =>
inv <= conv_std_logic_vector(1237,11);
logman <= conv_std_logic_vector(70038,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101001" =>
inv <= conv_std_logic_vector(1234,11);
logman <= conv_std_logic_vector(110776,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101010" =>
inv <= conv_std_logic_vector(1231,11);
logman <= conv_std_logic_vector(151613,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101011" =>
inv <= conv_std_logic_vector(1228,11);
logman <= conv_std_logic_vector(192550,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101100" =>
inv <= conv_std_logic_vector(1225,11);
logman <= conv_std_logic_vector(233587,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101101" =>
inv <= conv_std_logic_vector(1223,11);
logman <= conv_std_logic_vector(261001,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101110" =>
inv <= conv_std_logic_vector(1220,11);
logman <= conv_std_logic_vector(302205,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101111" =>
inv <= conv_std_logic_vector(1217,11);
logman <= conv_std_logic_vector(343512,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110000" =>
inv <= conv_std_logic_vector(1214,11);
logman <= conv_std_logic_vector(384920,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110001" =>
inv <= conv_std_logic_vector(1211,11);
logman <= conv_std_logic_vector(426431,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110010" =>
inv <= conv_std_logic_vector(1209,11);
logman <= conv_std_logic_vector(454162,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110011" =>
inv <= conv_std_logic_vector(1206,11);
logman <= conv_std_logic_vector(495844,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110100" =>
inv <= conv_std_logic_vector(1203,11);
logman <= conv_std_logic_vector(537630,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110101" =>
inv <= conv_std_logic_vector(1200,11);
logman <= conv_std_logic_vector(579521,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110110" =>
inv <= conv_std_logic_vector(1198,11);
logman <= conv_std_logic_vector(607506,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110111" =>
inv <= conv_std_logic_vector(1195,11);
logman <= conv_std_logic_vector(649572,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111000" =>
inv <= conv_std_logic_vector(1192,11);
logman <= conv_std_logic_vector(691744,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111001" =>
inv <= conv_std_logic_vector(1189,11);
logman <= conv_std_logic_vector(734021,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111010" =>
inv <= conv_std_logic_vector(1187,11);
logman <= conv_std_logic_vector(762266,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111011" =>
inv <= conv_std_logic_vector(1184,11);
logman <= conv_std_logic_vector(804722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111100" =>
inv <= conv_std_logic_vector(1181,11);
logman <= conv_std_logic_vector(847286,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111101" =>
inv <= conv_std_logic_vector(1179,11);
logman <= conv_std_logic_vector(875722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111110" =>
inv <= conv_std_logic_vector(1176,11);
logman <= conv_std_logic_vector(918466,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111111" =>
inv <= conv_std_logic_vector(1173,11);
logman <= conv_std_logic_vector(961320,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000000" =>
inv <= conv_std_logic_vector(1171,11);
logman <= conv_std_logic_vector(989950,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000001" =>
inv <= conv_std_logic_vector(1168,11);
logman <= conv_std_logic_vector(1032987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000010" =>
inv <= conv_std_logic_vector(1166,11);
logman <= conv_std_logic_vector(1061740,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000011" =>
inv <= conv_std_logic_vector(1163,11);
logman <= conv_std_logic_vector(1104961,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000100" =>
inv <= conv_std_logic_vector(1160,11);
logman <= conv_std_logic_vector(1148295,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000101" =>
inv <= conv_std_logic_vector(1158,11);
logman <= conv_std_logic_vector(1177246,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000110" =>
inv <= conv_std_logic_vector(1155,11);
logman <= conv_std_logic_vector(1220767,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000111" =>
inv <= conv_std_logic_vector(1153,11);
logman <= conv_std_logic_vector(1249843,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001000" =>
inv <= conv_std_logic_vector(1150,11);
logman <= conv_std_logic_vector(1293553,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001001" =>
inv <= conv_std_logic_vector(1148,11);
logman <= conv_std_logic_vector(1322756,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001010" =>
inv <= conv_std_logic_vector(1145,11);
logman <= conv_std_logic_vector(1366656,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001011" =>
inv <= conv_std_logic_vector(1143,11);
logman <= conv_std_logic_vector(1395987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001100" =>
inv <= conv_std_logic_vector(1140,11);
logman <= conv_std_logic_vector(1440080,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001101" =>
inv <= conv_std_logic_vector(1138,11);
logman <= conv_std_logic_vector(1469539,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001110" =>
inv <= conv_std_logic_vector(1135,11);
logman <= conv_std_logic_vector(1513826,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001111" =>
inv <= conv_std_logic_vector(1133,11);
logman <= conv_std_logic_vector(1543415,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010000" =>
inv <= conv_std_logic_vector(1130,11);
logman <= conv_std_logic_vector(1587898,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010001" =>
inv <= conv_std_logic_vector(1128,11);
logman <= conv_std_logic_vector(1617618,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010010" =>
inv <= conv_std_logic_vector(1126,11);
logman <= conv_std_logic_vector(1647391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010011" =>
inv <= conv_std_logic_vector(1123,11);
logman <= conv_std_logic_vector(1692151,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010100" =>
inv <= conv_std_logic_vector(1121,11);
logman <= conv_std_logic_vector(1722056,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010101" =>
inv <= conv_std_logic_vector(1118,11);
logman <= conv_std_logic_vector(1767016,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010110" =>
inv <= conv_std_logic_vector(1116,11);
logman <= conv_std_logic_vector(1797055,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010111" =>
inv <= conv_std_logic_vector(1114,11);
logman <= conv_std_logic_vector(1827149,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011000" =>
inv <= conv_std_logic_vector(1111,11);
logman <= conv_std_logic_vector(1872391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011001" =>
inv <= conv_std_logic_vector(1109,11);
logman <= conv_std_logic_vector(1902620,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011010" =>
inv <= conv_std_logic_vector(1107,11);
logman <= conv_std_logic_vector(1932904,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011011" =>
inv <= conv_std_logic_vector(1104,11);
logman <= conv_std_logic_vector(1978432,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011100" =>
inv <= conv_std_logic_vector(1102,11);
logman <= conv_std_logic_vector(2008853,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011101" =>
inv <= conv_std_logic_vector(1100,11);
logman <= conv_std_logic_vector(2039330,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011110" =>
inv <= conv_std_logic_vector(1097,11);
logman <= conv_std_logic_vector(2085148,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011111" =>
inv <= conv_std_logic_vector(1095,11);
logman <= conv_std_logic_vector(2115764,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100000" =>
inv <= conv_std_logic_vector(1093,11);
logman <= conv_std_logic_vector(2146435,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100001" =>
inv <= conv_std_logic_vector(1090,11);
logman <= conv_std_logic_vector(2192547,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100010" =>
inv <= conv_std_logic_vector(1088,11);
logman <= conv_std_logic_vector(2223360,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100011" =>
inv <= conv_std_logic_vector(1086,11);
logman <= conv_std_logic_vector(2254228,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100100" =>
inv <= conv_std_logic_vector(1084,11);
logman <= conv_std_logic_vector(2285154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100101" =>
inv <= conv_std_logic_vector(1082,11);
logman <= conv_std_logic_vector(2316137,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100110" =>
inv <= conv_std_logic_vector(1079,11);
logman <= conv_std_logic_vector(2362719,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100111" =>
inv <= conv_std_logic_vector(1077,11);
logman <= conv_std_logic_vector(2393845,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101000" =>
inv <= conv_std_logic_vector(1075,11);
logman <= conv_std_logic_vector(2425030,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101001" =>
inv <= conv_std_logic_vector(1073,11);
logman <= conv_std_logic_vector(2456272,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101010" =>
inv <= conv_std_logic_vector(1070,11);
logman <= conv_std_logic_vector(2503245,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101011" =>
inv <= conv_std_logic_vector(1068,11);
logman <= conv_std_logic_vector(2534634,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101100" =>
inv <= conv_std_logic_vector(1066,11);
logman <= conv_std_logic_vector(2566082,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101101" =>
inv <= conv_std_logic_vector(1064,11);
logman <= conv_std_logic_vector(2597588,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101110" =>
inv <= conv_std_logic_vector(1062,11);
logman <= conv_std_logic_vector(2629154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101111" =>
inv <= conv_std_logic_vector(1060,11);
logman <= conv_std_logic_vector(2660779,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110000" =>
inv <= conv_std_logic_vector(1058,11);
logman <= conv_std_logic_vector(2692464,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110001" =>
inv <= conv_std_logic_vector(1055,11);
logman <= conv_std_logic_vector(2740104,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110010" =>
inv <= conv_std_logic_vector(1053,11);
logman <= conv_std_logic_vector(2771940,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110011" =>
inv <= conv_std_logic_vector(1051,11);
logman <= conv_std_logic_vector(2803835,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110100" =>
inv <= conv_std_logic_vector(1049,11);
logman <= conv_std_logic_vector(2835792,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110101" =>
inv <= conv_std_logic_vector(1047,11);
logman <= conv_std_logic_vector(2867810,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110110" =>
inv <= conv_std_logic_vector(1045,11);
logman <= conv_std_logic_vector(2899888,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110111" =>
inv <= conv_std_logic_vector(1043,11);
logman <= conv_std_logic_vector(2932029,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111000" =>
inv <= conv_std_logic_vector(1041,11);
logman <= conv_std_logic_vector(2964231,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111001" =>
inv <= conv_std_logic_vector(1039,11);
logman <= conv_std_logic_vector(2996495,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111010" =>
inv <= conv_std_logic_vector(1037,11);
logman <= conv_std_logic_vector(3028821,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111011" =>
inv <= conv_std_logic_vector(1035,11);
logman <= conv_std_logic_vector(3061209,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111100" =>
inv <= conv_std_logic_vector(1033,11);
logman <= conv_std_logic_vector(3093660,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111101" =>
inv <= conv_std_logic_vector(1031,11);
logman <= conv_std_logic_vector(3126174,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111110" =>
inv <= conv_std_logic_vector(1029,11);
logman <= conv_std_logic_vector(3158751,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111111" =>
inv <= conv_std_logic_vector(1027,11);
logman <= conv_std_logic_vector(3191392,23);
logexp <= conv_std_logic_vector(126,8);
WHEN others =>
inv <= conv_std_logic_vector(0,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlut8 IS
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlut8;
ARCHITECTURE rtl OF fp_lnlut8 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "00000000" =>
inv <= conv_std_logic_vector(1024,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "00000001" =>
inv <= conv_std_logic_vector(2041,11);
logman <= conv_std_logic_vector(6316601,23);
logexp <= conv_std_logic_vector(118,8);
WHEN "00000010" =>
inv <= conv_std_logic_vector(2033,11);
logman <= conv_std_logic_vector(7397915,23);
logexp <= conv_std_logic_vector(119,8);
WHEN "00000011" =>
inv <= conv_std_logic_vector(2025,11);
logman <= conv_std_logic_vector(3738239,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000100" =>
inv <= conv_std_logic_vector(2017,11);
logman <= conv_std_logic_vector(7988584,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000101" =>
inv <= conv_std_logic_vector(2009,11);
logman <= conv_std_logic_vector(1933606,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000110" =>
inv <= conv_std_logic_vector(2002,11);
logman <= conv_std_logic_vector(3807503,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000111" =>
inv <= conv_std_logic_vector(1994,11);
logman <= conv_std_logic_vector(5957139,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001000" =>
inv <= conv_std_logic_vector(1986,11);
logman <= conv_std_logic_vector(8115417,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001001" =>
inv <= conv_std_logic_vector(1979,11);
logman <= conv_std_logic_vector(811223,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001010" =>
inv <= conv_std_logic_vector(1972,11);
logman <= conv_std_logic_vector(1762400,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001011" =>
inv <= conv_std_logic_vector(1964,11);
logman <= conv_std_logic_vector(2853602,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001100" =>
inv <= conv_std_logic_vector(1957,11);
logman <= conv_std_logic_vector(3812057,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001101" =>
inv <= conv_std_logic_vector(1950,11);
logman <= conv_std_logic_vector(4773946,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001110" =>
inv <= conv_std_logic_vector(1942,11);
logman <= conv_std_logic_vector(5877485,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001111" =>
inv <= conv_std_logic_vector(1935,11);
logman <= conv_std_logic_vector(6846817,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010000" =>
inv <= conv_std_logic_vector(1928,11);
logman <= conv_std_logic_vector(7819662,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010001" =>
inv <= conv_std_logic_vector(1921,11);
logman <= conv_std_logic_vector(203719,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010010" =>
inv <= conv_std_logic_vector(1914,11);
logman <= conv_std_logic_vector(693693,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010011" =>
inv <= conv_std_logic_vector(1907,11);
logman <= conv_std_logic_vector(1185462,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010100" =>
inv <= conv_std_logic_vector(1900,11);
logman <= conv_std_logic_vector(1679040,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010101" =>
inv <= conv_std_logic_vector(1893,11);
logman <= conv_std_logic_vector(2174439,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010110" =>
inv <= conv_std_logic_vector(1886,11);
logman <= conv_std_logic_vector(2671674,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010111" =>
inv <= conv_std_logic_vector(1880,11);
logman <= conv_std_logic_vector(3099346,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011000" =>
inv <= conv_std_logic_vector(1873,11);
logman <= conv_std_logic_vector(3600026,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011001" =>
inv <= conv_std_logic_vector(1866,11);
logman <= conv_std_logic_vector(4102580,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011010" =>
inv <= conv_std_logic_vector(1860,11);
logman <= conv_std_logic_vector(4534844,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011011" =>
inv <= conv_std_logic_vector(1853,11);
logman <= conv_std_logic_vector(5040917,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011100" =>
inv <= conv_std_logic_vector(1847,11);
logman <= conv_std_logic_vector(5476218,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011101" =>
inv <= conv_std_logic_vector(1840,11);
logman <= conv_std_logic_vector(5985860,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011110" =>
inv <= conv_std_logic_vector(1834,11);
logman <= conv_std_logic_vector(6424242,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011111" =>
inv <= conv_std_logic_vector(1827,11);
logman <= conv_std_logic_vector(6937504,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100000" =>
inv <= conv_std_logic_vector(1821,11);
logman <= conv_std_logic_vector(7379010,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100001" =>
inv <= conv_std_logic_vector(1815,11);
logman <= conv_std_logic_vector(7821973,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100010" =>
inv <= conv_std_logic_vector(1808,11);
logman <= conv_std_logic_vector(8340618,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100011" =>
inv <= conv_std_logic_vector(1802,11);
logman <= conv_std_logic_vector(199082,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100100" =>
inv <= conv_std_logic_vector(1796,11);
logman <= conv_std_logic_vector(422902,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100101" =>
inv <= conv_std_logic_vector(1790,11);
logman <= conv_std_logic_vector(647472,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100110" =>
inv <= conv_std_logic_vector(1784,11);
logman <= conv_std_logic_vector(872796,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100111" =>
inv <= conv_std_logic_vector(1778,11);
logman <= conv_std_logic_vector(1098879,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101000" =>
inv <= conv_std_logic_vector(1772,11);
logman <= conv_std_logic_vector(1325726,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101001" =>
inv <= conv_std_logic_vector(1766,11);
logman <= conv_std_logic_vector(1553342,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101010" =>
inv <= conv_std_logic_vector(1760,11);
logman <= conv_std_logic_vector(1781734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101011" =>
inv <= conv_std_logic_vector(1754,11);
logman <= conv_std_logic_vector(2010905,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101100" =>
inv <= conv_std_logic_vector(1748,11);
logman <= conv_std_logic_vector(2240861,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101101" =>
inv <= conv_std_logic_vector(1742,11);
logman <= conv_std_logic_vector(2471608,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101110" =>
inv <= conv_std_logic_vector(1737,11);
logman <= conv_std_logic_vector(2664505,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101111" =>
inv <= conv_std_logic_vector(1731,11);
logman <= conv_std_logic_vector(2896716,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110000" =>
inv <= conv_std_logic_vector(1725,11);
logman <= conv_std_logic_vector(3129733,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110001" =>
inv <= conv_std_logic_vector(1719,11);
logman <= conv_std_logic_vector(3363562,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110010" =>
inv <= conv_std_logic_vector(1714,11);
logman <= conv_std_logic_vector(3559044,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110011" =>
inv <= conv_std_logic_vector(1708,11);
logman <= conv_std_logic_vector(3794376,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110100" =>
inv <= conv_std_logic_vector(1703,11);
logman <= conv_std_logic_vector(3991119,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110101" =>
inv <= conv_std_logic_vector(1697,11);
logman <= conv_std_logic_vector(4227974,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110110" =>
inv <= conv_std_logic_vector(1692,11);
logman <= conv_std_logic_vector(4425994,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110111" =>
inv <= conv_std_logic_vector(1686,11);
logman <= conv_std_logic_vector(4664391,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111000" =>
inv <= conv_std_logic_vector(1681,11);
logman <= conv_std_logic_vector(4863705,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111001" =>
inv <= conv_std_logic_vector(1676,11);
logman <= conv_std_logic_vector(5063612,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111010" =>
inv <= conv_std_logic_vector(1670,11);
logman <= conv_std_logic_vector(5304290,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111011" =>
inv <= conv_std_logic_vector(1665,11);
logman <= conv_std_logic_vector(5505516,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111100" =>
inv <= conv_std_logic_vector(1660,11);
logman <= conv_std_logic_vector(5707347,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111101" =>
inv <= conv_std_logic_vector(1654,11);
logman <= conv_std_logic_vector(5950349,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111110" =>
inv <= conv_std_logic_vector(1649,11);
logman <= conv_std_logic_vector(6153525,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111111" =>
inv <= conv_std_logic_vector(1644,11);
logman <= conv_std_logic_vector(6357317,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000000" =>
inv <= conv_std_logic_vector(1639,11);
logman <= conv_std_logic_vector(6561731,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000001" =>
inv <= conv_std_logic_vector(1634,11);
logman <= conv_std_logic_vector(6766769,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000010" =>
inv <= conv_std_logic_vector(1629,11);
logman <= conv_std_logic_vector(6972435,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000011" =>
inv <= conv_std_logic_vector(1624,11);
logman <= conv_std_logic_vector(7178734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000100" =>
inv <= conv_std_logic_vector(1619,11);
logman <= conv_std_logic_vector(7385668,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000101" =>
inv <= conv_std_logic_vector(1614,11);
logman <= conv_std_logic_vector(7593243,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000110" =>
inv <= conv_std_logic_vector(1609,11);
logman <= conv_std_logic_vector(7801462,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000111" =>
inv <= conv_std_logic_vector(1604,11);
logman <= conv_std_logic_vector(8010329,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001000" =>
inv <= conv_std_logic_vector(1599,11);
logman <= conv_std_logic_vector(8219848,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001001" =>
inv <= conv_std_logic_vector(1594,11);
logman <= conv_std_logic_vector(20707,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001010" =>
inv <= conv_std_logic_vector(1589,11);
logman <= conv_std_logic_vector(126125,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001011" =>
inv <= conv_std_logic_vector(1584,11);
logman <= conv_std_logic_vector(231875,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001100" =>
inv <= conv_std_logic_vector(1580,11);
logman <= conv_std_logic_vector(316716,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001101" =>
inv <= conv_std_logic_vector(1575,11);
logman <= conv_std_logic_vector(423069,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001110" =>
inv <= conv_std_logic_vector(1570,11);
logman <= conv_std_logic_vector(529760,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001111" =>
inv <= conv_std_logic_vector(1566,11);
logman <= conv_std_logic_vector(615358,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010000" =>
inv <= conv_std_logic_vector(1561,11);
logman <= conv_std_logic_vector(722664,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010001" =>
inv <= conv_std_logic_vector(1556,11);
logman <= conv_std_logic_vector(830314,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010010" =>
inv <= conv_std_logic_vector(1552,11);
logman <= conv_std_logic_vector(916683,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010011" =>
inv <= conv_std_logic_vector(1547,11);
logman <= conv_std_logic_vector(1024958,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010100" =>
inv <= conv_std_logic_vector(1543,11);
logman <= conv_std_logic_vector(1111831,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010101" =>
inv <= conv_std_logic_vector(1538,11);
logman <= conv_std_logic_vector(1220738,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010110" =>
inv <= conv_std_logic_vector(1534,11);
logman <= conv_std_logic_vector(1308120,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010111" =>
inv <= conv_std_logic_vector(1529,11);
logman <= conv_std_logic_vector(1417667,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011000" =>
inv <= conv_std_logic_vector(1525,11);
logman <= conv_std_logic_vector(1505564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011001" =>
inv <= conv_std_logic_vector(1520,11);
logman <= conv_std_logic_vector(1615759,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011010" =>
inv <= conv_std_logic_vector(1516,11);
logman <= conv_std_logic_vector(1704177,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011011" =>
inv <= conv_std_logic_vector(1511,11);
logman <= conv_std_logic_vector(1815027,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011100" =>
inv <= conv_std_logic_vector(1507,11);
logman <= conv_std_logic_vector(1903972,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011101" =>
inv <= conv_std_logic_vector(1503,11);
logman <= conv_std_logic_vector(1993153,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011110" =>
inv <= conv_std_logic_vector(1498,11);
logman <= conv_std_logic_vector(2104964,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011111" =>
inv <= conv_std_logic_vector(1494,11);
logman <= conv_std_logic_vector(2194682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100000" =>
inv <= conv_std_logic_vector(1490,11);
logman <= conv_std_logic_vector(2284640,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100001" =>
inv <= conv_std_logic_vector(1486,11);
logman <= conv_std_logic_vector(2374840,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100010" =>
inv <= conv_std_logic_vector(1482,11);
logman <= conv_std_logic_vector(2465284,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100011" =>
inv <= conv_std_logic_vector(1477,11);
logman <= conv_std_logic_vector(2578682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100100" =>
inv <= conv_std_logic_vector(1473,11);
logman <= conv_std_logic_vector(2669677,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100101" =>
inv <= conv_std_logic_vector(1469,11);
logman <= conv_std_logic_vector(2760919,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100110" =>
inv <= conv_std_logic_vector(1465,11);
logman <= conv_std_logic_vector(2852411,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100111" =>
inv <= conv_std_logic_vector(1461,11);
logman <= conv_std_logic_vector(2944152,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101000" =>
inv <= conv_std_logic_vector(1457,11);
logman <= conv_std_logic_vector(3036145,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101001" =>
inv <= conv_std_logic_vector(1453,11);
logman <= conv_std_logic_vector(3128391,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101010" =>
inv <= conv_std_logic_vector(1449,11);
logman <= conv_std_logic_vector(3220891,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101011" =>
inv <= conv_std_logic_vector(1445,11);
logman <= conv_std_logic_vector(3313647,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101100" =>
inv <= conv_std_logic_vector(1441,11);
logman <= conv_std_logic_vector(3406660,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101101" =>
inv <= conv_std_logic_vector(1437,11);
logman <= conv_std_logic_vector(3499932,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101110" =>
inv <= conv_std_logic_vector(1433,11);
logman <= conv_std_logic_vector(3593464,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101111" =>
inv <= conv_std_logic_vector(1429,11);
logman <= conv_std_logic_vector(3687257,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110000" =>
inv <= conv_std_logic_vector(1425,11);
logman <= conv_std_logic_vector(3781312,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110001" =>
inv <= conv_std_logic_vector(1421,11);
logman <= conv_std_logic_vector(3875633,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110010" =>
inv <= conv_std_logic_vector(1417,11);
logman <= conv_std_logic_vector(3970219,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110011" =>
inv <= conv_std_logic_vector(1414,11);
logman <= conv_std_logic_vector(4041334,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110100" =>
inv <= conv_std_logic_vector(1410,11);
logman <= conv_std_logic_vector(4136389,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110101" =>
inv <= conv_std_logic_vector(1406,11);
logman <= conv_std_logic_vector(4231714,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110110" =>
inv <= conv_std_logic_vector(1402,11);
logman <= conv_std_logic_vector(4327311,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110111" =>
inv <= conv_std_logic_vector(1399,11);
logman <= conv_std_logic_vector(4399188,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111000" =>
inv <= conv_std_logic_vector(1395,11);
logman <= conv_std_logic_vector(4495263,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111001" =>
inv <= conv_std_logic_vector(1391,11);
logman <= conv_std_logic_vector(4591615,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111010" =>
inv <= conv_std_logic_vector(1388,11);
logman <= conv_std_logic_vector(4664061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111011" =>
inv <= conv_std_logic_vector(1384,11);
logman <= conv_std_logic_vector(4760899,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111100" =>
inv <= conv_std_logic_vector(1380,11);
logman <= conv_std_logic_vector(4858018,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111101" =>
inv <= conv_std_logic_vector(1377,11);
logman <= conv_std_logic_vector(4931041,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111110" =>
inv <= conv_std_logic_vector(1373,11);
logman <= conv_std_logic_vector(5028654,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111111" =>
inv <= conv_std_logic_vector(1369,11);
logman <= conv_std_logic_vector(5126552,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000000" =>
inv <= conv_std_logic_vector(1366,11);
logman <= conv_std_logic_vector(5200163,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000001" =>
inv <= conv_std_logic_vector(1362,11);
logman <= conv_std_logic_vector(5298564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000010" =>
inv <= conv_std_logic_vector(1359,11);
logman <= conv_std_logic_vector(5372554,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000011" =>
inv <= conv_std_logic_vector(1355,11);
logman <= conv_std_logic_vector(5471461,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000100" =>
inv <= conv_std_logic_vector(1352,11);
logman <= conv_std_logic_vector(5545834,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000101" =>
inv <= conv_std_logic_vector(1348,11);
logman <= conv_std_logic_vector(5645255,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000110" =>
inv <= conv_std_logic_vector(1345,11);
logman <= conv_std_logic_vector(5720014,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000111" =>
inv <= conv_std_logic_vector(1341,11);
logman <= conv_std_logic_vector(5819953,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001000" =>
inv <= conv_std_logic_vector(1338,11);
logman <= conv_std_logic_vector(5895103,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001001" =>
inv <= conv_std_logic_vector(1335,11);
logman <= conv_std_logic_vector(5970421,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001010" =>
inv <= conv_std_logic_vector(1331,11);
logman <= conv_std_logic_vector(6071110,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001011" =>
inv <= conv_std_logic_vector(1328,11);
logman <= conv_std_logic_vector(6146825,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001100" =>
inv <= conv_std_logic_vector(1324,11);
logman <= conv_std_logic_vector(6248045,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001101" =>
inv <= conv_std_logic_vector(1321,11);
logman <= conv_std_logic_vector(6324161,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001110" =>
inv <= conv_std_logic_vector(1318,11);
logman <= conv_std_logic_vector(6400450,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001111" =>
inv <= conv_std_logic_vector(1315,11);
logman <= conv_std_logic_vector(6476913,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010000" =>
inv <= conv_std_logic_vector(1311,11);
logman <= conv_std_logic_vector(6579135,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010001" =>
inv <= conv_std_logic_vector(1308,11);
logman <= conv_std_logic_vector(6656007,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010010" =>
inv <= conv_std_logic_vector(1305,11);
logman <= conv_std_logic_vector(6733055,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010011" =>
inv <= conv_std_logic_vector(1301,11);
logman <= conv_std_logic_vector(6836061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010100" =>
inv <= conv_std_logic_vector(1298,11);
logman <= conv_std_logic_vector(6913525,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010101" =>
inv <= conv_std_logic_vector(1295,11);
logman <= conv_std_logic_vector(6991167,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010110" =>
inv <= conv_std_logic_vector(1292,11);
logman <= conv_std_logic_vector(7068989,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010111" =>
inv <= conv_std_logic_vector(1289,11);
logman <= conv_std_logic_vector(7146993,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011000" =>
inv <= conv_std_logic_vector(1286,11);
logman <= conv_std_logic_vector(7225178,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011001" =>
inv <= conv_std_logic_vector(1282,11);
logman <= conv_std_logic_vector(7329709,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011010" =>
inv <= conv_std_logic_vector(1279,11);
logman <= conv_std_logic_vector(7408321,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011011" =>
inv <= conv_std_logic_vector(1276,11);
logman <= conv_std_logic_vector(7487119,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011100" =>
inv <= conv_std_logic_vector(1273,11);
logman <= conv_std_logic_vector(7566101,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011101" =>
inv <= conv_std_logic_vector(1270,11);
logman <= conv_std_logic_vector(7645270,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011110" =>
inv <= conv_std_logic_vector(1267,11);
logman <= conv_std_logic_vector(7724626,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011111" =>
inv <= conv_std_logic_vector(1264,11);
logman <= conv_std_logic_vector(7804171,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100000" =>
inv <= conv_std_logic_vector(1261,11);
logman <= conv_std_logic_vector(7883904,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100001" =>
inv <= conv_std_logic_vector(1258,11);
logman <= conv_std_logic_vector(7963827,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100010" =>
inv <= conv_std_logic_vector(1255,11);
logman <= conv_std_logic_vector(8043941,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100011" =>
inv <= conv_std_logic_vector(1252,11);
logman <= conv_std_logic_vector(8124247,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100100" =>
inv <= conv_std_logic_vector(1249,11);
logman <= conv_std_logic_vector(8204746,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100101" =>
inv <= conv_std_logic_vector(1246,11);
logman <= conv_std_logic_vector(8285438,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100110" =>
inv <= conv_std_logic_vector(1243,11);
logman <= conv_std_logic_vector(8366324,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100111" =>
inv <= conv_std_logic_vector(1240,11);
logman <= conv_std_logic_vector(29399,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101000" =>
inv <= conv_std_logic_vector(1237,11);
logman <= conv_std_logic_vector(70038,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101001" =>
inv <= conv_std_logic_vector(1234,11);
logman <= conv_std_logic_vector(110776,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101010" =>
inv <= conv_std_logic_vector(1231,11);
logman <= conv_std_logic_vector(151613,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101011" =>
inv <= conv_std_logic_vector(1228,11);
logman <= conv_std_logic_vector(192550,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101100" =>
inv <= conv_std_logic_vector(1225,11);
logman <= conv_std_logic_vector(233587,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101101" =>
inv <= conv_std_logic_vector(1223,11);
logman <= conv_std_logic_vector(261001,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101110" =>
inv <= conv_std_logic_vector(1220,11);
logman <= conv_std_logic_vector(302205,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101111" =>
inv <= conv_std_logic_vector(1217,11);
logman <= conv_std_logic_vector(343512,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110000" =>
inv <= conv_std_logic_vector(1214,11);
logman <= conv_std_logic_vector(384920,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110001" =>
inv <= conv_std_logic_vector(1211,11);
logman <= conv_std_logic_vector(426431,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110010" =>
inv <= conv_std_logic_vector(1209,11);
logman <= conv_std_logic_vector(454162,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110011" =>
inv <= conv_std_logic_vector(1206,11);
logman <= conv_std_logic_vector(495844,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110100" =>
inv <= conv_std_logic_vector(1203,11);
logman <= conv_std_logic_vector(537630,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110101" =>
inv <= conv_std_logic_vector(1200,11);
logman <= conv_std_logic_vector(579521,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110110" =>
inv <= conv_std_logic_vector(1198,11);
logman <= conv_std_logic_vector(607506,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110111" =>
inv <= conv_std_logic_vector(1195,11);
logman <= conv_std_logic_vector(649572,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111000" =>
inv <= conv_std_logic_vector(1192,11);
logman <= conv_std_logic_vector(691744,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111001" =>
inv <= conv_std_logic_vector(1189,11);
logman <= conv_std_logic_vector(734021,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111010" =>
inv <= conv_std_logic_vector(1187,11);
logman <= conv_std_logic_vector(762266,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111011" =>
inv <= conv_std_logic_vector(1184,11);
logman <= conv_std_logic_vector(804722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111100" =>
inv <= conv_std_logic_vector(1181,11);
logman <= conv_std_logic_vector(847286,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111101" =>
inv <= conv_std_logic_vector(1179,11);
logman <= conv_std_logic_vector(875722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111110" =>
inv <= conv_std_logic_vector(1176,11);
logman <= conv_std_logic_vector(918466,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111111" =>
inv <= conv_std_logic_vector(1173,11);
logman <= conv_std_logic_vector(961320,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000000" =>
inv <= conv_std_logic_vector(1171,11);
logman <= conv_std_logic_vector(989950,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000001" =>
inv <= conv_std_logic_vector(1168,11);
logman <= conv_std_logic_vector(1032987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000010" =>
inv <= conv_std_logic_vector(1166,11);
logman <= conv_std_logic_vector(1061740,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000011" =>
inv <= conv_std_logic_vector(1163,11);
logman <= conv_std_logic_vector(1104961,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000100" =>
inv <= conv_std_logic_vector(1160,11);
logman <= conv_std_logic_vector(1148295,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000101" =>
inv <= conv_std_logic_vector(1158,11);
logman <= conv_std_logic_vector(1177246,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000110" =>
inv <= conv_std_logic_vector(1155,11);
logman <= conv_std_logic_vector(1220767,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000111" =>
inv <= conv_std_logic_vector(1153,11);
logman <= conv_std_logic_vector(1249843,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001000" =>
inv <= conv_std_logic_vector(1150,11);
logman <= conv_std_logic_vector(1293553,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001001" =>
inv <= conv_std_logic_vector(1148,11);
logman <= conv_std_logic_vector(1322756,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001010" =>
inv <= conv_std_logic_vector(1145,11);
logman <= conv_std_logic_vector(1366656,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001011" =>
inv <= conv_std_logic_vector(1143,11);
logman <= conv_std_logic_vector(1395987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001100" =>
inv <= conv_std_logic_vector(1140,11);
logman <= conv_std_logic_vector(1440080,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001101" =>
inv <= conv_std_logic_vector(1138,11);
logman <= conv_std_logic_vector(1469539,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001110" =>
inv <= conv_std_logic_vector(1135,11);
logman <= conv_std_logic_vector(1513826,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001111" =>
inv <= conv_std_logic_vector(1133,11);
logman <= conv_std_logic_vector(1543415,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010000" =>
inv <= conv_std_logic_vector(1130,11);
logman <= conv_std_logic_vector(1587898,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010001" =>
inv <= conv_std_logic_vector(1128,11);
logman <= conv_std_logic_vector(1617618,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010010" =>
inv <= conv_std_logic_vector(1126,11);
logman <= conv_std_logic_vector(1647391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010011" =>
inv <= conv_std_logic_vector(1123,11);
logman <= conv_std_logic_vector(1692151,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010100" =>
inv <= conv_std_logic_vector(1121,11);
logman <= conv_std_logic_vector(1722056,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010101" =>
inv <= conv_std_logic_vector(1118,11);
logman <= conv_std_logic_vector(1767016,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010110" =>
inv <= conv_std_logic_vector(1116,11);
logman <= conv_std_logic_vector(1797055,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010111" =>
inv <= conv_std_logic_vector(1114,11);
logman <= conv_std_logic_vector(1827149,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011000" =>
inv <= conv_std_logic_vector(1111,11);
logman <= conv_std_logic_vector(1872391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011001" =>
inv <= conv_std_logic_vector(1109,11);
logman <= conv_std_logic_vector(1902620,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011010" =>
inv <= conv_std_logic_vector(1107,11);
logman <= conv_std_logic_vector(1932904,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011011" =>
inv <= conv_std_logic_vector(1104,11);
logman <= conv_std_logic_vector(1978432,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011100" =>
inv <= conv_std_logic_vector(1102,11);
logman <= conv_std_logic_vector(2008853,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011101" =>
inv <= conv_std_logic_vector(1100,11);
logman <= conv_std_logic_vector(2039330,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011110" =>
inv <= conv_std_logic_vector(1097,11);
logman <= conv_std_logic_vector(2085148,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011111" =>
inv <= conv_std_logic_vector(1095,11);
logman <= conv_std_logic_vector(2115764,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100000" =>
inv <= conv_std_logic_vector(1093,11);
logman <= conv_std_logic_vector(2146435,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100001" =>
inv <= conv_std_logic_vector(1090,11);
logman <= conv_std_logic_vector(2192547,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100010" =>
inv <= conv_std_logic_vector(1088,11);
logman <= conv_std_logic_vector(2223360,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100011" =>
inv <= conv_std_logic_vector(1086,11);
logman <= conv_std_logic_vector(2254228,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100100" =>
inv <= conv_std_logic_vector(1084,11);
logman <= conv_std_logic_vector(2285154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100101" =>
inv <= conv_std_logic_vector(1082,11);
logman <= conv_std_logic_vector(2316137,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100110" =>
inv <= conv_std_logic_vector(1079,11);
logman <= conv_std_logic_vector(2362719,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100111" =>
inv <= conv_std_logic_vector(1077,11);
logman <= conv_std_logic_vector(2393845,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101000" =>
inv <= conv_std_logic_vector(1075,11);
logman <= conv_std_logic_vector(2425030,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101001" =>
inv <= conv_std_logic_vector(1073,11);
logman <= conv_std_logic_vector(2456272,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101010" =>
inv <= conv_std_logic_vector(1070,11);
logman <= conv_std_logic_vector(2503245,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101011" =>
inv <= conv_std_logic_vector(1068,11);
logman <= conv_std_logic_vector(2534634,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101100" =>
inv <= conv_std_logic_vector(1066,11);
logman <= conv_std_logic_vector(2566082,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101101" =>
inv <= conv_std_logic_vector(1064,11);
logman <= conv_std_logic_vector(2597588,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101110" =>
inv <= conv_std_logic_vector(1062,11);
logman <= conv_std_logic_vector(2629154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101111" =>
inv <= conv_std_logic_vector(1060,11);
logman <= conv_std_logic_vector(2660779,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110000" =>
inv <= conv_std_logic_vector(1058,11);
logman <= conv_std_logic_vector(2692464,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110001" =>
inv <= conv_std_logic_vector(1055,11);
logman <= conv_std_logic_vector(2740104,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110010" =>
inv <= conv_std_logic_vector(1053,11);
logman <= conv_std_logic_vector(2771940,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110011" =>
inv <= conv_std_logic_vector(1051,11);
logman <= conv_std_logic_vector(2803835,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110100" =>
inv <= conv_std_logic_vector(1049,11);
logman <= conv_std_logic_vector(2835792,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110101" =>
inv <= conv_std_logic_vector(1047,11);
logman <= conv_std_logic_vector(2867810,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110110" =>
inv <= conv_std_logic_vector(1045,11);
logman <= conv_std_logic_vector(2899888,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110111" =>
inv <= conv_std_logic_vector(1043,11);
logman <= conv_std_logic_vector(2932029,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111000" =>
inv <= conv_std_logic_vector(1041,11);
logman <= conv_std_logic_vector(2964231,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111001" =>
inv <= conv_std_logic_vector(1039,11);
logman <= conv_std_logic_vector(2996495,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111010" =>
inv <= conv_std_logic_vector(1037,11);
logman <= conv_std_logic_vector(3028821,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111011" =>
inv <= conv_std_logic_vector(1035,11);
logman <= conv_std_logic_vector(3061209,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111100" =>
inv <= conv_std_logic_vector(1033,11);
logman <= conv_std_logic_vector(3093660,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111101" =>
inv <= conv_std_logic_vector(1031,11);
logman <= conv_std_logic_vector(3126174,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111110" =>
inv <= conv_std_logic_vector(1029,11);
logman <= conv_std_logic_vector(3158751,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111111" =>
inv <= conv_std_logic_vector(1027,11);
logman <= conv_std_logic_vector(3191392,23);
logexp <= conv_std_logic_vector(126,8);
WHEN others =>
inv <= conv_std_logic_vector(0,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlut8 IS
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlut8;
ARCHITECTURE rtl OF fp_lnlut8 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "00000000" =>
inv <= conv_std_logic_vector(1024,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "00000001" =>
inv <= conv_std_logic_vector(2041,11);
logman <= conv_std_logic_vector(6316601,23);
logexp <= conv_std_logic_vector(118,8);
WHEN "00000010" =>
inv <= conv_std_logic_vector(2033,11);
logman <= conv_std_logic_vector(7397915,23);
logexp <= conv_std_logic_vector(119,8);
WHEN "00000011" =>
inv <= conv_std_logic_vector(2025,11);
logman <= conv_std_logic_vector(3738239,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000100" =>
inv <= conv_std_logic_vector(2017,11);
logman <= conv_std_logic_vector(7988584,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000101" =>
inv <= conv_std_logic_vector(2009,11);
logman <= conv_std_logic_vector(1933606,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000110" =>
inv <= conv_std_logic_vector(2002,11);
logman <= conv_std_logic_vector(3807503,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000111" =>
inv <= conv_std_logic_vector(1994,11);
logman <= conv_std_logic_vector(5957139,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001000" =>
inv <= conv_std_logic_vector(1986,11);
logman <= conv_std_logic_vector(8115417,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001001" =>
inv <= conv_std_logic_vector(1979,11);
logman <= conv_std_logic_vector(811223,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001010" =>
inv <= conv_std_logic_vector(1972,11);
logman <= conv_std_logic_vector(1762400,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001011" =>
inv <= conv_std_logic_vector(1964,11);
logman <= conv_std_logic_vector(2853602,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001100" =>
inv <= conv_std_logic_vector(1957,11);
logman <= conv_std_logic_vector(3812057,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001101" =>
inv <= conv_std_logic_vector(1950,11);
logman <= conv_std_logic_vector(4773946,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001110" =>
inv <= conv_std_logic_vector(1942,11);
logman <= conv_std_logic_vector(5877485,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001111" =>
inv <= conv_std_logic_vector(1935,11);
logman <= conv_std_logic_vector(6846817,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010000" =>
inv <= conv_std_logic_vector(1928,11);
logman <= conv_std_logic_vector(7819662,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010001" =>
inv <= conv_std_logic_vector(1921,11);
logman <= conv_std_logic_vector(203719,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010010" =>
inv <= conv_std_logic_vector(1914,11);
logman <= conv_std_logic_vector(693693,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010011" =>
inv <= conv_std_logic_vector(1907,11);
logman <= conv_std_logic_vector(1185462,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010100" =>
inv <= conv_std_logic_vector(1900,11);
logman <= conv_std_logic_vector(1679040,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010101" =>
inv <= conv_std_logic_vector(1893,11);
logman <= conv_std_logic_vector(2174439,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010110" =>
inv <= conv_std_logic_vector(1886,11);
logman <= conv_std_logic_vector(2671674,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010111" =>
inv <= conv_std_logic_vector(1880,11);
logman <= conv_std_logic_vector(3099346,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011000" =>
inv <= conv_std_logic_vector(1873,11);
logman <= conv_std_logic_vector(3600026,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011001" =>
inv <= conv_std_logic_vector(1866,11);
logman <= conv_std_logic_vector(4102580,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011010" =>
inv <= conv_std_logic_vector(1860,11);
logman <= conv_std_logic_vector(4534844,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011011" =>
inv <= conv_std_logic_vector(1853,11);
logman <= conv_std_logic_vector(5040917,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011100" =>
inv <= conv_std_logic_vector(1847,11);
logman <= conv_std_logic_vector(5476218,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011101" =>
inv <= conv_std_logic_vector(1840,11);
logman <= conv_std_logic_vector(5985860,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011110" =>
inv <= conv_std_logic_vector(1834,11);
logman <= conv_std_logic_vector(6424242,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011111" =>
inv <= conv_std_logic_vector(1827,11);
logman <= conv_std_logic_vector(6937504,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100000" =>
inv <= conv_std_logic_vector(1821,11);
logman <= conv_std_logic_vector(7379010,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100001" =>
inv <= conv_std_logic_vector(1815,11);
logman <= conv_std_logic_vector(7821973,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100010" =>
inv <= conv_std_logic_vector(1808,11);
logman <= conv_std_logic_vector(8340618,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100011" =>
inv <= conv_std_logic_vector(1802,11);
logman <= conv_std_logic_vector(199082,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100100" =>
inv <= conv_std_logic_vector(1796,11);
logman <= conv_std_logic_vector(422902,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100101" =>
inv <= conv_std_logic_vector(1790,11);
logman <= conv_std_logic_vector(647472,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100110" =>
inv <= conv_std_logic_vector(1784,11);
logman <= conv_std_logic_vector(872796,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100111" =>
inv <= conv_std_logic_vector(1778,11);
logman <= conv_std_logic_vector(1098879,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101000" =>
inv <= conv_std_logic_vector(1772,11);
logman <= conv_std_logic_vector(1325726,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101001" =>
inv <= conv_std_logic_vector(1766,11);
logman <= conv_std_logic_vector(1553342,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101010" =>
inv <= conv_std_logic_vector(1760,11);
logman <= conv_std_logic_vector(1781734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101011" =>
inv <= conv_std_logic_vector(1754,11);
logman <= conv_std_logic_vector(2010905,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101100" =>
inv <= conv_std_logic_vector(1748,11);
logman <= conv_std_logic_vector(2240861,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101101" =>
inv <= conv_std_logic_vector(1742,11);
logman <= conv_std_logic_vector(2471608,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101110" =>
inv <= conv_std_logic_vector(1737,11);
logman <= conv_std_logic_vector(2664505,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101111" =>
inv <= conv_std_logic_vector(1731,11);
logman <= conv_std_logic_vector(2896716,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110000" =>
inv <= conv_std_logic_vector(1725,11);
logman <= conv_std_logic_vector(3129733,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110001" =>
inv <= conv_std_logic_vector(1719,11);
logman <= conv_std_logic_vector(3363562,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110010" =>
inv <= conv_std_logic_vector(1714,11);
logman <= conv_std_logic_vector(3559044,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110011" =>
inv <= conv_std_logic_vector(1708,11);
logman <= conv_std_logic_vector(3794376,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110100" =>
inv <= conv_std_logic_vector(1703,11);
logman <= conv_std_logic_vector(3991119,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110101" =>
inv <= conv_std_logic_vector(1697,11);
logman <= conv_std_logic_vector(4227974,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110110" =>
inv <= conv_std_logic_vector(1692,11);
logman <= conv_std_logic_vector(4425994,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110111" =>
inv <= conv_std_logic_vector(1686,11);
logman <= conv_std_logic_vector(4664391,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111000" =>
inv <= conv_std_logic_vector(1681,11);
logman <= conv_std_logic_vector(4863705,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111001" =>
inv <= conv_std_logic_vector(1676,11);
logman <= conv_std_logic_vector(5063612,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111010" =>
inv <= conv_std_logic_vector(1670,11);
logman <= conv_std_logic_vector(5304290,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111011" =>
inv <= conv_std_logic_vector(1665,11);
logman <= conv_std_logic_vector(5505516,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111100" =>
inv <= conv_std_logic_vector(1660,11);
logman <= conv_std_logic_vector(5707347,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111101" =>
inv <= conv_std_logic_vector(1654,11);
logman <= conv_std_logic_vector(5950349,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111110" =>
inv <= conv_std_logic_vector(1649,11);
logman <= conv_std_logic_vector(6153525,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111111" =>
inv <= conv_std_logic_vector(1644,11);
logman <= conv_std_logic_vector(6357317,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000000" =>
inv <= conv_std_logic_vector(1639,11);
logman <= conv_std_logic_vector(6561731,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000001" =>
inv <= conv_std_logic_vector(1634,11);
logman <= conv_std_logic_vector(6766769,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000010" =>
inv <= conv_std_logic_vector(1629,11);
logman <= conv_std_logic_vector(6972435,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000011" =>
inv <= conv_std_logic_vector(1624,11);
logman <= conv_std_logic_vector(7178734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000100" =>
inv <= conv_std_logic_vector(1619,11);
logman <= conv_std_logic_vector(7385668,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000101" =>
inv <= conv_std_logic_vector(1614,11);
logman <= conv_std_logic_vector(7593243,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000110" =>
inv <= conv_std_logic_vector(1609,11);
logman <= conv_std_logic_vector(7801462,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000111" =>
inv <= conv_std_logic_vector(1604,11);
logman <= conv_std_logic_vector(8010329,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001000" =>
inv <= conv_std_logic_vector(1599,11);
logman <= conv_std_logic_vector(8219848,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001001" =>
inv <= conv_std_logic_vector(1594,11);
logman <= conv_std_logic_vector(20707,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001010" =>
inv <= conv_std_logic_vector(1589,11);
logman <= conv_std_logic_vector(126125,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001011" =>
inv <= conv_std_logic_vector(1584,11);
logman <= conv_std_logic_vector(231875,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001100" =>
inv <= conv_std_logic_vector(1580,11);
logman <= conv_std_logic_vector(316716,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001101" =>
inv <= conv_std_logic_vector(1575,11);
logman <= conv_std_logic_vector(423069,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001110" =>
inv <= conv_std_logic_vector(1570,11);
logman <= conv_std_logic_vector(529760,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001111" =>
inv <= conv_std_logic_vector(1566,11);
logman <= conv_std_logic_vector(615358,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010000" =>
inv <= conv_std_logic_vector(1561,11);
logman <= conv_std_logic_vector(722664,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010001" =>
inv <= conv_std_logic_vector(1556,11);
logman <= conv_std_logic_vector(830314,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010010" =>
inv <= conv_std_logic_vector(1552,11);
logman <= conv_std_logic_vector(916683,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010011" =>
inv <= conv_std_logic_vector(1547,11);
logman <= conv_std_logic_vector(1024958,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010100" =>
inv <= conv_std_logic_vector(1543,11);
logman <= conv_std_logic_vector(1111831,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010101" =>
inv <= conv_std_logic_vector(1538,11);
logman <= conv_std_logic_vector(1220738,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010110" =>
inv <= conv_std_logic_vector(1534,11);
logman <= conv_std_logic_vector(1308120,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010111" =>
inv <= conv_std_logic_vector(1529,11);
logman <= conv_std_logic_vector(1417667,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011000" =>
inv <= conv_std_logic_vector(1525,11);
logman <= conv_std_logic_vector(1505564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011001" =>
inv <= conv_std_logic_vector(1520,11);
logman <= conv_std_logic_vector(1615759,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011010" =>
inv <= conv_std_logic_vector(1516,11);
logman <= conv_std_logic_vector(1704177,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011011" =>
inv <= conv_std_logic_vector(1511,11);
logman <= conv_std_logic_vector(1815027,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011100" =>
inv <= conv_std_logic_vector(1507,11);
logman <= conv_std_logic_vector(1903972,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011101" =>
inv <= conv_std_logic_vector(1503,11);
logman <= conv_std_logic_vector(1993153,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011110" =>
inv <= conv_std_logic_vector(1498,11);
logman <= conv_std_logic_vector(2104964,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011111" =>
inv <= conv_std_logic_vector(1494,11);
logman <= conv_std_logic_vector(2194682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100000" =>
inv <= conv_std_logic_vector(1490,11);
logman <= conv_std_logic_vector(2284640,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100001" =>
inv <= conv_std_logic_vector(1486,11);
logman <= conv_std_logic_vector(2374840,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100010" =>
inv <= conv_std_logic_vector(1482,11);
logman <= conv_std_logic_vector(2465284,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100011" =>
inv <= conv_std_logic_vector(1477,11);
logman <= conv_std_logic_vector(2578682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100100" =>
inv <= conv_std_logic_vector(1473,11);
logman <= conv_std_logic_vector(2669677,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100101" =>
inv <= conv_std_logic_vector(1469,11);
logman <= conv_std_logic_vector(2760919,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100110" =>
inv <= conv_std_logic_vector(1465,11);
logman <= conv_std_logic_vector(2852411,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100111" =>
inv <= conv_std_logic_vector(1461,11);
logman <= conv_std_logic_vector(2944152,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101000" =>
inv <= conv_std_logic_vector(1457,11);
logman <= conv_std_logic_vector(3036145,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101001" =>
inv <= conv_std_logic_vector(1453,11);
logman <= conv_std_logic_vector(3128391,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101010" =>
inv <= conv_std_logic_vector(1449,11);
logman <= conv_std_logic_vector(3220891,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101011" =>
inv <= conv_std_logic_vector(1445,11);
logman <= conv_std_logic_vector(3313647,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101100" =>
inv <= conv_std_logic_vector(1441,11);
logman <= conv_std_logic_vector(3406660,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101101" =>
inv <= conv_std_logic_vector(1437,11);
logman <= conv_std_logic_vector(3499932,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101110" =>
inv <= conv_std_logic_vector(1433,11);
logman <= conv_std_logic_vector(3593464,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101111" =>
inv <= conv_std_logic_vector(1429,11);
logman <= conv_std_logic_vector(3687257,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110000" =>
inv <= conv_std_logic_vector(1425,11);
logman <= conv_std_logic_vector(3781312,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110001" =>
inv <= conv_std_logic_vector(1421,11);
logman <= conv_std_logic_vector(3875633,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110010" =>
inv <= conv_std_logic_vector(1417,11);
logman <= conv_std_logic_vector(3970219,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110011" =>
inv <= conv_std_logic_vector(1414,11);
logman <= conv_std_logic_vector(4041334,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110100" =>
inv <= conv_std_logic_vector(1410,11);
logman <= conv_std_logic_vector(4136389,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110101" =>
inv <= conv_std_logic_vector(1406,11);
logman <= conv_std_logic_vector(4231714,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110110" =>
inv <= conv_std_logic_vector(1402,11);
logman <= conv_std_logic_vector(4327311,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110111" =>
inv <= conv_std_logic_vector(1399,11);
logman <= conv_std_logic_vector(4399188,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111000" =>
inv <= conv_std_logic_vector(1395,11);
logman <= conv_std_logic_vector(4495263,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111001" =>
inv <= conv_std_logic_vector(1391,11);
logman <= conv_std_logic_vector(4591615,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111010" =>
inv <= conv_std_logic_vector(1388,11);
logman <= conv_std_logic_vector(4664061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111011" =>
inv <= conv_std_logic_vector(1384,11);
logman <= conv_std_logic_vector(4760899,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111100" =>
inv <= conv_std_logic_vector(1380,11);
logman <= conv_std_logic_vector(4858018,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111101" =>
inv <= conv_std_logic_vector(1377,11);
logman <= conv_std_logic_vector(4931041,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111110" =>
inv <= conv_std_logic_vector(1373,11);
logman <= conv_std_logic_vector(5028654,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111111" =>
inv <= conv_std_logic_vector(1369,11);
logman <= conv_std_logic_vector(5126552,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000000" =>
inv <= conv_std_logic_vector(1366,11);
logman <= conv_std_logic_vector(5200163,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000001" =>
inv <= conv_std_logic_vector(1362,11);
logman <= conv_std_logic_vector(5298564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000010" =>
inv <= conv_std_logic_vector(1359,11);
logman <= conv_std_logic_vector(5372554,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000011" =>
inv <= conv_std_logic_vector(1355,11);
logman <= conv_std_logic_vector(5471461,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000100" =>
inv <= conv_std_logic_vector(1352,11);
logman <= conv_std_logic_vector(5545834,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000101" =>
inv <= conv_std_logic_vector(1348,11);
logman <= conv_std_logic_vector(5645255,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000110" =>
inv <= conv_std_logic_vector(1345,11);
logman <= conv_std_logic_vector(5720014,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000111" =>
inv <= conv_std_logic_vector(1341,11);
logman <= conv_std_logic_vector(5819953,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001000" =>
inv <= conv_std_logic_vector(1338,11);
logman <= conv_std_logic_vector(5895103,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001001" =>
inv <= conv_std_logic_vector(1335,11);
logman <= conv_std_logic_vector(5970421,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001010" =>
inv <= conv_std_logic_vector(1331,11);
logman <= conv_std_logic_vector(6071110,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001011" =>
inv <= conv_std_logic_vector(1328,11);
logman <= conv_std_logic_vector(6146825,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001100" =>
inv <= conv_std_logic_vector(1324,11);
logman <= conv_std_logic_vector(6248045,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001101" =>
inv <= conv_std_logic_vector(1321,11);
logman <= conv_std_logic_vector(6324161,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001110" =>
inv <= conv_std_logic_vector(1318,11);
logman <= conv_std_logic_vector(6400450,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001111" =>
inv <= conv_std_logic_vector(1315,11);
logman <= conv_std_logic_vector(6476913,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010000" =>
inv <= conv_std_logic_vector(1311,11);
logman <= conv_std_logic_vector(6579135,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010001" =>
inv <= conv_std_logic_vector(1308,11);
logman <= conv_std_logic_vector(6656007,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010010" =>
inv <= conv_std_logic_vector(1305,11);
logman <= conv_std_logic_vector(6733055,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010011" =>
inv <= conv_std_logic_vector(1301,11);
logman <= conv_std_logic_vector(6836061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010100" =>
inv <= conv_std_logic_vector(1298,11);
logman <= conv_std_logic_vector(6913525,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010101" =>
inv <= conv_std_logic_vector(1295,11);
logman <= conv_std_logic_vector(6991167,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010110" =>
inv <= conv_std_logic_vector(1292,11);
logman <= conv_std_logic_vector(7068989,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010111" =>
inv <= conv_std_logic_vector(1289,11);
logman <= conv_std_logic_vector(7146993,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011000" =>
inv <= conv_std_logic_vector(1286,11);
logman <= conv_std_logic_vector(7225178,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011001" =>
inv <= conv_std_logic_vector(1282,11);
logman <= conv_std_logic_vector(7329709,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011010" =>
inv <= conv_std_logic_vector(1279,11);
logman <= conv_std_logic_vector(7408321,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011011" =>
inv <= conv_std_logic_vector(1276,11);
logman <= conv_std_logic_vector(7487119,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011100" =>
inv <= conv_std_logic_vector(1273,11);
logman <= conv_std_logic_vector(7566101,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011101" =>
inv <= conv_std_logic_vector(1270,11);
logman <= conv_std_logic_vector(7645270,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011110" =>
inv <= conv_std_logic_vector(1267,11);
logman <= conv_std_logic_vector(7724626,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011111" =>
inv <= conv_std_logic_vector(1264,11);
logman <= conv_std_logic_vector(7804171,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100000" =>
inv <= conv_std_logic_vector(1261,11);
logman <= conv_std_logic_vector(7883904,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100001" =>
inv <= conv_std_logic_vector(1258,11);
logman <= conv_std_logic_vector(7963827,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100010" =>
inv <= conv_std_logic_vector(1255,11);
logman <= conv_std_logic_vector(8043941,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100011" =>
inv <= conv_std_logic_vector(1252,11);
logman <= conv_std_logic_vector(8124247,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100100" =>
inv <= conv_std_logic_vector(1249,11);
logman <= conv_std_logic_vector(8204746,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100101" =>
inv <= conv_std_logic_vector(1246,11);
logman <= conv_std_logic_vector(8285438,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100110" =>
inv <= conv_std_logic_vector(1243,11);
logman <= conv_std_logic_vector(8366324,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100111" =>
inv <= conv_std_logic_vector(1240,11);
logman <= conv_std_logic_vector(29399,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101000" =>
inv <= conv_std_logic_vector(1237,11);
logman <= conv_std_logic_vector(70038,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101001" =>
inv <= conv_std_logic_vector(1234,11);
logman <= conv_std_logic_vector(110776,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101010" =>
inv <= conv_std_logic_vector(1231,11);
logman <= conv_std_logic_vector(151613,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101011" =>
inv <= conv_std_logic_vector(1228,11);
logman <= conv_std_logic_vector(192550,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101100" =>
inv <= conv_std_logic_vector(1225,11);
logman <= conv_std_logic_vector(233587,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101101" =>
inv <= conv_std_logic_vector(1223,11);
logman <= conv_std_logic_vector(261001,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101110" =>
inv <= conv_std_logic_vector(1220,11);
logman <= conv_std_logic_vector(302205,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101111" =>
inv <= conv_std_logic_vector(1217,11);
logman <= conv_std_logic_vector(343512,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110000" =>
inv <= conv_std_logic_vector(1214,11);
logman <= conv_std_logic_vector(384920,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110001" =>
inv <= conv_std_logic_vector(1211,11);
logman <= conv_std_logic_vector(426431,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110010" =>
inv <= conv_std_logic_vector(1209,11);
logman <= conv_std_logic_vector(454162,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110011" =>
inv <= conv_std_logic_vector(1206,11);
logman <= conv_std_logic_vector(495844,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110100" =>
inv <= conv_std_logic_vector(1203,11);
logman <= conv_std_logic_vector(537630,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110101" =>
inv <= conv_std_logic_vector(1200,11);
logman <= conv_std_logic_vector(579521,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110110" =>
inv <= conv_std_logic_vector(1198,11);
logman <= conv_std_logic_vector(607506,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110111" =>
inv <= conv_std_logic_vector(1195,11);
logman <= conv_std_logic_vector(649572,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111000" =>
inv <= conv_std_logic_vector(1192,11);
logman <= conv_std_logic_vector(691744,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111001" =>
inv <= conv_std_logic_vector(1189,11);
logman <= conv_std_logic_vector(734021,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111010" =>
inv <= conv_std_logic_vector(1187,11);
logman <= conv_std_logic_vector(762266,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111011" =>
inv <= conv_std_logic_vector(1184,11);
logman <= conv_std_logic_vector(804722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111100" =>
inv <= conv_std_logic_vector(1181,11);
logman <= conv_std_logic_vector(847286,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111101" =>
inv <= conv_std_logic_vector(1179,11);
logman <= conv_std_logic_vector(875722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111110" =>
inv <= conv_std_logic_vector(1176,11);
logman <= conv_std_logic_vector(918466,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111111" =>
inv <= conv_std_logic_vector(1173,11);
logman <= conv_std_logic_vector(961320,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000000" =>
inv <= conv_std_logic_vector(1171,11);
logman <= conv_std_logic_vector(989950,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000001" =>
inv <= conv_std_logic_vector(1168,11);
logman <= conv_std_logic_vector(1032987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000010" =>
inv <= conv_std_logic_vector(1166,11);
logman <= conv_std_logic_vector(1061740,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000011" =>
inv <= conv_std_logic_vector(1163,11);
logman <= conv_std_logic_vector(1104961,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000100" =>
inv <= conv_std_logic_vector(1160,11);
logman <= conv_std_logic_vector(1148295,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000101" =>
inv <= conv_std_logic_vector(1158,11);
logman <= conv_std_logic_vector(1177246,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000110" =>
inv <= conv_std_logic_vector(1155,11);
logman <= conv_std_logic_vector(1220767,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000111" =>
inv <= conv_std_logic_vector(1153,11);
logman <= conv_std_logic_vector(1249843,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001000" =>
inv <= conv_std_logic_vector(1150,11);
logman <= conv_std_logic_vector(1293553,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001001" =>
inv <= conv_std_logic_vector(1148,11);
logman <= conv_std_logic_vector(1322756,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001010" =>
inv <= conv_std_logic_vector(1145,11);
logman <= conv_std_logic_vector(1366656,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001011" =>
inv <= conv_std_logic_vector(1143,11);
logman <= conv_std_logic_vector(1395987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001100" =>
inv <= conv_std_logic_vector(1140,11);
logman <= conv_std_logic_vector(1440080,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001101" =>
inv <= conv_std_logic_vector(1138,11);
logman <= conv_std_logic_vector(1469539,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001110" =>
inv <= conv_std_logic_vector(1135,11);
logman <= conv_std_logic_vector(1513826,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001111" =>
inv <= conv_std_logic_vector(1133,11);
logman <= conv_std_logic_vector(1543415,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010000" =>
inv <= conv_std_logic_vector(1130,11);
logman <= conv_std_logic_vector(1587898,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010001" =>
inv <= conv_std_logic_vector(1128,11);
logman <= conv_std_logic_vector(1617618,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010010" =>
inv <= conv_std_logic_vector(1126,11);
logman <= conv_std_logic_vector(1647391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010011" =>
inv <= conv_std_logic_vector(1123,11);
logman <= conv_std_logic_vector(1692151,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010100" =>
inv <= conv_std_logic_vector(1121,11);
logman <= conv_std_logic_vector(1722056,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010101" =>
inv <= conv_std_logic_vector(1118,11);
logman <= conv_std_logic_vector(1767016,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010110" =>
inv <= conv_std_logic_vector(1116,11);
logman <= conv_std_logic_vector(1797055,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010111" =>
inv <= conv_std_logic_vector(1114,11);
logman <= conv_std_logic_vector(1827149,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011000" =>
inv <= conv_std_logic_vector(1111,11);
logman <= conv_std_logic_vector(1872391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011001" =>
inv <= conv_std_logic_vector(1109,11);
logman <= conv_std_logic_vector(1902620,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011010" =>
inv <= conv_std_logic_vector(1107,11);
logman <= conv_std_logic_vector(1932904,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011011" =>
inv <= conv_std_logic_vector(1104,11);
logman <= conv_std_logic_vector(1978432,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011100" =>
inv <= conv_std_logic_vector(1102,11);
logman <= conv_std_logic_vector(2008853,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011101" =>
inv <= conv_std_logic_vector(1100,11);
logman <= conv_std_logic_vector(2039330,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011110" =>
inv <= conv_std_logic_vector(1097,11);
logman <= conv_std_logic_vector(2085148,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011111" =>
inv <= conv_std_logic_vector(1095,11);
logman <= conv_std_logic_vector(2115764,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100000" =>
inv <= conv_std_logic_vector(1093,11);
logman <= conv_std_logic_vector(2146435,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100001" =>
inv <= conv_std_logic_vector(1090,11);
logman <= conv_std_logic_vector(2192547,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100010" =>
inv <= conv_std_logic_vector(1088,11);
logman <= conv_std_logic_vector(2223360,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100011" =>
inv <= conv_std_logic_vector(1086,11);
logman <= conv_std_logic_vector(2254228,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100100" =>
inv <= conv_std_logic_vector(1084,11);
logman <= conv_std_logic_vector(2285154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100101" =>
inv <= conv_std_logic_vector(1082,11);
logman <= conv_std_logic_vector(2316137,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100110" =>
inv <= conv_std_logic_vector(1079,11);
logman <= conv_std_logic_vector(2362719,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100111" =>
inv <= conv_std_logic_vector(1077,11);
logman <= conv_std_logic_vector(2393845,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101000" =>
inv <= conv_std_logic_vector(1075,11);
logman <= conv_std_logic_vector(2425030,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101001" =>
inv <= conv_std_logic_vector(1073,11);
logman <= conv_std_logic_vector(2456272,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101010" =>
inv <= conv_std_logic_vector(1070,11);
logman <= conv_std_logic_vector(2503245,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101011" =>
inv <= conv_std_logic_vector(1068,11);
logman <= conv_std_logic_vector(2534634,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101100" =>
inv <= conv_std_logic_vector(1066,11);
logman <= conv_std_logic_vector(2566082,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101101" =>
inv <= conv_std_logic_vector(1064,11);
logman <= conv_std_logic_vector(2597588,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101110" =>
inv <= conv_std_logic_vector(1062,11);
logman <= conv_std_logic_vector(2629154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101111" =>
inv <= conv_std_logic_vector(1060,11);
logman <= conv_std_logic_vector(2660779,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110000" =>
inv <= conv_std_logic_vector(1058,11);
logman <= conv_std_logic_vector(2692464,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110001" =>
inv <= conv_std_logic_vector(1055,11);
logman <= conv_std_logic_vector(2740104,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110010" =>
inv <= conv_std_logic_vector(1053,11);
logman <= conv_std_logic_vector(2771940,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110011" =>
inv <= conv_std_logic_vector(1051,11);
logman <= conv_std_logic_vector(2803835,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110100" =>
inv <= conv_std_logic_vector(1049,11);
logman <= conv_std_logic_vector(2835792,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110101" =>
inv <= conv_std_logic_vector(1047,11);
logman <= conv_std_logic_vector(2867810,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110110" =>
inv <= conv_std_logic_vector(1045,11);
logman <= conv_std_logic_vector(2899888,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110111" =>
inv <= conv_std_logic_vector(1043,11);
logman <= conv_std_logic_vector(2932029,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111000" =>
inv <= conv_std_logic_vector(1041,11);
logman <= conv_std_logic_vector(2964231,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111001" =>
inv <= conv_std_logic_vector(1039,11);
logman <= conv_std_logic_vector(2996495,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111010" =>
inv <= conv_std_logic_vector(1037,11);
logman <= conv_std_logic_vector(3028821,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111011" =>
inv <= conv_std_logic_vector(1035,11);
logman <= conv_std_logic_vector(3061209,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111100" =>
inv <= conv_std_logic_vector(1033,11);
logman <= conv_std_logic_vector(3093660,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111101" =>
inv <= conv_std_logic_vector(1031,11);
logman <= conv_std_logic_vector(3126174,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111110" =>
inv <= conv_std_logic_vector(1029,11);
logman <= conv_std_logic_vector(3158751,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111111" =>
inv <= conv_std_logic_vector(1027,11);
logman <= conv_std_logic_vector(3191392,23);
logexp <= conv_std_logic_vector(126,8);
WHEN others =>
inv <= conv_std_logic_vector(0,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlut8 IS
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlut8;
ARCHITECTURE rtl OF fp_lnlut8 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "00000000" =>
inv <= conv_std_logic_vector(1024,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "00000001" =>
inv <= conv_std_logic_vector(2041,11);
logman <= conv_std_logic_vector(6316601,23);
logexp <= conv_std_logic_vector(118,8);
WHEN "00000010" =>
inv <= conv_std_logic_vector(2033,11);
logman <= conv_std_logic_vector(7397915,23);
logexp <= conv_std_logic_vector(119,8);
WHEN "00000011" =>
inv <= conv_std_logic_vector(2025,11);
logman <= conv_std_logic_vector(3738239,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000100" =>
inv <= conv_std_logic_vector(2017,11);
logman <= conv_std_logic_vector(7988584,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000101" =>
inv <= conv_std_logic_vector(2009,11);
logman <= conv_std_logic_vector(1933606,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000110" =>
inv <= conv_std_logic_vector(2002,11);
logman <= conv_std_logic_vector(3807503,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000111" =>
inv <= conv_std_logic_vector(1994,11);
logman <= conv_std_logic_vector(5957139,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001000" =>
inv <= conv_std_logic_vector(1986,11);
logman <= conv_std_logic_vector(8115417,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001001" =>
inv <= conv_std_logic_vector(1979,11);
logman <= conv_std_logic_vector(811223,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001010" =>
inv <= conv_std_logic_vector(1972,11);
logman <= conv_std_logic_vector(1762400,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001011" =>
inv <= conv_std_logic_vector(1964,11);
logman <= conv_std_logic_vector(2853602,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001100" =>
inv <= conv_std_logic_vector(1957,11);
logman <= conv_std_logic_vector(3812057,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001101" =>
inv <= conv_std_logic_vector(1950,11);
logman <= conv_std_logic_vector(4773946,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001110" =>
inv <= conv_std_logic_vector(1942,11);
logman <= conv_std_logic_vector(5877485,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001111" =>
inv <= conv_std_logic_vector(1935,11);
logman <= conv_std_logic_vector(6846817,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010000" =>
inv <= conv_std_logic_vector(1928,11);
logman <= conv_std_logic_vector(7819662,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010001" =>
inv <= conv_std_logic_vector(1921,11);
logman <= conv_std_logic_vector(203719,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010010" =>
inv <= conv_std_logic_vector(1914,11);
logman <= conv_std_logic_vector(693693,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010011" =>
inv <= conv_std_logic_vector(1907,11);
logman <= conv_std_logic_vector(1185462,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010100" =>
inv <= conv_std_logic_vector(1900,11);
logman <= conv_std_logic_vector(1679040,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010101" =>
inv <= conv_std_logic_vector(1893,11);
logman <= conv_std_logic_vector(2174439,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010110" =>
inv <= conv_std_logic_vector(1886,11);
logman <= conv_std_logic_vector(2671674,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010111" =>
inv <= conv_std_logic_vector(1880,11);
logman <= conv_std_logic_vector(3099346,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011000" =>
inv <= conv_std_logic_vector(1873,11);
logman <= conv_std_logic_vector(3600026,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011001" =>
inv <= conv_std_logic_vector(1866,11);
logman <= conv_std_logic_vector(4102580,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011010" =>
inv <= conv_std_logic_vector(1860,11);
logman <= conv_std_logic_vector(4534844,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011011" =>
inv <= conv_std_logic_vector(1853,11);
logman <= conv_std_logic_vector(5040917,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011100" =>
inv <= conv_std_logic_vector(1847,11);
logman <= conv_std_logic_vector(5476218,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011101" =>
inv <= conv_std_logic_vector(1840,11);
logman <= conv_std_logic_vector(5985860,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011110" =>
inv <= conv_std_logic_vector(1834,11);
logman <= conv_std_logic_vector(6424242,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011111" =>
inv <= conv_std_logic_vector(1827,11);
logman <= conv_std_logic_vector(6937504,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100000" =>
inv <= conv_std_logic_vector(1821,11);
logman <= conv_std_logic_vector(7379010,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100001" =>
inv <= conv_std_logic_vector(1815,11);
logman <= conv_std_logic_vector(7821973,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100010" =>
inv <= conv_std_logic_vector(1808,11);
logman <= conv_std_logic_vector(8340618,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100011" =>
inv <= conv_std_logic_vector(1802,11);
logman <= conv_std_logic_vector(199082,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100100" =>
inv <= conv_std_logic_vector(1796,11);
logman <= conv_std_logic_vector(422902,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100101" =>
inv <= conv_std_logic_vector(1790,11);
logman <= conv_std_logic_vector(647472,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100110" =>
inv <= conv_std_logic_vector(1784,11);
logman <= conv_std_logic_vector(872796,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100111" =>
inv <= conv_std_logic_vector(1778,11);
logman <= conv_std_logic_vector(1098879,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101000" =>
inv <= conv_std_logic_vector(1772,11);
logman <= conv_std_logic_vector(1325726,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101001" =>
inv <= conv_std_logic_vector(1766,11);
logman <= conv_std_logic_vector(1553342,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101010" =>
inv <= conv_std_logic_vector(1760,11);
logman <= conv_std_logic_vector(1781734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101011" =>
inv <= conv_std_logic_vector(1754,11);
logman <= conv_std_logic_vector(2010905,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101100" =>
inv <= conv_std_logic_vector(1748,11);
logman <= conv_std_logic_vector(2240861,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101101" =>
inv <= conv_std_logic_vector(1742,11);
logman <= conv_std_logic_vector(2471608,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101110" =>
inv <= conv_std_logic_vector(1737,11);
logman <= conv_std_logic_vector(2664505,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101111" =>
inv <= conv_std_logic_vector(1731,11);
logman <= conv_std_logic_vector(2896716,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110000" =>
inv <= conv_std_logic_vector(1725,11);
logman <= conv_std_logic_vector(3129733,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110001" =>
inv <= conv_std_logic_vector(1719,11);
logman <= conv_std_logic_vector(3363562,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110010" =>
inv <= conv_std_logic_vector(1714,11);
logman <= conv_std_logic_vector(3559044,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110011" =>
inv <= conv_std_logic_vector(1708,11);
logman <= conv_std_logic_vector(3794376,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110100" =>
inv <= conv_std_logic_vector(1703,11);
logman <= conv_std_logic_vector(3991119,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110101" =>
inv <= conv_std_logic_vector(1697,11);
logman <= conv_std_logic_vector(4227974,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110110" =>
inv <= conv_std_logic_vector(1692,11);
logman <= conv_std_logic_vector(4425994,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110111" =>
inv <= conv_std_logic_vector(1686,11);
logman <= conv_std_logic_vector(4664391,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111000" =>
inv <= conv_std_logic_vector(1681,11);
logman <= conv_std_logic_vector(4863705,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111001" =>
inv <= conv_std_logic_vector(1676,11);
logman <= conv_std_logic_vector(5063612,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111010" =>
inv <= conv_std_logic_vector(1670,11);
logman <= conv_std_logic_vector(5304290,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111011" =>
inv <= conv_std_logic_vector(1665,11);
logman <= conv_std_logic_vector(5505516,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111100" =>
inv <= conv_std_logic_vector(1660,11);
logman <= conv_std_logic_vector(5707347,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111101" =>
inv <= conv_std_logic_vector(1654,11);
logman <= conv_std_logic_vector(5950349,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111110" =>
inv <= conv_std_logic_vector(1649,11);
logman <= conv_std_logic_vector(6153525,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111111" =>
inv <= conv_std_logic_vector(1644,11);
logman <= conv_std_logic_vector(6357317,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000000" =>
inv <= conv_std_logic_vector(1639,11);
logman <= conv_std_logic_vector(6561731,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000001" =>
inv <= conv_std_logic_vector(1634,11);
logman <= conv_std_logic_vector(6766769,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000010" =>
inv <= conv_std_logic_vector(1629,11);
logman <= conv_std_logic_vector(6972435,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000011" =>
inv <= conv_std_logic_vector(1624,11);
logman <= conv_std_logic_vector(7178734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000100" =>
inv <= conv_std_logic_vector(1619,11);
logman <= conv_std_logic_vector(7385668,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000101" =>
inv <= conv_std_logic_vector(1614,11);
logman <= conv_std_logic_vector(7593243,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000110" =>
inv <= conv_std_logic_vector(1609,11);
logman <= conv_std_logic_vector(7801462,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000111" =>
inv <= conv_std_logic_vector(1604,11);
logman <= conv_std_logic_vector(8010329,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001000" =>
inv <= conv_std_logic_vector(1599,11);
logman <= conv_std_logic_vector(8219848,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001001" =>
inv <= conv_std_logic_vector(1594,11);
logman <= conv_std_logic_vector(20707,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001010" =>
inv <= conv_std_logic_vector(1589,11);
logman <= conv_std_logic_vector(126125,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001011" =>
inv <= conv_std_logic_vector(1584,11);
logman <= conv_std_logic_vector(231875,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001100" =>
inv <= conv_std_logic_vector(1580,11);
logman <= conv_std_logic_vector(316716,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001101" =>
inv <= conv_std_logic_vector(1575,11);
logman <= conv_std_logic_vector(423069,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001110" =>
inv <= conv_std_logic_vector(1570,11);
logman <= conv_std_logic_vector(529760,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001111" =>
inv <= conv_std_logic_vector(1566,11);
logman <= conv_std_logic_vector(615358,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010000" =>
inv <= conv_std_logic_vector(1561,11);
logman <= conv_std_logic_vector(722664,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010001" =>
inv <= conv_std_logic_vector(1556,11);
logman <= conv_std_logic_vector(830314,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010010" =>
inv <= conv_std_logic_vector(1552,11);
logman <= conv_std_logic_vector(916683,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010011" =>
inv <= conv_std_logic_vector(1547,11);
logman <= conv_std_logic_vector(1024958,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010100" =>
inv <= conv_std_logic_vector(1543,11);
logman <= conv_std_logic_vector(1111831,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010101" =>
inv <= conv_std_logic_vector(1538,11);
logman <= conv_std_logic_vector(1220738,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010110" =>
inv <= conv_std_logic_vector(1534,11);
logman <= conv_std_logic_vector(1308120,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010111" =>
inv <= conv_std_logic_vector(1529,11);
logman <= conv_std_logic_vector(1417667,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011000" =>
inv <= conv_std_logic_vector(1525,11);
logman <= conv_std_logic_vector(1505564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011001" =>
inv <= conv_std_logic_vector(1520,11);
logman <= conv_std_logic_vector(1615759,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011010" =>
inv <= conv_std_logic_vector(1516,11);
logman <= conv_std_logic_vector(1704177,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011011" =>
inv <= conv_std_logic_vector(1511,11);
logman <= conv_std_logic_vector(1815027,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011100" =>
inv <= conv_std_logic_vector(1507,11);
logman <= conv_std_logic_vector(1903972,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011101" =>
inv <= conv_std_logic_vector(1503,11);
logman <= conv_std_logic_vector(1993153,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011110" =>
inv <= conv_std_logic_vector(1498,11);
logman <= conv_std_logic_vector(2104964,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011111" =>
inv <= conv_std_logic_vector(1494,11);
logman <= conv_std_logic_vector(2194682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100000" =>
inv <= conv_std_logic_vector(1490,11);
logman <= conv_std_logic_vector(2284640,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100001" =>
inv <= conv_std_logic_vector(1486,11);
logman <= conv_std_logic_vector(2374840,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100010" =>
inv <= conv_std_logic_vector(1482,11);
logman <= conv_std_logic_vector(2465284,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100011" =>
inv <= conv_std_logic_vector(1477,11);
logman <= conv_std_logic_vector(2578682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100100" =>
inv <= conv_std_logic_vector(1473,11);
logman <= conv_std_logic_vector(2669677,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100101" =>
inv <= conv_std_logic_vector(1469,11);
logman <= conv_std_logic_vector(2760919,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100110" =>
inv <= conv_std_logic_vector(1465,11);
logman <= conv_std_logic_vector(2852411,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100111" =>
inv <= conv_std_logic_vector(1461,11);
logman <= conv_std_logic_vector(2944152,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101000" =>
inv <= conv_std_logic_vector(1457,11);
logman <= conv_std_logic_vector(3036145,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101001" =>
inv <= conv_std_logic_vector(1453,11);
logman <= conv_std_logic_vector(3128391,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101010" =>
inv <= conv_std_logic_vector(1449,11);
logman <= conv_std_logic_vector(3220891,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101011" =>
inv <= conv_std_logic_vector(1445,11);
logman <= conv_std_logic_vector(3313647,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101100" =>
inv <= conv_std_logic_vector(1441,11);
logman <= conv_std_logic_vector(3406660,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101101" =>
inv <= conv_std_logic_vector(1437,11);
logman <= conv_std_logic_vector(3499932,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101110" =>
inv <= conv_std_logic_vector(1433,11);
logman <= conv_std_logic_vector(3593464,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101111" =>
inv <= conv_std_logic_vector(1429,11);
logman <= conv_std_logic_vector(3687257,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110000" =>
inv <= conv_std_logic_vector(1425,11);
logman <= conv_std_logic_vector(3781312,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110001" =>
inv <= conv_std_logic_vector(1421,11);
logman <= conv_std_logic_vector(3875633,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110010" =>
inv <= conv_std_logic_vector(1417,11);
logman <= conv_std_logic_vector(3970219,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110011" =>
inv <= conv_std_logic_vector(1414,11);
logman <= conv_std_logic_vector(4041334,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110100" =>
inv <= conv_std_logic_vector(1410,11);
logman <= conv_std_logic_vector(4136389,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110101" =>
inv <= conv_std_logic_vector(1406,11);
logman <= conv_std_logic_vector(4231714,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110110" =>
inv <= conv_std_logic_vector(1402,11);
logman <= conv_std_logic_vector(4327311,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110111" =>
inv <= conv_std_logic_vector(1399,11);
logman <= conv_std_logic_vector(4399188,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111000" =>
inv <= conv_std_logic_vector(1395,11);
logman <= conv_std_logic_vector(4495263,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111001" =>
inv <= conv_std_logic_vector(1391,11);
logman <= conv_std_logic_vector(4591615,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111010" =>
inv <= conv_std_logic_vector(1388,11);
logman <= conv_std_logic_vector(4664061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111011" =>
inv <= conv_std_logic_vector(1384,11);
logman <= conv_std_logic_vector(4760899,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111100" =>
inv <= conv_std_logic_vector(1380,11);
logman <= conv_std_logic_vector(4858018,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111101" =>
inv <= conv_std_logic_vector(1377,11);
logman <= conv_std_logic_vector(4931041,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111110" =>
inv <= conv_std_logic_vector(1373,11);
logman <= conv_std_logic_vector(5028654,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111111" =>
inv <= conv_std_logic_vector(1369,11);
logman <= conv_std_logic_vector(5126552,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000000" =>
inv <= conv_std_logic_vector(1366,11);
logman <= conv_std_logic_vector(5200163,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000001" =>
inv <= conv_std_logic_vector(1362,11);
logman <= conv_std_logic_vector(5298564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000010" =>
inv <= conv_std_logic_vector(1359,11);
logman <= conv_std_logic_vector(5372554,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000011" =>
inv <= conv_std_logic_vector(1355,11);
logman <= conv_std_logic_vector(5471461,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000100" =>
inv <= conv_std_logic_vector(1352,11);
logman <= conv_std_logic_vector(5545834,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000101" =>
inv <= conv_std_logic_vector(1348,11);
logman <= conv_std_logic_vector(5645255,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000110" =>
inv <= conv_std_logic_vector(1345,11);
logman <= conv_std_logic_vector(5720014,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000111" =>
inv <= conv_std_logic_vector(1341,11);
logman <= conv_std_logic_vector(5819953,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001000" =>
inv <= conv_std_logic_vector(1338,11);
logman <= conv_std_logic_vector(5895103,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001001" =>
inv <= conv_std_logic_vector(1335,11);
logman <= conv_std_logic_vector(5970421,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001010" =>
inv <= conv_std_logic_vector(1331,11);
logman <= conv_std_logic_vector(6071110,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001011" =>
inv <= conv_std_logic_vector(1328,11);
logman <= conv_std_logic_vector(6146825,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001100" =>
inv <= conv_std_logic_vector(1324,11);
logman <= conv_std_logic_vector(6248045,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001101" =>
inv <= conv_std_logic_vector(1321,11);
logman <= conv_std_logic_vector(6324161,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001110" =>
inv <= conv_std_logic_vector(1318,11);
logman <= conv_std_logic_vector(6400450,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001111" =>
inv <= conv_std_logic_vector(1315,11);
logman <= conv_std_logic_vector(6476913,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010000" =>
inv <= conv_std_logic_vector(1311,11);
logman <= conv_std_logic_vector(6579135,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010001" =>
inv <= conv_std_logic_vector(1308,11);
logman <= conv_std_logic_vector(6656007,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010010" =>
inv <= conv_std_logic_vector(1305,11);
logman <= conv_std_logic_vector(6733055,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010011" =>
inv <= conv_std_logic_vector(1301,11);
logman <= conv_std_logic_vector(6836061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010100" =>
inv <= conv_std_logic_vector(1298,11);
logman <= conv_std_logic_vector(6913525,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010101" =>
inv <= conv_std_logic_vector(1295,11);
logman <= conv_std_logic_vector(6991167,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010110" =>
inv <= conv_std_logic_vector(1292,11);
logman <= conv_std_logic_vector(7068989,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010111" =>
inv <= conv_std_logic_vector(1289,11);
logman <= conv_std_logic_vector(7146993,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011000" =>
inv <= conv_std_logic_vector(1286,11);
logman <= conv_std_logic_vector(7225178,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011001" =>
inv <= conv_std_logic_vector(1282,11);
logman <= conv_std_logic_vector(7329709,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011010" =>
inv <= conv_std_logic_vector(1279,11);
logman <= conv_std_logic_vector(7408321,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011011" =>
inv <= conv_std_logic_vector(1276,11);
logman <= conv_std_logic_vector(7487119,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011100" =>
inv <= conv_std_logic_vector(1273,11);
logman <= conv_std_logic_vector(7566101,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011101" =>
inv <= conv_std_logic_vector(1270,11);
logman <= conv_std_logic_vector(7645270,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011110" =>
inv <= conv_std_logic_vector(1267,11);
logman <= conv_std_logic_vector(7724626,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011111" =>
inv <= conv_std_logic_vector(1264,11);
logman <= conv_std_logic_vector(7804171,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100000" =>
inv <= conv_std_logic_vector(1261,11);
logman <= conv_std_logic_vector(7883904,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100001" =>
inv <= conv_std_logic_vector(1258,11);
logman <= conv_std_logic_vector(7963827,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100010" =>
inv <= conv_std_logic_vector(1255,11);
logman <= conv_std_logic_vector(8043941,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100011" =>
inv <= conv_std_logic_vector(1252,11);
logman <= conv_std_logic_vector(8124247,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100100" =>
inv <= conv_std_logic_vector(1249,11);
logman <= conv_std_logic_vector(8204746,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100101" =>
inv <= conv_std_logic_vector(1246,11);
logman <= conv_std_logic_vector(8285438,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100110" =>
inv <= conv_std_logic_vector(1243,11);
logman <= conv_std_logic_vector(8366324,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100111" =>
inv <= conv_std_logic_vector(1240,11);
logman <= conv_std_logic_vector(29399,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101000" =>
inv <= conv_std_logic_vector(1237,11);
logman <= conv_std_logic_vector(70038,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101001" =>
inv <= conv_std_logic_vector(1234,11);
logman <= conv_std_logic_vector(110776,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101010" =>
inv <= conv_std_logic_vector(1231,11);
logman <= conv_std_logic_vector(151613,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101011" =>
inv <= conv_std_logic_vector(1228,11);
logman <= conv_std_logic_vector(192550,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101100" =>
inv <= conv_std_logic_vector(1225,11);
logman <= conv_std_logic_vector(233587,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101101" =>
inv <= conv_std_logic_vector(1223,11);
logman <= conv_std_logic_vector(261001,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101110" =>
inv <= conv_std_logic_vector(1220,11);
logman <= conv_std_logic_vector(302205,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101111" =>
inv <= conv_std_logic_vector(1217,11);
logman <= conv_std_logic_vector(343512,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110000" =>
inv <= conv_std_logic_vector(1214,11);
logman <= conv_std_logic_vector(384920,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110001" =>
inv <= conv_std_logic_vector(1211,11);
logman <= conv_std_logic_vector(426431,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110010" =>
inv <= conv_std_logic_vector(1209,11);
logman <= conv_std_logic_vector(454162,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110011" =>
inv <= conv_std_logic_vector(1206,11);
logman <= conv_std_logic_vector(495844,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110100" =>
inv <= conv_std_logic_vector(1203,11);
logman <= conv_std_logic_vector(537630,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110101" =>
inv <= conv_std_logic_vector(1200,11);
logman <= conv_std_logic_vector(579521,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110110" =>
inv <= conv_std_logic_vector(1198,11);
logman <= conv_std_logic_vector(607506,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110111" =>
inv <= conv_std_logic_vector(1195,11);
logman <= conv_std_logic_vector(649572,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111000" =>
inv <= conv_std_logic_vector(1192,11);
logman <= conv_std_logic_vector(691744,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111001" =>
inv <= conv_std_logic_vector(1189,11);
logman <= conv_std_logic_vector(734021,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111010" =>
inv <= conv_std_logic_vector(1187,11);
logman <= conv_std_logic_vector(762266,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111011" =>
inv <= conv_std_logic_vector(1184,11);
logman <= conv_std_logic_vector(804722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111100" =>
inv <= conv_std_logic_vector(1181,11);
logman <= conv_std_logic_vector(847286,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111101" =>
inv <= conv_std_logic_vector(1179,11);
logman <= conv_std_logic_vector(875722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111110" =>
inv <= conv_std_logic_vector(1176,11);
logman <= conv_std_logic_vector(918466,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111111" =>
inv <= conv_std_logic_vector(1173,11);
logman <= conv_std_logic_vector(961320,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000000" =>
inv <= conv_std_logic_vector(1171,11);
logman <= conv_std_logic_vector(989950,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000001" =>
inv <= conv_std_logic_vector(1168,11);
logman <= conv_std_logic_vector(1032987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000010" =>
inv <= conv_std_logic_vector(1166,11);
logman <= conv_std_logic_vector(1061740,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000011" =>
inv <= conv_std_logic_vector(1163,11);
logman <= conv_std_logic_vector(1104961,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000100" =>
inv <= conv_std_logic_vector(1160,11);
logman <= conv_std_logic_vector(1148295,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000101" =>
inv <= conv_std_logic_vector(1158,11);
logman <= conv_std_logic_vector(1177246,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000110" =>
inv <= conv_std_logic_vector(1155,11);
logman <= conv_std_logic_vector(1220767,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000111" =>
inv <= conv_std_logic_vector(1153,11);
logman <= conv_std_logic_vector(1249843,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001000" =>
inv <= conv_std_logic_vector(1150,11);
logman <= conv_std_logic_vector(1293553,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001001" =>
inv <= conv_std_logic_vector(1148,11);
logman <= conv_std_logic_vector(1322756,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001010" =>
inv <= conv_std_logic_vector(1145,11);
logman <= conv_std_logic_vector(1366656,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001011" =>
inv <= conv_std_logic_vector(1143,11);
logman <= conv_std_logic_vector(1395987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001100" =>
inv <= conv_std_logic_vector(1140,11);
logman <= conv_std_logic_vector(1440080,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001101" =>
inv <= conv_std_logic_vector(1138,11);
logman <= conv_std_logic_vector(1469539,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001110" =>
inv <= conv_std_logic_vector(1135,11);
logman <= conv_std_logic_vector(1513826,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001111" =>
inv <= conv_std_logic_vector(1133,11);
logman <= conv_std_logic_vector(1543415,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010000" =>
inv <= conv_std_logic_vector(1130,11);
logman <= conv_std_logic_vector(1587898,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010001" =>
inv <= conv_std_logic_vector(1128,11);
logman <= conv_std_logic_vector(1617618,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010010" =>
inv <= conv_std_logic_vector(1126,11);
logman <= conv_std_logic_vector(1647391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010011" =>
inv <= conv_std_logic_vector(1123,11);
logman <= conv_std_logic_vector(1692151,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010100" =>
inv <= conv_std_logic_vector(1121,11);
logman <= conv_std_logic_vector(1722056,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010101" =>
inv <= conv_std_logic_vector(1118,11);
logman <= conv_std_logic_vector(1767016,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010110" =>
inv <= conv_std_logic_vector(1116,11);
logman <= conv_std_logic_vector(1797055,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010111" =>
inv <= conv_std_logic_vector(1114,11);
logman <= conv_std_logic_vector(1827149,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011000" =>
inv <= conv_std_logic_vector(1111,11);
logman <= conv_std_logic_vector(1872391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011001" =>
inv <= conv_std_logic_vector(1109,11);
logman <= conv_std_logic_vector(1902620,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011010" =>
inv <= conv_std_logic_vector(1107,11);
logman <= conv_std_logic_vector(1932904,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011011" =>
inv <= conv_std_logic_vector(1104,11);
logman <= conv_std_logic_vector(1978432,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011100" =>
inv <= conv_std_logic_vector(1102,11);
logman <= conv_std_logic_vector(2008853,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011101" =>
inv <= conv_std_logic_vector(1100,11);
logman <= conv_std_logic_vector(2039330,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011110" =>
inv <= conv_std_logic_vector(1097,11);
logman <= conv_std_logic_vector(2085148,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011111" =>
inv <= conv_std_logic_vector(1095,11);
logman <= conv_std_logic_vector(2115764,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100000" =>
inv <= conv_std_logic_vector(1093,11);
logman <= conv_std_logic_vector(2146435,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100001" =>
inv <= conv_std_logic_vector(1090,11);
logman <= conv_std_logic_vector(2192547,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100010" =>
inv <= conv_std_logic_vector(1088,11);
logman <= conv_std_logic_vector(2223360,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100011" =>
inv <= conv_std_logic_vector(1086,11);
logman <= conv_std_logic_vector(2254228,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100100" =>
inv <= conv_std_logic_vector(1084,11);
logman <= conv_std_logic_vector(2285154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100101" =>
inv <= conv_std_logic_vector(1082,11);
logman <= conv_std_logic_vector(2316137,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100110" =>
inv <= conv_std_logic_vector(1079,11);
logman <= conv_std_logic_vector(2362719,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100111" =>
inv <= conv_std_logic_vector(1077,11);
logman <= conv_std_logic_vector(2393845,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101000" =>
inv <= conv_std_logic_vector(1075,11);
logman <= conv_std_logic_vector(2425030,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101001" =>
inv <= conv_std_logic_vector(1073,11);
logman <= conv_std_logic_vector(2456272,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101010" =>
inv <= conv_std_logic_vector(1070,11);
logman <= conv_std_logic_vector(2503245,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101011" =>
inv <= conv_std_logic_vector(1068,11);
logman <= conv_std_logic_vector(2534634,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101100" =>
inv <= conv_std_logic_vector(1066,11);
logman <= conv_std_logic_vector(2566082,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101101" =>
inv <= conv_std_logic_vector(1064,11);
logman <= conv_std_logic_vector(2597588,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101110" =>
inv <= conv_std_logic_vector(1062,11);
logman <= conv_std_logic_vector(2629154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101111" =>
inv <= conv_std_logic_vector(1060,11);
logman <= conv_std_logic_vector(2660779,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110000" =>
inv <= conv_std_logic_vector(1058,11);
logman <= conv_std_logic_vector(2692464,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110001" =>
inv <= conv_std_logic_vector(1055,11);
logman <= conv_std_logic_vector(2740104,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110010" =>
inv <= conv_std_logic_vector(1053,11);
logman <= conv_std_logic_vector(2771940,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110011" =>
inv <= conv_std_logic_vector(1051,11);
logman <= conv_std_logic_vector(2803835,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110100" =>
inv <= conv_std_logic_vector(1049,11);
logman <= conv_std_logic_vector(2835792,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110101" =>
inv <= conv_std_logic_vector(1047,11);
logman <= conv_std_logic_vector(2867810,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110110" =>
inv <= conv_std_logic_vector(1045,11);
logman <= conv_std_logic_vector(2899888,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110111" =>
inv <= conv_std_logic_vector(1043,11);
logman <= conv_std_logic_vector(2932029,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111000" =>
inv <= conv_std_logic_vector(1041,11);
logman <= conv_std_logic_vector(2964231,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111001" =>
inv <= conv_std_logic_vector(1039,11);
logman <= conv_std_logic_vector(2996495,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111010" =>
inv <= conv_std_logic_vector(1037,11);
logman <= conv_std_logic_vector(3028821,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111011" =>
inv <= conv_std_logic_vector(1035,11);
logman <= conv_std_logic_vector(3061209,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111100" =>
inv <= conv_std_logic_vector(1033,11);
logman <= conv_std_logic_vector(3093660,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111101" =>
inv <= conv_std_logic_vector(1031,11);
logman <= conv_std_logic_vector(3126174,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111110" =>
inv <= conv_std_logic_vector(1029,11);
logman <= conv_std_logic_vector(3158751,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111111" =>
inv <= conv_std_logic_vector(1027,11);
logman <= conv_std_logic_vector(3191392,23);
logexp <= conv_std_logic_vector(126,8);
WHEN others =>
inv <= conv_std_logic_vector(0,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlut8 IS
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlut8;
ARCHITECTURE rtl OF fp_lnlut8 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "00000000" =>
inv <= conv_std_logic_vector(1024,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "00000001" =>
inv <= conv_std_logic_vector(2041,11);
logman <= conv_std_logic_vector(6316601,23);
logexp <= conv_std_logic_vector(118,8);
WHEN "00000010" =>
inv <= conv_std_logic_vector(2033,11);
logman <= conv_std_logic_vector(7397915,23);
logexp <= conv_std_logic_vector(119,8);
WHEN "00000011" =>
inv <= conv_std_logic_vector(2025,11);
logman <= conv_std_logic_vector(3738239,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000100" =>
inv <= conv_std_logic_vector(2017,11);
logman <= conv_std_logic_vector(7988584,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000101" =>
inv <= conv_std_logic_vector(2009,11);
logman <= conv_std_logic_vector(1933606,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000110" =>
inv <= conv_std_logic_vector(2002,11);
logman <= conv_std_logic_vector(3807503,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000111" =>
inv <= conv_std_logic_vector(1994,11);
logman <= conv_std_logic_vector(5957139,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001000" =>
inv <= conv_std_logic_vector(1986,11);
logman <= conv_std_logic_vector(8115417,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001001" =>
inv <= conv_std_logic_vector(1979,11);
logman <= conv_std_logic_vector(811223,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001010" =>
inv <= conv_std_logic_vector(1972,11);
logman <= conv_std_logic_vector(1762400,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001011" =>
inv <= conv_std_logic_vector(1964,11);
logman <= conv_std_logic_vector(2853602,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001100" =>
inv <= conv_std_logic_vector(1957,11);
logman <= conv_std_logic_vector(3812057,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001101" =>
inv <= conv_std_logic_vector(1950,11);
logman <= conv_std_logic_vector(4773946,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001110" =>
inv <= conv_std_logic_vector(1942,11);
logman <= conv_std_logic_vector(5877485,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001111" =>
inv <= conv_std_logic_vector(1935,11);
logman <= conv_std_logic_vector(6846817,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010000" =>
inv <= conv_std_logic_vector(1928,11);
logman <= conv_std_logic_vector(7819662,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010001" =>
inv <= conv_std_logic_vector(1921,11);
logman <= conv_std_logic_vector(203719,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010010" =>
inv <= conv_std_logic_vector(1914,11);
logman <= conv_std_logic_vector(693693,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010011" =>
inv <= conv_std_logic_vector(1907,11);
logman <= conv_std_logic_vector(1185462,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010100" =>
inv <= conv_std_logic_vector(1900,11);
logman <= conv_std_logic_vector(1679040,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010101" =>
inv <= conv_std_logic_vector(1893,11);
logman <= conv_std_logic_vector(2174439,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010110" =>
inv <= conv_std_logic_vector(1886,11);
logman <= conv_std_logic_vector(2671674,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010111" =>
inv <= conv_std_logic_vector(1880,11);
logman <= conv_std_logic_vector(3099346,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011000" =>
inv <= conv_std_logic_vector(1873,11);
logman <= conv_std_logic_vector(3600026,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011001" =>
inv <= conv_std_logic_vector(1866,11);
logman <= conv_std_logic_vector(4102580,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011010" =>
inv <= conv_std_logic_vector(1860,11);
logman <= conv_std_logic_vector(4534844,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011011" =>
inv <= conv_std_logic_vector(1853,11);
logman <= conv_std_logic_vector(5040917,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011100" =>
inv <= conv_std_logic_vector(1847,11);
logman <= conv_std_logic_vector(5476218,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011101" =>
inv <= conv_std_logic_vector(1840,11);
logman <= conv_std_logic_vector(5985860,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011110" =>
inv <= conv_std_logic_vector(1834,11);
logman <= conv_std_logic_vector(6424242,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011111" =>
inv <= conv_std_logic_vector(1827,11);
logman <= conv_std_logic_vector(6937504,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100000" =>
inv <= conv_std_logic_vector(1821,11);
logman <= conv_std_logic_vector(7379010,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100001" =>
inv <= conv_std_logic_vector(1815,11);
logman <= conv_std_logic_vector(7821973,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100010" =>
inv <= conv_std_logic_vector(1808,11);
logman <= conv_std_logic_vector(8340618,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100011" =>
inv <= conv_std_logic_vector(1802,11);
logman <= conv_std_logic_vector(199082,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100100" =>
inv <= conv_std_logic_vector(1796,11);
logman <= conv_std_logic_vector(422902,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100101" =>
inv <= conv_std_logic_vector(1790,11);
logman <= conv_std_logic_vector(647472,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100110" =>
inv <= conv_std_logic_vector(1784,11);
logman <= conv_std_logic_vector(872796,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100111" =>
inv <= conv_std_logic_vector(1778,11);
logman <= conv_std_logic_vector(1098879,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101000" =>
inv <= conv_std_logic_vector(1772,11);
logman <= conv_std_logic_vector(1325726,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101001" =>
inv <= conv_std_logic_vector(1766,11);
logman <= conv_std_logic_vector(1553342,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101010" =>
inv <= conv_std_logic_vector(1760,11);
logman <= conv_std_logic_vector(1781734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101011" =>
inv <= conv_std_logic_vector(1754,11);
logman <= conv_std_logic_vector(2010905,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101100" =>
inv <= conv_std_logic_vector(1748,11);
logman <= conv_std_logic_vector(2240861,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101101" =>
inv <= conv_std_logic_vector(1742,11);
logman <= conv_std_logic_vector(2471608,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101110" =>
inv <= conv_std_logic_vector(1737,11);
logman <= conv_std_logic_vector(2664505,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101111" =>
inv <= conv_std_logic_vector(1731,11);
logman <= conv_std_logic_vector(2896716,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110000" =>
inv <= conv_std_logic_vector(1725,11);
logman <= conv_std_logic_vector(3129733,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110001" =>
inv <= conv_std_logic_vector(1719,11);
logman <= conv_std_logic_vector(3363562,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110010" =>
inv <= conv_std_logic_vector(1714,11);
logman <= conv_std_logic_vector(3559044,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110011" =>
inv <= conv_std_logic_vector(1708,11);
logman <= conv_std_logic_vector(3794376,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110100" =>
inv <= conv_std_logic_vector(1703,11);
logman <= conv_std_logic_vector(3991119,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110101" =>
inv <= conv_std_logic_vector(1697,11);
logman <= conv_std_logic_vector(4227974,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110110" =>
inv <= conv_std_logic_vector(1692,11);
logman <= conv_std_logic_vector(4425994,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110111" =>
inv <= conv_std_logic_vector(1686,11);
logman <= conv_std_logic_vector(4664391,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111000" =>
inv <= conv_std_logic_vector(1681,11);
logman <= conv_std_logic_vector(4863705,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111001" =>
inv <= conv_std_logic_vector(1676,11);
logman <= conv_std_logic_vector(5063612,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111010" =>
inv <= conv_std_logic_vector(1670,11);
logman <= conv_std_logic_vector(5304290,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111011" =>
inv <= conv_std_logic_vector(1665,11);
logman <= conv_std_logic_vector(5505516,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111100" =>
inv <= conv_std_logic_vector(1660,11);
logman <= conv_std_logic_vector(5707347,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111101" =>
inv <= conv_std_logic_vector(1654,11);
logman <= conv_std_logic_vector(5950349,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111110" =>
inv <= conv_std_logic_vector(1649,11);
logman <= conv_std_logic_vector(6153525,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111111" =>
inv <= conv_std_logic_vector(1644,11);
logman <= conv_std_logic_vector(6357317,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000000" =>
inv <= conv_std_logic_vector(1639,11);
logman <= conv_std_logic_vector(6561731,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000001" =>
inv <= conv_std_logic_vector(1634,11);
logman <= conv_std_logic_vector(6766769,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000010" =>
inv <= conv_std_logic_vector(1629,11);
logman <= conv_std_logic_vector(6972435,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000011" =>
inv <= conv_std_logic_vector(1624,11);
logman <= conv_std_logic_vector(7178734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000100" =>
inv <= conv_std_logic_vector(1619,11);
logman <= conv_std_logic_vector(7385668,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000101" =>
inv <= conv_std_logic_vector(1614,11);
logman <= conv_std_logic_vector(7593243,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000110" =>
inv <= conv_std_logic_vector(1609,11);
logman <= conv_std_logic_vector(7801462,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000111" =>
inv <= conv_std_logic_vector(1604,11);
logman <= conv_std_logic_vector(8010329,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001000" =>
inv <= conv_std_logic_vector(1599,11);
logman <= conv_std_logic_vector(8219848,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001001" =>
inv <= conv_std_logic_vector(1594,11);
logman <= conv_std_logic_vector(20707,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001010" =>
inv <= conv_std_logic_vector(1589,11);
logman <= conv_std_logic_vector(126125,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001011" =>
inv <= conv_std_logic_vector(1584,11);
logman <= conv_std_logic_vector(231875,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001100" =>
inv <= conv_std_logic_vector(1580,11);
logman <= conv_std_logic_vector(316716,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001101" =>
inv <= conv_std_logic_vector(1575,11);
logman <= conv_std_logic_vector(423069,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001110" =>
inv <= conv_std_logic_vector(1570,11);
logman <= conv_std_logic_vector(529760,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001111" =>
inv <= conv_std_logic_vector(1566,11);
logman <= conv_std_logic_vector(615358,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010000" =>
inv <= conv_std_logic_vector(1561,11);
logman <= conv_std_logic_vector(722664,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010001" =>
inv <= conv_std_logic_vector(1556,11);
logman <= conv_std_logic_vector(830314,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010010" =>
inv <= conv_std_logic_vector(1552,11);
logman <= conv_std_logic_vector(916683,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010011" =>
inv <= conv_std_logic_vector(1547,11);
logman <= conv_std_logic_vector(1024958,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010100" =>
inv <= conv_std_logic_vector(1543,11);
logman <= conv_std_logic_vector(1111831,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010101" =>
inv <= conv_std_logic_vector(1538,11);
logman <= conv_std_logic_vector(1220738,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010110" =>
inv <= conv_std_logic_vector(1534,11);
logman <= conv_std_logic_vector(1308120,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010111" =>
inv <= conv_std_logic_vector(1529,11);
logman <= conv_std_logic_vector(1417667,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011000" =>
inv <= conv_std_logic_vector(1525,11);
logman <= conv_std_logic_vector(1505564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011001" =>
inv <= conv_std_logic_vector(1520,11);
logman <= conv_std_logic_vector(1615759,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011010" =>
inv <= conv_std_logic_vector(1516,11);
logman <= conv_std_logic_vector(1704177,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011011" =>
inv <= conv_std_logic_vector(1511,11);
logman <= conv_std_logic_vector(1815027,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011100" =>
inv <= conv_std_logic_vector(1507,11);
logman <= conv_std_logic_vector(1903972,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011101" =>
inv <= conv_std_logic_vector(1503,11);
logman <= conv_std_logic_vector(1993153,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011110" =>
inv <= conv_std_logic_vector(1498,11);
logman <= conv_std_logic_vector(2104964,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011111" =>
inv <= conv_std_logic_vector(1494,11);
logman <= conv_std_logic_vector(2194682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100000" =>
inv <= conv_std_logic_vector(1490,11);
logman <= conv_std_logic_vector(2284640,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100001" =>
inv <= conv_std_logic_vector(1486,11);
logman <= conv_std_logic_vector(2374840,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100010" =>
inv <= conv_std_logic_vector(1482,11);
logman <= conv_std_logic_vector(2465284,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100011" =>
inv <= conv_std_logic_vector(1477,11);
logman <= conv_std_logic_vector(2578682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100100" =>
inv <= conv_std_logic_vector(1473,11);
logman <= conv_std_logic_vector(2669677,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100101" =>
inv <= conv_std_logic_vector(1469,11);
logman <= conv_std_logic_vector(2760919,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100110" =>
inv <= conv_std_logic_vector(1465,11);
logman <= conv_std_logic_vector(2852411,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100111" =>
inv <= conv_std_logic_vector(1461,11);
logman <= conv_std_logic_vector(2944152,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101000" =>
inv <= conv_std_logic_vector(1457,11);
logman <= conv_std_logic_vector(3036145,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101001" =>
inv <= conv_std_logic_vector(1453,11);
logman <= conv_std_logic_vector(3128391,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101010" =>
inv <= conv_std_logic_vector(1449,11);
logman <= conv_std_logic_vector(3220891,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101011" =>
inv <= conv_std_logic_vector(1445,11);
logman <= conv_std_logic_vector(3313647,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101100" =>
inv <= conv_std_logic_vector(1441,11);
logman <= conv_std_logic_vector(3406660,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101101" =>
inv <= conv_std_logic_vector(1437,11);
logman <= conv_std_logic_vector(3499932,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101110" =>
inv <= conv_std_logic_vector(1433,11);
logman <= conv_std_logic_vector(3593464,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101111" =>
inv <= conv_std_logic_vector(1429,11);
logman <= conv_std_logic_vector(3687257,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110000" =>
inv <= conv_std_logic_vector(1425,11);
logman <= conv_std_logic_vector(3781312,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110001" =>
inv <= conv_std_logic_vector(1421,11);
logman <= conv_std_logic_vector(3875633,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110010" =>
inv <= conv_std_logic_vector(1417,11);
logman <= conv_std_logic_vector(3970219,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110011" =>
inv <= conv_std_logic_vector(1414,11);
logman <= conv_std_logic_vector(4041334,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110100" =>
inv <= conv_std_logic_vector(1410,11);
logman <= conv_std_logic_vector(4136389,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110101" =>
inv <= conv_std_logic_vector(1406,11);
logman <= conv_std_logic_vector(4231714,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110110" =>
inv <= conv_std_logic_vector(1402,11);
logman <= conv_std_logic_vector(4327311,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110111" =>
inv <= conv_std_logic_vector(1399,11);
logman <= conv_std_logic_vector(4399188,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111000" =>
inv <= conv_std_logic_vector(1395,11);
logman <= conv_std_logic_vector(4495263,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111001" =>
inv <= conv_std_logic_vector(1391,11);
logman <= conv_std_logic_vector(4591615,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111010" =>
inv <= conv_std_logic_vector(1388,11);
logman <= conv_std_logic_vector(4664061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111011" =>
inv <= conv_std_logic_vector(1384,11);
logman <= conv_std_logic_vector(4760899,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111100" =>
inv <= conv_std_logic_vector(1380,11);
logman <= conv_std_logic_vector(4858018,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111101" =>
inv <= conv_std_logic_vector(1377,11);
logman <= conv_std_logic_vector(4931041,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111110" =>
inv <= conv_std_logic_vector(1373,11);
logman <= conv_std_logic_vector(5028654,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111111" =>
inv <= conv_std_logic_vector(1369,11);
logman <= conv_std_logic_vector(5126552,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000000" =>
inv <= conv_std_logic_vector(1366,11);
logman <= conv_std_logic_vector(5200163,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000001" =>
inv <= conv_std_logic_vector(1362,11);
logman <= conv_std_logic_vector(5298564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000010" =>
inv <= conv_std_logic_vector(1359,11);
logman <= conv_std_logic_vector(5372554,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000011" =>
inv <= conv_std_logic_vector(1355,11);
logman <= conv_std_logic_vector(5471461,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000100" =>
inv <= conv_std_logic_vector(1352,11);
logman <= conv_std_logic_vector(5545834,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000101" =>
inv <= conv_std_logic_vector(1348,11);
logman <= conv_std_logic_vector(5645255,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000110" =>
inv <= conv_std_logic_vector(1345,11);
logman <= conv_std_logic_vector(5720014,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000111" =>
inv <= conv_std_logic_vector(1341,11);
logman <= conv_std_logic_vector(5819953,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001000" =>
inv <= conv_std_logic_vector(1338,11);
logman <= conv_std_logic_vector(5895103,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001001" =>
inv <= conv_std_logic_vector(1335,11);
logman <= conv_std_logic_vector(5970421,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001010" =>
inv <= conv_std_logic_vector(1331,11);
logman <= conv_std_logic_vector(6071110,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001011" =>
inv <= conv_std_logic_vector(1328,11);
logman <= conv_std_logic_vector(6146825,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001100" =>
inv <= conv_std_logic_vector(1324,11);
logman <= conv_std_logic_vector(6248045,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001101" =>
inv <= conv_std_logic_vector(1321,11);
logman <= conv_std_logic_vector(6324161,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001110" =>
inv <= conv_std_logic_vector(1318,11);
logman <= conv_std_logic_vector(6400450,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001111" =>
inv <= conv_std_logic_vector(1315,11);
logman <= conv_std_logic_vector(6476913,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010000" =>
inv <= conv_std_logic_vector(1311,11);
logman <= conv_std_logic_vector(6579135,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010001" =>
inv <= conv_std_logic_vector(1308,11);
logman <= conv_std_logic_vector(6656007,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010010" =>
inv <= conv_std_logic_vector(1305,11);
logman <= conv_std_logic_vector(6733055,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010011" =>
inv <= conv_std_logic_vector(1301,11);
logman <= conv_std_logic_vector(6836061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010100" =>
inv <= conv_std_logic_vector(1298,11);
logman <= conv_std_logic_vector(6913525,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010101" =>
inv <= conv_std_logic_vector(1295,11);
logman <= conv_std_logic_vector(6991167,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010110" =>
inv <= conv_std_logic_vector(1292,11);
logman <= conv_std_logic_vector(7068989,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010111" =>
inv <= conv_std_logic_vector(1289,11);
logman <= conv_std_logic_vector(7146993,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011000" =>
inv <= conv_std_logic_vector(1286,11);
logman <= conv_std_logic_vector(7225178,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011001" =>
inv <= conv_std_logic_vector(1282,11);
logman <= conv_std_logic_vector(7329709,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011010" =>
inv <= conv_std_logic_vector(1279,11);
logman <= conv_std_logic_vector(7408321,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011011" =>
inv <= conv_std_logic_vector(1276,11);
logman <= conv_std_logic_vector(7487119,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011100" =>
inv <= conv_std_logic_vector(1273,11);
logman <= conv_std_logic_vector(7566101,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011101" =>
inv <= conv_std_logic_vector(1270,11);
logman <= conv_std_logic_vector(7645270,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011110" =>
inv <= conv_std_logic_vector(1267,11);
logman <= conv_std_logic_vector(7724626,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011111" =>
inv <= conv_std_logic_vector(1264,11);
logman <= conv_std_logic_vector(7804171,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100000" =>
inv <= conv_std_logic_vector(1261,11);
logman <= conv_std_logic_vector(7883904,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100001" =>
inv <= conv_std_logic_vector(1258,11);
logman <= conv_std_logic_vector(7963827,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100010" =>
inv <= conv_std_logic_vector(1255,11);
logman <= conv_std_logic_vector(8043941,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100011" =>
inv <= conv_std_logic_vector(1252,11);
logman <= conv_std_logic_vector(8124247,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100100" =>
inv <= conv_std_logic_vector(1249,11);
logman <= conv_std_logic_vector(8204746,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100101" =>
inv <= conv_std_logic_vector(1246,11);
logman <= conv_std_logic_vector(8285438,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100110" =>
inv <= conv_std_logic_vector(1243,11);
logman <= conv_std_logic_vector(8366324,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100111" =>
inv <= conv_std_logic_vector(1240,11);
logman <= conv_std_logic_vector(29399,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101000" =>
inv <= conv_std_logic_vector(1237,11);
logman <= conv_std_logic_vector(70038,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101001" =>
inv <= conv_std_logic_vector(1234,11);
logman <= conv_std_logic_vector(110776,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101010" =>
inv <= conv_std_logic_vector(1231,11);
logman <= conv_std_logic_vector(151613,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101011" =>
inv <= conv_std_logic_vector(1228,11);
logman <= conv_std_logic_vector(192550,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101100" =>
inv <= conv_std_logic_vector(1225,11);
logman <= conv_std_logic_vector(233587,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101101" =>
inv <= conv_std_logic_vector(1223,11);
logman <= conv_std_logic_vector(261001,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101110" =>
inv <= conv_std_logic_vector(1220,11);
logman <= conv_std_logic_vector(302205,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101111" =>
inv <= conv_std_logic_vector(1217,11);
logman <= conv_std_logic_vector(343512,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110000" =>
inv <= conv_std_logic_vector(1214,11);
logman <= conv_std_logic_vector(384920,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110001" =>
inv <= conv_std_logic_vector(1211,11);
logman <= conv_std_logic_vector(426431,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110010" =>
inv <= conv_std_logic_vector(1209,11);
logman <= conv_std_logic_vector(454162,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110011" =>
inv <= conv_std_logic_vector(1206,11);
logman <= conv_std_logic_vector(495844,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110100" =>
inv <= conv_std_logic_vector(1203,11);
logman <= conv_std_logic_vector(537630,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110101" =>
inv <= conv_std_logic_vector(1200,11);
logman <= conv_std_logic_vector(579521,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110110" =>
inv <= conv_std_logic_vector(1198,11);
logman <= conv_std_logic_vector(607506,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110111" =>
inv <= conv_std_logic_vector(1195,11);
logman <= conv_std_logic_vector(649572,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111000" =>
inv <= conv_std_logic_vector(1192,11);
logman <= conv_std_logic_vector(691744,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111001" =>
inv <= conv_std_logic_vector(1189,11);
logman <= conv_std_logic_vector(734021,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111010" =>
inv <= conv_std_logic_vector(1187,11);
logman <= conv_std_logic_vector(762266,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111011" =>
inv <= conv_std_logic_vector(1184,11);
logman <= conv_std_logic_vector(804722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111100" =>
inv <= conv_std_logic_vector(1181,11);
logman <= conv_std_logic_vector(847286,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111101" =>
inv <= conv_std_logic_vector(1179,11);
logman <= conv_std_logic_vector(875722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111110" =>
inv <= conv_std_logic_vector(1176,11);
logman <= conv_std_logic_vector(918466,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111111" =>
inv <= conv_std_logic_vector(1173,11);
logman <= conv_std_logic_vector(961320,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000000" =>
inv <= conv_std_logic_vector(1171,11);
logman <= conv_std_logic_vector(989950,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000001" =>
inv <= conv_std_logic_vector(1168,11);
logman <= conv_std_logic_vector(1032987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000010" =>
inv <= conv_std_logic_vector(1166,11);
logman <= conv_std_logic_vector(1061740,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000011" =>
inv <= conv_std_logic_vector(1163,11);
logman <= conv_std_logic_vector(1104961,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000100" =>
inv <= conv_std_logic_vector(1160,11);
logman <= conv_std_logic_vector(1148295,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000101" =>
inv <= conv_std_logic_vector(1158,11);
logman <= conv_std_logic_vector(1177246,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000110" =>
inv <= conv_std_logic_vector(1155,11);
logman <= conv_std_logic_vector(1220767,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000111" =>
inv <= conv_std_logic_vector(1153,11);
logman <= conv_std_logic_vector(1249843,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001000" =>
inv <= conv_std_logic_vector(1150,11);
logman <= conv_std_logic_vector(1293553,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001001" =>
inv <= conv_std_logic_vector(1148,11);
logman <= conv_std_logic_vector(1322756,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001010" =>
inv <= conv_std_logic_vector(1145,11);
logman <= conv_std_logic_vector(1366656,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001011" =>
inv <= conv_std_logic_vector(1143,11);
logman <= conv_std_logic_vector(1395987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001100" =>
inv <= conv_std_logic_vector(1140,11);
logman <= conv_std_logic_vector(1440080,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001101" =>
inv <= conv_std_logic_vector(1138,11);
logman <= conv_std_logic_vector(1469539,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001110" =>
inv <= conv_std_logic_vector(1135,11);
logman <= conv_std_logic_vector(1513826,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001111" =>
inv <= conv_std_logic_vector(1133,11);
logman <= conv_std_logic_vector(1543415,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010000" =>
inv <= conv_std_logic_vector(1130,11);
logman <= conv_std_logic_vector(1587898,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010001" =>
inv <= conv_std_logic_vector(1128,11);
logman <= conv_std_logic_vector(1617618,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010010" =>
inv <= conv_std_logic_vector(1126,11);
logman <= conv_std_logic_vector(1647391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010011" =>
inv <= conv_std_logic_vector(1123,11);
logman <= conv_std_logic_vector(1692151,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010100" =>
inv <= conv_std_logic_vector(1121,11);
logman <= conv_std_logic_vector(1722056,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010101" =>
inv <= conv_std_logic_vector(1118,11);
logman <= conv_std_logic_vector(1767016,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010110" =>
inv <= conv_std_logic_vector(1116,11);
logman <= conv_std_logic_vector(1797055,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010111" =>
inv <= conv_std_logic_vector(1114,11);
logman <= conv_std_logic_vector(1827149,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011000" =>
inv <= conv_std_logic_vector(1111,11);
logman <= conv_std_logic_vector(1872391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011001" =>
inv <= conv_std_logic_vector(1109,11);
logman <= conv_std_logic_vector(1902620,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011010" =>
inv <= conv_std_logic_vector(1107,11);
logman <= conv_std_logic_vector(1932904,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011011" =>
inv <= conv_std_logic_vector(1104,11);
logman <= conv_std_logic_vector(1978432,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011100" =>
inv <= conv_std_logic_vector(1102,11);
logman <= conv_std_logic_vector(2008853,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011101" =>
inv <= conv_std_logic_vector(1100,11);
logman <= conv_std_logic_vector(2039330,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011110" =>
inv <= conv_std_logic_vector(1097,11);
logman <= conv_std_logic_vector(2085148,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011111" =>
inv <= conv_std_logic_vector(1095,11);
logman <= conv_std_logic_vector(2115764,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100000" =>
inv <= conv_std_logic_vector(1093,11);
logman <= conv_std_logic_vector(2146435,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100001" =>
inv <= conv_std_logic_vector(1090,11);
logman <= conv_std_logic_vector(2192547,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100010" =>
inv <= conv_std_logic_vector(1088,11);
logman <= conv_std_logic_vector(2223360,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100011" =>
inv <= conv_std_logic_vector(1086,11);
logman <= conv_std_logic_vector(2254228,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100100" =>
inv <= conv_std_logic_vector(1084,11);
logman <= conv_std_logic_vector(2285154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100101" =>
inv <= conv_std_logic_vector(1082,11);
logman <= conv_std_logic_vector(2316137,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100110" =>
inv <= conv_std_logic_vector(1079,11);
logman <= conv_std_logic_vector(2362719,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100111" =>
inv <= conv_std_logic_vector(1077,11);
logman <= conv_std_logic_vector(2393845,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101000" =>
inv <= conv_std_logic_vector(1075,11);
logman <= conv_std_logic_vector(2425030,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101001" =>
inv <= conv_std_logic_vector(1073,11);
logman <= conv_std_logic_vector(2456272,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101010" =>
inv <= conv_std_logic_vector(1070,11);
logman <= conv_std_logic_vector(2503245,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101011" =>
inv <= conv_std_logic_vector(1068,11);
logman <= conv_std_logic_vector(2534634,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101100" =>
inv <= conv_std_logic_vector(1066,11);
logman <= conv_std_logic_vector(2566082,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101101" =>
inv <= conv_std_logic_vector(1064,11);
logman <= conv_std_logic_vector(2597588,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101110" =>
inv <= conv_std_logic_vector(1062,11);
logman <= conv_std_logic_vector(2629154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101111" =>
inv <= conv_std_logic_vector(1060,11);
logman <= conv_std_logic_vector(2660779,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110000" =>
inv <= conv_std_logic_vector(1058,11);
logman <= conv_std_logic_vector(2692464,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110001" =>
inv <= conv_std_logic_vector(1055,11);
logman <= conv_std_logic_vector(2740104,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110010" =>
inv <= conv_std_logic_vector(1053,11);
logman <= conv_std_logic_vector(2771940,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110011" =>
inv <= conv_std_logic_vector(1051,11);
logman <= conv_std_logic_vector(2803835,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110100" =>
inv <= conv_std_logic_vector(1049,11);
logman <= conv_std_logic_vector(2835792,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110101" =>
inv <= conv_std_logic_vector(1047,11);
logman <= conv_std_logic_vector(2867810,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110110" =>
inv <= conv_std_logic_vector(1045,11);
logman <= conv_std_logic_vector(2899888,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110111" =>
inv <= conv_std_logic_vector(1043,11);
logman <= conv_std_logic_vector(2932029,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111000" =>
inv <= conv_std_logic_vector(1041,11);
logman <= conv_std_logic_vector(2964231,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111001" =>
inv <= conv_std_logic_vector(1039,11);
logman <= conv_std_logic_vector(2996495,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111010" =>
inv <= conv_std_logic_vector(1037,11);
logman <= conv_std_logic_vector(3028821,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111011" =>
inv <= conv_std_logic_vector(1035,11);
logman <= conv_std_logic_vector(3061209,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111100" =>
inv <= conv_std_logic_vector(1033,11);
logman <= conv_std_logic_vector(3093660,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111101" =>
inv <= conv_std_logic_vector(1031,11);
logman <= conv_std_logic_vector(3126174,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111110" =>
inv <= conv_std_logic_vector(1029,11);
logman <= conv_std_logic_vector(3158751,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111111" =>
inv <= conv_std_logic_vector(1027,11);
logman <= conv_std_logic_vector(3191392,23);
logexp <= conv_std_logic_vector(126,8);
WHEN others =>
inv <= conv_std_logic_vector(0,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlut8 IS
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlut8;
ARCHITECTURE rtl OF fp_lnlut8 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "00000000" =>
inv <= conv_std_logic_vector(1024,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "00000001" =>
inv <= conv_std_logic_vector(2041,11);
logman <= conv_std_logic_vector(6316601,23);
logexp <= conv_std_logic_vector(118,8);
WHEN "00000010" =>
inv <= conv_std_logic_vector(2033,11);
logman <= conv_std_logic_vector(7397915,23);
logexp <= conv_std_logic_vector(119,8);
WHEN "00000011" =>
inv <= conv_std_logic_vector(2025,11);
logman <= conv_std_logic_vector(3738239,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000100" =>
inv <= conv_std_logic_vector(2017,11);
logman <= conv_std_logic_vector(7988584,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000101" =>
inv <= conv_std_logic_vector(2009,11);
logman <= conv_std_logic_vector(1933606,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000110" =>
inv <= conv_std_logic_vector(2002,11);
logman <= conv_std_logic_vector(3807503,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000111" =>
inv <= conv_std_logic_vector(1994,11);
logman <= conv_std_logic_vector(5957139,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001000" =>
inv <= conv_std_logic_vector(1986,11);
logman <= conv_std_logic_vector(8115417,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001001" =>
inv <= conv_std_logic_vector(1979,11);
logman <= conv_std_logic_vector(811223,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001010" =>
inv <= conv_std_logic_vector(1972,11);
logman <= conv_std_logic_vector(1762400,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001011" =>
inv <= conv_std_logic_vector(1964,11);
logman <= conv_std_logic_vector(2853602,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001100" =>
inv <= conv_std_logic_vector(1957,11);
logman <= conv_std_logic_vector(3812057,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001101" =>
inv <= conv_std_logic_vector(1950,11);
logman <= conv_std_logic_vector(4773946,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001110" =>
inv <= conv_std_logic_vector(1942,11);
logman <= conv_std_logic_vector(5877485,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001111" =>
inv <= conv_std_logic_vector(1935,11);
logman <= conv_std_logic_vector(6846817,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010000" =>
inv <= conv_std_logic_vector(1928,11);
logman <= conv_std_logic_vector(7819662,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010001" =>
inv <= conv_std_logic_vector(1921,11);
logman <= conv_std_logic_vector(203719,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010010" =>
inv <= conv_std_logic_vector(1914,11);
logman <= conv_std_logic_vector(693693,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010011" =>
inv <= conv_std_logic_vector(1907,11);
logman <= conv_std_logic_vector(1185462,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010100" =>
inv <= conv_std_logic_vector(1900,11);
logman <= conv_std_logic_vector(1679040,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010101" =>
inv <= conv_std_logic_vector(1893,11);
logman <= conv_std_logic_vector(2174439,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010110" =>
inv <= conv_std_logic_vector(1886,11);
logman <= conv_std_logic_vector(2671674,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010111" =>
inv <= conv_std_logic_vector(1880,11);
logman <= conv_std_logic_vector(3099346,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011000" =>
inv <= conv_std_logic_vector(1873,11);
logman <= conv_std_logic_vector(3600026,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011001" =>
inv <= conv_std_logic_vector(1866,11);
logman <= conv_std_logic_vector(4102580,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011010" =>
inv <= conv_std_logic_vector(1860,11);
logman <= conv_std_logic_vector(4534844,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011011" =>
inv <= conv_std_logic_vector(1853,11);
logman <= conv_std_logic_vector(5040917,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011100" =>
inv <= conv_std_logic_vector(1847,11);
logman <= conv_std_logic_vector(5476218,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011101" =>
inv <= conv_std_logic_vector(1840,11);
logman <= conv_std_logic_vector(5985860,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011110" =>
inv <= conv_std_logic_vector(1834,11);
logman <= conv_std_logic_vector(6424242,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011111" =>
inv <= conv_std_logic_vector(1827,11);
logman <= conv_std_logic_vector(6937504,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100000" =>
inv <= conv_std_logic_vector(1821,11);
logman <= conv_std_logic_vector(7379010,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100001" =>
inv <= conv_std_logic_vector(1815,11);
logman <= conv_std_logic_vector(7821973,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100010" =>
inv <= conv_std_logic_vector(1808,11);
logman <= conv_std_logic_vector(8340618,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100011" =>
inv <= conv_std_logic_vector(1802,11);
logman <= conv_std_logic_vector(199082,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100100" =>
inv <= conv_std_logic_vector(1796,11);
logman <= conv_std_logic_vector(422902,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100101" =>
inv <= conv_std_logic_vector(1790,11);
logman <= conv_std_logic_vector(647472,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100110" =>
inv <= conv_std_logic_vector(1784,11);
logman <= conv_std_logic_vector(872796,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100111" =>
inv <= conv_std_logic_vector(1778,11);
logman <= conv_std_logic_vector(1098879,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101000" =>
inv <= conv_std_logic_vector(1772,11);
logman <= conv_std_logic_vector(1325726,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101001" =>
inv <= conv_std_logic_vector(1766,11);
logman <= conv_std_logic_vector(1553342,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101010" =>
inv <= conv_std_logic_vector(1760,11);
logman <= conv_std_logic_vector(1781734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101011" =>
inv <= conv_std_logic_vector(1754,11);
logman <= conv_std_logic_vector(2010905,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101100" =>
inv <= conv_std_logic_vector(1748,11);
logman <= conv_std_logic_vector(2240861,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101101" =>
inv <= conv_std_logic_vector(1742,11);
logman <= conv_std_logic_vector(2471608,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101110" =>
inv <= conv_std_logic_vector(1737,11);
logman <= conv_std_logic_vector(2664505,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101111" =>
inv <= conv_std_logic_vector(1731,11);
logman <= conv_std_logic_vector(2896716,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110000" =>
inv <= conv_std_logic_vector(1725,11);
logman <= conv_std_logic_vector(3129733,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110001" =>
inv <= conv_std_logic_vector(1719,11);
logman <= conv_std_logic_vector(3363562,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110010" =>
inv <= conv_std_logic_vector(1714,11);
logman <= conv_std_logic_vector(3559044,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110011" =>
inv <= conv_std_logic_vector(1708,11);
logman <= conv_std_logic_vector(3794376,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110100" =>
inv <= conv_std_logic_vector(1703,11);
logman <= conv_std_logic_vector(3991119,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110101" =>
inv <= conv_std_logic_vector(1697,11);
logman <= conv_std_logic_vector(4227974,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110110" =>
inv <= conv_std_logic_vector(1692,11);
logman <= conv_std_logic_vector(4425994,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110111" =>
inv <= conv_std_logic_vector(1686,11);
logman <= conv_std_logic_vector(4664391,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111000" =>
inv <= conv_std_logic_vector(1681,11);
logman <= conv_std_logic_vector(4863705,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111001" =>
inv <= conv_std_logic_vector(1676,11);
logman <= conv_std_logic_vector(5063612,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111010" =>
inv <= conv_std_logic_vector(1670,11);
logman <= conv_std_logic_vector(5304290,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111011" =>
inv <= conv_std_logic_vector(1665,11);
logman <= conv_std_logic_vector(5505516,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111100" =>
inv <= conv_std_logic_vector(1660,11);
logman <= conv_std_logic_vector(5707347,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111101" =>
inv <= conv_std_logic_vector(1654,11);
logman <= conv_std_logic_vector(5950349,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111110" =>
inv <= conv_std_logic_vector(1649,11);
logman <= conv_std_logic_vector(6153525,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111111" =>
inv <= conv_std_logic_vector(1644,11);
logman <= conv_std_logic_vector(6357317,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000000" =>
inv <= conv_std_logic_vector(1639,11);
logman <= conv_std_logic_vector(6561731,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000001" =>
inv <= conv_std_logic_vector(1634,11);
logman <= conv_std_logic_vector(6766769,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000010" =>
inv <= conv_std_logic_vector(1629,11);
logman <= conv_std_logic_vector(6972435,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000011" =>
inv <= conv_std_logic_vector(1624,11);
logman <= conv_std_logic_vector(7178734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000100" =>
inv <= conv_std_logic_vector(1619,11);
logman <= conv_std_logic_vector(7385668,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000101" =>
inv <= conv_std_logic_vector(1614,11);
logman <= conv_std_logic_vector(7593243,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000110" =>
inv <= conv_std_logic_vector(1609,11);
logman <= conv_std_logic_vector(7801462,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000111" =>
inv <= conv_std_logic_vector(1604,11);
logman <= conv_std_logic_vector(8010329,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001000" =>
inv <= conv_std_logic_vector(1599,11);
logman <= conv_std_logic_vector(8219848,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001001" =>
inv <= conv_std_logic_vector(1594,11);
logman <= conv_std_logic_vector(20707,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001010" =>
inv <= conv_std_logic_vector(1589,11);
logman <= conv_std_logic_vector(126125,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001011" =>
inv <= conv_std_logic_vector(1584,11);
logman <= conv_std_logic_vector(231875,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001100" =>
inv <= conv_std_logic_vector(1580,11);
logman <= conv_std_logic_vector(316716,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001101" =>
inv <= conv_std_logic_vector(1575,11);
logman <= conv_std_logic_vector(423069,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001110" =>
inv <= conv_std_logic_vector(1570,11);
logman <= conv_std_logic_vector(529760,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001111" =>
inv <= conv_std_logic_vector(1566,11);
logman <= conv_std_logic_vector(615358,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010000" =>
inv <= conv_std_logic_vector(1561,11);
logman <= conv_std_logic_vector(722664,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010001" =>
inv <= conv_std_logic_vector(1556,11);
logman <= conv_std_logic_vector(830314,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010010" =>
inv <= conv_std_logic_vector(1552,11);
logman <= conv_std_logic_vector(916683,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010011" =>
inv <= conv_std_logic_vector(1547,11);
logman <= conv_std_logic_vector(1024958,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010100" =>
inv <= conv_std_logic_vector(1543,11);
logman <= conv_std_logic_vector(1111831,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010101" =>
inv <= conv_std_logic_vector(1538,11);
logman <= conv_std_logic_vector(1220738,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010110" =>
inv <= conv_std_logic_vector(1534,11);
logman <= conv_std_logic_vector(1308120,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010111" =>
inv <= conv_std_logic_vector(1529,11);
logman <= conv_std_logic_vector(1417667,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011000" =>
inv <= conv_std_logic_vector(1525,11);
logman <= conv_std_logic_vector(1505564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011001" =>
inv <= conv_std_logic_vector(1520,11);
logman <= conv_std_logic_vector(1615759,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011010" =>
inv <= conv_std_logic_vector(1516,11);
logman <= conv_std_logic_vector(1704177,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011011" =>
inv <= conv_std_logic_vector(1511,11);
logman <= conv_std_logic_vector(1815027,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011100" =>
inv <= conv_std_logic_vector(1507,11);
logman <= conv_std_logic_vector(1903972,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011101" =>
inv <= conv_std_logic_vector(1503,11);
logman <= conv_std_logic_vector(1993153,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011110" =>
inv <= conv_std_logic_vector(1498,11);
logman <= conv_std_logic_vector(2104964,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011111" =>
inv <= conv_std_logic_vector(1494,11);
logman <= conv_std_logic_vector(2194682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100000" =>
inv <= conv_std_logic_vector(1490,11);
logman <= conv_std_logic_vector(2284640,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100001" =>
inv <= conv_std_logic_vector(1486,11);
logman <= conv_std_logic_vector(2374840,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100010" =>
inv <= conv_std_logic_vector(1482,11);
logman <= conv_std_logic_vector(2465284,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100011" =>
inv <= conv_std_logic_vector(1477,11);
logman <= conv_std_logic_vector(2578682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100100" =>
inv <= conv_std_logic_vector(1473,11);
logman <= conv_std_logic_vector(2669677,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100101" =>
inv <= conv_std_logic_vector(1469,11);
logman <= conv_std_logic_vector(2760919,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100110" =>
inv <= conv_std_logic_vector(1465,11);
logman <= conv_std_logic_vector(2852411,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100111" =>
inv <= conv_std_logic_vector(1461,11);
logman <= conv_std_logic_vector(2944152,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101000" =>
inv <= conv_std_logic_vector(1457,11);
logman <= conv_std_logic_vector(3036145,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101001" =>
inv <= conv_std_logic_vector(1453,11);
logman <= conv_std_logic_vector(3128391,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101010" =>
inv <= conv_std_logic_vector(1449,11);
logman <= conv_std_logic_vector(3220891,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101011" =>
inv <= conv_std_logic_vector(1445,11);
logman <= conv_std_logic_vector(3313647,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101100" =>
inv <= conv_std_logic_vector(1441,11);
logman <= conv_std_logic_vector(3406660,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101101" =>
inv <= conv_std_logic_vector(1437,11);
logman <= conv_std_logic_vector(3499932,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101110" =>
inv <= conv_std_logic_vector(1433,11);
logman <= conv_std_logic_vector(3593464,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101111" =>
inv <= conv_std_logic_vector(1429,11);
logman <= conv_std_logic_vector(3687257,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110000" =>
inv <= conv_std_logic_vector(1425,11);
logman <= conv_std_logic_vector(3781312,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110001" =>
inv <= conv_std_logic_vector(1421,11);
logman <= conv_std_logic_vector(3875633,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110010" =>
inv <= conv_std_logic_vector(1417,11);
logman <= conv_std_logic_vector(3970219,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110011" =>
inv <= conv_std_logic_vector(1414,11);
logman <= conv_std_logic_vector(4041334,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110100" =>
inv <= conv_std_logic_vector(1410,11);
logman <= conv_std_logic_vector(4136389,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110101" =>
inv <= conv_std_logic_vector(1406,11);
logman <= conv_std_logic_vector(4231714,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110110" =>
inv <= conv_std_logic_vector(1402,11);
logman <= conv_std_logic_vector(4327311,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110111" =>
inv <= conv_std_logic_vector(1399,11);
logman <= conv_std_logic_vector(4399188,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111000" =>
inv <= conv_std_logic_vector(1395,11);
logman <= conv_std_logic_vector(4495263,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111001" =>
inv <= conv_std_logic_vector(1391,11);
logman <= conv_std_logic_vector(4591615,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111010" =>
inv <= conv_std_logic_vector(1388,11);
logman <= conv_std_logic_vector(4664061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111011" =>
inv <= conv_std_logic_vector(1384,11);
logman <= conv_std_logic_vector(4760899,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111100" =>
inv <= conv_std_logic_vector(1380,11);
logman <= conv_std_logic_vector(4858018,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111101" =>
inv <= conv_std_logic_vector(1377,11);
logman <= conv_std_logic_vector(4931041,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111110" =>
inv <= conv_std_logic_vector(1373,11);
logman <= conv_std_logic_vector(5028654,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111111" =>
inv <= conv_std_logic_vector(1369,11);
logman <= conv_std_logic_vector(5126552,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000000" =>
inv <= conv_std_logic_vector(1366,11);
logman <= conv_std_logic_vector(5200163,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000001" =>
inv <= conv_std_logic_vector(1362,11);
logman <= conv_std_logic_vector(5298564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000010" =>
inv <= conv_std_logic_vector(1359,11);
logman <= conv_std_logic_vector(5372554,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000011" =>
inv <= conv_std_logic_vector(1355,11);
logman <= conv_std_logic_vector(5471461,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000100" =>
inv <= conv_std_logic_vector(1352,11);
logman <= conv_std_logic_vector(5545834,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000101" =>
inv <= conv_std_logic_vector(1348,11);
logman <= conv_std_logic_vector(5645255,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000110" =>
inv <= conv_std_logic_vector(1345,11);
logman <= conv_std_logic_vector(5720014,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000111" =>
inv <= conv_std_logic_vector(1341,11);
logman <= conv_std_logic_vector(5819953,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001000" =>
inv <= conv_std_logic_vector(1338,11);
logman <= conv_std_logic_vector(5895103,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001001" =>
inv <= conv_std_logic_vector(1335,11);
logman <= conv_std_logic_vector(5970421,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001010" =>
inv <= conv_std_logic_vector(1331,11);
logman <= conv_std_logic_vector(6071110,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001011" =>
inv <= conv_std_logic_vector(1328,11);
logman <= conv_std_logic_vector(6146825,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001100" =>
inv <= conv_std_logic_vector(1324,11);
logman <= conv_std_logic_vector(6248045,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001101" =>
inv <= conv_std_logic_vector(1321,11);
logman <= conv_std_logic_vector(6324161,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001110" =>
inv <= conv_std_logic_vector(1318,11);
logman <= conv_std_logic_vector(6400450,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001111" =>
inv <= conv_std_logic_vector(1315,11);
logman <= conv_std_logic_vector(6476913,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010000" =>
inv <= conv_std_logic_vector(1311,11);
logman <= conv_std_logic_vector(6579135,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010001" =>
inv <= conv_std_logic_vector(1308,11);
logman <= conv_std_logic_vector(6656007,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010010" =>
inv <= conv_std_logic_vector(1305,11);
logman <= conv_std_logic_vector(6733055,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010011" =>
inv <= conv_std_logic_vector(1301,11);
logman <= conv_std_logic_vector(6836061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010100" =>
inv <= conv_std_logic_vector(1298,11);
logman <= conv_std_logic_vector(6913525,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010101" =>
inv <= conv_std_logic_vector(1295,11);
logman <= conv_std_logic_vector(6991167,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010110" =>
inv <= conv_std_logic_vector(1292,11);
logman <= conv_std_logic_vector(7068989,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010111" =>
inv <= conv_std_logic_vector(1289,11);
logman <= conv_std_logic_vector(7146993,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011000" =>
inv <= conv_std_logic_vector(1286,11);
logman <= conv_std_logic_vector(7225178,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011001" =>
inv <= conv_std_logic_vector(1282,11);
logman <= conv_std_logic_vector(7329709,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011010" =>
inv <= conv_std_logic_vector(1279,11);
logman <= conv_std_logic_vector(7408321,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011011" =>
inv <= conv_std_logic_vector(1276,11);
logman <= conv_std_logic_vector(7487119,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011100" =>
inv <= conv_std_logic_vector(1273,11);
logman <= conv_std_logic_vector(7566101,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011101" =>
inv <= conv_std_logic_vector(1270,11);
logman <= conv_std_logic_vector(7645270,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011110" =>
inv <= conv_std_logic_vector(1267,11);
logman <= conv_std_logic_vector(7724626,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011111" =>
inv <= conv_std_logic_vector(1264,11);
logman <= conv_std_logic_vector(7804171,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100000" =>
inv <= conv_std_logic_vector(1261,11);
logman <= conv_std_logic_vector(7883904,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100001" =>
inv <= conv_std_logic_vector(1258,11);
logman <= conv_std_logic_vector(7963827,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100010" =>
inv <= conv_std_logic_vector(1255,11);
logman <= conv_std_logic_vector(8043941,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100011" =>
inv <= conv_std_logic_vector(1252,11);
logman <= conv_std_logic_vector(8124247,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100100" =>
inv <= conv_std_logic_vector(1249,11);
logman <= conv_std_logic_vector(8204746,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100101" =>
inv <= conv_std_logic_vector(1246,11);
logman <= conv_std_logic_vector(8285438,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100110" =>
inv <= conv_std_logic_vector(1243,11);
logman <= conv_std_logic_vector(8366324,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100111" =>
inv <= conv_std_logic_vector(1240,11);
logman <= conv_std_logic_vector(29399,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101000" =>
inv <= conv_std_logic_vector(1237,11);
logman <= conv_std_logic_vector(70038,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101001" =>
inv <= conv_std_logic_vector(1234,11);
logman <= conv_std_logic_vector(110776,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101010" =>
inv <= conv_std_logic_vector(1231,11);
logman <= conv_std_logic_vector(151613,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101011" =>
inv <= conv_std_logic_vector(1228,11);
logman <= conv_std_logic_vector(192550,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101100" =>
inv <= conv_std_logic_vector(1225,11);
logman <= conv_std_logic_vector(233587,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101101" =>
inv <= conv_std_logic_vector(1223,11);
logman <= conv_std_logic_vector(261001,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101110" =>
inv <= conv_std_logic_vector(1220,11);
logman <= conv_std_logic_vector(302205,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101111" =>
inv <= conv_std_logic_vector(1217,11);
logman <= conv_std_logic_vector(343512,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110000" =>
inv <= conv_std_logic_vector(1214,11);
logman <= conv_std_logic_vector(384920,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110001" =>
inv <= conv_std_logic_vector(1211,11);
logman <= conv_std_logic_vector(426431,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110010" =>
inv <= conv_std_logic_vector(1209,11);
logman <= conv_std_logic_vector(454162,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110011" =>
inv <= conv_std_logic_vector(1206,11);
logman <= conv_std_logic_vector(495844,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110100" =>
inv <= conv_std_logic_vector(1203,11);
logman <= conv_std_logic_vector(537630,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110101" =>
inv <= conv_std_logic_vector(1200,11);
logman <= conv_std_logic_vector(579521,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110110" =>
inv <= conv_std_logic_vector(1198,11);
logman <= conv_std_logic_vector(607506,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110111" =>
inv <= conv_std_logic_vector(1195,11);
logman <= conv_std_logic_vector(649572,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111000" =>
inv <= conv_std_logic_vector(1192,11);
logman <= conv_std_logic_vector(691744,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111001" =>
inv <= conv_std_logic_vector(1189,11);
logman <= conv_std_logic_vector(734021,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111010" =>
inv <= conv_std_logic_vector(1187,11);
logman <= conv_std_logic_vector(762266,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111011" =>
inv <= conv_std_logic_vector(1184,11);
logman <= conv_std_logic_vector(804722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111100" =>
inv <= conv_std_logic_vector(1181,11);
logman <= conv_std_logic_vector(847286,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111101" =>
inv <= conv_std_logic_vector(1179,11);
logman <= conv_std_logic_vector(875722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111110" =>
inv <= conv_std_logic_vector(1176,11);
logman <= conv_std_logic_vector(918466,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111111" =>
inv <= conv_std_logic_vector(1173,11);
logman <= conv_std_logic_vector(961320,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000000" =>
inv <= conv_std_logic_vector(1171,11);
logman <= conv_std_logic_vector(989950,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000001" =>
inv <= conv_std_logic_vector(1168,11);
logman <= conv_std_logic_vector(1032987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000010" =>
inv <= conv_std_logic_vector(1166,11);
logman <= conv_std_logic_vector(1061740,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000011" =>
inv <= conv_std_logic_vector(1163,11);
logman <= conv_std_logic_vector(1104961,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000100" =>
inv <= conv_std_logic_vector(1160,11);
logman <= conv_std_logic_vector(1148295,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000101" =>
inv <= conv_std_logic_vector(1158,11);
logman <= conv_std_logic_vector(1177246,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000110" =>
inv <= conv_std_logic_vector(1155,11);
logman <= conv_std_logic_vector(1220767,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000111" =>
inv <= conv_std_logic_vector(1153,11);
logman <= conv_std_logic_vector(1249843,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001000" =>
inv <= conv_std_logic_vector(1150,11);
logman <= conv_std_logic_vector(1293553,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001001" =>
inv <= conv_std_logic_vector(1148,11);
logman <= conv_std_logic_vector(1322756,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001010" =>
inv <= conv_std_logic_vector(1145,11);
logman <= conv_std_logic_vector(1366656,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001011" =>
inv <= conv_std_logic_vector(1143,11);
logman <= conv_std_logic_vector(1395987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001100" =>
inv <= conv_std_logic_vector(1140,11);
logman <= conv_std_logic_vector(1440080,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001101" =>
inv <= conv_std_logic_vector(1138,11);
logman <= conv_std_logic_vector(1469539,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001110" =>
inv <= conv_std_logic_vector(1135,11);
logman <= conv_std_logic_vector(1513826,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001111" =>
inv <= conv_std_logic_vector(1133,11);
logman <= conv_std_logic_vector(1543415,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010000" =>
inv <= conv_std_logic_vector(1130,11);
logman <= conv_std_logic_vector(1587898,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010001" =>
inv <= conv_std_logic_vector(1128,11);
logman <= conv_std_logic_vector(1617618,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010010" =>
inv <= conv_std_logic_vector(1126,11);
logman <= conv_std_logic_vector(1647391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010011" =>
inv <= conv_std_logic_vector(1123,11);
logman <= conv_std_logic_vector(1692151,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010100" =>
inv <= conv_std_logic_vector(1121,11);
logman <= conv_std_logic_vector(1722056,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010101" =>
inv <= conv_std_logic_vector(1118,11);
logman <= conv_std_logic_vector(1767016,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010110" =>
inv <= conv_std_logic_vector(1116,11);
logman <= conv_std_logic_vector(1797055,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010111" =>
inv <= conv_std_logic_vector(1114,11);
logman <= conv_std_logic_vector(1827149,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011000" =>
inv <= conv_std_logic_vector(1111,11);
logman <= conv_std_logic_vector(1872391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011001" =>
inv <= conv_std_logic_vector(1109,11);
logman <= conv_std_logic_vector(1902620,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011010" =>
inv <= conv_std_logic_vector(1107,11);
logman <= conv_std_logic_vector(1932904,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011011" =>
inv <= conv_std_logic_vector(1104,11);
logman <= conv_std_logic_vector(1978432,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011100" =>
inv <= conv_std_logic_vector(1102,11);
logman <= conv_std_logic_vector(2008853,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011101" =>
inv <= conv_std_logic_vector(1100,11);
logman <= conv_std_logic_vector(2039330,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011110" =>
inv <= conv_std_logic_vector(1097,11);
logman <= conv_std_logic_vector(2085148,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011111" =>
inv <= conv_std_logic_vector(1095,11);
logman <= conv_std_logic_vector(2115764,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100000" =>
inv <= conv_std_logic_vector(1093,11);
logman <= conv_std_logic_vector(2146435,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100001" =>
inv <= conv_std_logic_vector(1090,11);
logman <= conv_std_logic_vector(2192547,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100010" =>
inv <= conv_std_logic_vector(1088,11);
logman <= conv_std_logic_vector(2223360,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100011" =>
inv <= conv_std_logic_vector(1086,11);
logman <= conv_std_logic_vector(2254228,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100100" =>
inv <= conv_std_logic_vector(1084,11);
logman <= conv_std_logic_vector(2285154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100101" =>
inv <= conv_std_logic_vector(1082,11);
logman <= conv_std_logic_vector(2316137,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100110" =>
inv <= conv_std_logic_vector(1079,11);
logman <= conv_std_logic_vector(2362719,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100111" =>
inv <= conv_std_logic_vector(1077,11);
logman <= conv_std_logic_vector(2393845,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101000" =>
inv <= conv_std_logic_vector(1075,11);
logman <= conv_std_logic_vector(2425030,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101001" =>
inv <= conv_std_logic_vector(1073,11);
logman <= conv_std_logic_vector(2456272,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101010" =>
inv <= conv_std_logic_vector(1070,11);
logman <= conv_std_logic_vector(2503245,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101011" =>
inv <= conv_std_logic_vector(1068,11);
logman <= conv_std_logic_vector(2534634,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101100" =>
inv <= conv_std_logic_vector(1066,11);
logman <= conv_std_logic_vector(2566082,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101101" =>
inv <= conv_std_logic_vector(1064,11);
logman <= conv_std_logic_vector(2597588,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101110" =>
inv <= conv_std_logic_vector(1062,11);
logman <= conv_std_logic_vector(2629154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101111" =>
inv <= conv_std_logic_vector(1060,11);
logman <= conv_std_logic_vector(2660779,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110000" =>
inv <= conv_std_logic_vector(1058,11);
logman <= conv_std_logic_vector(2692464,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110001" =>
inv <= conv_std_logic_vector(1055,11);
logman <= conv_std_logic_vector(2740104,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110010" =>
inv <= conv_std_logic_vector(1053,11);
logman <= conv_std_logic_vector(2771940,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110011" =>
inv <= conv_std_logic_vector(1051,11);
logman <= conv_std_logic_vector(2803835,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110100" =>
inv <= conv_std_logic_vector(1049,11);
logman <= conv_std_logic_vector(2835792,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110101" =>
inv <= conv_std_logic_vector(1047,11);
logman <= conv_std_logic_vector(2867810,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110110" =>
inv <= conv_std_logic_vector(1045,11);
logman <= conv_std_logic_vector(2899888,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110111" =>
inv <= conv_std_logic_vector(1043,11);
logman <= conv_std_logic_vector(2932029,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111000" =>
inv <= conv_std_logic_vector(1041,11);
logman <= conv_std_logic_vector(2964231,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111001" =>
inv <= conv_std_logic_vector(1039,11);
logman <= conv_std_logic_vector(2996495,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111010" =>
inv <= conv_std_logic_vector(1037,11);
logman <= conv_std_logic_vector(3028821,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111011" =>
inv <= conv_std_logic_vector(1035,11);
logman <= conv_std_logic_vector(3061209,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111100" =>
inv <= conv_std_logic_vector(1033,11);
logman <= conv_std_logic_vector(3093660,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111101" =>
inv <= conv_std_logic_vector(1031,11);
logman <= conv_std_logic_vector(3126174,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111110" =>
inv <= conv_std_logic_vector(1029,11);
logman <= conv_std_logic_vector(3158751,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111111" =>
inv <= conv_std_logic_vector(1027,11);
logman <= conv_std_logic_vector(3191392,23);
logexp <= conv_std_logic_vector(126,8);
WHEN others =>
inv <= conv_std_logic_vector(0,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlut8 IS
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlut8;
ARCHITECTURE rtl OF fp_lnlut8 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "00000000" =>
inv <= conv_std_logic_vector(1024,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "00000001" =>
inv <= conv_std_logic_vector(2041,11);
logman <= conv_std_logic_vector(6316601,23);
logexp <= conv_std_logic_vector(118,8);
WHEN "00000010" =>
inv <= conv_std_logic_vector(2033,11);
logman <= conv_std_logic_vector(7397915,23);
logexp <= conv_std_logic_vector(119,8);
WHEN "00000011" =>
inv <= conv_std_logic_vector(2025,11);
logman <= conv_std_logic_vector(3738239,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000100" =>
inv <= conv_std_logic_vector(2017,11);
logman <= conv_std_logic_vector(7988584,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000101" =>
inv <= conv_std_logic_vector(2009,11);
logman <= conv_std_logic_vector(1933606,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000110" =>
inv <= conv_std_logic_vector(2002,11);
logman <= conv_std_logic_vector(3807503,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000111" =>
inv <= conv_std_logic_vector(1994,11);
logman <= conv_std_logic_vector(5957139,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001000" =>
inv <= conv_std_logic_vector(1986,11);
logman <= conv_std_logic_vector(8115417,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001001" =>
inv <= conv_std_logic_vector(1979,11);
logman <= conv_std_logic_vector(811223,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001010" =>
inv <= conv_std_logic_vector(1972,11);
logman <= conv_std_logic_vector(1762400,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001011" =>
inv <= conv_std_logic_vector(1964,11);
logman <= conv_std_logic_vector(2853602,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001100" =>
inv <= conv_std_logic_vector(1957,11);
logman <= conv_std_logic_vector(3812057,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001101" =>
inv <= conv_std_logic_vector(1950,11);
logman <= conv_std_logic_vector(4773946,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001110" =>
inv <= conv_std_logic_vector(1942,11);
logman <= conv_std_logic_vector(5877485,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001111" =>
inv <= conv_std_logic_vector(1935,11);
logman <= conv_std_logic_vector(6846817,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010000" =>
inv <= conv_std_logic_vector(1928,11);
logman <= conv_std_logic_vector(7819662,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010001" =>
inv <= conv_std_logic_vector(1921,11);
logman <= conv_std_logic_vector(203719,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010010" =>
inv <= conv_std_logic_vector(1914,11);
logman <= conv_std_logic_vector(693693,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010011" =>
inv <= conv_std_logic_vector(1907,11);
logman <= conv_std_logic_vector(1185462,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010100" =>
inv <= conv_std_logic_vector(1900,11);
logman <= conv_std_logic_vector(1679040,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010101" =>
inv <= conv_std_logic_vector(1893,11);
logman <= conv_std_logic_vector(2174439,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010110" =>
inv <= conv_std_logic_vector(1886,11);
logman <= conv_std_logic_vector(2671674,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010111" =>
inv <= conv_std_logic_vector(1880,11);
logman <= conv_std_logic_vector(3099346,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011000" =>
inv <= conv_std_logic_vector(1873,11);
logman <= conv_std_logic_vector(3600026,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011001" =>
inv <= conv_std_logic_vector(1866,11);
logman <= conv_std_logic_vector(4102580,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011010" =>
inv <= conv_std_logic_vector(1860,11);
logman <= conv_std_logic_vector(4534844,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011011" =>
inv <= conv_std_logic_vector(1853,11);
logman <= conv_std_logic_vector(5040917,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011100" =>
inv <= conv_std_logic_vector(1847,11);
logman <= conv_std_logic_vector(5476218,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011101" =>
inv <= conv_std_logic_vector(1840,11);
logman <= conv_std_logic_vector(5985860,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011110" =>
inv <= conv_std_logic_vector(1834,11);
logman <= conv_std_logic_vector(6424242,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011111" =>
inv <= conv_std_logic_vector(1827,11);
logman <= conv_std_logic_vector(6937504,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100000" =>
inv <= conv_std_logic_vector(1821,11);
logman <= conv_std_logic_vector(7379010,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100001" =>
inv <= conv_std_logic_vector(1815,11);
logman <= conv_std_logic_vector(7821973,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100010" =>
inv <= conv_std_logic_vector(1808,11);
logman <= conv_std_logic_vector(8340618,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100011" =>
inv <= conv_std_logic_vector(1802,11);
logman <= conv_std_logic_vector(199082,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100100" =>
inv <= conv_std_logic_vector(1796,11);
logman <= conv_std_logic_vector(422902,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100101" =>
inv <= conv_std_logic_vector(1790,11);
logman <= conv_std_logic_vector(647472,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100110" =>
inv <= conv_std_logic_vector(1784,11);
logman <= conv_std_logic_vector(872796,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100111" =>
inv <= conv_std_logic_vector(1778,11);
logman <= conv_std_logic_vector(1098879,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101000" =>
inv <= conv_std_logic_vector(1772,11);
logman <= conv_std_logic_vector(1325726,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101001" =>
inv <= conv_std_logic_vector(1766,11);
logman <= conv_std_logic_vector(1553342,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101010" =>
inv <= conv_std_logic_vector(1760,11);
logman <= conv_std_logic_vector(1781734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101011" =>
inv <= conv_std_logic_vector(1754,11);
logman <= conv_std_logic_vector(2010905,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101100" =>
inv <= conv_std_logic_vector(1748,11);
logman <= conv_std_logic_vector(2240861,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101101" =>
inv <= conv_std_logic_vector(1742,11);
logman <= conv_std_logic_vector(2471608,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101110" =>
inv <= conv_std_logic_vector(1737,11);
logman <= conv_std_logic_vector(2664505,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101111" =>
inv <= conv_std_logic_vector(1731,11);
logman <= conv_std_logic_vector(2896716,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110000" =>
inv <= conv_std_logic_vector(1725,11);
logman <= conv_std_logic_vector(3129733,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110001" =>
inv <= conv_std_logic_vector(1719,11);
logman <= conv_std_logic_vector(3363562,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110010" =>
inv <= conv_std_logic_vector(1714,11);
logman <= conv_std_logic_vector(3559044,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110011" =>
inv <= conv_std_logic_vector(1708,11);
logman <= conv_std_logic_vector(3794376,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110100" =>
inv <= conv_std_logic_vector(1703,11);
logman <= conv_std_logic_vector(3991119,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110101" =>
inv <= conv_std_logic_vector(1697,11);
logman <= conv_std_logic_vector(4227974,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110110" =>
inv <= conv_std_logic_vector(1692,11);
logman <= conv_std_logic_vector(4425994,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110111" =>
inv <= conv_std_logic_vector(1686,11);
logman <= conv_std_logic_vector(4664391,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111000" =>
inv <= conv_std_logic_vector(1681,11);
logman <= conv_std_logic_vector(4863705,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111001" =>
inv <= conv_std_logic_vector(1676,11);
logman <= conv_std_logic_vector(5063612,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111010" =>
inv <= conv_std_logic_vector(1670,11);
logman <= conv_std_logic_vector(5304290,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111011" =>
inv <= conv_std_logic_vector(1665,11);
logman <= conv_std_logic_vector(5505516,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111100" =>
inv <= conv_std_logic_vector(1660,11);
logman <= conv_std_logic_vector(5707347,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111101" =>
inv <= conv_std_logic_vector(1654,11);
logman <= conv_std_logic_vector(5950349,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111110" =>
inv <= conv_std_logic_vector(1649,11);
logman <= conv_std_logic_vector(6153525,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111111" =>
inv <= conv_std_logic_vector(1644,11);
logman <= conv_std_logic_vector(6357317,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000000" =>
inv <= conv_std_logic_vector(1639,11);
logman <= conv_std_logic_vector(6561731,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000001" =>
inv <= conv_std_logic_vector(1634,11);
logman <= conv_std_logic_vector(6766769,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000010" =>
inv <= conv_std_logic_vector(1629,11);
logman <= conv_std_logic_vector(6972435,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000011" =>
inv <= conv_std_logic_vector(1624,11);
logman <= conv_std_logic_vector(7178734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000100" =>
inv <= conv_std_logic_vector(1619,11);
logman <= conv_std_logic_vector(7385668,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000101" =>
inv <= conv_std_logic_vector(1614,11);
logman <= conv_std_logic_vector(7593243,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000110" =>
inv <= conv_std_logic_vector(1609,11);
logman <= conv_std_logic_vector(7801462,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000111" =>
inv <= conv_std_logic_vector(1604,11);
logman <= conv_std_logic_vector(8010329,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001000" =>
inv <= conv_std_logic_vector(1599,11);
logman <= conv_std_logic_vector(8219848,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001001" =>
inv <= conv_std_logic_vector(1594,11);
logman <= conv_std_logic_vector(20707,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001010" =>
inv <= conv_std_logic_vector(1589,11);
logman <= conv_std_logic_vector(126125,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001011" =>
inv <= conv_std_logic_vector(1584,11);
logman <= conv_std_logic_vector(231875,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001100" =>
inv <= conv_std_logic_vector(1580,11);
logman <= conv_std_logic_vector(316716,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001101" =>
inv <= conv_std_logic_vector(1575,11);
logman <= conv_std_logic_vector(423069,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001110" =>
inv <= conv_std_logic_vector(1570,11);
logman <= conv_std_logic_vector(529760,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001111" =>
inv <= conv_std_logic_vector(1566,11);
logman <= conv_std_logic_vector(615358,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010000" =>
inv <= conv_std_logic_vector(1561,11);
logman <= conv_std_logic_vector(722664,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010001" =>
inv <= conv_std_logic_vector(1556,11);
logman <= conv_std_logic_vector(830314,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010010" =>
inv <= conv_std_logic_vector(1552,11);
logman <= conv_std_logic_vector(916683,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010011" =>
inv <= conv_std_logic_vector(1547,11);
logman <= conv_std_logic_vector(1024958,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010100" =>
inv <= conv_std_logic_vector(1543,11);
logman <= conv_std_logic_vector(1111831,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010101" =>
inv <= conv_std_logic_vector(1538,11);
logman <= conv_std_logic_vector(1220738,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010110" =>
inv <= conv_std_logic_vector(1534,11);
logman <= conv_std_logic_vector(1308120,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010111" =>
inv <= conv_std_logic_vector(1529,11);
logman <= conv_std_logic_vector(1417667,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011000" =>
inv <= conv_std_logic_vector(1525,11);
logman <= conv_std_logic_vector(1505564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011001" =>
inv <= conv_std_logic_vector(1520,11);
logman <= conv_std_logic_vector(1615759,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011010" =>
inv <= conv_std_logic_vector(1516,11);
logman <= conv_std_logic_vector(1704177,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011011" =>
inv <= conv_std_logic_vector(1511,11);
logman <= conv_std_logic_vector(1815027,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011100" =>
inv <= conv_std_logic_vector(1507,11);
logman <= conv_std_logic_vector(1903972,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011101" =>
inv <= conv_std_logic_vector(1503,11);
logman <= conv_std_logic_vector(1993153,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011110" =>
inv <= conv_std_logic_vector(1498,11);
logman <= conv_std_logic_vector(2104964,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011111" =>
inv <= conv_std_logic_vector(1494,11);
logman <= conv_std_logic_vector(2194682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100000" =>
inv <= conv_std_logic_vector(1490,11);
logman <= conv_std_logic_vector(2284640,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100001" =>
inv <= conv_std_logic_vector(1486,11);
logman <= conv_std_logic_vector(2374840,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100010" =>
inv <= conv_std_logic_vector(1482,11);
logman <= conv_std_logic_vector(2465284,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100011" =>
inv <= conv_std_logic_vector(1477,11);
logman <= conv_std_logic_vector(2578682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100100" =>
inv <= conv_std_logic_vector(1473,11);
logman <= conv_std_logic_vector(2669677,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100101" =>
inv <= conv_std_logic_vector(1469,11);
logman <= conv_std_logic_vector(2760919,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100110" =>
inv <= conv_std_logic_vector(1465,11);
logman <= conv_std_logic_vector(2852411,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100111" =>
inv <= conv_std_logic_vector(1461,11);
logman <= conv_std_logic_vector(2944152,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101000" =>
inv <= conv_std_logic_vector(1457,11);
logman <= conv_std_logic_vector(3036145,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101001" =>
inv <= conv_std_logic_vector(1453,11);
logman <= conv_std_logic_vector(3128391,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101010" =>
inv <= conv_std_logic_vector(1449,11);
logman <= conv_std_logic_vector(3220891,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101011" =>
inv <= conv_std_logic_vector(1445,11);
logman <= conv_std_logic_vector(3313647,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101100" =>
inv <= conv_std_logic_vector(1441,11);
logman <= conv_std_logic_vector(3406660,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101101" =>
inv <= conv_std_logic_vector(1437,11);
logman <= conv_std_logic_vector(3499932,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101110" =>
inv <= conv_std_logic_vector(1433,11);
logman <= conv_std_logic_vector(3593464,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101111" =>
inv <= conv_std_logic_vector(1429,11);
logman <= conv_std_logic_vector(3687257,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110000" =>
inv <= conv_std_logic_vector(1425,11);
logman <= conv_std_logic_vector(3781312,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110001" =>
inv <= conv_std_logic_vector(1421,11);
logman <= conv_std_logic_vector(3875633,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110010" =>
inv <= conv_std_logic_vector(1417,11);
logman <= conv_std_logic_vector(3970219,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110011" =>
inv <= conv_std_logic_vector(1414,11);
logman <= conv_std_logic_vector(4041334,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110100" =>
inv <= conv_std_logic_vector(1410,11);
logman <= conv_std_logic_vector(4136389,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110101" =>
inv <= conv_std_logic_vector(1406,11);
logman <= conv_std_logic_vector(4231714,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110110" =>
inv <= conv_std_logic_vector(1402,11);
logman <= conv_std_logic_vector(4327311,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110111" =>
inv <= conv_std_logic_vector(1399,11);
logman <= conv_std_logic_vector(4399188,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111000" =>
inv <= conv_std_logic_vector(1395,11);
logman <= conv_std_logic_vector(4495263,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111001" =>
inv <= conv_std_logic_vector(1391,11);
logman <= conv_std_logic_vector(4591615,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111010" =>
inv <= conv_std_logic_vector(1388,11);
logman <= conv_std_logic_vector(4664061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111011" =>
inv <= conv_std_logic_vector(1384,11);
logman <= conv_std_logic_vector(4760899,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111100" =>
inv <= conv_std_logic_vector(1380,11);
logman <= conv_std_logic_vector(4858018,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111101" =>
inv <= conv_std_logic_vector(1377,11);
logman <= conv_std_logic_vector(4931041,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111110" =>
inv <= conv_std_logic_vector(1373,11);
logman <= conv_std_logic_vector(5028654,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111111" =>
inv <= conv_std_logic_vector(1369,11);
logman <= conv_std_logic_vector(5126552,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000000" =>
inv <= conv_std_logic_vector(1366,11);
logman <= conv_std_logic_vector(5200163,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000001" =>
inv <= conv_std_logic_vector(1362,11);
logman <= conv_std_logic_vector(5298564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000010" =>
inv <= conv_std_logic_vector(1359,11);
logman <= conv_std_logic_vector(5372554,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000011" =>
inv <= conv_std_logic_vector(1355,11);
logman <= conv_std_logic_vector(5471461,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000100" =>
inv <= conv_std_logic_vector(1352,11);
logman <= conv_std_logic_vector(5545834,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000101" =>
inv <= conv_std_logic_vector(1348,11);
logman <= conv_std_logic_vector(5645255,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000110" =>
inv <= conv_std_logic_vector(1345,11);
logman <= conv_std_logic_vector(5720014,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000111" =>
inv <= conv_std_logic_vector(1341,11);
logman <= conv_std_logic_vector(5819953,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001000" =>
inv <= conv_std_logic_vector(1338,11);
logman <= conv_std_logic_vector(5895103,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001001" =>
inv <= conv_std_logic_vector(1335,11);
logman <= conv_std_logic_vector(5970421,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001010" =>
inv <= conv_std_logic_vector(1331,11);
logman <= conv_std_logic_vector(6071110,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001011" =>
inv <= conv_std_logic_vector(1328,11);
logman <= conv_std_logic_vector(6146825,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001100" =>
inv <= conv_std_logic_vector(1324,11);
logman <= conv_std_logic_vector(6248045,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001101" =>
inv <= conv_std_logic_vector(1321,11);
logman <= conv_std_logic_vector(6324161,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001110" =>
inv <= conv_std_logic_vector(1318,11);
logman <= conv_std_logic_vector(6400450,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001111" =>
inv <= conv_std_logic_vector(1315,11);
logman <= conv_std_logic_vector(6476913,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010000" =>
inv <= conv_std_logic_vector(1311,11);
logman <= conv_std_logic_vector(6579135,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010001" =>
inv <= conv_std_logic_vector(1308,11);
logman <= conv_std_logic_vector(6656007,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010010" =>
inv <= conv_std_logic_vector(1305,11);
logman <= conv_std_logic_vector(6733055,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010011" =>
inv <= conv_std_logic_vector(1301,11);
logman <= conv_std_logic_vector(6836061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010100" =>
inv <= conv_std_logic_vector(1298,11);
logman <= conv_std_logic_vector(6913525,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010101" =>
inv <= conv_std_logic_vector(1295,11);
logman <= conv_std_logic_vector(6991167,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010110" =>
inv <= conv_std_logic_vector(1292,11);
logman <= conv_std_logic_vector(7068989,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010111" =>
inv <= conv_std_logic_vector(1289,11);
logman <= conv_std_logic_vector(7146993,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011000" =>
inv <= conv_std_logic_vector(1286,11);
logman <= conv_std_logic_vector(7225178,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011001" =>
inv <= conv_std_logic_vector(1282,11);
logman <= conv_std_logic_vector(7329709,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011010" =>
inv <= conv_std_logic_vector(1279,11);
logman <= conv_std_logic_vector(7408321,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011011" =>
inv <= conv_std_logic_vector(1276,11);
logman <= conv_std_logic_vector(7487119,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011100" =>
inv <= conv_std_logic_vector(1273,11);
logman <= conv_std_logic_vector(7566101,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011101" =>
inv <= conv_std_logic_vector(1270,11);
logman <= conv_std_logic_vector(7645270,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011110" =>
inv <= conv_std_logic_vector(1267,11);
logman <= conv_std_logic_vector(7724626,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011111" =>
inv <= conv_std_logic_vector(1264,11);
logman <= conv_std_logic_vector(7804171,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100000" =>
inv <= conv_std_logic_vector(1261,11);
logman <= conv_std_logic_vector(7883904,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100001" =>
inv <= conv_std_logic_vector(1258,11);
logman <= conv_std_logic_vector(7963827,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100010" =>
inv <= conv_std_logic_vector(1255,11);
logman <= conv_std_logic_vector(8043941,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100011" =>
inv <= conv_std_logic_vector(1252,11);
logman <= conv_std_logic_vector(8124247,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100100" =>
inv <= conv_std_logic_vector(1249,11);
logman <= conv_std_logic_vector(8204746,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100101" =>
inv <= conv_std_logic_vector(1246,11);
logman <= conv_std_logic_vector(8285438,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100110" =>
inv <= conv_std_logic_vector(1243,11);
logman <= conv_std_logic_vector(8366324,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100111" =>
inv <= conv_std_logic_vector(1240,11);
logman <= conv_std_logic_vector(29399,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101000" =>
inv <= conv_std_logic_vector(1237,11);
logman <= conv_std_logic_vector(70038,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101001" =>
inv <= conv_std_logic_vector(1234,11);
logman <= conv_std_logic_vector(110776,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101010" =>
inv <= conv_std_logic_vector(1231,11);
logman <= conv_std_logic_vector(151613,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101011" =>
inv <= conv_std_logic_vector(1228,11);
logman <= conv_std_logic_vector(192550,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101100" =>
inv <= conv_std_logic_vector(1225,11);
logman <= conv_std_logic_vector(233587,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101101" =>
inv <= conv_std_logic_vector(1223,11);
logman <= conv_std_logic_vector(261001,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101110" =>
inv <= conv_std_logic_vector(1220,11);
logman <= conv_std_logic_vector(302205,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101111" =>
inv <= conv_std_logic_vector(1217,11);
logman <= conv_std_logic_vector(343512,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110000" =>
inv <= conv_std_logic_vector(1214,11);
logman <= conv_std_logic_vector(384920,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110001" =>
inv <= conv_std_logic_vector(1211,11);
logman <= conv_std_logic_vector(426431,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110010" =>
inv <= conv_std_logic_vector(1209,11);
logman <= conv_std_logic_vector(454162,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110011" =>
inv <= conv_std_logic_vector(1206,11);
logman <= conv_std_logic_vector(495844,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110100" =>
inv <= conv_std_logic_vector(1203,11);
logman <= conv_std_logic_vector(537630,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110101" =>
inv <= conv_std_logic_vector(1200,11);
logman <= conv_std_logic_vector(579521,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110110" =>
inv <= conv_std_logic_vector(1198,11);
logman <= conv_std_logic_vector(607506,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110111" =>
inv <= conv_std_logic_vector(1195,11);
logman <= conv_std_logic_vector(649572,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111000" =>
inv <= conv_std_logic_vector(1192,11);
logman <= conv_std_logic_vector(691744,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111001" =>
inv <= conv_std_logic_vector(1189,11);
logman <= conv_std_logic_vector(734021,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111010" =>
inv <= conv_std_logic_vector(1187,11);
logman <= conv_std_logic_vector(762266,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111011" =>
inv <= conv_std_logic_vector(1184,11);
logman <= conv_std_logic_vector(804722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111100" =>
inv <= conv_std_logic_vector(1181,11);
logman <= conv_std_logic_vector(847286,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111101" =>
inv <= conv_std_logic_vector(1179,11);
logman <= conv_std_logic_vector(875722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111110" =>
inv <= conv_std_logic_vector(1176,11);
logman <= conv_std_logic_vector(918466,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111111" =>
inv <= conv_std_logic_vector(1173,11);
logman <= conv_std_logic_vector(961320,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000000" =>
inv <= conv_std_logic_vector(1171,11);
logman <= conv_std_logic_vector(989950,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000001" =>
inv <= conv_std_logic_vector(1168,11);
logman <= conv_std_logic_vector(1032987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000010" =>
inv <= conv_std_logic_vector(1166,11);
logman <= conv_std_logic_vector(1061740,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000011" =>
inv <= conv_std_logic_vector(1163,11);
logman <= conv_std_logic_vector(1104961,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000100" =>
inv <= conv_std_logic_vector(1160,11);
logman <= conv_std_logic_vector(1148295,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000101" =>
inv <= conv_std_logic_vector(1158,11);
logman <= conv_std_logic_vector(1177246,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000110" =>
inv <= conv_std_logic_vector(1155,11);
logman <= conv_std_logic_vector(1220767,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000111" =>
inv <= conv_std_logic_vector(1153,11);
logman <= conv_std_logic_vector(1249843,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001000" =>
inv <= conv_std_logic_vector(1150,11);
logman <= conv_std_logic_vector(1293553,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001001" =>
inv <= conv_std_logic_vector(1148,11);
logman <= conv_std_logic_vector(1322756,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001010" =>
inv <= conv_std_logic_vector(1145,11);
logman <= conv_std_logic_vector(1366656,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001011" =>
inv <= conv_std_logic_vector(1143,11);
logman <= conv_std_logic_vector(1395987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001100" =>
inv <= conv_std_logic_vector(1140,11);
logman <= conv_std_logic_vector(1440080,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001101" =>
inv <= conv_std_logic_vector(1138,11);
logman <= conv_std_logic_vector(1469539,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001110" =>
inv <= conv_std_logic_vector(1135,11);
logman <= conv_std_logic_vector(1513826,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001111" =>
inv <= conv_std_logic_vector(1133,11);
logman <= conv_std_logic_vector(1543415,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010000" =>
inv <= conv_std_logic_vector(1130,11);
logman <= conv_std_logic_vector(1587898,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010001" =>
inv <= conv_std_logic_vector(1128,11);
logman <= conv_std_logic_vector(1617618,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010010" =>
inv <= conv_std_logic_vector(1126,11);
logman <= conv_std_logic_vector(1647391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010011" =>
inv <= conv_std_logic_vector(1123,11);
logman <= conv_std_logic_vector(1692151,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010100" =>
inv <= conv_std_logic_vector(1121,11);
logman <= conv_std_logic_vector(1722056,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010101" =>
inv <= conv_std_logic_vector(1118,11);
logman <= conv_std_logic_vector(1767016,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010110" =>
inv <= conv_std_logic_vector(1116,11);
logman <= conv_std_logic_vector(1797055,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010111" =>
inv <= conv_std_logic_vector(1114,11);
logman <= conv_std_logic_vector(1827149,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011000" =>
inv <= conv_std_logic_vector(1111,11);
logman <= conv_std_logic_vector(1872391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011001" =>
inv <= conv_std_logic_vector(1109,11);
logman <= conv_std_logic_vector(1902620,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011010" =>
inv <= conv_std_logic_vector(1107,11);
logman <= conv_std_logic_vector(1932904,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011011" =>
inv <= conv_std_logic_vector(1104,11);
logman <= conv_std_logic_vector(1978432,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011100" =>
inv <= conv_std_logic_vector(1102,11);
logman <= conv_std_logic_vector(2008853,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011101" =>
inv <= conv_std_logic_vector(1100,11);
logman <= conv_std_logic_vector(2039330,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011110" =>
inv <= conv_std_logic_vector(1097,11);
logman <= conv_std_logic_vector(2085148,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011111" =>
inv <= conv_std_logic_vector(1095,11);
logman <= conv_std_logic_vector(2115764,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100000" =>
inv <= conv_std_logic_vector(1093,11);
logman <= conv_std_logic_vector(2146435,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100001" =>
inv <= conv_std_logic_vector(1090,11);
logman <= conv_std_logic_vector(2192547,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100010" =>
inv <= conv_std_logic_vector(1088,11);
logman <= conv_std_logic_vector(2223360,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100011" =>
inv <= conv_std_logic_vector(1086,11);
logman <= conv_std_logic_vector(2254228,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100100" =>
inv <= conv_std_logic_vector(1084,11);
logman <= conv_std_logic_vector(2285154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100101" =>
inv <= conv_std_logic_vector(1082,11);
logman <= conv_std_logic_vector(2316137,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100110" =>
inv <= conv_std_logic_vector(1079,11);
logman <= conv_std_logic_vector(2362719,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100111" =>
inv <= conv_std_logic_vector(1077,11);
logman <= conv_std_logic_vector(2393845,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101000" =>
inv <= conv_std_logic_vector(1075,11);
logman <= conv_std_logic_vector(2425030,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101001" =>
inv <= conv_std_logic_vector(1073,11);
logman <= conv_std_logic_vector(2456272,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101010" =>
inv <= conv_std_logic_vector(1070,11);
logman <= conv_std_logic_vector(2503245,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101011" =>
inv <= conv_std_logic_vector(1068,11);
logman <= conv_std_logic_vector(2534634,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101100" =>
inv <= conv_std_logic_vector(1066,11);
logman <= conv_std_logic_vector(2566082,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101101" =>
inv <= conv_std_logic_vector(1064,11);
logman <= conv_std_logic_vector(2597588,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101110" =>
inv <= conv_std_logic_vector(1062,11);
logman <= conv_std_logic_vector(2629154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101111" =>
inv <= conv_std_logic_vector(1060,11);
logman <= conv_std_logic_vector(2660779,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110000" =>
inv <= conv_std_logic_vector(1058,11);
logman <= conv_std_logic_vector(2692464,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110001" =>
inv <= conv_std_logic_vector(1055,11);
logman <= conv_std_logic_vector(2740104,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110010" =>
inv <= conv_std_logic_vector(1053,11);
logman <= conv_std_logic_vector(2771940,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110011" =>
inv <= conv_std_logic_vector(1051,11);
logman <= conv_std_logic_vector(2803835,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110100" =>
inv <= conv_std_logic_vector(1049,11);
logman <= conv_std_logic_vector(2835792,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110101" =>
inv <= conv_std_logic_vector(1047,11);
logman <= conv_std_logic_vector(2867810,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110110" =>
inv <= conv_std_logic_vector(1045,11);
logman <= conv_std_logic_vector(2899888,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110111" =>
inv <= conv_std_logic_vector(1043,11);
logman <= conv_std_logic_vector(2932029,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111000" =>
inv <= conv_std_logic_vector(1041,11);
logman <= conv_std_logic_vector(2964231,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111001" =>
inv <= conv_std_logic_vector(1039,11);
logman <= conv_std_logic_vector(2996495,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111010" =>
inv <= conv_std_logic_vector(1037,11);
logman <= conv_std_logic_vector(3028821,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111011" =>
inv <= conv_std_logic_vector(1035,11);
logman <= conv_std_logic_vector(3061209,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111100" =>
inv <= conv_std_logic_vector(1033,11);
logman <= conv_std_logic_vector(3093660,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111101" =>
inv <= conv_std_logic_vector(1031,11);
logman <= conv_std_logic_vector(3126174,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111110" =>
inv <= conv_std_logic_vector(1029,11);
logman <= conv_std_logic_vector(3158751,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111111" =>
inv <= conv_std_logic_vector(1027,11);
logman <= conv_std_logic_vector(3191392,23);
logexp <= conv_std_logic_vector(126,8);
WHEN others =>
inv <= conv_std_logic_vector(0,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlut8 IS
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlut8;
ARCHITECTURE rtl OF fp_lnlut8 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "00000000" =>
inv <= conv_std_logic_vector(1024,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "00000001" =>
inv <= conv_std_logic_vector(2041,11);
logman <= conv_std_logic_vector(6316601,23);
logexp <= conv_std_logic_vector(118,8);
WHEN "00000010" =>
inv <= conv_std_logic_vector(2033,11);
logman <= conv_std_logic_vector(7397915,23);
logexp <= conv_std_logic_vector(119,8);
WHEN "00000011" =>
inv <= conv_std_logic_vector(2025,11);
logman <= conv_std_logic_vector(3738239,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000100" =>
inv <= conv_std_logic_vector(2017,11);
logman <= conv_std_logic_vector(7988584,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000101" =>
inv <= conv_std_logic_vector(2009,11);
logman <= conv_std_logic_vector(1933606,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000110" =>
inv <= conv_std_logic_vector(2002,11);
logman <= conv_std_logic_vector(3807503,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000111" =>
inv <= conv_std_logic_vector(1994,11);
logman <= conv_std_logic_vector(5957139,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001000" =>
inv <= conv_std_logic_vector(1986,11);
logman <= conv_std_logic_vector(8115417,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001001" =>
inv <= conv_std_logic_vector(1979,11);
logman <= conv_std_logic_vector(811223,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001010" =>
inv <= conv_std_logic_vector(1972,11);
logman <= conv_std_logic_vector(1762400,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001011" =>
inv <= conv_std_logic_vector(1964,11);
logman <= conv_std_logic_vector(2853602,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001100" =>
inv <= conv_std_logic_vector(1957,11);
logman <= conv_std_logic_vector(3812057,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001101" =>
inv <= conv_std_logic_vector(1950,11);
logman <= conv_std_logic_vector(4773946,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001110" =>
inv <= conv_std_logic_vector(1942,11);
logman <= conv_std_logic_vector(5877485,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001111" =>
inv <= conv_std_logic_vector(1935,11);
logman <= conv_std_logic_vector(6846817,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010000" =>
inv <= conv_std_logic_vector(1928,11);
logman <= conv_std_logic_vector(7819662,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010001" =>
inv <= conv_std_logic_vector(1921,11);
logman <= conv_std_logic_vector(203719,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010010" =>
inv <= conv_std_logic_vector(1914,11);
logman <= conv_std_logic_vector(693693,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010011" =>
inv <= conv_std_logic_vector(1907,11);
logman <= conv_std_logic_vector(1185462,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010100" =>
inv <= conv_std_logic_vector(1900,11);
logman <= conv_std_logic_vector(1679040,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010101" =>
inv <= conv_std_logic_vector(1893,11);
logman <= conv_std_logic_vector(2174439,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010110" =>
inv <= conv_std_logic_vector(1886,11);
logman <= conv_std_logic_vector(2671674,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010111" =>
inv <= conv_std_logic_vector(1880,11);
logman <= conv_std_logic_vector(3099346,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011000" =>
inv <= conv_std_logic_vector(1873,11);
logman <= conv_std_logic_vector(3600026,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011001" =>
inv <= conv_std_logic_vector(1866,11);
logman <= conv_std_logic_vector(4102580,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011010" =>
inv <= conv_std_logic_vector(1860,11);
logman <= conv_std_logic_vector(4534844,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011011" =>
inv <= conv_std_logic_vector(1853,11);
logman <= conv_std_logic_vector(5040917,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011100" =>
inv <= conv_std_logic_vector(1847,11);
logman <= conv_std_logic_vector(5476218,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011101" =>
inv <= conv_std_logic_vector(1840,11);
logman <= conv_std_logic_vector(5985860,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011110" =>
inv <= conv_std_logic_vector(1834,11);
logman <= conv_std_logic_vector(6424242,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011111" =>
inv <= conv_std_logic_vector(1827,11);
logman <= conv_std_logic_vector(6937504,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100000" =>
inv <= conv_std_logic_vector(1821,11);
logman <= conv_std_logic_vector(7379010,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100001" =>
inv <= conv_std_logic_vector(1815,11);
logman <= conv_std_logic_vector(7821973,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100010" =>
inv <= conv_std_logic_vector(1808,11);
logman <= conv_std_logic_vector(8340618,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100011" =>
inv <= conv_std_logic_vector(1802,11);
logman <= conv_std_logic_vector(199082,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100100" =>
inv <= conv_std_logic_vector(1796,11);
logman <= conv_std_logic_vector(422902,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100101" =>
inv <= conv_std_logic_vector(1790,11);
logman <= conv_std_logic_vector(647472,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100110" =>
inv <= conv_std_logic_vector(1784,11);
logman <= conv_std_logic_vector(872796,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100111" =>
inv <= conv_std_logic_vector(1778,11);
logman <= conv_std_logic_vector(1098879,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101000" =>
inv <= conv_std_logic_vector(1772,11);
logman <= conv_std_logic_vector(1325726,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101001" =>
inv <= conv_std_logic_vector(1766,11);
logman <= conv_std_logic_vector(1553342,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101010" =>
inv <= conv_std_logic_vector(1760,11);
logman <= conv_std_logic_vector(1781734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101011" =>
inv <= conv_std_logic_vector(1754,11);
logman <= conv_std_logic_vector(2010905,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101100" =>
inv <= conv_std_logic_vector(1748,11);
logman <= conv_std_logic_vector(2240861,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101101" =>
inv <= conv_std_logic_vector(1742,11);
logman <= conv_std_logic_vector(2471608,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101110" =>
inv <= conv_std_logic_vector(1737,11);
logman <= conv_std_logic_vector(2664505,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101111" =>
inv <= conv_std_logic_vector(1731,11);
logman <= conv_std_logic_vector(2896716,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110000" =>
inv <= conv_std_logic_vector(1725,11);
logman <= conv_std_logic_vector(3129733,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110001" =>
inv <= conv_std_logic_vector(1719,11);
logman <= conv_std_logic_vector(3363562,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110010" =>
inv <= conv_std_logic_vector(1714,11);
logman <= conv_std_logic_vector(3559044,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110011" =>
inv <= conv_std_logic_vector(1708,11);
logman <= conv_std_logic_vector(3794376,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110100" =>
inv <= conv_std_logic_vector(1703,11);
logman <= conv_std_logic_vector(3991119,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110101" =>
inv <= conv_std_logic_vector(1697,11);
logman <= conv_std_logic_vector(4227974,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110110" =>
inv <= conv_std_logic_vector(1692,11);
logman <= conv_std_logic_vector(4425994,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110111" =>
inv <= conv_std_logic_vector(1686,11);
logman <= conv_std_logic_vector(4664391,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111000" =>
inv <= conv_std_logic_vector(1681,11);
logman <= conv_std_logic_vector(4863705,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111001" =>
inv <= conv_std_logic_vector(1676,11);
logman <= conv_std_logic_vector(5063612,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111010" =>
inv <= conv_std_logic_vector(1670,11);
logman <= conv_std_logic_vector(5304290,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111011" =>
inv <= conv_std_logic_vector(1665,11);
logman <= conv_std_logic_vector(5505516,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111100" =>
inv <= conv_std_logic_vector(1660,11);
logman <= conv_std_logic_vector(5707347,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111101" =>
inv <= conv_std_logic_vector(1654,11);
logman <= conv_std_logic_vector(5950349,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111110" =>
inv <= conv_std_logic_vector(1649,11);
logman <= conv_std_logic_vector(6153525,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111111" =>
inv <= conv_std_logic_vector(1644,11);
logman <= conv_std_logic_vector(6357317,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000000" =>
inv <= conv_std_logic_vector(1639,11);
logman <= conv_std_logic_vector(6561731,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000001" =>
inv <= conv_std_logic_vector(1634,11);
logman <= conv_std_logic_vector(6766769,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000010" =>
inv <= conv_std_logic_vector(1629,11);
logman <= conv_std_logic_vector(6972435,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000011" =>
inv <= conv_std_logic_vector(1624,11);
logman <= conv_std_logic_vector(7178734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000100" =>
inv <= conv_std_logic_vector(1619,11);
logman <= conv_std_logic_vector(7385668,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000101" =>
inv <= conv_std_logic_vector(1614,11);
logman <= conv_std_logic_vector(7593243,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000110" =>
inv <= conv_std_logic_vector(1609,11);
logman <= conv_std_logic_vector(7801462,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000111" =>
inv <= conv_std_logic_vector(1604,11);
logman <= conv_std_logic_vector(8010329,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001000" =>
inv <= conv_std_logic_vector(1599,11);
logman <= conv_std_logic_vector(8219848,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001001" =>
inv <= conv_std_logic_vector(1594,11);
logman <= conv_std_logic_vector(20707,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001010" =>
inv <= conv_std_logic_vector(1589,11);
logman <= conv_std_logic_vector(126125,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001011" =>
inv <= conv_std_logic_vector(1584,11);
logman <= conv_std_logic_vector(231875,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001100" =>
inv <= conv_std_logic_vector(1580,11);
logman <= conv_std_logic_vector(316716,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001101" =>
inv <= conv_std_logic_vector(1575,11);
logman <= conv_std_logic_vector(423069,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001110" =>
inv <= conv_std_logic_vector(1570,11);
logman <= conv_std_logic_vector(529760,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001111" =>
inv <= conv_std_logic_vector(1566,11);
logman <= conv_std_logic_vector(615358,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010000" =>
inv <= conv_std_logic_vector(1561,11);
logman <= conv_std_logic_vector(722664,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010001" =>
inv <= conv_std_logic_vector(1556,11);
logman <= conv_std_logic_vector(830314,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010010" =>
inv <= conv_std_logic_vector(1552,11);
logman <= conv_std_logic_vector(916683,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010011" =>
inv <= conv_std_logic_vector(1547,11);
logman <= conv_std_logic_vector(1024958,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010100" =>
inv <= conv_std_logic_vector(1543,11);
logman <= conv_std_logic_vector(1111831,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010101" =>
inv <= conv_std_logic_vector(1538,11);
logman <= conv_std_logic_vector(1220738,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010110" =>
inv <= conv_std_logic_vector(1534,11);
logman <= conv_std_logic_vector(1308120,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010111" =>
inv <= conv_std_logic_vector(1529,11);
logman <= conv_std_logic_vector(1417667,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011000" =>
inv <= conv_std_logic_vector(1525,11);
logman <= conv_std_logic_vector(1505564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011001" =>
inv <= conv_std_logic_vector(1520,11);
logman <= conv_std_logic_vector(1615759,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011010" =>
inv <= conv_std_logic_vector(1516,11);
logman <= conv_std_logic_vector(1704177,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011011" =>
inv <= conv_std_logic_vector(1511,11);
logman <= conv_std_logic_vector(1815027,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011100" =>
inv <= conv_std_logic_vector(1507,11);
logman <= conv_std_logic_vector(1903972,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011101" =>
inv <= conv_std_logic_vector(1503,11);
logman <= conv_std_logic_vector(1993153,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011110" =>
inv <= conv_std_logic_vector(1498,11);
logman <= conv_std_logic_vector(2104964,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011111" =>
inv <= conv_std_logic_vector(1494,11);
logman <= conv_std_logic_vector(2194682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100000" =>
inv <= conv_std_logic_vector(1490,11);
logman <= conv_std_logic_vector(2284640,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100001" =>
inv <= conv_std_logic_vector(1486,11);
logman <= conv_std_logic_vector(2374840,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100010" =>
inv <= conv_std_logic_vector(1482,11);
logman <= conv_std_logic_vector(2465284,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100011" =>
inv <= conv_std_logic_vector(1477,11);
logman <= conv_std_logic_vector(2578682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100100" =>
inv <= conv_std_logic_vector(1473,11);
logman <= conv_std_logic_vector(2669677,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100101" =>
inv <= conv_std_logic_vector(1469,11);
logman <= conv_std_logic_vector(2760919,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100110" =>
inv <= conv_std_logic_vector(1465,11);
logman <= conv_std_logic_vector(2852411,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100111" =>
inv <= conv_std_logic_vector(1461,11);
logman <= conv_std_logic_vector(2944152,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101000" =>
inv <= conv_std_logic_vector(1457,11);
logman <= conv_std_logic_vector(3036145,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101001" =>
inv <= conv_std_logic_vector(1453,11);
logman <= conv_std_logic_vector(3128391,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101010" =>
inv <= conv_std_logic_vector(1449,11);
logman <= conv_std_logic_vector(3220891,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101011" =>
inv <= conv_std_logic_vector(1445,11);
logman <= conv_std_logic_vector(3313647,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101100" =>
inv <= conv_std_logic_vector(1441,11);
logman <= conv_std_logic_vector(3406660,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101101" =>
inv <= conv_std_logic_vector(1437,11);
logman <= conv_std_logic_vector(3499932,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101110" =>
inv <= conv_std_logic_vector(1433,11);
logman <= conv_std_logic_vector(3593464,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101111" =>
inv <= conv_std_logic_vector(1429,11);
logman <= conv_std_logic_vector(3687257,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110000" =>
inv <= conv_std_logic_vector(1425,11);
logman <= conv_std_logic_vector(3781312,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110001" =>
inv <= conv_std_logic_vector(1421,11);
logman <= conv_std_logic_vector(3875633,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110010" =>
inv <= conv_std_logic_vector(1417,11);
logman <= conv_std_logic_vector(3970219,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110011" =>
inv <= conv_std_logic_vector(1414,11);
logman <= conv_std_logic_vector(4041334,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110100" =>
inv <= conv_std_logic_vector(1410,11);
logman <= conv_std_logic_vector(4136389,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110101" =>
inv <= conv_std_logic_vector(1406,11);
logman <= conv_std_logic_vector(4231714,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110110" =>
inv <= conv_std_logic_vector(1402,11);
logman <= conv_std_logic_vector(4327311,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110111" =>
inv <= conv_std_logic_vector(1399,11);
logman <= conv_std_logic_vector(4399188,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111000" =>
inv <= conv_std_logic_vector(1395,11);
logman <= conv_std_logic_vector(4495263,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111001" =>
inv <= conv_std_logic_vector(1391,11);
logman <= conv_std_logic_vector(4591615,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111010" =>
inv <= conv_std_logic_vector(1388,11);
logman <= conv_std_logic_vector(4664061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111011" =>
inv <= conv_std_logic_vector(1384,11);
logman <= conv_std_logic_vector(4760899,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111100" =>
inv <= conv_std_logic_vector(1380,11);
logman <= conv_std_logic_vector(4858018,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111101" =>
inv <= conv_std_logic_vector(1377,11);
logman <= conv_std_logic_vector(4931041,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111110" =>
inv <= conv_std_logic_vector(1373,11);
logman <= conv_std_logic_vector(5028654,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111111" =>
inv <= conv_std_logic_vector(1369,11);
logman <= conv_std_logic_vector(5126552,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000000" =>
inv <= conv_std_logic_vector(1366,11);
logman <= conv_std_logic_vector(5200163,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000001" =>
inv <= conv_std_logic_vector(1362,11);
logman <= conv_std_logic_vector(5298564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000010" =>
inv <= conv_std_logic_vector(1359,11);
logman <= conv_std_logic_vector(5372554,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000011" =>
inv <= conv_std_logic_vector(1355,11);
logman <= conv_std_logic_vector(5471461,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000100" =>
inv <= conv_std_logic_vector(1352,11);
logman <= conv_std_logic_vector(5545834,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000101" =>
inv <= conv_std_logic_vector(1348,11);
logman <= conv_std_logic_vector(5645255,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000110" =>
inv <= conv_std_logic_vector(1345,11);
logman <= conv_std_logic_vector(5720014,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000111" =>
inv <= conv_std_logic_vector(1341,11);
logman <= conv_std_logic_vector(5819953,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001000" =>
inv <= conv_std_logic_vector(1338,11);
logman <= conv_std_logic_vector(5895103,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001001" =>
inv <= conv_std_logic_vector(1335,11);
logman <= conv_std_logic_vector(5970421,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001010" =>
inv <= conv_std_logic_vector(1331,11);
logman <= conv_std_logic_vector(6071110,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001011" =>
inv <= conv_std_logic_vector(1328,11);
logman <= conv_std_logic_vector(6146825,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001100" =>
inv <= conv_std_logic_vector(1324,11);
logman <= conv_std_logic_vector(6248045,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001101" =>
inv <= conv_std_logic_vector(1321,11);
logman <= conv_std_logic_vector(6324161,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001110" =>
inv <= conv_std_logic_vector(1318,11);
logman <= conv_std_logic_vector(6400450,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001111" =>
inv <= conv_std_logic_vector(1315,11);
logman <= conv_std_logic_vector(6476913,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010000" =>
inv <= conv_std_logic_vector(1311,11);
logman <= conv_std_logic_vector(6579135,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010001" =>
inv <= conv_std_logic_vector(1308,11);
logman <= conv_std_logic_vector(6656007,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010010" =>
inv <= conv_std_logic_vector(1305,11);
logman <= conv_std_logic_vector(6733055,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010011" =>
inv <= conv_std_logic_vector(1301,11);
logman <= conv_std_logic_vector(6836061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010100" =>
inv <= conv_std_logic_vector(1298,11);
logman <= conv_std_logic_vector(6913525,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010101" =>
inv <= conv_std_logic_vector(1295,11);
logman <= conv_std_logic_vector(6991167,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010110" =>
inv <= conv_std_logic_vector(1292,11);
logman <= conv_std_logic_vector(7068989,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010111" =>
inv <= conv_std_logic_vector(1289,11);
logman <= conv_std_logic_vector(7146993,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011000" =>
inv <= conv_std_logic_vector(1286,11);
logman <= conv_std_logic_vector(7225178,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011001" =>
inv <= conv_std_logic_vector(1282,11);
logman <= conv_std_logic_vector(7329709,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011010" =>
inv <= conv_std_logic_vector(1279,11);
logman <= conv_std_logic_vector(7408321,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011011" =>
inv <= conv_std_logic_vector(1276,11);
logman <= conv_std_logic_vector(7487119,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011100" =>
inv <= conv_std_logic_vector(1273,11);
logman <= conv_std_logic_vector(7566101,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011101" =>
inv <= conv_std_logic_vector(1270,11);
logman <= conv_std_logic_vector(7645270,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011110" =>
inv <= conv_std_logic_vector(1267,11);
logman <= conv_std_logic_vector(7724626,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011111" =>
inv <= conv_std_logic_vector(1264,11);
logman <= conv_std_logic_vector(7804171,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100000" =>
inv <= conv_std_logic_vector(1261,11);
logman <= conv_std_logic_vector(7883904,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100001" =>
inv <= conv_std_logic_vector(1258,11);
logman <= conv_std_logic_vector(7963827,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100010" =>
inv <= conv_std_logic_vector(1255,11);
logman <= conv_std_logic_vector(8043941,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100011" =>
inv <= conv_std_logic_vector(1252,11);
logman <= conv_std_logic_vector(8124247,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100100" =>
inv <= conv_std_logic_vector(1249,11);
logman <= conv_std_logic_vector(8204746,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100101" =>
inv <= conv_std_logic_vector(1246,11);
logman <= conv_std_logic_vector(8285438,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100110" =>
inv <= conv_std_logic_vector(1243,11);
logman <= conv_std_logic_vector(8366324,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100111" =>
inv <= conv_std_logic_vector(1240,11);
logman <= conv_std_logic_vector(29399,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101000" =>
inv <= conv_std_logic_vector(1237,11);
logman <= conv_std_logic_vector(70038,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101001" =>
inv <= conv_std_logic_vector(1234,11);
logman <= conv_std_logic_vector(110776,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101010" =>
inv <= conv_std_logic_vector(1231,11);
logman <= conv_std_logic_vector(151613,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101011" =>
inv <= conv_std_logic_vector(1228,11);
logman <= conv_std_logic_vector(192550,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101100" =>
inv <= conv_std_logic_vector(1225,11);
logman <= conv_std_logic_vector(233587,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101101" =>
inv <= conv_std_logic_vector(1223,11);
logman <= conv_std_logic_vector(261001,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101110" =>
inv <= conv_std_logic_vector(1220,11);
logman <= conv_std_logic_vector(302205,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101111" =>
inv <= conv_std_logic_vector(1217,11);
logman <= conv_std_logic_vector(343512,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110000" =>
inv <= conv_std_logic_vector(1214,11);
logman <= conv_std_logic_vector(384920,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110001" =>
inv <= conv_std_logic_vector(1211,11);
logman <= conv_std_logic_vector(426431,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110010" =>
inv <= conv_std_logic_vector(1209,11);
logman <= conv_std_logic_vector(454162,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110011" =>
inv <= conv_std_logic_vector(1206,11);
logman <= conv_std_logic_vector(495844,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110100" =>
inv <= conv_std_logic_vector(1203,11);
logman <= conv_std_logic_vector(537630,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110101" =>
inv <= conv_std_logic_vector(1200,11);
logman <= conv_std_logic_vector(579521,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110110" =>
inv <= conv_std_logic_vector(1198,11);
logman <= conv_std_logic_vector(607506,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110111" =>
inv <= conv_std_logic_vector(1195,11);
logman <= conv_std_logic_vector(649572,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111000" =>
inv <= conv_std_logic_vector(1192,11);
logman <= conv_std_logic_vector(691744,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111001" =>
inv <= conv_std_logic_vector(1189,11);
logman <= conv_std_logic_vector(734021,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111010" =>
inv <= conv_std_logic_vector(1187,11);
logman <= conv_std_logic_vector(762266,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111011" =>
inv <= conv_std_logic_vector(1184,11);
logman <= conv_std_logic_vector(804722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111100" =>
inv <= conv_std_logic_vector(1181,11);
logman <= conv_std_logic_vector(847286,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111101" =>
inv <= conv_std_logic_vector(1179,11);
logman <= conv_std_logic_vector(875722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111110" =>
inv <= conv_std_logic_vector(1176,11);
logman <= conv_std_logic_vector(918466,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111111" =>
inv <= conv_std_logic_vector(1173,11);
logman <= conv_std_logic_vector(961320,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000000" =>
inv <= conv_std_logic_vector(1171,11);
logman <= conv_std_logic_vector(989950,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000001" =>
inv <= conv_std_logic_vector(1168,11);
logman <= conv_std_logic_vector(1032987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000010" =>
inv <= conv_std_logic_vector(1166,11);
logman <= conv_std_logic_vector(1061740,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000011" =>
inv <= conv_std_logic_vector(1163,11);
logman <= conv_std_logic_vector(1104961,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000100" =>
inv <= conv_std_logic_vector(1160,11);
logman <= conv_std_logic_vector(1148295,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000101" =>
inv <= conv_std_logic_vector(1158,11);
logman <= conv_std_logic_vector(1177246,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000110" =>
inv <= conv_std_logic_vector(1155,11);
logman <= conv_std_logic_vector(1220767,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000111" =>
inv <= conv_std_logic_vector(1153,11);
logman <= conv_std_logic_vector(1249843,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001000" =>
inv <= conv_std_logic_vector(1150,11);
logman <= conv_std_logic_vector(1293553,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001001" =>
inv <= conv_std_logic_vector(1148,11);
logman <= conv_std_logic_vector(1322756,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001010" =>
inv <= conv_std_logic_vector(1145,11);
logman <= conv_std_logic_vector(1366656,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001011" =>
inv <= conv_std_logic_vector(1143,11);
logman <= conv_std_logic_vector(1395987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001100" =>
inv <= conv_std_logic_vector(1140,11);
logman <= conv_std_logic_vector(1440080,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001101" =>
inv <= conv_std_logic_vector(1138,11);
logman <= conv_std_logic_vector(1469539,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001110" =>
inv <= conv_std_logic_vector(1135,11);
logman <= conv_std_logic_vector(1513826,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001111" =>
inv <= conv_std_logic_vector(1133,11);
logman <= conv_std_logic_vector(1543415,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010000" =>
inv <= conv_std_logic_vector(1130,11);
logman <= conv_std_logic_vector(1587898,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010001" =>
inv <= conv_std_logic_vector(1128,11);
logman <= conv_std_logic_vector(1617618,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010010" =>
inv <= conv_std_logic_vector(1126,11);
logman <= conv_std_logic_vector(1647391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010011" =>
inv <= conv_std_logic_vector(1123,11);
logman <= conv_std_logic_vector(1692151,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010100" =>
inv <= conv_std_logic_vector(1121,11);
logman <= conv_std_logic_vector(1722056,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010101" =>
inv <= conv_std_logic_vector(1118,11);
logman <= conv_std_logic_vector(1767016,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010110" =>
inv <= conv_std_logic_vector(1116,11);
logman <= conv_std_logic_vector(1797055,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010111" =>
inv <= conv_std_logic_vector(1114,11);
logman <= conv_std_logic_vector(1827149,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011000" =>
inv <= conv_std_logic_vector(1111,11);
logman <= conv_std_logic_vector(1872391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011001" =>
inv <= conv_std_logic_vector(1109,11);
logman <= conv_std_logic_vector(1902620,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011010" =>
inv <= conv_std_logic_vector(1107,11);
logman <= conv_std_logic_vector(1932904,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011011" =>
inv <= conv_std_logic_vector(1104,11);
logman <= conv_std_logic_vector(1978432,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011100" =>
inv <= conv_std_logic_vector(1102,11);
logman <= conv_std_logic_vector(2008853,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011101" =>
inv <= conv_std_logic_vector(1100,11);
logman <= conv_std_logic_vector(2039330,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011110" =>
inv <= conv_std_logic_vector(1097,11);
logman <= conv_std_logic_vector(2085148,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011111" =>
inv <= conv_std_logic_vector(1095,11);
logman <= conv_std_logic_vector(2115764,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100000" =>
inv <= conv_std_logic_vector(1093,11);
logman <= conv_std_logic_vector(2146435,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100001" =>
inv <= conv_std_logic_vector(1090,11);
logman <= conv_std_logic_vector(2192547,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100010" =>
inv <= conv_std_logic_vector(1088,11);
logman <= conv_std_logic_vector(2223360,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100011" =>
inv <= conv_std_logic_vector(1086,11);
logman <= conv_std_logic_vector(2254228,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100100" =>
inv <= conv_std_logic_vector(1084,11);
logman <= conv_std_logic_vector(2285154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100101" =>
inv <= conv_std_logic_vector(1082,11);
logman <= conv_std_logic_vector(2316137,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100110" =>
inv <= conv_std_logic_vector(1079,11);
logman <= conv_std_logic_vector(2362719,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100111" =>
inv <= conv_std_logic_vector(1077,11);
logman <= conv_std_logic_vector(2393845,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101000" =>
inv <= conv_std_logic_vector(1075,11);
logman <= conv_std_logic_vector(2425030,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101001" =>
inv <= conv_std_logic_vector(1073,11);
logman <= conv_std_logic_vector(2456272,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101010" =>
inv <= conv_std_logic_vector(1070,11);
logman <= conv_std_logic_vector(2503245,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101011" =>
inv <= conv_std_logic_vector(1068,11);
logman <= conv_std_logic_vector(2534634,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101100" =>
inv <= conv_std_logic_vector(1066,11);
logman <= conv_std_logic_vector(2566082,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101101" =>
inv <= conv_std_logic_vector(1064,11);
logman <= conv_std_logic_vector(2597588,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101110" =>
inv <= conv_std_logic_vector(1062,11);
logman <= conv_std_logic_vector(2629154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101111" =>
inv <= conv_std_logic_vector(1060,11);
logman <= conv_std_logic_vector(2660779,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110000" =>
inv <= conv_std_logic_vector(1058,11);
logman <= conv_std_logic_vector(2692464,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110001" =>
inv <= conv_std_logic_vector(1055,11);
logman <= conv_std_logic_vector(2740104,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110010" =>
inv <= conv_std_logic_vector(1053,11);
logman <= conv_std_logic_vector(2771940,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110011" =>
inv <= conv_std_logic_vector(1051,11);
logman <= conv_std_logic_vector(2803835,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110100" =>
inv <= conv_std_logic_vector(1049,11);
logman <= conv_std_logic_vector(2835792,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110101" =>
inv <= conv_std_logic_vector(1047,11);
logman <= conv_std_logic_vector(2867810,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110110" =>
inv <= conv_std_logic_vector(1045,11);
logman <= conv_std_logic_vector(2899888,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110111" =>
inv <= conv_std_logic_vector(1043,11);
logman <= conv_std_logic_vector(2932029,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111000" =>
inv <= conv_std_logic_vector(1041,11);
logman <= conv_std_logic_vector(2964231,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111001" =>
inv <= conv_std_logic_vector(1039,11);
logman <= conv_std_logic_vector(2996495,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111010" =>
inv <= conv_std_logic_vector(1037,11);
logman <= conv_std_logic_vector(3028821,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111011" =>
inv <= conv_std_logic_vector(1035,11);
logman <= conv_std_logic_vector(3061209,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111100" =>
inv <= conv_std_logic_vector(1033,11);
logman <= conv_std_logic_vector(3093660,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111101" =>
inv <= conv_std_logic_vector(1031,11);
logman <= conv_std_logic_vector(3126174,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111110" =>
inv <= conv_std_logic_vector(1029,11);
logman <= conv_std_logic_vector(3158751,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111111" =>
inv <= conv_std_logic_vector(1027,11);
logman <= conv_std_logic_vector(3191392,23);
logexp <= conv_std_logic_vector(126,8);
WHEN others =>
inv <= conv_std_logic_vector(0,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlut8 IS
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlut8;
ARCHITECTURE rtl OF fp_lnlut8 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "00000000" =>
inv <= conv_std_logic_vector(1024,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "00000001" =>
inv <= conv_std_logic_vector(2041,11);
logman <= conv_std_logic_vector(6316601,23);
logexp <= conv_std_logic_vector(118,8);
WHEN "00000010" =>
inv <= conv_std_logic_vector(2033,11);
logman <= conv_std_logic_vector(7397915,23);
logexp <= conv_std_logic_vector(119,8);
WHEN "00000011" =>
inv <= conv_std_logic_vector(2025,11);
logman <= conv_std_logic_vector(3738239,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000100" =>
inv <= conv_std_logic_vector(2017,11);
logman <= conv_std_logic_vector(7988584,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000101" =>
inv <= conv_std_logic_vector(2009,11);
logman <= conv_std_logic_vector(1933606,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000110" =>
inv <= conv_std_logic_vector(2002,11);
logman <= conv_std_logic_vector(3807503,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000111" =>
inv <= conv_std_logic_vector(1994,11);
logman <= conv_std_logic_vector(5957139,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001000" =>
inv <= conv_std_logic_vector(1986,11);
logman <= conv_std_logic_vector(8115417,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001001" =>
inv <= conv_std_logic_vector(1979,11);
logman <= conv_std_logic_vector(811223,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001010" =>
inv <= conv_std_logic_vector(1972,11);
logman <= conv_std_logic_vector(1762400,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001011" =>
inv <= conv_std_logic_vector(1964,11);
logman <= conv_std_logic_vector(2853602,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001100" =>
inv <= conv_std_logic_vector(1957,11);
logman <= conv_std_logic_vector(3812057,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001101" =>
inv <= conv_std_logic_vector(1950,11);
logman <= conv_std_logic_vector(4773946,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001110" =>
inv <= conv_std_logic_vector(1942,11);
logman <= conv_std_logic_vector(5877485,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001111" =>
inv <= conv_std_logic_vector(1935,11);
logman <= conv_std_logic_vector(6846817,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010000" =>
inv <= conv_std_logic_vector(1928,11);
logman <= conv_std_logic_vector(7819662,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010001" =>
inv <= conv_std_logic_vector(1921,11);
logman <= conv_std_logic_vector(203719,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010010" =>
inv <= conv_std_logic_vector(1914,11);
logman <= conv_std_logic_vector(693693,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010011" =>
inv <= conv_std_logic_vector(1907,11);
logman <= conv_std_logic_vector(1185462,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010100" =>
inv <= conv_std_logic_vector(1900,11);
logman <= conv_std_logic_vector(1679040,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010101" =>
inv <= conv_std_logic_vector(1893,11);
logman <= conv_std_logic_vector(2174439,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010110" =>
inv <= conv_std_logic_vector(1886,11);
logman <= conv_std_logic_vector(2671674,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010111" =>
inv <= conv_std_logic_vector(1880,11);
logman <= conv_std_logic_vector(3099346,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011000" =>
inv <= conv_std_logic_vector(1873,11);
logman <= conv_std_logic_vector(3600026,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011001" =>
inv <= conv_std_logic_vector(1866,11);
logman <= conv_std_logic_vector(4102580,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011010" =>
inv <= conv_std_logic_vector(1860,11);
logman <= conv_std_logic_vector(4534844,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011011" =>
inv <= conv_std_logic_vector(1853,11);
logman <= conv_std_logic_vector(5040917,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011100" =>
inv <= conv_std_logic_vector(1847,11);
logman <= conv_std_logic_vector(5476218,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011101" =>
inv <= conv_std_logic_vector(1840,11);
logman <= conv_std_logic_vector(5985860,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011110" =>
inv <= conv_std_logic_vector(1834,11);
logman <= conv_std_logic_vector(6424242,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011111" =>
inv <= conv_std_logic_vector(1827,11);
logman <= conv_std_logic_vector(6937504,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100000" =>
inv <= conv_std_logic_vector(1821,11);
logman <= conv_std_logic_vector(7379010,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100001" =>
inv <= conv_std_logic_vector(1815,11);
logman <= conv_std_logic_vector(7821973,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100010" =>
inv <= conv_std_logic_vector(1808,11);
logman <= conv_std_logic_vector(8340618,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100011" =>
inv <= conv_std_logic_vector(1802,11);
logman <= conv_std_logic_vector(199082,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100100" =>
inv <= conv_std_logic_vector(1796,11);
logman <= conv_std_logic_vector(422902,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100101" =>
inv <= conv_std_logic_vector(1790,11);
logman <= conv_std_logic_vector(647472,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100110" =>
inv <= conv_std_logic_vector(1784,11);
logman <= conv_std_logic_vector(872796,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100111" =>
inv <= conv_std_logic_vector(1778,11);
logman <= conv_std_logic_vector(1098879,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101000" =>
inv <= conv_std_logic_vector(1772,11);
logman <= conv_std_logic_vector(1325726,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101001" =>
inv <= conv_std_logic_vector(1766,11);
logman <= conv_std_logic_vector(1553342,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101010" =>
inv <= conv_std_logic_vector(1760,11);
logman <= conv_std_logic_vector(1781734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101011" =>
inv <= conv_std_logic_vector(1754,11);
logman <= conv_std_logic_vector(2010905,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101100" =>
inv <= conv_std_logic_vector(1748,11);
logman <= conv_std_logic_vector(2240861,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101101" =>
inv <= conv_std_logic_vector(1742,11);
logman <= conv_std_logic_vector(2471608,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101110" =>
inv <= conv_std_logic_vector(1737,11);
logman <= conv_std_logic_vector(2664505,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101111" =>
inv <= conv_std_logic_vector(1731,11);
logman <= conv_std_logic_vector(2896716,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110000" =>
inv <= conv_std_logic_vector(1725,11);
logman <= conv_std_logic_vector(3129733,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110001" =>
inv <= conv_std_logic_vector(1719,11);
logman <= conv_std_logic_vector(3363562,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110010" =>
inv <= conv_std_logic_vector(1714,11);
logman <= conv_std_logic_vector(3559044,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110011" =>
inv <= conv_std_logic_vector(1708,11);
logman <= conv_std_logic_vector(3794376,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110100" =>
inv <= conv_std_logic_vector(1703,11);
logman <= conv_std_logic_vector(3991119,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110101" =>
inv <= conv_std_logic_vector(1697,11);
logman <= conv_std_logic_vector(4227974,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110110" =>
inv <= conv_std_logic_vector(1692,11);
logman <= conv_std_logic_vector(4425994,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110111" =>
inv <= conv_std_logic_vector(1686,11);
logman <= conv_std_logic_vector(4664391,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111000" =>
inv <= conv_std_logic_vector(1681,11);
logman <= conv_std_logic_vector(4863705,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111001" =>
inv <= conv_std_logic_vector(1676,11);
logman <= conv_std_logic_vector(5063612,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111010" =>
inv <= conv_std_logic_vector(1670,11);
logman <= conv_std_logic_vector(5304290,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111011" =>
inv <= conv_std_logic_vector(1665,11);
logman <= conv_std_logic_vector(5505516,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111100" =>
inv <= conv_std_logic_vector(1660,11);
logman <= conv_std_logic_vector(5707347,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111101" =>
inv <= conv_std_logic_vector(1654,11);
logman <= conv_std_logic_vector(5950349,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111110" =>
inv <= conv_std_logic_vector(1649,11);
logman <= conv_std_logic_vector(6153525,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111111" =>
inv <= conv_std_logic_vector(1644,11);
logman <= conv_std_logic_vector(6357317,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000000" =>
inv <= conv_std_logic_vector(1639,11);
logman <= conv_std_logic_vector(6561731,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000001" =>
inv <= conv_std_logic_vector(1634,11);
logman <= conv_std_logic_vector(6766769,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000010" =>
inv <= conv_std_logic_vector(1629,11);
logman <= conv_std_logic_vector(6972435,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000011" =>
inv <= conv_std_logic_vector(1624,11);
logman <= conv_std_logic_vector(7178734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000100" =>
inv <= conv_std_logic_vector(1619,11);
logman <= conv_std_logic_vector(7385668,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000101" =>
inv <= conv_std_logic_vector(1614,11);
logman <= conv_std_logic_vector(7593243,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000110" =>
inv <= conv_std_logic_vector(1609,11);
logman <= conv_std_logic_vector(7801462,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000111" =>
inv <= conv_std_logic_vector(1604,11);
logman <= conv_std_logic_vector(8010329,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001000" =>
inv <= conv_std_logic_vector(1599,11);
logman <= conv_std_logic_vector(8219848,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001001" =>
inv <= conv_std_logic_vector(1594,11);
logman <= conv_std_logic_vector(20707,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001010" =>
inv <= conv_std_logic_vector(1589,11);
logman <= conv_std_logic_vector(126125,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001011" =>
inv <= conv_std_logic_vector(1584,11);
logman <= conv_std_logic_vector(231875,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001100" =>
inv <= conv_std_logic_vector(1580,11);
logman <= conv_std_logic_vector(316716,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001101" =>
inv <= conv_std_logic_vector(1575,11);
logman <= conv_std_logic_vector(423069,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001110" =>
inv <= conv_std_logic_vector(1570,11);
logman <= conv_std_logic_vector(529760,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001111" =>
inv <= conv_std_logic_vector(1566,11);
logman <= conv_std_logic_vector(615358,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010000" =>
inv <= conv_std_logic_vector(1561,11);
logman <= conv_std_logic_vector(722664,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010001" =>
inv <= conv_std_logic_vector(1556,11);
logman <= conv_std_logic_vector(830314,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010010" =>
inv <= conv_std_logic_vector(1552,11);
logman <= conv_std_logic_vector(916683,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010011" =>
inv <= conv_std_logic_vector(1547,11);
logman <= conv_std_logic_vector(1024958,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010100" =>
inv <= conv_std_logic_vector(1543,11);
logman <= conv_std_logic_vector(1111831,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010101" =>
inv <= conv_std_logic_vector(1538,11);
logman <= conv_std_logic_vector(1220738,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010110" =>
inv <= conv_std_logic_vector(1534,11);
logman <= conv_std_logic_vector(1308120,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010111" =>
inv <= conv_std_logic_vector(1529,11);
logman <= conv_std_logic_vector(1417667,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011000" =>
inv <= conv_std_logic_vector(1525,11);
logman <= conv_std_logic_vector(1505564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011001" =>
inv <= conv_std_logic_vector(1520,11);
logman <= conv_std_logic_vector(1615759,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011010" =>
inv <= conv_std_logic_vector(1516,11);
logman <= conv_std_logic_vector(1704177,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011011" =>
inv <= conv_std_logic_vector(1511,11);
logman <= conv_std_logic_vector(1815027,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011100" =>
inv <= conv_std_logic_vector(1507,11);
logman <= conv_std_logic_vector(1903972,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011101" =>
inv <= conv_std_logic_vector(1503,11);
logman <= conv_std_logic_vector(1993153,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011110" =>
inv <= conv_std_logic_vector(1498,11);
logman <= conv_std_logic_vector(2104964,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011111" =>
inv <= conv_std_logic_vector(1494,11);
logman <= conv_std_logic_vector(2194682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100000" =>
inv <= conv_std_logic_vector(1490,11);
logman <= conv_std_logic_vector(2284640,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100001" =>
inv <= conv_std_logic_vector(1486,11);
logman <= conv_std_logic_vector(2374840,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100010" =>
inv <= conv_std_logic_vector(1482,11);
logman <= conv_std_logic_vector(2465284,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100011" =>
inv <= conv_std_logic_vector(1477,11);
logman <= conv_std_logic_vector(2578682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100100" =>
inv <= conv_std_logic_vector(1473,11);
logman <= conv_std_logic_vector(2669677,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100101" =>
inv <= conv_std_logic_vector(1469,11);
logman <= conv_std_logic_vector(2760919,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100110" =>
inv <= conv_std_logic_vector(1465,11);
logman <= conv_std_logic_vector(2852411,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100111" =>
inv <= conv_std_logic_vector(1461,11);
logman <= conv_std_logic_vector(2944152,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101000" =>
inv <= conv_std_logic_vector(1457,11);
logman <= conv_std_logic_vector(3036145,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101001" =>
inv <= conv_std_logic_vector(1453,11);
logman <= conv_std_logic_vector(3128391,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101010" =>
inv <= conv_std_logic_vector(1449,11);
logman <= conv_std_logic_vector(3220891,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101011" =>
inv <= conv_std_logic_vector(1445,11);
logman <= conv_std_logic_vector(3313647,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101100" =>
inv <= conv_std_logic_vector(1441,11);
logman <= conv_std_logic_vector(3406660,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101101" =>
inv <= conv_std_logic_vector(1437,11);
logman <= conv_std_logic_vector(3499932,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101110" =>
inv <= conv_std_logic_vector(1433,11);
logman <= conv_std_logic_vector(3593464,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101111" =>
inv <= conv_std_logic_vector(1429,11);
logman <= conv_std_logic_vector(3687257,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110000" =>
inv <= conv_std_logic_vector(1425,11);
logman <= conv_std_logic_vector(3781312,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110001" =>
inv <= conv_std_logic_vector(1421,11);
logman <= conv_std_logic_vector(3875633,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110010" =>
inv <= conv_std_logic_vector(1417,11);
logman <= conv_std_logic_vector(3970219,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110011" =>
inv <= conv_std_logic_vector(1414,11);
logman <= conv_std_logic_vector(4041334,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110100" =>
inv <= conv_std_logic_vector(1410,11);
logman <= conv_std_logic_vector(4136389,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110101" =>
inv <= conv_std_logic_vector(1406,11);
logman <= conv_std_logic_vector(4231714,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110110" =>
inv <= conv_std_logic_vector(1402,11);
logman <= conv_std_logic_vector(4327311,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110111" =>
inv <= conv_std_logic_vector(1399,11);
logman <= conv_std_logic_vector(4399188,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111000" =>
inv <= conv_std_logic_vector(1395,11);
logman <= conv_std_logic_vector(4495263,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111001" =>
inv <= conv_std_logic_vector(1391,11);
logman <= conv_std_logic_vector(4591615,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111010" =>
inv <= conv_std_logic_vector(1388,11);
logman <= conv_std_logic_vector(4664061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111011" =>
inv <= conv_std_logic_vector(1384,11);
logman <= conv_std_logic_vector(4760899,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111100" =>
inv <= conv_std_logic_vector(1380,11);
logman <= conv_std_logic_vector(4858018,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111101" =>
inv <= conv_std_logic_vector(1377,11);
logman <= conv_std_logic_vector(4931041,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111110" =>
inv <= conv_std_logic_vector(1373,11);
logman <= conv_std_logic_vector(5028654,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111111" =>
inv <= conv_std_logic_vector(1369,11);
logman <= conv_std_logic_vector(5126552,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000000" =>
inv <= conv_std_logic_vector(1366,11);
logman <= conv_std_logic_vector(5200163,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000001" =>
inv <= conv_std_logic_vector(1362,11);
logman <= conv_std_logic_vector(5298564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000010" =>
inv <= conv_std_logic_vector(1359,11);
logman <= conv_std_logic_vector(5372554,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000011" =>
inv <= conv_std_logic_vector(1355,11);
logman <= conv_std_logic_vector(5471461,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000100" =>
inv <= conv_std_logic_vector(1352,11);
logman <= conv_std_logic_vector(5545834,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000101" =>
inv <= conv_std_logic_vector(1348,11);
logman <= conv_std_logic_vector(5645255,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000110" =>
inv <= conv_std_logic_vector(1345,11);
logman <= conv_std_logic_vector(5720014,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000111" =>
inv <= conv_std_logic_vector(1341,11);
logman <= conv_std_logic_vector(5819953,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001000" =>
inv <= conv_std_logic_vector(1338,11);
logman <= conv_std_logic_vector(5895103,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001001" =>
inv <= conv_std_logic_vector(1335,11);
logman <= conv_std_logic_vector(5970421,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001010" =>
inv <= conv_std_logic_vector(1331,11);
logman <= conv_std_logic_vector(6071110,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001011" =>
inv <= conv_std_logic_vector(1328,11);
logman <= conv_std_logic_vector(6146825,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001100" =>
inv <= conv_std_logic_vector(1324,11);
logman <= conv_std_logic_vector(6248045,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001101" =>
inv <= conv_std_logic_vector(1321,11);
logman <= conv_std_logic_vector(6324161,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001110" =>
inv <= conv_std_logic_vector(1318,11);
logman <= conv_std_logic_vector(6400450,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001111" =>
inv <= conv_std_logic_vector(1315,11);
logman <= conv_std_logic_vector(6476913,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010000" =>
inv <= conv_std_logic_vector(1311,11);
logman <= conv_std_logic_vector(6579135,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010001" =>
inv <= conv_std_logic_vector(1308,11);
logman <= conv_std_logic_vector(6656007,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010010" =>
inv <= conv_std_logic_vector(1305,11);
logman <= conv_std_logic_vector(6733055,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010011" =>
inv <= conv_std_logic_vector(1301,11);
logman <= conv_std_logic_vector(6836061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010100" =>
inv <= conv_std_logic_vector(1298,11);
logman <= conv_std_logic_vector(6913525,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010101" =>
inv <= conv_std_logic_vector(1295,11);
logman <= conv_std_logic_vector(6991167,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010110" =>
inv <= conv_std_logic_vector(1292,11);
logman <= conv_std_logic_vector(7068989,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010111" =>
inv <= conv_std_logic_vector(1289,11);
logman <= conv_std_logic_vector(7146993,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011000" =>
inv <= conv_std_logic_vector(1286,11);
logman <= conv_std_logic_vector(7225178,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011001" =>
inv <= conv_std_logic_vector(1282,11);
logman <= conv_std_logic_vector(7329709,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011010" =>
inv <= conv_std_logic_vector(1279,11);
logman <= conv_std_logic_vector(7408321,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011011" =>
inv <= conv_std_logic_vector(1276,11);
logman <= conv_std_logic_vector(7487119,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011100" =>
inv <= conv_std_logic_vector(1273,11);
logman <= conv_std_logic_vector(7566101,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011101" =>
inv <= conv_std_logic_vector(1270,11);
logman <= conv_std_logic_vector(7645270,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011110" =>
inv <= conv_std_logic_vector(1267,11);
logman <= conv_std_logic_vector(7724626,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011111" =>
inv <= conv_std_logic_vector(1264,11);
logman <= conv_std_logic_vector(7804171,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100000" =>
inv <= conv_std_logic_vector(1261,11);
logman <= conv_std_logic_vector(7883904,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100001" =>
inv <= conv_std_logic_vector(1258,11);
logman <= conv_std_logic_vector(7963827,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100010" =>
inv <= conv_std_logic_vector(1255,11);
logman <= conv_std_logic_vector(8043941,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100011" =>
inv <= conv_std_logic_vector(1252,11);
logman <= conv_std_logic_vector(8124247,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100100" =>
inv <= conv_std_logic_vector(1249,11);
logman <= conv_std_logic_vector(8204746,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100101" =>
inv <= conv_std_logic_vector(1246,11);
logman <= conv_std_logic_vector(8285438,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100110" =>
inv <= conv_std_logic_vector(1243,11);
logman <= conv_std_logic_vector(8366324,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100111" =>
inv <= conv_std_logic_vector(1240,11);
logman <= conv_std_logic_vector(29399,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101000" =>
inv <= conv_std_logic_vector(1237,11);
logman <= conv_std_logic_vector(70038,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101001" =>
inv <= conv_std_logic_vector(1234,11);
logman <= conv_std_logic_vector(110776,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101010" =>
inv <= conv_std_logic_vector(1231,11);
logman <= conv_std_logic_vector(151613,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101011" =>
inv <= conv_std_logic_vector(1228,11);
logman <= conv_std_logic_vector(192550,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101100" =>
inv <= conv_std_logic_vector(1225,11);
logman <= conv_std_logic_vector(233587,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101101" =>
inv <= conv_std_logic_vector(1223,11);
logman <= conv_std_logic_vector(261001,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101110" =>
inv <= conv_std_logic_vector(1220,11);
logman <= conv_std_logic_vector(302205,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101111" =>
inv <= conv_std_logic_vector(1217,11);
logman <= conv_std_logic_vector(343512,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110000" =>
inv <= conv_std_logic_vector(1214,11);
logman <= conv_std_logic_vector(384920,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110001" =>
inv <= conv_std_logic_vector(1211,11);
logman <= conv_std_logic_vector(426431,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110010" =>
inv <= conv_std_logic_vector(1209,11);
logman <= conv_std_logic_vector(454162,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110011" =>
inv <= conv_std_logic_vector(1206,11);
logman <= conv_std_logic_vector(495844,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110100" =>
inv <= conv_std_logic_vector(1203,11);
logman <= conv_std_logic_vector(537630,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110101" =>
inv <= conv_std_logic_vector(1200,11);
logman <= conv_std_logic_vector(579521,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110110" =>
inv <= conv_std_logic_vector(1198,11);
logman <= conv_std_logic_vector(607506,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110111" =>
inv <= conv_std_logic_vector(1195,11);
logman <= conv_std_logic_vector(649572,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111000" =>
inv <= conv_std_logic_vector(1192,11);
logman <= conv_std_logic_vector(691744,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111001" =>
inv <= conv_std_logic_vector(1189,11);
logman <= conv_std_logic_vector(734021,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111010" =>
inv <= conv_std_logic_vector(1187,11);
logman <= conv_std_logic_vector(762266,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111011" =>
inv <= conv_std_logic_vector(1184,11);
logman <= conv_std_logic_vector(804722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111100" =>
inv <= conv_std_logic_vector(1181,11);
logman <= conv_std_logic_vector(847286,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111101" =>
inv <= conv_std_logic_vector(1179,11);
logman <= conv_std_logic_vector(875722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111110" =>
inv <= conv_std_logic_vector(1176,11);
logman <= conv_std_logic_vector(918466,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111111" =>
inv <= conv_std_logic_vector(1173,11);
logman <= conv_std_logic_vector(961320,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000000" =>
inv <= conv_std_logic_vector(1171,11);
logman <= conv_std_logic_vector(989950,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000001" =>
inv <= conv_std_logic_vector(1168,11);
logman <= conv_std_logic_vector(1032987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000010" =>
inv <= conv_std_logic_vector(1166,11);
logman <= conv_std_logic_vector(1061740,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000011" =>
inv <= conv_std_logic_vector(1163,11);
logman <= conv_std_logic_vector(1104961,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000100" =>
inv <= conv_std_logic_vector(1160,11);
logman <= conv_std_logic_vector(1148295,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000101" =>
inv <= conv_std_logic_vector(1158,11);
logman <= conv_std_logic_vector(1177246,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000110" =>
inv <= conv_std_logic_vector(1155,11);
logman <= conv_std_logic_vector(1220767,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000111" =>
inv <= conv_std_logic_vector(1153,11);
logman <= conv_std_logic_vector(1249843,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001000" =>
inv <= conv_std_logic_vector(1150,11);
logman <= conv_std_logic_vector(1293553,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001001" =>
inv <= conv_std_logic_vector(1148,11);
logman <= conv_std_logic_vector(1322756,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001010" =>
inv <= conv_std_logic_vector(1145,11);
logman <= conv_std_logic_vector(1366656,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001011" =>
inv <= conv_std_logic_vector(1143,11);
logman <= conv_std_logic_vector(1395987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001100" =>
inv <= conv_std_logic_vector(1140,11);
logman <= conv_std_logic_vector(1440080,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001101" =>
inv <= conv_std_logic_vector(1138,11);
logman <= conv_std_logic_vector(1469539,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001110" =>
inv <= conv_std_logic_vector(1135,11);
logman <= conv_std_logic_vector(1513826,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001111" =>
inv <= conv_std_logic_vector(1133,11);
logman <= conv_std_logic_vector(1543415,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010000" =>
inv <= conv_std_logic_vector(1130,11);
logman <= conv_std_logic_vector(1587898,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010001" =>
inv <= conv_std_logic_vector(1128,11);
logman <= conv_std_logic_vector(1617618,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010010" =>
inv <= conv_std_logic_vector(1126,11);
logman <= conv_std_logic_vector(1647391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010011" =>
inv <= conv_std_logic_vector(1123,11);
logman <= conv_std_logic_vector(1692151,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010100" =>
inv <= conv_std_logic_vector(1121,11);
logman <= conv_std_logic_vector(1722056,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010101" =>
inv <= conv_std_logic_vector(1118,11);
logman <= conv_std_logic_vector(1767016,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010110" =>
inv <= conv_std_logic_vector(1116,11);
logman <= conv_std_logic_vector(1797055,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010111" =>
inv <= conv_std_logic_vector(1114,11);
logman <= conv_std_logic_vector(1827149,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011000" =>
inv <= conv_std_logic_vector(1111,11);
logman <= conv_std_logic_vector(1872391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011001" =>
inv <= conv_std_logic_vector(1109,11);
logman <= conv_std_logic_vector(1902620,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011010" =>
inv <= conv_std_logic_vector(1107,11);
logman <= conv_std_logic_vector(1932904,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011011" =>
inv <= conv_std_logic_vector(1104,11);
logman <= conv_std_logic_vector(1978432,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011100" =>
inv <= conv_std_logic_vector(1102,11);
logman <= conv_std_logic_vector(2008853,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011101" =>
inv <= conv_std_logic_vector(1100,11);
logman <= conv_std_logic_vector(2039330,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011110" =>
inv <= conv_std_logic_vector(1097,11);
logman <= conv_std_logic_vector(2085148,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011111" =>
inv <= conv_std_logic_vector(1095,11);
logman <= conv_std_logic_vector(2115764,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100000" =>
inv <= conv_std_logic_vector(1093,11);
logman <= conv_std_logic_vector(2146435,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100001" =>
inv <= conv_std_logic_vector(1090,11);
logman <= conv_std_logic_vector(2192547,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100010" =>
inv <= conv_std_logic_vector(1088,11);
logman <= conv_std_logic_vector(2223360,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100011" =>
inv <= conv_std_logic_vector(1086,11);
logman <= conv_std_logic_vector(2254228,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100100" =>
inv <= conv_std_logic_vector(1084,11);
logman <= conv_std_logic_vector(2285154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100101" =>
inv <= conv_std_logic_vector(1082,11);
logman <= conv_std_logic_vector(2316137,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100110" =>
inv <= conv_std_logic_vector(1079,11);
logman <= conv_std_logic_vector(2362719,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100111" =>
inv <= conv_std_logic_vector(1077,11);
logman <= conv_std_logic_vector(2393845,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101000" =>
inv <= conv_std_logic_vector(1075,11);
logman <= conv_std_logic_vector(2425030,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101001" =>
inv <= conv_std_logic_vector(1073,11);
logman <= conv_std_logic_vector(2456272,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101010" =>
inv <= conv_std_logic_vector(1070,11);
logman <= conv_std_logic_vector(2503245,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101011" =>
inv <= conv_std_logic_vector(1068,11);
logman <= conv_std_logic_vector(2534634,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101100" =>
inv <= conv_std_logic_vector(1066,11);
logman <= conv_std_logic_vector(2566082,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101101" =>
inv <= conv_std_logic_vector(1064,11);
logman <= conv_std_logic_vector(2597588,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101110" =>
inv <= conv_std_logic_vector(1062,11);
logman <= conv_std_logic_vector(2629154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101111" =>
inv <= conv_std_logic_vector(1060,11);
logman <= conv_std_logic_vector(2660779,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110000" =>
inv <= conv_std_logic_vector(1058,11);
logman <= conv_std_logic_vector(2692464,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110001" =>
inv <= conv_std_logic_vector(1055,11);
logman <= conv_std_logic_vector(2740104,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110010" =>
inv <= conv_std_logic_vector(1053,11);
logman <= conv_std_logic_vector(2771940,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110011" =>
inv <= conv_std_logic_vector(1051,11);
logman <= conv_std_logic_vector(2803835,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110100" =>
inv <= conv_std_logic_vector(1049,11);
logman <= conv_std_logic_vector(2835792,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110101" =>
inv <= conv_std_logic_vector(1047,11);
logman <= conv_std_logic_vector(2867810,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110110" =>
inv <= conv_std_logic_vector(1045,11);
logman <= conv_std_logic_vector(2899888,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110111" =>
inv <= conv_std_logic_vector(1043,11);
logman <= conv_std_logic_vector(2932029,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111000" =>
inv <= conv_std_logic_vector(1041,11);
logman <= conv_std_logic_vector(2964231,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111001" =>
inv <= conv_std_logic_vector(1039,11);
logman <= conv_std_logic_vector(2996495,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111010" =>
inv <= conv_std_logic_vector(1037,11);
logman <= conv_std_logic_vector(3028821,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111011" =>
inv <= conv_std_logic_vector(1035,11);
logman <= conv_std_logic_vector(3061209,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111100" =>
inv <= conv_std_logic_vector(1033,11);
logman <= conv_std_logic_vector(3093660,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111101" =>
inv <= conv_std_logic_vector(1031,11);
logman <= conv_std_logic_vector(3126174,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111110" =>
inv <= conv_std_logic_vector(1029,11);
logman <= conv_std_logic_vector(3158751,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111111" =>
inv <= conv_std_logic_vector(1027,11);
logman <= conv_std_logic_vector(3191392,23);
logexp <= conv_std_logic_vector(126,8);
WHEN others =>
inv <= conv_std_logic_vector(0,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013, Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.jtag.all;
use work.config.all;
entity bschain is
generic (tech: integer := CFG_FABTECH;
enable: integer range 0 to 1 := CFG_BOUNDSCAN_EN;
hzsup: integer range 0 to 1 := 1);
port (
-- Chain control signals
chain_tck : in std_ulogic;
chain_tckn : in std_ulogic;
chain_tdi : in std_ulogic;
chain_tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic;
bsupdi : in std_ulogic;
bsupdo : in std_ulogic;
bsdrive : in std_ulogic;
bshighz : in std_ulogic;
-- Pad-side signals
Presetn : in std_ulogic;
Pclksel : in std_logic_vector (1 downto 0);
Pclk : in std_ulogic;
Perrorn : out std_ulogic;
Paddress : out std_logic_vector(27 downto 0);
Pdatain : in std_logic_vector(31 downto 0);
Pdataout : out std_logic_vector(31 downto 0);
Pdataen : out std_logic_vector(31 downto 0);
Pcbin : in std_logic_vector(7 downto 0);
Pcbout : out std_logic_vector(7 downto 0);
Pcben : out std_logic_vector(7 downto 0);
Psdclk : out std_ulogic;
Psdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
Psdwen : out std_ulogic; -- sdram write enable
Psdrasn : out std_ulogic; -- sdram ras
Psdcasn : out std_ulogic; -- sdram cas
Psddqm : out std_logic_vector (3 downto 0); -- sdram dqm
Pdsutx : out std_ulogic; -- DSU tx data
Pdsurx : in std_ulogic; -- DSU rx data
Pdsuen : in std_ulogic;
Pdsubre : in std_ulogic;
Pdsuact : out std_ulogic;
Ptxd1 : out std_ulogic; -- UART1 tx data
Prxd1 : in std_ulogic; -- UART1 rx data
Ptxd2 : out std_ulogic; -- UART2 tx data
Prxd2 : in std_ulogic; -- UART2 rx data
Pramsn : out std_logic_vector (4 downto 0);
Pramoen : out std_logic_vector (4 downto 0);
Prwen : out std_logic_vector (3 downto 0);
Poen : out std_ulogic;
Pwriten : out std_ulogic;
Pread : out std_ulogic;
Piosn : out std_ulogic;
Promsn : out std_logic_vector (1 downto 0);
Pbrdyn : in std_ulogic;
Pbexcn : in std_ulogic;
Pwdogn : out std_ulogic;
Pgpioin : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Pgpioout : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Pgpioen : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Pprom32 : in std_ulogic;
Ppromedac : in std_ulogic;
Pspw_clksel : in std_logic_vector (1 downto 0);
Pspw_clk : in std_ulogic;
Pspw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_ten : out std_logic_vector(0 to CFG_SPW_NUM-1);
Plclk2x : in std_ulogic;
Plclk4x : in std_ulogic;
Plclkdis : out std_ulogic;
Plclklock : in std_ulogic;
Plock : out std_ulogic;
Proen : in std_ulogic;
Proout : out std_ulogic;
-- Core-side signals
Cresetn : out std_ulogic;
Cclksel : out std_logic_vector (1 downto 0);
Cclk : out std_ulogic;
Cerrorn : in std_ulogic;
Caddress : in std_logic_vector(27 downto 0);
Cdatain : out std_logic_vector(31 downto 0);
Cdataout : in std_logic_vector(31 downto 0);
Cdataen : in std_logic_vector(31 downto 0);
Ccbin : out std_logic_vector(7 downto 0);
Ccbout : in std_logic_vector(7 downto 0);
Ccben : in std_logic_vector(7 downto 0);
Csdclk : in std_ulogic;
Csdcsn : in std_logic_vector (1 downto 0); -- sdram chip select
Csdwen : in std_ulogic; -- sdram write enable
Csdrasn : in std_ulogic; -- sdram ras
Csdcasn : in std_ulogic; -- sdram cas
Csddqm : in std_logic_vector (3 downto 0); -- sdram dqm
Cdsutx : in std_ulogic; -- DSU tx data
Cdsurx : out std_ulogic; -- DSU rx data
Cdsuen : out std_ulogic;
Cdsubre : out std_ulogic;
Cdsuact : in std_ulogic;
Ctxd1 : in std_ulogic; -- UART1 tx data
Crxd1 : out std_ulogic; -- UART1 rx data
Ctxd2 : in std_ulogic; -- UART2 tx data
Crxd2 : out std_ulogic; -- UART2 rx data
Cramsn : in std_logic_vector (4 downto 0);
Cramoen : in std_logic_vector (4 downto 0);
Crwen : in std_logic_vector (3 downto 0);
Coen : in std_ulogic;
Cwriten : in std_ulogic;
Cread : in std_ulogic;
Ciosn : in std_ulogic;
Cromsn : in std_logic_vector (1 downto 0);
Cbrdyn : out std_ulogic;
Cbexcn : out std_ulogic;
Cwdogn : in std_ulogic;
Cgpioin : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Cgpioout : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Cgpioen : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Cprom32 : out std_ulogic;
Cpromedac : out std_ulogic;
Cspw_clksel : out std_logic_vector (1 downto 0);
Cspw_clk : out std_ulogic;
Cspw_rxd : out std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_rxs : out std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_txd : in std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_txs : in std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_ten : in std_logic_vector(0 to CFG_SPW_NUM-1);
Clclk2x : out std_ulogic;
Clclk4x : out std_ulogic;
Clclkdis : in std_ulogic;
Clclklock : out std_ulogic;
Clock : in std_ulogic;
Croen : out std_ulogic;
Croout : in std_ulogic
);
end;
architecture rtl of bschain is
signal sr1_tdi, sr1a_tdi, sr2a_tdi, sr2_tdi, sr3a_tdi, sr3_tdi, sr4_tdi: std_ulogic;
signal sr1i, sr1o: std_logic_vector(4 downto 0);
signal sr3i, sr3o: std_logic_vector(41 downto 0);
signal sr5i, sr5o: std_logic_vector(11+5*CFG_SPW_NUM downto 0);
begin
-----------------------------------------------------------------------------
-- Scan chain registers (note: adjust order to match pad ring)
sr1a: bscanregs
generic map (tech => tech, nsigs => sr1i'length, dirmask => 2#00001#, enable => enable)
port map (sr1i, sr1o, chain_tck, chain_tckn, sr1a_tdi, chain_tdo,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr1i <= Presetn & Pclksel & Pclk & Cerrorn;
Cresetn <= sr1o(4); Cclksel <= sr1o(3 downto 2);
Cclk <= sr1o(1); Perrorn <= sr1o(0);
sr1b: bscanregs
generic map (tech => tech, nsigs => Paddress'length, dirmask => 16#3FFFFFFF#, enable => enable)
port map (Caddress, Paddress, chain_tck, chain_tckn, sr1_tdi, sr1a_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr2a: bscanregsbd
generic map (tech => tech, nsigs => Pdataout'length, enable => enable, hzsup => hzsup)
port map (Pdataout, Pdataen, Pdatain, Cdataout, Cdataen, Cdatain,
chain_tck, chain_tckn, sr2a_tdi, sr1_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr2b: bscanregsbd
generic map (tech => tech, nsigs => Pcbout'length, enable => enable, hzsup => hzsup)
port map (Pcbout, Pcben, Pcbin, Ccbout, Ccben, Ccbin,
chain_tck, chain_tckn, sr2_tdi, sr2a_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr3a: bscanregs
generic map (tech => tech, nsigs => sr3i'length-30, dirmask => 2#11_11111111_10#, enable => enable)
port map (sr3i(sr3i'high downto 30), sr3o(sr3i'high downto 30), chain_tck, chain_tckn, sr3a_tdi, sr2_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr3b: bscanregs
generic map (tech => tech, nsigs => 30, dirmask => 2#001101_01111111_11111111_11111001#, enable => enable)
port map (sr3i(29 downto 0), sr3o(29 downto 0), chain_tck, chain_tckn, sr3_tdi, sr3a_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr3i(41 downto 30) <= Csdclk & Csdcsn & Csdwen & Csdrasn & Csdcasn &
Csddqm & Cdsutx & Pdsurx;
sr3i(29 downto 23) <= Pdsuen & Pdsubre & Cdsuact & Ctxd1 & Prxd1 & Ctxd2 & Prxd2;
sr3i(22 downto 9) <= Cramsn & Cramoen & Crwen;
sr3i(8 downto 0) <= Coen & Cwriten & Cread & Ciosn & Cromsn(1 downto 0) & Pbrdyn & Pbexcn & Cwdogn;
Psdclk <= sr3o(41); Psdcsn <= sr3o(40 downto 39); Psdwen <= sr3o(38);
Psdrasn <= sr3o(37); Psdcasn <= sr3o(36); Psddqm <= sr3o(35 downto 32);
Pdsutx <= sr3o(31); Cdsurx <= sr3o(30); Cdsuen <= sr3o(29);
Cdsubre <= sr3o(28); Pdsuact <= sr3o(27); Ptxd1 <= sr3o(26);
Crxd1 <= sr3o(25); Ptxd2 <= sr3o(24); Crxd2 <= sr3o(23);
Pramsn <= sr3o(22 downto 18); Pramoen <= sr3o(17 downto 13); Prwen <= sr3o(12 downto 9);
Poen <= sr3o(8); Pwriten <= sr3o(7); Pread <= sr3o(6);
Piosn <= sr3o(5); Promsn <= sr3o(4 downto 3); Cbrdyn <= sr3o(2);
Cbexcn <= sr3o(1); Pwdogn <= sr3o(0);
sr4: bscanregsbd
generic map (tech => tech, nsigs => Pgpioin'length, enable => enable, hzsup => hzsup)
port map (Pgpioout, Pgpioen, Pgpioin, Cgpioout, Cgpioen, Cgpioin,
chain_tck, chain_tckn, sr4_tdi, sr3_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr5: bscanregs
generic map (tech => tech, nsigs => sr5i'length, dirmask => 2#00000011_10010101#, enable => enable)
port map (sr5i, sr5o, chain_tck, chain_tckn, chain_tdi, sr4_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr5i <= Pprom32 & Ppromedac & Pspw_clksel & Pspw_clk & Pspw_rxd & Pspw_rxs &
Cspw_txd & Cspw_txs & Cspw_ten & Plclk2x & Plclk4x &
Clclkdis & Plclklock & Clock & Proen & Croout;
Cprom32 <= sr5o(11+5*CFG_SPW_NUM);
Cpromedac <= sr5o(10+5*CFG_SPW_NUM);
Cspw_clksel <= sr5o(9+5*CFG_SPW_NUM downto 8+5*CFG_SPW_NUM);
Cspw_clk <= sr5o(7+5*CFG_SPW_NUM);
Cspw_rxd <= sr5o(6+5*CFG_SPW_NUM downto 7+4*CFG_SPW_NUM);
Cspw_rxs <= sr5o(6+4*CFG_SPW_NUM downto 7+3*CFG_SPW_NUM);
Pspw_txd <= sr5o(6+3*CFG_SPW_NUM downto 7+2*CFG_SPW_NUM);
Pspw_txs <= sr5o(6+2*CFG_SPW_NUM downto 7+CFG_SPW_NUM);
Pspw_ten <= sr5o(6+CFG_SPW_NUM downto 7);
Clclk2x <= sr5o(6);
Clclk4x <= sr5o(5);
Plclkdis <= sr5o(4);
Clclklock <= sr5o(3);
Plock <= sr5o(2);
Croen <= sr5o(1);
Proout <= sr5o(0);
end;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
entity decod7seg is
port (C: in std_logic_vector(4 downto 0);
F: out std_logic_vector(6 downto 0)
);
end decod7seg;
architecture decod7seg_estr of decod7seg is
begin
F <= "1000000" when C = "00000" else--0--O
"1111001" when C = "00001" else--1--I
"0100100" when C = "00010" else--2--Z
"0110000" when C = "00011" else--3
"0011001" when C = "00100" else--4
"0010010" when C = "00101" else--5--S
"0000010" when C = "00110" else--6
"1111000" when C = "00111" else--7
"0000000" when C = "01000" else--8
"0010000" when C = "01001" else--9--g
"0001000" when C = "01010" else--A
"0000011" when C = "01011" else--b
"1000110" when C = "01100" else--C
"0100001" when C = "01101" else--d
"0000110" when C = "01110" else--E
"0001110" when C = "01111" else--F
"0001001" when C = "10000" else--H--X
"1100001" when C = "10001" else--J
"0000101" when C = "10010" else--K
"1000111" when C = "10011" else--L
"0100011" when C = "10100" else--m
"1001000" when C = "10101" else--n
"0001100" when C = "10110" else--P
"0011000" when C = "10111" else--q
"0101111" when C = "11000" else--r
"0000111" when C = "11001" else--t
"1000001" when C = "11010" else--U--V
"0101011" when C = "11011" else--W
"0010001" when C = "11100" else--Y
"1111111";--espaço
end decod7seg_estr; |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH
);
port (
clk : in std_ulogic; -- FPGA main clock input
-- Buttons & LEDs
btnCpuResetn : in std_ulogic; -- Reset button
Led : out std_logic_vector(15 downto 0);
-- Onboard Cellular RAM
RamOE : out std_ulogic;
RamWE : out std_ulogic;
RamAdv : out std_ulogic;
RamCE : out std_ulogic;
RamClk : out std_ulogic;
RamCRE : out std_ulogic;
RamLB : out std_ulogic;
RamUB : out std_ulogic;
address : out std_logic_vector(22 downto 0);
data : inout std_logic_vector(15 downto 0);
-- USB-RS232 interface
RsRx : in std_logic;
RsTx : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
-- Memory controler signals
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
-- AMBA bus signals
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to 0);
signal irqo : irq_out_vector(0 to 0);
signal dbgi : l3_debug_in_vector(0 to 0);
signal dbgo : l3_debug_out_vector(0 to 0);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ndsuact : std_ulogic;
signal gpti : gptimer_in_type;
signal clkm, rstn : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart (unconnected)
signal rxd1 : std_logic;
signal txd1 : std_logic;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkm : signal is true;
constant clock_mult : integer := 10; -- Clock multiplier
constant clock_div : integer := 20; -- Clock divider
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * clock_mult / clock_div; -- CPU freq in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 0)
port map (btnCpuResetn, clkm, lock, rstn, rstraw);
lock <= cgo.clklock;
-- clock generator
clkgen0 : clkgen
generic map (fabtech, clock_mult, clock_div, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (clk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (ioen => 1, nahbm => 4, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
u0 : leon3s
generic map (hindex=>0, fabtech=>fabtech, memtech=>memtech, dsu=>1, fpu=>0, v8=>2,
mac=>0, isetsize=>8, dsetsize=>8,icen=>1, dcen=>1,tbuf=>2)
port map (clkm, rstn, ahbmi, ahbmo(0), ahbsi, ahbso, irqi(0), irqo(0), dbgi(0), dbgo(0));
-- LEON3 Debug Support Unit
dsu0 : dsu3
generic map (hindex => 2, ncpu => 1, tech => memtech, irq => 0, kbytes => 2)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
-- Debug UART
dcom0 : ahbuart
generic map (hindex => 1, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(1));
dsurx_pad : inpad generic map (tech => padtech) port map (RsRx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (RsTx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => 3)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(3),
open, open, open, open, open, open, open, gnd);
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0, rommask => 0,
iomask => 0, ram8 => 0, ram16 => 1,srbanks=>1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "01"; -- Sets data bus width for PROM accesses.
-- Bidirectional data bus
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(23 downto 16),
memo.bdrive(1), memi.data(23 downto 16));
bdr2 : iopadv generic map (tech => padtech, width => 8)
port map (data(15 downto 8), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
-- Out signals to memory
addr_pad : outpadv generic map (tech => padtech, width => 23) -- Address bus
port map (address, memo.address(23 downto 1));
oen_pad : outpad generic map (tech => padtech) -- Output Enable
port map (RamOE, memo.oen);
cs_pad : outpad generic map (tech => padtech) -- SRAM Chip select
port map (RamCE, memo.ramsn(0));
lb_pad : outpad generic map (tech => padtech)
port map (RamLB, memo.mben(0));
ub_pad : outpad generic map (tech => padtech)
port map (RamUB, memo.mben(1));
wri_pad : outpad generic map (tech => padtech) -- Write enable
port map (RamWE, memo.writen);
RamCRE <= '0'; -- Special SRAM signals specific
RamClk <= '0'; -- to Nexys4 board
RamAdv <= '0';
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- APB Bridge
generic map (hindex => 1, haddr => 16#800#)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
irqctrl0 : irqmp -- Interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => 1)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
timer0 : gptimer -- Time Unit
generic map (pindex => 3, paddr => 3, pirq => 8,
sepirq => 1, ntimers => 2)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => 1)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
--pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
|
---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity eth_dma is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic; --enable receive DMA
select_eth : in std_logic;
rec_isr : out std_logic; --data received
send_isr : out std_logic; --transmit done
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector( 3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector( 3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end; --entity eth_dma
architecture logic of eth_dma is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal rec_data : std_logic_vector(27 downto 0);
signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
signal rec_words : std_logic_vector(13 downto 0);
signal rec_dma : std_logic_vector(1 downto 0); --active & request
signal rec_done : std_logic;
signal send_clk : std_logic_vector(1 downto 0); --transmit
signal send_read : std_logic_vector(31 downto 0); --from DDR
signal send_data : std_logic_vector(31 downto 0);
signal send_cnt : std_logic_vector(2 downto 0); --nibbles
signal send_words : std_logic_vector(8 downto 0);
signal send_level : std_logic_vector(8 downto 0);
signal send_dma : std_logic_vector(1 downto 0); --active & request
signal send_enable: std_logic;
begin --architecture
dma_proc: process(clk, reset, enable_eth, select_eth,
data_read, pause_in, mem_address, mem_byte_we, data_w,
E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
rec_clk, rec_store, rec_data,
rec_cnt, rec_words, rec_dma, rec_done,
send_clk, send_read, send_data, send_cnt, send_words,
send_level, send_dma, send_enable)
begin
if reset = '1' then
rec_clk <= "00";
rec_cnt <= "000";
rec_words <= ZERO(13 downto 0);
rec_dma <= "00";
rec_done <= '0';
send_clk <= "00";
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= ZERO(8 downto 0);
send_dma <= "00";
send_enable <= '0';
elsif rising_edge(clk) then
--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
rec_clk <= rec_clk(0) & E_RX_CLK;
if rec_clk = "01" and enable_eth = '1' then
if E_RX_DV = '1' or rec_cnt /= "000" then
if rec_cnt = "111" then
rec_store <= rec_data & E_RXD;
rec_dma(0) <= '1'; --request DMA
end if;
rec_data <= rec_data(23 downto 0) & E_RXD;
rec_cnt <= rec_cnt + 1;
end if;
end if;
--Set transmit count or clear receive interrupt
if select_eth = '1' then
if mem_byte_we /= "0000" then
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= data_w(8 downto 0);
send_dma(0) <= '1';
else
rec_done <= '0';
end if;
end if;
--Transmit nibble on low->high E_TX_CLK. Get 32 bits from DDR.
send_clk <= send_clk(0) & E_TX_CLK;
if send_clk = "01" then
if send_cnt = "111" then
if send_words /= send_level then
send_data <= send_read;
send_dma(0) <= '1';
send_enable <= '1';
else
send_enable <= '0';
end if;
else
send_data(31 downto 4) <= send_data(27 downto 0);
end if;
send_cnt <= send_cnt + 1;
end if;
--Pick which type of DMA operation: bit0 = request; bit1 = active
if pause_in = '0' then
if rec_dma(1) = '1' then
rec_dma <= "00"; --DMA done
rec_words <= rec_words + 1;
if E_RX_DV = '0' then
rec_done <= '1';
end if;
elsif send_dma(1) = '1' then
send_dma <= "00";
send_words <= send_words + 1;
send_read <= data_read;
elsif rec_dma(0) = '1' then
rec_dma(1) <= '1'; --start DMA
elsif send_dma(0) = '1' then
send_dma(1) <= '1'; --start DMA
end if;
end if;
end if; --rising_edge(clk)
E_TXD <= send_data(31 downto 28);
E_TX_EN <= send_enable;
rec_isr <= rec_done;
if send_words = send_level then
send_isr <= '1';
else
send_isr <= '0';
end if;
if rec_dma(1) = '1' then
address <= "0001001111111111" & rec_words; --0x13ff0000
byte_we <= "1111";
data_write <= rec_store;
pause_out <= '1'; --to CPU
elsif send_dma(1) = '1' then
address <= "000100111111111000000" & send_words; --0x13fe0000
byte_we <= "0000";
data_write <= data_w;
pause_out <= '1';
else
address <= mem_address; --Send request from CPU to DDR
byte_we <= mem_byte_we;
data_write <= data_w;
pause_out <= '0';
end if;
end process;
end; --architecture logic
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF2_4_block5.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block5
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_4_block5 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_13 : IN std_logic; -- ufix1
dout_13_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_13_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block5;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block5 IS
-- Signals
SIGNAL dout_13_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_13_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_15_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_15_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_13_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_13_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_14_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_14_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
dout_13_re_signed <= signed(dout_13_re);
dout_13_im_signed <= signed(dout_13_im);
dout_15_re_signed <= signed(dout_15_re);
dout_15_im_signed <= signed(dout_15_im);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, dout_13_re_signed, dout_13_im_signed,
dout_15_re_signed, dout_15_im_signed, dout_1_vld, rotate_13)
VARIABLE add_cast : signed(16 DOWNTO 0);
VARIABLE add_cast_0 : signed(16 DOWNTO 0);
VARIABLE add_cast_1 : signed(16 DOWNTO 0);
VARIABLE add_cast_2 : signed(16 DOWNTO 0);
VARIABLE sub_cast : signed(16 DOWNTO 0);
VARIABLE sub_cast_0 : signed(16 DOWNTO 0);
VARIABLE sub_cast_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp : signed(16 DOWNTO 0);
VARIABLE add_cast_3 : signed(16 DOWNTO 0);
VARIABLE add_cast_4 : signed(16 DOWNTO 0);
VARIABLE add_cast_5 : signed(16 DOWNTO 0);
VARIABLE add_cast_6 : signed(16 DOWNTO 0);
VARIABLE sra_temp_0 : signed(16 DOWNTO 0);
VARIABLE sub_cast_3 : signed(16 DOWNTO 0);
VARIABLE sub_cast_4 : signed(16 DOWNTO 0);
VARIABLE sub_cast_5 : signed(16 DOWNTO 0);
VARIABLE sub_cast_6 : signed(16 DOWNTO 0);
VARIABLE sra_temp_1 : signed(16 DOWNTO 0);
VARIABLE sra_temp_2 : signed(16 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_13 /= '0' THEN
IF dout_1_vld = '1' THEN
add_cast_1 := resize(dout_13_re_signed, 17);
add_cast_2 := resize(dout_15_im_signed, 17);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(dout_13_re_signed, 17);
sub_cast_2 := resize(dout_15_im_signed, 17);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast_1 - sub_cast_2;
add_cast_5 := resize(dout_13_im_signed, 17);
add_cast_6 := resize(dout_15_re_signed, 17);
Radix22ButterflyG2_NF_btf2_im_reg_next <= add_cast_5 + add_cast_6;
sub_cast_5 := resize(dout_13_im_signed, 17);
sub_cast_6 := resize(dout_15_re_signed, 17);
Radix22ButterflyG2_NF_btf1_im_reg_next <= sub_cast_5 - sub_cast_6;
END IF;
ELSIF dout_1_vld = '1' THEN
add_cast := resize(dout_13_re_signed, 17);
add_cast_0 := resize(dout_15_re_signed, 17);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(dout_13_re_signed, 17);
sub_cast_0 := resize(dout_15_re_signed, 17);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_3 := resize(dout_13_im_signed, 17);
add_cast_4 := resize(dout_15_im_signed, 17);
Radix22ButterflyG2_NF_btf1_im_reg_next <= add_cast_3 + add_cast_4;
sub_cast_3 := resize(dout_13_im_signed, 17);
sub_cast_4 := resize(dout_15_im_signed, 17);
Radix22ButterflyG2_NF_btf2_im_reg_next <= sub_cast_3 - sub_cast_4;
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_re_reg, 1);
dout_13_re_tmp <= sra_temp(15 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_im_reg, 1);
dout_13_im_tmp <= sra_temp_0(15 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_re_reg, 1);
dout_14_re_tmp <= sra_temp_1(15 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_im_reg, 1);
dout_14_im_tmp <= sra_temp_2(15 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_14_re <= std_logic_vector(dout_14_re_tmp);
dout_14_im <= std_logic_vector(dout_14_im_tmp);
dout_13_re_1 <= std_logic_vector(dout_13_re_tmp);
dout_13_im_1 <= std_logic_vector(dout_13_im_tmp);
END rtl;
|
entity procinter is
end;
architecture arch of procinter is
procedure proc (procedure proc2 (v : natural)) is
begin
null;
end proc;
begin
end arch;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.