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-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
library ieee_proposed; use ieee_proposed.electrical_systems.all;
package transmission_lines_types is
type word is array (0 to 31) of bit;
subtype bus_lines is integer range 0 to 31;
nature electrical_bus is array (bus_lines) of electrical;
end package transmission_lines_types;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
use work.transmission_lines_types.all;
-- end not in book
entity transmission_lines is
port ( terminal data_bus : electrical_bus;
signal clk : in bit; signal data_out : out word );
end entity transmission_lines;
----------------------------------------------------------------
architecture abstract of transmission_lines is
constant threshold : voltage := 1.5;
quantity bus_voltages across bus_currents through
data_bus to electrical_ref;
begin
logic_value_maps : process (clk) is
begin
if clk = '1' then
for index in bus_lines loop
if bus_voltages(index) > threshold then
data_out(index) <= '1';
else
data_out(index) <= '0';
end if;
end loop;
end if;
end process logic_value_maps;
-- additional VHDL-AMS code to describe reflections and attenuation
-- ...
end architecture abstract;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
library ieee_proposed; use ieee_proposed.electrical_systems.all;
package transmission_lines_types is
type word is array (0 to 31) of bit;
subtype bus_lines is integer range 0 to 31;
nature electrical_bus is array (bus_lines) of electrical;
end package transmission_lines_types;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
use work.transmission_lines_types.all;
-- end not in book
entity transmission_lines is
port ( terminal data_bus : electrical_bus;
signal clk : in bit; signal data_out : out word );
end entity transmission_lines;
----------------------------------------------------------------
architecture abstract of transmission_lines is
constant threshold : voltage := 1.5;
quantity bus_voltages across bus_currents through
data_bus to electrical_ref;
begin
logic_value_maps : process (clk) is
begin
if clk = '1' then
for index in bus_lines loop
if bus_voltages(index) > threshold then
data_out(index) <= '1';
else
data_out(index) <= '0';
end if;
end loop;
end if;
end process logic_value_maps;
-- additional VHDL-AMS code to describe reflections and attenuation
-- ...
end architecture abstract;
|
-------------------------------------------------------------------------------
-- File downloaded from http://www.nandland.com
-------------------------------------------------------------------------------
-- Description:
-- A LFSR or Linear Feedback Shift Register is a quick and easy
-- way to generate pseudo-random data inside of an FPGA. The LFSR can be used
-- for things like counters, test patterns, scrambling of data, and others.
-- This module creates an LFSR whose width gets set by a generic. The
-- o_LFSR_Done will pulse once all combinations of the LFSR are complete. The
-- number of clock cycles that it takes o_LFSR_Done to pulse is equal to
-- 2^g_Num_Bits-1. For example, setting g_Num_Bits to 5 means that o_LFSR_Done
-- will pulse every 2^5-1 = 31 clock cycles. o_LFSR_Data will change on each
-- clock cycle that the module is enabled, which can be used if desired.
--
-- Generics:
-- g_Num_Bits - Set to the integer number of bits wide to create your LFSR.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity lfsr is
generic (
g_Num_Bits : integer := 5
);
port (
i_Clk : in std_logic;
i_Enable : in std_logic;
-- Optional Seed Value
i_Seed_DV : in std_logic;
i_Seed_Data : in std_logic_vector(g_Num_Bits-1 downto 0);
o_LFSR_Data : out std_logic_vector(g_Num_Bits-1 downto 0);
o_LFSR_Done : out std_logic
);
end entity lfsr;
architecture rtl of lfsr is
signal r_LFSR : std_logic_vector(g_Num_Bits downto 1) := (others => '0');
signal w_XNOR : std_logic;
begin
-- Purpose: Load up LFSR with Seed if Data Valid (DV) pulse is detected.
-- Othewise just run LFSR when enabled.
p_LFSR : process (i_Clk) is
begin
if rising_edge(i_Clk) then
if i_Enable = '1' then
if i_Seed_DV = '1' then
r_LFSR <= i_Seed_Data;
else
r_LFSR <= r_LFSR(r_LFSR'left-1 downto 1) & w_XNOR;
end if;
end if;
end if;
end process p_LFSR;
-- Create Feedback Polynomials. Based on Application Note:
-- http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf
g_LFSR_3 : if g_Num_Bits = 3 generate
w_XNOR <= r_LFSR(3) xnor r_LFSR(2);
end generate g_LFSR_3;
g_LFSR_4 : if g_Num_Bits = 4 generate
w_XNOR <= r_LFSR(4) xnor r_LFSR(3);
end generate g_LFSR_4;
g_LFSR_5 : if g_Num_Bits = 5 generate
w_XNOR <= r_LFSR(5) xnor r_LFSR(3);
end generate g_LFSR_5;
g_LFSR_6 : if g_Num_Bits = 6 generate
w_XNOR <= r_LFSR(6) xnor r_LFSR(5);
end generate g_LFSR_6;
g_LFSR_7 : if g_Num_Bits = 7 generate
w_XNOR <= r_LFSR(7) xnor r_LFSR(6);
end generate g_LFSR_7;
g_LFSR_8 : if g_Num_Bits = 8 generate
w_XNOR <= r_LFSR(8) xnor r_LFSR(6) xnor r_LFSR(5) xnor r_LFSR(4);
end generate g_LFSR_8;
g_LFSR_9 : if g_Num_Bits = 9 generate
w_XNOR <= r_LFSR(9) xnor r_LFSR(5);
end generate g_LFSR_9;
g_LFSR_10 : if g_Num_Bits = 10 generate
w_XNOR <= r_LFSR(10) xnor r_LFSR(7);
end generate g_LFSR_10;
g_LFSR_11 : if g_Num_Bits = 11 generate
w_XNOR <= r_LFSR(11) xnor r_LFSR(9);
end generate g_LFSR_11;
g_LFSR_12 : if g_Num_Bits = 12 generate
w_XNOR <= r_LFSR(12) xnor r_LFSR(6) xnor r_LFSR(4) xnor r_LFSR(1);
end generate g_LFSR_12;
g_LFSR_13 : if g_Num_Bits = 13 generate
w_XNOR <= r_LFSR(13) xnor r_LFSR(4) xnor r_LFSR(3) xnor r_LFSR(1);
end generate g_LFSR_13;
g_LFSR_14 : if g_Num_Bits = 14 generate
w_XNOR <= r_LFSR(14) xnor r_LFSR(5) xnor r_LFSR(3) xnor r_LFSR(1);
end generate g_LFSR_14;
g_LFSR_15 : if g_Num_Bits = 15 generate
w_XNOR <= r_LFSR(15) xnor r_LFSR(14);
end generate g_LFSR_15;
g_LFSR_16 : if g_Num_Bits = 16 generate
w_XNOR <= r_LFSR(16) xnor r_LFSR(15) xnor r_LFSR(13) xnor r_LFSR(4);
end generate g_LFSR_16;
g_LFSR_17 : if g_Num_Bits = 17 generate
w_XNOR <= r_LFSR(17) xnor r_LFSR(14);
end generate g_LFSR_17;
g_LFSR_18 : if g_Num_Bits = 18 generate
w_XNOR <= r_LFSR(18) xnor r_LFSR(11);
end generate g_LFSR_18;
g_LFSR_19 : if g_Num_Bits = 19 generate
w_XNOR <= r_LFSR(19) xnor r_LFSR(6) xnor r_LFSR(2) xnor r_LFSR(1);
end generate g_LFSR_19;
g_LFSR_20 : if g_Num_Bits = 20 generate
w_XNOR <= r_LFSR(20) xnor r_LFSR(17);
end generate g_LFSR_20;
g_LFSR_21 : if g_Num_Bits = 21 generate
w_XNOR <= r_LFSR(21) xnor r_LFSR(19);
end generate g_LFSR_21;
g_LFSR_22 : if g_Num_Bits = 22 generate
w_XNOR <= r_LFSR(22) xnor r_LFSR(21);
end generate g_LFSR_22;
g_LFSR_23 : if g_Num_Bits = 23 generate
w_XNOR <= r_LFSR(23) xnor r_LFSR(18);
end generate g_LFSR_23;
g_LFSR_24 : if g_Num_Bits = 24 generate
w_XNOR <= r_LFSR(24) xnor r_LFSR(23) xnor r_LFSR(22) xnor r_LFSR(17);
end generate g_LFSR_24;
g_LFSR_25 : if g_Num_Bits = 25 generate
w_XNOR <= r_LFSR(25) xnor r_LFSR(22);
end generate g_LFSR_25;
g_LFSR_26 : if g_Num_Bits = 26 generate
w_XNOR <= r_LFSR(26) xnor r_LFSR(6) xnor r_LFSR(2) xnor r_LFSR(1);
end generate g_LFSR_26;
g_LFSR_27 : if g_Num_Bits = 27 generate
w_XNOR <= r_LFSR(27) xnor r_LFSR(5) xnor r_LFSR(2) xnor r_LFSR(1);
end generate g_LFSR_27;
g_LFSR_28 : if g_Num_Bits = 28 generate
w_XNOR <= r_LFSR(28) xnor r_LFSR(25);
end generate g_LFSR_28;
g_LFSR_29 : if g_Num_Bits = 29 generate
w_XNOR <= r_LFSR(29) xnor r_LFSR(27);
end generate g_LFSR_29;
g_LFSR_30 : if g_Num_Bits = 30 generate
w_XNOR <= r_LFSR(30) xnor r_LFSR(6) xnor r_LFSR(4) xnor r_LFSR(1);
end generate g_LFSR_30;
g_LFSR_31 : if g_Num_Bits = 31 generate
w_XNOR <= r_LFSR(31) xnor r_LFSR(28);
end generate g_LFSR_31;
g_LFSR_32 : if g_Num_Bits = 32 generate
w_XNOR <= r_LFSR(32) xnor r_LFSR(22) xnor r_LFSR(2) xnor r_LFSR(1);
end generate g_LFSR_32;
o_LFSR_Data <= r_LFSR(r_LFSR'left downto 1);
o_LFSR_Done <= '1' when r_LFSR(r_LFSR'left downto 1) = i_Seed_Data else '0';
end architecture rtl; |
entity test is
subtype t is foo(open, open);
end;
|
----------------------------------------------------------------------------------------------------
-- muxer
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
----------------------------------------------------------------------------------------------------
-- PACKAGE
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
package muxer_pkg is
--muxer componenet declaration
component muxer is
generic( INIT_SEL : std_logic_vector(1 downto 0) := b"10");
port( clk : in std_logic;
clk_2x : in std_logic;
rst : in std_logic;
sig1 : in std_logic_vector;
sig2 : in std_logic_vector;
sigs : out std_logic_vector);
end component;
end package;
----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--This entity takes 2 input signals and interlaces them into 1 output signal. During development
--it was determined that the clock inputs must be phase aligned for best results
entity muxer is
generic( INIT_SEL : std_logic_vector(1 downto 0) := b"10");
port( clk : in std_logic;
clk_2x : in std_logic;
rst : in std_logic;
sig1 : in std_logic_vector;
sig2 : in std_logic_vector;
sigs : out std_logic_vector);
end muxer;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE
----------------------------------------------------------------------------------------------------
architecture behave of muxer is
signal sig1_reg : std_logic_vector(sig1'range) := (others => '0');
signal sig2_reg : std_logic_vector(sig2'range) := (others => '0');
signal selector : std_logic_vector(1 downto 0) := INIT_SEL;
signal sigs_reg : std_logic_vector(sigs'range) := (others => '0');
begin
--Register the inputs
reg_in : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
sig1_reg <= (others => '0');
sig2_reg <= (others => '0');
else
sig1_reg <= sig1;
sig2_reg <= sig2;
end if;
end if;
end process;
--Selection
update_selection : process(clk_2x)
begin
if(rising_edge(clk_2x)) then
if(rst = '1') then
selector <= INIT_SEL;
else
selector <= std_logic_vector(rotate_left(unsigned(selector), 1));
end if;
end if;
end process;
--Register the output
reg_out : process(clk_2x)
begin
if(rising_edge(clk_2x)) then
if(rst = '1') then
sigs_reg <= (others => '0');
else
case selector is
when b"01" => sigs_reg <= sig1;
when b"10" => sigs_reg <= sig2;
when others => sigs_reg <= (others => '-');
end case;
end if;
end if;
end process;
sigs <= sigs_reg;
end behave;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 69
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 69
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := artix7;
constant CFG_MEMTECH : integer := artix7;
constant CFG_PADTECH : integer := artix7;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := artix7;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (8);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON processor core
constant CFG_LEON : integer := 3;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_BWMASK : integer := 16#0#;
constant CFG_CACHEBW : integer := 128;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*1;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 2;
constant CFG_AHBWP : integer := 2;
constant CFG_LEONFT_EN : integer := 0 + 0*8;
constant CFG_LEON_NETLIST : integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 1;
constant CFG_STAT_CNT : integer := (4);
constant CFG_STAT_NMAX : integer := (0);
constant CFG_STAT_DSUEN : integer := 1;
constant CFG_NP_ASI : integer := 1;
constant CFG_WRPSR : integer := 1;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- L2 Cache
constant CFG_L2_EN : integer := 1;
constant CFG_L2_SIZE : integer := 64;
constant CFG_L2_WAYS : integer := 1;
constant CFG_L2_HPROT : integer := 0;
constant CFG_L2_PEN : integer := 0;
constant CFG_L2_WT : integer := 0;
constant CFG_L2_RAN : integer := 0;
constant CFG_L2_SHARE : integer := 0;
constant CFG_L2_LSZ : integer := 32;
constant CFG_L2_MAP : integer := 16#00F0#;
constant CFG_L2_MTRR : integer := (0);
constant CFG_L2_EDAC : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG 7-Series
constant CFG_MIG_7SERIES : integer := 1;
constant CFG_MIG_7SERIES_MODEL : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 0;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 32;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (7);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0B#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (8);
constant CFG_SPIMCTRL_ASCALER : integer := (8);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (1);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
entity repro is
end repro;
architecture behaviour of repro is
signal selector : bit_vector(1 downto 0) := "10";
signal result : bit_vector(7 downto 0);
signal op_1 : bit_vector(7 downto 0);
signal op_2 : bit_vector(7 downto 0);
begin
with selector select
result <= op_1 and op_2 when "00",
(others => '0') when others;
end behaviour;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_b_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-rtl-a.vhd,v 1.2 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: inst_b_e-rtl-a.vhd,v $
-- Revision 1.2 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_b_e
--
architecture rtl of inst_b_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_ba
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component ent_bb
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_ba
inst_ba: ent_ba
;
-- End of Generated Instance Port Map for inst_ba
-- Generated Instance Port Map for inst_bb
inst_bb: ent_bb
;
-- End of Generated Instance Port Map for inst_bb
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_sc_fifo is
generic(
DATA_WIDTH : positive;
FIFO_DEPTH : positive;
DEVICE_FAMILY : string
);
port(
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH - 1 downto 0);
data_out : out std_logic_vector(DATA_WIDTH - 1 downto 0);
read : in std_logic;
write : in std_logic;
empty : out std_logic;
full : out std_logic;
usedw : out std_logic_vector(bit_width(FIFO_DEPTH) - 1 downto 0);
overflow : out std_logic
);
end cmos_sensor_input_sc_fifo;
architecture rtl of cmos_sensor_input_sc_fifo is
component scfifo
generic(
add_ram_output_register : string;
intended_device_family : string;
lpm_numwords : natural;
lpm_showahead : string;
lpm_type : string;
lpm_width : natural;
lpm_widthu : natural;
overflow_checking : string;
underflow_checking : string;
use_eab : string
);
port(
clock : in std_logic;
data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
rdreq : in std_logic;
sclr : in std_logic;
wrreq : in std_logic;
empty : out std_logic;
full : out std_logic;
q : out std_logic_vector(DATA_WIDTH - 1 downto 0);
usedw : out std_logic_vector(bit_width(FIFO_DEPTH) - 2 downto 0)
);
end component;
signal scfifo_clock : std_logic;
signal scfifo_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal scfifo_rdreq : std_logic;
signal scfifo_sclr : std_logic;
signal scfifo_wrreq : std_logic;
signal scfifo_empty : std_logic;
signal scfifo_full : std_logic;
signal scfifo_q : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal scfifo_usedw : std_logic_vector(bit_width(FIFO_DEPTH) - 2 downto 0);
signal reg_overflow : std_logic;
begin
FIFO_OVERFLOW : process(clk, reset)
begin
if reset = '1' then
reg_overflow <= '0';
elsif rising_edge(clk) then
if clr = '1' then
reg_overflow <= '0';
else
reg_overflow <= reg_overflow or (write and scfifo_full);
end if;
end if;
end process;
OUTPUTS : process(reg_overflow, scfifo_empty, scfifo_full, scfifo_q, scfifo_usedw)
begin
data_out <= scfifo_q;
empty <= scfifo_empty;
full <= scfifo_full;
overflow <= reg_overflow;
if scfifo_full = '1' then
usedw <= std_logic_vector(to_unsigned(FIFO_DEPTH, usedw'length));
elsif scfifo_empty = '1' then
usedw <= std_logic_vector(to_unsigned(0, usedw'length));
else
usedw <= std_logic_vector(resize(unsigned(scfifo_usedw), usedw'length));
end if;
end process;
-- scfifo connections ------------------------------------------------------
scfifo_clock <= clk;
scfifo_data <= data_in;
scfifo_rdreq <= read and not scfifo_empty;
scfifo_sclr <= clr;
scfifo_wrreq <= write and not scfifo_full;
scfifo_component : scfifo
generic map(
add_ram_output_register => "OFF",
intended_device_family => DEVICE_FAMILY,
lpm_numwords => FIFO_DEPTH,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => DATA_WIDTH,
lpm_widthu => bit_width(FIFO_DEPTH) - 1,
overflow_checking => "OFF",
underflow_checking => "OFF",
use_eab => "ON"
)
port map(
clock => scfifo_clock,
data => scfifo_data,
rdreq => scfifo_rdreq,
sclr => scfifo_sclr,
wrreq => scfifo_wrreq,
empty => scfifo_empty,
full => scfifo_full,
q => scfifo_q,
usedw => scfifo_usedw
);
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_sc_fifo is
generic(
DATA_WIDTH : positive;
FIFO_DEPTH : positive;
DEVICE_FAMILY : string
);
port(
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH - 1 downto 0);
data_out : out std_logic_vector(DATA_WIDTH - 1 downto 0);
read : in std_logic;
write : in std_logic;
empty : out std_logic;
full : out std_logic;
usedw : out std_logic_vector(bit_width(FIFO_DEPTH) - 1 downto 0);
overflow : out std_logic
);
end cmos_sensor_input_sc_fifo;
architecture rtl of cmos_sensor_input_sc_fifo is
component scfifo
generic(
add_ram_output_register : string;
intended_device_family : string;
lpm_numwords : natural;
lpm_showahead : string;
lpm_type : string;
lpm_width : natural;
lpm_widthu : natural;
overflow_checking : string;
underflow_checking : string;
use_eab : string
);
port(
clock : in std_logic;
data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
rdreq : in std_logic;
sclr : in std_logic;
wrreq : in std_logic;
empty : out std_logic;
full : out std_logic;
q : out std_logic_vector(DATA_WIDTH - 1 downto 0);
usedw : out std_logic_vector(bit_width(FIFO_DEPTH) - 2 downto 0)
);
end component;
signal scfifo_clock : std_logic;
signal scfifo_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal scfifo_rdreq : std_logic;
signal scfifo_sclr : std_logic;
signal scfifo_wrreq : std_logic;
signal scfifo_empty : std_logic;
signal scfifo_full : std_logic;
signal scfifo_q : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal scfifo_usedw : std_logic_vector(bit_width(FIFO_DEPTH) - 2 downto 0);
signal reg_overflow : std_logic;
begin
FIFO_OVERFLOW : process(clk, reset)
begin
if reset = '1' then
reg_overflow <= '0';
elsif rising_edge(clk) then
if clr = '1' then
reg_overflow <= '0';
else
reg_overflow <= reg_overflow or (write and scfifo_full);
end if;
end if;
end process;
OUTPUTS : process(reg_overflow, scfifo_empty, scfifo_full, scfifo_q, scfifo_usedw)
begin
data_out <= scfifo_q;
empty <= scfifo_empty;
full <= scfifo_full;
overflow <= reg_overflow;
if scfifo_full = '1' then
usedw <= std_logic_vector(to_unsigned(FIFO_DEPTH, usedw'length));
elsif scfifo_empty = '1' then
usedw <= std_logic_vector(to_unsigned(0, usedw'length));
else
usedw <= std_logic_vector(resize(unsigned(scfifo_usedw), usedw'length));
end if;
end process;
-- scfifo connections ------------------------------------------------------
scfifo_clock <= clk;
scfifo_data <= data_in;
scfifo_rdreq <= read and not scfifo_empty;
scfifo_sclr <= clr;
scfifo_wrreq <= write and not scfifo_full;
scfifo_component : scfifo
generic map(
add_ram_output_register => "OFF",
intended_device_family => DEVICE_FAMILY,
lpm_numwords => FIFO_DEPTH,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => DATA_WIDTH,
lpm_widthu => bit_width(FIFO_DEPTH) - 1,
overflow_checking => "OFF",
underflow_checking => "OFF",
use_eab => "ON"
)
port map(
clock => scfifo_clock,
data => scfifo_data,
rdreq => scfifo_rdreq,
sclr => scfifo_sclr,
wrreq => scfifo_wrreq,
empty => scfifo_empty,
full => scfifo_full,
q => scfifo_q,
usedw => scfifo_usedw
);
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_sc_fifo is
generic(
DATA_WIDTH : positive;
FIFO_DEPTH : positive;
DEVICE_FAMILY : string
);
port(
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH - 1 downto 0);
data_out : out std_logic_vector(DATA_WIDTH - 1 downto 0);
read : in std_logic;
write : in std_logic;
empty : out std_logic;
full : out std_logic;
usedw : out std_logic_vector(bit_width(FIFO_DEPTH) - 1 downto 0);
overflow : out std_logic
);
end cmos_sensor_input_sc_fifo;
architecture rtl of cmos_sensor_input_sc_fifo is
component scfifo
generic(
add_ram_output_register : string;
intended_device_family : string;
lpm_numwords : natural;
lpm_showahead : string;
lpm_type : string;
lpm_width : natural;
lpm_widthu : natural;
overflow_checking : string;
underflow_checking : string;
use_eab : string
);
port(
clock : in std_logic;
data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
rdreq : in std_logic;
sclr : in std_logic;
wrreq : in std_logic;
empty : out std_logic;
full : out std_logic;
q : out std_logic_vector(DATA_WIDTH - 1 downto 0);
usedw : out std_logic_vector(bit_width(FIFO_DEPTH) - 2 downto 0)
);
end component;
signal scfifo_clock : std_logic;
signal scfifo_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal scfifo_rdreq : std_logic;
signal scfifo_sclr : std_logic;
signal scfifo_wrreq : std_logic;
signal scfifo_empty : std_logic;
signal scfifo_full : std_logic;
signal scfifo_q : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal scfifo_usedw : std_logic_vector(bit_width(FIFO_DEPTH) - 2 downto 0);
signal reg_overflow : std_logic;
begin
FIFO_OVERFLOW : process(clk, reset)
begin
if reset = '1' then
reg_overflow <= '0';
elsif rising_edge(clk) then
if clr = '1' then
reg_overflow <= '0';
else
reg_overflow <= reg_overflow or (write and scfifo_full);
end if;
end if;
end process;
OUTPUTS : process(reg_overflow, scfifo_empty, scfifo_full, scfifo_q, scfifo_usedw)
begin
data_out <= scfifo_q;
empty <= scfifo_empty;
full <= scfifo_full;
overflow <= reg_overflow;
if scfifo_full = '1' then
usedw <= std_logic_vector(to_unsigned(FIFO_DEPTH, usedw'length));
elsif scfifo_empty = '1' then
usedw <= std_logic_vector(to_unsigned(0, usedw'length));
else
usedw <= std_logic_vector(resize(unsigned(scfifo_usedw), usedw'length));
end if;
end process;
-- scfifo connections ------------------------------------------------------
scfifo_clock <= clk;
scfifo_data <= data_in;
scfifo_rdreq <= read and not scfifo_empty;
scfifo_sclr <= clr;
scfifo_wrreq <= write and not scfifo_full;
scfifo_component : scfifo
generic map(
add_ram_output_register => "OFF",
intended_device_family => DEVICE_FAMILY,
lpm_numwords => FIFO_DEPTH,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => DATA_WIDTH,
lpm_widthu => bit_width(FIFO_DEPTH) - 1,
overflow_checking => "OFF",
underflow_checking => "OFF",
use_eab => "ON"
)
port map(
clock => scfifo_clock,
data => scfifo_data,
rdreq => scfifo_rdreq,
sclr => scfifo_sclr,
wrreq => scfifo_wrreq,
empty => scfifo_empty,
full => scfifo_full,
q => scfifo_q,
usedw => scfifo_usedw
);
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_sc_fifo is
generic(
DATA_WIDTH : positive;
FIFO_DEPTH : positive;
DEVICE_FAMILY : string
);
port(
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH - 1 downto 0);
data_out : out std_logic_vector(DATA_WIDTH - 1 downto 0);
read : in std_logic;
write : in std_logic;
empty : out std_logic;
full : out std_logic;
usedw : out std_logic_vector(bit_width(FIFO_DEPTH) - 1 downto 0);
overflow : out std_logic
);
end cmos_sensor_input_sc_fifo;
architecture rtl of cmos_sensor_input_sc_fifo is
component scfifo
generic(
add_ram_output_register : string;
intended_device_family : string;
lpm_numwords : natural;
lpm_showahead : string;
lpm_type : string;
lpm_width : natural;
lpm_widthu : natural;
overflow_checking : string;
underflow_checking : string;
use_eab : string
);
port(
clock : in std_logic;
data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
rdreq : in std_logic;
sclr : in std_logic;
wrreq : in std_logic;
empty : out std_logic;
full : out std_logic;
q : out std_logic_vector(DATA_WIDTH - 1 downto 0);
usedw : out std_logic_vector(bit_width(FIFO_DEPTH) - 2 downto 0)
);
end component;
signal scfifo_clock : std_logic;
signal scfifo_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal scfifo_rdreq : std_logic;
signal scfifo_sclr : std_logic;
signal scfifo_wrreq : std_logic;
signal scfifo_empty : std_logic;
signal scfifo_full : std_logic;
signal scfifo_q : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal scfifo_usedw : std_logic_vector(bit_width(FIFO_DEPTH) - 2 downto 0);
signal reg_overflow : std_logic;
begin
FIFO_OVERFLOW : process(clk, reset)
begin
if reset = '1' then
reg_overflow <= '0';
elsif rising_edge(clk) then
if clr = '1' then
reg_overflow <= '0';
else
reg_overflow <= reg_overflow or (write and scfifo_full);
end if;
end if;
end process;
OUTPUTS : process(reg_overflow, scfifo_empty, scfifo_full, scfifo_q, scfifo_usedw)
begin
data_out <= scfifo_q;
empty <= scfifo_empty;
full <= scfifo_full;
overflow <= reg_overflow;
if scfifo_full = '1' then
usedw <= std_logic_vector(to_unsigned(FIFO_DEPTH, usedw'length));
elsif scfifo_empty = '1' then
usedw <= std_logic_vector(to_unsigned(0, usedw'length));
else
usedw <= std_logic_vector(resize(unsigned(scfifo_usedw), usedw'length));
end if;
end process;
-- scfifo connections ------------------------------------------------------
scfifo_clock <= clk;
scfifo_data <= data_in;
scfifo_rdreq <= read and not scfifo_empty;
scfifo_sclr <= clr;
scfifo_wrreq <= write and not scfifo_full;
scfifo_component : scfifo
generic map(
add_ram_output_register => "OFF",
intended_device_family => DEVICE_FAMILY,
lpm_numwords => FIFO_DEPTH,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => DATA_WIDTH,
lpm_widthu => bit_width(FIFO_DEPTH) - 1,
overflow_checking => "OFF",
underflow_checking => "OFF",
use_eab => "ON"
)
port map(
clock => scfifo_clock,
data => scfifo_data,
rdreq => scfifo_rdreq,
sclr => scfifo_sclr,
wrreq => scfifo_wrreq,
empty => scfifo_empty,
full => scfifo_full,
q => scfifo_q,
usedw => scfifo_usedw
);
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_sc_fifo is
generic(
DATA_WIDTH : positive;
FIFO_DEPTH : positive;
DEVICE_FAMILY : string
);
port(
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH - 1 downto 0);
data_out : out std_logic_vector(DATA_WIDTH - 1 downto 0);
read : in std_logic;
write : in std_logic;
empty : out std_logic;
full : out std_logic;
usedw : out std_logic_vector(bit_width(FIFO_DEPTH) - 1 downto 0);
overflow : out std_logic
);
end cmos_sensor_input_sc_fifo;
architecture rtl of cmos_sensor_input_sc_fifo is
component scfifo
generic(
add_ram_output_register : string;
intended_device_family : string;
lpm_numwords : natural;
lpm_showahead : string;
lpm_type : string;
lpm_width : natural;
lpm_widthu : natural;
overflow_checking : string;
underflow_checking : string;
use_eab : string
);
port(
clock : in std_logic;
data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
rdreq : in std_logic;
sclr : in std_logic;
wrreq : in std_logic;
empty : out std_logic;
full : out std_logic;
q : out std_logic_vector(DATA_WIDTH - 1 downto 0);
usedw : out std_logic_vector(bit_width(FIFO_DEPTH) - 2 downto 0)
);
end component;
signal scfifo_clock : std_logic;
signal scfifo_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal scfifo_rdreq : std_logic;
signal scfifo_sclr : std_logic;
signal scfifo_wrreq : std_logic;
signal scfifo_empty : std_logic;
signal scfifo_full : std_logic;
signal scfifo_q : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal scfifo_usedw : std_logic_vector(bit_width(FIFO_DEPTH) - 2 downto 0);
signal reg_overflow : std_logic;
begin
FIFO_OVERFLOW : process(clk, reset)
begin
if reset = '1' then
reg_overflow <= '0';
elsif rising_edge(clk) then
if clr = '1' then
reg_overflow <= '0';
else
reg_overflow <= reg_overflow or (write and scfifo_full);
end if;
end if;
end process;
OUTPUTS : process(reg_overflow, scfifo_empty, scfifo_full, scfifo_q, scfifo_usedw)
begin
data_out <= scfifo_q;
empty <= scfifo_empty;
full <= scfifo_full;
overflow <= reg_overflow;
if scfifo_full = '1' then
usedw <= std_logic_vector(to_unsigned(FIFO_DEPTH, usedw'length));
elsif scfifo_empty = '1' then
usedw <= std_logic_vector(to_unsigned(0, usedw'length));
else
usedw <= std_logic_vector(resize(unsigned(scfifo_usedw), usedw'length));
end if;
end process;
-- scfifo connections ------------------------------------------------------
scfifo_clock <= clk;
scfifo_data <= data_in;
scfifo_rdreq <= read and not scfifo_empty;
scfifo_sclr <= clr;
scfifo_wrreq <= write and not scfifo_full;
scfifo_component : scfifo
generic map(
add_ram_output_register => "OFF",
intended_device_family => DEVICE_FAMILY,
lpm_numwords => FIFO_DEPTH,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => DATA_WIDTH,
lpm_widthu => bit_width(FIFO_DEPTH) - 1,
overflow_checking => "OFF",
underflow_checking => "OFF",
use_eab => "ON"
)
port map(
clock => scfifo_clock,
data => scfifo_data,
rdreq => scfifo_rdreq,
sclr => scfifo_sclr,
wrreq => scfifo_wrreq,
empty => scfifo_empty,
full => scfifo_full,
q => scfifo_q,
usedw => scfifo_usedw
);
end rtl;
|
library verilog;
use verilog.vl_types.all;
entity nfa_accept_samples_generic_hw is
generic(
ap_const_logic_1: vl_logic := Hi1;
ap_const_logic_0: vl_logic := Hi0;
ap_ST_st1_fsm_0 : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
ap_ST_st2_fsm_1 : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi1);
ap_ST_st3_fsm_2 : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi0, Hi1, Hi0);
ap_ST_st4_fsm_3 : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi0, Hi1, Hi1);
ap_ST_st5_fsm_4 : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi1, Hi0, Hi0);
ap_ST_st6_fsm_5 : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi1, Hi0, Hi1);
ap_ST_st7_fsm_6 : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi1, Hi1, Hi0);
ap_ST_st8_fsm_7 : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi1, Hi1, Hi1);
ap_ST_st9_fsm_8 : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi1, Hi0, Hi0, Hi0);
ap_ST_st10_fsm_9: vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi1, Hi0, Hi0, Hi1);
ap_ST_st11_fsm_10: vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi1, Hi0, Hi1, Hi0);
ap_ST_st12_fsm_11: vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi1, Hi0, Hi1, Hi1);
ap_ST_st13_fsm_12: vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi1, Hi1, Hi0, Hi0);
ap_ST_st14_fsm_13: vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi1, Hi1, Hi0, Hi1);
ap_ST_st15_fsm_14: vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi1, Hi1, Hi1, Hi0);
ap_ST_st16_fsm_15: vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi1, Hi1, Hi1, Hi1);
ap_ST_st17_fsm_16: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi0, Hi0, Hi0, Hi0);
ap_ST_st18_fsm_17: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi0, Hi0, Hi0, Hi1);
ap_ST_st19_fsm_18: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi0, Hi0, Hi1, Hi0);
ap_ST_st20_fsm_19: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi0, Hi0, Hi1, Hi1);
ap_ST_st21_fsm_20: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi0, Hi1, Hi0, Hi0);
ap_ST_st22_fsm_21: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi0, Hi1, Hi0, Hi1);
ap_ST_st23_fsm_22: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi0, Hi1, Hi1, Hi0);
ap_ST_st24_fsm_23: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi0, Hi1, Hi1, Hi1);
ap_ST_st25_fsm_24: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi1, Hi0, Hi0, Hi0);
ap_ST_st26_fsm_25: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi1, Hi0, Hi0, Hi1);
ap_ST_st27_fsm_26: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi1, Hi0, Hi1, Hi0);
ap_ST_st28_fsm_27: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi1, Hi0, Hi1, Hi1);
ap_ST_st29_fsm_28: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi1, Hi1, Hi0, Hi0);
ap_ST_st30_fsm_29: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi1, Hi1, Hi0, Hi1);
ap_ST_st31_fsm_30: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi1, Hi1, Hi1, Hi0);
ap_ST_st32_fsm_31: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi1, Hi1, Hi1, Hi1);
ap_ST_st33_fsm_32: vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi0, Hi0, Hi0);
ap_ST_st34_fsm_33: vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi0, Hi0, Hi1);
ap_ST_st35_fsm_34: vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi0, Hi1, Hi0);
ap_ST_st36_fsm_35: vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi0, Hi1, Hi1);
ap_ST_st37_fsm_36: vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi1, Hi0, Hi0);
ap_const_lv1_0 : vl_logic := Hi0;
ap_const_lv16_0 : vl_logic_vector(0 to 15) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
ap_const_lv64_0 : vl_logic_vector(0 to 63) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
ap_const_lv1_1 : vl_logic := Hi1;
ap_const_lv32_0 : integer := 0;
ap_const_lv2_2 : vl_logic_vector(0 to 1) := (Hi1, Hi0);
ap_const_lv32_1 : integer := 1;
ap_const_lv64_1 : vl_logic_vector(0 to 63) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1);
ap_const_lv16_1 : vl_logic_vector(0 to 15) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1);
ap_const_lv5_0 : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi0, Hi0, Hi0);
ap_const_lv8_0 : vl_logic_vector(0 to 7) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
ap_true : vl_logic := Hi1
);
port(
ap_clk : in vl_logic;
ap_rst : in vl_logic;
ap_start : in vl_logic;
ap_done : out vl_logic;
ap_idle : out vl_logic;
ap_ready : out vl_logic;
nfa_initials_buckets_req_din: out vl_logic;
nfa_initials_buckets_req_full_n: in vl_logic;
nfa_initials_buckets_req_write: out vl_logic;
nfa_initials_buckets_rsp_empty_n: in vl_logic;
nfa_initials_buckets_rsp_read: out vl_logic;
nfa_initials_buckets_address: out vl_logic_vector(31 downto 0);
nfa_initials_buckets_datain: in vl_logic_vector(31 downto 0);
nfa_initials_buckets_dataout: out vl_logic_vector(31 downto 0);
nfa_initials_buckets_size: out vl_logic_vector(31 downto 0);
nfa_finals_buckets_req_din: out vl_logic;
nfa_finals_buckets_req_full_n: in vl_logic;
nfa_finals_buckets_req_write: out vl_logic;
nfa_finals_buckets_rsp_empty_n: in vl_logic;
nfa_finals_buckets_rsp_read: out vl_logic;
nfa_finals_buckets_address: out vl_logic_vector(31 downto 0);
nfa_finals_buckets_datain: in vl_logic_vector(31 downto 0);
nfa_finals_buckets_dataout: out vl_logic_vector(31 downto 0);
nfa_finals_buckets_size: out vl_logic_vector(31 downto 0);
nfa_forward_buckets_req_din: out vl_logic;
nfa_forward_buckets_req_full_n: in vl_logic;
nfa_forward_buckets_req_write: out vl_logic;
nfa_forward_buckets_rsp_empty_n: in vl_logic;
nfa_forward_buckets_rsp_read: out vl_logic;
nfa_forward_buckets_address: out vl_logic_vector(31 downto 0);
nfa_forward_buckets_datain: in vl_logic_vector(31 downto 0);
nfa_forward_buckets_dataout: out vl_logic_vector(31 downto 0);
nfa_forward_buckets_size: out vl_logic_vector(31 downto 0);
nfa_symbols : in vl_logic_vector(7 downto 0);
sample_buffer_req_din: out vl_logic;
sample_buffer_req_full_n: in vl_logic;
sample_buffer_req_write: out vl_logic;
sample_buffer_rsp_empty_n: in vl_logic;
sample_buffer_rsp_read: out vl_logic;
sample_buffer_address: out vl_logic_vector(31 downto 0);
sample_buffer_datain: in vl_logic_vector(7 downto 0);
sample_buffer_dataout: out vl_logic_vector(7 downto 0);
sample_buffer_size: out vl_logic_vector(31 downto 0);
sample_buffer_length: in vl_logic_vector(31 downto 0);
sample_length : in vl_logic_vector(15 downto 0);
indices_req_din : out vl_logic;
indices_req_full_n: in vl_logic;
indices_req_write: out vl_logic;
indices_rsp_empty_n: in vl_logic;
indices_rsp_read: out vl_logic;
indices_address : out vl_logic_vector(31 downto 0);
indices_datain : in vl_logic_vector(55 downto 0);
indices_dataout : out vl_logic_vector(55 downto 0);
indices_size : out vl_logic_vector(31 downto 0);
i_size : in vl_logic_vector(15 downto 0);
begin_index : in vl_logic_vector(15 downto 0);
begin_sample : in vl_logic_vector(15 downto 0);
end_index : in vl_logic_vector(15 downto 0);
end_sample : in vl_logic_vector(15 downto 0);
stop_on_first : in vl_logic_vector(0 downto 0);
accept : in vl_logic_vector(0 downto 0);
ap_return : out vl_logic_vector(31 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of ap_const_logic_1 : constant is 1;
attribute mti_svvh_generic_type of ap_const_logic_0 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st1_fsm_0 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st2_fsm_1 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st3_fsm_2 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st4_fsm_3 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st5_fsm_4 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st6_fsm_5 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st7_fsm_6 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st8_fsm_7 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st9_fsm_8 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st10_fsm_9 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st11_fsm_10 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st12_fsm_11 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st13_fsm_12 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st14_fsm_13 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st15_fsm_14 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st16_fsm_15 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st17_fsm_16 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st18_fsm_17 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st19_fsm_18 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st20_fsm_19 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st21_fsm_20 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st22_fsm_21 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st23_fsm_22 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st24_fsm_23 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st25_fsm_24 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st26_fsm_25 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st27_fsm_26 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st28_fsm_27 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st29_fsm_28 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st30_fsm_29 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st31_fsm_30 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st32_fsm_31 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st33_fsm_32 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st34_fsm_33 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st35_fsm_34 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st36_fsm_35 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_st37_fsm_36 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv1_0 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv16_0 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv64_0 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv1_1 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv32_0 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv2_2 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv32_1 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv64_1 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv16_1 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv5_0 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv8_0 : constant is 1;
attribute mti_svvh_generic_type of ap_true : constant is 1;
end nfa_accept_samples_generic_hw;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Little endian encoded number to number in one-hot encoding
--
-- .. hwt-autodoc::
--
ENTITY BinToOneHot IS
GENERIC(
DATA_WIDTH : INTEGER := 1
);
PORT(
din : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
en : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF BinToOneHot IS
BEGIN
dout(0) <= en;
ASSERT DATA_WIDTH = 1 REPORT "Generated only for this value" SEVERITY failure;
END ARCHITECTURE;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Master for SPI interface
--
-- :ivar ~.SPI_FREQ_PESCALER: frequency prescaler to get SPI clk from main clk (Param)
-- :ivar ~.SS_WAIT_CLK_TICKS: number of SPI ticks to wait with SPI clk activation after slave select
-- :ivar ~.HAS_TX: if set true write part will be instantiated
-- :ivar ~.HAS_RX: if set true read part will be instantiated
--
-- :attention: this implementation expects that slaves are reading data on rising edge of SPI clk
-- and data from slaves are ready on risign edge as well
-- and SPI clk is kept high in idle
-- (most of them does but there are some exceptions)
--
-- .. hwt-autodoc::
--
ENTITY SpiMaster IS
GENERIC(
FREQ : INTEGER := 100000000;
HAS_MISO : BOOLEAN := TRUE;
HAS_MOSI : BOOLEAN := TRUE;
HAS_RX : BOOLEAN := TRUE;
HAS_TX : BOOLEAN := TRUE;
SLAVE_CNT : INTEGER := 1;
SPI_DATA_WIDTH : INTEGER := 1;
SPI_FREQ_PESCALER : INTEGER := 32;
SS_WAIT_CLK_TICKS : INTEGER := 4
);
PORT(
clk : IN STD_LOGIC;
data_din : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
data_dout : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_last : IN STD_LOGIC;
data_rd : OUT STD_LOGIC;
data_slave : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
data_vld : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
spi_clk : OUT STD_LOGIC;
spi_cs : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
spi_miso : IN STD_LOGIC;
spi_mosi : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF SpiMaster IS
--
-- Little endian encoded number to number in one-hot encoding
--
-- .. hwt-autodoc::
--
COMPONENT BinToOneHot IS
GENERIC(
DATA_WIDTH : INTEGER := 1
);
PORT(
din : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
en : IN STD_LOGIC
);
END COMPONENT;
SIGNAL clkIntern : STD_LOGIC := '1';
SIGNAL clkIntern_next : STD_LOGIC;
SIGNAL clkIntern_next_edgeDetect_last : STD_LOGIC := '1';
SIGNAL clkIntern_next_edgeDetect_last_next : STD_LOGIC;
SIGNAL clkIntern_next_falling : STD_LOGIC;
SIGNAL clkIntern_next_rising : STD_LOGIC;
SIGNAL clkOut : STD_LOGIC := '1';
SIGNAL clkOut_next : STD_LOGIC;
SIGNAL endOfWord : STD_LOGIC;
SIGNAL endOfWordDelayed : STD_LOGIC := '0';
SIGNAL endOfWordDelayed_next : STD_LOGIC;
SIGNAL endOfWordtimerCntr256 : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"FF";
SIGNAL endOfWordtimerCntr256_next : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL endOfWordtimerTick256 : STD_LOGIC;
SIGNAL rxReg : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rxReg_next : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL sig_csDecoder_din : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL sig_csDecoder_dout : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL sig_csDecoder_en : STD_LOGIC;
SIGNAL slaveSelectWaitRequired : STD_LOGIC := '1';
SIGNAL slaveSelectWaitRequired_next : STD_LOGIC;
SIGNAL timersRst : STD_LOGIC;
SIGNAL txInitialized : STD_LOGIC := '0';
SIGNAL txInitialized_next : STD_LOGIC;
SIGNAL txReg : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL txReg_next : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
csDecoder_inst: BinToOneHot GENERIC MAP(
DATA_WIDTH => 1
) PORT MAP(
din => sig_csDecoder_din,
dout => sig_csDecoder_dout,
en => sig_csDecoder_en
);
assig_process_clkIntern_next: PROCESS(clkIntern, data_vld, endOfWordDelayed, endOfWordtimerCntr256)
BEGIN
IF endOfWordtimerCntr256(3 DOWNTO 0) = X"0" AND (NOT endOfWordDelayed AND data_vld) = '1' THEN
clkIntern_next <= NOT clkIntern;
ELSE
clkIntern_next <= clkIntern;
END IF;
END PROCESS;
clkIntern_next_edgeDetect_last_next <= clkIntern_next;
clkIntern_next_falling <= NOT clkIntern_next AND clkIntern_next_edgeDetect_last;
clkIntern_next_rising <= clkIntern_next AND NOT clkIntern_next_edgeDetect_last;
assig_process_clkOut_next: PROCESS(clkOut, data_vld, endOfWordDelayed, endOfWordtimerCntr256, slaveSelectWaitRequired)
BEGIN
IF slaveSelectWaitRequired = '0' AND (endOfWordtimerCntr256(3 DOWNTO 0) = X"0" AND (NOT endOfWordDelayed AND data_vld) = '1') THEN
clkOut_next <= NOT clkOut;
ELSE
clkOut_next <= clkOut;
END IF;
END PROCESS;
data_din <= rxReg;
data_rd <= endOfWordDelayed;
endOfWord <= '1' WHEN (endOfWordtimerCntr256 = X"00" AND (NOT endOfWordDelayed AND data_vld) = '1' AND timersRst = '0') ELSE '0';
endOfWordDelayed_next <= endOfWordtimerTick256;
assig_process_endOfWordtimerCntr256_next: PROCESS(data_vld, endOfWordDelayed, endOfWordtimerCntr256, timersRst)
VARIABLE tmpCastExpr_0 : UNSIGNED(7 DOWNTO 0);
BEGIN
tmpCastExpr_0 := UNSIGNED(endOfWordtimerCntr256) - UNSIGNED'(X"01");
IF timersRst = '1' OR ((NOT endOfWordDelayed AND data_vld) = '1' AND endOfWordtimerCntr256 = X"00") THEN
endOfWordtimerCntr256_next <= X"FF";
ELSIF (NOT endOfWordDelayed AND data_vld) = '1' THEN
endOfWordtimerCntr256_next <= STD_LOGIC_VECTOR(tmpCastExpr_0);
ELSE
endOfWordtimerCntr256_next <= endOfWordtimerCntr256;
END IF;
END PROCESS;
endOfWordtimerTick256 <= endOfWord;
assig_process_rxReg_next: PROCESS(clkIntern_next_rising, rxReg, slaveSelectWaitRequired, spi_miso)
BEGIN
IF (clkIntern_next_rising AND NOT slaveSelectWaitRequired) = '1' THEN
rxReg_next <= rxReg(6 DOWNTO 0) & spi_miso;
ELSE
rxReg_next <= rxReg;
END IF;
END PROCESS;
sig_csDecoder_din <= data_slave;
sig_csDecoder_en <= data_vld;
assig_process_slaveSelectWaitRequired_next: PROCESS(data_last, data_vld, endOfWordDelayed, endOfWordtimerCntr256, endOfWordtimerTick256, slaveSelectWaitRequired)
BEGIN
IF endOfWordtimerTick256 = '1' THEN
slaveSelectWaitRequired_next <= data_last;
ELSIF endOfWordtimerCntr256(6 DOWNTO 0) = "0000000" AND (NOT endOfWordDelayed AND data_vld) = '1' THEN
slaveSelectWaitRequired_next <= '0';
ELSE
slaveSelectWaitRequired_next <= slaveSelectWaitRequired;
END IF;
END PROCESS;
spi_clk <= clkOut;
spi_cs <= NOT sig_csDecoder_dout;
spi_mosi <= txReg(7);
timersRst <= '1' WHEN ((NOT endOfWordDelayed AND data_vld) = '0' OR (slaveSelectWaitRequired = '1' AND (endOfWordtimerCntr256(6 DOWNTO 0) = "0000000" AND (NOT endOfWordDelayed AND data_vld) = '1'))) ELSE '0';
assig_process_txInitialized: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
txInitialized <= '0';
slaveSelectWaitRequired <= '1';
endOfWordtimerCntr256 <= X"FF";
endOfWordDelayed <= '0';
clkOut <= '1';
clkIntern_next_edgeDetect_last <= '1';
clkIntern <= '1';
ELSE
txInitialized <= txInitialized_next;
slaveSelectWaitRequired <= slaveSelectWaitRequired_next;
endOfWordtimerCntr256 <= endOfWordtimerCntr256_next;
endOfWordDelayed <= endOfWordDelayed_next;
clkOut <= clkOut_next;
clkIntern_next_edgeDetect_last <= clkIntern_next_edgeDetect_last_next;
clkIntern <= clkIntern_next;
END IF;
END IF;
END PROCESS;
assig_process_txInitialized_next: PROCESS(clkIntern_next_falling, data_dout, endOfWordDelayed, slaveSelectWaitRequired, txInitialized, txReg)
BEGIN
IF (clkIntern_next_falling AND NOT slaveSelectWaitRequired) = '1' THEN
IF txInitialized = '1' THEN
txReg_next <= txReg(6 DOWNTO 0) & '0';
IF endOfWordDelayed = '1' THEN
txInitialized_next <= '0';
ELSE
txInitialized_next <= txInitialized;
END IF;
ELSE
txInitialized_next <= '1';
txReg_next <= data_dout;
END IF;
ELSIF endOfWordDelayed = '1' THEN
txInitialized_next <= '0';
txReg_next <= txReg;
ELSE
txInitialized_next <= txInitialized;
txReg_next <= txReg;
END IF;
END PROCESS;
assig_process_txReg: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
txReg <= txReg_next;
rxReg <= rxReg_next;
END IF;
END PROCESS;
ASSERT FREQ = 100000000 REPORT "Generated only for this value" SEVERITY failure;
ASSERT HAS_MISO = TRUE REPORT "Generated only for this value" SEVERITY failure;
ASSERT HAS_MOSI = TRUE REPORT "Generated only for this value" SEVERITY failure;
ASSERT HAS_RX = TRUE REPORT "Generated only for this value" SEVERITY failure;
ASSERT HAS_TX = TRUE REPORT "Generated only for this value" SEVERITY failure;
ASSERT SLAVE_CNT = 1 REPORT "Generated only for this value" SEVERITY failure;
ASSERT SPI_DATA_WIDTH = 1 REPORT "Generated only for this value" SEVERITY failure;
ASSERT SPI_FREQ_PESCALER = 32 REPORT "Generated only for this value" SEVERITY failure;
ASSERT SS_WAIT_CLK_TICKS = 4 REPORT "Generated only for this value" SEVERITY failure;
END ARCHITECTURE;
|
-------------------------------------------------------------------------------
-- system_microblaze_0_bram_block_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library microblaze_0_bram_block_elaborate_v1_00_a;
use microblaze_0_bram_block_elaborate_v1_00_a.all;
entity system_microblaze_0_bram_block_wrapper is
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to 3);
BRAM_Addr_A : in std_logic_vector(0 to 31);
BRAM_Din_A : out std_logic_vector(0 to 31);
BRAM_Dout_A : in std_logic_vector(0 to 31);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to 3);
BRAM_Addr_B : in std_logic_vector(0 to 31);
BRAM_Din_B : out std_logic_vector(0 to 31);
BRAM_Dout_B : in std_logic_vector(0 to 31)
);
attribute x_core_info : STRING;
attribute keep_hierarchy : STRING;
attribute x_core_info of system_microblaze_0_bram_block_wrapper : entity is "microblaze_0_bram_block_elaborate_v1_00_a";
attribute keep_hierarchy of system_microblaze_0_bram_block_wrapper : entity is "yes";
end system_microblaze_0_bram_block_wrapper;
architecture STRUCTURE of system_microblaze_0_bram_block_wrapper is
component microblaze_0_bram_block_elaborate is
generic (
C_MEMSIZE : integer;
C_PORT_DWIDTH : integer;
C_PORT_AWIDTH : integer;
C_NUM_WE : integer;
C_FAMILY : string
);
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
);
end component;
begin
microblaze_0_bram_block : microblaze_0_bram_block_elaborate
generic map (
C_MEMSIZE => 16#8000#,
C_PORT_DWIDTH => 32,
C_PORT_AWIDTH => 32,
C_NUM_WE => 4,
C_FAMILY => "spartan6"
)
port map (
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Rst_B => BRAM_Rst_B,
BRAM_Clk_B => BRAM_Clk_B,
BRAM_EN_B => BRAM_EN_B,
BRAM_WEN_B => BRAM_WEN_B,
BRAM_Addr_B => BRAM_Addr_B,
BRAM_Din_B => BRAM_Din_B,
BRAM_Dout_B => BRAM_Dout_B
);
end architecture STRUCTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity opcode_decoder is
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
OPCODE : IN std_logic_vector(7 downto 0);
OP_CYC : IN cycle; -- current cycle (M1, M2, ...)
INT : IN std_logic; -- interrupt
RRZ : IN std_logic; -- RR is zero
OP_CAT : OUT op_category;
-- select signals
D_SX : out std_logic_vector(1 downto 0); -- ALU select X
D_SY : out std_logic_vector(3 downto 0); -- ALU select Y
D_OP : out std_logic_vector(4 downto 0); -- ALU operation
D_SA : out std_logic_vector(4 downto 0); -- select address
D_SMQ : out std_logic;
-- write enable/select signal
D_WE_RR : out std_logic;
D_WE_LL : out std_logic;
D_WE_SP : out SP_OP;
D_RD_O : out std_logic;
D_WE_O : out std_logic;
D_LOCK : out std_logic;
-- input/output
D_IO : out std_logic;
PC_OP : out std_logic_vector(2 downto 0);
LAST_M : out std_logic; -- last M cycle of an opcode
HLT : out std_logic
);
end opcode_decoder;
architecture Behavioral of opcode_decoder is
function pc(A : std_logic;
OP : std_logic_vector(2 downto 0)) return std_logic_vector is
begin
if (A = '1') then return OP;
else return PC_NEXT;
end if;
end;
function hadr( A : std_logic;
ADR : std_logic_vector(4 downto 0)) return std_logic_vector is
begin
return ADR(4 downto 1) & A;
end;
function mix(A : std_logic) return std_logic_vector is
begin
if (A = '1') then return ALU_X_MIX_Y;
else return ALU_MOVE_Y;
end if;
end;
function sp(A : std_logic;
OP : SP_OP) return SP_OP is
begin
if (A = '1') then return OP;
else return SP_NOP;
end if;
end;
signal LAST : cycle;
signal ENABLE_INT : std_logic;
signal DISABLE_INT : std_logic;
signal DISABLE_CNT : std_logic_vector(3 downto 0);
signal HALT_REQ : std_logic;
signal UNHALT_REQ : std_logic;
signal HALTED : std_logic;
signal INT_M1 : std_logic;
signal INT_M2 : std_logic;
begin
LAST_M <= '1' when (OP_CYC = LAST) else '0';
HLT <= HALTED; -- show when CPU is halted
-- HLT <= '1' when DISABLE_CNT = 0 else '0'; -- show when ints enabled
process(CLK_I, CLR)
begin
if (CLR = '1') then
DISABLE_CNT <= "0001"; -- 1 x disabled
INT_M2 <= '0';
HALTED <= '0';
elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
if (DISABLE_INT = '1') then
DISABLE_CNT <= DISABLE_CNT + 1;
elsif (ENABLE_INT = '1' and DISABLE_CNT /= 0) then
DISABLE_CNT <= DISABLE_CNT - 1;
end if;
if (UNHALT_REQ = '1') then
HALTED <= '0';
elsif (HALT_REQ = '1') then
HALTED <= '1';
end if;
INT_M2 <= INT_M1;
end if;
end process;
process(OPCODE, OP_CYC, INT, RRZ, INT_M2, DISABLE_CNT, HALTED)
variable IS_M1 : std_logic;
variable IS_M2, IS_M1_M2 : std_logic;
variable IS_M3, IS_M2_M3 : std_logic;
variable IS_M4, IS_M3_M4 : std_logic;
variable IS_M5 : std_logic;
begin
if (OP_CYC = M1) then IS_M1 := '1'; else IS_M1 := '0'; end if;
if (OP_CYC = M2) then IS_M2 := '1'; else IS_M2 := '0'; end if;
if (OP_CYC = M3) then IS_M3 := '1'; else IS_M3 := '0'; end if;
if (OP_CYC = M4) then IS_M4 := '1'; else IS_M4 := '0'; end if;
if (OP_CYC = M5) then IS_M5 := '1'; else IS_M5 := '0'; end if;
IS_M1_M2 := IS_M1 or IS_M2;
IS_M2_M3 := IS_M2 or IS_M3;
IS_M3_M4 := IS_M3 or IS_M4;
-- default: NOP
--
OP_CAT <= undef;
D_SX <= SX_ANY;
D_SY <= SY_ANY;
D_OP <= "00000";
D_SA <= "00000";
D_SMQ <= '0';
D_WE_RR <= '0';
D_WE_LL <= '0';
D_WE_SP <= SP_NOP;
D_WE_O <= '0';
D_RD_O <= '0';
D_LOCK <= '0';
D_IO <= '0';
PC_OP <= PC_NEXT;
LAST <= M1; -- default: single cycle opcode (M1 only)
ENABLE_INT <= '0';
DISABLE_INT <= '0';
HALT_REQ <= '0';
UNHALT_REQ <= '0';
INT_M1 <= '0';
if ((IS_M1 = '1' and INT = '1' and DISABLE_CNT = "0000") -- new INT or
or INT_M2 = '1' ) then -- continue INT
OP_CAT <= INTR;
LAST <= M2;
INT_M1 <= IS_M1;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_PC;
D_SY <= SY_SY0; -- PC + 0 (current PC)
D_SA <= ADR_dSP;
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M1, PC_INT);
D_SMQ <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
DISABLE_INT <= IS_M1;
UNHALT_REQ <= '1';
elsif (HALTED = '1') then
OP_CAT <= HALT_WAIT;
LAST <= M2;
PC_OP <= PC_WAIT;
elsif (OPCODE(7) = '1') then
case OPCODE(6 downto 4) is
when "010" =>
OP_CAT <= ADD_RR_I;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_UQ;
D_WE_RR <= IS_M1;
when "011" =>
OP_CAT <= SUB_RR_I;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_UQ;
D_WE_RR <= IS_M1;
when "100" =>
OP_CAT <= MOVE_I_RR;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SQ;
D_WE_RR <= IS_M1;
when "101" =>
OP_CAT <= SEQ_LL_I;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_SQ;
D_WE_RR <= IS_M1; -- !! RR
when "110" =>
OP_CAT <= MOVE_I_LL;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UQ;
D_WE_LL <= IS_M1;
when "111" =>
case OPCODE(3 downto 0) is
when "0100" =>
OP_CAT <= ADD_RR_I;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3;
when "0101" =>
OP_CAT <= ADD_RR_I;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
LAST <= M2;
D_WE_RR <= IS_M2;
when "0110" =>
OP_CAT <= SUB_RR_I;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3;
when "0111" =>
OP_CAT <= SUB_RR_I;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
LAST <= M2;
D_WE_RR <= IS_M2;
when "1000" =>
OP_CAT <= MOVE_I_RR;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3;
when "1001" =>
OP_CAT <= MOVE_I_RR;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SI8;
LAST <= M2;
D_WE_RR <= IS_M2;
when "1010" =>
OP_CAT <= SEQ_LL_I;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3; -- SEQ sets RR !
when "1011" =>
OP_CAT <= SEQ_LL_I;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_SI8;
LAST <= M2;
D_WE_RR <= IS_M2; -- SEQ sets RR !
when "1100" =>
OP_CAT <= MOVE_I_LL;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_I16;
LAST <= M3;
D_WE_LL <= IS_M3;
when "1101" =>
OP_CAT <= MOVE_I_LL;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SI8;
LAST <= M2;
D_WE_LL <= IS_M2;
when others => -- undefined
end case;
when others => -- undefined
end case;
else
case OPCODE(6 downto 0) is
-- 00000000000000000000000000000000000000000000000000000000000000000000
when "0000000" =>
OP_CAT <= HALT;
HALT_REQ <= '1';
PC_OP <= PC_WAIT;
when "0000001" =>
OP_CAT <= NOP;
when "0000010" =>
OP_CAT <= JMP_i;
LAST <= M3;
PC_OP <= pc(IS_M2, PC_JMP);
when "0000011" =>
OP_CAT <= JMP_RRNZ_i;
LAST <= M3;
PC_OP <= pc(IS_M2 and not RRZ, PC_JMP);
when "0000100" =>
OP_CAT <= JMP_RRZ_i;
LAST <= M3;
PC_OP <= pc(IS_M2 and RRZ, PC_JMP);
when "0000101" =>
OP_CAT <= CALL_i;
LAST <= M3;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_PC;
D_SY <= SY_SY3; -- PC + 3
D_SA <= ADR_dSP;
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M2, PC_JMP);
D_SMQ <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
when "0000110" =>
OP_CAT <= CALL_RR;
LAST <= M2;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_PC;
D_SY <= SY_SY1; -- PC + 1
D_SA <= ADR_dSP;
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M1, PC_JPRR);
D_SMQ <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
when "0000111" | "1111000" =>
if (OPCODE(0) = '1') then
OP_CAT <= RET;
else
OP_CAT <= RETI;
ENABLE_INT <= IS_M1;
end if;
LAST <= M5;
D_SA <= ADR_SPi; -- read address: (SP)+
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_INC);
case OP_CYC is
when M1 => PC_OP <= PC_WAIT;
when M2 => PC_OP <= PC_WAIT;
when M3 => PC_OP <= PC_RETL;
when M4 => PC_OP <= PC_RETH;
when others =>
end case;
when "0001000" =>
OP_CAT <= MOVE_SPi_RR;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
LAST <= M3;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
D_WE_RR <= IS_M2_M3;
D_WE_SP <= sp(IS_M1_M2, SP_INC);
D_OP <= mix(IS_M3);
when "0001001" =>
OP_CAT <= MOVE_SPi_RS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
when "0001010" =>
OP_CAT <= MOVE_SPi_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
D_WE_RR <= IS_M2;
when "0001011" =>
OP_CAT <= MOVE_SPi_LL;
LAST <= M3;
D_SX <= SX_LL;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
D_WE_SP <= sp(IS_M1_M2, SP_INC);
D_WE_LL <= IS_M2_M3;
D_OP <= mix(IS_M3);
when "0001100" =>
OP_CAT <= MOVE_SPi_LS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
D_WE_LL <= IS_M2;
when "0001101" =>
OP_CAT <= MOVE_SPi_LU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
D_WE_LL <= IS_M2;
when "0001110" =>
OP_CAT <= MOVE_RR_dSP;
LAST <= M2;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
D_SMQ <= IS_M1;
when "0001111" =>
OP_CAT <= MOVE_R_dSP;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_O <= '1';
D_WE_SP <= SP_LOAD;
-- 11111111111111111111111111111111111111111111111111111111111111111111
when "0010000" =>
OP_CAT <= AND_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_AND_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010001" =>
OP_CAT <= AND_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_AND_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0010010" =>
OP_CAT <= OR_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010011" =>
OP_CAT <= OR_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0010100" =>
OP_CAT <= XOR_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_XOR_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010101" =>
OP_CAT <= XOR_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_XOR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0010110" =>
OP_CAT <= SEQ_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010111" =>
OP_CAT <= SEQ_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0011000" =>
OP_CAT <= SNE_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_NE_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011001" =>
OP_CAT <= SNE_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_NE_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0011010" =>
OP_CAT <= SGE_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_GE_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011011" =>
OP_CAT <= SGE_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_GE_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
when "0011100" =>
OP_CAT <= SGT_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_GT_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011101" =>
OP_CAT <= SGT_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_GT_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
when "0011110" =>
OP_CAT <= SLE_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LE_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011111" =>
OP_CAT <= SLE_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LE_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
-- 22222222222222222222222222222222222222222222222222222222222222222222
when "0100000" =>
OP_CAT <= SLT_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LT_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100001" =>
OP_CAT <= SLT_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LT_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
when "0100010" =>
OP_CAT <= SHS_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_HS_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100011" =>
OP_CAT <= SHS_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_HS_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0100100" =>
OP_CAT <= SHI_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_HI_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100101" =>
OP_CAT <= SHI_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_HI_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0100110" =>
OP_CAT <= SLS_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LS_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100111" =>
OP_CAT <= SLS_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LS_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0101000" =>
OP_CAT <= SLO_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LO_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0101001" =>
OP_CAT <= SLO_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LO_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0101010" =>
OP_CAT <= ADD_SP_I;
LAST <= M3; -- wait for ##
D_OP <= ALU_ANY;
D_SX <= SX_ANY;
D_SY <= SY_ANY;
D_SA <= ADR_16SP_L;
D_WE_SP <= sp(IS_M2, SP_LOAD);
when "0101011" =>
OP_CAT <= ADD_SP_I;
LAST <= M2; -- wait for #
D_OP <= ALU_ANY;
D_SX <= SX_ANY;
D_SY <= SY_ANY;
D_SA <= ADR_8SP_L;
D_WE_SP <= sp(IS_M1, SP_LOAD);
when "0101100" =>
OP_CAT <= CLRW_dSP;
LAST <= M2;
D_OP <= ALU_X_AND_Y;
D_SX <= SX_ANY;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_O <= '1';
D_LOCK <= IS_M1;
D_WE_SP <= SP_LOAD;
PC_OP <= pc(IS_M1, PC_WAIT);
when "0101101" =>
OP_CAT <= CLRB_dSP;
D_OP <= ALU_X_AND_Y;
D_SX <= SX_ANY;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_O <= IS_M1;
D_WE_SP <= SP_LOAD;
when "0101110" =>
OP_CAT <= IN_ci_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_IO;
D_RD_O <= IS_M1;
D_IO <= IS_M1;
D_WE_RR <= IS_M2;
when "0101111" =>
OP_CAT <= OUT_R_ci;
LAST <= M2;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_IO;
D_WE_O <= IS_M1;
D_IO <= IS_M1;
-- 33333333333333333333333333333333333333333333333333333333333333333333
when "0110000" =>
OP_CAT <= AND_LL_RR;
D_OP <= ALU_X_AND_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110001" =>
OP_CAT <= OR_LL_RR;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110010" =>
OP_CAT <= XOR_LL_RR;
D_OP <= ALU_X_XOR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110011" =>
OP_CAT <= SEQ_LL_RR;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110100" =>
OP_CAT <= SNE_LL_RR;
D_OP <= ALU_X_NE_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110101" =>
OP_CAT <= SGE_LL_RR;
D_OP <= ALU_X_GE_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110110" =>
OP_CAT <= SGT_LL_RR;
D_OP <= ALU_X_GT_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110111" =>
OP_CAT <= SLE_LL_RR;
D_OP <= ALU_X_LE_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111000" =>
OP_CAT <= SLT_LL_RR;
D_OP <= ALU_X_LT_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111001" =>
OP_CAT <= SHS_LL_RR;
D_OP <= ALU_X_HS_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111010" =>
OP_CAT <= SHI_LL_RR;
D_OP <= ALU_X_HI_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111011" =>
OP_CAT <= SLS_LL_RR;
D_OP <= ALU_X_LS_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111100" =>
OP_CAT <= SLO_LL_RR;
D_OP <= ALU_X_LO_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111101" =>
OP_CAT <= LNOT_RR;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_WE_RR <= IS_M1;
when "0111110" =>
OP_CAT <= NEG_RR;
D_OP <= ALU_NEG_Y;
D_SX <= SX_ANY;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111111" =>
OP_CAT <= NOT_RR;
D_OP <= ALU_NOT_Y;
D_SX <= SX_ANY;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
-- 44444444444444444444444444444444444444444444444444444444444444444444
when "1000000" =>
OP_CAT <= MOVE_LL_RR;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_SY0;
D_WE_RR <= IS_M1;
when "1000001" =>
OP_CAT <= MOVE_LL_cRR;
LAST <= M2;
PC_OP <= pc(IS_M1, PC_WAIT);
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_SY0;
D_SA <= hadr(IS_M2, ADR_cRR_H);
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_SMQ <= IS_M2;
when "1000010" =>
OP_CAT <= MOVE_L_cRR;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_SY0;
D_SA <= ADR_cRR_L;
D_WE_O <= IS_M1;
when "1000011" =>
OP_CAT <= MOVE_RR_LL;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_WE_LL <= IS_M1;
when "1000100" =>
OP_CAT <= MOVE_RR_cLL;
LAST <= M2;
PC_OP <= pc(IS_M1, PC_WAIT);
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= hadr(IS_M2, ADR_cLL_H);
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_SMQ <= IS_M2;
when "1000101" =>
OP_CAT <= MOVE_R_cLL;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_cLL_L;
D_WE_O <= IS_M1;
when "1000110" =>
OP_CAT <= MOVE_cRR_RR;
LAST <= M3;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_WE_RR <= not IS_M1; -- M2 or M3
PC_OP <= pc(IS_M1_M2, PC_WAIT);
D_OP <= mix(IS_M3);
D_SA <= hadr(IS_M2, ADR_cRR_H);
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
when "1000111" =>
OP_CAT <= MOVE_cRR_RS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_cRR_L;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
PC_OP <= pc(IS_M1, PC_WAIT);
when "1001000" =>
OP_CAT <= MOVE_cRR_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_cRR_L;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
PC_OP <= pc(IS_M1, PC_WAIT);
when "1001001" =>
OP_CAT <= MOVE_ci_RR;
LAST <= M4;
D_SX <= SX_RR;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M4);
D_WE_RR <= IS_M3_M4;
D_SA <= hadr(IS_M3, ADR_cI16_H);
D_RD_O <= IS_M2_M3;
D_LOCK <= IS_M2;
when "1001010" =>
OP_CAT <= MOVE_ci_RS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_cI16_L;
D_RD_O <= IS_M2;
D_WE_RR <= IS_M3;
when "1001011" =>
OP_CAT <= MOVE_ci_RU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_cI16_L;
D_RD_O <= IS_M2;
D_WE_RR <= IS_M3;
when "1001100" =>
OP_CAT <= MOVE_ci_LL;
LAST <= M4;
D_SX <= SX_LL;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M4);
D_SA <= hadr(IS_M3, ADR_cI16_H);
D_RD_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_WE_LL <= IS_M3_M4;
when "1001101" =>
OP_CAT <= MOVE_ci_LS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_cI16_L;
D_RD_O <= IS_M2;
D_WE_LL <= IS_M3;
when "1001110" =>
OP_CAT <= MOVE_ci_LU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_cI16_L;
D_RD_O <= IS_M2;
D_WE_LL <= IS_M3;
when "1001111" =>
OP_CAT <= MOVE_RR_SP;
D_SA <= ADR_cRR_L;
D_WE_SP <= SP_LOAD;
-- 55555555555555555555555555555555555555555555555555555555555555555555
when "1010000" =>
-- spare
when "1010001" =>
-- spare
when "1010010" =>
OP_CAT <= LSL_RR_i;
LAST <= M2;
D_OP <= ALU_X_LSL_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1010011" =>
OP_CAT <= ASR_RR_i;
LAST <= M2;
D_OP <= ALU_X_ASR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1010100" =>
OP_CAT <= LSR_RR_i;
LAST <= M2;
D_OP <= ALU_X_LSR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1010101" =>
OP_CAT <= LSL_LL_RR;
D_OP <= ALU_X_LSL_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1010110" =>
OP_CAT <= ASR_LL_RR;
D_OP <= ALU_X_ASR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1010111" =>
OP_CAT <= LSR_LL_RR;
D_OP <= ALU_X_LSR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1011000" =>
OP_CAT <= ADD_LL_RR;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1011001" =>
OP_CAT <= SUB_LL_RR;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1011010" =>
OP_CAT <= MOVE_RR_ci;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= hadr(IS_M3, ADR_cI16_H);
D_WE_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_SMQ <= IS_M3;
when "1011011" =>
OP_CAT <= MOVE_R_ci;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= ADR_cI16_L;
D_WE_O <= IS_M2;
when "1011100" => -- long offset / long move
OP_CAT <= MOVE_RR_uSP;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= hadr(IS_M3, ADR_16SP_H);
D_WE_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_SMQ <= IS_M3;
when "1011101" => -- short offset / long move
OP_CAT <= MOVE_RR_uSP;
LAST <= M2;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= hadr(IS_M2, ADR_8SP_H);
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_SMQ <= IS_M2;
when "1011110" => -- long offset / short move
OP_CAT <= MOVE_R_uSP;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= ADR_16SP_L;
D_WE_O <= IS_M2;
D_OP <= ALU_X_OR_Y;
when "1011111" => -- short offset / short move
OP_CAT <= MOVE_R_uSP;
LAST <= M2;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= ADR_8SP_L;
D_WE_O <= IS_M1;
D_OP <= ALU_X_OR_Y;
-- 66666666666666666666666666666666666666666666666666666666666666666666
when "1100000" => -- long offset, long move
OP_CAT <= MOVE_uSP_RR;
LAST <= M4;
D_SX <= SX_RR;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M3_M4);
D_SA <= hadr(IS_M3, ADR_16SP_H);
D_RD_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_WE_RR <= IS_M3_M4;
when "1100001" => -- short offset, long move
OP_CAT <= MOVE_uSP_RR;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_UM;
PC_OP <= pc(IS_M2, PC_WAIT);
D_OP <= mix(IS_M3);
D_SA <= hadr(IS_M2, ADR_8SP_H);
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_WE_RR <= IS_M2_M3;
when "1100010" => -- long offset, short move
OP_CAT <= MOVE_uSP_RS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_16SP_L;
D_RD_O <= IS_M2;
D_WE_RR <= IS_M3;
when "1100011" => -- short offset, short move
OP_CAT <= MOVE_uSP_RS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_8SP_L;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
when "1100100" => -- long offset, short move
OP_CAT <= MOVE_uSP_RU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_16SP_L;
D_RD_O <= IS_M2;
D_WE_RR <= IS_M3;
when "1100101" => -- short offset, short move
OP_CAT <= MOVE_uSP_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_8SP_L;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
when "1100110" => -- long offset, long move
OP_CAT <= MOVE_uSP_LL;
LAST <= M4;
D_SX <= SX_LL;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M4);
D_SA <= hadr(IS_M3, ADR_8SP_H);
D_RD_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_WE_LL <= IS_M3_M4;
when "1100111" => -- short offset, long move
OP_CAT <= MOVE_uSP_LL;
LAST <= M3;
D_SX <= SX_LL;
D_SY <= SY_UM;
PC_OP <= pc(IS_M2, PC_WAIT);
D_OP <= mix(IS_M3);
D_SA <= hadr(IS_M2, ADR_8SP_H);
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_WE_LL <= IS_M2_M3;
when "1101000" => -- long offset, short move
OP_CAT <= MOVE_uSP_LS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_16SP_L;
D_RD_O <= IS_M2;
D_WE_LL <= IS_M3;
when "1101001" => -- short offset, short move
OP_CAT <= MOVE_uSP_LS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_8SP_L;
D_RD_O <= IS_M1;
D_WE_LL <= IS_M2;
when "1101010" => -- long offset, short move
OP_CAT <= MOVE_uSP_LU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_16SP_L;
D_RD_O <= IS_M2;
D_WE_LL <= IS_M3;
when "1101011" => -- short offset, short move
OP_CAT <= MOVE_uSP_LU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_8SP_L;
D_RD_O <= IS_M1;
D_WE_LL <= IS_M2;
when "1101100" =>
OP_CAT <= LEA_uSP_RR;
LAST <= M3;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_SP;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "1101101" =>
OP_CAT <= LEA_uSP_RR;
LAST <= M2;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_SP;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1101110" =>
OP_CAT <= MOVE_dRR_dLL;
LAST <= M3;
D_WE_RR <= IS_M1;
D_RD_O <= IS_M1;
D_WE_O <= IS_M2;
D_WE_LL <= IS_M3;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
case OP_CYC is
when M1 => -- decrement RR
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_SY1;
D_SA <= ADR_dRR;
when M2 => -- write read memory
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_dLL;
when others => -- decrement LL
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_LL;
D_SY <= SY_SY1;
end case;
when "1101111" =>
OP_CAT <= MOVE_RRi_LLi;
LAST <= M3;
D_WE_RR <= IS_M1;
D_RD_O <= IS_M1;
D_WE_O <= IS_M2;
D_WE_LL <= IS_M3;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
case OP_CYC is
when M1 => -- decrement RR
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_SY1;
D_SA <= ADR_RRi;
when M2 => -- write read memory
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_dLL;
when others => -- decrement LL
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_LL;
D_SY <= SY_SY1;
end case;
-- 77777777777777777777777777777777777777777777777777777777777777777777
when "1110000" =>
OP_CAT <= MUL_IS;
D_OP <= ALU_MUL_IS;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110001" =>
OP_CAT <= MUL_IU;
D_OP <= ALU_MUL_IU;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110010" =>
OP_CAT <= DIV_IS;
D_OP <= ALU_DIV_IS;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110011" =>
OP_CAT <= DIV_IU;
D_OP <= ALU_DIV_IU;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110100" =>
OP_CAT <= MD_STEP;
D_OP <= ALU_MD_STP;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110101" =>
OP_CAT <= MD_FIN;
D_OP <= ALU_MD_FIN;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110110" =>
OP_CAT <= MOD_FIN;
D_OP <= ALU_MOD_FIN;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110111" =>
OP_CAT <= EI;
ENABLE_INT <= IS_M1;
when "1111001" =>
OP_CAT <= DI;
DISABLE_INT <= IS_M1;
-- undefined --------------------------------------------------------
when others =>
end case;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity opcode_decoder is
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
OPCODE : IN std_logic_vector(7 downto 0);
OP_CYC : IN cycle; -- current cycle (M1, M2, ...)
INT : IN std_logic; -- interrupt
RRZ : IN std_logic; -- RR is zero
OP_CAT : OUT op_category;
-- select signals
D_SX : out std_logic_vector(1 downto 0); -- ALU select X
D_SY : out std_logic_vector(3 downto 0); -- ALU select Y
D_OP : out std_logic_vector(4 downto 0); -- ALU operation
D_SA : out std_logic_vector(4 downto 0); -- select address
D_SMQ : out std_logic;
-- write enable/select signal
D_WE_RR : out std_logic;
D_WE_LL : out std_logic;
D_WE_SP : out SP_OP;
D_RD_O : out std_logic;
D_WE_O : out std_logic;
D_LOCK : out std_logic;
-- input/output
D_IO : out std_logic;
PC_OP : out std_logic_vector(2 downto 0);
LAST_M : out std_logic; -- last M cycle of an opcode
HLT : out std_logic
);
end opcode_decoder;
architecture Behavioral of opcode_decoder is
function pc(A : std_logic;
OP : std_logic_vector(2 downto 0)) return std_logic_vector is
begin
if (A = '1') then return OP;
else return PC_NEXT;
end if;
end;
function hadr( A : std_logic;
ADR : std_logic_vector(4 downto 0)) return std_logic_vector is
begin
return ADR(4 downto 1) & A;
end;
function mix(A : std_logic) return std_logic_vector is
begin
if (A = '1') then return ALU_X_MIX_Y;
else return ALU_MOVE_Y;
end if;
end;
function sp(A : std_logic;
OP : SP_OP) return SP_OP is
begin
if (A = '1') then return OP;
else return SP_NOP;
end if;
end;
signal LAST : cycle;
signal ENABLE_INT : std_logic;
signal DISABLE_INT : std_logic;
signal DISABLE_CNT : std_logic_vector(3 downto 0);
signal HALT_REQ : std_logic;
signal UNHALT_REQ : std_logic;
signal HALTED : std_logic;
signal INT_M1 : std_logic;
signal INT_M2 : std_logic;
begin
LAST_M <= '1' when (OP_CYC = LAST) else '0';
HLT <= HALTED; -- show when CPU is halted
-- HLT <= '1' when DISABLE_CNT = 0 else '0'; -- show when ints enabled
process(CLK_I, CLR)
begin
if (CLR = '1') then
DISABLE_CNT <= "0001"; -- 1 x disabled
INT_M2 <= '0';
HALTED <= '0';
elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
if (DISABLE_INT = '1') then
DISABLE_CNT <= DISABLE_CNT + 1;
elsif (ENABLE_INT = '1' and DISABLE_CNT /= 0) then
DISABLE_CNT <= DISABLE_CNT - 1;
end if;
if (UNHALT_REQ = '1') then
HALTED <= '0';
elsif (HALT_REQ = '1') then
HALTED <= '1';
end if;
INT_M2 <= INT_M1;
end if;
end process;
process(OPCODE, OP_CYC, INT, RRZ, INT_M2, DISABLE_CNT, HALTED)
variable IS_M1 : std_logic;
variable IS_M2, IS_M1_M2 : std_logic;
variable IS_M3, IS_M2_M3 : std_logic;
variable IS_M4, IS_M3_M4 : std_logic;
variable IS_M5 : std_logic;
begin
if (OP_CYC = M1) then IS_M1 := '1'; else IS_M1 := '0'; end if;
if (OP_CYC = M2) then IS_M2 := '1'; else IS_M2 := '0'; end if;
if (OP_CYC = M3) then IS_M3 := '1'; else IS_M3 := '0'; end if;
if (OP_CYC = M4) then IS_M4 := '1'; else IS_M4 := '0'; end if;
if (OP_CYC = M5) then IS_M5 := '1'; else IS_M5 := '0'; end if;
IS_M1_M2 := IS_M1 or IS_M2;
IS_M2_M3 := IS_M2 or IS_M3;
IS_M3_M4 := IS_M3 or IS_M4;
-- default: NOP
--
OP_CAT <= undef;
D_SX <= SX_ANY;
D_SY <= SY_ANY;
D_OP <= "00000";
D_SA <= "00000";
D_SMQ <= '0';
D_WE_RR <= '0';
D_WE_LL <= '0';
D_WE_SP <= SP_NOP;
D_WE_O <= '0';
D_RD_O <= '0';
D_LOCK <= '0';
D_IO <= '0';
PC_OP <= PC_NEXT;
LAST <= M1; -- default: single cycle opcode (M1 only)
ENABLE_INT <= '0';
DISABLE_INT <= '0';
HALT_REQ <= '0';
UNHALT_REQ <= '0';
INT_M1 <= '0';
if ((IS_M1 = '1' and INT = '1' and DISABLE_CNT = "0000") -- new INT or
or INT_M2 = '1' ) then -- continue INT
OP_CAT <= INTR;
LAST <= M2;
INT_M1 <= IS_M1;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_PC;
D_SY <= SY_SY0; -- PC + 0 (current PC)
D_SA <= ADR_dSP;
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M1, PC_INT);
D_SMQ <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
DISABLE_INT <= IS_M1;
UNHALT_REQ <= '1';
elsif (HALTED = '1') then
OP_CAT <= HALT_WAIT;
LAST <= M2;
PC_OP <= PC_WAIT;
elsif (OPCODE(7) = '1') then
case OPCODE(6 downto 4) is
when "010" =>
OP_CAT <= ADD_RR_I;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_UQ;
D_WE_RR <= IS_M1;
when "011" =>
OP_CAT <= SUB_RR_I;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_UQ;
D_WE_RR <= IS_M1;
when "100" =>
OP_CAT <= MOVE_I_RR;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SQ;
D_WE_RR <= IS_M1;
when "101" =>
OP_CAT <= SEQ_LL_I;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_SQ;
D_WE_RR <= IS_M1; -- !! RR
when "110" =>
OP_CAT <= MOVE_I_LL;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UQ;
D_WE_LL <= IS_M1;
when "111" =>
case OPCODE(3 downto 0) is
when "0100" =>
OP_CAT <= ADD_RR_I;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3;
when "0101" =>
OP_CAT <= ADD_RR_I;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
LAST <= M2;
D_WE_RR <= IS_M2;
when "0110" =>
OP_CAT <= SUB_RR_I;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3;
when "0111" =>
OP_CAT <= SUB_RR_I;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
LAST <= M2;
D_WE_RR <= IS_M2;
when "1000" =>
OP_CAT <= MOVE_I_RR;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3;
when "1001" =>
OP_CAT <= MOVE_I_RR;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SI8;
LAST <= M2;
D_WE_RR <= IS_M2;
when "1010" =>
OP_CAT <= SEQ_LL_I;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3; -- SEQ sets RR !
when "1011" =>
OP_CAT <= SEQ_LL_I;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_SI8;
LAST <= M2;
D_WE_RR <= IS_M2; -- SEQ sets RR !
when "1100" =>
OP_CAT <= MOVE_I_LL;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_I16;
LAST <= M3;
D_WE_LL <= IS_M3;
when "1101" =>
OP_CAT <= MOVE_I_LL;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SI8;
LAST <= M2;
D_WE_LL <= IS_M2;
when others => -- undefined
end case;
when others => -- undefined
end case;
else
case OPCODE(6 downto 0) is
-- 00000000000000000000000000000000000000000000000000000000000000000000
when "0000000" =>
OP_CAT <= HALT;
HALT_REQ <= '1';
PC_OP <= PC_WAIT;
when "0000001" =>
OP_CAT <= NOP;
when "0000010" =>
OP_CAT <= JMP_i;
LAST <= M3;
PC_OP <= pc(IS_M2, PC_JMP);
when "0000011" =>
OP_CAT <= JMP_RRNZ_i;
LAST <= M3;
PC_OP <= pc(IS_M2 and not RRZ, PC_JMP);
when "0000100" =>
OP_CAT <= JMP_RRZ_i;
LAST <= M3;
PC_OP <= pc(IS_M2 and RRZ, PC_JMP);
when "0000101" =>
OP_CAT <= CALL_i;
LAST <= M3;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_PC;
D_SY <= SY_SY3; -- PC + 3
D_SA <= ADR_dSP;
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M2, PC_JMP);
D_SMQ <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
when "0000110" =>
OP_CAT <= CALL_RR;
LAST <= M2;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_PC;
D_SY <= SY_SY1; -- PC + 1
D_SA <= ADR_dSP;
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M1, PC_JPRR);
D_SMQ <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
when "0000111" | "1111000" =>
if (OPCODE(0) = '1') then
OP_CAT <= RET;
else
OP_CAT <= RETI;
ENABLE_INT <= IS_M1;
end if;
LAST <= M5;
D_SA <= ADR_SPi; -- read address: (SP)+
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_INC);
case OP_CYC is
when M1 => PC_OP <= PC_WAIT;
when M2 => PC_OP <= PC_WAIT;
when M3 => PC_OP <= PC_RETL;
when M4 => PC_OP <= PC_RETH;
when others =>
end case;
when "0001000" =>
OP_CAT <= MOVE_SPi_RR;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
LAST <= M3;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
D_WE_RR <= IS_M2_M3;
D_WE_SP <= sp(IS_M1_M2, SP_INC);
D_OP <= mix(IS_M3);
when "0001001" =>
OP_CAT <= MOVE_SPi_RS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
when "0001010" =>
OP_CAT <= MOVE_SPi_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
D_WE_RR <= IS_M2;
when "0001011" =>
OP_CAT <= MOVE_SPi_LL;
LAST <= M3;
D_SX <= SX_LL;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
D_WE_SP <= sp(IS_M1_M2, SP_INC);
D_WE_LL <= IS_M2_M3;
D_OP <= mix(IS_M3);
when "0001100" =>
OP_CAT <= MOVE_SPi_LS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
D_WE_LL <= IS_M2;
when "0001101" =>
OP_CAT <= MOVE_SPi_LU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
D_WE_LL <= IS_M2;
when "0001110" =>
OP_CAT <= MOVE_RR_dSP;
LAST <= M2;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
D_SMQ <= IS_M1;
when "0001111" =>
OP_CAT <= MOVE_R_dSP;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_O <= '1';
D_WE_SP <= SP_LOAD;
-- 11111111111111111111111111111111111111111111111111111111111111111111
when "0010000" =>
OP_CAT <= AND_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_AND_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010001" =>
OP_CAT <= AND_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_AND_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0010010" =>
OP_CAT <= OR_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010011" =>
OP_CAT <= OR_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0010100" =>
OP_CAT <= XOR_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_XOR_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010101" =>
OP_CAT <= XOR_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_XOR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0010110" =>
OP_CAT <= SEQ_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010111" =>
OP_CAT <= SEQ_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0011000" =>
OP_CAT <= SNE_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_NE_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011001" =>
OP_CAT <= SNE_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_NE_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0011010" =>
OP_CAT <= SGE_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_GE_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011011" =>
OP_CAT <= SGE_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_GE_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
when "0011100" =>
OP_CAT <= SGT_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_GT_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011101" =>
OP_CAT <= SGT_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_GT_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
when "0011110" =>
OP_CAT <= SLE_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LE_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011111" =>
OP_CAT <= SLE_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LE_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
-- 22222222222222222222222222222222222222222222222222222222222222222222
when "0100000" =>
OP_CAT <= SLT_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LT_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100001" =>
OP_CAT <= SLT_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LT_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
when "0100010" =>
OP_CAT <= SHS_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_HS_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100011" =>
OP_CAT <= SHS_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_HS_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0100100" =>
OP_CAT <= SHI_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_HI_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100101" =>
OP_CAT <= SHI_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_HI_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0100110" =>
OP_CAT <= SLS_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LS_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100111" =>
OP_CAT <= SLS_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LS_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0101000" =>
OP_CAT <= SLO_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LO_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0101001" =>
OP_CAT <= SLO_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LO_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0101010" =>
OP_CAT <= ADD_SP_I;
LAST <= M3; -- wait for ##
D_OP <= ALU_ANY;
D_SX <= SX_ANY;
D_SY <= SY_ANY;
D_SA <= ADR_16SP_L;
D_WE_SP <= sp(IS_M2, SP_LOAD);
when "0101011" =>
OP_CAT <= ADD_SP_I;
LAST <= M2; -- wait for #
D_OP <= ALU_ANY;
D_SX <= SX_ANY;
D_SY <= SY_ANY;
D_SA <= ADR_8SP_L;
D_WE_SP <= sp(IS_M1, SP_LOAD);
when "0101100" =>
OP_CAT <= CLRW_dSP;
LAST <= M2;
D_OP <= ALU_X_AND_Y;
D_SX <= SX_ANY;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_O <= '1';
D_LOCK <= IS_M1;
D_WE_SP <= SP_LOAD;
PC_OP <= pc(IS_M1, PC_WAIT);
when "0101101" =>
OP_CAT <= CLRB_dSP;
D_OP <= ALU_X_AND_Y;
D_SX <= SX_ANY;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_O <= IS_M1;
D_WE_SP <= SP_LOAD;
when "0101110" =>
OP_CAT <= IN_ci_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_IO;
D_RD_O <= IS_M1;
D_IO <= IS_M1;
D_WE_RR <= IS_M2;
when "0101111" =>
OP_CAT <= OUT_R_ci;
LAST <= M2;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_IO;
D_WE_O <= IS_M1;
D_IO <= IS_M1;
-- 33333333333333333333333333333333333333333333333333333333333333333333
when "0110000" =>
OP_CAT <= AND_LL_RR;
D_OP <= ALU_X_AND_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110001" =>
OP_CAT <= OR_LL_RR;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110010" =>
OP_CAT <= XOR_LL_RR;
D_OP <= ALU_X_XOR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110011" =>
OP_CAT <= SEQ_LL_RR;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110100" =>
OP_CAT <= SNE_LL_RR;
D_OP <= ALU_X_NE_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110101" =>
OP_CAT <= SGE_LL_RR;
D_OP <= ALU_X_GE_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110110" =>
OP_CAT <= SGT_LL_RR;
D_OP <= ALU_X_GT_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110111" =>
OP_CAT <= SLE_LL_RR;
D_OP <= ALU_X_LE_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111000" =>
OP_CAT <= SLT_LL_RR;
D_OP <= ALU_X_LT_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111001" =>
OP_CAT <= SHS_LL_RR;
D_OP <= ALU_X_HS_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111010" =>
OP_CAT <= SHI_LL_RR;
D_OP <= ALU_X_HI_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111011" =>
OP_CAT <= SLS_LL_RR;
D_OP <= ALU_X_LS_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111100" =>
OP_CAT <= SLO_LL_RR;
D_OP <= ALU_X_LO_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111101" =>
OP_CAT <= LNOT_RR;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_WE_RR <= IS_M1;
when "0111110" =>
OP_CAT <= NEG_RR;
D_OP <= ALU_NEG_Y;
D_SX <= SX_ANY;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111111" =>
OP_CAT <= NOT_RR;
D_OP <= ALU_NOT_Y;
D_SX <= SX_ANY;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
-- 44444444444444444444444444444444444444444444444444444444444444444444
when "1000000" =>
OP_CAT <= MOVE_LL_RR;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_SY0;
D_WE_RR <= IS_M1;
when "1000001" =>
OP_CAT <= MOVE_LL_cRR;
LAST <= M2;
PC_OP <= pc(IS_M1, PC_WAIT);
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_SY0;
D_SA <= hadr(IS_M2, ADR_cRR_H);
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_SMQ <= IS_M2;
when "1000010" =>
OP_CAT <= MOVE_L_cRR;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_SY0;
D_SA <= ADR_cRR_L;
D_WE_O <= IS_M1;
when "1000011" =>
OP_CAT <= MOVE_RR_LL;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_WE_LL <= IS_M1;
when "1000100" =>
OP_CAT <= MOVE_RR_cLL;
LAST <= M2;
PC_OP <= pc(IS_M1, PC_WAIT);
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= hadr(IS_M2, ADR_cLL_H);
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_SMQ <= IS_M2;
when "1000101" =>
OP_CAT <= MOVE_R_cLL;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_cLL_L;
D_WE_O <= IS_M1;
when "1000110" =>
OP_CAT <= MOVE_cRR_RR;
LAST <= M3;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_WE_RR <= not IS_M1; -- M2 or M3
PC_OP <= pc(IS_M1_M2, PC_WAIT);
D_OP <= mix(IS_M3);
D_SA <= hadr(IS_M2, ADR_cRR_H);
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
when "1000111" =>
OP_CAT <= MOVE_cRR_RS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_cRR_L;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
PC_OP <= pc(IS_M1, PC_WAIT);
when "1001000" =>
OP_CAT <= MOVE_cRR_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_cRR_L;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
PC_OP <= pc(IS_M1, PC_WAIT);
when "1001001" =>
OP_CAT <= MOVE_ci_RR;
LAST <= M4;
D_SX <= SX_RR;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M4);
D_WE_RR <= IS_M3_M4;
D_SA <= hadr(IS_M3, ADR_cI16_H);
D_RD_O <= IS_M2_M3;
D_LOCK <= IS_M2;
when "1001010" =>
OP_CAT <= MOVE_ci_RS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_cI16_L;
D_RD_O <= IS_M2;
D_WE_RR <= IS_M3;
when "1001011" =>
OP_CAT <= MOVE_ci_RU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_cI16_L;
D_RD_O <= IS_M2;
D_WE_RR <= IS_M3;
when "1001100" =>
OP_CAT <= MOVE_ci_LL;
LAST <= M4;
D_SX <= SX_LL;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M4);
D_SA <= hadr(IS_M3, ADR_cI16_H);
D_RD_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_WE_LL <= IS_M3_M4;
when "1001101" =>
OP_CAT <= MOVE_ci_LS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_cI16_L;
D_RD_O <= IS_M2;
D_WE_LL <= IS_M3;
when "1001110" =>
OP_CAT <= MOVE_ci_LU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_cI16_L;
D_RD_O <= IS_M2;
D_WE_LL <= IS_M3;
when "1001111" =>
OP_CAT <= MOVE_RR_SP;
D_SA <= ADR_cRR_L;
D_WE_SP <= SP_LOAD;
-- 55555555555555555555555555555555555555555555555555555555555555555555
when "1010000" =>
-- spare
when "1010001" =>
-- spare
when "1010010" =>
OP_CAT <= LSL_RR_i;
LAST <= M2;
D_OP <= ALU_X_LSL_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1010011" =>
OP_CAT <= ASR_RR_i;
LAST <= M2;
D_OP <= ALU_X_ASR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1010100" =>
OP_CAT <= LSR_RR_i;
LAST <= M2;
D_OP <= ALU_X_LSR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1010101" =>
OP_CAT <= LSL_LL_RR;
D_OP <= ALU_X_LSL_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1010110" =>
OP_CAT <= ASR_LL_RR;
D_OP <= ALU_X_ASR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1010111" =>
OP_CAT <= LSR_LL_RR;
D_OP <= ALU_X_LSR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1011000" =>
OP_CAT <= ADD_LL_RR;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1011001" =>
OP_CAT <= SUB_LL_RR;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1011010" =>
OP_CAT <= MOVE_RR_ci;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= hadr(IS_M3, ADR_cI16_H);
D_WE_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_SMQ <= IS_M3;
when "1011011" =>
OP_CAT <= MOVE_R_ci;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= ADR_cI16_L;
D_WE_O <= IS_M2;
when "1011100" => -- long offset / long move
OP_CAT <= MOVE_RR_uSP;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= hadr(IS_M3, ADR_16SP_H);
D_WE_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_SMQ <= IS_M3;
when "1011101" => -- short offset / long move
OP_CAT <= MOVE_RR_uSP;
LAST <= M2;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= hadr(IS_M2, ADR_8SP_H);
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_SMQ <= IS_M2;
when "1011110" => -- long offset / short move
OP_CAT <= MOVE_R_uSP;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= ADR_16SP_L;
D_WE_O <= IS_M2;
D_OP <= ALU_X_OR_Y;
when "1011111" => -- short offset / short move
OP_CAT <= MOVE_R_uSP;
LAST <= M2;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= ADR_8SP_L;
D_WE_O <= IS_M1;
D_OP <= ALU_X_OR_Y;
-- 66666666666666666666666666666666666666666666666666666666666666666666
when "1100000" => -- long offset, long move
OP_CAT <= MOVE_uSP_RR;
LAST <= M4;
D_SX <= SX_RR;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M3_M4);
D_SA <= hadr(IS_M3, ADR_16SP_H);
D_RD_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_WE_RR <= IS_M3_M4;
when "1100001" => -- short offset, long move
OP_CAT <= MOVE_uSP_RR;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_UM;
PC_OP <= pc(IS_M2, PC_WAIT);
D_OP <= mix(IS_M3);
D_SA <= hadr(IS_M2, ADR_8SP_H);
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_WE_RR <= IS_M2_M3;
when "1100010" => -- long offset, short move
OP_CAT <= MOVE_uSP_RS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_16SP_L;
D_RD_O <= IS_M2;
D_WE_RR <= IS_M3;
when "1100011" => -- short offset, short move
OP_CAT <= MOVE_uSP_RS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_8SP_L;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
when "1100100" => -- long offset, short move
OP_CAT <= MOVE_uSP_RU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_16SP_L;
D_RD_O <= IS_M2;
D_WE_RR <= IS_M3;
when "1100101" => -- short offset, short move
OP_CAT <= MOVE_uSP_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_8SP_L;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
when "1100110" => -- long offset, long move
OP_CAT <= MOVE_uSP_LL;
LAST <= M4;
D_SX <= SX_LL;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M4);
D_SA <= hadr(IS_M3, ADR_8SP_H);
D_RD_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_WE_LL <= IS_M3_M4;
when "1100111" => -- short offset, long move
OP_CAT <= MOVE_uSP_LL;
LAST <= M3;
D_SX <= SX_LL;
D_SY <= SY_UM;
PC_OP <= pc(IS_M2, PC_WAIT);
D_OP <= mix(IS_M3);
D_SA <= hadr(IS_M2, ADR_8SP_H);
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_WE_LL <= IS_M2_M3;
when "1101000" => -- long offset, short move
OP_CAT <= MOVE_uSP_LS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_16SP_L;
D_RD_O <= IS_M2;
D_WE_LL <= IS_M3;
when "1101001" => -- short offset, short move
OP_CAT <= MOVE_uSP_LS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_8SP_L;
D_RD_O <= IS_M1;
D_WE_LL <= IS_M2;
when "1101010" => -- long offset, short move
OP_CAT <= MOVE_uSP_LU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_16SP_L;
D_RD_O <= IS_M2;
D_WE_LL <= IS_M3;
when "1101011" => -- short offset, short move
OP_CAT <= MOVE_uSP_LU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_8SP_L;
D_RD_O <= IS_M1;
D_WE_LL <= IS_M2;
when "1101100" =>
OP_CAT <= LEA_uSP_RR;
LAST <= M3;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_SP;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "1101101" =>
OP_CAT <= LEA_uSP_RR;
LAST <= M2;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_SP;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1101110" =>
OP_CAT <= MOVE_dRR_dLL;
LAST <= M3;
D_WE_RR <= IS_M1;
D_RD_O <= IS_M1;
D_WE_O <= IS_M2;
D_WE_LL <= IS_M3;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
case OP_CYC is
when M1 => -- decrement RR
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_SY1;
D_SA <= ADR_dRR;
when M2 => -- write read memory
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_dLL;
when others => -- decrement LL
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_LL;
D_SY <= SY_SY1;
end case;
when "1101111" =>
OP_CAT <= MOVE_RRi_LLi;
LAST <= M3;
D_WE_RR <= IS_M1;
D_RD_O <= IS_M1;
D_WE_O <= IS_M2;
D_WE_LL <= IS_M3;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
case OP_CYC is
when M1 => -- decrement RR
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_SY1;
D_SA <= ADR_RRi;
when M2 => -- write read memory
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_dLL;
when others => -- decrement LL
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_LL;
D_SY <= SY_SY1;
end case;
-- 77777777777777777777777777777777777777777777777777777777777777777777
when "1110000" =>
OP_CAT <= MUL_IS;
D_OP <= ALU_MUL_IS;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110001" =>
OP_CAT <= MUL_IU;
D_OP <= ALU_MUL_IU;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110010" =>
OP_CAT <= DIV_IS;
D_OP <= ALU_DIV_IS;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110011" =>
OP_CAT <= DIV_IU;
D_OP <= ALU_DIV_IU;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110100" =>
OP_CAT <= MD_STEP;
D_OP <= ALU_MD_STP;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110101" =>
OP_CAT <= MD_FIN;
D_OP <= ALU_MD_FIN;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110110" =>
OP_CAT <= MOD_FIN;
D_OP <= ALU_MOD_FIN;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110111" =>
OP_CAT <= EI;
ENABLE_INT <= IS_M1;
when "1111001" =>
OP_CAT <= DI;
DISABLE_INT <= IS_M1;
-- undefined --------------------------------------------------------
when others =>
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
--
-- Takes all the VHDL bits and makes a 6510 (6502) out of them
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity chip6502 is
port (
a : out std_logic_vector(15 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
pi : in std_logic_vector(7 downto 0);
po : out std_logic_vector(7 downto 0);
r1w0 : out std_logic;
sync : out std_logic;
nmi0 : in std_logic;
irq0 : in std_logic;
so0 : in std_logic;
rdy : in std_logic;
res0 : in std_logic;
ph4Xin : in std_logic; -- clock input
ph0 : out std_logic;
ph1 : out std_logic; -- clock on high edge
ph2 : out std_logic -- clock on low edge
);
end chip6502;
architecture interaction of chip6502 is
subtype slv2 is std_logic_vector(1 downto 0);
subtype u8 is unsigned(7 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype word is std_logic_vector(15 downto 0);
constant v_nmi_l : word := x"FFFA";
constant v_nmi_h : word := x"FFFB";
constant v_res_l : word := x"FFFC";
constant v_res_h : word := x"FFFD";
constant v_irq_l : word := x"FFFE";
constant v_irq_h : word := x"FFFF";
component clockgen
port (
ph4Xin : in std_logic;
ph0 : out std_logic;
ph1 : out std_logic;
ph2 : out std_logic;
stg : out slv2;
res0 : in std_logic
);
end component;
subtype clkstg_t is std_logic_vector(1 downto 0);
signal clkStg : clkstg_t;
signal iph0 : std_logic;
signal iph1 : std_logic;
signal iph2 : std_logic;
constant sysclk_PH2_p : clkstg_t := "00";
constant sysclk_PH2_m : clkstg_t := "01";
constant sysclk_PH1_p : clkstg_t := "10";
constant sysclk_PH1_m : clkstg_t := "11";
component ioport8bit is
port (
ce : in std_logic;
clk : in std_logic;
res0 : in std_logic;
r1w0 : in std_logic;
a : in std_logic;
din : in byte;
dout : out byte;
ioi : in byte;
ioo : out byte
);
end component;
signal io_o : byte;
signal io_i : byte;
signal io_ce : std_logic;
signal io_clk : std_logic;
component alu_8bit
port (
a_in : in byte;
b_in : in byte;
c_in : in std_logic;
d_in : in std_logic; -- the dreaded BCD mode
op_in : in unsigned(2 downto 0);
n_out : out std_logic;
v_out : out std_logic;
z_out : out std_logic;
c_out : out std_logic;
r_out : out byte
);
end component;
signal ALUcin : std_logic;
signal ALUdin : std_logic;
signal ALUain : byte;
signal ALUbin : byte;
signal ALUop : unsigned(2 downto 0);
signal ALUrout : byte;
signal ALUnout : std_logic;
signal ALUvout : std_logic;
signal ALUzout : std_logic;
signal ALUcout : std_logic;
signal regbus : byte;
signal outval : byte;
signal abus : word;
signal DBen : std_logic := '1';
signal DBrw : std_logic := '1';
signal dbRE : std_logic;
signal dbWE : std_logic;
signal nDBen : std_logic;
signal aen0 : std_logic := '1';
signal aen1 : std_logic;
alias abus_off is aen0;
subtype seqType is byte;
function countSeq(src : seqType) return seqType is
variable v : unsigned(7 downto 0);
begin
v := unsigned(src);
v := v + 1;
return seqType(v);
end countSeq;
signal seq : seqType := x"00";
subtype dbctl_t is std_logic_vector(2 downto 0);
signal DB_ctl : dbctl_t := "011";
alias dbctl_sync : std_logic is DB_ctl(2);
alias dbctl_off : std_logic is DB_ctl(1);
alias dbctl_r1w0 : std_logic is DB_ctl(0);
subtype aop_t is std_logic_vector(2 downto 0);
signal aop : aop_t := "000";
constant aop_add : aop_t := "000";
constant aop_and : aop_t := "001";
constant aop_or : aop_t := "010";
constant aop_xor : aop_t := "011";
constant aop_lsl : aop_t := "100";
constant aop_lsr : aop_t := "101";
constant aop_rol : aop_t := "110";
constant aop_ror : aop_t := "111";
signal alu_bin_mode : slv2;
constant bin_reg : slv2 := "00";
constant bin_set : slv2 := "01";
constant bin_clr : slv2 := "10";
constant bin_ireg : slv2 := "11";
signal alu_cin_mode : slv2;
constant cin_psw : slv2 := "00";
constant cin_set : slv2 := "01";
constant cin_clr : slv2 := "10";
constant cin_aux : slv2 := "11";
signal alu_din_mode : std_logic;
constant din_clr : std_logic := '0';
constant din_psw : std_logic := '1';
--signal alu_bin_reg : byte;
alias alu_bin_reg : byte is ALUbin;
signal alu_bin_tie : byte;
type stage_t is (
stg_reset,
stg_fetch,
stg_sub_incpc, -- pc++
stg_sub_imm, -- mem=pc++
stg_sub_abs, -- meml=[pc++], memh=[pc++]
stg_sub_absx, -- meml=[X+(PC++)], memh=[C+(PC++)]
stg_sub_absy, -- meml=[Y+(PC++)], memh=[C+(PC++)]
stg_sub_zp, -- meml=[PC++], memh=[0]
stg_sub_zpx, -- meml=[X+(PC++)], memh=[0]
stg_sub_zpy, -- meml=[Y+(PC++)], memh=[0]
stg_sub_indx, -- buf2l=[X+(PC++)], buf2h=[0]. mem=[buf2].w
stg_sub_indy, -- buf2l=[PC++], buf2h=[0], mem=[Y+buf2].w
stg_mem2buf, -- BUF=[mem]
stg_mem2a, -- A=[mem]
stg_aCMPmem, -- NZC=A-[mem]
stg_aADDmem, -- NVZC,A=A+[mem]
stg_aSUBmem, -- NVZC,A=A-[mem]
stg_aORmem, -- A=A|[mem]
stg_aXORmem, -- A=A^[mem]
stg_aANDmem, -- A=A&mem
stg_xCMPmem, -- NZC=X-[mem]
stg_yCMPmem, -- NZC=Y-[mem]
stg_mem2x, -- X=[mem]
stg_mem2y, -- Y=[mem]
stg_a2mem, -- [mem]=A
stg_x2mem, -- [mem]=X
stg_y2mem, -- [mem]=Y
stg_ASLmem, -- ***TODO*** C <-- [7][mem][0] <-- 0
stg_ROLmem, -- ***TODO*** C <-- [7][mem][0] <-- C
stg_LSRmem, -- ***TODO*** 0 --> [7][mem][0] --> C
stg_RORmem, -- ***TODO*** C --> [7][mem][0] --> C
stg_INCmem, -- NZ=++[mem]
stg_DECmem, -- NZ=--[mem]
stg_BITmem, -- Z=[mem]&A, NV=[mem][7:6]
stg_BRK, -- ***TODO*** ++PC, B=1, raise (unmaskable) IRQ
stg_IRQ, -- [SP--]=PCH, [SP--]=PCL, [SP--]=PSW, I=1, PCL=[v_irq_l], PCH=[v_irq_h]
stg_NMI, -- [SP--]=PCH, [SP--]=PCL, [SP--]=PSW, I=1, PCL=[v_nmi_l], PCH=[v_nmi_h]
stg_CLC,
stg_SEC,
stg_CLI,
stg_SEI,
stg_CLV,
stg_CLD,
stg_SED,
stg_TXS,
stg_TSX,
stg_PHA,
stg_PLA,
stg_PHP,
stg_PLP,
stg_TAX,
stg_TXA,
stg_TAY,
stg_TYA,
stg_DEX,
stg_DEY,
stg_INX,
stg_INY,
stg_JMP_abs,
stg_JMP_ind,
stg_reljmp, -- take branch
stg_BCC,
stg_BCS,
stg_BNE,
stg_BEQ,
stg_BPL,
stg_BMI,
stg_BVC,
stg_BVS,
stg_ASL_a,
stg_LSR_a,
stg_ROL_a,
stg_ROR_a,
stg_RTS,
stg_RTI,
stg_JSR,
stg_tail
);
signal seq_stage : stage_t := stg_reset;
signal ret_stage : stage_t := stg_fetch; -- return stage for sub stage
signal ir : byte := x"00";
signal reg_a : byte := x"00";
signal reg_x : byte := x"00";
signal reg_y : byte := x"00";
signal reg_pc : word := x"0000";
signal reg_sp : byte := x"00";
signal reg_p : byte := x"00";
alias psw_n is reg_p(7);
alias psw_v is reg_p(6);
alias psw_b is reg_p(4);
alias psw_d is reg_p(3);
alias psw_i is reg_p(2);
alias psw_z is reg_p(1);
alias psw_c is reg_p(0);
signal buf_data : byte := x"00";
signal buf_addr : word := x"0000";
signal buf2 : word := x"0000";
alias reg_pcl : byte is reg_pc(7 downto 0);
alias reg_pch : byte is reg_pc(15 downto 8);
alias buf_addr_l : byte is buf_addr(7 downto 0);
alias buf_addr_h : byte is buf_addr(15 downto 8);
alias buf2l : byte is buf2(7 downto 0);
alias buf2h : byte is buf2(15 downto 8);
signal private_c : std_logic;
signal NMI_last : std_logic;
function isZero(src: byte) return std_logic is
begin
return ((src(0) nor src(1)) and (src(2) nor src(3))) and
((src(4) nor src(5)) and (src(6) nor src(7)));
end isZero;
function dec(arg : byte) return byte is
variable argu : unsigned(8 downto 0);
begin
argu := ('0' & u8(arg)) - "000000001";
return byte(argu(7 downto 0));
end dec;
function inc(arg : byte) return byte is
variable argu : unsigned(8 downto 0);
begin
argu := ('0' & u8(arg)) + "000000001";
return byte(argu(7 downto 0));
end inc;
function inc16(arg : word) return word is
variable argu : unsigned(16 downto 0);
begin
argu := ('0' & u16(arg)) + ('0' & x"01");
return word(argu(15 downto 0));
end inc16;
function sgn(arg : byte) return byte is
begin
return arg(7) & arg(7) & arg(7) & arg(7) &
arg(7) & arg(7) & arg(7) & arg(7);
end sgn;
function getb(arg : byte; bp : integer) return std_logic is
begin
return arg(bp);
end getb;
begin
clock: clockgen port map(
ph4Xin => ph4Xin,
ph0 => iph0,
ph1 => iph1,
ph2 => iph2,
stg => clkStg,
res0 => res0
);
ph0 <= iph0;
ph1 <= iph1;
ph2 <= iph2;
io8bit: ioport8bit port map(
ce => io_ce,
clk => io_clk,
res0 => res0,
r1w0 => dbRW,
a => abus(0),
din => io_i,
dout => io_o,
ioi => pi,
ioo => po
);
io_clk <= (not clkStg(1)) and clkStg(0);
io_ce <= not ( (((abus(15) or abus(14)) or (abus(13) or abus(12))) or
((abus(11) or abus(10)) or (abus( 9) or abus( 8)))) or
(((abus( 7) or abus( 6)) or (abus( 5) or abus( 4))) or
((abus( 3) or abus( 2)) or abus( 1) )) );
io_i <= regbus;
alunit: alu_8bit port map(
a_in => ALUain,
b_in => ALU_bin_tie,
c_in => ALUcin,
d_in => ALUdin,
op_in => ALUop,
n_out => ALUnout,
v_out => ALUvout,
z_out => ALUzout,
c_out => ALUcout,
r_out => ALUrout
);
alu_cin_mux: process(alu_cin_mode,psw_c,private_c) is
begin
case alu_cin_mode is
when cin_set => ALUcin <= '1';
when cin_clr => ALUcin <= '0';
when cin_aux => ALUcin <= private_c;
when others => ALUcin <= psw_c;
end case;
end process alu_cin_mux;
alu_din_mux: process(alu_din_mode,psw_d) is
begin
case alu_din_mode is
when din_clr => ALUdin <= '0';
when others => ALUdin <= psw_d;
end case;
end process alu_din_mux;
alu_bin_mux: process(alu_bin_mode,alu_bin_reg) is
begin
case alu_bin_mode is
when bin_clr => alu_bin_tie <= "00000000";
when bin_set => alu_bin_tie <= "11111111";
when bin_ireg => alu_bin_tie <= not alu_bin_reg;
when others => alu_bin_tie <= alu_bin_reg;
end case;
end process alu_bin_mux;
sync <= DB_ctl(2);
DBen <= DB_ctl(1);
DBrw <= DB_ctl(0);
nDBen <= not DBen;
DBre <= DBrw;
DBwe <= not DBrw;
aen1 <= not aen0;
r1w0 <= DBrw;
ALUop <= unsigned(aop);
-- Allow connection of data bus as output during write operations or disconnected
-- (high-Z) otherwise allowing other devices to use data bus while the CPU is halted.
db_ogate: process(nDBen,DBwe,outval) iS
begin
if ((nDBen and DBwe) = '1') then
if (io_ce='1') then
do <= io_o;
else
do <= outval;
end if;
else
do <= "ZZZZZZZZ";
end if;
end process db_ogate;
-- Allow connection of data bus as input during read operations or disconnected
-- (high-Z) otherwise allowing other devices to use data bus while the CPU is halted.
db_igate: process(nDBen,DBre,di) is
begin
if ((nDBen and DBre) = '1') then
regbus <= di;
else
regbus <= "ZZZZZZZZ";
end if;
end process db_igate;
addr_gate: process(aen1,abus) is
begin
if (aen1='1') then
a <= abus;
else
a <= "ZZZZZZZZZZZZZZZZ";
end if;
end process addr_gate;
main_proc: process(res0,ph4Xin) is
variable doNMI : std_logic;
variable tmp8 : byte;
begin
-- Status register stuff
reg_p(5) <= '0';
if (so0 = '0') then
psw_V <= '1';
end if;
if (res0 = '0') then
seq <= x"00";
seq_stage <= stg_reset;
ret_stage <= stg_reset;
dbctl_r1w0 <= '1';
dbctl_off <= '1';
dbctl_sync <= '0';
abus_off <= '1';
doNMI := '0';
elsif (rising_edge(ph4Xin)) then
-- allows sensing NMI on any clock
-- (but won't trigger until epilogue)
doNMI := doNMI or (NMI_last and (not nmi0)); -- only on transition to '0'
NMI_last <= nmi0; -- saves the state read
-- reset stage
if (seq_stage = stg_reset) then
if ((not (clkStg = sysclk_PH2_m)) and seq=x"00") then
else
-- we enter here at seq x00 on PH1+
case seq is
when x"00" => seq <= countSeq(seq); -- PH1+: put RES vector L on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= v_res_l;
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) write to PCL
reg_pcl <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: put RES vector H on abus
abus <= v_res_h;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pch <= regbus;
seq_stage <= stg_fetch; -- change to instruction decode
seq <= x"00";
when others => null;
end case;
end if;
end if;
-- instruction fetch/decode stage
if (seq_stage = stg_fetch) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
dbctl_sync <= '1'; -- sync on for instruction decode
abus_off <= '0';
abus <= reg_pc; -- PC on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) get instruction
ir <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: sync off
dbctl_sync <= '0';
ALUain <= reg_pcl;
alu_cin_mode <= cin_set;
alu_bin_mode <= bin_clr;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"05" => -- PH1-: store PCL=1+PCL
reg_pcl <= ALUrout;
private_c <= ALUcout;
seq <= countSeq(seq);
when x"06" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux; -- apply carry from PCL+1
seq <= countSeq(seq);
when x"07" => -- PH2-:
reg_pch <= ALUrout; -- store PCH=PCH+C
if (rdy = '1') then
abus_off <= '0';
dbctl_off <= '0';
seq <= x"00";
case ir is
when x"4C" =>
seq_stage <= stg_JMP_abs; -- JMP abs
when x"6C" =>
seq_stage <= stg_JMP_ind; -- JMP ind
when x"18" =>
seq_stage <= stg_CLC; -- CLC
when x"38" =>
seq_stage <= stg_SEC; -- SEC
when x"58" =>
seq_stage <= stg_CLI; -- CLI
when x"78" =>
seq_stage <= stg_SEI; -- SEI
when x"B8" =>
seq_stage <= stg_CLV; -- CLV
when x"D8" =>
seq_stage <= stg_CLD; -- CLD
when x"F8" =>
seq_stage <= stg_SED; -- SED
when x"A9" => -- LDA
ret_stage <= stg_mem2a; -- imm
seq_stage <= stg_sub_imm;
when x"AD" => -- abs
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_abs;
when x"BD" => -- abs+x
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_absx;
when x"B9" => -- abs+y
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_absy;
when x"A5" => -- zp
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_zp;
when x"B5" => -- zp+x
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_zpx;
when x"A1" => -- indirect,X
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_indx;
when x"B1" => -- indirect,Y
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_indy;
when x"A2" => -- LDX
ret_stage <= stg_mem2x; -- imm
seq_stage <= stg_sub_imm;
when x"AE" => -- abs
ret_stage <= stg_mem2x;
seq_stage <= stg_sub_abs;
when x"BE" => -- abs+y
ret_stage <= stg_mem2x;
seq_stage <= stg_sub_absy;
when x"A6" => -- zp
ret_stage <= stg_mem2x;
seq_stage <= stg_sub_zp;
when x"B6" => -- zp+y
ret_stage <= stg_mem2x;
seq_stage <= stg_sub_zpy;
when x"A0" => -- LDY
ret_stage <= stg_mem2y; -- imm
seq_stage <= stg_sub_imm;
when x"AC" => -- abs
ret_stage <= stg_mem2y;
seq_stage <= stg_sub_abs;
when x"BC" => -- abs+x
ret_stage <= stg_mem2y;
seq_stage <= stg_sub_absx;
when x"A4" => -- zp
ret_stage <= stg_mem2y;
seq_stage <= stg_sub_zp;
when x"B4" => -- zp+x
ret_stage <= stg_mem2y;
seq_stage <= stg_sub_zpx;
when x"8D" => -- STA
ret_stage <= stg_a2mem; -- abs
seq_stage <= stg_sub_abs;
when x"9D" => -- abs+x
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_absx;
when x"99" => -- abs+y
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_absy;
when x"85" => -- zp
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_zp;
when x"95" => -- zp+x
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_zpx;
when x"81" => -- indirect,X
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_indx;
when x"91" => -- indirect,Y
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_indy;
when x"8E" => -- STX
ret_stage <= stg_x2mem; -- abs
seq_stage <= stg_sub_abs;
when x"86" => -- zp
ret_stage <= stg_x2mem;
seq_stage <= stg_sub_zp;
when x"96" => -- zp+y
ret_stage <= stg_x2mem;
seq_stage <= stg_sub_zpy;
when x"8C" => -- STY
ret_stage <= stg_y2mem; -- abs
seq_stage <= stg_sub_abs;
when x"84" => -- zp
ret_stage <= stg_y2mem;
seq_stage <= stg_sub_zp;
when x"94" => -- zp+x
ret_stage <= stg_y2mem;
seq_stage <= stg_sub_zpx;
when x"09" => -- ORA A | mem
ret_stage <= stg_aORmem; -- imm
seq_stage <= stg_sub_imm;
when x"0D" => -- abs
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_abs;
when x"1D" => -- abs+x
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_absx;
when x"19" => -- abs+y
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_absy;
when x"05" => -- zp
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_zp;
when x"15" => -- zp+x
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_zpx;
when x"01" => -- indirect,X
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_indx;
when x"11" => -- indirect,Y
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_indy;
when x"29" => -- AND A & mem
ret_stage <= stg_aANDmem; -- imm
seq_stage <= stg_sub_imm;
when x"2D" => -- abs
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_abs;
when x"3D" => -- abs+x
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_absx;
when x"39" => -- abs+y
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_absy;
when x"25" => -- zp
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_zp;
when x"35" => -- zp+x
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_zpx;
when x"21" => -- indirect,X
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_indx;
when x"31" => -- indirect,Y
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_indy;
when x"24" => -- BIT Z=A&M, NV=[MEM][7:6]
ret_stage <= stg_BITmem; -- zp
seq_stage <= stg_sub_zp;
when x"2C" => -- abs
ret_stage <= stg_BITmem;
seq_stage <= stg_sub_abs;
when x"49" => -- EOR A ^ mem
ret_stage <= stg_aXORmem; -- imm
seq_stage <= stg_sub_imm;
when x"4D" => -- abs
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_abs;
when x"5D" => -- abs+x
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_absx;
when x"59" => -- abs+y
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_absy;
when x"45" => -- zp
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_zp;
when x"55" => -- zp+x
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_zpx;
when x"41" => -- indirect,X
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_indx;
when x"51" => -- indirect,Y
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_indy;
when x"69" => -- ADC C + A + mem
ret_stage <= stg_aADDmem; -- imm
seq_stage <= stg_sub_imm;
when x"6D" => -- abs
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_abs;
when x"7D" => -- abs+x
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_absx;
when x"79" => -- abs+y
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_absy;
when x"65" => -- zp
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_zp;
when x"75" => -- zp+x
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_zpx;
when x"61" => -- indirect,X
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_indx;
when x"71" => -- indirect,Y
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_indy;
when x"C9" => -- CMP NZC = A - mem
ret_stage <= stg_aCMPmem; -- imm
seq_stage <= stg_sub_imm;
when x"CD" => -- abs
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_abs;
when x"DD" => -- abs+x
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_absx;
when x"D9" => -- abs+y
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_absy;
when x"C5" => -- zp
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_zp;
when x"D5" => -- zp+x
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_zpx;
when x"C1" => -- indirect,X
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_indx;
when x"D1" => -- indirect,Y
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_indy;
when x"C0" => -- CPY NZC = Y - mem
ret_stage <= stg_yCMPmem; -- imm
seq_stage <= stg_sub_imm;
when x"C4" => -- zp
ret_stage <= stg_yCMPmem;
seq_stage <= stg_sub_zp;
when x"CC" => -- abs
ret_stage <= stg_yCMPmem;
seq_stage <= stg_sub_abs;
when x"E0" => -- CPX NZC = X - mem
ret_stage <= stg_xCMPmem; -- imm
seq_stage <= stg_sub_imm;
when x"E4" => -- zp
ret_stage <= stg_xCMPmem;
seq_stage <= stg_sub_zp;
when x"EC" => -- abs
ret_stage <= stg_xCMPmem;
seq_stage <= stg_sub_abs;
when x"E9" => -- SBC A + C - (mem+1)
ret_stage <= stg_aSUBmem; -- imm
seq_stage <= stg_sub_imm;
when x"ED" => -- abs
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_abs;
when x"FD" => -- abs+x
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_absx;
when x"F9" => -- abs+y
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_absy;
when x"E5" => -- zp
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_zp;
when x"F5" => -- zp+x
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_zpx;
when x"E1" => -- indirect,X
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_indx;
when x"F1" => -- indirect,Y
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_indy;
when x"9A" => -- TXS sp=x
seq_stage <= stg_TXS;
when x"BA" => -- TSX x=sp
seq_stage <= stg_TSX;
when x"48" => -- PHA [sp--]=a
seq_stage <= stg_PHA;
when x"68" => -- PLA a=[++sp]
seq_stage <= stg_PLA;
when x"08" => -- PHP [sp--]=P
seq_stage <= stg_PHP;
when x"28" => -- PLP P=[++sp]
seq_stage <= stg_PLP;
when x"AA" => -- TAX X=A
seq_stage <= stg_TAX;
when x"8A" => -- TXA A=X
seq_stage <= stg_TXA;
when x"A8" => -- TAY Y=A
seq_stage <= stg_TAY;
when x"98" => -- TYA A=Y
seq_stage <= stg_TYA;
when x"CA" => -- DEX X=X-1
seq_stage <= stg_DEX;
when x"88" => -- DEY Y=Y-1
seq_stage <= stg_DEY;
when x"C6" => -- DEC --[mem]
ret_stage <= stg_decmem; -- zp
seq_stage <= stg_sub_zp;
when x"D6" =>
ret_stage <= stg_decmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"CE" =>
ret_stage <= stg_decmem; -- abs
seq_stage <= stg_sub_abs;
when x"DE" =>
ret_stage <= stg_decmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"E8" => -- INX X=X+1
seq_stage <= stg_INX;
when x"C8" => -- INY Y=Y+1
seq_stage <= stg_INY;
when x"E6" => -- INC ++[mem]
ret_stage <= stg_incmem; -- zp
seq_stage <= stg_sub_zp;
when x"F6" =>
ret_stage <= stg_incmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"EE" =>
ret_stage <= stg_incmem; -- abs
seq_stage <= stg_sub_abs;
when x"FE" =>
ret_stage <= stg_incmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"10" => -- BPL PC+OP when N=0
seq_stage <= stg_BPL;
when x"30" => -- BMI PC+OP when N=1
seq_stage <= stg_BMI;
when x"50" => -- BVC PC+OP when V=0
seq_stage <= stg_BVC;
when x"70" => -- BVS PC+OP when V=1
seq_stage <= stg_BVS;
when x"90" => -- BCC PC+OP when C=0
seq_stage <= stg_BCC;
when x"B0" => -- BCS PC+OP when C=1
seq_stage <= stg_BCS;
when x"D0" => -- BNE PC+OP when Z=0
seq_stage <= stg_BNE;
when x"F0" => -- BEQ PC+OP when Z=1
seq_stage <= stg_BEQ;
when x"0A" => -- ASL C << T << '0'
seq_stage <= stg_ASL_a; -- a
when x"06" =>
ret_stage <= stg_ASLmem; -- zp
seq_stage <= stg_sub_zp;
when x"16" =>
ret_stage <= stg_ASLmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"0E" =>
ret_stage <= stg_ASLmem; -- abs
seq_stage <= stg_sub_abs;
when x"1E" =>
ret_stage <= stg_ASLmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"2A" => -- ROL C << T << C
seq_stage <= stg_ROL_a; -- a
when x"26" =>
ret_stage <= stg_ROLmem; -- zp
seq_stage <= stg_sub_zp;
when x"36" =>
ret_stage <= stg_ROLmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"2E" =>
ret_stage <= stg_ROLmem; -- abs
seq_stage <= stg_sub_abs;
when x"3E" =>
ret_stage <= stg_ROLmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"4A" => -- LSR '0' >> T >> C
seq_stage <= stg_LSR_a; -- a
when x"46" =>
ret_stage <= stg_LSRmem; -- zp
seq_stage <= stg_sub_zp;
when x"56" =>
ret_stage <= stg_LSRmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"4E" =>
ret_stage <= stg_LSRmem; -- abs
seq_stage <= stg_sub_abs;
when x"5E" =>
ret_stage <= stg_LSRmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"6A" => -- ROR C >> T >> C
seq_stage <= stg_ROR_a; -- a
when x"66" =>
ret_stage <= stg_ROLmem; -- zp
seq_stage <= stg_sub_zp;
when x"76" =>
ret_stage <= stg_ROLmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"6E" =>
ret_stage <= stg_ROLmem; -- abs
seq_stage <= stg_sub_abs;
when x"7E" =>
ret_stage <= stg_ROLmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"60" => -- RTS PCH=[++SP],PCL=[++SP],++PC
seq_stage <= stg_RTS;
when x"40" => -- RTI P=[++SP], PCH=[++SP],PCL=[++SP]
seq_stage <= stg_RTI;
when x"20" => -- JSR [email protected] to stack, PC=OP.w
seq_stage <= stg_JSR;
when others =>
seq_stage <= stg_tail; -- NOP
end case;
else
abus_off <= '1'; -- burn a full PH1/PH2 cycle if RDY=0
dbctl_off <= '1';
seq <= x"08";
end if;
when x"08" => seq <= countSeq(seq); -- PH1+: burn
when x"09" => seq <= countSeq(seq); -- PH1-: burn
when x"0A" => seq <= x"07"; -- PH2+: will check RDY again on PH2-
when others => null;
end case;
end if;
-- epilogue stage (also handles NOP)
-- checks for interrupts
if (seq_stage = stg_tail) then
case seq is
when x"00" => -- PH1+: burn
abus_off <= '0'; -- abus enabled
dbctl_off <= '0'; -- dbus enabled
dbctl_r1w0 <= '1'; -- dbus to read
seq <= countSeq(seq);
when x"01" => -- PH1-: burn
seq <= countSeq(seq);
when x"02" => -- PH2+: burn
seq <= countSeq(seq);
when x"03" =>
seq_stage <= stg_fetch; -- PH2-: return to fetch (on PH1+)
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_incpc) then
case seq is
when x"00" => -- PH1+:
ALUain <= reg_pcl;
alu_cin_mode <= cin_set;
alu_bin_mode <= bin_clr;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"01" => -- PH1-: store PCL=PCL+1
reg_pcl <= ALUrout;
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux; -- apply carry from PCL+1
seq <= countSeq(seq);
when x"03" => -- PH2-:
reg_pch <= ALUrout; -- store PCH=PCH+C
seq <= x"00";
seq_stage <= ret_stage; -- PH2+: set return-to stage (on PH1+)
when others => null;
end case;
end if;
if (seq_stage = stg_incmem) then -- ++[MEM]
case seq is
when x"00" => -- PH1+:
dbctl_off <= '0'; -- BUS: read from [MEM]
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr;
alu_cin_mode <= cin_set; -- ALU: Rout=Ain+1
alu_bin_mode <= bin_clr;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
ALUain <= regbus; -- [MEM] => Ain
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- BUS: write to [MEM]
psw_z <= ALUzout; -- NZ,Dout=[MEM]+1
psw_n <= ALUnout;
outval <= ALUrout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq <= x"00";
seq_stage <= stg_tail; -- instruction finished
when others => null;
end case;
end if;
if (seq_stage = stg_decmem) then -- --[MEM]
case seq is
when x"00" => -- PH1+:
dbctl_off <= '0'; -- BUS: read from [MEM]
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr;
alu_cin_mode <= cin_clr; -- ALU: Rout=Ain-1
alu_bin_mode <= bin_set;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
ALUain <= regbus; -- [MEM] => Ain
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- BUS: write to [MEM]
psw_z <= ALUzout; -- NZ,Dout=[MEM]+1
psw_n <= ALUnout;
outval <= ALUrout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq <= x"00";
seq_stage <= stg_tail; -- instruction finished
when others => null;
end case;
end if;
if (seq_stage = stg_reljmp) then
case seq is -- PC+=(signed)BUF
when x"00" => -- PH1+:
ALUain <= reg_pcl;
ALUbin <= buf_data;
alu_cin_mode <= cin_clr;
alu_bin_mode <= bin_reg;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"01" => -- PH1-: store PCL=PCL+BUF
reg_pcl <= ALUrout;
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
ALUbin <= sgn(buf_data); -- sign extend BUF for PCH
alu_cin_mode <= cin_aux; -- apply carry from PCL+BUF
seq <= countSeq(seq);
when x"03" => -- PH2-:
reg_pch <= ALUrout; -- store PCH=PCH+C+sgn(BUF)
seq <= x"00";
seq_stage <= stg_tail; -- branch finished
when others => null;
end case;
end if;
-- JMP abs
if (seq_stage = stg_JMP_abs) then
case seq is
when x"00" => -- PH1+: put PC on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= reg_pc;
ALUain <= reg_pcl;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_pcl <= ALUrout;
private_c <= ALUcout; -- ++PC
seq <= countSeq(seq);
when x"02" => -- PH2+: pass
ALUain <= reg_pch;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) write to MEML
buf_addr_l <= regbus; -- (we can't store to PC as we're using it)
reg_pch <= ALUrout;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pch <= regbus;
reg_pcl <= buf_addr_l; -- copy buffered lobyte to PCL
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- JMP ind
if (seq_stage = stg_JMP_ind) then
case seq is
when x"00" => -- PH1+: put PC on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= reg_pc;
ALUain <= reg_pcl;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_pcl <= ALUrout;
private_c <= ALUcout; -- ++PC
seq <= countSeq(seq);
when x"02" => -- PH2+: pass
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) write to MEML
buf_addr_l <= regbus; -- save to MEML
reg_pch <= ALUrout;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) write to PCH
buf_addr_h <= regbus; -- save to MEMH
seq <= countSeq(seq);
when x"08" => -- PH1+:
abus <= buf_addr; -- put MEM on abus
ALUain <= buf_addr_l; -- set up for ++MEM
ALU_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr)
buf2l <= ALUrout;
private_c <= ALUcout; -- BUF2=MEM+1
seq <= countSeq(seq);
when x"0a" => -- PH2+:
ALUain <= buf_addr_h; --
ALU_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"0b" => -- PH2-: (valid data)
reg_pcl <= regbus; -- PCL=(MEM)
buf_addr_l <= buf2l;
buf_addr_h <= ALUrout; -- ++MEM
seq <= countSeq(seq);
when x"0c" => -- PH1+:
abus <= buf_addr; -- put MEM (+1) on abus
seq <= countSeq(seq);
when x"0d" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0e" => seq <= countSeq(seq); -- PH2+: pass
when x"0f" => -- PH2-: (valid data)
reg_pch <= regbus; -- PCH=MEM (+1)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_mem2buf) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
buf_data <= regbus; -- save to BUF
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_mem2a) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_a <= regbus; -- save to A
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aANDmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_a <= reg_A and regbus; -- A = A & [mem]
psw_z <= isZero(reg_A and regbus); -- Z flag
psw_n <= getb(reg_A and regbus,7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_BITmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
psw_z <= isZero(regbus and reg_A); -- Z flag as if A & [mem]
psw_n <= regbus(7); -- N flag <= [mem][7]
psw_v <= regbus(6); -- V flag <= [mem][6]
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aADDmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_psw; -- P.D => din
alu_cin_mode <= cin_psw; -- P.C => cin
alu_bin_mode <= bin_reg; -- reg => bin
ALUain <= reg_a; -- A
aop <= aop_add; -- + P.C +
ALUbin <= regbus; -- mem
seq <= countSeq(seq);
when x"04" => -- PH1+:
reg_a <= ALUrout; -- store result
psw_n <= ALUnout;
psw_v <= ALUvout;
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aSUBmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_psw; -- P.D => din
alu_cin_mode <= cin_psw; -- P.C => cin
alu_bin_mode <= bin_ireg; -- ^reg => bin (1's compliment)
ALUain <= reg_a; -- A
aop <= aop_add; -- + P.C -
ALUbin <= regbus; -- (mem+1)
seq <= countSeq(seq);
when x"04" => -- PH1+:
reg_a <= ALUrout; -- store result
psw_n <= ALUnout;
psw_v <= ALUvout;
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aCMPmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_clr; -- 0 => din
alu_cin_mode <= cin_set; -- 1 => cin
alu_bin_mode <= bin_ireg; -- ^reg => bin (1's compliment)
ALUain <= reg_a; -- A
aop <= aop_add; -- + 1 -
ALUbin <= regbus; -- (mem+1)
seq <= countSeq(seq);
when x"04" => -- PH1+:
psw_n <= ALUnout; -- store result (NZC only)
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_xCMPmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_clr; -- 0 => din
alu_cin_mode <= cin_set; -- 1 => cin
alu_bin_mode <= bin_ireg; -- ^reg => bin (1's compliment)
ALUain <= reg_x; -- X
aop <= aop_add; -- + 1 -
ALUbin <= regbus; -- (mem+1)
seq <= countSeq(seq);
when x"04" => -- PH1+:
psw_n <= ALUnout; -- store result (NZC only)
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_yCMPmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_clr; -- 0 => din
alu_cin_mode <= cin_set; -- 1 => cin
alu_bin_mode <= bin_ireg; -- ^reg => bin (1's compliment)
ALUain <= reg_y; -- Y
aop <= aop_add; -- + 1 -
ALUbin <= regbus; -- (mem+1)
seq <= countSeq(seq);
when x"04" => -- PH1+:
psw_n <= ALUnout; -- store result (NZC only)
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aORmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_a <= reg_A or regbus; -- A = A | [mem]
psw_z <= isZero(reg_A or regbus); -- Z flag
psw_n <= getb(reg_A or regbus,7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aXORmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_a <= reg_A xor regbus; -- A = A ^ [mem]
psw_z <= isZero(reg_A xor regbus); -- Z flag
psw_n <= getb(reg_A xor regbus,7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_mem2x) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_x <= regbus; -- save to X
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_mem2y) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_y <= regbus; -- save to Y
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_a2mem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '0'; -- write
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => -- PH2+:
outval <= reg_a; -- A to data out
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_x2mem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '0'; -- write
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => -- PH2+:
outval <= reg_x; -- X to data out
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_y2mem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '0'; -- write
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => -- PH2+:
outval <= reg_y; -- Y to data out
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_imm) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
buf_addr <= reg_pc; -- MEM=PC
ALUain <= reg_pcl;
alu_cin_mode <= cin_set;
alu_bin_mode <= bin_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_pcl <= ALUrout;
private_c <= ALUcout;
alu_cin_mode <= cin_aux;
ALUain <= reg_pch;
seq <= countSeq(seq);
when x"02" => -- PH2+:
reg_pch <= ALUrout; -- PC=PC+1
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) store data to A
seq <= x"00";
seq_stage <= ret_stage;
when others => null;
end case;
end if;
if (seq_stage = stg_sub_abs) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_l <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
alu_cin_mode <= cin_set;
ALUain <= reg_pcl;
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr) pass
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"06" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_h <= regbus; -- save to MEMH
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_absx) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_l <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
alu_cin_mode <= cin_set;
ALUain <= reg_pcl;
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr) pass
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"06" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_h <= regbus; -- save to MEMH
seq <= countSeq(seq);
when x"08" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEM+X
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_x; -- MEML+X
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr) pass
buf_addr_l <= ALUrout; -- MEML=MEML+X
private_c <= ALUcout;
seq <= countSeq(seq);
when x"0A" => -- PH2+:
ALUain <= buf_addr_h;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_aux; -- MEMH+C
seq <= countSeq(seq);
when x"0B" => -- PH2-: (valid data)
buf_addr_h <= ALUrout; -- MEMH=MEMH+C
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_absy) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_l <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
alu_cin_mode <= cin_set;
ALUain <= reg_pcl;
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr) pass
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"06" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_h <= regbus; -- save to MEMH
seq <= countSeq(seq);
when x"08" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEM+Y
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_y; -- MEML+Y
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr)
buf_addr_l <= ALUrout; -- MEML=MEML+Y
private_c <= ALUcout;
seq <= countSeq(seq);
when x"0A" => -- PH2+:
ALUain <= buf_addr_h;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_aux; -- MEMH+C
seq <= countSeq(seq);
when x"0B" => -- PH2-: (valid data)
buf_addr_h <= ALUrout; -- MEMH=MEMH+C
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_zp) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
buf_addr_h <= x"00";
buf_addr_l <= regbus; -- MEM = 00:[PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_zpx) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
buf_addr_h <= x"00";
buf_addr_l <= regbus; -- MEM = 00:[PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq <= countSeq(seq);
when x"04" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEML+X
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_x; -- MEML+X
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr)
buf_addr_l <= ALUrout; -- MEML=MEML+X
seq <= countSeq(seq);
when x"06" => seq <= countSeq(seq); -- PH2+: pass (ZP offset wraps around)
when x"07" => -- PH2-: (valid data)
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_indx) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
buf_addr_l <= regbus; -- MEM = 00:[PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq <= countSeq(seq);
when x"04" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEML+X
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_x; -- MEML+X
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- BUF2=00:MEML+X
buf2h <= x"00";
seq <= countSeq(seq);
when x"06" => seq <= countSeq(seq); -- PH2+: pass (ZP offset wraps around)
when x"07" => seq <= countSeq(seq); -- PH2-: (valid data) pass
when x"08" => -- PH1+:
abus <= buf2; -- buf2 on abus
seq <= countSeq(seq);
when x"09" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0a" => seq <= countSeq(seq); -- PH2+: pass
when x"0b" => -- PH2-: (valid data)
buf_addr_l <= regbus; -- MEML=[buf2++]
buf2 <= inc16(buf2);
seq <= countSeq(seq);
when x"0c" => -- PH1+:
abus <= buf2; -- buf2 (+1) on abus
seq <= countSeq(seq);
when x"0d" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0e" => seq <= countSeq(seq); -- PH2+: pass
when x"0f" => -- PH2-: (valid data)
buf_addr_h <= regbus; -- MEMH=[buf2] (+1)
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_zpy) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
buf_addr_h <= x"00";
buf_addr_l <= regbus; -- MEM = 00:[PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq <= countSeq(seq);
when x"04" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEML+Y
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_y; -- MEML+Y
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr)
buf_addr_l <= ALUrout; -- MEML=MEML+Y
seq <= countSeq(seq);
when x"06" => seq <= countSeq(seq); -- PH2+: pass (ZP offset wraps around)
when x"07" => -- PH2-: (valid data)
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_indy) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
buf2h <= x"00";
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data)
buf_addr_l <= regbus; -- MEML = [PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq <= countSeq(seq);
when x"04" => -- PH1+:
abus <= x"00" & buf_addr_l; -- put 00:MEML on abus
buf2 <= x"00" & buf_addr_l; -- buf2=00:MEML
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) pass
buf_addr_l <= regbus; -- MEML = [BUF2]
buf2 <= inc16(buf2); -- ++buf2
seq <= countSeq(seq);
when x"08" => -- PH1+:
abus <= buf2; -- buf2 (buf+1) on abus
ALUain <= buf_addr_l; -- start MEM=MEM+Y
ALUbin <= reg_y; -- MEML+Y
ALU_cin_mode <= cin_clr;
ALU_bin_mode <= bin_reg;
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr)
buf_addr_l <= ALUrout; -- MEML=MEML+Y
private_c <= ALUcout;
alu_cin_mode <= cin_aux;
alu_bin_mode <= bin_clr;
seq <= countSeq(seq);
when x"0a" => -- PH2+:
seq <= countSeq(seq);
when x"0b" => -- PH2-: (valid data)
ALUain <= regbus; -- C+[BUF2] (MSB)
seq <= countSeq(seq);
when x"0c" => -- PH1+:
buf_addr_h <= ALUrout; -- MEMH=C+[BUF2] (MSB)
seq <= countSeq(seq); -- MEM=MEM+Y done
when x"0d" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0e" => seq <= countSeq(seq); -- PH2+: pass
when x"0f" => -- PH2-: (valid data)
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
-- CLC
if (seq_stage = stg_CLC) then
case seq is
when x"00" => -- PH1+: C=0
psw_c <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- SEC
if (seq_stage = stg_SEC) then
case seq is
when x"00" => -- PH1+: C=1
psw_c <= '1';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- CLI
if (seq_stage = stg_CLI) then
case seq is
when x"00" => -- PH1+: I=0
psw_i <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- SEI
if (seq_stage = stg_SEI) then
case seq is
when x"00" => -- PH1+: I=1
psw_i <= '1';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- CLV
if (seq_stage = stg_CLV) then
case seq is
when x"00" => -- PH1+: V=0
psw_v <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- CLD
if (seq_stage = stg_CLD) then
case seq is
when x"00" => -- PH1+: D=0
psw_d <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- SED
if (seq_stage = stg_SED) then
case seq is
when x"00" => -- PH1+: D=1
psw_d <= '1';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TXS
if (seq_stage = stg_TXS) then
case seq is
when x"00" => -- PH1+:
reg_sp <= reg_x; -- store SP=X
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TSX
if (seq_stage = stg_TSX) then
case seq is
when x"00" => -- PH1+:
reg_x <= reg_sp; -- store X=SP
psw_z <= isZero(reg_sp); -- Z flag
psw_n <= reg_sp(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- PHA
if (seq_stage = stg_PHA) then
case seq is
when x"00" => -- PH1+:
abus <= (x"01" & reg_sp); -- 01:sp to abus
abus_off <= '0';
dbctl_off <= '0'; -- dbus to write
dbctl_r1w0 <= '0';
ALUain <= reg_sp;
alu_bin_mode <= bin_set;
alu_cin_mode <= cin_clr;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr) sp=sp-1
reg_sp <= ALUrout;
seq <= countSeq(seq);
when x"02" => -- PH2+: place a on dbus
outval <= reg_a;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) instruction done
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- PHP
if (seq_stage = stg_PHP) then
case seq is
when x"00" => -- PH1+:
abus <= (x"01" & reg_sp); -- 01:sp to abus
abus_off <= '0';
dbctl_off <= '0'; -- dbus to write
dbctl_r1w0 <= '0';
ALUain <= reg_sp;
alu_bin_mode <= bin_set;
alu_cin_mode <= cin_clr;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr) sp=sp-1
reg_sp <= ALUrout;
seq <= countSeq(seq);
when x"02" => -- PH2+: place a on dbus
outval <= (reg_p(7 downto 6) & "01" &
reg_p(3 downto 0)); -- 6502 quirk: B always set on pushed psw
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) instruction done
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- PLA
if (seq_stage = stg_PLA) then
case seq is
when x"00" => -- PH1+:
abus_off <= '0';
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus to read
ALUain <= reg_sp;
alu_bin_mode <= bin_clr; -- sp pre-increment
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_sp <= ALUrout; -- we didn't have addr ready this PH1+
seq <= countSeq(seq); -- so we'll need to wait for next PH1+
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => seq <= countSeq(seq); -- PH2-: pass
when x"04" => -- PH1+: now we have address for bus
abus <= (x"01" & reg_sp); -- 01:sp to abus
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr)
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) instruction done
reg_a <= regbus;
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- PLP
if (seq_stage = stg_PLP) then
case seq is
when x"00" => -- PH1+:
abus_off <= '0';
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus to read
ALUain <= reg_sp;
alu_bin_mode <= bin_clr; -- sp pre-increment
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_sp <= ALUrout; -- we didn't have addr ready this PH1+
seq <= countSeq(seq); -- so we'll need to wait for next PH1+
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => seq <= countSeq(seq); -- PH2-: pass
when x"04" => -- PH1+: now we have address for bus
abus <= (x"01" & reg_sp); -- 01:sp to abus
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr)
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) instruction done
reg_p <= (regbus(7 downto 6) & "0" &
regbus(4 downto 0)); -- store status value (unused bit forced to 0)
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- TAX
if (seq_stage = stg_TAX) then
case seq is
when x"00" => -- PH1+:
reg_x <= reg_a; -- store X=A
psw_z <= isZero(reg_a); -- Z flag
psw_n <= reg_a(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TXA
if (seq_stage = stg_TXA) then
case seq is
when x"00" => -- PH1+:
reg_a <= reg_x; -- store A=X
psw_z <= isZero(reg_x); -- Z flag
psw_n <= reg_x(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TAY
if (seq_stage = stg_TAY) then
case seq is
when x"00" => -- PH1+:
reg_y <= reg_a; -- store Y=A
psw_z <= isZero(reg_a); -- Z flag
psw_n <= reg_a(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TYA
if (seq_stage = stg_TYA) then
case seq is
when x"00" => -- PH1+:
reg_a <= reg_y; -- store A=Y
psw_z <= isZero(reg_y); -- Z flag
psw_n <= reg_y(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- DEX
if (seq_stage = stg_DEX) then
case seq is
when x"00" => -- PH1+: BUF=x-1
buf_data <= dec(reg_x);
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
reg_x <= buf_data;
psw_z <= isZero(buf_data);
psw_n <= buf_data(7);
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- DEY
if (seq_stage = stg_DEY) then
case seq is
when x"00" => -- PH1+: BUF=y-1
buf_data <= dec(reg_y);
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
reg_y <= buf_data;
psw_z <= isZero(buf_data);
psw_n <= buf_data(7);
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- INX
if (seq_stage = stg_INX) then
case seq is
when x"00" => -- PH1+: BUF=x+1
buf_data <= inc(reg_x);
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
reg_x <= buf_data;
psw_z <= isZero(buf_data);
psw_n <= buf_data(7);
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- INY
if (seq_stage = stg_INY) then
case seq is
when x"00" => -- PH1+: BUF=y+1
buf_data <= inc(reg_y);
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
reg_y <= buf_data;
psw_z <= isZero(buf_data);
psw_n <= buf_data(7);
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- BCC
if (seq_stage = stg_BCC) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_C = '0') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BCS
if (seq_stage = stg_BCS) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_C = '1') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc; -- ++PC then branch or finish
when others => null;
end case;
end if;
-- BNE
if (seq_stage = stg_BNE) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_Z = '0') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BEQ
if (seq_stage = stg_BEQ) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_Z = '1') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BPL
if (seq_stage = stg_BPL) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_N = '0') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BMI
if (seq_stage = stg_BMI) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_N = '1') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BVC
if (seq_stage = stg_BVC) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_V = '0') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BVS
if (seq_stage = stg_BVS) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_V = '1') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- ASL A
if (seq_stage = stg_ASL_a) then
case seq is
when x"00" => -- PH1+:
tmp8 := reg_a(6 downto 0) & '0'; -- tmp = A << 1
psw_c <= reg_a(7); -- C = A(7)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
reg_a <= tmp8; -- A = tmp
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ASL [mem]
if (seq_stage = stg_ASLmem) then
case seq is
when x"00" => -- PH1+: put MEM on abus (read)
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
tmp8 := regbus(6 downto 0) & '0'; -- tmp = [mem] << 1
psw_c <= regbus(7); -- C = [mem](7)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
outval <= tmp8;
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- bus to write ([MEM]=tmp)
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- LSR A
if (seq_stage = stg_LSR_a) then
case seq is
when x"00" => -- PH1+:
tmp8 := '0' & reg_a(7 downto 1); -- tmp = A >> 1
psw_c <= reg_a(0); -- C = A(0)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
reg_a <= tmp8; -- A = tmp
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- LSR [mem]
if (seq_stage = stg_LSRmem) then
case seq is
when x"00" => -- PH1+: put MEM on abus (read)
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
tmp8 := '0' & regbus(7 downto 1); -- tmp = [mem] >> 1
psw_c <= regbus(0); -- C = [mem](0)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
outval <= tmp8;
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- bus to write ([MEM]=tmp)
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ROL A
if (seq_stage = stg_ROL_a) then
case seq is
when x"00" => -- PH1+:
tmp8 := reg_a(6 downto 0) & psw_c; -- tmp = A[6:0],C
psw_c <= reg_a(7); -- C = A(7)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
reg_a <= tmp8; -- A = tmp
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ROL[mem]
if (seq_stage = stg_ROLmem) then
case seq is
when x"00" => -- PH1+: put MEM on abus (read)
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
tmp8 := regbus(6 downto 0) & psw_c; -- tmp = [mem](6:0),C
psw_c <= regbus(7); -- C = [mem](7)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
outval <= tmp8;
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- bus to write ([MEM]=tmp)
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ROR A
if (seq_stage = stg_ROR_a) then
case seq is
when x"00" => -- PH1+:
tmp8 := psw_c & reg_a(7 downto 1); -- tmp = C,A[7:1]
psw_c <= reg_a(0); -- C = A(0)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
reg_a <= tmp8; -- A = tmp
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ROR [mem]
if (seq_stage = stg_RORmem) then
case seq is
when x"00" => -- PH1+: put MEM on abus (read)
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
tmp8 := psw_c & regbus(7 downto 1); -- tmp = C,[mem](7:1)
psw_c <= regbus(0); -- C = [mem](0)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
outval <= tmp8;
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- bus to write ([MEM]=tmp)
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- RTS (PCH=[++SP], PCL=[++SP], incpc, tail)
if (seq_stage = stg_RTS) then
case seq is
when x"00" => -- PH1+:
abus_off <= '0';
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus to read
ALUain <= reg_sp;
alu_bin_mode <= bin_clr; -- sp pre-increment
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf_data <= ALUrout; -- we didn't have addr ready on PH1+
seq <= countSeq(seq); -- so we'll store this SP+1 in BUF
when x"02" => -- PH2+: and pipeline BUF+1 (SP+2)
ALUain <= buf_data; -- through this bus cycle
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"03" => seq <= countSeq(seq); -- PH2-: (valid data)
reg_sp <= ALUrout; -- SP=SP+2
seq <= countSeq(seq); -- BUF is PCL, SP is PCH
when x"04" => -- PH1+: put out address of PCL
abus <= (x"01" & buf_data); -- 01:BUF
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr)
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) instruction done
reg_pcl <= regbus;
seq <= countSeq(seq);
when x"08" => -- PH1+: put out address of PCH
abus <= (x"01" & reg_sp); -- 01:SP
seq <= countSeq(seq);
when x"09" => seq <= countSeq(seq); -- PH1-: (valid addr)
when x"0a" => seq <= countSeq(seq); -- PH2+: pass
when x"0b" => -- PH2-: (valid data)
reg_pch <= regbus;
seq <= countSeq(seq);
seq <= x"00";
ret_stage <= stg_tail; -- JSR saves PC-1 so we incpc
seq_stage <= stg_sub_incpc; -- first, then tail (done)
when others => null;
end case;
end if;
-- RTI (P=[++SP], PCH=[++SP], PCL=[++SP], tail)
if (seq_stage = stg_RTI) then
case seq is
when x"00" => -- PH1+:
abus_off <= '0';
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus to read
ALUain <= reg_sp;
alu_bin_mode <= bin_clr; -- sp pre-increment
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr) not yet available
reg_sp <= ALUrout; -- ++SP (now on psw)
ALUain <= ALUrout; -- set up next ++SP
seq <= countSeq(seq); -- we need to wait for next PH1+
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => seq <= countSeq(seq); -- PH2-: pass
when x"04" => -- PH1+: now we have addresses for bus
abus <= (x"01" & reg_sp); -- 01:sp (psw) to abus
reg_sp <= ALUrout; -- ++SP (now on PCL)
ALUain <= ALUrout; -- set up next ++SP
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
reg_p <= (regbus(7 downto 6) & "00" &
regbus(3 downto 0)); -- store psw (unused/brk set to 0)
seq <= countSeq(seq);
when x"08" => -- PH1+:
abus <= (x"01" & reg_sp); -- 01:sp (PCL) to abus
seq <= countSeq(seq);
when x"09" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0a" => seq <= countSeq(seq); -- PH2+: pass
when x"0b" => -- PH2-: (valid data)
reg_pcl <= regbus; -- save PCL=[SP]
reg_sp <= ALUrout; -- ++SP (now on PCH)
seq <= countSeq(seq); -- BUF is PCL, SP is PCH
when x"0c" => -- PH1+: put out address of PCL
abus <= (x"01" & reg_sp); -- 01:sp (PCH) to abus
seq <= countSeq(seq);
when x"0d" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0e" => seq <= countSeq(seq); -- PH2+: pass
when x"0f" => -- PH2-: (valid data)
reg_pch <= regbus; -- save PCH=[SP]
seq <= x"00";
seq_stage <= stg_tail; -- instruction done
when others => null;
end case;
end if;
-- JSR (buf_addr=[pc].w, ++pc, [sp--]=PCL, [sp--]=PCH)
if (seq_stage = stg_JSR) then
case seq is
when x"00" => -- PH1+:
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= reg_pc;
ALUain <= reg_pcl;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_pcl <= ALUrout;
private_c <= ALUcout; -- ++PC
seq <= countSeq(seq);
when x"02" => -- PH2+: pass
ALUain <= reg_pch;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) write to MEML
buf_addr_l <= regbus; -- (we can't store to PC as we're using it)
reg_pch <= ALUrout;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to MEMH
buf_addr_h <= regbus; -- (PC not yet saved)
seq <= countSeq(seq);
when x"08" => -- PH1+:
dbctl_r1w0 <= '0'; -- data bus to write mode
abus <= (x"01" & reg_sp); -- put out address of 01:SP
ALUain <= reg_sp; -- set up SP--
alu_bin_mode <= bin_set;
alu_cin_mode <= cin_clr;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr)
reg_sp <= ALUrout; -- SP--
seq <= countSeq(seq);
when x"0a" => seq <= countSeq(seq); -- PH2+:
outval <= reg_pch; -- [01:SP]=PCH
seq <= countSeq(seq);
when x"0b" => -- PH2-: (valid data) pass
seq <= countSeq(seq);
when x"0c" => -- PH1+:
dbctl_r1w0 <= '0'; -- data bus to write mode
abus <= (x"01" & reg_sp); -- put out address of 01:SP
ALUain <= reg_sp; -- set up SP--
alu_bin_mode <= bin_set;
alu_cin_mode <= cin_clr;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"0d" => -- PH1-: (valid addr)
reg_sp <= ALUrout; -- SP--
seq <= countSeq(seq);
when x"0e" => seq <= countSeq(seq); -- PH2+:
outval <= reg_pcl; -- [01:SP]=PCL
seq <= countSeq(seq);
when x"0f" => -- PH2-: (valid data)
dbctl_r1w0 <= '1'; -- shut off write
reg_pc <= buf_addr; -- PC=MEM
seq_stage <= stg_tail;
seq <= x"00"; -- instruction done
when others => null;
end case;
end if;
end if;
end process main_proc;
end interaction;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbsse_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end bbsse_rnd;
architecture behaviour of bbsse_rnd is
constant st0: std_logic_vector(3 downto 0) := "1101";
constant st1: std_logic_vector(3 downto 0) := "0010";
constant st11: std_logic_vector(3 downto 0) := "1011";
constant st4: std_logic_vector(3 downto 0) := "1110";
constant st2: std_logic_vector(3 downto 0) := "1111";
constant st3: std_logic_vector(3 downto 0) := "0001";
constant st5: std_logic_vector(3 downto 0) := "0110";
constant st6: std_logic_vector(3 downto 0) := "0000";
constant st7: std_logic_vector(3 downto 0) := "1010";
constant st8: std_logic_vector(3 downto 0) := "1000";
constant st9: std_logic_vector(3 downto 0) := "0100";
constant st10: std_logic_vector(3 downto 0) := "1001";
constant st12: std_logic_vector(3 downto 0) := "1100";
constant st13: std_logic_vector(3 downto 0) := "0011";
constant st14: std_logic_vector(3 downto 0) := "0111";
constant st15: std_logic_vector(3 downto 0) := "0101";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when st0 =>
if std_match(input, "0------") then next_state <= st0; output <= "0000000";
elsif std_match(input, "10----0") then next_state <= st1; output <= "00110-0";
elsif std_match(input, "10----1") then next_state <= st1; output <= "00010-0";
elsif std_match(input, "11----0") then next_state <= st11; output <= "0011010";
elsif std_match(input, "11----1") then next_state <= st11; output <= "0001010";
end if;
when st1 =>
if std_match(input, "100----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "101-1--") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "101-0--") then next_state <= st2; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st2 =>
if std_match(input, "10-----") then next_state <= st3; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st3 =>
if std_match(input, "10--0--") then next_state <= st2; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st4 =>
if std_match(input, "10-----") then next_state <= st5; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st5 =>
if std_match(input, "10-1---") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "10-00--") then next_state <= st6; output <= "0100010";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st6 =>
if std_match(input, "10---0-") then next_state <= st6; output <= "0100000";
elsif std_match(input, "10---1-") then next_state <= st7; output <= "01000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st7 =>
if std_match(input, "10-----") then next_state <= st8; output <= "0000010";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st8 =>
if std_match(input, "10---0-") then next_state <= st8; output <= "0000000";
elsif std_match(input, "10---1-") then next_state <= st9; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st9 =>
if std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st10 =>
if std_match(input, "1001---") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "10-01--") then next_state <= st1; output <= "00010-0";
elsif std_match(input, "10-00--") then next_state <= st6; output <= "0100010";
elsif std_match(input, "1011---") then next_state <= st9; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st11 =>
if std_match(input, "0----0-") then next_state <= st11; output <= "000--00";
elsif std_match(input, "11---0-") then next_state <= st11; output <= "0000000";
elsif std_match(input, "0----1-") then next_state <= st0; output <= "000---1";
elsif std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "11---1-") then next_state <= st12; output <= "00001-0";
end if;
when st12 =>
if std_match(input, "11-----") then next_state <= st12; output <= "00001-0";
elsif std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when st13 =>
if std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when st14 =>
if std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when st15 =>
if std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
|
-------------------------------------------------------------------------------
--
-- The testbench for t48_core.
--
-- $Id: tb.vhd,v 1.14 2006-06-21 01:04:05 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb is
end tb;
use work.t48_core_comp_pack.all;
use work.t48_tb_pack.all;
architecture behav of tb is
-- clock period, 11 MHz
constant period_c : time := 90 ns;
component if_timing
port(
xtal_i : in std_logic;
ale_i : in std_logic;
psen_n_i : in std_logic;
rd_n_i : in std_logic;
wr_n_i : in std_logic;
prog_n_i : in std_logic;
db_bus_i : in std_logic_vector(7 downto 0);
p2_i : in std_logic_vector(7 downto 0)
);
end component;
component lpm_rom
generic (
LPM_WIDTH : positive;
LPM_TYPE : string := "LPM_ROM";
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_FILE : string;
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_HINT : string := "UNUSED"
);
port (
address : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
inclock : in std_logic;
outclock : in std_logic;
memenab : in std_logic;
q : out std_logic_vector(LPM_WIDTH-1 downto 0)
);
end component;
signal xtal_s : std_logic;
signal xtal_n_s : std_logic;
signal res_n_s : std_logic;
signal xtal3_s : std_logic;
signal int_n_s : std_logic;
signal ale_s : std_logic;
signal rom_addr_s : std_logic_vector(11 downto 0);
signal rom_data_s : std_logic_vector( 7 downto 0);
signal ram_data_to_s : std_logic_vector( 7 downto 0);
signal ram_data_from_s : std_logic_vector( 7 downto 0);
signal ram_addr_s : std_logic_vector( 7 downto 0);
signal ram_we_s : std_logic;
signal p1_s : std_logic_vector( 7 downto 0);
signal t48_p1_s : std_logic_vector( 7 downto 0);
signal p1_low_imp_s : std_logic;
signal p2_s : std_logic_vector( 7 downto 0);
signal t48_p2_s : std_logic_vector( 7 downto 0);
signal p2l_low_imp_s : std_logic;
signal p2h_low_imp_s : std_logic;
signal psen_n_s : std_logic;
signal prog_n_s : std_logic;
signal bus_s : std_logic_vector( 7 downto 0);
signal t48_bus_s : std_logic_vector( 7 downto 0);
signal bus_dir_s : std_logic;
signal ext_mem_addr_q : std_logic_vector( 7 downto 0);
signal ext_ram_data_from_s : std_logic_vector( 7 downto 0);
signal ext_ram_we_q : std_logic;
signal rd_n_s : std_logic;
signal wr_n_s : std_logic;
signal ext_rom_data_s : std_logic_vector( 7 downto 0);
signal ext_rom_addr_s : std_logic_vector(11 downto 0);
signal tb_p1_q : std_logic_vector( 7 downto 0);
signal tb_p2_q : std_logic_vector( 7 downto 0);
signal ext_mem_sel_we_q : boolean;
signal ena_ext_ram_q : boolean;
signal ena_tb_periph_q : boolean;
signal zero_s : std_logic;
signal one_s : std_logic;
signal zero_byte_s : std_logic_vector( 7 downto 0);
begin
zero_s <= '0';
one_s <= '1';
zero_byte_s <= (others => '0');
-----------------------------------------------------------------------------
-- Internal ROM, 2k bytes
-- Initialized by file rom_t49.hex.
-----------------------------------------------------------------------------
rom_internal_2k : lpm_rom
generic map (
LPM_WIDTH => 8,
LPM_TYPE => "LPM_ROM",
LPM_WIDTHAD => 11,
LPM_NUMWORDS => 2 ** 11,
LPM_FILE => "rom_t49.hex",
LPM_ADDRESS_CONTROL => "REGISTERED",
LPM_OUTDATA => "UNREGISTERED",
LPM_HINT => "UNUSED"
)
port map (
address => rom_addr_s(10 downto 0),
inclock => xtal_s,
outclock => zero_s, -- unused
memenab => one_s,
q => rom_data_s
);
-----------------------------------------------------------------------------
-- External ROM, 2k bytes
-- Initialized by file rom_t49_ext.hex.
-----------------------------------------------------------------------------
ext_rom_addr_s(11 downto 8) <= t48_p2_s(3 downto 0);
ext_rom_addr_s( 7 downto 0) <= ext_mem_addr_q;
rom_external_2k : lpm_rom
generic map (
LPM_WIDTH => 8,
LPM_TYPE => "LPM_ROM",
LPM_WIDTHAD => 11,
LPM_NUMWORDS => 2 ** 11,
LPM_FILE => "rom_t49_ext.hex",
LPM_ADDRESS_CONTROL => "REGISTERED",
LPM_OUTDATA => "UNREGISTERED",
LPM_HINT => "UNUSED"
)
port map (
address => ext_rom_addr_s(10 downto 0),
inclock => xtal_s,
outclock => zero_s, -- unused
memenab => one_s,
q => ext_rom_data_s
);
-----------------------------------------------------------------------------
-- Internal RAM, 256 bytes
-----------------------------------------------------------------------------
ram_256 : generic_ram_ena
generic map (
addr_width_g => 8,
data_width_g => 8
)
port map (
clk_i => xtal_s,
a_i => ram_addr_s,
we_i => ram_we_s,
ena_i => one_s,
d_i => ram_data_to_s,
d_o => ram_data_from_s
);
-----------------------------------------------------------------------------
-- External RAM, 256 bytes
-----------------------------------------------------------------------------
ext_ram_b : generic_ram_ena
generic map (
addr_width_g => 8,
data_width_g => 8
)
port map (
clk_i => xtal_s,
a_i => ext_mem_addr_q,
we_i => ext_ram_we_q,
ena_i => one_s,
d_i => bus_s,
d_o => ext_ram_data_from_s
);
t48_core_b : t48_core
generic map (
xtal_div_3_g => 1,
register_mnemonic_g => 1,
include_port1_g => 1,
include_port2_g => 1,
include_bus_g => 1,
include_timer_g => 1,
sample_t1_state_g => 4
)
port map (
xtal_i => xtal_s,
xtal_en_i => one_s,
reset_i => res_n_s,
t0_i => p1_s(0),
t0_o => open,
t0_dir_o => open,
int_n_i => int_n_s,
ea_i => rom_addr_s(11),
rd_n_o => rd_n_s,
psen_n_o => psen_n_s,
wr_n_o => wr_n_s,
ale_o => ale_s,
db_i => bus_s,
db_o => t48_bus_s,
db_dir_o => bus_dir_s,
t1_i => p1_s(1),
p2_i => p2_s,
p2_o => t48_p2_s,
p2l_low_imp_o => p2l_low_imp_s,
p2h_low_imp_o => p2h_low_imp_s,
p1_i => p1_s,
p1_o => t48_p1_s,
p1_low_imp_o => p1_low_imp_s,
prog_n_o => prog_n_s,
clk_i => xtal_s,
en_clk_i => xtal3_s,
xtal3_o => xtal3_s,
dmem_addr_o => ram_addr_s,
dmem_we_o => ram_we_s,
dmem_data_i => ram_data_from_s,
dmem_data_o => ram_data_to_s,
pmem_addr_o => rom_addr_s,
pmem_data_i => rom_data_s
);
if_timing_b : if_timing
port map (
xtal_i => xtal_s,
ale_i => ale_s,
psen_n_i => psen_n_s,
rd_n_i => rd_n_s,
wr_n_i => wr_n_s,
prog_n_i => prog_n_s,
db_bus_i => bus_s,
p2_i => t48_p2_s
);
-----------------------------------------------------------------------------
-- Port logic
--
ports: process (t48_p1_s,
p1_low_imp_s,
t48_p2_s,
p2l_low_imp_s,
p2h_low_imp_s)
function t48_port_f(t48_p : std_logic_vector;
low_imp : std_logic) return std_logic_vector is
variable p_v : std_logic_vector(t48_p'range);
begin
if low_imp = '1' then
p_v := t48_p;
else
for i in p_v'range loop
if t48_p(i) = '1' then
p_v(i) := 'H';
else
p_v(i) := t48_p(i);
end if;
end loop;
end if;
return p_v;
end;
begin
p1_s <= t48_port_f(t48_p => t48_p1_s,
low_imp => p1_low_imp_s);
p2_s(3 downto 0) <= t48_port_f(t48_p => t48_p2_s(3 downto 0),
low_imp => p2l_low_imp_s);
p2_s(7 downto 4) <= t48_port_f(t48_p => t48_p2_s(7 downto 4),
low_imp => p2h_low_imp_s);
end process ports;
--
-----------------------------------------------------------------------------
bus_s <= t48_bus_s
when bus_dir_s = '1' else
(others => 'Z');
bus_s <= ext_ram_data_from_s
when rd_n_s = '0' and ena_ext_ram_q else
(others => 'Z');
bus_s <= ext_rom_data_s
when psen_n_s = '0' else
(others => 'Z');
-----------------------------------------------------------------------------
-- External memory access signals
--
ext_mem: process (wr_n_s,
ext_mem_addr_q,
ena_ext_ram_q,
ale_s,
bus_s,
xtal_s)
begin
if ale_s'event and ale_s = '0' then
if not is_X(bus_s) then
ext_mem_addr_q <= bus_s;
else
ext_mem_addr_q <= (others => '0');
end if;
end if;
if wr_n_s'event and wr_n_s = '1' then
-- write enable for external RAM
if ena_ext_ram_q then
ext_ram_we_q <= '1';
end if;
-- process external memory selector
if ext_mem_addr_q = "11111111" then
ext_mem_sel_we_q <= true;
end if;
end if;
if xtal_s'event and xtal_s = '1' then
ext_ram_we_q <= '0';
ext_mem_sel_we_q <= false;
end if;
end process ext_mem;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process ext_mem_sel
--
-- Purpose:
-- Select external memory address space.
-- This is either
-- + external RAM
-- + testbench peripherals
--
ext_mem_sel: process (res_n_s, xtal_s)
begin
if res_n_s = '0' then
ena_ext_ram_q <= true;
ena_tb_periph_q <= false;
elsif xtal_s'event and xtal_s = '1' then
if ext_mem_sel_we_q then
if bus_s(0) = '1' then
ena_ext_ram_q <= true;
else
ena_ext_ram_q <= false;
end if;
if bus_s(1) = '1' then
ena_tb_periph_q <= true;
else
ena_tb_periph_q <= false;
end if;
end if;
end if;
end process ext_mem_sel;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process tb_periph
--
-- Purpose:
-- Implements the testbenc peripherals driving P1 and P2.
--
tb_periph: process (res_n_s, wr_n_s)
function oc_f (pX : std_logic_vector) return std_logic_vector is
variable r_v : std_logic_vector(pX'range);
begin
for i in pX'range loop
if pX(i) = '0' then
r_v(i) := '0';
else
r_v(i) := 'H';
end if;
end loop;
return r_v;
end;
begin
if res_n_s = '0' then
tb_p1_q <= (others => 'H');
tb_p2_q <= (others => 'H');
elsif wr_n_s'event and wr_n_s = '1' then
if ena_tb_periph_q then
case ext_mem_addr_q is
-- P1
when "00000000" =>
tb_p1_q <= oc_f(t48_bus_s);
-- P2
when "00000001" =>
tb_p2_q <= oc_f(t48_bus_s);
when others =>
null;
end case;
end if;
end if;
end process tb_periph;
--
-----------------------------------------------------------------------------
p1_s <= tb_p1_q;
p2_s <= tb_p2_q;
xtal_n_s <= not xtal_s;
-----------------------------------------------------------------------------
-- The clock generator
--
clk_gen: process
begin
xtal_s <= '0';
wait for period_c/2;
xtal_s <= '1';
wait for period_c/2;
end process clk_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- The reset generator
--
res_gen: process
begin
res_n_s <= '0';
wait for 5 * period_c;
res_n_s <= '1';
wait;
end process res_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- The interrupt generator
--
int_gen: process
begin
int_n_s <= '1';
wait for 750 * period_c;
int_n_s <= '0';
wait for 45 * period_c;
end process int_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- End of simulation detection
--
eos: process
begin
outer: loop
wait on tb_accu_s;
if tb_accu_s = "10101010" then
wait on tb_accu_s;
if tb_accu_s = "01010101" then
wait on tb_accu_s;
if tb_accu_s = "00000001" then
-- wait for instruction strobe of this move
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
-- wait for next strobe
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
assert false
report "Simulation Result: PASS."
severity note;
else
assert false
report "Simulation Result: FAIL."
severity note;
end if;
assert false
report "End of simulation reached."
severity failure;
end if;
end if;
end loop;
end process eos;
--
-----------------------------------------------------------------------------
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.13 2006/06/20 00:45:26 arniml
-- new input xtal_en_i
--
-- Revision 1.12 2005/11/01 21:21:48 arniml
-- split low impedance markers for P2
--
-- Revision 1.11 2005/09/07 17:39:40 arniml
-- fix missing assignment to outclock
--
-- Revision 1.10 2004/05/21 11:24:47 arniml
-- split 4k internal ROM into
-- + 2k internal ROM
-- + 2k external ROM
-- EA of t48_core is driven by MSB of internal ROM address
-- if upper 2k block is selected, the system switches to EA mode on the fly
--
-- Revision 1.9 2004/05/17 14:43:33 arniml
-- add testbench peripherals for P1 and P2
-- this became necessary to observe a difference between externally applied
-- port data and internally applied port data
--
-- Revision 1.8 2004/04/25 20:41:48 arniml
-- connect if_timing to P2 output of T48
--
-- Revision 1.7 2004/04/25 16:23:21 arniml
-- added if_timing
--
-- Revision 1.6 2004/04/14 20:57:44 arniml
-- wait for instruction strobe after final end-of-simulation detection
-- this ensures that the last mov instruction is part of the dump and
-- enables 100% matching with i8039 simulator
--
-- Revision 1.5 2004/03/29 19:45:15 arniml
-- rename pX_limp to pX_low_imp
--
-- Revision 1.4 2004/03/28 21:30:25 arniml
-- connect prog_n_o
--
-- Revision 1.3 2004/03/26 22:39:28 arniml
-- enhance simulation result string
--
-- Revision 1.2 2004/03/24 23:22:35 arniml
-- put ext_ram on falling clock edge to sample the write enable properly
--
-- Revision 1.1 2004/03/24 21:42:10 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc712.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:09 1996 --
-- **************************** --
ENTITY c03s04b01x00p24n01i00712ent IS
END c03s04b01x00p24n01i00712ent;
ARCHITECTURE c03s04b01x00p24n01i00712arch OF c03s04b01x00p24n01i00712ent IS
-- Some constants...
constant StringLength: INTEGER := 16;
constant NumOfStrings: INTEGER := 5;
-- Types...;
subtype STR16 is STRING (1 to StringLength);
type string_table is array (1 to NumOfStrings) of STR16;
-- Objects...
constant string_array: string_table :=
( "This is string 1"
,"__Hello World__"
,"This is string " & "3"
,"_Bird is a word_"
,"_Goodbye (ciao)_"
);
type ft3 is file of STRING;
BEGIN
TESTING: PROCESS
-- Declare the actual file to write.
file FILEV : ft3 open write_mode is "iofile.01";
BEGIN
for i in 1 to NumOfStrings loop
write(FILEV, string_array(i));
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p24n01i00712 - This test should produce an output file iofile.01 and tested by s010102.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p24n01i00712arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc712.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:09 1996 --
-- **************************** --
ENTITY c03s04b01x00p24n01i00712ent IS
END c03s04b01x00p24n01i00712ent;
ARCHITECTURE c03s04b01x00p24n01i00712arch OF c03s04b01x00p24n01i00712ent IS
-- Some constants...
constant StringLength: INTEGER := 16;
constant NumOfStrings: INTEGER := 5;
-- Types...;
subtype STR16 is STRING (1 to StringLength);
type string_table is array (1 to NumOfStrings) of STR16;
-- Objects...
constant string_array: string_table :=
( "This is string 1"
,"__Hello World__"
,"This is string " & "3"
,"_Bird is a word_"
,"_Goodbye (ciao)_"
);
type ft3 is file of STRING;
BEGIN
TESTING: PROCESS
-- Declare the actual file to write.
file FILEV : ft3 open write_mode is "iofile.01";
BEGIN
for i in 1 to NumOfStrings loop
write(FILEV, string_array(i));
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p24n01i00712 - This test should produce an output file iofile.01 and tested by s010102.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p24n01i00712arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc712.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:09 1996 --
-- **************************** --
ENTITY c03s04b01x00p24n01i00712ent IS
END c03s04b01x00p24n01i00712ent;
ARCHITECTURE c03s04b01x00p24n01i00712arch OF c03s04b01x00p24n01i00712ent IS
-- Some constants...
constant StringLength: INTEGER := 16;
constant NumOfStrings: INTEGER := 5;
-- Types...;
subtype STR16 is STRING (1 to StringLength);
type string_table is array (1 to NumOfStrings) of STR16;
-- Objects...
constant string_array: string_table :=
( "This is string 1"
,"__Hello World__"
,"This is string " & "3"
,"_Bird is a word_"
,"_Goodbye (ciao)_"
);
type ft3 is file of STRING;
BEGIN
TESTING: PROCESS
-- Declare the actual file to write.
file FILEV : ft3 open write_mode is "iofile.01";
BEGIN
for i in 1 to NumOfStrings loop
write(FILEV, string_array(i));
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p24n01i00712 - This test should produce an output file iofile.01 and tested by s010102.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p24n01i00712arch;
|
-- file: clk_32to288_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to288_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to288_dcm;
architecture xilinx of clk_32to288_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to288_dcm,clk_wiz_v3_6,{component_name=clk_32to288_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 9,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
|
-- file: clk_32to288_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to288_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to288_dcm;
architecture xilinx of clk_32to288_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to288_dcm,clk_wiz_v3_6,{component_name=clk_32to288_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 9,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
|
-- file: clk_32to288_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to288_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to288_dcm;
architecture xilinx of clk_32to288_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to288_dcm,clk_wiz_v3_6,{component_name=clk_32to288_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 9,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
|
-- file: clk_32to288_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to288_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to288_dcm;
architecture xilinx of clk_32to288_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to288_dcm,clk_wiz_v3_6,{component_name=clk_32to288_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 9,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
|
-- file: clk_32to288_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to288_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to288_dcm;
architecture xilinx of clk_32to288_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to288_dcm,clk_wiz_v3_6,{component_name=clk_32to288_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 9,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
|
-- file: clk_32to288_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to288_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to288_dcm;
architecture xilinx of clk_32to288_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to288_dcm,clk_wiz_v3_6,{component_name=clk_32to288_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 9,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
|
-- file: clk_32to288_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to288_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to288_dcm;
architecture xilinx of clk_32to288_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to288_dcm,clk_wiz_v3_6,{component_name=clk_32to288_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 9,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
|
-- file: clk_32to288_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to288_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to288_dcm;
architecture xilinx of clk_32to288_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to288_dcm,clk_wiz_v3_6,{component_name=clk_32to288_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 9,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
|
-- file: clk_32to288_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to288_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to288_dcm;
architecture xilinx of clk_32to288_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to288_dcm,clk_wiz_v3_6,{component_name=clk_32to288_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 9,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
|
-- file: clk_32to288_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to288_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to288_dcm;
architecture xilinx of clk_32to288_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to288_dcm,clk_wiz_v3_6,{component_name=clk_32to288_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 9,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
|
-- file: clk_32to288_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to288_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to288_dcm;
architecture xilinx of clk_32to288_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to288_dcm,clk_wiz_v3_6,{component_name=clk_32to288_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 9,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
|
-- file: clk_32to288_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to288_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to288_dcm;
architecture xilinx of clk_32to288_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to288_dcm,clk_wiz_v3_6,{component_name=clk_32to288_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 9,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
|
-- file: clk_32to288_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to288_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to288_dcm;
architecture xilinx of clk_32to288_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to288_dcm,clk_wiz_v3_6,{component_name=clk_32to288_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 9,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:57:08 04/04/2014
-- Design Name:
-- Module Name: C:/Users/Tom/projs/code/amplitude_adjust/amplitude_adjust_test.vhd
-- Project Name: amplitude_adjust
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: amplitude_adjust
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY amplitude_adjust_test IS
END amplitude_adjust_test;
ARCHITECTURE behavior OF amplitude_adjust_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT amplitude_adjust
PORT(
x_in : IN std_logic_vector(11 downto 0);
x_out : OUT std_logic_vector(11 downto 0);
adjust : IN std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal x_in : std_logic_vector(11 downto 0) := (others => '0');
signal adjust : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal x_out : std_logic_vector(11 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
signal temp_adj: unsigned(5 downto 0) := "111111";
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: amplitude_adjust PORT MAP (
x_in => x_in,
x_out => x_out,
adjust => adjust
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
x_in <= (others => '1');
loop
temp_adj <= temp_adj - 1;
adjust <= std_logic_vector(temp_adj);
wait for 10ns;
end loop;
wait;
end process;
END;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 17:41:04 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_xbar_0/zqynq_lab_1_design_xbar_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_xbar_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter is
port (
S_AXI_ARREADY : out STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_arvalid : out STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rlast_i0 : out STD_LOGIC;
\m_axi_arqos[15]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
ADDRESS_HIT_0 : out STD_LOGIC;
match : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[3].r_issuing_cnt_reg[27]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[2].r_issuing_cnt_reg[19]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
p_93_in : out STD_LOGIC;
p_39_in : out STD_LOGIC;
p_57_in : out STD_LOGIC;
p_75_in : out STD_LOGIC;
\gen_master_slots[4].r_issuing_cnt_reg[32]\ : out STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_arready_4 : in STD_LOGIC;
p_23_in : in STD_LOGIC;
\read_cs__0\ : in STD_LOGIC;
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
r_issuing_cnt : in STD_LOGIC_VECTOR ( 16 downto 0 );
\r_cmd_pop_0__1\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
\r_cmd_pop_1__1\ : in STD_LOGIC;
\r_cmd_pop_3__1\ : in STD_LOGIC;
\r_cmd_pop_2__1\ : in STD_LOGIC;
m_valid_i : in STD_LOGIC;
\r_cmd_pop_4__1\ : in STD_LOGIC;
\s_axi_araddr[24]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter : entity is "axi_crossbar_v2_1_14_addr_arbiter";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter is
signal \^address_hit_0\ : STD_LOGIC;
signal \^d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^aa_mi_arvalid\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[2]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_3_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\ : STD_LOGIC;
signal \^m_axi_arqos[15]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^match\ : STD_LOGIC;
signal s_ready_i2 : STD_LOGIC;
signal st_aa_artarget_hot : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_rid_i[11]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[10]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_4\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[18]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[19]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[19]_i_4\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[26]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[27]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[27]_i_4\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_axi_arvalid[2]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_axi_arvalid[3]_INST_0\ : label is "soft_lutpair2";
begin
ADDRESS_HIT_0 <= \^address_hit_0\;
D(2 downto 0) <= \^d\(2 downto 0);
Q(0) <= \^q\(0);
aa_mi_arvalid <= \^aa_mi_arvalid\;
\m_axi_arqos[15]\(68 downto 0) <= \^m_axi_arqos[15]\(68 downto 0);
match <= \^match\;
\gen_axi.s_axi_rid_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^q\(0),
I1 => \^aa_mi_arvalid\,
I2 => mi_arready_4,
I3 => p_23_in,
O => \gen_axi.s_axi_rid_i_reg[11]\(0)
);
\gen_axi.s_axi_rlast_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"55035500"
)
port map (
I0 => \read_cs__0\,
I1 => \^m_axi_arqos[15]\(45),
I2 => \^m_axi_arqos[15]\(44),
I3 => p_23_in,
I4 => \gen_axi.s_axi_rlast_i_i_5_n_0\,
O => s_axi_rlast_i0
);
\gen_axi.s_axi_rlast_i_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \^m_axi_arqos[15]\(46),
I1 => \^m_axi_arqos[15]\(47),
I2 => \^m_axi_arqos[15]\(48),
I3 => \^m_axi_arqos[15]\(49),
I4 => \^m_axi_arqos[15]\(51),
I5 => \^m_axi_arqos[15]\(50),
O => \gen_axi.s_axi_rlast_i_i_5_n_0\
);
\gen_master_slots[0].r_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \r_cmd_pop_0__1\,
I2 => m_axi_arready(0),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(0),
I5 => r_issuing_cnt(1),
O => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0)
);
\gen_master_slots[0].r_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I1 => r_issuing_cnt(1),
I2 => r_issuing_cnt(2),
O => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(1),
I1 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I2 => r_issuing_cnt(3),
I3 => r_issuing_cnt(2),
O => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(0),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(0),
O => p_93_in
);
\gen_master_slots[0].r_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \r_cmd_pop_0__1\,
I2 => m_axi_arready(0),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(0),
I5 => r_issuing_cnt(1),
O => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I1 => r_issuing_cnt(5),
I2 => r_issuing_cnt(6),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(5),
I1 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I2 => r_issuing_cnt(7),
I3 => r_issuing_cnt(6),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(1),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(1),
O => p_75_in
);
\gen_master_slots[1].r_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(4),
I1 => \r_cmd_pop_1__1\,
I2 => m_axi_arready(1),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(1),
I5 => r_issuing_cnt(5),
O => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(4),
I1 => \r_cmd_pop_1__1\,
I2 => m_axi_arready(1),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(1),
I5 => r_issuing_cnt(5),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0)
);
\gen_master_slots[2].r_issuing_cnt[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(8),
I1 => \r_cmd_pop_2__1\,
I2 => m_axi_arready(2),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(2),
I5 => r_issuing_cnt(9),
O => \gen_master_slots[2].r_issuing_cnt_reg[19]\(0)
);
\gen_master_slots[2].r_issuing_cnt[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\,
I1 => r_issuing_cnt(9),
I2 => r_issuing_cnt(10),
O => \gen_master_slots[2].r_issuing_cnt_reg[19]\(1)
);
\gen_master_slots[2].r_issuing_cnt[19]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(9),
I1 => \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\,
I2 => r_issuing_cnt(11),
I3 => r_issuing_cnt(10),
O => \gen_master_slots[2].r_issuing_cnt_reg[19]\(2)
);
\gen_master_slots[2].r_issuing_cnt[19]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(2),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(2),
O => p_57_in
);
\gen_master_slots[2].r_issuing_cnt[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(8),
I1 => \r_cmd_pop_2__1\,
I2 => m_axi_arready(2),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(2),
I5 => r_issuing_cnt(9),
O => \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\
);
\gen_master_slots[3].r_issuing_cnt[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(12),
I1 => \r_cmd_pop_3__1\,
I2 => m_axi_arready(3),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(3),
I5 => r_issuing_cnt(13),
O => \gen_master_slots[3].r_issuing_cnt_reg[27]\(0)
);
\gen_master_slots[3].r_issuing_cnt[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\,
I1 => r_issuing_cnt(13),
I2 => r_issuing_cnt(14),
O => \gen_master_slots[3].r_issuing_cnt_reg[27]\(1)
);
\gen_master_slots[3].r_issuing_cnt[27]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(13),
I1 => \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\,
I2 => r_issuing_cnt(15),
I3 => r_issuing_cnt(14),
O => \gen_master_slots[3].r_issuing_cnt_reg[27]\(2)
);
\gen_master_slots[3].r_issuing_cnt[27]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(3),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(3),
O => p_39_in
);
\gen_master_slots[3].r_issuing_cnt[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(12),
I1 => \r_cmd_pop_3__1\,
I2 => m_axi_arready(3),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(3),
I5 => r_issuing_cnt(13),
O => \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\
);
\gen_master_slots[4].r_issuing_cnt[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"807F0080"
)
port map (
I0 => \^q\(0),
I1 => \^aa_mi_arvalid\,
I2 => mi_arready_4,
I3 => \r_cmd_pop_4__1\,
I4 => r_issuing_cnt(16),
O => \gen_master_slots[4].r_issuing_cnt_reg[32]\
);
\gen_no_arbiter.m_mesg_i[11]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_mi_arvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(0),
Q => \^m_axi_arqos[15]\(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(10),
Q => \^m_axi_arqos[15]\(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(11),
Q => \^m_axi_arqos[15]\(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(12),
Q => \^m_axi_arqos[15]\(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(13),
Q => \^m_axi_arqos[15]\(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(14),
Q => \^m_axi_arqos[15]\(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(15),
Q => \^m_axi_arqos[15]\(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(16),
Q => \^m_axi_arqos[15]\(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(17),
Q => \^m_axi_arqos[15]\(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(18),
Q => \^m_axi_arqos[15]\(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(19),
Q => \^m_axi_arqos[15]\(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(1),
Q => \^m_axi_arqos[15]\(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(20),
Q => \^m_axi_arqos[15]\(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(21),
Q => \^m_axi_arqos[15]\(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(22),
Q => \^m_axi_arqos[15]\(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(23),
Q => \^m_axi_arqos[15]\(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(24),
Q => \^m_axi_arqos[15]\(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(25),
Q => \^m_axi_arqos[15]\(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(26),
Q => \^m_axi_arqos[15]\(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(27),
Q => \^m_axi_arqos[15]\(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(28),
Q => \^m_axi_arqos[15]\(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(29),
Q => \^m_axi_arqos[15]\(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(2),
Q => \^m_axi_arqos[15]\(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(30),
Q => \^m_axi_arqos[15]\(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(31),
Q => \^m_axi_arqos[15]\(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(32),
Q => \^m_axi_arqos[15]\(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(33),
Q => \^m_axi_arqos[15]\(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(34),
Q => \^m_axi_arqos[15]\(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(35),
Q => \^m_axi_arqos[15]\(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(36),
Q => \^m_axi_arqos[15]\(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(37),
Q => \^m_axi_arqos[15]\(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(38),
Q => \^m_axi_arqos[15]\(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(39),
Q => \^m_axi_arqos[15]\(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(3),
Q => \^m_axi_arqos[15]\(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(40),
Q => \^m_axi_arqos[15]\(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(41),
Q => \^m_axi_arqos[15]\(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(42),
Q => \^m_axi_arqos[15]\(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(43),
Q => \^m_axi_arqos[15]\(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(44),
Q => \^m_axi_arqos[15]\(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(45),
Q => \^m_axi_arqos[15]\(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(46),
Q => \^m_axi_arqos[15]\(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(47),
Q => \^m_axi_arqos[15]\(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(48),
Q => \^m_axi_arqos[15]\(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(49),
Q => \^m_axi_arqos[15]\(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(4),
Q => \^m_axi_arqos[15]\(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(50),
Q => \^m_axi_arqos[15]\(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(51),
Q => \^m_axi_arqos[15]\(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(52),
Q => \^m_axi_arqos[15]\(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(53),
Q => \^m_axi_arqos[15]\(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(54),
Q => \^m_axi_arqos[15]\(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(55),
Q => \^m_axi_arqos[15]\(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(56),
Q => \^m_axi_arqos[15]\(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(57),
Q => \^m_axi_arqos[15]\(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(58),
Q => \^m_axi_arqos[15]\(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(5),
Q => \^m_axi_arqos[15]\(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(59),
Q => \^m_axi_arqos[15]\(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(60),
Q => \^m_axi_arqos[15]\(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(61),
Q => \^m_axi_arqos[15]\(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(62),
Q => \^m_axi_arqos[15]\(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(63),
Q => \^m_axi_arqos[15]\(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(64),
Q => \^m_axi_arqos[15]\(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(6),
Q => \^m_axi_arqos[15]\(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(65),
Q => \^m_axi_arqos[15]\(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(66),
Q => \^m_axi_arqos[15]\(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(67),
Q => \^m_axi_arqos[15]\(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(68),
Q => \^m_axi_arqos[15]\(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(7),
Q => \^m_axi_arqos[15]\(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(8),
Q => \^m_axi_arqos[15]\(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(9),
Q => \^m_axi_arqos[15]\(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^address_hit_0\,
I1 => \^match\,
O => st_aa_artarget_hot(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_arqos[3]\(29),
I1 => \s_axi_arqos[3]\(28),
I2 => \s_axi_arqos[3]\(31),
I3 => \s_axi_arqos[3]\(30),
I4 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^address_hit_0\
);
\gen_no_arbiter.m_target_hot_i[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I1 => \s_axi_arqos[3]\(29),
I2 => \s_axi_arqos[3]\(28),
I3 => \s_axi_arqos[3]\(31),
I4 => \s_axi_arqos[3]\(30),
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(0)
);
\gen_no_arbiter.m_target_hot_i[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000001000000000"
)
port map (
I0 => \s_axi_arqos[3]\(34),
I1 => \s_axi_arqos[3]\(35),
I2 => \s_axi_arqos[3]\(33),
I3 => \s_axi_arqos[3]\(32),
I4 => \s_axi_arqos[3]\(37),
I5 => \s_axi_arqos[3]\(36),
O => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\
);
\gen_no_arbiter.m_target_hot_i[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_arqos[3]\(29),
I1 => \s_axi_arqos[3]\(28),
I2 => \s_axi_arqos[3]\(31),
I3 => \s_axi_arqos[3]\(30),
I4 => \gen_no_arbiter.m_target_hot_i[2]_i_2__0_n_0\,
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(1)
);
\gen_no_arbiter.m_target_hot_i[2]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => \s_axi_arqos[3]\(35),
I1 => \s_axi_arqos[3]\(34),
I2 => \s_axi_arqos[3]\(32),
I3 => \s_axi_arqos[3]\(33),
I4 => \s_axi_arqos[3]\(36),
I5 => \s_axi_arqos[3]\(37),
O => \gen_no_arbiter.m_target_hot_i[2]_i_2__0_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \gen_no_arbiter.m_target_hot_i[3]_i_2__0_n_0\,
I1 => \s_axi_arqos[3]\(25),
I2 => \s_axi_arqos[3]\(26),
I3 => \s_axi_arqos[3]\(27),
I4 => \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\,
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(2)
);
\gen_no_arbiter.m_target_hot_i[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \s_axi_arqos[3]\(32),
I1 => \s_axi_arqos[3]\(33),
I2 => \s_axi_arqos[3]\(34),
I3 => \s_axi_arqos[3]\(35),
I4 => \s_axi_arqos[3]\(37),
I5 => \s_axi_arqos[3]\(36),
O => \gen_no_arbiter.m_target_hot_i[3]_i_2__0_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \s_axi_arqos[3]\(31),
I1 => \s_axi_arqos[3]\(30),
I2 => \s_axi_arqos[3]\(29),
I3 => \s_axi_arqos[3]\(28),
O => \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \s_axi_arqos[3]\(40),
I1 => \s_axi_arqos[3]\(41),
I2 => \s_axi_arqos[3]\(38),
I3 => \s_axi_arqos[3]\(39),
I4 => \s_axi_arqos[3]\(43),
I5 => \s_axi_arqos[3]\(42),
O => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\
);
\gen_no_arbiter.m_target_hot_i[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^d\(1),
I1 => \^d\(2),
I2 => \^d\(0),
I3 => \^address_hit_0\,
O => \^match\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => st_aa_artarget_hot(0),
Q => aa_mi_artarget_hot(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(0),
Q => aa_mi_artarget_hot(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(1),
Q => aa_mi_artarget_hot(2),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(2),
Q => aa_mi_artarget_hot(3),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \s_axi_araddr[24]\(0),
Q => \^q\(0),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"DC"
)
port map (
I0 => \gen_no_arbiter.m_valid_i_i_2_n_0\,
I1 => m_valid_i,
I2 => \^aa_mi_arvalid\,
O => \gen_no_arbiter.m_valid_i_i_1_n_0\
);
\gen_no_arbiter.m_valid_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF88800000000"
)
port map (
I0 => m_axi_arready(2),
I1 => aa_mi_artarget_hot(2),
I2 => m_axi_arready(1),
I3 => aa_mi_artarget_hot(1),
I4 => \gen_no_arbiter.m_valid_i_i_3_n_0\,
I5 => \^aa_mi_arvalid\,
O => \gen_no_arbiter.m_valid_i_i_2_n_0\
);
\gen_no_arbiter.m_valid_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => aa_mi_artarget_hot(0),
I1 => m_axi_arready(0),
I2 => \^q\(0),
I3 => mi_arready_4,
I4 => m_axi_arready(3),
I5 => aa_mi_artarget_hot(3),
O => \gen_no_arbiter.m_valid_i_i_3_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1_n_0\,
Q => \^aa_mi_arvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => E(0),
Q => S_AXI_ARREADY(0),
R => '0'
);
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(0),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(0)
);
\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(1),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(1)
);
\m_axi_arvalid[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(2),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(2)
);
\m_axi_arvalid[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(3),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 is
port (
ss_aa_awready : out STD_LOGIC;
aa_sa_awvalid : out STD_LOGIC;
\mi_awready_mux__3\ : out STD_LOGIC;
\s_ready_i0__1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
p_84_in : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
p_66_in : out STD_LOGIC;
p_48_in : out STD_LOGIC;
p_101_in : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
write_cs01_out : out STD_LOGIC;
ADDRESS_HIT_0 : out STD_LOGIC;
match : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]_0\ : out STD_LOGIC;
\sa_wm_awready_mux__3\ : out STD_LOGIC;
\gen_master_slots[4].w_issuing_cnt_reg[32]\ : out STD_LOGIC;
\m_axi_awqos[15]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_valid_i : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
mi_awready_4 : in STD_LOGIC;
\s_axi_awqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_46_out : in STD_LOGIC;
\chosen_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[24]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 : entity is "axi_crossbar_v2_1_14_addr_arbiter";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 is
signal \^address_hit_0\ : STD_LOGIC;
signal \^d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^aa_sa_awvalid\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[2]_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\ : STD_LOGIC;
signal \m_ready_d[1]_i_4_n_0\ : STD_LOGIC;
signal \^match\ : STD_LOGIC;
signal \^mi_awready_mux__3\ : STD_LOGIC;
signal \^s_ready_i0__1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal s_ready_i2 : STD_LOGIC;
signal \^ss_aa_awready\ : STD_LOGIC;
signal st_aa_awtarget_hot : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^write_cs01_out\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_wready_i_i_2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_4\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_4\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[27]_i_4\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[4]_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_axi_awvalid[2]_INST_0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_axi_awvalid[3]_INST_0\ : label is "soft_lutpair14";
begin
ADDRESS_HIT_0 <= \^address_hit_0\;
D(2 downto 0) <= \^d\(2 downto 0);
Q(4 downto 0) <= \^q\(4 downto 0);
aa_sa_awvalid <= \^aa_sa_awvalid\;
match <= \^match\;
\mi_awready_mux__3\ <= \^mi_awready_mux__3\;
\s_ready_i0__1\(0) <= \^s_ready_i0__1\(0);
ss_aa_awready <= \^ss_aa_awready\;
write_cs01_out <= \^write_cs01_out\;
\gen_axi.s_axi_wready_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => mi_awready_4,
I1 => \^q\(4),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => \^write_cs01_out\
);
\gen_master_slots[0].w_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(0),
I1 => \^q\(0),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_101_in
);
\gen_master_slots[1].w_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(1),
I1 => \^q\(1),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_84_in
);
\gen_master_slots[2].w_issuing_cnt[19]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(2),
I1 => \^q\(2),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_66_in
);
\gen_master_slots[3].w_issuing_cnt[27]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(3),
I1 => \^q\(3),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_48_in
);
\gen_master_slots[4].w_issuing_cnt[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"95552AAA"
)
port map (
I0 => \^write_cs01_out\,
I1 => s_axi_bready(0),
I2 => p_46_out,
I3 => \chosen_reg[4]\(0),
I4 => w_issuing_cnt(0),
O => \gen_master_slots[4].w_issuing_cnt_reg[32]\
);
\gen_no_arbiter.m_mesg_i[11]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_sa_awvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(0),
Q => \m_axi_awqos[15]\(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(10),
Q => \m_axi_awqos[15]\(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(11),
Q => \m_axi_awqos[15]\(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(12),
Q => \m_axi_awqos[15]\(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(13),
Q => \m_axi_awqos[15]\(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(14),
Q => \m_axi_awqos[15]\(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(15),
Q => \m_axi_awqos[15]\(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(16),
Q => \m_axi_awqos[15]\(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(17),
Q => \m_axi_awqos[15]\(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(18),
Q => \m_axi_awqos[15]\(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(19),
Q => \m_axi_awqos[15]\(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(1),
Q => \m_axi_awqos[15]\(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(20),
Q => \m_axi_awqos[15]\(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(21),
Q => \m_axi_awqos[15]\(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(22),
Q => \m_axi_awqos[15]\(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(23),
Q => \m_axi_awqos[15]\(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(24),
Q => \m_axi_awqos[15]\(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(25),
Q => \m_axi_awqos[15]\(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(26),
Q => \m_axi_awqos[15]\(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(27),
Q => \m_axi_awqos[15]\(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(28),
Q => \m_axi_awqos[15]\(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(29),
Q => \m_axi_awqos[15]\(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(2),
Q => \m_axi_awqos[15]\(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(30),
Q => \m_axi_awqos[15]\(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(31),
Q => \m_axi_awqos[15]\(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(32),
Q => \m_axi_awqos[15]\(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(33),
Q => \m_axi_awqos[15]\(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(34),
Q => \m_axi_awqos[15]\(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(35),
Q => \m_axi_awqos[15]\(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(36),
Q => \m_axi_awqos[15]\(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(37),
Q => \m_axi_awqos[15]\(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(38),
Q => \m_axi_awqos[15]\(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(39),
Q => \m_axi_awqos[15]\(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(3),
Q => \m_axi_awqos[15]\(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(40),
Q => \m_axi_awqos[15]\(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(41),
Q => \m_axi_awqos[15]\(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(42),
Q => \m_axi_awqos[15]\(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(43),
Q => \m_axi_awqos[15]\(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(44),
Q => \m_axi_awqos[15]\(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(45),
Q => \m_axi_awqos[15]\(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(46),
Q => \m_axi_awqos[15]\(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(47),
Q => \m_axi_awqos[15]\(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(48),
Q => \m_axi_awqos[15]\(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(49),
Q => \m_axi_awqos[15]\(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(4),
Q => \m_axi_awqos[15]\(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(50),
Q => \m_axi_awqos[15]\(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(51),
Q => \m_axi_awqos[15]\(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(52),
Q => \m_axi_awqos[15]\(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(53),
Q => \m_axi_awqos[15]\(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(54),
Q => \m_axi_awqos[15]\(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(55),
Q => \m_axi_awqos[15]\(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(56),
Q => \m_axi_awqos[15]\(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(57),
Q => \m_axi_awqos[15]\(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(58),
Q => \m_axi_awqos[15]\(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(5),
Q => \m_axi_awqos[15]\(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(59),
Q => \m_axi_awqos[15]\(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(60),
Q => \m_axi_awqos[15]\(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(61),
Q => \m_axi_awqos[15]\(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(62),
Q => \m_axi_awqos[15]\(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(63),
Q => \m_axi_awqos[15]\(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(64),
Q => \m_axi_awqos[15]\(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(6),
Q => \m_axi_awqos[15]\(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(65),
Q => \m_axi_awqos[15]\(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(66),
Q => \m_axi_awqos[15]\(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(67),
Q => \m_axi_awqos[15]\(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(68),
Q => \m_axi_awqos[15]\(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(7),
Q => \m_axi_awqos[15]\(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(8),
Q => \m_axi_awqos[15]\(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(9),
Q => \m_axi_awqos[15]\(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^address_hit_0\,
I1 => \^match\,
O => st_aa_awtarget_hot(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_awqos[3]\(29),
I1 => \s_axi_awqos[3]\(28),
I2 => \s_axi_awqos[3]\(31),
I3 => \s_axi_awqos[3]\(30),
I4 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^address_hit_0\
);
\gen_no_arbiter.m_target_hot_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I1 => \s_axi_awqos[3]\(29),
I2 => \s_axi_awqos[3]\(28),
I3 => \s_axi_awqos[3]\(31),
I4 => \s_axi_awqos[3]\(30),
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(0)
);
\gen_no_arbiter.m_target_hot_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000001000000000"
)
port map (
I0 => \s_axi_awqos[3]\(34),
I1 => \s_axi_awqos[3]\(35),
I2 => \s_axi_awqos[3]\(33),
I3 => \s_axi_awqos[3]\(32),
I4 => \s_axi_awqos[3]\(37),
I5 => \s_axi_awqos[3]\(36),
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\
);
\gen_no_arbiter.m_target_hot_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_awqos[3]\(29),
I1 => \s_axi_awqos[3]\(28),
I2 => \s_axi_awqos[3]\(31),
I3 => \s_axi_awqos[3]\(30),
I4 => \gen_no_arbiter.m_target_hot_i[2]_i_2_n_0\,
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(1)
);
\gen_no_arbiter.m_target_hot_i[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => \s_axi_awqos[3]\(35),
I1 => \s_axi_awqos[3]\(34),
I2 => \s_axi_awqos[3]\(32),
I3 => \s_axi_awqos[3]\(33),
I4 => \s_axi_awqos[3]\(36),
I5 => \s_axi_awqos[3]\(37),
O => \gen_no_arbiter.m_target_hot_i[2]_i_2_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \gen_no_arbiter.m_target_hot_i[3]_i_2_n_0\,
I1 => \s_axi_awqos[3]\(25),
I2 => \s_axi_awqos[3]\(26),
I3 => \s_axi_awqos[3]\(27),
I4 => \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\,
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(2)
);
\gen_no_arbiter.m_target_hot_i[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \s_axi_awqos[3]\(32),
I1 => \s_axi_awqos[3]\(33),
I2 => \s_axi_awqos[3]\(34),
I3 => \s_axi_awqos[3]\(35),
I4 => \s_axi_awqos[3]\(37),
I5 => \s_axi_awqos[3]\(36),
O => \gen_no_arbiter.m_target_hot_i[3]_i_2_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \s_axi_awqos[3]\(31),
I1 => \s_axi_awqos[3]\(30),
I2 => \s_axi_awqos[3]\(29),
I3 => \s_axi_awqos[3]\(28),
O => \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \s_axi_awqos[3]\(40),
I1 => \s_axi_awqos[3]\(41),
I2 => \s_axi_awqos[3]\(38),
I3 => \s_axi_awqos[3]\(39),
I4 => \s_axi_awqos[3]\(43),
I5 => \s_axi_awqos[3]\(42),
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\
);
\gen_no_arbiter.m_target_hot_i[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^d\(1),
I1 => \^d\(2),
I2 => \^d\(0),
I3 => \^address_hit_0\,
O => \^match\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => st_aa_awtarget_hot(0),
Q => \^q\(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(0),
Q => \^q\(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(1),
Q => \^q\(2),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(2),
Q => \^q\(3),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \s_axi_awaddr[24]\(0),
Q => \^q\(4),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF1F00"
)
port map (
I0 => m_ready_d(1),
I1 => \^mi_awready_mux__3\,
I2 => \^s_ready_i0__1\(0),
I3 => \^aa_sa_awvalid\,
I4 => m_valid_i,
O => \gen_no_arbiter.m_valid_i_i_1__0_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1__0_n_0\,
Q => \^aa_sa_awvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i[0]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^ss_aa_awready\,
I1 => s_axi_awvalid(0),
I2 => m_ready_d_0(0),
O => \gen_no_arbiter.s_ready_i_reg[0]_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => E(0),
Q => \^ss_aa_awready\,
R => '0'
);
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(0),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(0)
);
\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(1)
);
\m_axi_awvalid[2]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(2),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(2)
);
\m_axi_awvalid[3]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(3),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(3)
);
\m_ready_d[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^q\(4),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(2),
I4 => \^q\(3),
O => \sa_wm_awready_mux__3\
);
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \m_ready_d[1]_i_4_n_0\,
I1 => \^q\(1),
I2 => m_axi_awready(1),
I3 => \^q\(2),
I4 => m_axi_awready(2),
O => \^mi_awready_mux__3\
);
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => m_ready_d(0),
I1 => \^q\(3),
I2 => \^q\(2),
I3 => \^q\(1),
I4 => \^q\(0),
I5 => \^q\(4),
O => \^s_ready_i0__1\(0)
);
\m_ready_d[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \^q\(0),
I1 => m_axi_awready(0),
I2 => \^q\(4),
I3 => mi_awready_4,
I4 => m_axi_awready(3),
I5 => \^q\(3),
O => \m_ready_d[1]_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].w_issuing_cnt_reg[24]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
\s_axi_bvalid[0]\ : out STD_LOGIC;
resp_select : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
f_mux4_return : out STD_LOGIC_VECTOR ( 13 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 16 downto 0 );
p_84_in : in STD_LOGIC;
p_66_in : in STD_LOGIC;
p_48_in : in STD_LOGIC;
p_101_in : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
match : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
p_0_out : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
p_46_out : in STD_LOGIC;
p_128_out : in STD_LOGIC;
p_108_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
st_mr_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
st_mr_bmesg : in STD_LOGIC_VECTOR ( 7 downto 0 );
p_68_out : in STD_LOGIC;
p_88_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp : entity is "axi_crossbar_v2_1_14_arbiter_resp";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp is
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_24_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_25_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_26_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_36_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_37_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_38_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_39_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6_n_0\ : STD_LOGIC;
signal last_rr_hot : STD_LOGIC;
signal \last_rr_hot[0]_i_2__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_3__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_2__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_3__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_2__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_3__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_4__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_5__0_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_5_in6_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_7_in9_in : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal \^resp_select\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \resp_select__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_bvalid[0]\ : STD_LOGIC;
signal \^s_ready_i_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \w_cmd_pop_0__0\ : STD_LOGIC;
signal \w_cmd_pop_1__0\ : STD_LOGIC;
signal \w_cmd_pop_2__0\ : STD_LOGIC;
signal \w_cmd_pop_3__0\ : STD_LOGIC;
signal \w_cmd_pop_4__0\ : STD_LOGIC;
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[3]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[4]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3\ : label is "soft_lutpair157";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_3\ : label is "soft_lutpair161";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_3\ : label is "soft_lutpair157";
attribute SOFT_HLUTNM of \gen_master_slots[2].w_issuing_cnt[19]_i_3\ : label is "soft_lutpair161";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[27]_i_3\ : label is "soft_lutpair156";
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_2__0\ : label is "soft_lutpair159";
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_3__0\ : label is "soft_lutpair160";
attribute SOFT_HLUTNM of \last_rr_hot[1]_i_2__0\ : label is "soft_lutpair158";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_3__0\ : label is "soft_lutpair159";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_2__0\ : label is "soft_lutpair160";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_3__0\ : label is "soft_lutpair158";
attribute SOFT_HLUTNM of \s_axi_bvalid[0]_INST_0_i_1\ : label is "soft_lutpair156";
begin
SR(0) <= \^sr\(0);
m_valid_i <= \^m_valid_i\;
resp_select(0) <= \^resp_select\(0);
\s_axi_bvalid[0]\ <= \^s_axi_bvalid[0]\;
s_ready_i_reg(4 downto 0) <= \^s_ready_i_reg\(4 downto 0);
\chosen[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBBBBBBBBB8"
)
port map (
I0 => s_axi_bready(0),
I1 => \^s_axi_bvalid[0]\,
I2 => p_46_out,
I3 => p_128_out,
I4 => p_108_out,
I5 => m_valid_i_reg,
O => need_arbitration
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(0),
Q => \^s_ready_i_reg\(0),
R => \^sr\(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(1),
Q => \^s_ready_i_reg\(1),
R => \^sr\(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(2),
Q => \^s_ready_i_reg\(2),
R => \^sr\(0)
);
\chosen_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(3),
Q => \^s_ready_i_reg\(3),
R => \^sr\(0)
);
\chosen_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(4),
Q => \^s_ready_i_reg\(4),
R => \^sr\(0)
);
\gen_fpga.gen_mux_5_8[0].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(36),
I1 => st_mr_bid(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(24),
I5 => st_mr_bid(12),
O => f_mux4_return(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(46),
I1 => st_mr_bid(10),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(34),
I5 => st_mr_bid(22),
O => f_mux4_return(10)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_ready_i_reg\(4),
I1 => p_46_out,
O => \^resp_select\(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(47),
I1 => st_mr_bid(11),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(35),
I5 => st_mr_bid(23),
O => f_mux4_return(11)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_68_out,
I1 => \^s_ready_i_reg\(3),
I2 => p_108_out,
I3 => \^s_ready_i_reg\(1),
O => \resp_select__0\(0)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bmesg(6),
I1 => st_mr_bmesg(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bmesg(4),
I5 => st_mr_bmesg(2),
O => f_mux4_return(12)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bmesg(7),
I1 => st_mr_bmesg(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bmesg(5),
I5 => st_mr_bmesg(3),
O => f_mux4_return(13)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(37),
I1 => st_mr_bid(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(25),
I5 => st_mr_bid(13),
O => f_mux4_return(1)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(38),
I1 => st_mr_bid(2),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(26),
I5 => st_mr_bid(14),
O => f_mux4_return(2)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(39),
I1 => st_mr_bid(3),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(27),
I5 => st_mr_bid(15),
O => f_mux4_return(3)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(40),
I1 => st_mr_bid(4),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(28),
I5 => st_mr_bid(16),
O => f_mux4_return(4)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(41),
I1 => st_mr_bid(5),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(29),
I5 => st_mr_bid(17),
O => f_mux4_return(5)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(42),
I1 => st_mr_bid(6),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(30),
I5 => st_mr_bid(18),
O => f_mux4_return(6)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(43),
I1 => st_mr_bid(7),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(31),
I5 => st_mr_bid(19),
O => f_mux4_return(7)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(44),
I1 => st_mr_bid(8),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(32),
I5 => st_mr_bid(20),
O => f_mux4_return(8)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(45),
I1 => st_mr_bid(9),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(33),
I5 => st_mr_bid(21),
O => f_mux4_return(9)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(1),
I1 => w_issuing_cnt(2),
I2 => w_issuing_cnt(0),
I3 => w_issuing_cnt(3),
I4 => \w_cmd_pop_0__0\,
I5 => p_101_in,
O => \gen_master_slots[0].w_issuing_cnt_reg[0]\(0)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(0),
I1 => p_128_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_0__0\
);
\gen_master_slots[1].w_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(5),
I1 => w_issuing_cnt(6),
I2 => w_issuing_cnt(4),
I3 => w_issuing_cnt(7),
I4 => \w_cmd_pop_1__0\,
I5 => p_84_in,
O => E(0)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(1),
I1 => p_108_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_1__0\
);
\gen_master_slots[2].w_issuing_cnt[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(9),
I1 => w_issuing_cnt(10),
I2 => w_issuing_cnt(8),
I3 => w_issuing_cnt(11),
I4 => \w_cmd_pop_2__0\,
I5 => p_66_in,
O => \gen_master_slots[2].w_issuing_cnt_reg[16]\(0)
);
\gen_master_slots[2].w_issuing_cnt[19]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(2),
I1 => p_88_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_2__0\
);
\gen_master_slots[3].w_issuing_cnt[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(13),
I1 => w_issuing_cnt(14),
I2 => w_issuing_cnt(12),
I3 => w_issuing_cnt(15),
I4 => \w_cmd_pop_3__0\,
I5 => p_48_in,
O => \gen_master_slots[3].w_issuing_cnt_reg[24]\(0)
);
\gen_master_slots[3].w_issuing_cnt[27]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(3),
I1 => p_68_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_3__0\
);
\gen_no_arbiter.m_mesg_i[11]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn_d,
O => \^sr\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => \gen_no_arbiter.s_ready_i_reg[0]\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\,
I5 => aa_sa_awvalid,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8888888AAAAAAAA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_0\,
I1 => \gen_multi_thread.accept_cnt_reg[0]\,
I2 => \^s_axi_bvalid[0]\,
I3 => p_0_out,
I4 => s_axi_bready(0),
I5 => Q(0),
O => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_36_n_0\,
I1 => \s_axi_awaddr[30]\(0),
I2 => ADDRESS_HIT_0,
I3 => \gen_no_arbiter.s_ready_i[0]_i_37_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"ECA0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_38_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_39_n_0\,
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_26_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(4),
I1 => p_46_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_4__0\
);
\gen_no_arbiter.s_ready_i[0]_i_36\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_1__0\,
I1 => w_issuing_cnt(4),
I2 => w_issuing_cnt(7),
I3 => w_issuing_cnt(5),
I4 => w_issuing_cnt(6),
O => \gen_no_arbiter.s_ready_i[0]_i_36_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_37\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_0__0\,
I1 => w_issuing_cnt(0),
I2 => w_issuing_cnt(3),
I3 => w_issuing_cnt(1),
I4 => w_issuing_cnt(2),
O => \gen_no_arbiter.s_ready_i[0]_i_37_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_38\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_2__0\,
I1 => w_issuing_cnt(8),
I2 => w_issuing_cnt(11),
I3 => w_issuing_cnt(9),
I4 => w_issuing_cnt(10),
O => \gen_no_arbiter.s_ready_i[0]_i_38_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_39\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_3__0\,
I1 => w_issuing_cnt(12),
I2 => w_issuing_cnt(15),
I3 => w_issuing_cnt(13),
I4 => w_issuing_cnt(14),
O => \gen_no_arbiter.s_ready_i[0]_i_39_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8AAA8A8A8AAAA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\,
I2 => \gen_no_arbiter.s_ready_i[0]_i_26_n_0\,
I3 => \w_cmd_pop_4__0\,
I4 => match,
I5 => w_issuing_cnt(16),
O => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\
);
\last_rr_hot[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_128_out,
I1 => p_68_out,
I2 => p_46_out,
I3 => \last_rr_hot[0]_i_2__0_n_0\,
I4 => \last_rr_hot[0]_i_3__0_n_0\,
I5 => p_6_in,
O => next_rr_hot(0)
);
\last_rr_hot[0]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_5_in6_in,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_108_out,
I3 => p_88_out,
O => \last_rr_hot[0]_i_2__0_n_0\
);
\last_rr_hot[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_46_out,
I1 => p_7_in9_in,
I2 => p_8_in,
O => \last_rr_hot[0]_i_3__0_n_0\
);
\last_rr_hot[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_108_out,
I1 => p_128_out,
I2 => p_46_out,
I3 => \last_rr_hot[1]_i_2__0_n_0\,
I4 => \last_rr_hot[4]_i_4__0_n_0\,
I5 => p_7_in9_in,
O => next_rr_hot(1)
);
\last_rr_hot[1]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_6_in,
I1 => p_5_in6_in,
I2 => p_88_out,
I3 => p_68_out,
O => \last_rr_hot[1]_i_2__0_n_0\
);
\last_rr_hot[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_88_out,
I1 => m_valid_i_reg_0,
I2 => \last_rr_hot[4]_i_5__0_n_0\,
I3 => p_46_out,
I4 => \last_rr_hot[2]_i_3__0_n_0\,
I5 => p_8_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_108_out,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_5_in6_in,
O => \last_rr_hot[2]_i_3__0_n_0\
);
\last_rr_hot[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_68_out,
I1 => p_108_out,
I2 => p_88_out,
I3 => \last_rr_hot[3]_i_2__0_n_0\,
I4 => \last_rr_hot[3]_i_3__0_n_0\,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(3)
);
\last_rr_hot[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_8_in,
I1 => p_7_in9_in,
I2 => p_46_out,
I3 => p_128_out,
O => \last_rr_hot[3]_i_2__0_n_0\
);
\last_rr_hot[3]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_88_out,
I1 => p_5_in6_in,
I2 => p_6_in,
O => \last_rr_hot[3]_i_3__0_n_0\
);
\last_rr_hot[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(3),
I2 => next_rr_hot(2),
I3 => next_rr_hot(1),
I4 => next_rr_hot(0),
I5 => next_rr_hot(4),
O => last_rr_hot
);
\last_rr_hot[4]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_46_out,
I1 => m_valid_i_reg,
I2 => \last_rr_hot[4]_i_4__0_n_0\,
I3 => p_108_out,
I4 => \last_rr_hot[4]_i_5__0_n_0\,
I5 => p_5_in6_in,
O => next_rr_hot(4)
);
\last_rr_hot[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_128_out,
I1 => p_8_in,
I2 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[4]_i_4__0_n_0\
);
\last_rr_hot[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_68_out,
I1 => p_6_in,
I2 => p_7_in9_in,
O => \last_rr_hot[4]_i_5__0_n_0\
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(0),
Q => \last_rr_hot_reg_n_0_[0]\,
R => \^sr\(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(1),
Q => p_5_in6_in,
R => \^sr\(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(2),
Q => p_6_in,
R => \^sr\(0)
);
\last_rr_hot_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(3),
Q => p_7_in9_in,
R => \^sr\(0)
);
\last_rr_hot_reg[4]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(4),
Q => p_8_in,
S => \^sr\(0)
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \^resp_select\(0),
I1 => p_128_out,
I2 => \^s_ready_i_reg\(0),
I3 => p_108_out,
I4 => \^s_ready_i_reg\(1),
I5 => \resp_select__0\(1),
O => \^s_axi_bvalid[0]\
);
\s_axi_bvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_68_out,
I1 => \^s_ready_i_reg\(3),
I2 => p_88_out,
I3 => \^s_ready_i_reg\(2),
O => \resp_select__0\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_8 is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
f_mux4_return : out STD_LOGIC_VECTOR ( 46 downto 0 );
\s_axi_rvalid[0]\ : out STD_LOGIC;
resp_select : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : in STD_LOGIC;
\r_cmd_pop_4__1\ : in STD_LOGIC;
match : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_122_out : in STD_LOGIC;
st_mr_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
st_mr_rmesg : in STD_LOGIC_VECTOR ( 135 downto 0 );
\m_payload_i_reg[34]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_62_out : in STD_LOGIC;
p_102_out : in STD_LOGIC;
S_AXI_ARREADY : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[34]_4\ : in STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_40_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_82_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_8 : entity is "axi_crossbar_v2_1_14_arbiter_resp";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_8;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_8 is
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_24__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\ : STD_LOGIC;
signal last_rr_hot : STD_LOGIC;
signal \last_rr_hot[0]_i_2_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_3_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_2_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_3_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_2_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_3_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_4_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_5_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_0_in1_in : STD_LOGIC_VECTOR ( 3 downto 1 );
signal p_5_in6_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_7_in9_in : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal \^resp_select\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \resp_select__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_rvalid[0]\ : STD_LOGIC;
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[3]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[4]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_2\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_3\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \last_rr_hot[1]_i_2\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_3\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_2\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_3\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \last_rr_hot[4]_i_4\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \last_rr_hot[4]_i_5\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__2\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__3\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \s_axi_rvalid[0]_INST_0_i_1\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \s_axi_rvalid[0]_INST_0_i_3\ : label is "soft_lutpair123";
begin
Q(4 downto 0) <= \^q\(4 downto 0);
m_valid_i <= \^m_valid_i\;
resp_select(0) <= \^resp_select\(0);
\s_axi_rvalid[0]\ <= \^s_axi_rvalid[0]\;
\chosen[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBBBBBBBBB8"
)
port map (
I0 => s_axi_rready(0),
I1 => \^s_axi_rvalid[0]\,
I2 => p_40_out,
I3 => p_122_out,
I4 => p_102_out,
I5 => m_valid_i_reg,
O => need_arbitration
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(0),
Q => \^q\(0),
R => SR(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(1),
Q => \^q\(1),
R => SR(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(2),
Q => \^q\(2),
R => SR(0)
);
\chosen_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(3),
Q => \^q\(3),
R => SR(0)
);
\chosen_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(4),
Q => \^q\(4),
R => SR(0)
);
\gen_fpga.gen_mux_5_8[0].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(36),
I1 => st_mr_rid(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(24),
I5 => st_mr_rid(12),
O => f_mux4_return(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(46),
I1 => st_mr_rid(10),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(34),
I5 => st_mr_rid(22),
O => f_mux4_return(10)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(4),
I1 => p_40_out,
O => \^resp_select\(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(47),
I1 => st_mr_rid(11),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(35),
I5 => st_mr_rid(23),
O => f_mux4_return(11)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_62_out,
I1 => \^q\(3),
I2 => p_102_out,
I3 => \^q\(1),
O => \resp_select__0\(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_62_out,
I1 => \^q\(3),
I2 => p_82_out,
I3 => \^q\(2),
O => \resp_select__0\(1)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(102),
I1 => st_mr_rmesg(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(68),
I5 => st_mr_rmesg(34),
O => f_mux4_return(12)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(103),
I1 => st_mr_rmesg(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(69),
I5 => st_mr_rmesg(35),
O => f_mux4_return(13)
);
\gen_fpga.gen_mux_5_8[15].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(104),
I1 => st_mr_rmesg(2),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(70),
I5 => st_mr_rmesg(36),
O => f_mux4_return(14)
);
\gen_fpga.gen_mux_5_8[16].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(105),
I1 => st_mr_rmesg(3),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(71),
I5 => st_mr_rmesg(37),
O => f_mux4_return(15)
);
\gen_fpga.gen_mux_5_8[17].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(106),
I1 => st_mr_rmesg(4),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(72),
I5 => st_mr_rmesg(38),
O => f_mux4_return(16)
);
\gen_fpga.gen_mux_5_8[18].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(107),
I1 => st_mr_rmesg(5),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(73),
I5 => st_mr_rmesg(39),
O => f_mux4_return(17)
);
\gen_fpga.gen_mux_5_8[19].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(108),
I1 => st_mr_rmesg(6),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(74),
I5 => st_mr_rmesg(40),
O => f_mux4_return(18)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(37),
I1 => st_mr_rid(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(25),
I5 => st_mr_rid(13),
O => f_mux4_return(1)
);
\gen_fpga.gen_mux_5_8[20].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(109),
I1 => st_mr_rmesg(7),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(75),
I5 => st_mr_rmesg(41),
O => f_mux4_return(19)
);
\gen_fpga.gen_mux_5_8[21].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(110),
I1 => st_mr_rmesg(8),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(76),
I5 => st_mr_rmesg(42),
O => f_mux4_return(20)
);
\gen_fpga.gen_mux_5_8[22].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(111),
I1 => st_mr_rmesg(9),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(77),
I5 => st_mr_rmesg(43),
O => f_mux4_return(21)
);
\gen_fpga.gen_mux_5_8[23].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(112),
I1 => st_mr_rmesg(10),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(78),
I5 => st_mr_rmesg(44),
O => f_mux4_return(22)
);
\gen_fpga.gen_mux_5_8[24].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(113),
I1 => st_mr_rmesg(11),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(79),
I5 => st_mr_rmesg(45),
O => f_mux4_return(23)
);
\gen_fpga.gen_mux_5_8[25].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(114),
I1 => st_mr_rmesg(12),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(80),
I5 => st_mr_rmesg(46),
O => f_mux4_return(24)
);
\gen_fpga.gen_mux_5_8[26].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(115),
I1 => st_mr_rmesg(13),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(81),
I5 => st_mr_rmesg(47),
O => f_mux4_return(25)
);
\gen_fpga.gen_mux_5_8[27].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(116),
I1 => st_mr_rmesg(14),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(82),
I5 => st_mr_rmesg(48),
O => f_mux4_return(26)
);
\gen_fpga.gen_mux_5_8[28].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(117),
I1 => st_mr_rmesg(15),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(83),
I5 => st_mr_rmesg(49),
O => f_mux4_return(27)
);
\gen_fpga.gen_mux_5_8[29].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(118),
I1 => st_mr_rmesg(16),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(84),
I5 => st_mr_rmesg(50),
O => f_mux4_return(28)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(38),
I1 => st_mr_rid(2),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(26),
I5 => st_mr_rid(14),
O => f_mux4_return(2)
);
\gen_fpga.gen_mux_5_8[30].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(119),
I1 => st_mr_rmesg(17),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(85),
I5 => st_mr_rmesg(51),
O => f_mux4_return(29)
);
\gen_fpga.gen_mux_5_8[31].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(120),
I1 => st_mr_rmesg(18),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(86),
I5 => st_mr_rmesg(52),
O => f_mux4_return(30)
);
\gen_fpga.gen_mux_5_8[32].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(121),
I1 => st_mr_rmesg(19),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(87),
I5 => st_mr_rmesg(53),
O => f_mux4_return(31)
);
\gen_fpga.gen_mux_5_8[33].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(122),
I1 => st_mr_rmesg(20),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(88),
I5 => st_mr_rmesg(54),
O => f_mux4_return(32)
);
\gen_fpga.gen_mux_5_8[34].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(123),
I1 => st_mr_rmesg(21),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(89),
I5 => st_mr_rmesg(55),
O => f_mux4_return(33)
);
\gen_fpga.gen_mux_5_8[35].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(124),
I1 => st_mr_rmesg(22),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(90),
I5 => st_mr_rmesg(56),
O => f_mux4_return(34)
);
\gen_fpga.gen_mux_5_8[36].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(125),
I1 => st_mr_rmesg(23),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(91),
I5 => st_mr_rmesg(57),
O => f_mux4_return(35)
);
\gen_fpga.gen_mux_5_8[37].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(126),
I1 => st_mr_rmesg(24),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(92),
I5 => st_mr_rmesg(58),
O => f_mux4_return(36)
);
\gen_fpga.gen_mux_5_8[38].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(127),
I1 => st_mr_rmesg(25),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(93),
I5 => st_mr_rmesg(59),
O => f_mux4_return(37)
);
\gen_fpga.gen_mux_5_8[39].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(128),
I1 => st_mr_rmesg(26),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(94),
I5 => st_mr_rmesg(60),
O => f_mux4_return(38)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(39),
I1 => st_mr_rid(3),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(27),
I5 => st_mr_rid(15),
O => f_mux4_return(3)
);
\gen_fpga.gen_mux_5_8[40].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(129),
I1 => st_mr_rmesg(27),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(95),
I5 => st_mr_rmesg(61),
O => f_mux4_return(39)
);
\gen_fpga.gen_mux_5_8[41].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(130),
I1 => st_mr_rmesg(28),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(96),
I5 => st_mr_rmesg(62),
O => f_mux4_return(40)
);
\gen_fpga.gen_mux_5_8[42].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(131),
I1 => st_mr_rmesg(29),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(97),
I5 => st_mr_rmesg(63),
O => f_mux4_return(41)
);
\gen_fpga.gen_mux_5_8[43].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(132),
I1 => st_mr_rmesg(30),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(98),
I5 => st_mr_rmesg(64),
O => f_mux4_return(42)
);
\gen_fpga.gen_mux_5_8[44].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(133),
I1 => st_mr_rmesg(31),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(99),
I5 => st_mr_rmesg(65),
O => f_mux4_return(43)
);
\gen_fpga.gen_mux_5_8[45].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(134),
I1 => st_mr_rmesg(32),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(100),
I5 => st_mr_rmesg(66),
O => f_mux4_return(44)
);
\gen_fpga.gen_mux_5_8[46].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(135),
I1 => st_mr_rmesg(33),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(101),
I5 => st_mr_rmesg(67),
O => f_mux4_return(45)
);
\gen_fpga.gen_mux_5_8[47].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => \m_payload_i_reg[34]_0\(0),
I1 => \m_payload_i_reg[34]_1\(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => \m_payload_i_reg[34]_2\(0),
I5 => \m_payload_i_reg[34]_3\(0),
O => f_mux4_return(46)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(40),
I1 => st_mr_rid(4),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(28),
I5 => st_mr_rid(16),
O => f_mux4_return(4)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(41),
I1 => st_mr_rid(5),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(29),
I5 => st_mr_rid(17),
O => f_mux4_return(5)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(42),
I1 => st_mr_rid(6),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(30),
I5 => st_mr_rid(18),
O => f_mux4_return(6)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(43),
I1 => st_mr_rid(7),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(31),
I5 => st_mr_rid(19),
O => f_mux4_return(7)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(44),
I1 => st_mr_rid(8),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(32),
I5 => st_mr_rid(20),
O => f_mux4_return(8)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(45),
I1 => st_mr_rid(9),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(33),
I5 => st_mr_rid(21),
O => f_mux4_return(9)
);
\gen_no_arbiter.s_ready_i[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => E(0)
);
\gen_no_arbiter.s_ready_i[0]_i_24__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4440404044444444"
)
port map (
I0 => S_AXI_ARREADY(0),
I1 => s_axi_arvalid(0),
I2 => \gen_multi_thread.accept_cnt_reg[0]\,
I3 => \^s_axi_rvalid[0]\,
I4 => \m_payload_i_reg[34]_4\,
I5 => \gen_multi_thread.accept_cnt_reg[3]\(0),
O => \gen_no_arbiter.s_ready_i[0]_i_24__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\,
I5 => aa_mi_arvalid,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8AAA8A8A8AAAA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_24__0_n_0\,
I1 => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
I2 => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
I3 => \r_cmd_pop_4__1\,
I4 => match,
I5 => r_issuing_cnt(0),
O => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\
);
\last_rr_hot[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_122_out,
I1 => p_62_out,
I2 => p_40_out,
I3 => \last_rr_hot[0]_i_2_n_0\,
I4 => \last_rr_hot[0]_i_3_n_0\,
I5 => p_6_in,
O => next_rr_hot(0)
);
\last_rr_hot[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_5_in6_in,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_102_out,
I3 => p_82_out,
O => \last_rr_hot[0]_i_2_n_0\
);
\last_rr_hot[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_40_out,
I1 => p_7_in9_in,
I2 => p_8_in,
O => \last_rr_hot[0]_i_3_n_0\
);
\last_rr_hot[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_102_out,
I1 => p_40_out,
I2 => p_122_out,
I3 => \last_rr_hot[1]_i_2_n_0\,
I4 => \last_rr_hot[4]_i_4_n_0\,
I5 => p_7_in9_in,
O => next_rr_hot(1)
);
\last_rr_hot[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_6_in,
I1 => p_5_in6_in,
I2 => p_82_out,
I3 => p_62_out,
O => \last_rr_hot[1]_i_2_n_0\
);
\last_rr_hot[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_82_out,
I1 => m_valid_i_reg_0,
I2 => \last_rr_hot[4]_i_5_n_0\,
I3 => p_40_out,
I4 => \last_rr_hot[2]_i_3_n_0\,
I5 => p_8_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_102_out,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_5_in6_in,
O => \last_rr_hot[2]_i_3_n_0\
);
\last_rr_hot[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_62_out,
I1 => p_102_out,
I2 => p_82_out,
I3 => \last_rr_hot[3]_i_2_n_0\,
I4 => \last_rr_hot[3]_i_3_n_0\,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(3)
);
\last_rr_hot[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_8_in,
I1 => p_7_in9_in,
I2 => p_40_out,
I3 => p_122_out,
O => \last_rr_hot[3]_i_2_n_0\
);
\last_rr_hot[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_82_out,
I1 => p_5_in6_in,
I2 => p_6_in,
O => \last_rr_hot[3]_i_3_n_0\
);
\last_rr_hot[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(3),
I2 => next_rr_hot(2),
I3 => next_rr_hot(1),
I4 => next_rr_hot(0),
I5 => next_rr_hot(4),
O => last_rr_hot
);
\last_rr_hot[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_40_out,
I1 => m_valid_i_reg,
I2 => \last_rr_hot[4]_i_4_n_0\,
I3 => p_102_out,
I4 => \last_rr_hot[4]_i_5_n_0\,
I5 => p_5_in6_in,
O => next_rr_hot(4)
);
\last_rr_hot[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_122_out,
I1 => p_8_in,
I2 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[4]_i_4_n_0\
);
\last_rr_hot[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_62_out,
I1 => p_6_in,
I2 => p_7_in9_in,
O => \last_rr_hot[4]_i_5_n_0\
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(0),
Q => \last_rr_hot_reg_n_0_[0]\,
R => SR(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(1),
Q => p_5_in6_in,
R => SR(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(2),
Q => p_6_in,
R => SR(0)
);
\last_rr_hot_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(3),
Q => p_7_in9_in,
R => SR(0)
);
\last_rr_hot_reg[4]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(4),
Q => p_8_in,
S => SR(0)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(0),
I1 => s_axi_rready(0),
I2 => p_122_out,
O => \m_payload_i_reg[0]\(0)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(1),
I1 => s_axi_rready(0),
I2 => p_102_out,
O => \m_payload_i_reg[0]_0\(0)
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(4),
I1 => s_axi_rready(0),
I2 => p_40_out,
O => \m_payload_i_reg[34]\(0)
);
\m_payload_i[46]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(3),
I1 => s_axi_rready(0),
I2 => p_62_out,
O => \m_payload_i_reg[0]_1\(0)
);
\m_payload_i[46]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(2),
I1 => s_axi_rready(0),
I2 => p_82_out,
O => \m_payload_i_reg[0]_2\(0)
);
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF8"
)
port map (
I0 => \^q\(0),
I1 => p_122_out,
I2 => p_0_in1_in(2),
I3 => p_0_in1_in(1),
I4 => p_0_in1_in(3),
I5 => \^resp_select\(0),
O => \^s_axi_rvalid[0]\
);
\s_axi_rvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(2),
I1 => p_82_out,
O => p_0_in1_in(2)
);
\s_axi_rvalid[0]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(1),
I1 => p_102_out,
O => p_0_in1_in(1)
);
\s_axi_rvalid[0]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(3),
I1 => p_62_out,
O => p_0_in1_in(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_decerr_slave is
port (
mi_awready_4 : out STD_LOGIC;
p_22_in : out STD_LOGIC;
p_29_in : out STD_LOGIC;
p_23_in : out STD_LOGIC;
p_25_in : out STD_LOGIC;
\read_cs__0\ : out STD_LOGIC;
mi_arready_4 : out STD_LOGIC;
\m_payload_i_reg[13]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_sa_awvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_rready_4 : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_mesg_i_reg[51]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
mi_bready_4 : in STD_LOGIC;
\write_cs0__0\ : in STD_LOGIC;
write_cs01_out : in STD_LOGIC;
s_axi_rlast_i0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_mesg_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
aresetn_d : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_decerr_slave : entity is "axi_crossbar_v2_1_14_decerr_slave";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_decerr_slave;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_decerr_slave is
signal \gen_axi.read_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt_reg\ : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \gen_axi.read_cnt_reg__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_axi.read_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_awready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bid_i[11]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bvalid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_4_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_wready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \^mi_arready_4\ : STD_LOGIC;
signal \^mi_awready_4\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^p_22_in\ : STD_LOGIC;
signal \^p_23_in\ : STD_LOGIC;
signal \^p_25_in\ : STD_LOGIC;
signal \^p_29_in\ : STD_LOGIC;
signal \^read_cs__0\ : STD_LOGIC;
signal write_cs : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.read_cnt[0]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[1]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[2]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[4]_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.s_axi_arready_i_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_3\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.write_cs[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gen_axi.write_cs[1]_i_1\ : label is "soft_lutpair16";
begin
mi_arready_4 <= \^mi_arready_4\;
mi_awready_4 <= \^mi_awready_4\;
p_22_in <= \^p_22_in\;
p_23_in <= \^p_23_in\;
p_25_in <= \^p_25_in\;
p_29_in <= \^p_29_in\;
\read_cs__0\ <= \^read_cs__0\;
\gen_axi.read_cnt[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(0),
I1 => \^p_23_in\,
I2 => \gen_no_arbiter.m_mesg_i_reg[51]\(12),
O => p_0_in(0)
);
\gen_axi.read_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E22E"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(13),
I1 => \^p_23_in\,
I2 => \gen_axi.read_cnt_reg__0\(0),
I3 => \gen_axi.read_cnt_reg\(1),
O => p_0_in(1)
);
\gen_axi.read_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCAA03AA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(14),
I1 => \gen_axi.read_cnt_reg\(1),
I2 => \gen_axi.read_cnt_reg__0\(0),
I3 => \^p_23_in\,
I4 => \gen_axi.read_cnt_reg\(2),
O => p_0_in(2)
);
\gen_axi.read_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFCAAAA0003AAAA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(15),
I1 => \gen_axi.read_cnt_reg__0\(0),
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.read_cnt_reg\(2),
I4 => \^p_23_in\,
I5 => \gen_axi.read_cnt_reg\(3),
O => p_0_in(3)
);
\gen_axi.read_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFCAAAA0003AAAA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(16),
I1 => \gen_axi.read_cnt_reg\(2),
I2 => \gen_axi.read_cnt[4]_i_2_n_0\,
I3 => \gen_axi.read_cnt_reg\(3),
I4 => \^p_23_in\,
I5 => \gen_axi.read_cnt_reg\(4),
O => p_0_in(4)
);
\gen_axi.read_cnt[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \gen_axi.read_cnt_reg\(1),
I1 => \gen_axi.read_cnt_reg__0\(0),
O => \gen_axi.read_cnt[4]_i_2_n_0\
);
\gen_axi.read_cnt[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CA3A"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(17),
I1 => \gen_axi.read_cnt[5]_i_2_n_0\,
I2 => \^p_23_in\,
I3 => \gen_axi.read_cnt_reg\(5),
O => p_0_in(5)
);
\gen_axi.read_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg\(3),
I1 => \gen_axi.read_cnt_reg__0\(0),
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.read_cnt_reg\(2),
I4 => \gen_axi.read_cnt_reg\(4),
O => \gen_axi.read_cnt[5]_i_2_n_0\
);
\gen_axi.read_cnt[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CA3A"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(18),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \^p_23_in\,
I3 => \gen_axi.read_cnt_reg\(6),
O => p_0_in(6)
);
\gen_axi.read_cnt[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F40404040404040"
)
port map (
I0 => \^read_cs__0\,
I1 => mi_rready_4,
I2 => \^p_23_in\,
I3 => \^mi_arready_4\,
I4 => aa_mi_arvalid,
I5 => \gen_no_arbiter.m_target_hot_i_reg[4]\(0),
O => \gen_axi.read_cnt[7]_i_1_n_0\
);
\gen_axi.read_cnt[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCAA03AA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(19),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \gen_axi.read_cnt_reg\(6),
I3 => \^p_23_in\,
I4 => \gen_axi.read_cnt_reg\(7),
O => p_0_in(7)
);
\gen_axi.read_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg\(4),
I1 => \gen_axi.read_cnt_reg\(2),
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.read_cnt_reg__0\(0),
I4 => \gen_axi.read_cnt_reg\(3),
I5 => \gen_axi.read_cnt_reg\(5),
O => \gen_axi.read_cnt[7]_i_3_n_0\
);
\gen_axi.read_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(0),
Q => \gen_axi.read_cnt_reg__0\(0),
R => SR(0)
);
\gen_axi.read_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(1),
Q => \gen_axi.read_cnt_reg\(1),
R => SR(0)
);
\gen_axi.read_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(2),
Q => \gen_axi.read_cnt_reg\(2),
R => SR(0)
);
\gen_axi.read_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(3),
Q => \gen_axi.read_cnt_reg\(3),
R => SR(0)
);
\gen_axi.read_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(4),
Q => \gen_axi.read_cnt_reg\(4),
R => SR(0)
);
\gen_axi.read_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(5),
Q => \gen_axi.read_cnt_reg\(5),
R => SR(0)
);
\gen_axi.read_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(6),
Q => \gen_axi.read_cnt_reg\(6),
R => SR(0)
);
\gen_axi.read_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(7),
Q => \gen_axi.read_cnt_reg\(7),
R => SR(0)
);
\gen_axi.read_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F70707070707070"
)
port map (
I0 => \^read_cs__0\,
I1 => mi_rready_4,
I2 => \^p_23_in\,
I3 => \^mi_arready_4\,
I4 => aa_mi_arvalid,
I5 => \gen_no_arbiter.m_target_hot_i_reg[4]\(0),
O => \gen_axi.read_cs[0]_i_1_n_0\
);
\gen_axi.read_cs_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.read_cs[0]_i_1_n_0\,
Q => \^p_23_in\,
R => SR(0)
);
\gen_axi.s_axi_arready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FBBB0000"
)
port map (
I0 => \^mi_arready_4\,
I1 => \^p_23_in\,
I2 => \^read_cs__0\,
I3 => mi_rready_4,
I4 => aresetn_d,
I5 => E(0),
O => \gen_axi.s_axi_arready_i_i_1_n_0\
);
\gen_axi.s_axi_arready_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \gen_axi.read_cnt[4]_i_2_n_0\,
I1 => \gen_axi.read_cnt_reg\(6),
I2 => \gen_axi.read_cnt_reg\(7),
I3 => \gen_axi.s_axi_arready_i_i_3_n_0\,
I4 => \gen_axi.read_cnt_reg\(2),
I5 => \gen_axi.read_cnt_reg\(3),
O => \^read_cs__0\
);
\gen_axi.s_axi_arready_i_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \gen_axi.read_cnt_reg\(4),
I1 => \gen_axi.read_cnt_reg\(5),
O => \gen_axi.s_axi_arready_i_i_3_n_0\
);
\gen_axi.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_arready_i_i_1_n_0\,
Q => \^mi_arready_4\,
R => '0'
);
\gen_axi.s_axi_awready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFBB0000F0FF"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => Q(0),
I2 => mi_bready_4,
I3 => write_cs(1),
I4 => write_cs(0),
I5 => \^mi_awready_4\,
O => \gen_axi.s_axi_awready_i_i_1_n_0\
);
\gen_axi.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_awready_i_i_1_n_0\,
Q => \^mi_awready_4\,
R => SR(0)
);
\gen_axi.s_axi_bid_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => write_cs(1),
I1 => write_cs(0),
I2 => m_ready_d(0),
I3 => aa_sa_awvalid,
I4 => Q(0),
I5 => \^mi_awready_4\,
O => \gen_axi.s_axi_bid_i[11]_i_1_n_0\
);
\gen_axi.s_axi_bid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(0),
Q => \m_payload_i_reg[13]\(0),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(10),
Q => \m_payload_i_reg[13]\(10),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(11),
Q => \m_payload_i_reg[13]\(11),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(1),
Q => \m_payload_i_reg[13]\(1),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(2),
Q => \m_payload_i_reg[13]\(2),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(3),
Q => \m_payload_i_reg[13]\(3),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(4),
Q => \m_payload_i_reg[13]\(4),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(5),
Q => \m_payload_i_reg[13]\(5),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(6),
Q => \m_payload_i_reg[13]\(6),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(7),
Q => \m_payload_i_reg[13]\(7),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(8),
Q => \m_payload_i_reg[13]\(8),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(9),
Q => \m_payload_i_reg[13]\(9),
R => SR(0)
);
\gen_axi.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFF00C0"
)
port map (
I0 => mi_bready_4,
I1 => write_cs(0),
I2 => \write_cs0__0\,
I3 => write_cs(1),
I4 => \^p_29_in\,
O => \gen_axi.s_axi_bvalid_i_i_1_n_0\
);
\gen_axi.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_bvalid_i_i_1_n_0\,
Q => \^p_29_in\,
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(0),
Q => \skid_buffer_reg[46]\(0),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(10),
Q => \skid_buffer_reg[46]\(10),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(11),
Q => \skid_buffer_reg[46]\(11),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(1),
Q => \skid_buffer_reg[46]\(1),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(2),
Q => \skid_buffer_reg[46]\(2),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(3),
Q => \skid_buffer_reg[46]\(3),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(4),
Q => \skid_buffer_reg[46]\(4),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(5),
Q => \skid_buffer_reg[46]\(5),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(6),
Q => \skid_buffer_reg[46]\(6),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(7),
Q => \skid_buffer_reg[46]\(7),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(8),
Q => \skid_buffer_reg[46]\(8),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(9),
Q => \skid_buffer_reg[46]\(9),
R => SR(0)
);
\gen_axi.s_axi_rlast_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFBFFAAAA0800"
)
port map (
I0 => s_axi_rlast_i0,
I1 => \gen_axi.s_axi_rlast_i_i_3_n_0\,
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.s_axi_rlast_i_i_4_n_0\,
I4 => E(0),
I5 => \^p_25_in\,
O => \gen_axi.s_axi_rlast_i_i_1_n_0\
);
\gen_axi.s_axi_rlast_i_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \gen_axi.read_cnt_reg\(2),
I1 => \gen_axi.read_cnt_reg\(3),
O => \gen_axi.s_axi_rlast_i_i_3_n_0\
);
\gen_axi.s_axi_rlast_i_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \gen_axi.read_cnt_reg\(4),
I1 => \gen_axi.read_cnt_reg\(5),
I2 => \gen_axi.read_cnt_reg\(6),
I3 => \gen_axi.read_cnt_reg\(7),
I4 => mi_rready_4,
I5 => \^p_23_in\,
O => \gen_axi.s_axi_rlast_i_i_4_n_0\
);
\gen_axi.s_axi_rlast_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_rlast_i_i_1_n_0\,
Q => \^p_25_in\,
R => SR(0)
);
\gen_axi.s_axi_wready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF5F000C"
)
port map (
I0 => \write_cs0__0\,
I1 => write_cs01_out,
I2 => write_cs(0),
I3 => write_cs(1),
I4 => \^p_22_in\,
O => \gen_axi.s_axi_wready_i_i_1_n_0\
);
\gen_axi.s_axi_wready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_wready_i_i_1_n_0\,
Q => \^p_22_in\,
R => SR(0)
);
\gen_axi.write_cs[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4522"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => write_cs(1),
I2 => \write_cs0__0\,
I3 => write_cs(0),
O => \gen_axi.write_cs[0]_i_1_n_0\
);
\gen_axi.write_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE00FE44"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => write_cs(1),
I2 => \write_cs0__0\,
I3 => write_cs(0),
I4 => mi_bready_4,
O => \gen_axi.write_cs[1]_i_1_n_0\
);
\gen_axi.write_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[0]_i_1_n_0\,
Q => write_cs(0),
R => SR(0)
);
\gen_axi.write_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[1]_i_1_n_0\,
Q => write_cs(1),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter is
port (
\s_axi_awready[0]\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
ss_wr_awvalid : out STD_LOGIC;
ss_wr_awready : in STD_LOGIC;
ss_aa_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter : entity is "axi_crossbar_v2_1_14_splitter";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_valid_i_i_2__0\ : label is "soft_lutpair190";
attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair190";
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C0008000C0000"
)
port map (
I0 => s_axi_awvalid(0),
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => ss_wr_awready,
I4 => \^m_ready_d\(0),
I5 => ss_aa_awready,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000C8C0"
)
port map (
I0 => s_axi_awvalid(0),
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => ss_wr_awready,
I4 => \^m_ready_d\(0),
I5 => ss_aa_awready,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\m_valid_i_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(1),
O => ss_wr_awvalid
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEE0"
)
port map (
I0 => \^m_ready_d\(1),
I1 => ss_wr_awready,
I2 => \^m_ready_d\(0),
I3 => ss_aa_awready,
O => \s_axi_awready[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter_5 is
port (
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_axi.s_axi_awready_i_reg\ : out STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[19]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[3].w_issuing_cnt_reg[27]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[0].w_issuing_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 15 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_108_out : in STD_LOGIC;
\chosen_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_88_out : in STD_LOGIC;
p_68_out : in STD_LOGIC;
p_128_out : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\mi_awready_mux__3\ : in STD_LOGIC;
\s_ready_i0__1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\sa_wm_awready_mux__3\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter_5 : entity is "axi_crossbar_v2_1_14_splitter";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter_5;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter_5 is
signal \^gen_axi.s_axi_awready_i_reg\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\ : STD_LOGIC;
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_awready_i_i_2\ : label is "soft_lutpair194";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[2]_i_1\ : label is "soft_lutpair197";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_2\ : label is "soft_lutpair197";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[10]_i_1\ : label is "soft_lutpair193";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_2\ : label is "soft_lutpair193";
attribute SOFT_HLUTNM of \gen_master_slots[2].w_issuing_cnt[18]_i_1\ : label is "soft_lutpair195";
attribute SOFT_HLUTNM of \gen_master_slots[2].w_issuing_cnt[19]_i_2\ : label is "soft_lutpair195";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[26]_i_1\ : label is "soft_lutpair196";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[27]_i_2\ : label is "soft_lutpair196";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_1\ : label is "soft_lutpair194";
begin
\gen_axi.s_axi_awready_i_reg\ <= \^gen_axi.s_axi_awready_i_reg\;
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\gen_axi.s_axi_awready_i_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_ready_d\(1),
I1 => aa_sa_awvalid,
O => \^gen_axi.s_axi_awready_i_reg\
);
\gen_master_slots[0].w_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(0),
I1 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I2 => w_issuing_cnt(1),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(0)
);
\gen_master_slots[0].w_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I1 => w_issuing_cnt(0),
I2 => w_issuing_cnt(1),
I3 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(1)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(1),
I1 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I2 => w_issuing_cnt(0),
I3 => w_issuing_cnt(3),
I4 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(2)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(0),
I2 => m_axi_awready(0),
I3 => s_axi_bready(0),
I4 => p_128_out,
I5 => \chosen_reg[3]\(0),
O => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I1 => w_issuing_cnt(4),
I2 => w_issuing_cnt(5),
I3 => w_issuing_cnt(6),
O => D(1)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(5),
I1 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I2 => w_issuing_cnt(4),
I3 => w_issuing_cnt(7),
I4 => w_issuing_cnt(6),
O => D(2)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(1),
I2 => m_axi_awready(1),
I3 => s_axi_bready(0),
I4 => p_108_out,
I5 => \chosen_reg[3]\(1),
O => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(4),
I1 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I2 => w_issuing_cnt(5),
O => D(0)
);
\gen_master_slots[2].w_issuing_cnt[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(8),
I1 => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\,
I2 => w_issuing_cnt(9),
O => \gen_master_slots[2].w_issuing_cnt_reg[19]\(0)
);
\gen_master_slots[2].w_issuing_cnt[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\,
I1 => w_issuing_cnt(8),
I2 => w_issuing_cnt(9),
I3 => w_issuing_cnt(10),
O => \gen_master_slots[2].w_issuing_cnt_reg[19]\(1)
);
\gen_master_slots[2].w_issuing_cnt[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(9),
I1 => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\,
I2 => w_issuing_cnt(8),
I3 => w_issuing_cnt(11),
I4 => w_issuing_cnt(10),
O => \gen_master_slots[2].w_issuing_cnt_reg[19]\(2)
);
\gen_master_slots[2].w_issuing_cnt[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(2),
I2 => m_axi_awready(2),
I3 => s_axi_bready(0),
I4 => p_88_out,
I5 => \chosen_reg[3]\(2),
O => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\
);
\gen_master_slots[3].w_issuing_cnt[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(12),
I1 => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\,
I2 => w_issuing_cnt(13),
O => \gen_master_slots[3].w_issuing_cnt_reg[27]\(0)
);
\gen_master_slots[3].w_issuing_cnt[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\,
I1 => w_issuing_cnt(12),
I2 => w_issuing_cnt(13),
I3 => w_issuing_cnt(14),
O => \gen_master_slots[3].w_issuing_cnt_reg[27]\(1)
);
\gen_master_slots[3].w_issuing_cnt[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(13),
I1 => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\,
I2 => w_issuing_cnt(12),
I3 => w_issuing_cnt(15),
I4 => w_issuing_cnt(14),
O => \gen_master_slots[3].w_issuing_cnt_reg[27]\(2)
);
\gen_master_slots[3].w_issuing_cnt[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(3),
I2 => m_axi_awready(3),
I3 => s_axi_bready(0),
I4 => p_68_out,
I5 => \chosen_reg[3]\(3),
O => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C0008000C0000"
)
port map (
I0 => aa_sa_awvalid,
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => \mi_awready_mux__3\,
I4 => \^m_ready_d\(0),
I5 => \sa_wm_awready_mux__3\,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000C8C0"
)
port map (
I0 => aa_sa_awvalid,
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => \mi_awready_mux__3\,
I4 => \s_ready_i0__1\(0),
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
port (
\storage_data1_reg[0]\ : out STD_LOGIC;
push : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
out0 : in STD_LOGIC_VECTOR ( 0 to 0 );
load_s1 : in STD_LOGIC;
m_select_enc : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
signal \gen_primitive_shifter.gen_srls[0].srl_inst_n_0\ : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => push,
CLK => aclk,
D => D(0),
Q => \gen_primitive_shifter.gen_srls[0].srl_inst_n_0\,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\storage_data1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0EEFFFFF0EE0000"
)
port map (
I0 => \s_axi_awaddr[30]\(1),
I1 => \s_axi_awaddr[30]\(0),
I2 => \gen_primitive_shifter.gen_srls[0].srl_inst_n_0\,
I3 => out0(0),
I4 => load_s1,
I5 => m_select_enc(0),
O => \storage_data1_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\ is
port (
\storage_data1_reg[1]\ : out STD_LOGIC;
push : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
out0 : in STD_LOGIC_VECTOR ( 0 to 0 );
load_s1 : in STD_LOGIC;
m_select_enc : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\ is
signal p_2_out : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => push,
CLK => aclk,
D => D(0),
Q => p_2_out,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\storage_data1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0EEFFFFF0EE0000"
)
port map (
I0 => \s_axi_awaddr[30]\(1),
I1 => \s_axi_awaddr[30]\(0),
I2 => p_2_out,
I3 => out0(0),
I4 => load_s1,
I5 => m_select_enc(0),
O => \storage_data1_reg[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\ is
port (
push : out STD_LOGIC;
\storage_data1_reg[2]\ : out STD_LOGIC;
\m_aready__1\ : out STD_LOGIC;
\m_aready0__3\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
match : in STD_LOGIC;
out0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
load_s1 : in STD_LOGIC;
m_select_enc : in STD_LOGIC_VECTOR ( 2 downto 0 );
ss_wr_awready : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_22_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\ is
signal \^m_aready0__3\ : STD_LOGIC;
signal \^m_aready__1\ : STD_LOGIC;
signal p_3_out : STD_LOGIC;
signal \^push\ : STD_LOGIC;
signal \s_axi_wready[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[2].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[2].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\m_aready0__3\ <= \^m_aready0__3\;
\m_aready__1\ <= \^m_aready__1\;
push <= \^push\;
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => \^push\,
CLK => aclk,
D => D(0),
Q => p_3_out,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0088000000F80000"
)
port map (
I0 => ss_wr_awready,
I1 => out0(0),
I2 => out0(1),
I3 => m_ready_d(0),
I4 => s_axi_awvalid(0),
I5 => \^m_aready__1\,
O => \^push\
);
\m_valid_i_i_1__8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => s_axi_wlast(0),
I1 => m_avalid,
I2 => s_axi_wvalid(0),
I3 => \^m_aready0__3\,
O => \^m_aready__1\
);
\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAFEAAAAAAAEA"
)
port map (
I0 => \s_axi_wready[0]_INST_0_i_2_n_0\,
I1 => m_axi_wready(1),
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
I5 => m_axi_wready(2),
O => \^m_aready0__3\
);
\s_axi_wready[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0000CA000000CA"
)
port map (
I0 => m_axi_wready(0),
I1 => p_22_in,
I2 => m_select_enc(2),
I3 => m_select_enc(1),
I4 => m_select_enc(0),
I5 => m_axi_wready(3),
O => \s_axi_wready[0]_INST_0_i_2_n_0\
);
\storage_data1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"C5FFC500"
)
port map (
I0 => match,
I1 => p_3_out,
I2 => out0(0),
I3 => load_s1,
I4 => m_select_enc(2),
O => \storage_data1_reg[2]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
\m_payload_i_reg[2]_0\ : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
mi_bready_4 : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_29_in : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\ : STD_LOGIC;
signal \^m_payload_i_reg[2]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^mi_bready_4\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
begin
\m_payload_i_reg[2]_0\ <= \^m_payload_i_reg[2]_0\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
mi_bready_4 <= \^mi_bready_4\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]\,
Q => \^s_ready_i_reg_0\,
R => '0'
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => p_29_in,
I1 => \^mi_bready_4\,
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[2]_0\,
I4 => Q(0),
O => \m_valid_i_i_1__0_n_0\
);
\m_valid_i_i_1__9\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^s_ready_i_reg_0\,
O => \^m_valid_i_reg_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__0_n_0\,
Q => \^m_payload_i_reg[2]_0\,
R => \^m_valid_i_reg_0\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
I1 => p_29_in,
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \^s_ready_i_reg_0\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^mi_bready_4\,
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
\m_axi_bid[35]\ : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC;
signal \s_ready_i_i_1__3_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i[13]_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => \m_valid_i_i_1__2_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__2_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__3_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__3_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
\m_axi_bid[23]\ : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal \s_ready_i_i_1__1_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i_i_1_n_0,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__1_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__1_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
p_108_out : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal \s_ready_i_i_1__0_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\last_rr_hot[2]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => p_108_out,
O => \chosen_reg[2]\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
m_valid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => m_valid_i_i_2_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i_i_2_n_0,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__0_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__0_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
\chosen_reg[4]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
p_88_out : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^p_1_in\ : STD_LOGIC;
signal s_ready_i_i_2_n_0 : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
p_1_in <= \^p_1_in\;
\aresetn_d[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(1),
I1 => aresetn,
O => \aresetn_d_reg[1]\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => p_0_in(1),
R => '0'
);
\last_rr_hot[4]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => p_88_out,
O => \chosen_reg[4]\
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]_0\
);
s_ready_i_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(1),
O => \^p_1_in\
);
s_ready_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_1\,
O => s_ready_i_i_2_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i_i_2_n_0,
Q => \^m_axi_bready\(0),
R => \^p_1_in\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\skid_buffer_reg[34]_0\ : out STD_LOGIC;
\r_cmd_pop_4__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_23_in : in STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_25_in : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \s_ready_i_i_1__6_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 34 );
signal \^skid_buffer_reg[34]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__3\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__3\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__3\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__3\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__3\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__3\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__3\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__3\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__3\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__3\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__3\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__3\ : label is "soft_lutpair114";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0);
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\skid_buffer_reg[34]_0\ <= \^skid_buffer_reg[34]_0\;
\gen_master_slots[4].r_issuing_cnt[32]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
I1 => \chosen_reg[4]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \r_cmd_pop_4__1\
);
\m_payload_i[34]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => p_25_in,
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(0),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(1),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(2),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(3),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(4),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[40]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(5),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(6),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(7),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(8),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(9),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(10),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(11),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_valid_i_i_1__5\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^skid_buffer_reg[34]_0\,
I1 => p_23_in,
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[4]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__6\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[4]\(0),
I3 => \^skid_buffer_reg[34]_0\,
I4 => p_23_in,
O => \s_ready_i_i_1__6_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__6_n_0\,
Q => \^skid_buffer_reg[34]_0\,
R => p_1_in
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => p_25_in,
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[3]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_3__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[4]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].r_issuing_cnt_reg[27]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_39_in : in STD_LOGIC;
p_82_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\chosen_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \^m_axi_rready[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_3__1\ : STD_LOGIC;
signal \s_ready_i_i_1__7_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[27]_i_3\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \last_rr_hot[4]_i_3\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__7\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__2\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__2\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__2\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__2\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__2\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__2\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__2\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__2\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__2\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__2\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__2\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__2\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__2\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__2\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__2\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__2\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__2\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__2\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__2\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__2\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair110";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[3]\ <= \^m_axi_rready[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_3__1\ <= \^r_cmd_pop_3__1\;
\gen_master_slots[3].r_issuing_cnt[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(1),
I1 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(2),
I2 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(0),
I3 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(3),
I4 => \^r_cmd_pop_3__1\,
I5 => p_39_in,
O => E(0)
);
\gen_master_slots[3].r_issuing_cnt[27]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[3]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_3__1\
);
\gen_no_arbiter.s_ready_i[0]_i_38__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_3__1\,
I1 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(0),
I2 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(3),
I3 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(1),
I4 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(2),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\last_rr_hot[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => p_82_out,
O => \chosen_reg[4]\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__7\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__6\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[3]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[3]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__7\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[3]\(0),
I3 => \^m_axi_rready[3]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__7_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__7_n_0\,
Q => \^m_axi_rready[3]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[2]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_2__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].r_issuing_cnt_reg[19]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_57_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\gen_master_slots[3].r_issuing_cnt_reg[24]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\chosen_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_37__0_n_0\ : STD_LOGIC;
signal \^m_axi_rready[2]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_2__1\ : STD_LOGIC;
signal \s_ready_i_i_1__8_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__6\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair85";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[2]\ <= \^m_axi_rready[2]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_2__1\ <= \^r_cmd_pop_2__1\;
\gen_master_slots[2].r_issuing_cnt[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(1),
I1 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(2),
I2 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(0),
I3 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(3),
I4 => \^r_cmd_pop_2__1\,
I5 => p_57_in,
O => E(0)
);
\gen_master_slots[2].r_issuing_cnt[19]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[2]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_2__1\
);
\gen_no_arbiter.s_ready_i[0]_i_26__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ECA0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_37__0_n_0\,
I1 => \gen_master_slots[3].r_issuing_cnt_reg[24]\,
I2 => D(0),
I3 => D(1),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_37__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_2__1\,
I1 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(0),
I2 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(3),
I3 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(1),
I4 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_37__0_n_0\
);
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__6\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__7\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[2]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[2]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__8\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[2]\(0),
I3 => \^m_axi_rready[2]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__8_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__8_n_0\,
Q => \^m_axi_rready[2]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_1__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_75_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\chosen_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_35__0_n_0\ : STD_LOGIC;
signal \^m_axi_rready[1]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_1__1\ : STD_LOGIC;
signal \s_ready_i_i_1__5_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__5\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair62";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[1]\ <= \^m_axi_rready[1]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_1__1\ <= \^r_cmd_pop_1__1\;
\gen_master_slots[1].r_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1),
I1 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2),
I2 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0),
I3 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(3),
I4 => \^r_cmd_pop_1__1\,
I5 => p_75_in,
O => E(0)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[1]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_1__1\
);
\gen_no_arbiter.s_ready_i[0]_i_25__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_35__0_n_0\,
I1 => D(0),
I2 => ADDRESS_HIT_0,
I3 => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_35__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_1__1\,
I1 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0),
I2 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(3),
I3 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1),
I4 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_35__0_n_0\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[1]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[1]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__5\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[1]\(0),
I3 => \^m_axi_rready[1]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__5_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__5_n_0\,
Q => \^m_axi_rready[1]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_0__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[2]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_93_in : in STD_LOGIC;
p_102_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\chosen_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \^m_axi_rready[0]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_0__1\ : STD_LOGIC;
signal \s_ready_i_i_1__4_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_3\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_2\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__4\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair40";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[0]\ <= \^m_axi_rready[0]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_0__1\ <= \^r_cmd_pop_0__1\;
\gen_master_slots[0].r_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1),
I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2),
I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3),
I4 => \^r_cmd_pop_0__1\,
I5 => p_93_in,
O => E(0)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[0]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_0__1\
);
\gen_no_arbiter.s_ready_i[0]_i_36__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_0__1\,
I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0),
I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1),
I4 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\last_rr_hot[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => p_102_out,
O => \chosen_reg[2]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[0]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[0]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[0]\(0),
I3 => \^m_axi_rready[0]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__4_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__4_n_0\,
Q => \^m_axi_rready[0]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc is
port (
\s_axi_rid[0]\ : out STD_LOGIC;
\s_axi_rid[1]\ : out STD_LOGIC;
\s_axi_rid[2]\ : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC;
\s_axi_rid[4]\ : out STD_LOGIC;
\s_axi_rid[5]\ : out STD_LOGIC;
\s_axi_rid[6]\ : out STD_LOGIC;
\s_axi_rid[7]\ : out STD_LOGIC;
\s_axi_rid[8]\ : out STD_LOGIC;
\s_axi_rid[9]\ : out STD_LOGIC;
\s_axi_rid[10]\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
resp_select : in STD_LOGIC_VECTOR ( 0 to 0 );
f_mux4_return : in STD_LOGIC_VECTOR ( 46 downto 0 );
st_mr_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_0 : in STD_LOGIC;
\thread_valid_0__2\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_3 : in STD_LOGIC;
\thread_valid_3__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_4 : in STD_LOGIC;
\thread_valid_4__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_7 : in STD_LOGIC;
\thread_valid_7__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_6 : in STD_LOGIC;
\thread_valid_6__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_5 : in STD_LOGIC;
\thread_valid_5__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_2 : in STD_LOGIC;
\thread_valid_2__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_1 : in STD_LOGIC;
\thread_valid_1__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ARREADY : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc : entity is "generic_baseblocks_v2_1_0_mux_enc";
end zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc is
signal \any_pop__1\ : STD_LOGIC;
signal \^s_axi_rid[0]\ : STD_LOGIC;
signal \^s_axi_rid[10]\ : STD_LOGIC;
signal \^s_axi_rid[11]\ : STD_LOGIC;
signal \^s_axi_rid[1]\ : STD_LOGIC;
signal \^s_axi_rid[2]\ : STD_LOGIC;
signal \^s_axi_rid[3]\ : STD_LOGIC;
signal \^s_axi_rid[4]\ : STD_LOGIC;
signal \^s_axi_rid[5]\ : STD_LOGIC;
signal \^s_axi_rid[6]\ : STD_LOGIC;
signal \^s_axi_rid[7]\ : STD_LOGIC;
signal \^s_axi_rid[8]\ : STD_LOGIC;
signal \^s_axi_rid[9]\ : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[0].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[10].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[11].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[12].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[13].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[15].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[16].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[17].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[18].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[19].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[1].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[20].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[21].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[22].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[23].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[24].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[25].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[26].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[27].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[28].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[29].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[2].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[30].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[31].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[32].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[33].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[34].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[35].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[36].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[37].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[38].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[39].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[3].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[40].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[41].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[42].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[43].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[44].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[45].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[46].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[47].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[4].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[5].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[6].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[7].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[8].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[9].mux_s2_inst\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1__0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1__0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_34__0\ : label is "soft_lutpair128";
begin
\s_axi_rid[0]\ <= \^s_axi_rid[0]\;
\s_axi_rid[10]\ <= \^s_axi_rid[10]\;
\s_axi_rid[11]\ <= \^s_axi_rid[11]\;
\s_axi_rid[1]\ <= \^s_axi_rid[1]\;
\s_axi_rid[2]\ <= \^s_axi_rid[2]\;
\s_axi_rid[3]\ <= \^s_axi_rid[3]\;
\s_axi_rid[4]\ <= \^s_axi_rid[4]\;
\s_axi_rid[5]\ <= \^s_axi_rid[5]\;
\s_axi_rid[6]\ <= \^s_axi_rid[6]\;
\s_axi_rid[7]\ <= \^s_axi_rid[7]\;
\s_axi_rid[8]\ <= \^s_axi_rid[8]\;
\s_axi_rid[9]\ <= \^s_axi_rid[9]\;
s_axi_rlast(0) <= \^s_axi_rlast\(0);
\gen_fpga.gen_mux_5_8[0].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(0),
I1 => st_mr_rid(0),
O => \^s_axi_rid[0]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(10),
I1 => st_mr_rid(10),
O => \^s_axi_rid[10]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(11),
I1 => st_mr_rid(11),
O => \^s_axi_rid[11]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(12),
I1 => '1',
O => s_axi_rresp(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(13),
I1 => '1',
O => s_axi_rresp(1),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[15].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(14),
I1 => '0',
O => s_axi_rdata(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[16].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(15),
I1 => '0',
O => s_axi_rdata(1),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[17].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(16),
I1 => '0',
O => s_axi_rdata(2),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[18].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(17),
I1 => '0',
O => s_axi_rdata(3),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[19].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(18),
I1 => '0',
O => s_axi_rdata(4),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(1),
I1 => st_mr_rid(1),
O => \^s_axi_rid[1]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[20].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(19),
I1 => '0',
O => s_axi_rdata(5),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[21].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(20),
I1 => '0',
O => s_axi_rdata(6),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[22].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(21),
I1 => '0',
O => s_axi_rdata(7),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[23].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(22),
I1 => '0',
O => s_axi_rdata(8),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[24].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(23),
I1 => '0',
O => s_axi_rdata(9),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[25].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(24),
I1 => '0',
O => s_axi_rdata(10),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[26].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(25),
I1 => '0',
O => s_axi_rdata(11),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[27].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(26),
I1 => '0',
O => s_axi_rdata(12),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[28].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(27),
I1 => '0',
O => s_axi_rdata(13),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[29].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(28),
I1 => '0',
O => s_axi_rdata(14),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(2),
I1 => st_mr_rid(2),
O => \^s_axi_rid[2]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[30].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(29),
I1 => '0',
O => s_axi_rdata(15),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[31].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(30),
I1 => '0',
O => s_axi_rdata(16),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[32].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(31),
I1 => '0',
O => s_axi_rdata(17),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[33].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(32),
I1 => '0',
O => s_axi_rdata(18),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[34].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(33),
I1 => '0',
O => s_axi_rdata(19),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[35].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(34),
I1 => '0',
O => s_axi_rdata(20),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[36].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(35),
I1 => '0',
O => s_axi_rdata(21),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[37].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(36),
I1 => '0',
O => s_axi_rdata(22),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[38].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(37),
I1 => '0',
O => s_axi_rdata(23),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[39].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(38),
I1 => '0',
O => s_axi_rdata(24),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(3),
I1 => st_mr_rid(3),
O => \^s_axi_rid[3]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[40].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(39),
I1 => '0',
O => s_axi_rdata(25),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[41].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(40),
I1 => '0',
O => s_axi_rdata(26),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[42].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(41),
I1 => '0',
O => s_axi_rdata(27),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[43].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(42),
I1 => '0',
O => s_axi_rdata(28),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[44].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(43),
I1 => '0',
O => s_axi_rdata(29),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[45].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(44),
I1 => '0',
O => s_axi_rdata(30),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[46].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(45),
I1 => '0',
O => s_axi_rdata(31),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[47].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(46),
I1 => \m_payload_i_reg[34]\(0),
O => \^s_axi_rlast\(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(4),
I1 => st_mr_rid(4),
O => \^s_axi_rid[4]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(5),
I1 => st_mr_rid(5),
O => \^s_axi_rid[5]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(6),
I1 => st_mr_rid(6),
O => \^s_axi_rid[6]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(7),
I1 => st_mr_rid(7),
O => \^s_axi_rid[7]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(8),
I1 => st_mr_rid(8),
O => \^s_axi_rid[8]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(9),
I1 => st_mr_rid(9),
O => \^s_axi_rid[9]\,
S => resp_select(0)
);
\gen_multi_thread.accept_cnt[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9A65"
)
port map (
I0 => Q(0),
I1 => \any_pop__1\,
I2 => S_AXI_ARREADY(0),
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFF2200D"
)
port map (
I0 => S_AXI_ARREADY(0),
I1 => \any_pop__1\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
I3 => Q(3),
I4 => \any_pop__1\,
I5 => S_AXI_ARREADY(0),
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FF0800FFAE0051"
)
port map (
I0 => Q(1),
I1 => S_AXI_ARREADY(0),
I2 => \any_pop__1\,
I3 => Q(0),
I4 => Q(3),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_0,
I1 => \any_pop__1\,
I2 => \thread_valid_0__2\,
I3 => CO(0),
O => E(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_1,
I1 => \any_pop__1\,
I2 => \thread_valid_1__2\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_2,
I1 => \any_pop__1\,
I2 => \thread_valid_2__2\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_3,
I1 => \any_pop__1\,
I2 => \thread_valid_3__2\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_4,
I1 => \any_pop__1\,
I2 => \thread_valid_4__2\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_5,
I1 => \any_pop__1\,
I2 => \thread_valid_5__2\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_6,
I1 => \any_pop__1\,
I2 => \thread_valid_6__2\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_7,
I1 => \any_pop__1\,
I2 => \thread_valid_7__2\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_rready(0),
I1 => \^s_axi_rlast\(0),
I2 => \chosen_reg[0]\,
O => \any_pop__1\
);
\gen_no_arbiter.s_ready_i[0]_i_34__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_axi_rlast\(0),
I1 => s_axi_rready(0),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\i__carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(9),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11),
I5 => \^s_axi_rid[11]\,
O => S(3)
);
\i__carry_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(6),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(8),
I5 => \^s_axi_rid[8]\,
O => S(2)
);
\i__carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(3),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(5),
I5 => \^s_axi_rid[5]\,
O => S(1)
);
\i__carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(0),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(2),
I5 => \^s_axi_rid[2]\,
O => S(0)
);
p_10_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(9),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3)
);
p_10_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(6),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2)
);
p_10_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(3),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1)
);
p_10_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(0),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0)
);
p_12_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3)
);
p_12_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2)
);
p_12_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1)
);
p_12_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0)
);
p_14_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(9),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3)
);
p_14_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(6),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2)
);
p_14_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(3),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1)
);
p_14_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(0),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
p_2_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(9),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3)
);
p_2_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(6),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2)
);
p_2_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(3),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1)
);
p_2_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(0),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0)
);
p_4_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(9),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3)
);
p_4_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(6),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2)
);
p_4_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(3),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1)
);
p_4_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(0),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0)
);
p_6_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(9),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3)
);
p_6_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(6),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2)
);
p_6_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(3),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1)
);
p_6_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(0),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0)
);
p_8_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(9),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3)
);
p_8_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(6),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2)
);
p_8_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(3),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1)
);
p_8_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(0),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc__parameterized0\ is
port (
\s_axi_bid[0]\ : out STD_LOGIC;
\s_axi_bid[1]\ : out STD_LOGIC;
\s_axi_bid[2]\ : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC;
\s_axi_bid[4]\ : out STD_LOGIC;
\s_axi_bid[5]\ : out STD_LOGIC;
\s_axi_bid[6]\ : out STD_LOGIC;
\s_axi_bid[7]\ : out STD_LOGIC;
\s_axi_bid[8]\ : out STD_LOGIC;
\s_axi_bid[9]\ : out STD_LOGIC;
\s_axi_bid[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
p_0_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
resp_select : in STD_LOGIC_VECTOR ( 0 to 0 );
f_mux4_return : in STD_LOGIC_VECTOR ( 13 downto 0 );
st_mr_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
cmd_push_0 : in STD_LOGIC;
\thread_valid_0__2\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_3 : in STD_LOGIC;
\thread_valid_3__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_4 : in STD_LOGIC;
\thread_valid_4__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_7 : in STD_LOGIC;
\thread_valid_7__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_6 : in STD_LOGIC;
\thread_valid_6__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_5 : in STD_LOGIC;
\thread_valid_5__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_2 : in STD_LOGIC;
\thread_valid_2__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_1 : in STD_LOGIC;
\thread_valid_1__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc__parameterized0\ : entity is "generic_baseblocks_v2_1_0_mux_enc";
end \zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc__parameterized0\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc__parameterized0\ is
signal \any_pop__1\ : STD_LOGIC;
signal \^p_0_out\ : STD_LOGIC;
signal \^s_axi_bid[0]\ : STD_LOGIC;
signal \^s_axi_bid[10]\ : STD_LOGIC;
signal \^s_axi_bid[11]\ : STD_LOGIC;
signal \^s_axi_bid[1]\ : STD_LOGIC;
signal \^s_axi_bid[2]\ : STD_LOGIC;
signal \^s_axi_bid[3]\ : STD_LOGIC;
signal \^s_axi_bid[4]\ : STD_LOGIC;
signal \^s_axi_bid[5]\ : STD_LOGIC;
signal \^s_axi_bid[6]\ : STD_LOGIC;
signal \^s_axi_bid[7]\ : STD_LOGIC;
signal \^s_axi_bid[8]\ : STD_LOGIC;
signal \^s_axi_bid[9]\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[0].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[10].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[11].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[12].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[13].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[15].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[1].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[2].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[3].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[4].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[5].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[6].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[7].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[8].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[9].mux_s2_inst\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1\ : label is "soft_lutpair162";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1\ : label is "soft_lutpair162";
begin
p_0_out <= \^p_0_out\;
\s_axi_bid[0]\ <= \^s_axi_bid[0]\;
\s_axi_bid[10]\ <= \^s_axi_bid[10]\;
\s_axi_bid[11]\ <= \^s_axi_bid[11]\;
\s_axi_bid[1]\ <= \^s_axi_bid[1]\;
\s_axi_bid[2]\ <= \^s_axi_bid[2]\;
\s_axi_bid[3]\ <= \^s_axi_bid[3]\;
\s_axi_bid[4]\ <= \^s_axi_bid[4]\;
\s_axi_bid[5]\ <= \^s_axi_bid[5]\;
\s_axi_bid[6]\ <= \^s_axi_bid[6]\;
\s_axi_bid[7]\ <= \^s_axi_bid[7]\;
\s_axi_bid[8]\ <= \^s_axi_bid[8]\;
\s_axi_bid[9]\ <= \^s_axi_bid[9]\;
\gen_fpga.gen_mux_5_8[0].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(0),
I1 => st_mr_bid(0),
O => \^s_axi_bid[0]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(10),
I1 => st_mr_bid(10),
O => \^s_axi_bid[10]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(11),
I1 => st_mr_bid(11),
O => \^s_axi_bid[11]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(12),
I1 => '1',
O => s_axi_bresp(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(13),
I1 => '1',
O => s_axi_bresp(1),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[15].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => '1',
I1 => '1',
O => \^p_0_out\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(1),
I1 => st_mr_bid(1),
O => \^s_axi_bid[1]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(2),
I1 => st_mr_bid(2),
O => \^s_axi_bid[2]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(3),
I1 => st_mr_bid(3),
O => \^s_axi_bid[3]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(4),
I1 => st_mr_bid(4),
O => \^s_axi_bid[4]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(5),
I1 => st_mr_bid(5),
O => \^s_axi_bid[5]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(6),
I1 => st_mr_bid(6),
O => \^s_axi_bid[6]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(7),
I1 => st_mr_bid(7),
O => \^s_axi_bid[7]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(8),
I1 => st_mr_bid(8),
O => \^s_axi_bid[8]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(9),
I1 => st_mr_bid(9),
O => \^s_axi_bid[9]\,
S => resp_select(0)
);
\gen_multi_thread.accept_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9A65"
)
port map (
I0 => Q(0),
I1 => \any_pop__1\,
I2 => \m_ready_d_reg[1]\,
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFF2200D"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \any_pop__1\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
I3 => Q(3),
I4 => \any_pop__1\,
I5 => \m_ready_d_reg[1]\,
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FF0800FFAE0051"
)
port map (
I0 => Q(1),
I1 => \m_ready_d_reg[1]\,
I2 => \any_pop__1\,
I3 => Q(0),
I4 => Q(3),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_0,
I1 => \any_pop__1\,
I2 => \thread_valid_0__2\,
I3 => CO(0),
O => E(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_1,
I1 => \any_pop__1\,
I2 => \thread_valid_1__2\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_2,
I1 => \any_pop__1\,
I2 => \thread_valid_2__2\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_3,
I1 => \any_pop__1\,
I2 => \thread_valid_3__2\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_4,
I1 => \any_pop__1\,
I2 => \thread_valid_4__2\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_5,
I1 => \any_pop__1\,
I2 => \thread_valid_5__2\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_6,
I1 => \any_pop__1\,
I2 => \thread_valid_6__2\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_7,
I1 => \any_pop__1\,
I2 => \thread_valid_7__2\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_bready(0),
I1 => \^p_0_out\,
I2 => m_valid_i_reg,
O => \any_pop__1\
);
\i__carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(9),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11),
I5 => \^s_axi_bid[11]\,
O => S(3)
);
\i__carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(6),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(8),
I5 => \^s_axi_bid[8]\,
O => S(2)
);
\i__carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(3),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(5),
I5 => \^s_axi_bid[5]\,
O => S(1)
);
\i__carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(0),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(2),
I5 => \^s_axi_bid[2]\,
O => S(0)
);
\p_10_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(9),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3)
);
\p_10_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(6),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2)
);
\p_10_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(3),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1)
);
\p_10_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(0),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0)
);
\p_12_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3)
);
\p_12_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2)
);
\p_12_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1)
);
\p_12_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0)
);
\p_14_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(9),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3)
);
\p_14_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(6),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2)
);
\p_14_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(3),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1)
);
\p_14_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(0),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
\p_2_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(9),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3)
);
\p_2_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(6),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2)
);
\p_2_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(3),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1)
);
\p_2_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(0),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0)
);
\p_4_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(9),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3)
);
\p_4_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(6),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2)
);
\p_4_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(3),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1)
);
\p_4_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(0),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0)
);
\p_6_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(9),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3)
);
\p_6_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(6),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2)
);
\p_6_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(3),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1)
);
\p_6_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(0),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0)
);
\p_8_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(9),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3)
);
\p_8_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(6),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2)
);
\p_8_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(3),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1)
);
\p_8_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(0),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor is
port (
\s_axi_rid[0]\ : out STD_LOGIC;
\s_axi_rid[1]\ : out STD_LOGIC;
\s_axi_rid[2]\ : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC;
\s_axi_rid[4]\ : out STD_LOGIC;
\s_axi_rid[5]\ : out STD_LOGIC;
\s_axi_rid[6]\ : out STD_LOGIC;
\s_axi_rid[7]\ : out STD_LOGIC;
\s_axi_rid[8]\ : out STD_LOGIC;
\s_axi_rid[9]\ : out STD_LOGIC;
\s_axi_rid[10]\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
\s_axi_rvalid[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
st_mr_rid : in STD_LOGIC_VECTOR ( 59 downto 0 );
\m_payload_i_reg[34]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : in STD_LOGIC;
\r_cmd_pop_4__1\ : in STD_LOGIC;
match : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
\s_axi_araddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ARREADY : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_122_out : in STD_LOGIC;
st_mr_rmesg : in STD_LOGIC_VECTOR ( 135 downto 0 );
\m_payload_i_reg[34]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_62_out : in STD_LOGIC;
p_102_out : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
p_40_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_82_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\s_axi_arid[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor : entity is "axi_crossbar_v2_1_14_si_transactor";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \accum_push_5__0\ : STD_LOGIC;
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 58 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal aid_match_00_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal \aid_match_0__0\ : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal aid_match_10_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal \aid_match_1__0\ : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal aid_match_20_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal \aid_match_2__0\ : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal aid_match_30_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal \aid_match_3__0\ : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal aid_match_40_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal \aid_match_4__0\ : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal aid_match_50_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal \aid_match_5__0\ : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal aid_match_60_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal \aid_match_6__0\ : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal aid_match_70_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal \aid_match_7__0\ : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal f_mux4_return : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \gen_multi_thread.accept_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_47\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_48\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_49\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_50\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_51\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_52\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_53\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_54\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_55\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_56\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_57\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_58\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_59\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_60\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_61\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_62\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_63\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_64\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_65\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_66\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_67\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_68\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_69\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_70\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_71\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_72\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_73\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_74\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_75\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_76\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_77\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_78\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_79\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_80\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_81\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_82\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_83\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_84\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_85\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_86\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_87\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_88\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_89\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_90\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_91\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_23__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_27__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_28_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_30__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_31_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_33__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_7__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal resp_select : STD_LOGIC_VECTOR ( 2 to 2 );
signal \^s_axi_rvalid[0]\ : STD_LOGIC;
signal \thread_valid_0__2\ : STD_LOGIC;
signal \thread_valid_1__2\ : STD_LOGIC;
signal \thread_valid_2__2\ : STD_LOGIC;
signal \thread_valid_3__2\ : STD_LOGIC;
signal \thread_valid_4__2\ : STD_LOGIC;
signal \thread_valid_5__2\ : STD_LOGIC;
signal \thread_valid_6__2\ : STD_LOGIC;
signal \thread_valid_7__2\ : STD_LOGIC;
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1\ : label is "soft_lutpair155";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\ : label is "soft_lutpair147";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\ : label is "soft_lutpair147";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\ : label is "soft_lutpair150";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\ : label is "soft_lutpair150";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\ : label is "soft_lutpair149";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\ : label is "soft_lutpair149";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2__0\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3__0\ : label is "soft_lutpair143";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4__0\ : label is "soft_lutpair144";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\ : label is "soft_lutpair154";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\ : label is "soft_lutpair154";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\ : label is "soft_lutpair153";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\ : label is "soft_lutpair153";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3__0\ : label is "soft_lutpair145";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4__0\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\ : label is "soft_lutpair151";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\ : label is "soft_lutpair151";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\ : label is "soft_lutpair148";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\ : label is "soft_lutpair148";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2__0\ : label is "soft_lutpair146";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3__0\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\ : label is "soft_lutpair152";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\ : label is "soft_lutpair152";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5__0\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9__0\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_10__0\ : label is "soft_lutpair145";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_13__0\ : label is "soft_lutpair144";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_16__0\ : label is "soft_lutpair143";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_19__0\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_20__0\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_27__0\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_29__0\ : label is "soft_lutpair146";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_32__0\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_33__0\ : label is "soft_lutpair155";
begin
D(0) <= \^d\(0);
\s_axi_rvalid[0]\ <= \^s_axi_rvalid[0]\;
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_00_carry_i_1_n_0,
S(2) => aid_match_00_carry_i_2_n_0,
S(1) => aid_match_00_carry_i_3_n_0,
S(0) => aid_match_00_carry_i_4_n_0
);
aid_match_00_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
O => aid_match_00_carry_i_1_n_0
);
aid_match_00_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
O => aid_match_00_carry_i_2_n_0
);
aid_match_00_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
O => aid_match_00_carry_i_3_n_0
);
aid_match_00_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
O => aid_match_00_carry_i_4_n_0
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_10_carry_i_1_n_0,
S(2) => aid_match_10_carry_i_2_n_0,
S(1) => aid_match_10_carry_i_3_n_0,
S(0) => aid_match_10_carry_i_4_n_0
);
aid_match_10_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
I5 => \s_axi_arid[11]\(11),
O => aid_match_10_carry_i_1_n_0
);
aid_match_10_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
I5 => \s_axi_arid[11]\(8),
O => aid_match_10_carry_i_2_n_0
);
aid_match_10_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
I5 => \s_axi_arid[11]\(5),
O => aid_match_10_carry_i_3_n_0
);
aid_match_10_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
I5 => \s_axi_arid[11]\(2),
O => aid_match_10_carry_i_4_n_0
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_20_carry_i_1_n_0,
S(2) => aid_match_20_carry_i_2_n_0,
S(1) => aid_match_20_carry_i_3_n_0,
S(0) => aid_match_20_carry_i_4_n_0
);
aid_match_20_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
O => aid_match_20_carry_i_1_n_0
);
aid_match_20_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
O => aid_match_20_carry_i_2_n_0
);
aid_match_20_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
O => aid_match_20_carry_i_3_n_0
);
aid_match_20_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
O => aid_match_20_carry_i_4_n_0
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_30_carry_i_1_n_0,
S(2) => aid_match_30_carry_i_2_n_0,
S(1) => aid_match_30_carry_i_3_n_0,
S(0) => aid_match_30_carry_i_4_n_0
);
aid_match_30_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
O => aid_match_30_carry_i_1_n_0
);
aid_match_30_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
O => aid_match_30_carry_i_2_n_0
);
aid_match_30_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
O => aid_match_30_carry_i_3_n_0
);
aid_match_30_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
O => aid_match_30_carry_i_4_n_0
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_40_carry_i_1_n_0,
S(2) => aid_match_40_carry_i_2_n_0,
S(1) => aid_match_40_carry_i_3_n_0,
S(0) => aid_match_40_carry_i_4_n_0
);
aid_match_40_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
O => aid_match_40_carry_i_1_n_0
);
aid_match_40_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
O => aid_match_40_carry_i_2_n_0
);
aid_match_40_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
O => aid_match_40_carry_i_3_n_0
);
aid_match_40_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
O => aid_match_40_carry_i_4_n_0
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_50_carry_i_1_n_0,
S(2) => aid_match_50_carry_i_2_n_0,
S(1) => aid_match_50_carry_i_3_n_0,
S(0) => aid_match_50_carry_i_4_n_0
);
aid_match_50_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
O => aid_match_50_carry_i_1_n_0
);
aid_match_50_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
O => aid_match_50_carry_i_2_n_0
);
aid_match_50_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
O => aid_match_50_carry_i_3_n_0
);
aid_match_50_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
O => aid_match_50_carry_i_4_n_0
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_60_carry_i_1_n_0,
S(2) => aid_match_60_carry_i_2_n_0,
S(1) => aid_match_60_carry_i_3_n_0,
S(0) => aid_match_60_carry_i_4_n_0
);
aid_match_60_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
O => aid_match_60_carry_i_1_n_0
);
aid_match_60_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
O => aid_match_60_carry_i_2_n_0
);
aid_match_60_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
O => aid_match_60_carry_i_3_n_0
);
aid_match_60_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
O => aid_match_60_carry_i_4_n_0
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_70_carry_i_1_n_0,
S(2) => aid_match_70_carry_i_2_n_0,
S(1) => aid_match_70_carry_i_3_n_0,
S(0) => aid_match_70_carry_i_4_n_0
);
aid_match_70_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
O => aid_match_70_carry_i_1_n_0
);
aid_match_70_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
O => aid_match_70_carry_i_2_n_0
);
aid_match_70_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
O => aid_match_70_carry_i_3_n_0
);
aid_match_70_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
O => aid_match_70_carry_i_4_n_0
);
\gen_multi_thread.accept_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.accept_cnt[0]_i_1_n_0\,
Q => \gen_multi_thread.accept_cnt_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.mux_resp_multi_thread_n_58\,
Q => \gen_multi_thread.accept_cnt_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.mux_resp_multi_thread_n_57\,
Q => \gen_multi_thread.accept_cnt_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.mux_resp_multi_thread_n_56\,
Q => \gen_multi_thread.accept_cnt_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_8
port map (
E(0) => E(0),
Q(4 downto 0) => Q(4 downto 0),
SR(0) => SR(0),
S_AXI_ARREADY(0) => S_AXI_ARREADY(0),
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
aresetn_d => aresetn_d,
f_mux4_return(46 downto 14) => f_mux4_return(47 downto 15),
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
\gen_multi_thread.accept_cnt_reg[0]\ => \gen_no_arbiter.s_ready_i[0]_i_33__0_n_0\,
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.accept_cnt_reg__0\(3),
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ => \gen_no_arbiter.s_ready_i[0]_i_7__0_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\,
\m_payload_i_reg[0]\(0) => \m_payload_i_reg[0]\(0),
\m_payload_i_reg[0]_0\(0) => \m_payload_i_reg[0]_0\(0),
\m_payload_i_reg[0]_1\(0) => \m_payload_i_reg[0]_1\(0),
\m_payload_i_reg[0]_2\(0) => \m_payload_i_reg[0]_2\(0),
\m_payload_i_reg[34]\(0) => \m_payload_i_reg[34]\(0),
\m_payload_i_reg[34]_0\(0) => \m_payload_i_reg[34]_1\(0),
\m_payload_i_reg[34]_1\(0) => \m_payload_i_reg[34]_2\(0),
\m_payload_i_reg[34]_2\(0) => \m_payload_i_reg[34]_3\(0),
\m_payload_i_reg[34]_3\(0) => \m_payload_i_reg[34]_4\(0),
\m_payload_i_reg[34]_4\ => \gen_multi_thread.mux_resp_multi_thread_n_59\,
m_valid_i => m_valid_i,
m_valid_i_reg => m_valid_i_reg,
m_valid_i_reg_0 => m_valid_i_reg_0,
match => match,
p_102_out => p_102_out,
p_122_out => p_122_out,
p_40_out => p_40_out,
p_62_out => p_62_out,
p_82_out => p_82_out,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
r_issuing_cnt(0) => r_issuing_cnt(0),
resp_select(0) => resp_select(2),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_rready(0) => s_axi_rready(0),
\s_axi_rvalid[0]\ => \^s_axi_rvalid[0]\,
st_mr_rid(47 downto 0) => st_mr_rid(47 downto 0),
st_mr_rmesg(135 downto 0) => st_mr_rmesg(135 downto 0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(0),
I1 => cmd_push_0,
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(2),
I3 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(1),
I1 => cmd_push_0,
I2 => active_cnt(0),
I3 => active_cnt(3),
I4 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\,
Q => active_cnt(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\,
Q => active_cnt(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\,
Q => active_cnt(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\,
Q => active_cnt(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"E222"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I1 => \thread_valid_0__2\,
I2 => aid_match_00,
I3 => S_AXI_ARREADY(0),
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(0),
Q => active_target(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_1,
I1 => active_cnt(8),
I2 => active_cnt(10),
I3 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(9),
I1 => cmd_push_1,
I2 => active_cnt(8),
I3 => active_cnt(11),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(8),
I1 => cmd_push_1,
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\,
Q => active_cnt(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\,
Q => active_cnt(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\,
Q => active_cnt(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\,
Q => active_cnt(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8080808"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => aid_match_10,
I4 => S_AXI_ARREADY(0),
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(0),
Q => active_target(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(16),
I1 => cmd_push_2,
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_2,
I1 => active_cnt(16),
I2 => active_cnt(18),
I3 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(17),
I1 => cmd_push_2,
I2 => active_cnt(16),
I3 => active_cnt(19),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\,
Q => active_cnt(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\,
Q => active_cnt(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\,
Q => active_cnt(18),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\,
Q => active_cnt(19),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80008000800080"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => \thread_valid_2__2\,
I4 => aid_match_20,
I5 => S_AXI_ARREADY(0),
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(3),
I2 => active_cnt(1),
I3 => active_cnt(0),
O => \thread_valid_0__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
O => \thread_valid_1__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
O => \thread_valid_2__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(0),
Q => active_target(18),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(24),
I1 => cmd_push_3,
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(26),
I3 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(25),
I1 => cmd_push_3,
I2 => active_cnt(24),
I3 => active_cnt(27),
I4 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\,
Q => active_cnt(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\,
Q => active_cnt(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\,
Q => active_cnt(26),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\,
Q => active_cnt(27),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[26]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I2 => \thread_valid_3__2\,
I3 => aid_match_30,
I4 => S_AXI_ARREADY(0),
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(0),
Q => active_target(26),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(32),
I1 => cmd_push_4,
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_4,
I1 => active_cnt(32),
I2 => active_cnt(34),
I3 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(33),
I1 => cmd_push_4,
I2 => active_cnt(32),
I3 => active_cnt(35),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\,
Q => active_cnt(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\,
Q => active_cnt(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\,
Q => active_cnt(34),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\,
Q => active_cnt(35),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\,
I1 => \thread_valid_3__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I3 => \thread_valid_4__2\,
I4 => aid_match_40,
I5 => S_AXI_ARREADY(0),
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555557FFFFFFFF"
)
port map (
I0 => \thread_valid_0__2\,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
I5 => \thread_valid_2__2\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
O => \thread_valid_3__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(35),
I2 => active_cnt(33),
I3 => active_cnt(32),
O => \thread_valid_4__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(0),
Q => active_target(34),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(40),
I1 => cmd_push_5,
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_5,
I1 => active_cnt(40),
I2 => active_cnt(42),
I3 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(41),
I1 => cmd_push_5,
I2 => active_cnt(40),
I3 => active_cnt(43),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\,
Q => active_cnt(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\,
Q => active_cnt(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\,
Q => active_cnt(42),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\,
Q => active_cnt(43),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[42]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I2 => \thread_valid_5__2\,
I3 => aid_match_50,
I4 => S_AXI_ARREADY(0),
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(0),
Q => active_target(42),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(48),
I1 => cmd_push_6,
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_6,
I1 => active_cnt(48),
I2 => active_cnt(50),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(49),
I1 => cmd_push_6,
I2 => active_cnt(48),
I3 => active_cnt(51),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\,
Q => active_cnt(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\,
Q => active_cnt(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\,
Q => active_cnt(50),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\,
Q => active_cnt(51),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \thread_valid_5__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I3 => \thread_valid_6__2\,
I4 => aid_match_60,
I5 => S_AXI_ARREADY(0),
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
O => \thread_valid_5__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(51),
I2 => active_cnt(49),
I3 => active_cnt(48),
O => \thread_valid_6__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(0),
Q => active_target(50),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(56),
I1 => cmd_push_7,
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_7,
I1 => active_cnt(56),
I2 => active_cnt(58),
I3 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(57),
I1 => cmd_push_7,
I2 => active_cnt(56),
I3 => active_cnt(59),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
O => \thread_valid_7__2\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\,
Q => active_cnt(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\,
Q => active_cnt(57),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\,
Q => active_cnt(58),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\,
Q => active_cnt(59),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_araddr[30]\(2),
I1 => \s_axi_araddr[30]\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_araddr[30]\(2),
I1 => \s_axi_araddr[30]\(1),
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF404040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I3 => \aid_match_7__0\,
I4 => S_AXI_ARREADY(0),
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF55555557"
)
port map (
I0 => \thread_valid_3__2\,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
I5 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\,
O => \accum_push_5__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => \thread_valid_6__2\,
I5 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => S_AXI_ARREADY(0),
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0\,
I4 => \aid_match_6__0\,
I5 => \aid_match_7__0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
I4 => aid_match_70,
O => \aid_match_7__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_00,
I1 => \thread_valid_0__2\,
I2 => aid_match_10,
I3 => \thread_valid_1__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_20,
I1 => \thread_valid_2__2\,
I2 => aid_match_30,
I3 => \thread_valid_3__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_40,
I1 => \thread_valid_4__2\,
I2 => aid_match_50,
I3 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(48),
I1 => active_cnt(49),
I2 => active_cnt(51),
I3 => active_cnt(50),
I4 => aid_match_60,
O => \aid_match_6__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(57),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(0),
Q => active_target(58),
R => SR(0)
);
\gen_multi_thread.mux_resp_multi_thread\: entity work.zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc
port map (
CO(0) => p_14_out,
D(2) => \gen_multi_thread.mux_resp_multi_thread_n_56\,
D(1) => \gen_multi_thread.mux_resp_multi_thread_n_57\,
D(0) => \gen_multi_thread.mux_resp_multi_thread_n_58\,
E(0) => \gen_multi_thread.mux_resp_multi_thread_n_47\,
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg__0\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_60\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_61\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_62\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_63\,
S_AXI_ARREADY(0) => S_AXI_ARREADY(0),
\chosen_reg[0]\ => \^s_axi_rvalid[0]\,
cmd_push_0 => cmd_push_0,
cmd_push_1 => cmd_push_1,
cmd_push_2 => cmd_push_2,
cmd_push_3 => cmd_push_3,
cmd_push_4 => cmd_push_4,
cmd_push_5 => cmd_push_5,
cmd_push_6 => cmd_push_6,
cmd_push_7 => cmd_push_7,
f_mux4_return(46 downto 14) => f_mux4_return(47 downto 15),
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_55\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3) => \gen_multi_thread.mux_resp_multi_thread_n_88\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2) => \gen_multi_thread.mux_resp_multi_thread_n_89\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1) => \gen_multi_thread.mux_resp_multi_thread_n_90\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_91\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_54\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_84\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_85\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_86\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_87\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_53\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_80\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_81\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_82\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_83\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_48\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_76\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_77\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_78\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_79\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0) => p_8_out,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_49\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_72\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_73\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_74\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_75\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_52\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_68\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_69\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_70\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_71\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_51\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_64\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_65\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_66\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_67\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_50\,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0) => p_0_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_multi_thread.mux_resp_multi_thread_n_59\,
\m_payload_i_reg[34]\(0) => \m_payload_i_reg[34]_0\(0),
resp_select(0) => resp_select(2),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rid[0]\ => \s_axi_rid[0]\,
\s_axi_rid[10]\ => \s_axi_rid[10]\,
\s_axi_rid[11]\ => \s_axi_rid[11]\,
\s_axi_rid[1]\ => \s_axi_rid[1]\,
\s_axi_rid[2]\ => \s_axi_rid[2]\,
\s_axi_rid[3]\ => \s_axi_rid[3]\,
\s_axi_rid[4]\ => \s_axi_rid[4]\,
\s_axi_rid[5]\ => \s_axi_rid[5]\,
\s_axi_rid[6]\ => \s_axi_rid[6]\,
\s_axi_rid[7]\ => \s_axi_rid[7]\,
\s_axi_rid[8]\ => \s_axi_rid[8]\,
\s_axi_rid[9]\ => \s_axi_rid[9]\,
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
st_mr_rid(11 downto 0) => st_mr_rid(59 downto 48),
\thread_valid_0__2\ => \thread_valid_0__2\,
\thread_valid_1__2\ => \thread_valid_1__2\,
\thread_valid_2__2\ => \thread_valid_2__2\,
\thread_valid_3__2\ => \thread_valid_3__2\,
\thread_valid_4__2\ => \thread_valid_4__2\,
\thread_valid_5__2\ => \thread_valid_5__2\,
\thread_valid_6__2\ => \thread_valid_6__2\,
\thread_valid_7__2\ => \thread_valid_7__2\
);
\gen_no_arbiter.m_target_hot_i[4]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => match,
O => \^d\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(24),
I1 => active_cnt(25),
I2 => active_cnt(27),
I3 => active_cnt(26),
I4 => aid_match_30,
O => \aid_match_3__0\
);
\gen_no_arbiter.s_ready_i[0]_i_11__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(17),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(16),
O => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(18),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(16),
I1 => active_cnt(17),
I2 => active_cnt(19),
I3 => active_cnt(18),
I4 => aid_match_20,
O => \aid_match_2__0\
);
\gen_no_arbiter.s_ready_i[0]_i_14__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(9),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(8),
O => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_15__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(10),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_16__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(8),
I1 => active_cnt(9),
I2 => active_cnt(11),
I3 => active_cnt(10),
I4 => aid_match_10,
O => \aid_match_1__0\
);
\gen_no_arbiter.s_ready_i[0]_i_17__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(1),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(2),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(0),
I1 => active_cnt(1),
I2 => active_cnt(3),
I3 => active_cnt(2),
I4 => aid_match_00,
O => \aid_match_0__0\
);
\gen_no_arbiter.s_ready_i[0]_i_20__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(49),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(48),
O => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_21__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(50),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_22__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(57),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(56),
O => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_23__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(58),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_23__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_27__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(41),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(40),
O => \gen_no_arbiter.s_ready_i[0]_i_27__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_28\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(42),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_29__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(40),
I1 => active_cnt(41),
I2 => active_cnt(43),
I3 => active_cnt(42),
I4 => aid_match_50,
O => \aid_match_5__0\
);
\gen_no_arbiter.s_ready_i[0]_i_30__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(33),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(32),
O => \gen_no_arbiter.s_ready_i[0]_i_30__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_31\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(34),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_31_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_32__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(32),
I1 => active_cnt(33),
I2 => active_cnt(35),
I3 => active_cnt(34),
I4 => aid_match_40,
O => \aid_match_4__0\
);
\gen_no_arbiter.s_ready_i[0]_i_33__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(0),
I1 => \gen_multi_thread.accept_cnt_reg__0\(2),
I2 => \gen_multi_thread.accept_cnt_reg__0\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_33__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\,
I2 => \aid_match_3__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\,
I5 => \aid_match_2__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\,
I2 => \aid_match_1__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\,
I5 => \aid_match_0__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\,
I2 => \aid_match_6__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_23__0_n_0\,
I5 => \aid_match_7__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_27__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\,
I2 => \aid_match_5__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_30__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_31_n_0\,
I5 => \aid_match_4__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_7__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(25),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(26),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_60\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_61\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_62\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_63\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_80\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_81\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_82\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_83\
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_84\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_85\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_86\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_87\
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_88\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_89\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_90\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_91\
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_64\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_65\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_66\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_67\
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_68\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_69\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_70\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_71\
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_72\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_73\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_74\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_75\
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_76\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_77\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_78\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_79\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
port (
\s_axi_bid[0]\ : out STD_LOGIC;
\s_axi_bid[1]\ : out STD_LOGIC;
\s_axi_bid[2]\ : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC;
\s_axi_bid[4]\ : out STD_LOGIC;
\s_axi_bid[5]\ : out STD_LOGIC;
\s_axi_bid[6]\ : out STD_LOGIC;
\s_axi_bid[7]\ : out STD_LOGIC;
\s_axi_bid[8]\ : out STD_LOGIC;
\s_axi_bid[9]\ : out STD_LOGIC;
\s_axi_bid[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].w_issuing_cnt_reg[24]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\s_axi_bvalid[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
st_mr_bid : in STD_LOGIC_VECTOR ( 59 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 16 downto 0 );
p_84_in : in STD_LOGIC;
p_66_in : in STD_LOGIC;
p_48_in : in STD_LOGIC;
p_101_in : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
match : in STD_LOGIC;
ADDRESS_HIT_0 : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_46_out : in STD_LOGIC;
p_128_out : in STD_LOGIC;
p_108_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
st_mr_bmesg : in STD_LOGIC_VECTOR ( 7 downto 0 );
p_68_out : in STD_LOGIC;
p_88_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\s_axi_awid[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ : entity is "axi_crossbar_v2_1_14_si_transactor";
end \zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
signal \^d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \accum_push_5__0\ : STD_LOGIC;
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 58 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal \aid_match_00_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal \aid_match_0__0\ : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal \aid_match_10_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal \aid_match_1__0\ : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal \aid_match_20_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal \aid_match_2__0\ : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal \aid_match_30_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal \aid_match_3__0\ : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal \aid_match_40_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal \aid_match_4__0\ : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal \aid_match_50_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal \aid_match_5__0\ : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal \aid_match_60_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal \aid_match_6__0\ : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal \aid_match_70_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal \aid_match_7__0\ : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal f_mux4_return : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_15\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_16\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_17\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_18\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_19\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_20\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_21\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_22\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_23\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_24\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_25\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_26\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_27\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_28\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_29\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_30\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_31\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_32\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_33\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_34\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_35\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_36\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_37\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_38\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_39\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_40\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_41\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_42\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_43\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_44\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_45\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_46\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_47\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_48\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_49\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_50\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_51\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_52\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_53\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_54\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_55\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_56\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_57\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_58\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_15_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_17_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_20_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_21_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_22_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_23_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_28__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_29_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_31__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_32_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_35_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_7_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9_n_0\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal p_0_out_0 : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal resp_select : STD_LOGIC_VECTOR ( 2 to 2 );
signal \^s_axi_bvalid[0]\ : STD_LOGIC;
signal \thread_valid_0__2\ : STD_LOGIC;
signal \thread_valid_1__2\ : STD_LOGIC;
signal \thread_valid_2__2\ : STD_LOGIC;
signal \thread_valid_3__2\ : STD_LOGIC;
signal \thread_valid_4__2\ : STD_LOGIC;
signal \thread_valid_5__2\ : STD_LOGIC;
signal \thread_valid_6__2\ : STD_LOGIC;
signal \thread_valid_7__2\ : STD_LOGIC;
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1__0\ : label is "soft_lutpair189";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\ : label is "soft_lutpair181";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\ : label is "soft_lutpair181";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\ : label is "soft_lutpair175";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\ : label is "soft_lutpair175";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\ : label is "soft_lutpair174";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\ : label is "soft_lutpair174";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\ : label is "soft_lutpair184";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1\ : label is "soft_lutpair184";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\ : label is "soft_lutpair183";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\ : label is "soft_lutpair183";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\ : label is "soft_lutpair173";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\ : label is "soft_lutpair173";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2\ : label is "soft_lutpair176";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3\ : label is "soft_lutpair177";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4\ : label is "soft_lutpair178";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\ : label is "soft_lutpair188";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1\ : label is "soft_lutpair188";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\ : label is "soft_lutpair168";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\ : label is "soft_lutpair168";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\ : label is "soft_lutpair187";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1\ : label is "soft_lutpair187";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\ : label is "soft_lutpair166";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\ : label is "soft_lutpair166";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3\ : label is "soft_lutpair179";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4\ : label is "soft_lutpair172";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\ : label is "soft_lutpair185";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\ : label is "soft_lutpair185";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\ : label is "soft_lutpair171";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\ : label is "soft_lutpair171";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\ : label is "soft_lutpair182";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\ : label is "soft_lutpair182";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\ : label is "soft_lutpair170";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\ : label is "soft_lutpair170";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2\ : label is "soft_lutpair180";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3\ : label is "soft_lutpair163";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\ : label is "soft_lutpair186";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\ : label is "soft_lutpair186";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\ : label is "soft_lutpair169";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\ : label is "soft_lutpair169";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\ : label is "soft_lutpair164";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1\ : label is "soft_lutpair167";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1\ : label is "soft_lutpair165";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5\ : label is "soft_lutpair164";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9\ : label is "soft_lutpair163";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_10\ : label is "soft_lutpair179";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_13\ : label is "soft_lutpair178";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_16\ : label is "soft_lutpair177";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_19\ : label is "soft_lutpair176";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_20\ : label is "soft_lutpair165";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_28__0\ : label is "soft_lutpair167";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_30\ : label is "soft_lutpair180";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_33\ : label is "soft_lutpair172";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_35\ : label is "soft_lutpair189";
begin
D(2 downto 0) <= \^d\(2 downto 0);
SR(0) <= \^sr\(0);
\s_axi_bvalid[0]\ <= \^s_axi_bvalid[0]\;
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_00_carry_i_1__0_n_0\,
S(2) => \aid_match_00_carry_i_2__0_n_0\,
S(1) => \aid_match_00_carry_i_3__0_n_0\,
S(0) => \aid_match_00_carry_i_4__0_n_0\
);
\aid_match_00_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
O => \aid_match_00_carry_i_1__0_n_0\
);
\aid_match_00_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8),
O => \aid_match_00_carry_i_2__0_n_0\
);
\aid_match_00_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
O => \aid_match_00_carry_i_3__0_n_0\
);
\aid_match_00_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
O => \aid_match_00_carry_i_4__0_n_0\
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_10_carry_i_1__0_n_0\,
S(2) => \aid_match_10_carry_i_2__0_n_0\,
S(1) => \aid_match_10_carry_i_3__0_n_0\,
S(0) => \aid_match_10_carry_i_4__0_n_0\
);
\aid_match_10_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
I5 => \s_axi_awid[11]\(11),
O => \aid_match_10_carry_i_1__0_n_0\
);
\aid_match_10_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8),
I5 => \s_axi_awid[11]\(8),
O => \aid_match_10_carry_i_2__0_n_0\
);
\aid_match_10_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
I5 => \s_axi_awid[11]\(5),
O => \aid_match_10_carry_i_3__0_n_0\
);
\aid_match_10_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
I5 => \s_axi_awid[11]\(2),
O => \aid_match_10_carry_i_4__0_n_0\
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_20_carry_i_1__0_n_0\,
S(2) => \aid_match_20_carry_i_2__0_n_0\,
S(1) => \aid_match_20_carry_i_3__0_n_0\,
S(0) => \aid_match_20_carry_i_4__0_n_0\
);
\aid_match_20_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
O => \aid_match_20_carry_i_1__0_n_0\
);
\aid_match_20_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8),
O => \aid_match_20_carry_i_2__0_n_0\
);
\aid_match_20_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
O => \aid_match_20_carry_i_3__0_n_0\
);
\aid_match_20_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
O => \aid_match_20_carry_i_4__0_n_0\
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_30_carry_i_1__0_n_0\,
S(2) => \aid_match_30_carry_i_2__0_n_0\,
S(1) => \aid_match_30_carry_i_3__0_n_0\,
S(0) => \aid_match_30_carry_i_4__0_n_0\
);
\aid_match_30_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
O => \aid_match_30_carry_i_1__0_n_0\
);
\aid_match_30_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8),
O => \aid_match_30_carry_i_2__0_n_0\
);
\aid_match_30_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
O => \aid_match_30_carry_i_3__0_n_0\
);
\aid_match_30_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
O => \aid_match_30_carry_i_4__0_n_0\
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_40_carry_i_1__0_n_0\,
S(2) => \aid_match_40_carry_i_2__0_n_0\,
S(1) => \aid_match_40_carry_i_3__0_n_0\,
S(0) => \aid_match_40_carry_i_4__0_n_0\
);
\aid_match_40_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
O => \aid_match_40_carry_i_1__0_n_0\
);
\aid_match_40_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8),
O => \aid_match_40_carry_i_2__0_n_0\
);
\aid_match_40_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
O => \aid_match_40_carry_i_3__0_n_0\
);
\aid_match_40_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
O => \aid_match_40_carry_i_4__0_n_0\
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_50_carry_i_1__0_n_0\,
S(2) => \aid_match_50_carry_i_2__0_n_0\,
S(1) => \aid_match_50_carry_i_3__0_n_0\,
S(0) => \aid_match_50_carry_i_4__0_n_0\
);
\aid_match_50_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
O => \aid_match_50_carry_i_1__0_n_0\
);
\aid_match_50_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8),
O => \aid_match_50_carry_i_2__0_n_0\
);
\aid_match_50_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
O => \aid_match_50_carry_i_3__0_n_0\
);
\aid_match_50_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
O => \aid_match_50_carry_i_4__0_n_0\
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_60_carry_i_1__0_n_0\,
S(2) => \aid_match_60_carry_i_2__0_n_0\,
S(1) => \aid_match_60_carry_i_3__0_n_0\,
S(0) => \aid_match_60_carry_i_4__0_n_0\
);
\aid_match_60_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
O => \aid_match_60_carry_i_1__0_n_0\
);
\aid_match_60_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8),
O => \aid_match_60_carry_i_2__0_n_0\
);
\aid_match_60_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
O => \aid_match_60_carry_i_3__0_n_0\
);
\aid_match_60_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
O => \aid_match_60_carry_i_4__0_n_0\
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_70_carry_i_1__0_n_0\,
S(2) => \aid_match_70_carry_i_2__0_n_0\,
S(1) => \aid_match_70_carry_i_3__0_n_0\,
S(0) => \aid_match_70_carry_i_4__0_n_0\
);
\aid_match_70_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
O => \aid_match_70_carry_i_1__0_n_0\
);
\aid_match_70_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8),
O => \aid_match_70_carry_i_2__0_n_0\
);
\aid_match_70_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
O => \aid_match_70_carry_i_3__0_n_0\
);
\aid_match_70_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
O => \aid_match_70_carry_i_4__0_n_0\
);
\gen_multi_thread.accept_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\,
Q => \gen_multi_thread.accept_cnt_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.mux_resp_multi_thread_n_26\,
Q => \gen_multi_thread.accept_cnt_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.mux_resp_multi_thread_n_25\,
Q => \gen_multi_thread.accept_cnt_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.mux_resp_multi_thread_n_24\,
Q => \gen_multi_thread.accept_cnt_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp
port map (
ADDRESS_HIT_0 => ADDRESS_HIT_0,
E(0) => E(0),
Q(0) => \gen_multi_thread.accept_cnt_reg\(3),
SR(0) => \^sr\(0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_master_slots[0].w_issuing_cnt_reg[0]\(0) => \gen_master_slots[0].w_issuing_cnt_reg[0]\(0),
\gen_master_slots[2].w_issuing_cnt_reg[16]\(0) => \gen_master_slots[2].w_issuing_cnt_reg[16]\(0),
\gen_master_slots[3].w_issuing_cnt_reg[24]\(0) => \gen_master_slots[3].w_issuing_cnt_reg[24]\(0),
\gen_multi_thread.accept_cnt_reg[0]\ => \gen_no_arbiter.s_ready_i[0]_i_35_n_0\,
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]\(0) => \gen_no_arbiter.s_ready_i_reg[0]\(0),
\gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_no_arbiter.s_ready_i_reg[0]_0\,
m_valid_i => m_valid_i,
m_valid_i_reg => m_valid_i_reg,
m_valid_i_reg_0 => m_valid_i_reg_0,
match => match,
p_0_out => p_0_out_0,
p_101_in => p_101_in,
p_108_out => p_108_out,
p_128_out => p_128_out,
p_46_out => p_46_out,
p_48_in => p_48_in,
p_66_in => p_66_in,
p_68_out => p_68_out,
p_84_in => p_84_in,
p_88_out => p_88_out,
resp_select(0) => resp_select(2),
\s_axi_awaddr[30]\(2 downto 0) => \s_axi_awaddr[30]\(2 downto 0),
s_axi_bready(0) => s_axi_bready(0),
\s_axi_bvalid[0]\ => \^s_axi_bvalid[0]\,
s_ready_i_reg(4 downto 0) => Q(4 downto 0),
st_mr_bid(47 downto 0) => st_mr_bid(47 downto 0),
st_mr_bmesg(7 downto 0) => st_mr_bmesg(7 downto 0),
w_issuing_cnt(16 downto 0) => w_issuing_cnt(16 downto 0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(0),
I1 => cmd_push_0,
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(2),
I3 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(1),
I1 => cmd_push_0,
I2 => active_cnt(0),
I3 => active_cnt(3),
I4 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\,
Q => active_cnt(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\,
Q => active_cnt(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\,
Q => active_cnt(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\,
Q => active_cnt(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E222"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I1 => \thread_valid_0__2\,
I2 => aid_match_00,
I3 => \m_ready_d_reg[1]\,
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(0),
Q => active_target(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(1),
Q => active_target(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(2),
Q => active_target(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_1,
I1 => active_cnt(8),
I2 => active_cnt(10),
I3 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(9),
I1 => cmd_push_1,
I2 => active_cnt(8),
I3 => active_cnt(11),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(8),
I1 => cmd_push_1,
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\,
Q => active_cnt(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\,
Q => active_cnt(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\,
Q => active_cnt(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\,
Q => active_cnt(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8080808"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => aid_match_10,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(2),
Q => active_target(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(0),
Q => active_target(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(1),
Q => active_target(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(16),
I1 => cmd_push_2,
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_2,
I1 => active_cnt(16),
I2 => active_cnt(18),
I3 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(17),
I1 => cmd_push_2,
I2 => active_cnt(16),
I3 => active_cnt(19),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\,
Q => active_cnt(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\,
Q => active_cnt(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\,
Q => active_cnt(18),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\,
Q => active_cnt(19),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80008000800080"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => \thread_valid_2__2\,
I4 => aid_match_20,
I5 => \m_ready_d_reg[1]\,
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(3),
I2 => active_cnt(1),
I3 => active_cnt(0),
O => \thread_valid_0__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
O => \thread_valid_1__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
O => \thread_valid_2__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(0),
Q => active_target(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(1),
Q => active_target(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(2),
Q => active_target(18),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(24),
I1 => cmd_push_3,
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(26),
I3 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(25),
I1 => cmd_push_3,
I2 => active_cnt(24),
I3 => active_cnt(27),
I4 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\,
Q => active_cnt(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\,
Q => active_cnt(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\,
Q => active_cnt(26),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\,
Q => active_cnt(27),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I2 => \thread_valid_3__2\,
I3 => aid_match_30,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(0),
Q => active_target(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(1),
Q => active_target(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(2),
Q => active_target(26),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(32),
I1 => cmd_push_4,
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_4,
I1 => active_cnt(32),
I2 => active_cnt(34),
I3 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(33),
I1 => cmd_push_4,
I2 => active_cnt(32),
I3 => active_cnt(35),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\,
Q => active_cnt(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\,
Q => active_cnt(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\,
Q => active_cnt(34),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\,
Q => active_cnt(35),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\,
I1 => \thread_valid_3__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I3 => \thread_valid_4__2\,
I4 => aid_match_40,
I5 => \m_ready_d_reg[1]\,
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555557FFFFFFFF"
)
port map (
I0 => \thread_valid_0__2\,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
I5 => \thread_valid_2__2\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
O => \thread_valid_3__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(35),
I2 => active_cnt(33),
I3 => active_cnt(32),
O => \thread_valid_4__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(0),
Q => active_target(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(1),
Q => active_target(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(2),
Q => active_target(34),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(40),
I1 => cmd_push_5,
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_5,
I1 => active_cnt(40),
I2 => active_cnt(42),
I3 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(41),
I1 => cmd_push_5,
I2 => active_cnt(40),
I3 => active_cnt(43),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\,
Q => active_cnt(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\,
Q => active_cnt(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\,
Q => active_cnt(42),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\,
Q => active_cnt(43),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[42]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I2 => \thread_valid_5__2\,
I3 => aid_match_50,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(0),
Q => active_target(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(1),
Q => active_target(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(2),
Q => active_target(42),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(48),
I1 => cmd_push_6,
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_6,
I1 => active_cnt(48),
I2 => active_cnt(50),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(49),
I1 => cmd_push_6,
I2 => active_cnt(48),
I3 => active_cnt(51),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\,
Q => active_cnt(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\,
Q => active_cnt(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\,
Q => active_cnt(50),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\,
Q => active_cnt(51),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \thread_valid_5__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I3 => \thread_valid_6__2\,
I4 => aid_match_60,
I5 => \m_ready_d_reg[1]\,
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
O => \thread_valid_5__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(51),
I2 => active_cnt(49),
I3 => active_cnt(48),
O => \thread_valid_6__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(0),
Q => active_target(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(1),
Q => active_target(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(2),
Q => active_target(50),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(56),
I1 => cmd_push_7,
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_7,
I1 => active_cnt(56),
I2 => active_cnt(58),
I3 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(57),
I1 => cmd_push_7,
I2 => active_cnt(56),
I3 => active_cnt(59),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
O => \thread_valid_7__2\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\,
Q => active_cnt(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\,
Q => active_cnt(57),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\,
Q => active_cnt(58),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\,
Q => active_cnt(59),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_awaddr[30]\(2),
I1 => \s_axi_awaddr[30]\(0),
O => \^d\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_awaddr[30]\(2),
I1 => \s_axi_awaddr[30]\(1),
O => \^d\(1)
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF404040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I3 => \aid_match_7__0\,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF55555557"
)
port map (
I0 => \thread_valid_3__2\,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
I5 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\,
O => \accum_push_5__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => \thread_valid_6__2\,
I5 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0\,
I4 => \aid_match_6__0\,
I5 => \aid_match_7__0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
I4 => aid_match_70,
O => \aid_match_7__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_00,
I1 => \thread_valid_0__2\,
I2 => aid_match_10,
I3 => \thread_valid_1__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_20,
I1 => \thread_valid_2__2\,
I2 => aid_match_30,
I3 => \thread_valid_3__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_40,
I1 => \thread_valid_4__2\,
I2 => aid_match_50,
I3 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(48),
I1 => active_cnt(49),
I2 => active_cnt(51),
I3 => active_cnt(50),
I4 => aid_match_60,
O => \aid_match_6__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(0),
Q => active_target(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(1),
Q => active_target(57),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(2),
Q => active_target(58),
R => \^sr\(0)
);
\gen_multi_thread.mux_resp_multi_thread\: entity work.\zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc__parameterized0\
port map (
CO(0) => p_14_out,
D(2) => \gen_multi_thread.mux_resp_multi_thread_n_24\,
D(1) => \gen_multi_thread.mux_resp_multi_thread_n_25\,
D(0) => \gen_multi_thread.mux_resp_multi_thread_n_26\,
E(0) => \gen_multi_thread.mux_resp_multi_thread_n_15\,
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_27\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_28\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_29\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_30\,
cmd_push_0 => cmd_push_0,
cmd_push_1 => cmd_push_1,
cmd_push_2 => cmd_push_2,
cmd_push_3 => cmd_push_3,
cmd_push_4 => cmd_push_4,
cmd_push_5 => cmd_push_5,
cmd_push_6 => cmd_push_6,
cmd_push_7 => cmd_push_7,
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_23\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3) => \gen_multi_thread.mux_resp_multi_thread_n_55\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2) => \gen_multi_thread.mux_resp_multi_thread_n_56\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1) => \gen_multi_thread.mux_resp_multi_thread_n_57\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_58\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_22\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_51\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_52\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_53\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_54\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_21\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_47\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_48\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_49\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_50\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_16\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_43\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_44\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_45\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_46\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0) => p_8_out,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_17\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_39\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_40\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_41\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_42\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_20\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_35\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_36\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_37\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_38\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_19\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_31\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_32\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_33\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_34\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_18\,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0) => p_0_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11 downto 0),
\m_ready_d_reg[1]\ => \m_ready_d_reg[1]\,
m_valid_i_reg => \^s_axi_bvalid[0]\,
p_0_out => p_0_out_0,
resp_select(0) => resp_select(2),
\s_axi_bid[0]\ => \s_axi_bid[0]\,
\s_axi_bid[10]\ => \s_axi_bid[10]\,
\s_axi_bid[11]\ => \s_axi_bid[11]\,
\s_axi_bid[1]\ => \s_axi_bid[1]\,
\s_axi_bid[2]\ => \s_axi_bid[2]\,
\s_axi_bid[3]\ => \s_axi_bid[3]\,
\s_axi_bid[4]\ => \s_axi_bid[4]\,
\s_axi_bid[5]\ => \s_axi_bid[5]\,
\s_axi_bid[6]\ => \s_axi_bid[6]\,
\s_axi_bid[7]\ => \s_axi_bid[7]\,
\s_axi_bid[8]\ => \s_axi_bid[8]\,
\s_axi_bid[9]\ => \s_axi_bid[9]\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
st_mr_bid(11 downto 0) => st_mr_bid(59 downto 48),
\thread_valid_0__2\ => \thread_valid_0__2\,
\thread_valid_1__2\ => \thread_valid_1__2\,
\thread_valid_2__2\ => \thread_valid_2__2\,
\thread_valid_3__2\ => \thread_valid_3__2\,
\thread_valid_4__2\ => \thread_valid_4__2\,
\thread_valid_5__2\ => \thread_valid_5__2\,
\thread_valid_6__2\ => \thread_valid_6__2\,
\thread_valid_7__2\ => \thread_valid_7__2\
);
\gen_no_arbiter.m_target_hot_i[4]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => match,
O => \^d\(2)
);
\gen_no_arbiter.s_ready_i[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(24),
I1 => active_cnt(25),
I2 => active_cnt(27),
I3 => active_cnt(26),
I4 => aid_match_30,
O => \aid_match_3__0\
);
\gen_no_arbiter.s_ready_i[0]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(17),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(16),
O => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(18),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(16),
I1 => active_cnt(17),
I2 => active_cnt(19),
I3 => active_cnt(18),
I4 => aid_match_20,
O => \aid_match_2__0\
);
\gen_no_arbiter.s_ready_i[0]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(9),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(8),
O => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(10),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(8),
I1 => active_cnt(9),
I2 => active_cnt(11),
I3 => active_cnt(10),
I4 => aid_match_10,
O => \aid_match_1__0\
);
\gen_no_arbiter.s_ready_i[0]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(1),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(2),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(0),
I1 => active_cnt(1),
I2 => active_cnt(3),
I3 => active_cnt(2),
I4 => aid_match_00,
O => \aid_match_0__0\
);
\gen_no_arbiter.s_ready_i[0]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(49),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(48),
O => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(50),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(57),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(56),
O => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(58),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_28__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(41),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(40),
O => \gen_no_arbiter.s_ready_i[0]_i_28__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_29\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(42),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_29_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\,
I2 => \aid_match_3__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\,
I5 => \aid_match_2__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_30\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(40),
I1 => active_cnt(41),
I2 => active_cnt(43),
I3 => active_cnt(42),
I4 => aid_match_50,
O => \aid_match_5__0\
);
\gen_no_arbiter.s_ready_i[0]_i_31__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(33),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(32),
O => \gen_no_arbiter.s_ready_i[0]_i_31__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_32\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(34),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_32_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_33\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(32),
I1 => active_cnt(33),
I2 => active_cnt(35),
I3 => active_cnt(34),
I4 => aid_match_40,
O => \aid_match_4__0\
);
\gen_no_arbiter.s_ready_i[0]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
I1 => \gen_multi_thread.accept_cnt_reg\(2),
I2 => \gen_multi_thread.accept_cnt_reg\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_35_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\,
I2 => \aid_match_1__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\,
I5 => \aid_match_0__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\,
I2 => \aid_match_6__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\,
I5 => \aid_match_7__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_28__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_29_n_0\,
I2 => \aid_match_5__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_31__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_32_n_0\,
I5 => \aid_match_4__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(25),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(26),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_27\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_28\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_29\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_30\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_47\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_48\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_49\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_50\
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_51\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_52\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_53\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_54\
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_55\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_56\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_57\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_58\
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_31\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_32\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_33\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_34\
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_35\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_36\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_37\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_38\
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_39\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_40\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_41\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_42\
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_43\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_44\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_45\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_46\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
port (
ss_wr_awready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
\write_cs0__0\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
match : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_22_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo : entity is "axi_data_fifo_v2_1_12_axic_reg_srl_fifo";
end zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
signal \/FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
signal \/FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[2]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[3]\ : signal is "yes";
signal areset_d1 : STD_LOGIC;
signal fifoaddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[0].srl_nx1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[1].srl_nx1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[2].srl_nx1_n_1\ : STD_LOGIC;
signal load_s1 : STD_LOGIC;
signal \m_aready0__3\ : STD_LOGIC;
signal \m_aready__1\ : STD_LOGIC;
signal m_avalid : STD_LOGIC;
signal m_select_enc : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \m_valid_i__0\ : STD_LOGIC;
signal m_valid_i_n_0 : STD_LOGIC;
signal p_0_in5_out : STD_LOGIC;
signal p_0_in8_in : STD_LOGIC;
attribute RTL_KEEP of p_0_in8_in : signal is "yes";
signal p_9_in : STD_LOGIC;
attribute RTL_KEEP of p_9_in : signal is "yes";
signal push : STD_LOGIC;
signal \s_ready_i1__4\ : STD_LOGIC;
signal \s_ready_i_i_1__9_n_0\ : STD_LOGIC;
signal \^ss_wr_awready\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_onehot_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[3]\ : label is "yes";
attribute syn_keep : string;
attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[2]\ : label is "1";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0\ : label is "soft_lutpair191";
attribute SOFT_HLUTNM of \m_axi_wvalid[1]_INST_0\ : label is "soft_lutpair191";
attribute SOFT_HLUTNM of \m_axi_wvalid[2]_INST_0\ : label is "soft_lutpair192";
attribute SOFT_HLUTNM of \m_axi_wvalid[3]_INST_0\ : label is "soft_lutpair192";
begin
ss_wr_awready <= \^ss_wr_awready\;
\/FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20202F20"
)
port map (
I0 => s_axi_awvalid(0),
I1 => m_ready_d(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[1]_i_1_n_0\
);
\/FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B0B0B0BF"
)
port map (
I0 => m_ready_d(0),
I1 => s_axi_awvalid(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[2]_i_1_n_0\
);
\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"008A0000"
)
port map (
I0 => \m_aready__1\,
I1 => m_ready_d(0),
I2 => s_axi_awvalid(0),
I3 => p_9_in,
I4 => p_0_in8_in,
O => \FSM_onehot_state[0]_i_1_n_0\
);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF488F488F488"
)
port map (
I0 => \m_aready__1\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => \m_valid_i__0\
);
\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00007500"
)
port map (
I0 => \m_aready__1\,
I1 => m_ready_d(0),
I2 => s_axi_awvalid(0),
I3 => p_0_in8_in,
I4 => p_9_in,
O => \FSM_onehot_state[3]_i_2_n_0\
);
\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \FSM_onehot_state[0]_i_1_n_0\,
Q => p_9_in,
S => areset_d1
);
\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \/FSM_onehot_state[1]_i_1_n_0\,
Q => p_0_in8_in,
R => areset_d1
);
\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \/FSM_onehot_state[2]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[2]\,
R => areset_d1
);
\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \FSM_onehot_state[3]_i_2_n_0\,
Q => \FSM_onehot_state_reg_n_0_[3]\,
R => areset_d1
);
areset_d1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => SR(0),
Q => areset_d1,
R => '0'
);
\gen_axi.write_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000800000"
)
port map (
I0 => s_axi_wlast(0),
I1 => m_avalid,
I2 => s_axi_wvalid(0),
I3 => m_select_enc(0),
I4 => m_select_enc(2),
I5 => m_select_enc(1),
O => \write_cs0__0\
);
\gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => push,
I3 => fifoaddr(0),
O => \gen_rep[0].fifoaddr[0]_i_1_n_0\
);
\gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FF77008"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(0),
I3 => push,
I4 => fifoaddr(1),
O => \gen_rep[0].fifoaddr[1]_i_1_n_0\
);
\gen_rep[0].fifoaddr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8FFFFFF770000008"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(0),
I3 => fifoaddr(1),
I4 => push,
I5 => fifoaddr(2),
O => \gen_rep[0].fifoaddr[2]_i_1_n_0\
);
\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[0]_i_1_n_0\,
Q => fifoaddr(0),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[1]_i_1_n_0\,
Q => fifoaddr(1),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[2]_i_1_n_0\,
Q => fifoaddr(2),
S => SR(0)
);
\gen_srls[0].gen_rep[0].srl_nx1\: entity work.\zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\
port map (
D(0) => D(0),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
load_s1 => load_s1,
m_select_enc(0) => m_select_enc(0),
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
push => push,
\s_axi_awaddr[30]\(1) => \s_axi_awaddr[30]\(2),
\s_axi_awaddr[30]\(0) => \s_axi_awaddr[30]\(0),
\storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_0\
);
\gen_srls[0].gen_rep[1].srl_nx1\: entity work.\zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\
port map (
D(0) => D(1),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
load_s1 => load_s1,
m_select_enc(0) => m_select_enc(1),
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
push => push,
\s_axi_awaddr[30]\(1 downto 0) => \s_axi_awaddr[30]\(2 downto 1),
\storage_data1_reg[1]\ => \gen_srls[0].gen_rep[1].srl_nx1_n_0\
);
\gen_srls[0].gen_rep[2].srl_nx1\: entity work.\zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\
port map (
D(0) => D(2),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
load_s1 => load_s1,
\m_aready0__3\ => \m_aready0__3\,
\m_aready__1\ => \m_aready__1\,
m_avalid => m_avalid,
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_ready_d(0) => m_ready_d(0),
m_select_enc(2 downto 0) => m_select_enc(2 downto 0),
match => match,
out0(1) => p_0_in8_in,
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
p_22_in => p_22_in,
push => push,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => \^ss_wr_awready\,
\storage_data1_reg[2]\ => \gen_srls[0].gen_rep[2].srl_nx1_n_1\
);
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000008"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(0)
);
\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(1)
);
\m_axi_wvalid[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(2)
);
\m_axi_wvalid[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00008000"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(3)
);
m_valid_i: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF400F400F400"
)
port map (
I0 => \m_aready__1\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => m_valid_i_n_0
);
m_valid_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(1),
I3 => fifoaddr(0),
I4 => fifoaddr(2),
I5 => push,
O => p_0_in5_out
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => m_valid_i_n_0,
Q => m_avalid,
R => areset_d1
);
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => m_avalid,
I1 => \m_aready0__3\,
O => s_axi_wready(0)
);
\s_ready_i_i_1__9\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0FFF0F8"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => areset_d1,
I3 => \s_ready_i1__4\,
I4 => \^ss_wr_awready\,
O => \s_ready_i_i_1__9_n_0\
);
\s_ready_i_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000700000000000"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(2),
I3 => fifoaddr(1),
I4 => fifoaddr(0),
I5 => push,
O => \s_ready_i1__4\
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__9_n_0\,
Q => \^ss_wr_awready\,
R => SR(0)
);
\storage_data1[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0FCA0A0A0ECA0A0"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[3]\,
I1 => p_9_in,
I2 => \m_aready__1\,
I3 => m_ready_d(0),
I4 => s_axi_awvalid(0),
I5 => p_0_in8_in,
O => load_s1
);
\storage_data1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[0].srl_nx1_n_0\,
Q => m_select_enc(0),
R => '0'
);
\storage_data1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[1].srl_nx1_n_0\,
Q => m_select_enc(1),
R => '0'
);
\storage_data1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[2].srl_nx1_n_1\,
Q => m_select_enc(2),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice is
port (
p_128_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_122_out : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_0__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[2]\ : out STD_LOGIC;
\chosen_reg[2]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_93_in : in STD_LOGIC;
p_102_out : in STD_LOGIC;
p_108_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice is
begin
b_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\
port map (
D(13 downto 0) => D(13 downto 0),
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\chosen_reg[2]\ => \chosen_reg[2]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_128_out,
p_108_out => p_108_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\chosen_reg[0]\(0) => \chosen_reg[0]\(0),
\chosen_reg[0]_0\(0) => \chosen_reg[0]_0\(0),
\chosen_reg[2]\ => \chosen_reg[2]\,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0) => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => \m_axi_rready[0]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_122_out,
p_102_out => p_102_out,
p_1_in => p_1_in,
p_93_in => p_93_in,
\r_cmd_pop_0__1\ => \r_cmd_pop_0__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 is
port (
p_108_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_102_out : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_1__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_75_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\m_axi_bid[23]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 is
begin
b_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\
port map (
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
\m_axi_bid[23]\(13 downto 0) => \m_axi_bid[23]\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_108_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\
port map (
ADDRESS_HIT_0 => ADDRESS_HIT_0,
D(0) => D(0),
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\chosen_reg[1]\(0) => \chosen_reg[1]\(0),
\chosen_reg[1]_0\(0) => \chosen_reg[1]_0\(0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(3 downto 0) => \gen_master_slots[1].r_issuing_cnt_reg[11]\(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[1]\ => \m_axi_rready[1]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_102_out,
p_1_in => p_1_in,
p_75_in => p_75_in,
\r_cmd_pop_1__1\ => \r_cmd_pop_1__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 is
port (
p_88_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_82_out : out STD_LOGIC;
\m_axi_rready[2]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_2__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].r_issuing_cnt_reg[19]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_57_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\gen_master_slots[3].r_issuing_cnt_reg[24]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_axi_bid[35]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 is
begin
b_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\
port map (
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
\m_axi_bid[35]\(13 downto 0) => \m_axi_bid[35]\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_88_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\
port map (
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\chosen_reg[2]\(0) => \chosen_reg[2]\(0),
\chosen_reg[2]_0\(0) => \chosen_reg[2]_0\(0),
\gen_master_slots[2].r_issuing_cnt_reg[19]\(3 downto 0) => \gen_master_slots[2].r_issuing_cnt_reg[19]\(3 downto 0),
\gen_master_slots[3].r_issuing_cnt_reg[24]\ => \gen_master_slots[3].r_issuing_cnt_reg[24]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[2]\ => \m_axi_rready[2]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_82_out,
p_1_in => p_1_in,
p_57_in => p_57_in,
\r_cmd_pop_2__1\ => \r_cmd_pop_2__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_3 is
port (
p_68_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
p_62_out : out STD_LOGIC;
\m_axi_rready[3]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_3__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[4]\ : out STD_LOGIC;
\chosen_reg[4]_0\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].r_issuing_cnt_reg[27]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_39_in : in STD_LOGIC;
p_82_out : in STD_LOGIC;
p_88_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_3 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_3;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_3 is
signal \^p_1_in\ : STD_LOGIC;
begin
p_1_in <= \^p_1_in\;
b_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\
port map (
D(13 downto 0) => D(13 downto 0),
Q(0) => Q(0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\aresetn_d_reg[1]_1\ => \aresetn_d_reg[1]_1\,
\chosen_reg[4]\ => \chosen_reg[4]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_68_out,
p_1_in => \^p_1_in\,
p_88_out => p_88_out,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]_0\,
\chosen_reg[3]\(0) => \chosen_reg[3]\(0),
\chosen_reg[3]_0\(0) => \chosen_reg[3]_0\(0),
\chosen_reg[4]\ => \chosen_reg[4]\,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(3 downto 0) => \gen_master_slots[3].r_issuing_cnt_reg[27]\(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[3]\ => \m_axi_rready[3]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_62_out,
p_1_in => \^p_1_in\,
p_39_in => p_39_in,
p_82_out => p_82_out,
\r_cmd_pop_3__1\ => \r_cmd_pop_3__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_4 is
port (
p_46_out : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
mi_bready_4 : out STD_LOGIC;
p_40_out : out STD_LOGIC;
mi_rready_4 : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
\r_cmd_pop_4__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_29_in : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_23_in : in STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_25_in : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_4 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_4;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_4 is
signal \^m_valid_i_reg\ : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
b_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
D(11 downto 0) => D(11 downto 0),
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[0]\ => \aresetn_d_reg[0]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(11 downto 0),
\m_payload_i_reg[2]_0\ => p_46_out,
m_valid_i_reg_0 => \^m_valid_i_reg\,
mi_bready_4 => mi_bready_4,
p_1_in => p_1_in,
p_29_in => p_29_in,
s_axi_bready(0) => s_axi_bready(0),
s_ready_i_reg_0 => s_ready_i_reg
);
r_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \^m_valid_i_reg\,
\chosen_reg[4]\(0) => \chosen_reg[4]\(0),
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => \gen_axi.s_axi_rid_i_reg[11]\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0),
m_valid_i_reg_0 => p_40_out,
p_1_in => p_1_in,
p_23_in => p_23_in,
p_25_in => p_25_in,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
s_axi_rready(0) => s_axi_rready(0),
\skid_buffer_reg[34]_0\ => mi_rready_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_wdata_router is
port (
ss_wr_awready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
\write_cs0__0\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
match : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_22_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_wdata_router : entity is "axi_crossbar_v2_1_14_wdata_router";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_wdata_router;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_wdata_router is
begin
wrouter_aw_fifo: entity work.zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo
port map (
D(2 downto 0) => D(2 downto 0),
SR(0) => SR(0),
aclk => aclk,
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
m_ready_d(0) => m_ready_d(0),
match => match,
p_22_in => p_22_in,
\s_axi_awaddr[30]\(2 downto 0) => \s_axi_awaddr[30]\(2 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
\write_cs0__0\ => \write_cs0__0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_crossbar is
port (
M_AXI_RREADY : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 68 downto 0 );
\m_axi_arqos[15]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
S_AXI_ARREADY : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_rid[0]\ : out STD_LOGIC;
\s_axi_rid[1]\ : out STD_LOGIC;
\s_axi_rid[2]\ : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC;
\s_axi_rid[4]\ : out STD_LOGIC;
\s_axi_rid[5]\ : out STD_LOGIC;
\s_axi_rid[6]\ : out STD_LOGIC;
\s_axi_rid[7]\ : out STD_LOGIC;
\s_axi_rid[8]\ : out STD_LOGIC;
\s_axi_rid[9]\ : out STD_LOGIC;
\s_axi_rid[10]\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_bid[0]\ : out STD_LOGIC;
\s_axi_bid[1]\ : out STD_LOGIC;
\s_axi_bid[2]\ : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC;
\s_axi_bid[4]\ : out STD_LOGIC;
\s_axi_bid[5]\ : out STD_LOGIC;
\s_axi_bid[6]\ : out STD_LOGIC;
\s_axi_bid[7]\ : out STD_LOGIC;
\s_axi_bid[8]\ : out STD_LOGIC;
\s_axi_bid[9]\ : out STD_LOGIC;
\s_axi_bid[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
\s_axi_awready[0]\ : out STD_LOGIC;
\s_axi_bvalid[0]\ : out STD_LOGIC;
\s_axi_rvalid[0]\ : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 68 downto 0 );
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
aresetn : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_crossbar : entity is "axi_crossbar_v2_1_14_crossbar";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_crossbar;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_crossbar is
signal \^q\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 4 to 4 );
signal aa_mi_arvalid : STD_LOGIC;
signal aa_mi_awtarget_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal aa_sa_awvalid : STD_LOGIC;
signal addr_arbiter_ar_n_79 : STD_LOGIC;
signal addr_arbiter_ar_n_80 : STD_LOGIC;
signal addr_arbiter_ar_n_81 : STD_LOGIC;
signal addr_arbiter_ar_n_82 : STD_LOGIC;
signal addr_arbiter_ar_n_83 : STD_LOGIC;
signal addr_arbiter_ar_n_84 : STD_LOGIC;
signal addr_arbiter_ar_n_85 : STD_LOGIC;
signal addr_arbiter_ar_n_86 : STD_LOGIC;
signal addr_arbiter_ar_n_87 : STD_LOGIC;
signal addr_arbiter_ar_n_88 : STD_LOGIC;
signal addr_arbiter_ar_n_89 : STD_LOGIC;
signal addr_arbiter_ar_n_90 : STD_LOGIC;
signal addr_arbiter_ar_n_99 : STD_LOGIC;
signal addr_arbiter_aw_n_23 : STD_LOGIC;
signal addr_arbiter_aw_n_25 : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_4\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_54\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_55\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_6\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_53\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_53\ : STD_LOGIC;
signal \gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_55\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_56\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_57\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_7\ : STD_LOGIC;
signal \gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[4].reg_slice_mi_n_1\ : STD_LOGIC;
signal \gen_master_slots[4].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst/chosen\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gen_multi_thread.arbiter_resp_inst/chosen_9\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\ : STD_LOGIC;
signal \^m_axi_arqos[15]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d_12 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_valid_i : STD_LOGIC;
signal m_valid_i_10 : STD_LOGIC;
signal match : STD_LOGIC;
signal match_3 : STD_LOGIC;
signal mi_arready_4 : STD_LOGIC;
signal mi_awready_4 : STD_LOGIC;
signal \mi_awready_mux__3\ : STD_LOGIC;
signal mi_bready_4 : STD_LOGIC;
signal mi_rready_4 : STD_LOGIC;
signal p_101_in : STD_LOGIC;
signal p_102_out : STD_LOGIC;
signal p_104_out : STD_LOGIC;
signal p_108_out : STD_LOGIC;
signal p_122_out : STD_LOGIC;
signal p_124_out : STD_LOGIC;
signal p_128_out : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_22_in : STD_LOGIC;
signal p_23_in : STD_LOGIC;
signal p_25_in : STD_LOGIC;
signal p_28_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_29_in : STD_LOGIC;
signal p_32_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_39_in : STD_LOGIC;
signal p_40_out : STD_LOGIC;
signal p_42_out : STD_LOGIC;
signal p_46_out : STD_LOGIC;
signal p_48_in : STD_LOGIC;
signal p_57_in : STD_LOGIC;
signal p_62_out : STD_LOGIC;
signal p_64_out : STD_LOGIC;
signal p_66_in : STD_LOGIC;
signal p_68_out : STD_LOGIC;
signal p_75_in : STD_LOGIC;
signal p_82_out : STD_LOGIC;
signal p_84_in : STD_LOGIC;
signal p_84_out : STD_LOGIC;
signal p_88_out : STD_LOGIC;
signal p_93_in : STD_LOGIC;
signal \r_cmd_pop_0__1\ : STD_LOGIC;
signal \r_cmd_pop_1__1\ : STD_LOGIC;
signal \r_cmd_pop_2__1\ : STD_LOGIC;
signal \r_cmd_pop_3__1\ : STD_LOGIC;
signal \r_cmd_pop_4__1\ : STD_LOGIC;
signal r_issuing_cnt : STD_LOGIC_VECTOR ( 32 downto 0 );
signal \r_pipe/p_1_in\ : STD_LOGIC;
signal \r_pipe/p_1_in_5\ : STD_LOGIC;
signal \r_pipe/p_1_in_6\ : STD_LOGIC;
signal \r_pipe/p_1_in_7\ : STD_LOGIC;
signal \r_pipe/p_1_in_8\ : STD_LOGIC;
signal \read_cs__0\ : STD_LOGIC;
signal reset : STD_LOGIC;
signal \^s_axi_awready[0]\ : STD_LOGIC;
signal s_axi_rlast_i0 : STD_LOGIC;
signal s_axi_rvalid_i : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal s_ready_i0_11 : STD_LOGIC;
signal \s_ready_i0__1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \sa_wm_awready_mux__3\ : STD_LOGIC;
signal splitter_aw_mi_n_0 : STD_LOGIC;
signal splitter_aw_mi_n_1 : STD_LOGIC;
signal splitter_aw_mi_n_10 : STD_LOGIC;
signal splitter_aw_mi_n_11 : STD_LOGIC;
signal splitter_aw_mi_n_12 : STD_LOGIC;
signal splitter_aw_mi_n_2 : STD_LOGIC;
signal splitter_aw_mi_n_3 : STD_LOGIC;
signal splitter_aw_mi_n_4 : STD_LOGIC;
signal splitter_aw_mi_n_5 : STD_LOGIC;
signal splitter_aw_mi_n_6 : STD_LOGIC;
signal splitter_aw_mi_n_7 : STD_LOGIC;
signal splitter_aw_mi_n_8 : STD_LOGIC;
signal splitter_aw_mi_n_9 : STD_LOGIC;
signal ss_aa_awready : STD_LOGIC;
signal ss_wr_awready : STD_LOGIC;
signal ss_wr_awvalid : STD_LOGIC;
signal st_aa_awtarget_enc : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_mr_bid : STD_LOGIC_VECTOR ( 59 downto 0 );
signal st_mr_bmesg : STD_LOGIC_VECTOR ( 10 downto 0 );
signal st_mr_rid : STD_LOGIC_VECTOR ( 59 downto 0 );
signal st_mr_rmesg : STD_LOGIC_VECTOR ( 139 downto 0 );
signal w_issuing_cnt : STD_LOGIC_VECTOR ( 32 downto 0 );
signal write_cs01_out : STD_LOGIC;
signal \write_cs0__0\ : STD_LOGIC;
begin
Q(68 downto 0) <= \^q\(68 downto 0);
S_AXI_ARREADY(0) <= \^s_axi_arready\(0);
\m_axi_arqos[15]\(68 downto 0) <= \^m_axi_arqos[15]\(68 downto 0);
\s_axi_awready[0]\ <= \^s_axi_awready[0]\;
addr_arbiter_ar: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
D(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\,
D(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
E(0) => s_ready_i0,
Q(0) => aa_mi_artarget_hot(4),
SR(0) => reset,
S_AXI_ARREADY(0) => \^s_axi_arready\(0),
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
\gen_axi.s_axi_rid_i_reg[11]\(0) => s_axi_rvalid_i,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(2) => addr_arbiter_ar_n_79,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(1) => addr_arbiter_ar_n_80,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(0) => addr_arbiter_ar_n_81,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(2) => addr_arbiter_ar_n_82,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(1) => addr_arbiter_ar_n_83,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(0) => addr_arbiter_ar_n_84,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(2) => addr_arbiter_ar_n_88,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(1) => addr_arbiter_ar_n_89,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(0) => addr_arbiter_ar_n_90,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(2) => addr_arbiter_ar_n_85,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(1) => addr_arbiter_ar_n_86,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(0) => addr_arbiter_ar_n_87,
\gen_master_slots[4].r_issuing_cnt_reg[32]\ => addr_arbiter_ar_n_99,
\m_axi_arqos[15]\(68 downto 0) => \^m_axi_arqos[15]\(68 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_valid_i => m_valid_i,
match => match,
mi_arready_4 => mi_arready_4,
p_23_in => p_23_in,
p_39_in => p_39_in,
p_57_in => p_57_in,
p_75_in => p_75_in,
p_93_in => p_93_in,
\r_cmd_pop_0__1\ => \r_cmd_pop_0__1\,
\r_cmd_pop_1__1\ => \r_cmd_pop_1__1\,
\r_cmd_pop_2__1\ => \r_cmd_pop_2__1\,
\r_cmd_pop_3__1\ => \r_cmd_pop_3__1\,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
r_issuing_cnt(16) => r_issuing_cnt(32),
r_issuing_cnt(15 downto 12) => r_issuing_cnt(27 downto 24),
r_issuing_cnt(11 downto 8) => r_issuing_cnt(19 downto 16),
r_issuing_cnt(7 downto 4) => r_issuing_cnt(11 downto 8),
r_issuing_cnt(3 downto 0) => r_issuing_cnt(3 downto 0),
\read_cs__0\ => \read_cs__0\,
\s_axi_araddr[24]\(0) => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49\,
\s_axi_arqos[3]\(68 downto 0) => \s_axi_arqos[3]\(68 downto 0),
s_axi_rlast_i0 => s_axi_rlast_i0
);
addr_arbiter_aw: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_4\,
D(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\,
D(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\,
E(0) => s_ready_i0_11,
Q(4 downto 0) => aa_mi_awtarget_hot(4 downto 0),
SR(0) => reset,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
\chosen_reg[4]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(4),
\gen_master_slots[4].w_issuing_cnt_reg[32]\ => addr_arbiter_aw_n_25,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_aw_n_23,
\m_axi_awqos[15]\(68 downto 0) => \^q\(68 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_ready_d(1 downto 0) => m_ready_d_12(1 downto 0),
m_ready_d_0(0) => m_ready_d(0),
m_valid_i => m_valid_i_10,
match => match_3,
mi_awready_4 => mi_awready_4,
\mi_awready_mux__3\ => \mi_awready_mux__3\,
p_101_in => p_101_in,
p_46_out => p_46_out,
p_48_in => p_48_in,
p_66_in => p_66_in,
p_84_in => p_84_in,
\s_axi_awaddr[24]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\,
\s_axi_awqos[3]\(68 downto 0) => D(68 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
\s_ready_i0__1\(0) => \s_ready_i0__1\(0),
\sa_wm_awready_mux__3\ => \sa_wm_awready_mux__3\,
ss_aa_awready => ss_aa_awready,
w_issuing_cnt(0) => w_issuing_cnt(32),
write_cs01_out => write_cs01_out
);
aresetn_d_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => aresetn_d,
R => '0'
);
\gen_decerr_slave.decerr_slave_inst\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_decerr_slave
port map (
E(0) => s_axi_rvalid_i,
Q(0) => aa_mi_awtarget_hot(4),
SR(0) => reset,
aa_mi_arvalid => aa_mi_arvalid,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_no_arbiter.m_mesg_i_reg[11]\(11 downto 0) => \^q\(11 downto 0),
\gen_no_arbiter.m_mesg_i_reg[51]\(19 downto 12) => \^m_axi_arqos[15]\(51 downto 44),
\gen_no_arbiter.m_mesg_i_reg[51]\(11 downto 0) => \^m_axi_arqos[15]\(11 downto 0),
\gen_no_arbiter.m_target_hot_i_reg[4]\(0) => aa_mi_artarget_hot(4),
\m_payload_i_reg[13]\(11 downto 0) => p_32_in(11 downto 0),
m_ready_d(0) => m_ready_d_12(1),
\m_ready_d_reg[1]\ => splitter_aw_mi_n_3,
mi_arready_4 => mi_arready_4,
mi_awready_4 => mi_awready_4,
mi_bready_4 => mi_bready_4,
mi_rready_4 => mi_rready_4,
p_22_in => p_22_in,
p_23_in => p_23_in,
p_25_in => p_25_in,
p_29_in => p_29_in,
\read_cs__0\ => \read_cs__0\,
s_axi_rlast_i0 => s_axi_rlast_i0,
\skid_buffer_reg[46]\(11 downto 0) => p_28_in(11 downto 0),
write_cs01_out => write_cs01_out,
\write_cs0__0\ => \write_cs0__0\
);
\gen_master_slots[0].r_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(0),
O => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].r_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\,
Q => r_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_81,
Q => r_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_80,
Q => r_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_79,
Q => r_issuing_cnt(3),
R => reset
);
\gen_master_slots[0].reg_slice_mi\: entity work.zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice
port map (
D(13 downto 2) => m_axi_bid(11 downto 0),
D(1 downto 0) => m_axi_bresp(1 downto 0),
E(0) => \gen_master_slots[0].reg_slice_mi_n_4\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[0]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(0),
\chosen_reg[0]_0\(0) => \r_pipe/p_1_in_8\,
\chosen_reg[2]\ => \gen_master_slots[0].reg_slice_mi_n_54\,
\chosen_reg[2]_0\ => \gen_master_slots[0].reg_slice_mi_n_55\,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0) => r_issuing_cnt(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_124_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(1 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(34 downto 3),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(1 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_6\,
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => M_AXI_RREADY(0),
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
p_102_out => p_102_out,
p_108_out => p_108_out,
p_122_out => p_122_out,
p_128_out => p_128_out,
p_1_in => p_1_in,
p_93_in => p_93_in,
\r_cmd_pop_0__1\ => \r_cmd_pop_0__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[0].w_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(0),
O => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].w_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\,
Q => w_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => splitter_aw_mi_n_12,
Q => w_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => splitter_aw_mi_n_11,
Q => w_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => splitter_aw_mi_n_10,
Q => w_issuing_cnt(3),
R => reset
);
\gen_master_slots[1].r_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(8),
O => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].r_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_83,
Q => r_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_82,
Q => r_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\,
Q => r_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_84,
Q => r_issuing_cnt(9),
R => reset
);
\gen_master_slots[1].reg_slice_mi\: entity work.zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
E(0) => \gen_master_slots[1].reg_slice_mi_n_4\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(1),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[1]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(1),
\chosen_reg[1]_0\(0) => \r_pipe/p_1_in_7\,
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_6\,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(3 downto 0) => r_issuing_cnt(11 downto 8),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(23 downto 12),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_104_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(36 downto 35),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(69 downto 38),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(23 downto 12),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(4 downto 3),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_53\,
\m_axi_bid[23]\(13 downto 2) => m_axi_bid(23 downto 12),
\m_axi_bid[23]\(1 downto 0) => m_axi_bresp(3 downto 2),
m_axi_bready(0) => m_axi_bready(1),
m_axi_bvalid(0) => m_axi_bvalid(1),
m_axi_rdata(31 downto 0) => m_axi_rdata(63 downto 32),
m_axi_rid(11 downto 0) => m_axi_rid(23 downto 12),
m_axi_rlast(0) => m_axi_rlast(1),
\m_axi_rready[1]\ => M_AXI_RREADY(1),
m_axi_rresp(1 downto 0) => m_axi_rresp(3 downto 2),
m_axi_rvalid(0) => m_axi_rvalid(1),
p_102_out => p_102_out,
p_108_out => p_108_out,
p_1_in => p_1_in,
p_75_in => p_75_in,
\r_cmd_pop_1__1\ => \r_cmd_pop_1__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[1].w_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(8),
O => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].w_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => splitter_aw_mi_n_1,
Q => w_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => splitter_aw_mi_n_0,
Q => w_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\,
Q => w_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => splitter_aw_mi_n_2,
Q => w_issuing_cnt(9),
R => reset
);
\gen_master_slots[2].r_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(16),
O => \gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0\
);
\gen_master_slots[2].r_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => \gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0\,
Q => r_issuing_cnt(16),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_90,
Q => r_issuing_cnt(17),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_89,
Q => r_issuing_cnt(18),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_88,
Q => r_issuing_cnt(19),
R => reset
);
\gen_master_slots[2].reg_slice_mi\: entity work.zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2
port map (
D(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\,
E(0) => \gen_master_slots[2].reg_slice_mi_n_4\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(2),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[2]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2),
\chosen_reg[2]_0\(0) => \r_pipe/p_1_in\,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(3 downto 0) => r_issuing_cnt(19 downto 16),
\gen_master_slots[3].r_issuing_cnt_reg[24]\ => \gen_master_slots[3].reg_slice_mi_n_7\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(35 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_84_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(71 downto 70),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(104 downto 73),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(35 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(7 downto 6),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[2].reg_slice_mi_n_53\,
\m_axi_bid[35]\(13 downto 2) => m_axi_bid(35 downto 24),
\m_axi_bid[35]\(1 downto 0) => m_axi_bresp(5 downto 4),
m_axi_bready(0) => m_axi_bready(2),
m_axi_bvalid(0) => m_axi_bvalid(2),
m_axi_rdata(31 downto 0) => m_axi_rdata(95 downto 64),
m_axi_rid(11 downto 0) => m_axi_rid(35 downto 24),
m_axi_rlast(0) => m_axi_rlast(2),
\m_axi_rready[2]\ => M_AXI_RREADY(2),
m_axi_rresp(1 downto 0) => m_axi_rresp(5 downto 4),
m_axi_rvalid(0) => m_axi_rvalid(2),
p_1_in => p_1_in,
p_57_in => p_57_in,
p_82_out => p_82_out,
p_88_out => p_88_out,
\r_cmd_pop_2__1\ => \r_cmd_pop_2__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[2].w_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(16),
O => \gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0\
);
\gen_master_slots[2].w_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => \gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0\,
Q => w_issuing_cnt(16),
R => reset
);
\gen_master_slots[2].w_issuing_cnt_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => splitter_aw_mi_n_6,
Q => w_issuing_cnt(17),
R => reset
);
\gen_master_slots[2].w_issuing_cnt_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => splitter_aw_mi_n_5,
Q => w_issuing_cnt(18),
R => reset
);
\gen_master_slots[2].w_issuing_cnt_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => splitter_aw_mi_n_4,
Q => w_issuing_cnt(19),
R => reset
);
\gen_master_slots[3].r_issuing_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(24),
O => \gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0\
);
\gen_master_slots[3].r_issuing_cnt_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => \gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0\,
Q => r_issuing_cnt(24),
R => reset
);
\gen_master_slots[3].r_issuing_cnt_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => addr_arbiter_ar_n_87,
Q => r_issuing_cnt(25),
R => reset
);
\gen_master_slots[3].r_issuing_cnt_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => addr_arbiter_ar_n_86,
Q => r_issuing_cnt(26),
R => reset
);
\gen_master_slots[3].r_issuing_cnt_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => addr_arbiter_ar_n_85,
Q => r_issuing_cnt(27),
R => reset
);
\gen_master_slots[3].reg_slice_mi\: entity work.zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_3
port map (
D(13 downto 2) => m_axi_bid(47 downto 36),
D(1 downto 0) => m_axi_bresp(7 downto 6),
E(0) => \gen_master_slots[3].reg_slice_mi_n_5\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(3),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \gen_master_slots[3].reg_slice_mi_n_57\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_1\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[3]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(3),
\chosen_reg[3]_0\(0) => \r_pipe/p_1_in_5\,
\chosen_reg[4]\ => \gen_master_slots[3].reg_slice_mi_n_55\,
\chosen_reg[4]_0\ => \gen_master_slots[3].reg_slice_mi_n_56\,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(3 downto 0) => r_issuing_cnt(27 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(47 downto 36),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_64_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(106 downto 105),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(139 downto 108),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(47 downto 36),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(10 downto 9),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[3].reg_slice_mi_n_7\,
m_axi_bready(0) => m_axi_bready(3),
m_axi_bvalid(0) => m_axi_bvalid(3),
m_axi_rdata(31 downto 0) => m_axi_rdata(127 downto 96),
m_axi_rid(11 downto 0) => m_axi_rid(47 downto 36),
m_axi_rlast(0) => m_axi_rlast(3),
\m_axi_rready[3]\ => M_AXI_RREADY(3),
m_axi_rresp(1 downto 0) => m_axi_rresp(7 downto 6),
m_axi_rvalid(0) => m_axi_rvalid(3),
p_1_in => p_1_in,
p_39_in => p_39_in,
p_62_out => p_62_out,
p_68_out => p_68_out,
p_82_out => p_82_out,
p_88_out => p_88_out,
\r_cmd_pop_3__1\ => \r_cmd_pop_3__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[3].w_issuing_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(24),
O => \gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0\
);
\gen_master_slots[3].w_issuing_cnt_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => \gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0\,
Q => w_issuing_cnt(24),
R => reset
);
\gen_master_slots[3].w_issuing_cnt_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => splitter_aw_mi_n_9,
Q => w_issuing_cnt(25),
R => reset
);
\gen_master_slots[3].w_issuing_cnt_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => splitter_aw_mi_n_8,
Q => w_issuing_cnt(26),
R => reset
);
\gen_master_slots[3].w_issuing_cnt_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => splitter_aw_mi_n_7,
Q => w_issuing_cnt(27),
R => reset
);
\gen_master_slots[4].r_issuing_cnt_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_ar_n_99,
Q => r_issuing_cnt(32),
R => reset
);
\gen_master_slots[4].reg_slice_mi\: entity work.zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_4
port map (
D(11 downto 0) => p_32_in(11 downto 0),
E(0) => \r_pipe/p_1_in_6\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(4),
aclk => aclk,
\aresetn_d_reg[0]\ => \gen_master_slots[3].reg_slice_mi_n_57\,
\chosen_reg[4]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(4),
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => p_28_in(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 1) => st_mr_rid(59 downto 48),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => p_42_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(11 downto 0) => st_mr_bid(59 downto 48),
m_valid_i_reg => \gen_master_slots[4].reg_slice_mi_n_1\,
mi_bready_4 => mi_bready_4,
mi_rready_4 => mi_rready_4,
p_1_in => p_1_in,
p_23_in => p_23_in,
p_25_in => p_25_in,
p_29_in => p_29_in,
p_40_out => p_40_out,
p_46_out => p_46_out,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0),
s_ready_i_reg => \gen_master_slots[4].reg_slice_mi_n_5\
);
\gen_master_slots[4].w_issuing_cnt_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_aw_n_25,
Q => w_issuing_cnt(32),
R => reset
);
\gen_slave_slots[0].gen_si_read.si_transactor_ar\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
D(0) => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49\,
E(0) => s_ready_i0,
Q(4 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen\(4 downto 0),
SR(0) => reset,
S_AXI_ARREADY(0) => \^s_axi_arready\(0),
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_53\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].reg_slice_mi_n_53\,
\m_payload_i_reg[0]\(0) => \r_pipe/p_1_in_8\,
\m_payload_i_reg[0]_0\(0) => \r_pipe/p_1_in_7\,
\m_payload_i_reg[0]_1\(0) => \r_pipe/p_1_in_5\,
\m_payload_i_reg[0]_2\(0) => \r_pipe/p_1_in\,
\m_payload_i_reg[34]\(0) => \r_pipe/p_1_in_6\,
\m_payload_i_reg[34]_0\(0) => p_42_out,
\m_payload_i_reg[34]_1\(0) => p_64_out,
\m_payload_i_reg[34]_2\(0) => p_124_out,
\m_payload_i_reg[34]_3\(0) => p_84_out,
\m_payload_i_reg[34]_4\(0) => p_104_out,
m_valid_i => m_valid_i,
m_valid_i_reg => \gen_master_slots[3].reg_slice_mi_n_55\,
m_valid_i_reg_0 => \gen_master_slots[0].reg_slice_mi_n_54\,
match => match,
p_102_out => p_102_out,
p_122_out => p_122_out,
p_40_out => p_40_out,
p_62_out => p_62_out,
p_82_out => p_82_out,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
r_issuing_cnt(0) => r_issuing_cnt(32),
\s_axi_araddr[30]\(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\,
\s_axi_araddr[30]\(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\,
\s_axi_araddr[30]\(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
\s_axi_arid[11]\(11 downto 0) => \s_axi_arqos[3]\(11 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rid[0]\ => \s_axi_rid[0]\,
\s_axi_rid[10]\ => \s_axi_rid[10]\,
\s_axi_rid[11]\ => \s_axi_rid[11]\,
\s_axi_rid[1]\ => \s_axi_rid[1]\,
\s_axi_rid[2]\ => \s_axi_rid[2]\,
\s_axi_rid[3]\ => \s_axi_rid[3]\,
\s_axi_rid[4]\ => \s_axi_rid[4]\,
\s_axi_rid[5]\ => \s_axi_rid[5]\,
\s_axi_rid[6]\ => \s_axi_rid[6]\,
\s_axi_rid[7]\ => \s_axi_rid[7]\,
\s_axi_rid[8]\ => \s_axi_rid[8]\,
\s_axi_rid[9]\ => \s_axi_rid[9]\,
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
\s_axi_rvalid[0]\ => \s_axi_rvalid[0]\,
st_mr_rid(59 downto 0) => st_mr_rid(59 downto 0),
st_mr_rmesg(135 downto 104) => st_mr_rmesg(139 downto 108),
st_mr_rmesg(103 downto 70) => st_mr_rmesg(106 downto 73),
st_mr_rmesg(69 downto 36) => st_mr_rmesg(71 downto 38),
st_mr_rmesg(35 downto 2) => st_mr_rmesg(36 downto 3),
st_mr_rmesg(1 downto 0) => st_mr_rmesg(1 downto 0)
);
\gen_slave_slots[0].gen_si_write.si_transactor_aw\: entity work.\zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_4\,
D(2) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\,
D(1 downto 0) => st_aa_awtarget_enc(1 downto 0),
E(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
Q(4 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(4 downto 0),
SR(0) => reset,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_master_slots[0].w_issuing_cnt_reg[0]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
\gen_master_slots[2].w_issuing_cnt_reg[16]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
\gen_master_slots[3].w_issuing_cnt_reg[24]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
\gen_no_arbiter.s_ready_i_reg[0]\(0) => s_ready_i0_11,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_aw_n_23,
\m_ready_d_reg[1]\ => \^s_axi_awready[0]\,
m_valid_i => m_valid_i_10,
m_valid_i_reg => \gen_master_slots[3].reg_slice_mi_n_56\,
m_valid_i_reg_0 => \gen_master_slots[0].reg_slice_mi_n_55\,
match => match_3,
p_101_in => p_101_in,
p_108_out => p_108_out,
p_128_out => p_128_out,
p_46_out => p_46_out,
p_48_in => p_48_in,
p_66_in => p_66_in,
p_68_out => p_68_out,
p_84_in => p_84_in,
p_88_out => p_88_out,
\s_axi_awaddr[30]\(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\,
\s_axi_awaddr[30]\(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\,
\s_axi_awaddr[30]\(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\,
\s_axi_awid[11]\(11 downto 0) => D(11 downto 0),
\s_axi_bid[0]\ => \s_axi_bid[0]\,
\s_axi_bid[10]\ => \s_axi_bid[10]\,
\s_axi_bid[11]\ => \s_axi_bid[11]\,
\s_axi_bid[1]\ => \s_axi_bid[1]\,
\s_axi_bid[2]\ => \s_axi_bid[2]\,
\s_axi_bid[3]\ => \s_axi_bid[3]\,
\s_axi_bid[4]\ => \s_axi_bid[4]\,
\s_axi_bid[5]\ => \s_axi_bid[5]\,
\s_axi_bid[6]\ => \s_axi_bid[6]\,
\s_axi_bid[7]\ => \s_axi_bid[7]\,
\s_axi_bid[8]\ => \s_axi_bid[8]\,
\s_axi_bid[9]\ => \s_axi_bid[9]\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
\s_axi_bvalid[0]\ => \s_axi_bvalid[0]\,
st_mr_bid(59 downto 0) => st_mr_bid(59 downto 0),
st_mr_bmesg(7 downto 6) => st_mr_bmesg(10 downto 9),
st_mr_bmesg(5 downto 4) => st_mr_bmesg(7 downto 6),
st_mr_bmesg(3 downto 2) => st_mr_bmesg(4 downto 3),
st_mr_bmesg(1 downto 0) => st_mr_bmesg(1 downto 0),
w_issuing_cnt(16) => w_issuing_cnt(32),
w_issuing_cnt(15 downto 12) => w_issuing_cnt(27 downto 24),
w_issuing_cnt(11 downto 8) => w_issuing_cnt(19 downto 16),
w_issuing_cnt(7 downto 4) => w_issuing_cnt(11 downto 8),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
\gen_slave_slots[0].gen_si_write.splitter_aw_si\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter
port map (
aclk => aclk,
aresetn_d => aresetn_d,
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
\s_axi_awready[0]\ => \^s_axi_awready[0]\,
s_axi_awvalid(0) => s_axi_awvalid(0),
ss_aa_awready => ss_aa_awready,
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid
);
\gen_slave_slots[0].gen_si_write.wdata_router_w\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_wdata_router
port map (
D(2) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\,
D(1 downto 0) => st_aa_awtarget_enc(1 downto 0),
SR(0) => reset,
aclk => aclk,
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
m_ready_d(0) => m_ready_d(1),
match => match_3,
p_22_in => p_22_in,
\s_axi_awaddr[30]\(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\,
\s_axi_awaddr[30]\(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\,
\s_axi_awaddr[30]\(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
\write_cs0__0\ => \write_cs0__0\
);
splitter_aw_mi: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter_5
port map (
D(2) => splitter_aw_mi_n_0,
D(1) => splitter_aw_mi_n_1,
D(0) => splitter_aw_mi_n_2,
Q(3 downto 0) => aa_mi_awtarget_hot(3 downto 0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\chosen_reg[3]\(3 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(3 downto 0),
\gen_axi.s_axi_awready_i_reg\ => splitter_aw_mi_n_3,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(2) => splitter_aw_mi_n_10,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(1) => splitter_aw_mi_n_11,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(0) => splitter_aw_mi_n_12,
\gen_master_slots[2].w_issuing_cnt_reg[19]\(2) => splitter_aw_mi_n_4,
\gen_master_slots[2].w_issuing_cnt_reg[19]\(1) => splitter_aw_mi_n_5,
\gen_master_slots[2].w_issuing_cnt_reg[19]\(0) => splitter_aw_mi_n_6,
\gen_master_slots[3].w_issuing_cnt_reg[27]\(2) => splitter_aw_mi_n_7,
\gen_master_slots[3].w_issuing_cnt_reg[27]\(1) => splitter_aw_mi_n_8,
\gen_master_slots[3].w_issuing_cnt_reg[27]\(0) => splitter_aw_mi_n_9,
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_ready_d(1 downto 0) => m_ready_d_12(1 downto 0),
\mi_awready_mux__3\ => \mi_awready_mux__3\,
p_108_out => p_108_out,
p_128_out => p_128_out,
p_68_out => p_68_out,
p_88_out => p_88_out,
s_axi_bready(0) => s_axi_bready(0),
\s_ready_i0__1\(0) => \s_ready_i0__1\(0),
\sa_wm_awready_mux__3\ => \sa_wm_awready_mux__3\,
w_issuing_cnt(15 downto 12) => w_issuing_cnt(27 downto 24),
w_issuing_cnt(11 downto 8) => w_issuing_cnt(19 downto 16),
w_issuing_cnt(7 downto 4) => w_issuing_cnt(11 downto 8),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_ruser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000001101000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 4;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "axi_crossbar_v2_1_14_axi_crossbar";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute P_INCR : string;
attribute P_INCR of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute P_LOCK : integer;
attribute P_LOCK of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "4'b1111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "4'b1111";
attribute P_ONES : string;
attribute P_ONES of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 127 downto 96 );
signal \^m_axi_arburst\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \^m_axi_arcache\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_arlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_arlock\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^m_axi_arqos\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_arsize\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 127 downto 96 );
signal \^m_axi_awburst\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \^m_axi_awcache\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_awlen\ : STD_LOGIC_VECTOR ( 31 downto 24 );
signal \^m_axi_awlock\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \^m_axi_awprot\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^m_axi_awqos\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_awsize\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\(0) <= s_axi_wlast(0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
m_axi_araddr(127 downto 96) <= \^m_axi_araddr\(127 downto 96);
m_axi_araddr(95 downto 64) <= \^m_axi_araddr\(127 downto 96);
m_axi_araddr(63 downto 32) <= \^m_axi_araddr\(127 downto 96);
m_axi_araddr(31 downto 0) <= \^m_axi_araddr\(127 downto 96);
m_axi_arburst(7 downto 6) <= \^m_axi_arburst\(7 downto 6);
m_axi_arburst(5 downto 4) <= \^m_axi_arburst\(7 downto 6);
m_axi_arburst(3 downto 2) <= \^m_axi_arburst\(7 downto 6);
m_axi_arburst(1 downto 0) <= \^m_axi_arburst\(7 downto 6);
m_axi_arcache(15 downto 12) <= \^m_axi_arcache\(15 downto 12);
m_axi_arcache(11 downto 8) <= \^m_axi_arcache\(15 downto 12);
m_axi_arcache(7 downto 4) <= \^m_axi_arcache\(15 downto 12);
m_axi_arcache(3 downto 0) <= \^m_axi_arcache\(15 downto 12);
m_axi_arid(47 downto 36) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(35 downto 24) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(23 downto 12) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(11 downto 0) <= \^m_axi_arid\(11 downto 0);
m_axi_arlen(31 downto 24) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(23 downto 16) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(15 downto 8) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(7 downto 0) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlock(3) <= \^m_axi_arlock\(3);
m_axi_arlock(2) <= \^m_axi_arlock\(3);
m_axi_arlock(1) <= \^m_axi_arlock\(3);
m_axi_arlock(0) <= \^m_axi_arlock\(3);
m_axi_arprot(11 downto 9) <= \^m_axi_arprot\(11 downto 9);
m_axi_arprot(8 downto 6) <= \^m_axi_arprot\(11 downto 9);
m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(11 downto 9);
m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(11 downto 9);
m_axi_arqos(15 downto 12) <= \^m_axi_arqos\(15 downto 12);
m_axi_arqos(11 downto 8) <= \^m_axi_arqos\(15 downto 12);
m_axi_arqos(7 downto 4) <= \^m_axi_arqos\(15 downto 12);
m_axi_arqos(3 downto 0) <= \^m_axi_arqos\(15 downto 12);
m_axi_arregion(15) <= \<const0>\;
m_axi_arregion(14) <= \<const0>\;
m_axi_arregion(13) <= \<const0>\;
m_axi_arregion(12) <= \<const0>\;
m_axi_arregion(11) <= \<const0>\;
m_axi_arregion(10) <= \<const0>\;
m_axi_arregion(9) <= \<const0>\;
m_axi_arregion(8) <= \<const0>\;
m_axi_arregion(7) <= \<const0>\;
m_axi_arregion(6) <= \<const0>\;
m_axi_arregion(5) <= \<const0>\;
m_axi_arregion(4) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(11 downto 9) <= \^m_axi_arsize\(11 downto 9);
m_axi_arsize(8 downto 6) <= \^m_axi_arsize\(11 downto 9);
m_axi_arsize(5 downto 3) <= \^m_axi_arsize\(11 downto 9);
m_axi_arsize(2 downto 0) <= \^m_axi_arsize\(11 downto 9);
m_axi_aruser(3) <= \<const0>\;
m_axi_aruser(2) <= \<const0>\;
m_axi_aruser(1) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awaddr(127 downto 96) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awaddr(95 downto 64) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awaddr(63 downto 32) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awaddr(31 downto 0) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awburst(7 downto 6) <= \^m_axi_awburst\(7 downto 6);
m_axi_awburst(5 downto 4) <= \^m_axi_awburst\(7 downto 6);
m_axi_awburst(3 downto 2) <= \^m_axi_awburst\(7 downto 6);
m_axi_awburst(1 downto 0) <= \^m_axi_awburst\(7 downto 6);
m_axi_awcache(15 downto 12) <= \^m_axi_awcache\(15 downto 12);
m_axi_awcache(11 downto 8) <= \^m_axi_awcache\(15 downto 12);
m_axi_awcache(7 downto 4) <= \^m_axi_awcache\(15 downto 12);
m_axi_awcache(3 downto 0) <= \^m_axi_awcache\(15 downto 12);
m_axi_awid(47 downto 36) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(35 downto 24) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(23 downto 12) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(11 downto 0) <= \^m_axi_awid\(11 downto 0);
m_axi_awlen(31 downto 24) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(23 downto 16) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(15 downto 8) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(7 downto 0) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlock(3) <= \^m_axi_awlock\(3);
m_axi_awlock(2) <= \^m_axi_awlock\(3);
m_axi_awlock(1) <= \^m_axi_awlock\(3);
m_axi_awlock(0) <= \^m_axi_awlock\(3);
m_axi_awprot(11 downto 9) <= \^m_axi_awprot\(11 downto 9);
m_axi_awprot(8 downto 6) <= \^m_axi_awprot\(11 downto 9);
m_axi_awprot(5 downto 3) <= \^m_axi_awprot\(11 downto 9);
m_axi_awprot(2 downto 0) <= \^m_axi_awprot\(11 downto 9);
m_axi_awqos(15 downto 12) <= \^m_axi_awqos\(15 downto 12);
m_axi_awqos(11 downto 8) <= \^m_axi_awqos\(15 downto 12);
m_axi_awqos(7 downto 4) <= \^m_axi_awqos\(15 downto 12);
m_axi_awqos(3 downto 0) <= \^m_axi_awqos\(15 downto 12);
m_axi_awregion(15) <= \<const0>\;
m_axi_awregion(14) <= \<const0>\;
m_axi_awregion(13) <= \<const0>\;
m_axi_awregion(12) <= \<const0>\;
m_axi_awregion(11) <= \<const0>\;
m_axi_awregion(10) <= \<const0>\;
m_axi_awregion(9) <= \<const0>\;
m_axi_awregion(8) <= \<const0>\;
m_axi_awregion(7) <= \<const0>\;
m_axi_awregion(6) <= \<const0>\;
m_axi_awregion(5) <= \<const0>\;
m_axi_awregion(4) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(11 downto 9) <= \^m_axi_awsize\(11 downto 9);
m_axi_awsize(8 downto 6) <= \^m_axi_awsize\(11 downto 9);
m_axi_awsize(5 downto 3) <= \^m_axi_awsize\(11 downto 9);
m_axi_awsize(2 downto 0) <= \^m_axi_awsize\(11 downto 9);
m_axi_awuser(3) <= \<const0>\;
m_axi_awuser(2) <= \<const0>\;
m_axi_awuser(1) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(127 downto 96) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(95 downto 64) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(47) <= \<const0>\;
m_axi_wid(46) <= \<const0>\;
m_axi_wid(45) <= \<const0>\;
m_axi_wid(44) <= \<const0>\;
m_axi_wid(43) <= \<const0>\;
m_axi_wid(42) <= \<const0>\;
m_axi_wid(41) <= \<const0>\;
m_axi_wid(40) <= \<const0>\;
m_axi_wid(39) <= \<const0>\;
m_axi_wid(38) <= \<const0>\;
m_axi_wid(37) <= \<const0>\;
m_axi_wid(36) <= \<const0>\;
m_axi_wid(35) <= \<const0>\;
m_axi_wid(34) <= \<const0>\;
m_axi_wid(33) <= \<const0>\;
m_axi_wid(32) <= \<const0>\;
m_axi_wid(31) <= \<const0>\;
m_axi_wid(30) <= \<const0>\;
m_axi_wid(29) <= \<const0>\;
m_axi_wid(28) <= \<const0>\;
m_axi_wid(27) <= \<const0>\;
m_axi_wid(26) <= \<const0>\;
m_axi_wid(25) <= \<const0>\;
m_axi_wid(24) <= \<const0>\;
m_axi_wid(23) <= \<const0>\;
m_axi_wid(22) <= \<const0>\;
m_axi_wid(21) <= \<const0>\;
m_axi_wid(20) <= \<const0>\;
m_axi_wid(19) <= \<const0>\;
m_axi_wid(18) <= \<const0>\;
m_axi_wid(17) <= \<const0>\;
m_axi_wid(16) <= \<const0>\;
m_axi_wid(15) <= \<const0>\;
m_axi_wid(14) <= \<const0>\;
m_axi_wid(13) <= \<const0>\;
m_axi_wid(12) <= \<const0>\;
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast(3) <= \^s_axi_wlast\(0);
m_axi_wlast(2) <= \^s_axi_wlast\(0);
m_axi_wlast(1) <= \^s_axi_wlast\(0);
m_axi_wlast(0) <= \^s_axi_wlast\(0);
m_axi_wstrb(15 downto 12) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(11 downto 8) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(3) <= \<const0>\;
m_axi_wuser(2) <= \<const0>\;
m_axi_wuser(1) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_samd.crossbar_samd\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_crossbar
port map (
D(68 downto 65) => s_axi_awqos(3 downto 0),
D(64 downto 61) => s_axi_awcache(3 downto 0),
D(60 downto 59) => s_axi_awburst(1 downto 0),
D(58 downto 56) => s_axi_awprot(2 downto 0),
D(55) => s_axi_awlock(0),
D(54 downto 52) => s_axi_awsize(2 downto 0),
D(51 downto 44) => s_axi_awlen(7 downto 0),
D(43 downto 12) => s_axi_awaddr(31 downto 0),
D(11 downto 0) => s_axi_awid(11 downto 0),
M_AXI_RREADY(3 downto 0) => m_axi_rready(3 downto 0),
Q(68 downto 65) => \^m_axi_awqos\(15 downto 12),
Q(64 downto 61) => \^m_axi_awcache\(15 downto 12),
Q(60 downto 59) => \^m_axi_awburst\(7 downto 6),
Q(58 downto 56) => \^m_axi_awprot\(11 downto 9),
Q(55) => \^m_axi_awlock\(3),
Q(54 downto 52) => \^m_axi_awsize\(11 downto 9),
Q(51 downto 44) => \^m_axi_awlen\(31 downto 24),
Q(43 downto 12) => \^m_axi_awaddr\(127 downto 96),
Q(11 downto 0) => \^m_axi_awid\(11 downto 0),
S_AXI_ARREADY(0) => s_axi_arready(0),
aclk => aclk,
aresetn => aresetn,
\m_axi_arqos[15]\(68 downto 65) => \^m_axi_arqos\(15 downto 12),
\m_axi_arqos[15]\(64 downto 61) => \^m_axi_arcache\(15 downto 12),
\m_axi_arqos[15]\(60 downto 59) => \^m_axi_arburst\(7 downto 6),
\m_axi_arqos[15]\(58 downto 56) => \^m_axi_arprot\(11 downto 9),
\m_axi_arqos[15]\(55) => \^m_axi_arlock\(3),
\m_axi_arqos[15]\(54 downto 52) => \^m_axi_arsize\(11 downto 9),
\m_axi_arqos[15]\(51 downto 44) => \^m_axi_arlen\(7 downto 0),
\m_axi_arqos[15]\(43 downto 12) => \^m_axi_araddr\(127 downto 96),
\m_axi_arqos[15]\(11 downto 0) => \^m_axi_arid\(11 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_axi_bid(47 downto 0) => m_axi_bid(47 downto 0),
m_axi_bready(3 downto 0) => m_axi_bready(3 downto 0),
m_axi_bresp(7 downto 0) => m_axi_bresp(7 downto 0),
m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(47 downto 0) => m_axi_rid(47 downto 0),
m_axi_rlast(3 downto 0) => m_axi_rlast(3 downto 0),
m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
m_axi_rvalid(3 downto 0) => m_axi_rvalid(3 downto 0),
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
\s_axi_arqos[3]\(68 downto 65) => s_axi_arqos(3 downto 0),
\s_axi_arqos[3]\(64 downto 61) => s_axi_arcache(3 downto 0),
\s_axi_arqos[3]\(60 downto 59) => s_axi_arburst(1 downto 0),
\s_axi_arqos[3]\(58 downto 56) => s_axi_arprot(2 downto 0),
\s_axi_arqos[3]\(55) => s_axi_arlock(0),
\s_axi_arqos[3]\(54 downto 52) => s_axi_arsize(2 downto 0),
\s_axi_arqos[3]\(51 downto 44) => s_axi_arlen(7 downto 0),
\s_axi_arqos[3]\(43 downto 12) => s_axi_araddr(31 downto 0),
\s_axi_arqos[3]\(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
\s_axi_awready[0]\ => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
\s_axi_bid[0]\ => s_axi_bid(0),
\s_axi_bid[10]\ => s_axi_bid(10),
\s_axi_bid[11]\ => s_axi_bid(11),
\s_axi_bid[1]\ => s_axi_bid(1),
\s_axi_bid[2]\ => s_axi_bid(2),
\s_axi_bid[3]\ => s_axi_bid(3),
\s_axi_bid[4]\ => s_axi_bid(4),
\s_axi_bid[5]\ => s_axi_bid(5),
\s_axi_bid[6]\ => s_axi_bid(6),
\s_axi_bid[7]\ => s_axi_bid(7),
\s_axi_bid[8]\ => s_axi_bid(8),
\s_axi_bid[9]\ => s_axi_bid(9),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
\s_axi_bvalid[0]\ => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rid[0]\ => s_axi_rid(0),
\s_axi_rid[10]\ => s_axi_rid(10),
\s_axi_rid[11]\ => s_axi_rid(11),
\s_axi_rid[1]\ => s_axi_rid(1),
\s_axi_rid[2]\ => s_axi_rid(2),
\s_axi_rid[3]\ => s_axi_rid(3),
\s_axi_rid[4]\ => s_axi_rid(4),
\s_axi_rid[5]\ => s_axi_rid(5),
\s_axi_rid[6]\ => s_axi_rid(6),
\s_axi_rid[7]\ => s_axi_rid(7),
\s_axi_rid[8]\ => s_axi_rid(8),
\s_axi_rid[9]\ => s_axi_rid(9),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
\s_axi_rvalid[0]\ => s_axi_rvalid(0),
s_axi_wlast(0) => \^s_axi_wlast\(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zqynq_lab_1_design_xbar_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_xbar_0 : entity is "zqynq_lab_1_design_xbar_0,axi_crossbar_v2_1_14_axi_crossbar,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_xbar_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zqynq_lab_1_design_xbar_0 : entity is "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2.1";
end zqynq_lab_1_design_xbar_0;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of inst : label is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of inst : label is "128'b00000000000000000000000000001101000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of inst : label is "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of inst : label is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of inst : label is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of inst : label is 4;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of inst : label is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of inst : label is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of inst : label is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of inst : label is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 8;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of inst : label is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of inst : label is "zynq";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of inst : label is 8;
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of inst : label is "4'b1111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "4'b1111";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of inst : label is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
begin
inst: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(127 downto 0) => m_axi_araddr(127 downto 0),
m_axi_arburst(7 downto 0) => m_axi_arburst(7 downto 0),
m_axi_arcache(15 downto 0) => m_axi_arcache(15 downto 0),
m_axi_arid(47 downto 0) => m_axi_arid(47 downto 0),
m_axi_arlen(31 downto 0) => m_axi_arlen(31 downto 0),
m_axi_arlock(3 downto 0) => m_axi_arlock(3 downto 0),
m_axi_arprot(11 downto 0) => m_axi_arprot(11 downto 0),
m_axi_arqos(15 downto 0) => m_axi_arqos(15 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arregion(15 downto 0) => m_axi_arregion(15 downto 0),
m_axi_arsize(11 downto 0) => m_axi_arsize(11 downto 0),
m_axi_aruser(3 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_axi_awaddr(127 downto 0) => m_axi_awaddr(127 downto 0),
m_axi_awburst(7 downto 0) => m_axi_awburst(7 downto 0),
m_axi_awcache(15 downto 0) => m_axi_awcache(15 downto 0),
m_axi_awid(47 downto 0) => m_axi_awid(47 downto 0),
m_axi_awlen(31 downto 0) => m_axi_awlen(31 downto 0),
m_axi_awlock(3 downto 0) => m_axi_awlock(3 downto 0),
m_axi_awprot(11 downto 0) => m_axi_awprot(11 downto 0),
m_axi_awqos(15 downto 0) => m_axi_awqos(15 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awregion(15 downto 0) => m_axi_awregion(15 downto 0),
m_axi_awsize(11 downto 0) => m_axi_awsize(11 downto 0),
m_axi_awuser(3 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_axi_bid(47 downto 0) => m_axi_bid(47 downto 0),
m_axi_bready(3 downto 0) => m_axi_bready(3 downto 0),
m_axi_bresp(7 downto 0) => m_axi_bresp(7 downto 0),
m_axi_buser(3 downto 0) => B"0000",
m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(47 downto 0) => m_axi_rid(47 downto 0),
m_axi_rlast(3 downto 0) => m_axi_rlast(3 downto 0),
m_axi_rready(3 downto 0) => m_axi_rready(3 downto 0),
m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
m_axi_ruser(3 downto 0) => B"0000",
m_axi_rvalid(3 downto 0) => m_axi_rvalid(3 downto 0),
m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
m_axi_wid(47 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(47 downto 0),
m_axi_wlast(3 downto 0) => m_axi_wlast(3 downto 0),
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
m_axi_wuser(3 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: CPE233:F17:Mux4x1:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY Program_Counter_Mux4x1_0_1 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END Program_Counter_Mux4x1_0_1;
ARCHITECTURE Program_Counter_Mux4x1_0_1_arch OF Program_Counter_Mux4x1_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Program_Counter_Mux4x1_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT Mux4x1 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT Mux4x1;
BEGIN
U0 : Mux4x1
PORT MAP (
A => A,
B => B,
C => C,
D => D,
SEL => SEL,
X => X
);
END Program_Counter_Mux4x1_0_1_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: CPE233:F17:Mux4x1:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY Program_Counter_Mux4x1_0_1 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END Program_Counter_Mux4x1_0_1;
ARCHITECTURE Program_Counter_Mux4x1_0_1_arch OF Program_Counter_Mux4x1_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Program_Counter_Mux4x1_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT Mux4x1 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT Mux4x1;
BEGIN
U0 : Mux4x1
PORT MAP (
A => A,
B => B,
C => C,
D => D,
SEL => SEL,
X => X
);
END Program_Counter_Mux4x1_0_1_arch;
|
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`protect end_protected
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-e.vhd,v 1.2 2007/03/03 17:24:06 wig Exp $
-- $Date: 2007/03/03 17:24:06 $
-- $Log: inst_t_e-e.vhd,v $
-- Revision 1.2 2007/03/03 17:24:06 wig
-- Updated testcase for case matches. Added filename serialization.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_t_e
--
entity inst_t_e is
-- Generics:
-- No Generated Generics for Entity inst_t_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_t_e
end inst_t_e;
--
-- End of Generated Entity inst_t_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_ch_20_11.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_20_11 is
end entity ch_20_11;
----------------------------------------------------------------
architecture test of ch_20_11 is
component comp is
end component comp;
signal clk_phase1, clk_phase2 : bit;
-- code from book:
group signal_pair is (signal, signal);
group clock_pair : signal_pair ( clk_phase1, clk_phase2 );
attribute max_skew : time;
attribute max_skew of clock_pair : group is 200 ps;
group component_instances is ( label <> );
group U1 : component_instances ( nand1, nand2, nand3 );
group U2 : component_instances ( inv1, inv2 );
attribute IC_allocation : string;
attribute IC_allocation of U1 : group is "74LS00";
attribute IC_allocation of U2 : group is "74LS04";
-- end of code from book
begin
nand1 : component comp;
nand2 : component comp;
nand3 : component comp;
inv1 : component comp;
inv2 : component comp;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_ch_20_11.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_20_11 is
end entity ch_20_11;
----------------------------------------------------------------
architecture test of ch_20_11 is
component comp is
end component comp;
signal clk_phase1, clk_phase2 : bit;
-- code from book:
group signal_pair is (signal, signal);
group clock_pair : signal_pair ( clk_phase1, clk_phase2 );
attribute max_skew : time;
attribute max_skew of clock_pair : group is 200 ps;
group component_instances is ( label <> );
group U1 : component_instances ( nand1, nand2, nand3 );
group U2 : component_instances ( inv1, inv2 );
attribute IC_allocation : string;
attribute IC_allocation of U1 : group is "74LS00";
attribute IC_allocation of U2 : group is "74LS04";
-- end of code from book
begin
nand1 : component comp;
nand2 : component comp;
nand3 : component comp;
inv1 : component comp;
inv2 : component comp;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_ch_20_11.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_20_11 is
end entity ch_20_11;
----------------------------------------------------------------
architecture test of ch_20_11 is
component comp is
end component comp;
signal clk_phase1, clk_phase2 : bit;
-- code from book:
group signal_pair is (signal, signal);
group clock_pair : signal_pair ( clk_phase1, clk_phase2 );
attribute max_skew : time;
attribute max_skew of clock_pair : group is 200 ps;
group component_instances is ( label <> );
group U1 : component_instances ( nand1, nand2, nand3 );
group U2 : component_instances ( inv1, inv2 );
attribute IC_allocation : string;
attribute IC_allocation of U1 : group is "74LS00";
attribute IC_allocation of U2 : group is "74LS04";
-- end of code from book
begin
nand1 : component comp;
nand2 : component comp;
nand3 : component comp;
inv1 : component comp;
inv2 : component comp;
end architecture test;
|
architecture RTL of FIFO is
begin
BLOCK_LABEL : block begin end block;
BLOCK_LABEL : block begin end block;
BLOCK_LABEL : block--Comment
begin end block;
BLOCK_LABEL : block --Comment
begin end block;
BLOCK_LABEL : block --Comment
begin end block;
BLOCK_LABEL : block (guard_condition)begin end block;
BLOCK_LABEL : block (guard_condition) begin end block;
BLOCK_LABEL : block (guard_condition)
begin end block;
BLOCK_LABEL : block
begin end block;
end architecture RTL;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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DDBOPkMw9w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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a9B0qJ7/pjdFZCMGQ/WlCt+XnoDLi9PpSJoCIg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23584)
`protect data_block
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`protect begin_protected
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`protect begin_protected
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`protect end_protected
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hist is
port (
clk : in std_logic;
se : in std_logic;
z_addr : in std_logic_vector(1 downto 0);
i_addr : in std_logic_vector(1 downto 0);
we : in std_logic;
D : in std_logic_vector(3 downto 0);
Q: out std_logic_vector(3 downto 0)
);
end entity;
architecture hist of hist is
type ram_type is array(6 downto 0) of std_logic_vector(3 downto 0);
signal ram : ram_type := ("0000","0000","0000","0000","0000","0000","0000");
signal Qt : std_logic_vector(3 downto 0) :="0000";
begin
process(clk)
begin
if rising_edge(clk) then
if we = '1' then
if se = '1' then
--1 for increment, 0 for zeroing
Q<=ram(conv_integer(i_addr)) + 1;
ram(conv_integer((i_addr)))<=ram(conv_integer((i_addr))) + 1;
elsif se = '0' then
--addr<=z_addr;
Q<=ram(conv_integer((z_addr)));
ram(conv_integer((z_addr)))<="0000";
end if;
end if;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- system_dlmb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_v10_v2_00_b;
use lmb_v10_v2_00_b.all;
entity system_dlmb_wrapper is
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 3);
Sl_DBus : in std_logic_vector(0 to 31);
Sl_Ready : in std_logic_vector(0 to 0);
Sl_Wait : in std_logic_vector(0 to 0);
Sl_UE : in std_logic_vector(0 to 0);
Sl_CE : in std_logic_vector(0 to 0);
LMB_ABus : out std_logic_vector(0 to 31);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to 31);
LMB_WriteDBus : out std_logic_vector(0 to 31);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to 3)
);
end system_dlmb_wrapper;
architecture STRUCTURE of system_dlmb_wrapper is
component lmb_v10 is
generic (
C_LMB_NUM_SLAVES : integer;
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_EXT_RESET_HIGH : integer
);
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1);
Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1);
Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_Wait : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_UE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_CE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1)
);
end component;
begin
dlmb : lmb_v10
generic map (
C_LMB_NUM_SLAVES => 1,
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_EXT_RESET_HIGH => 1
)
port map (
LMB_Clk => LMB_Clk,
SYS_Rst => SYS_Rst,
LMB_Rst => LMB_Rst,
M_ABus => M_ABus,
M_ReadStrobe => M_ReadStrobe,
M_WriteStrobe => M_WriteStrobe,
M_AddrStrobe => M_AddrStrobe,
M_DBus => M_DBus,
M_BE => M_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB_ABus => LMB_ABus,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadDBus => LMB_ReadDBus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_Ready => LMB_Ready,
LMB_Wait => LMB_Wait,
LMB_UE => LMB_UE,
LMB_CE => LMB_CE,
LMB_BE => LMB_BE
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
-- system_dlmb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_v10_v2_00_b;
use lmb_v10_v2_00_b.all;
entity system_dlmb_wrapper is
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 3);
Sl_DBus : in std_logic_vector(0 to 31);
Sl_Ready : in std_logic_vector(0 to 0);
Sl_Wait : in std_logic_vector(0 to 0);
Sl_UE : in std_logic_vector(0 to 0);
Sl_CE : in std_logic_vector(0 to 0);
LMB_ABus : out std_logic_vector(0 to 31);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to 31);
LMB_WriteDBus : out std_logic_vector(0 to 31);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to 3)
);
end system_dlmb_wrapper;
architecture STRUCTURE of system_dlmb_wrapper is
component lmb_v10 is
generic (
C_LMB_NUM_SLAVES : integer;
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_EXT_RESET_HIGH : integer
);
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1);
Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1);
Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_Wait : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_UE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_CE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1)
);
end component;
begin
dlmb : lmb_v10
generic map (
C_LMB_NUM_SLAVES => 1,
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_EXT_RESET_HIGH => 1
)
port map (
LMB_Clk => LMB_Clk,
SYS_Rst => SYS_Rst,
LMB_Rst => LMB_Rst,
M_ABus => M_ABus,
M_ReadStrobe => M_ReadStrobe,
M_WriteStrobe => M_WriteStrobe,
M_AddrStrobe => M_AddrStrobe,
M_DBus => M_DBus,
M_BE => M_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB_ABus => LMB_ABus,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadDBus => LMB_ReadDBus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_Ready => LMB_Ready,
LMB_Wait => LMB_Wait,
LMB_UE => LMB_UE,
LMB_CE => LMB_CE,
LMB_BE => LMB_BE
);
end architecture STRUCTURE;
|
-- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_12;
USE proc_sys_reset_v5_0_12.proc_sys_reset;
ENTITY gcd_block_design_rst_ps7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END gcd_block_design_rst_ps7_0_100M_0;
ARCHITECTURE gcd_block_design_rst_ps7_0_100M_0_arch OF gcd_block_design_rst_ps7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF gcd_block_design_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0";
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END gcd_block_design_rst_ps7_0_100M_0_arch;
|
-- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_12;
USE proc_sys_reset_v5_0_12.proc_sys_reset;
ENTITY gcd_block_design_rst_ps7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END gcd_block_design_rst_ps7_0_100M_0;
ARCHITECTURE gcd_block_design_rst_ps7_0_100M_0_arch OF gcd_block_design_rst_ps7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF gcd_block_design_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0";
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END gcd_block_design_rst_ps7_0_100M_0_arch;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief TileLink-to-AXI4 bridge implementation.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
library rocketlib;
use rocketlib.types_rocket.all;
entity Tile2Axi is
port (
clk : in std_logic;
nrst : in std_logic;
--! Tile-to-AXI direction
tloi : in tile_out_type;
msto : out nasti_master_out_type;
--! AXI-to-Tile direction
msti : in nasti_master_in_type;
tlio : out tile_in_type
);
end;
architecture arch_Tile2Axi of Tile2Axi is
component TLToAXI4
port (
clock : in std_logic;
reset : in std_logic;
io_in_0_a_ready : out std_logic;
io_in_0_a_valid : in std_logic;
io_in_0_a_bits_opcode : in std_logic_vector(2 downto 0);
io_in_0_a_bits_param : in std_logic_vector(2 downto 0);
io_in_0_a_bits_size : in std_logic_vector(3 downto 0);
io_in_0_a_bits_source : in std_logic_vector(5 downto 0);
io_in_0_a_bits_address : in std_logic_vector(31 downto 0);
io_in_0_a_bits_mask : in std_logic_vector(7 downto 0);
io_in_0_a_bits_data : in std_logic_vector(63 downto 0);
io_in_0_b_ready : in std_logic;
io_in_0_b_valid : out std_logic;
io_in_0_b_bits_opcode : out std_logic_vector(2 downto 0);
io_in_0_b_bits_param : out std_logic_vector(1 downto 0);
io_in_0_b_bits_size : out std_logic_vector(3 downto 0);
io_in_0_b_bits_source : out std_logic_vector(5 downto 0);
io_in_0_b_bits_address : out std_logic_vector(31 downto 0);
io_in_0_b_bits_mask : out std_logic_vector(7 downto 0);
io_in_0_b_bits_data : out std_logic_vector(63 downto 0);
io_in_0_c_ready : out std_logic;
io_in_0_c_valid : in std_logic;
io_in_0_c_bits_opcode : in std_logic_vector(2 downto 0);
io_in_0_c_bits_param : in std_logic_vector(2 downto 0);
io_in_0_c_bits_size : in std_logic_vector(3 downto 0);
io_in_0_c_bits_source : in std_logic_vector(5 downto 0);
io_in_0_c_bits_address : in std_logic_vector(31 downto 0);
io_in_0_c_bits_data : in std_logic_vector(63 downto 0);
io_in_0_c_bits_error : in std_logic;
io_in_0_d_ready : in std_logic;
io_in_0_d_valid : out std_logic;
io_in_0_d_bits_opcode : out std_logic_vector(2 downto 0);
io_in_0_d_bits_param : out std_logic_vector(1 downto 0);
io_in_0_d_bits_size : out std_logic_vector(3 downto 0);
io_in_0_d_bits_source : out std_logic_vector(5 downto 0);
io_in_0_d_bits_sink : out std_logic;
io_in_0_d_bits_addr_lo : out std_logic_vector(2 downto 0);
io_in_0_d_bits_data : out std_logic_vector(63 downto 0);
io_in_0_d_bits_error : out std_logic;
io_in_0_e_ready : out std_logic;
io_in_0_e_valid : in std_logic;
io_in_0_e_bits_sink : in std_logic;
io_out_0_aw_ready : in std_logic;
io_out_0_aw_valid : out std_logic;
io_out_0_aw_bits_id : out std_logic_vector(3 downto 0);
io_out_0_aw_bits_addr : out std_logic_vector(31 downto 0);
io_out_0_aw_bits_len : out std_logic_vector(7 downto 0);
io_out_0_aw_bits_size : out std_logic_vector(2 downto 0);
io_out_0_aw_bits_burst : out std_logic_vector(1 downto 0);
io_out_0_aw_bits_lock : out std_logic;
io_out_0_aw_bits_cache : out std_logic_vector(3 downto 0);
io_out_0_aw_bits_prot : out std_logic_vector(2 downto 0);
io_out_0_aw_bits_qos : out std_logic_vector(3 downto 0);
io_out_0_w_ready : in std_logic;
io_out_0_w_valid : out std_logic;
io_out_0_w_bits_data : out std_logic_vector(63 downto 0);
io_out_0_w_bits_strb : out std_logic_vector(7 downto 0);
io_out_0_w_bits_last : out std_logic;
io_out_0_b_ready : out std_logic;
io_out_0_b_valid : in std_logic;
io_out_0_b_bits_id : in std_logic_vector(3 downto 0);
io_out_0_b_bits_resp : in std_logic_vector(1 downto 0);
io_out_0_ar_ready : in std_logic;
io_out_0_ar_valid : out std_logic;
io_out_0_ar_bits_id : out std_logic_vector(3 downto 0);
io_out_0_ar_bits_addr : out std_logic_vector(31 downto 0);
io_out_0_ar_bits_len : out std_logic_vector(7 downto 0);
io_out_0_ar_bits_size : out std_logic_vector(2 downto 0);
io_out_0_ar_bits_burst : out std_logic_vector(1 downto 0);
io_out_0_ar_bits_lock : out std_logic;
io_out_0_ar_bits_cache : out std_logic_vector(3 downto 0);
io_out_0_ar_bits_prot : out std_logic_vector(2 downto 0);
io_out_0_ar_bits_qos : out std_logic_vector(3 downto 0);
io_out_0_r_ready : out std_logic;
io_out_0_r_valid : in std_logic;
io_out_0_r_bits_id : in std_logic_vector(3 downto 0);
io_out_0_r_bits_data : in std_logic_vector(63 downto 0);
io_out_0_r_bits_resp : in std_logic_vector(1 downto 0);
io_out_0_r_bits_last : in std_logic
);
end component;
signal reset : std_logic;
signal wb_a_source : std_logic_vector(5 downto 0);
signal wb_b_source : std_logic_vector(5 downto 0);
signal wb_c_source : std_logic_vector(5 downto 0);
signal wb_d_source : std_logic_vector(5 downto 0);
signal wb_aw_bits_addr : std_logic_vector(31 downto 0);
signal wb_ar_bits_addr : std_logic_vector(31 downto 0);
begin
reset <= not nrst;
wb_a_source <= "000" & tloi.a_source;
tlio.b_source <= wb_b_source(2 downto 0);
wb_c_source <= "000" & tloi.c_source;
tlio.d_source <= wb_d_source(2 downto 0);
tlio.d_sink(3 downto 1) <= "000";
ver0 : TLToAXI4 port map (
clock => clk,
reset => reset,
io_in_0_a_ready => tlio.a_ready,
io_in_0_a_valid => tloi.a_valid,
io_in_0_a_bits_opcode => tloi.a_opcode,
io_in_0_a_bits_param => tloi.a_param,
io_in_0_a_bits_size => tloi.a_size,
io_in_0_a_bits_source => wb_a_source,
io_in_0_a_bits_address => tloi.a_address,
io_in_0_a_bits_mask => tloi.a_mask,
io_in_0_a_bits_data => tloi.a_data,
io_in_0_b_ready => tloi.b_ready,
io_in_0_b_valid => tlio.b_valid,
io_in_0_b_bits_opcode => tlio.b_opcode,
io_in_0_b_bits_param => tlio.b_param,
io_in_0_b_bits_size => tlio.b_size,
io_in_0_b_bits_source => wb_b_source,
io_in_0_b_bits_address => tlio.b_address,
io_in_0_b_bits_mask => tlio.b_mask,
io_in_0_b_bits_data => tlio.b_data,
io_in_0_c_ready => tlio.c_ready,
io_in_0_c_valid => tloi.c_valid,
io_in_0_c_bits_opcode => tloi.c_opcode,
io_in_0_c_bits_param => tloi.c_param,
io_in_0_c_bits_size => tloi.c_size,
io_in_0_c_bits_source => wb_c_source,
io_in_0_c_bits_address => tloi.c_address,
io_in_0_c_bits_data => tloi.c_data,
io_in_0_c_bits_error => tloi.c_error,
io_in_0_d_ready => tloi.d_ready,
io_in_0_d_valid => tlio.d_valid,
io_in_0_d_bits_opcode => tlio.d_opcode,
io_in_0_d_bits_param => tlio.d_param,
io_in_0_d_bits_size => tlio.d_size,
io_in_0_d_bits_source => wb_d_source,
io_in_0_d_bits_sink => tlio.d_sink(0),
io_in_0_d_bits_addr_lo => tlio.d_addr_lo,
io_in_0_d_bits_data => tlio.d_data,
io_in_0_d_bits_error => tlio.d_error,
io_in_0_e_ready => tlio.e_ready,
io_in_0_e_valid => tloi.e_valid,
io_in_0_e_bits_sink => tloi.e_sink(0),
io_out_0_aw_ready => msti.aw_ready,
io_out_0_aw_valid => msto.aw_valid,
io_out_0_aw_bits_id => msto.aw_id(3 downto 0),
io_out_0_aw_bits_addr => wb_aw_bits_addr,
io_out_0_aw_bits_len => msto.aw_bits.len,
io_out_0_aw_bits_size => msto.aw_bits.size,
io_out_0_aw_bits_burst => msto.aw_bits.burst,
io_out_0_aw_bits_lock => msto.aw_bits.lock,
io_out_0_aw_bits_cache => msto.aw_bits.cache,
io_out_0_aw_bits_prot => msto.aw_bits.prot,
io_out_0_aw_bits_qos => msto.aw_bits.qos,
io_out_0_w_ready => msti.w_ready,
io_out_0_w_valid => msto.w_valid,
io_out_0_w_bits_data => msto.w_data,
io_out_0_w_bits_strb => msto.w_strb,
io_out_0_w_bits_last => msto.w_last,
io_out_0_b_ready => msto.b_ready,
io_out_0_b_valid => msti.b_valid,
io_out_0_b_bits_id => msti.b_id(3 downto 0),
io_out_0_b_bits_resp => msti.b_resp,
io_out_0_ar_ready => msti.ar_ready,
io_out_0_ar_valid => msto.ar_valid,
io_out_0_ar_bits_id => msto.ar_id(3 downto 0),
io_out_0_ar_bits_addr => wb_ar_bits_addr,
io_out_0_ar_bits_len => msto.ar_bits.len,
io_out_0_ar_bits_size => msto.ar_bits.size,
io_out_0_ar_bits_burst => msto.ar_bits.burst,
io_out_0_ar_bits_lock => msto.ar_bits.lock,
io_out_0_ar_bits_cache => msto.ar_bits.cache,
io_out_0_ar_bits_prot => msto.ar_bits.prot,
io_out_0_ar_bits_qos => msto.ar_bits.qos,
io_out_0_r_ready => msto.r_ready,
io_out_0_r_valid => msti.r_valid,
io_out_0_r_bits_id => msti.r_id(3 downto 0),
io_out_0_r_bits_data => msti.r_data,
io_out_0_r_bits_resp => msti.r_resp,
io_out_0_r_bits_last => msti.r_last
);
msto.aw_bits.addr <= wb_aw_bits_addr(31 downto 3) & "000";
msto.ar_bits.addr <= wb_ar_bits_addr(31 downto 3) & "000";
end;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bg_low IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END bg_low;
ARCHITECTURE bg_low_arch OF bg_low IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bg_low_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bg_low_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bg_low_arch : ARCHITECTURE IS "bg_low,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bg_low_arch: ARCHITECTURE IS "bg_low,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bg_low.mif,C" &
"_INIT_FILE=bg_low.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=1092,C_READ_DEPTH_A=1092,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=10" &
"92,C_READ_DEPTH_B=1092,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BH" &
"V_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.5912999999999999 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bg_low.mif",
C_INIT_FILE => "bg_low.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 1092,
C_READ_DEPTH_A => 1092,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 1092,
C_READ_DEPTH_B => 1092,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.5912999999999999 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bg_low_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2602.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02602ent IS
END c13s03b01x00p02n01i02602ent;
ARCHITECTURE c13s03b01x00p02n01i02602arch OF c13s03b01x00p02n01i02602ent IS
BEGIN
TESTING: PROCESS
variable k, : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02602 - Identifier can not end with ','."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02602arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2602.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02602ent IS
END c13s03b01x00p02n01i02602ent;
ARCHITECTURE c13s03b01x00p02n01i02602arch OF c13s03b01x00p02n01i02602ent IS
BEGIN
TESTING: PROCESS
variable k, : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02602 - Identifier can not end with ','."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02602arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2602.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02602ent IS
END c13s03b01x00p02n01i02602ent;
ARCHITECTURE c13s03b01x00p02n01i02602arch OF c13s03b01x00p02n01i02602ent IS
BEGIN
TESTING: PROCESS
variable k, : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02602 - Identifier can not end with ','."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02602arch;
|
--!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
library misclib;
use misclib.types_misc.all;
entity axi4_flashspi is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
wait_while_write : boolean := true -- hold AXI bus response until end of write cycle
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_spi : in spi_in_type;
o_spi : out spi_out_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type );
end;
architecture arch_axi4_flashspi of axi4_flashspi is
constant xconfig : axi4_slave_config_type := (
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES,
irq_idx => conv_std_logic_vector(0, 8),
xaddr => conv_std_logic_vector(xaddr, CFG_SYSBUS_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_SYSBUS_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_SPI_FLASH
);
constant zero32 : std_logic_vector(31 downto 0) := (others => '0');
type state_type is (idle, wsetup, rsetup, txcmd, rbyte, wbyte, rd_complete, wr_complete, wr_accept);
type page_buf_type is array (0 to 31) of std_logic_vector(31 downto 0); --128 bytes
type registers is record
scaler : std_logic_vector(31 downto 0);
scaler_cnt : std_logic_vector(31 downto 0);
state : state_type;
rready : std_logic;
wready : std_logic;
-- Access to control registers always 4 bytes only
raddr : std_logic_vector(17 downto 2);
rdata : std_logic_vector(63 downto 0);
waddr : std_logic_vector(7 downto 2);
wdata : std_logic_vector(31 downto 0);
csn : std_logic;
sck : std_logic;
op64 : std_logic;
so_shifter : std_logic_vector(31 downto 0);
si_shifter : std_logic_vector(63 downto 0);
cmdbit_cnt : integer range 0 to 31;
databyte_cnt : integer range 0 to 255;
databyte_mask : std_logic_vector(6 downto 0);
wraccess : std_logic;
bytes_received : integer range 0 to 8;
buf_addr : std_logic_vector(6 downto 0);
end record;
constant R_RESET : registers := (
(others => '0'), (others => '0'), idle, -- scaler, scaler_cnt, state
'0', '0', -- rready, wready
(others => '0'), (others => '0'), -- raddr, rdata
(others => '0'), (others => '0'), -- waddr, wdata
'1', '0', '0', -- csn, sck, op64
(others => '0'), (others => '0'), -- so_shifter, si_shifter
0, 0, -- cmdbit_cnt, databyte_cnt
(others => '0'), '0', -- databyte_mask, wraccess
0, (others => '0') -- bytes_received, buf_addr
);
signal wb_page_addr : std_logic_vector(4 downto 0);
signal wb_page_rdata0 : std_logic_vector(31 downto 0);
signal wb_page_wdata0 : std_logic_vector(31 downto 0);
signal w_page_we0 : std_logic;
signal pagebuf0 : page_buf_type;
signal wb_page_rdata1 : std_logic_vector(31 downto 0);
signal wb_page_wdata1 : std_logic_vector(31 downto 0);
signal w_page_we1 : std_logic;
signal pagebuf1 : page_buf_type;
signal wb_bus_raddr : global_addr_array_type;
signal w_bus_re : std_logic;
signal wb_bus_waddr : global_addr_array_type;
signal w_bus_we : std_logic;
signal wb_bus_wstrb : std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
signal wb_bus_wdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
signal w_data_ready : std_logic;
signal r, rin : registers;
begin
axi0 : axi4_slave generic map (
async_reset => async_reset
) port map (
i_clk => clk,
i_nrst => nrst,
i_xcfg => xconfig,
i_xslvi => i_axi,
o_xslvo => o_axi,
i_ready => w_data_ready,
i_rdata => r.rdata,
o_re => w_bus_re,
o_r32 => open,
o_radr => wb_bus_raddr,
o_wadr => wb_bus_waddr,
o_we => w_bus_we,
o_wstrb => wb_bus_wstrb,
o_wdata => wb_bus_wdata
);
comblogic : process(nrst, i_spi, r, wb_page_rdata0, wb_page_rdata1,
w_bus_re, wb_bus_raddr, wb_bus_waddr, w_bus_we,
wb_bus_wstrb, wb_bus_wdata)
variable v : registers;
variable rdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
variable wstrb : std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable posedge_flag : std_logic;
variable negedge_flag : std_logic;
variable vb_page_addr_mux : std_logic_vector(4 downto 0);
variable vb_page_addr : std_logic_vector(4 downto 0);
variable vb_page_wdata0 : std_logic_vector(31 downto 0);
variable v_page_we0 : std_logic;
variable vb_page_wdata1 : std_logic_vector(31 downto 0);
variable v_page_we1 : std_logic;
begin
v := r;
vb_page_addr := (others => '0');
vb_page_wdata0 := (others => '0');
v_page_we0 := '0';
vb_page_wdata1 := (others => '0');
v_page_we1 := '0';
v.rready := '0';
v.wready := '0';
w_data_ready <= r.rready or r.wready;
-- system bus clock scaler to baudrate:
posedge_flag := '0';
negedge_flag := '0';
if r.scaler /= zero32 then
if r.csn = '1' then
v.scaler_cnt := zero32;
v.sck := '0';
elsif r.scaler_cnt = (r.scaler-1) then
v.scaler_cnt := zero32;
v.sck := not r.sck;
posedge_flag := not r.sck;
negedge_flag := r.sck;
else
v.scaler_cnt := r.scaler_cnt + 1;
end if;
end if;
case r.state is
when idle =>
v.so_shifter := (others => '0');
v.csn := '1';
v.sck := '0';
when rsetup =>
v.wraccess := '0';
v.bytes_received := 0;
if r.raddr(17) = '1' then
-- Control registers:
case conv_integer(r.raddr(16 downto 2)) is
when 0 =>
v.state := rd_complete;
v.si_shifter(31 downto 0) := r.scaler;
v.si_shifter(63 downto 32) := (others => '0');
v.bytes_received := 1; -- to avoid bytes swapping
when 4 => -- Read Flash STATUS
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 7;
v.databyte_cnt := 0;
v.databyte_mask := (others => '0'); -- Clear mask to enable 'rbyte' state
v.so_shifter := X"05000000";
v.si_shifter := (others => '0');
when 6 => -- Read Flash ID and Release from Deep Power-down
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 31;
v.databyte_cnt := 0; -- Read one Byte Manufacturer ID = 0x29
v.databyte_mask := (others => '0'); -- Clear mask to enable 'rbyte' state
v.so_shifter := X"AB000000";
v.si_shifter := (others => '0');
when others =>
v.state := rd_complete;
v.si_shifter := (others => '0');
end case;
else
-- Access to SPI
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 31;
if r.op64 = '1' then
v.databyte_cnt := 7;
else
v.databyte_cnt := 3;
end if;
v.databyte_mask := (others => '0');
-- [31:24] - command 0x3 = READ
-- [23:17] - ignored by flash
-- [16:0] - address
v.so_shifter := X"03" & "0000000" & r.raddr(16 downto 2) & "00";
end if;
when wsetup =>
-- Only control request. Write to page buffer doesn't get here:
v.wraccess := '1';
case conv_integer(r.waddr) is
when 0 =>
v.state := wr_complete;
v.scaler := r.wdata;
when 4 => -- Write Flash STATUS
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 15;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"01" & r.wdata(7 downto 0) & X"0000";
when 8 => -- Write Enable
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 7;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"06000000";
when 10 => -- Page Write
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 31;
v.databyte_cnt := 0;
v.databyte_mask := (others => '0'); -- Clear mask to enter 'wbyte' state
v.so_shifter := X"02" & r.wdata(23 downto 8) & X"00";
v.buf_addr := (others => '0');
when 12 => -- Write Disable
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 7;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"04000000";
when 14 => -- Page Erase
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 31;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"42" & r.wdata(23 downto 0);
when 16 => -- Sector Erase
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 31;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"D8" & r.wdata(23 downto 0);
when 18 => -- Chip Erase
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 7;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"C7000000";
when 20 => -- Deep Power-Down mode enable
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 7;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"B9000000";
when others =>
v.state := wr_complete;
end case;
when txcmd =>
if negedge_flag = '1' then
v.so_shifter := r.so_shifter(30 downto 0) & "0";
if r.cmdbit_cnt = 0 then
if r.databyte_mask = "0000000" then
if r.wraccess = '1' then
v.state := wbyte;
-- Transmit 256 bytes of page buffer starting from 0 offset
v.so_shifter := wb_page_rdata0(7 downto 0) & wb_page_rdata0(15 downto 8)
& wb_page_rdata0(23 downto 16) & wb_page_rdata0(31 downto 24);
v.buf_addr := r.buf_addr + 1;
v.databyte_cnt := 3;
else
v.state := rbyte;
end if;
else
if r.wraccess = '1' then
v.state := wr_complete;
else
v.state := rd_complete;
end if;
end if;
else
v.cmdbit_cnt := r.cmdbit_cnt - 1;
end if;
end if;
when rbyte =>
if posedge_flag = '1' then
v.si_shifter := r.si_shifter(62 downto 0) & i_spi.SDI;
v.databyte_mask := r.databyte_mask(5 downto 0) & '1';
if r.databyte_mask = "1111111" then
v.bytes_received := r.bytes_received + 1;
if r.databyte_cnt = 0 then
v.state := rd_complete;
else
v.databyte_cnt := r.databyte_cnt - 1;
v.databyte_mask := (others => '0');
end if;
end if;
end if;
when rd_complete =>
v.rready := '1'; -- End of access wait-states
if r.bytes_received = 8 then
v.rdata := r.si_shifter(7 downto 0) & r.si_shifter(15 downto 8)
& r.si_shifter(23 downto 16) & r.si_shifter(31 downto 24)
& r.si_shifter(39 downto 32) & r.si_shifter(47 downto 40)
& r.si_shifter(55 downto 48) & r.si_shifter(63 downto 56);
elsif r.bytes_received = 4 then
v.rdata := r.si_shifter(7 downto 0) & r.si_shifter(15 downto 8)
& r.si_shifter(23 downto 16) & r.si_shifter(31 downto 24)
& r.si_shifter(7 downto 0) & r.si_shifter(15 downto 8)
& r.si_shifter(23 downto 16) & r.si_shifter(31 downto 24);
else
v.rdata := r.si_shifter;
end if;
v.state := idle;
when wbyte =>
if negedge_flag = '1' then
v.so_shifter := r.so_shifter(30 downto 0) & "0";
v.databyte_mask := r.databyte_mask(5 downto 0) & '1';
if r.databyte_mask = "1111111" then
v.databyte_mask := (others => '0');
if r.databyte_cnt = 0 then
v.buf_addr := r.buf_addr + 1;
if conv_integer(r.buf_addr) = 64 then
v.state := wr_complete;
elsif r.buf_addr(0) = '1' then
v.databyte_cnt := 3;
v.so_shifter := wb_page_rdata1(7 downto 0) & wb_page_rdata1(15 downto 8)
& wb_page_rdata1(23 downto 16) & wb_page_rdata1(31 downto 24);
else
v.databyte_cnt := 3;
v.so_shifter := wb_page_rdata0(7 downto 0) & wb_page_rdata0(15 downto 8)
& wb_page_rdata0(23 downto 16) & wb_page_rdata0(31 downto 24);
end if;
else
v.databyte_cnt := r.databyte_cnt - 1;
end if;
end if;
end if;
when wr_complete =>
if wait_while_write then
v.wready := '1'; -- End of access wait-states
end if;
v.state := wr_accept;
v.csn := '1';
when wr_accept =>
-- To avoid re-accept the same write request
v.state := idle;
when others =>
end case;
if w_bus_re = '1' then
v.state := rsetup;
v.raddr := wb_bus_raddr(0)(17 downto 2);
if wb_bus_raddr(0)(2) = '1' then
v.op64 := '0';
else
v.op64 := '1';
end if;
end if;
-- Wait states: Read and Write transaction takes at least 1 wait state, except
-- 0 clocks (no wait states). Writing into page buffer
-- 1 clock. Read/Write control register without access to SPI Flash (scaler, example)
-- N clocks. When access to Flash, depending length of SPI sequence and scaler.
if w_bus_we = '1' then
wstrb := wb_bus_wstrb;
if wb_bus_waddr(0)(17) = '0' then
-- Write to page buffer
v.wready := '1'; -- No wait states needed
vb_page_addr := wb_bus_waddr(0)(7 downto 3);
if wb_bus_waddr(0)(2) = '0' then
-- 4 or 8 bytes
v_page_we0 := wstrb(3) or wstrb(2) or wstrb(1) or wstrb(0);
vb_page_wdata0 := wb_bus_wdata(31 downto 0);
v_page_we1 := wstrb(7) or wstrb(6) or wstrb(5) or wstrb(4);
vb_page_wdata1 := wb_bus_wdata(63 downto 32);
else
-- 4-bytes only
v_page_we0 := '0';
vb_page_wdata0 := (others => '0');
v_page_we1 := wstrb(3) or wstrb(2) or wstrb(1) or wstrb(0);
vb_page_wdata1 := wb_bus_wdata(31 downto 0);
end if;
elsif r.state = idle then
if not wait_while_write then
v.wready := '1';
end if;
v.state := wsetup;
-- Only 4-bytes access to control registers:
if wb_bus_waddr(0)(2) = '0' and wstrb = X"F0" then
v.waddr := wb_bus_waddr(1)(7 downto 2);
v.wdata := wb_bus_wdata(63 downto 32);
else
v.waddr := wb_bus_waddr(0)(7 downto 2);
v.wdata := wb_bus_wdata(31 downto 0);
end if;
end if;
end if;
if r.state = txcmd or r.state = wbyte then
vb_page_addr_mux := r.buf_addr(5 downto 1);
else
vb_page_addr_mux := vb_page_addr;
end if;
if not async_reset and nrst = '0' then
v := R_RESET;
end if;
rin <= v;
wb_page_addr <= vb_page_addr_mux;
wb_page_wdata0 <= vb_page_wdata0;
w_page_we0 <= v_page_we0;
wb_page_wdata1 <= vb_page_wdata1;
w_page_we1 <= v_page_we1;
end process;
cfg <= xconfig;
o_spi.SDO <= r.so_shifter(31);
o_spi.SCK <= r.sck;
o_spi.nCS <= r.csn;
o_spi.nWP <= '1';
o_spi.nHOLD <= '1';
o_spi.RESET <= '0';
reg : process (nrst, clk, wb_page_addr, w_page_we0, wb_page_wdata0,
w_page_we1, wb_page_wdata1)
begin
if nrst = '0' then
pagebuf0 <= (others => (others => '1'));
pagebuf1 <= (others => (others => '1'));
elsif rising_edge(clk) then
if w_page_we0 = '1' then
pagebuf0(conv_integer(wb_page_addr)) <= wb_page_wdata0;
end if;
if w_page_we1 = '1' then
pagebuf1(conv_integer(wb_page_addr)) <= wb_page_wdata1;
end if;
end if;
end process;
wb_page_rdata0 <= pagebuf0(conv_integer(wb_page_addr));
wb_page_rdata1 <= pagebuf1(conv_integer(wb_page_addr));
-- registers:
regs : process(nrst, clk)
begin
if async_reset and nrst = '0' then
r <= R_RESET;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc631.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:48 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:11 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:26 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00631ent IS
END c03s04b01x00p01n01i00631ent;
ARCHITECTURE c03s04b01x00p01n01i00631arch OF c03s04b01x00p01n01i00631ent IS
type byte is array (0 to 7) of bit;
type byte_file is file of byte;
constant C38 : byte := (others => '1');
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : byte_file open read_mode is "iofile.40";
variable v : byte;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C38) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00631"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00631 - File reading operation (byte file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00631arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc631.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:48 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:11 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:26 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00631ent IS
END c03s04b01x00p01n01i00631ent;
ARCHITECTURE c03s04b01x00p01n01i00631arch OF c03s04b01x00p01n01i00631ent IS
type byte is array (0 to 7) of bit;
type byte_file is file of byte;
constant C38 : byte := (others => '1');
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : byte_file open read_mode is "iofile.40";
variable v : byte;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C38) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00631"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00631 - File reading operation (byte file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00631arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc631.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:48 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:11 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:26 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00631ent IS
END c03s04b01x00p01n01i00631ent;
ARCHITECTURE c03s04b01x00p01n01i00631arch OF c03s04b01x00p01n01i00631ent IS
type byte is array (0 to 7) of bit;
type byte_file is file of byte;
constant C38 : byte := (others => '1');
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : byte_file open read_mode is "iofile.40";
variable v : byte;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C38) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00631"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00631 - File reading operation (byte file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00631arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1958.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01958ent IS
END c07s02b01x00p02n02i01958ent;
ARCHITECTURE c07s02b01x00p02n02i01958arch OF c07s02b01x00p02n02i01958ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := FALSE;
variable b : boolean := TRUE;
variable c : boolean;
BEGIN
c := a or b;
assert NOT(c=TRUE)
report "***PASSED TEST: c07s02b01x00p02n02i01958"
severity NOTE;
assert ( c=TRUE )
report "***FAILED TEST: c07s02b01x00p02n02i01958 - Logical operation of 'OR'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01958arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1958.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01958ent IS
END c07s02b01x00p02n02i01958ent;
ARCHITECTURE c07s02b01x00p02n02i01958arch OF c07s02b01x00p02n02i01958ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := FALSE;
variable b : boolean := TRUE;
variable c : boolean;
BEGIN
c := a or b;
assert NOT(c=TRUE)
report "***PASSED TEST: c07s02b01x00p02n02i01958"
severity NOTE;
assert ( c=TRUE )
report "***FAILED TEST: c07s02b01x00p02n02i01958 - Logical operation of 'OR'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01958arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1958.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01958ent IS
END c07s02b01x00p02n02i01958ent;
ARCHITECTURE c07s02b01x00p02n02i01958arch OF c07s02b01x00p02n02i01958ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := FALSE;
variable b : boolean := TRUE;
variable c : boolean;
BEGIN
c := a or b;
assert NOT(c=TRUE)
report "***PASSED TEST: c07s02b01x00p02n02i01958"
severity NOTE;
assert ( c=TRUE )
report "***FAILED TEST: c07s02b01x00p02n02i01958 - Logical operation of 'OR'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01958arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2943.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p07n04i02943ent IS
function F (i,j : integer) return integer;
-- Failure_here: Function body spec does not conform to declaration spec.
function F (i : integer; j : integer) return integer is
begin
return (i + j);
end;
END c02s02b00x00p07n04i02943ent;
ARCHITECTURE c02s02b00x00p07n04i02943arch OF c02s02b00x00p07n04i02943ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n04i02943 - Subprogram specification in package body does not conform to the subprogram specification of the declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n04i02943arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2943.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p07n04i02943ent IS
function F (i,j : integer) return integer;
-- Failure_here: Function body spec does not conform to declaration spec.
function F (i : integer; j : integer) return integer is
begin
return (i + j);
end;
END c02s02b00x00p07n04i02943ent;
ARCHITECTURE c02s02b00x00p07n04i02943arch OF c02s02b00x00p07n04i02943ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n04i02943 - Subprogram specification in package body does not conform to the subprogram specification of the declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n04i02943arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2943.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p07n04i02943ent IS
function F (i,j : integer) return integer;
-- Failure_here: Function body spec does not conform to declaration spec.
function F (i : integer; j : integer) return integer is
begin
return (i + j);
end;
END c02s02b00x00p07n04i02943ent;
ARCHITECTURE c02s02b00x00p07n04i02943arch OF c02s02b00x00p07n04i02943ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n04i02943 - Subprogram specification in package body does not conform to the subprogram specification of the declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n04i02943arch;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: BINARYZACJA_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BINARYZACJA_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BINARYZACJA_TB_PKG.ALL;
ENTITY BINARYZACJA_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BINARYZACJA_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BINARYZACJA_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= std_logic_vector_len("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (255 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"BINARYZACJA.mif",
DEFAULT_DATA,
8,
256);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.BINARYZACJA_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(3),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.BINARYZACJA_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 3 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<3)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: BINARYZACJA_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BINARYZACJA_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BINARYZACJA_TB_PKG.ALL;
ENTITY BINARYZACJA_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BINARYZACJA_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BINARYZACJA_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= std_logic_vector_len("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (255 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"BINARYZACJA.mif",
DEFAULT_DATA,
8,
256);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.BINARYZACJA_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(3),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.BINARYZACJA_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 3 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<3)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: BINARYZACJA_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BINARYZACJA_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BINARYZACJA_TB_PKG.ALL;
ENTITY BINARYZACJA_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BINARYZACJA_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BINARYZACJA_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= std_logic_vector_len("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (255 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"BINARYZACJA.mif",
DEFAULT_DATA,
8,
256);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.BINARYZACJA_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(3),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.BINARYZACJA_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 3 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<3)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: BINARYZACJA_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BINARYZACJA_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BINARYZACJA_TB_PKG.ALL;
ENTITY BINARYZACJA_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BINARYZACJA_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BINARYZACJA_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= std_logic_vector_len("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (255 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"BINARYZACJA.mif",
DEFAULT_DATA,
8,
256);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.BINARYZACJA_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(3),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.BINARYZACJA_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 3 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<3)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1888.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01888ent IS
END c07s01b00x00p08n01i01888ent;
ARCHITECTURE c07s01b00x00p08n01i01888arch OF c07s01b00x00p08n01i01888ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal ibus : cmd_bus(small_int);
signal s_int : small_int;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= ibus'right(small_int'(c07s01b00x00p08n01i01888arch)) after 5 ns;
-- architecture body name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01888 - Architecture body names are not permitted as primaries in a qualified expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01888arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1888.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01888ent IS
END c07s01b00x00p08n01i01888ent;
ARCHITECTURE c07s01b00x00p08n01i01888arch OF c07s01b00x00p08n01i01888ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal ibus : cmd_bus(small_int);
signal s_int : small_int;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= ibus'right(small_int'(c07s01b00x00p08n01i01888arch)) after 5 ns;
-- architecture body name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01888 - Architecture body names are not permitted as primaries in a qualified expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01888arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1888.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01888ent IS
END c07s01b00x00p08n01i01888ent;
ARCHITECTURE c07s01b00x00p08n01i01888arch OF c07s01b00x00p08n01i01888ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal ibus : cmd_bus(small_int);
signal s_int : small_int;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= ibus'right(small_int'(c07s01b00x00p08n01i01888arch)) after 5 ns;
-- architecture body name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01888 - Architecture body names are not permitted as primaries in a qualified expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01888arch;
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Miguel Angel
--
-- Create Date: 11:24:19 08/19/2015
-- Design Name:
-- Module Name: Full-Adder_Bit - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE Webpack 14.7
-- Description:
-- 1-bit full adder
--
-- Dependencies:
--
-- Revision: 1.0
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
-- library UNISIM;
-- use UNISIM.VComponents.all;
entity Full_Adder_Bit is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
c : in STD_LOGIC;
sout : out STD_LOGIC;
Cout : out STD_LOGIC
);
end Full_Adder_Bit;
architecture Behavioral of Full_Adder_Bit is
begin
-- 1-bit Adder definition
Sout <= A xor B xor c;
Cout <= (A and B) or (A and c) or (B and c);
end Behavioral;
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_sample_mul
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for generating mul envelope
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_sample_mul is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_sample_mul;
architecture Behavioral of hwt_sample_mul is
----------------------------------------------------------------
-- mulcomponent declarations
----------------------------------------------------------------
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_addrESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_mul : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMAddr_mul2: std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMData_mul : std_logic_vector(0 to 31); -- add to local ram
signal i_RAMData_mul : std_logic_vector(0 to 31); -- local ram to add
signal i_RAMData_mul2: std_logic_vector(0 to 31);
signal o_RAMWE_mul : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(0, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal refresh_state : std_logic;
signal process_state : integer range 0 to 2;
signal mul_data : signed(63 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant add_START : std_logic_vector(31 downto 0) := x"0000000F";
constant add_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
--o_RAMData_mul <= std_logic_vector(mul_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_addrESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_addrESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_mul = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_mul))) := o_RAMData_mul;
else -- else needed, because add is consuming samples
i_RAMData_mul <= local_ram(to_integer(unsigned(o_RAMAddr_mul)));
i_RAMData_mul2<= local_ram(to_integer(unsigned(o_RAMAddr_mul2)));
end if;
end if;
end process;
add_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(0, 16);
osif_ctrl_signal <= (others => '0');
o_RAMWE_mul<= '0';
o_RAMAddr_mul <= (others => '0');
o_RAMAddr_mul2 <= std_logic_vector(to_signed(C_MAX_SAMPLE_COUNT,o_RAMAddr_mul2'length));
refresh_state <= '0';
done := False;
elsif rising_edge(clk) then
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = add_START then
sample_count <= to_unsigned(0, 16);
state <= STATE_REFRESH_INPUT;
elsif osif_ctrl_signal = add_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_INPUT =>
-- Refresh your signals
case refresh_state is
when '0' =>
memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.source_addr, X"00000000", std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
if done then
refresh_state <= '1';
end if;
when '1' =>
memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.opt_arg_addr, std_logic_vector(to_unsigned(C_MAX_SAMPLE_COUNT,32)), std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
if done then
refresh_state <= '0';
state <= STATE_PROCESS;
end if;
when others =>
refresh_state <= '0';
end case;
when STATE_PROCESS =>
if sample_count < to_unsigned(C_MAX_SAMPLE_COUNT, 16) then
case process_state is
when 0 =>
mul_data <= signed(i_RAMData_mul) * signed(i_RAMData_mul2);
process_state <= 1;
when 1 =>
o_RAMData_mul <= std_logic_vector(resize(mul_data(31 downto 0), 32));
o_RAMWE_mul <= '1';
process_state <= 0;
when 2 =>
o_RAMWE_mul <= '0';
o_RAMAddr_mul <= std_logic_vector(unsigned(o_RAMAddr_mul) + 1);
o_RAMAddr_mul2 <= std_logic_vector(unsigned(o_RAMAddr_mul2) + 1);
sample_count <= sample_count + 1;
process_state <= 0;
end case;
else
-- Samples have been generated
o_RAMAddr_mul <= (others => '0');
o_RAMAddr_mul2 <= (others => '0');
sample_count <= to_unsigned(0, 16);
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_addr std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package caph_flow_pkg is
constant MAX_IMAGE_WIDTH : integer := 1920;
constant MAX_IMAGE_HEIGHT : integer := 1024;
-- start of Frame & start of Line has same vhdl header
-- End of Frame/Line too ...
constant SoF:integer := 0;
constant EoF:integer := 1;
constant SoL : integer := 0;
constant EoL : integer := 1;
constant Data:integer:= 2;
constant TOKEN_HEADER_SIZE:integer :=2;
-- codage des headers caph
type my_caph_header_t is array (0 to 2) of std_logic_vector(1 downto 0);
constant CaphHeader : my_caph_header_t := ("01","10","11");
-- Must match caph_toplevel instanciation parameter ...
constant MEM_ADDR_BUS_SIZE: integer := 4;
type caph_port_t is
record
data : std_logic_vector(31 downto 0);
wr : std_logic;
full : std_logic;
end record;
constant NB_PORTS : integer := 10;
type caph_ports_t is array (0 to NB_PORTS-1) of caph_port_t;
end package caph_flow_pkg;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity Shifter is
generic (N : integer := 16);
port (A : in std_logic_vector(N-1 downto 0);
B : out std_logic_vector(N-1 downto 0);
C : out std_logic_vector(N-1 downto 0);
D : out std_logic_vector(N-1 downto 0);
E : out std_logic_vector(N-1 downto 0)
);
end Shifter;
architecture Behavioral of Shifter is
begin
B <= A; -- A
C <= not(A) + 1; -- -A
D(N-1 downto 1) <= A(N-2 downto 0); -- 2A
D(0) <= '0';
process(A) -- -2A
variable var : std_logic_vector(N-1 downto 0);
begin
var := not(A) + 1;
E(N-1 downto 1) <= var(N-2 downto 0);
E(0) <= '0';
end process;
end Behavioral;
|
package mypkg is
constant msg : string := "Message from mylib.mypkg";
end mypkg;
|
package mypkg is
constant msg : string := "Message from mylib.mypkg";
end mypkg;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_channel is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 5;
Rxy_rst : integer := 60;
Cx_rst : integer := 15;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
DCTS : in std_logic;
DRTS : in std_logic;
RTS : out std_logic;
CTS : out std_logic;
flit_type : in std_logic_vector(2 downto 0);
destination_address : in std_logic_vector(NoC_size-1 downto 0);
Grant_N_in , Grant_E_in , Grant_W_in , Grant_S_in , Grant_L_in : in std_logic;
Grant_N_out, Grant_E_out, Grant_W_out, Grant_S_out, Grant_L_out: out std_logic;
Req_N_in , Req_E_in , Req_W_in , Req_S_in , Req_L_in :in std_logic;
Req_N_out , Req_E_out, Req_W_out, Req_S_out, Req_L_out:out std_logic;
read_pointer_out, write_pointer_out: out std_logic_vector(3 downto 0);
write_en_out :out std_logic;
Xbar_sel: out std_logic_vector(4 downto 0)
);
end router_channel;
architecture behavior of router_channel is
COMPONENT FIFO is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
read_pointer_out, write_pointer_out: out std_logic_vector(3 downto 0);
write_en_out :out std_logic;
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
--err_CTS_in,
err_write_en,
err_not_CTS_in,
--err_not_write_en,
err_read_en_mismatch : out std_logic
);
end COMPONENT;
COMPONENT Arbiter
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
-- Checker outputs
--err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end COMPONENT;
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal empty: std_logic;
-- Signals related to Checkers
-- LBDR Checkers signals
-- North
signal N_err_header_empty_Requests_FF_Requests_in,
N_err_tail_Requests_in_all_zero,
N_err_header_tail_Requests_FF_Requests_in,
N_err_dst_addr_cur_addr_N1,
N_err_dst_addr_cur_addr_not_N1,
N_err_dst_addr_cur_addr_E1,
N_err_dst_addr_cur_addr_not_E1,
N_err_dst_addr_cur_addr_W1,
N_err_dst_addr_cur_addr_not_W1,
N_err_dst_addr_cur_addr_S1,
N_err_dst_addr_cur_addr_not_S1,
N_err_dst_addr_cur_addr_not_Req_L_in,
N_err_dst_addr_cur_addr_Req_L_in,
N_err_header_not_empty_Req_N_in,
N_err_header_not_empty_Req_E_in,
N_err_header_not_empty_Req_W_in,
N_err_header_not_empty_Req_S_in : std_logic;
-- Arbiter Checkers signals
-- North
signal N_err_state_IDLE_xbar,
N_err_state_not_IDLE_xbar,
N_err_state_IDLE_RTS_FF_in,
N_err_state_not_IDLE_RTS_FF_RTS_FF_in,
N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
N_err_RTS_FF_not_DCTS_state_state_in,
N_err_not_RTS_FF_state_in_next_state,
N_err_RTS_FF_DCTS_state_in_next_state,
N_err_not_DCTS_Grants,
N_err_DCTS_not_RTS_FF_Grants,
N_err_DCTS_RTS_FF_IDLE_Grants,
N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
N_err_Requests_next_state_IDLE,
N_err_IDLE_Req_L,
N_err_Local_Req_L,
N_err_North_Req_N,
N_err_IDLE_Req_N,
N_err_Local_Req_N,
N_err_South_Req_L,
N_err_West_Req_L,
N_err_South_Req_N,
N_err_East_Req_L,
N_err_West_Req_N,
N_err_East_Req_N,
N_err_next_state_onehot,
N_err_state_in_onehot,
N_err_state_north_xbar_sel,
N_err_state_east_xbar_sel,
N_err_state_west_xbar_sel,
N_err_state_south_xbar_sel : std_logic;
-- FIFO Control Part Checkers signals
-- North
signal N_err_write_en_write_pointer,
N_err_not_write_en_write_pointer,
N_err_read_pointer_write_pointer_not_empty,
N_err_read_pointer_write_pointer_empty,
N_err_read_pointer_write_pointer_not_full,
N_err_read_pointer_write_pointer_full,
N_err_read_pointer_increment,
N_err_read_pointer_not_increment,
N_err_write_en,
N_err_not_CTS_in,
N_err_read_en_mismatch : std_logic;
-- Error Signals for each module (ORed combination of checker outputs)
signal N_LBDR_checkers_output: std_logic;
signal N_Arbiter_checkers_output: std_logic;
signal N_FIFO_control_part_checkers_output: std_logic;
begin
-- OR of checker outputs for each module (corresponding to each direction)
-- This is used for feeding the checker outputs to shift registers (later)
-- LBDR
N_LBDR_checkers_output <= N_err_header_empty_Requests_FF_Requests_in or
N_err_tail_Requests_in_all_zero or
N_err_header_tail_Requests_FF_Requests_in or
N_err_dst_addr_cur_addr_N1 or
N_err_dst_addr_cur_addr_not_N1 or
N_err_dst_addr_cur_addr_E1 or
N_err_dst_addr_cur_addr_not_E1 or
N_err_dst_addr_cur_addr_W1 or
N_err_dst_addr_cur_addr_not_W1 or
N_err_dst_addr_cur_addr_S1 or
N_err_dst_addr_cur_addr_not_S1 or
N_err_dst_addr_cur_addr_not_Req_L_in or
N_err_dst_addr_cur_addr_Req_L_in or
N_err_header_not_empty_Req_N_in or
N_err_header_not_empty_Req_E_in or
N_err_header_not_empty_Req_W_in or
N_err_header_not_empty_Req_S_in;
-- Arbiter
N_Arbiter_checkers_output <= N_err_state_IDLE_xbar or
N_err_state_not_IDLE_xbar or
N_err_state_IDLE_RTS_FF_in or
N_err_state_not_IDLE_RTS_FF_RTS_FF_in or
N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in or
N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in or
N_err_RTS_FF_not_DCTS_state_state_in or
N_err_not_RTS_FF_state_in_next_state or
N_err_RTS_FF_DCTS_state_in_next_state or
N_err_not_DCTS_Grants or
N_err_DCTS_not_RTS_FF_Grants or
N_err_DCTS_RTS_FF_IDLE_Grants or
N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot or
N_err_Requests_next_state_IDLE or
N_err_IDLE_Req_L or
N_err_Local_Req_L or
N_err_North_Req_N or
N_err_IDLE_Req_N or
N_err_Local_Req_N or
N_err_South_Req_L or
N_err_West_Req_L or
N_err_South_Req_N or
N_err_East_Req_L or
N_err_West_Req_N or
N_err_East_Req_N or
N_err_next_state_onehot or
N_err_state_in_onehot or
N_err_state_north_xbar_sel or
N_err_state_east_xbar_sel or
N_err_state_west_xbar_sel or
N_err_state_south_xbar_sel;
-- FIFO Control Part
N_FIFO_control_part_checkers_output <= N_err_write_en_write_pointer or
N_err_not_write_en_write_pointer or
N_err_read_pointer_write_pointer_not_empty or
N_err_read_pointer_write_pointer_empty or
N_err_read_pointer_write_pointer_not_full or
N_err_read_pointer_write_pointer_full or
N_err_read_pointer_increment or
N_err_read_pointer_not_increment or
N_err_write_en or
N_err_not_CTS_in or
N_err_read_en_mismatch;
------------------------------------------------------------------------------------------------------------------------------
-- all the FIFOs
FIFO_unit: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, DRTS => DRTS,
read_en_N => Grant_N_in, read_en_E =>Grant_E_in, read_en_W =>Grant_W_in, read_en_S =>Grant_S_in, read_en_L =>Grant_L_in,
CTS => CTS, empty_out => empty,
read_pointer_out => read_pointer_out, write_pointer_out => write_pointer_out,
write_en_out => write_en_out,
err_write_en_write_pointer => N_err_write_en_write_pointer,
err_not_write_en_write_pointer => N_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => N_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => N_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => N_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => N_err_read_pointer_write_pointer_full,
err_read_pointer_increment => N_err_read_pointer_increment,
err_read_pointer_not_increment => N_err_read_pointer_not_increment,
err_write_en => N_err_write_en,
err_not_CTS_in => N_err_not_CTS_in,
err_read_en_mismatch => N_err_read_en_mismatch
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_unit: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty, flit_type => flit_type, dst_addr=> destination_address,
Req_N=> Req_N_out, Req_E=>Req_E_out, Req_W=>Req_W_out, Req_S=>Req_S_out, Req_L=>Req_L_out,
err_header_empty_Requests_FF_Requests_in => N_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => N_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => N_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => N_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => N_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => N_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => N_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => N_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => N_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => N_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => N_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => N_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => N_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => N_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => N_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => N_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => N_err_header_not_empty_Req_S_in
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Arbiters
Arbiter_unit: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_N_in , Req_E => Req_E_in, Req_W => Req_W_in, Req_S => Req_S_in, Req_L => Req_L_in,
DCTS => DCTS, Grant_N => Grant_N_out, Grant_E => Grant_E_out, Grant_W => Grant_W_out, Grant_S => Grant_S_out, Grant_L => Grant_L_out,
Xbar_sel => Xbar_sel,
RTS => RTS,
err_state_IDLE_xbar => N_err_state_IDLE_xbar ,
err_state_not_IDLE_xbar => N_err_state_not_IDLE_xbar ,
err_state_IDLE_RTS_FF_in => N_err_state_IDLE_RTS_FF_in ,
err_state_not_IDLE_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in ,
err_RTS_FF_not_DCTS_state_state_in => N_err_RTS_FF_not_DCTS_state_state_in ,
err_not_RTS_FF_state_in_next_state => N_err_not_RTS_FF_state_in_next_state ,
err_RTS_FF_DCTS_state_in_next_state => N_err_RTS_FF_DCTS_state_in_next_state ,
err_not_DCTS_Grants => N_err_not_DCTS_Grants ,
err_DCTS_not_RTS_FF_Grants => N_err_DCTS_not_RTS_FF_Grants ,
err_DCTS_RTS_FF_IDLE_Grants => N_err_DCTS_RTS_FF_IDLE_Grants ,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot ,
err_Requests_next_state_IDLE => N_err_Requests_next_state_IDLE ,
err_IDLE_Req_L => N_err_IDLE_Req_L ,
err_Local_Req_L => N_err_Local_Req_L ,
err_North_Req_N => N_err_North_Req_N ,
err_IDLE_Req_N => N_err_IDLE_Req_N ,
err_Local_Req_N => N_err_Local_Req_N ,
err_South_Req_L => N_err_South_Req_L ,
err_West_Req_L => N_err_West_Req_L ,
err_South_Req_N => N_err_South_Req_N ,
err_East_Req_L => N_err_East_Req_L ,
err_West_Req_N => N_err_West_Req_N ,
err_East_Req_N => N_err_East_Req_N ,
err_next_state_onehot => N_err_next_state_onehot ,
err_state_in_onehot => N_err_state_in_onehot ,
err_state_north_xbar_sel => N_err_state_north_xbar_sel ,
err_state_east_xbar_sel => N_err_state_east_xbar_sel ,
err_state_west_xbar_sel => N_err_state_west_xbar_sel ,
err_state_south_xbar_sel => N_err_state_south_xbar_sel
);
end;
|
-------------------------------------------------------------------------------
-- $Id: qspi_occupancy_reg.vhd
-------------------------------------------------------------------------------
-- qspi_occupancy_reg.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_occupancy_reg.vhd
-- Version: v3.0
-- Description: Serial Peripheral Interface (SPI) Module for interfacing
-- with a 32-bit AXI4 Bus.Defines logic for occupancy regist
-- -er.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_spi.
--
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-- Author: SK
-- ~~~~~~
-- - Redesigned version of axi_quad_spi.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_DBUS_WIDTH -- Width of the slave data bus
-- C_OCCUPANCY_NUM_BITS -- Number of bits in occupancy count
-- C_NUM_BITS_REG -- Width of SPI registers
-- C_NUM_TRANSFER_BITS -- SPI Serial transfer width.
-- Can be 8, 16 or 32 bit wide
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Reset -- Reset Signal
-- SLAVE ATTACHMENT INTERFACE
--===========================
-- Bus2IP_OCC_REG_RdCE -- Read CE for occupancy register
-- SPIXfer_done -- SPI transfer done flag
-- FIFO INTERFACE
-- IP2Reg_OCC_Data -- Occupancy data read from FIFO
-- IP2Bus_OCC_REG_Data -- Data to be send on the bus
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_occupancy_reg is
generic
(
C_OCCUPANCY_NUM_BITS: integer-- --Number of bits in occupancy count
);
port
(
-- Slave attachment ports
Bus2IP_OCC_REG_RdCE : in std_logic;
IP2Reg_OCC_Data : in std_logic_vector(0 to (C_OCCUPANCY_NUM_BITS-1));
IP2Bus_OCC_REG_Data : out std_logic_vector(0 to (C_OCCUPANCY_NUM_BITS-1))
);
end qspi_occupancy_reg;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of qspi_occupancy_reg is
-------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
begin
-----
-- OCCUPANCY_REG_RD_GENERATE : Occupancy Register Read Generate
-------------------------------
OCCUPANCY_REG_RD_GENERATE: for j in 0 to C_OCCUPANCY_NUM_BITS-1 generate
begin
IP2Bus_OCC_REG_Data(j) <= IP2Reg_OCC_Data(C_OCCUPANCY_NUM_BITS-1-j) and
Bus2IP_OCC_REG_RdCE;
end generate OCCUPANCY_REG_RD_GENERATE;
end imp;
--------------------------------------------------------------------------------
|
-- Copyright (c) 2013 Nuand LLC
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use ieee.math_complex.all ;
library nuand ;
use nuand.util.all ;
entity fx3_model is
port (
fx3_pclk : buffer std_logic := '1' ;
fx3_gpif : inout std_logic_vector(31 downto 0) ;
fx3_ctl : inout std_logic_vector(12 downto 0) ;
fx3_uart_rxd : in std_logic ;
fx3_uart_txd : buffer std_logic ;
fx3_uart_cts : buffer std_logic ;
fx3_rx_en : in std_logic ;
fx3_rx_meta_en : in std_logic ;
fx3_tx_en : in std_logic ;
fx3_tx_meta_en : in std_logic
) ;
end entity ; -- fx3_model
architecture dma of fx3_model is
constant PCLK_HALF_PERIOD : time := 1 sec * (1.0/100.0e6/2.0) ;
-- Control mapping
-- alias dma0_rx_ack is fx3_ctl( 0) ;
-- alias dma1_rx_ack is fx3_ctl( 1) ;
-- alias dma2_tx_ack is fx3_ctl( 2) ;
-- alias dma3_tx_ack is fx3_ctl( 3) ;
-- alias dma_rx_enable is fx3_ctl( 4) ;
-- alias dma_tx_enable is fx3_ctl( 5) ;
-- alias dma_idle is fx3_ctl( 6) ;
-- alias system_reset is fx3_ctl( 7) ;
-- alias dma0_rx_reqx is fx3_ctl( 8) ;
-- alias dma1_rx_reqx is fx3_ctl(12) ; -- due to 9 being connected to dclk
-- alias dma2_tx_reqx is fx3_ctl(10) ;
-- alias dma3_tx_reqx is fx3_ctl(11) ;
type gpif_state_t is (IDLE, TX_SAMPLES, RX_SAMPLES) ;
signal gpif_state : gpif_state_t ;
begin
-- DCLK which isn't used
fx3_ctl(9) <= '0' ;
-- Create a 100MHz clock output
fx3_pclk <= not fx3_pclk after PCLK_HALF_PERIOD ;
rx_sample_stream : process
constant BLOCK_SIZE : natural := 512 ;
variable count : natural := 0 ;
begin
-- dma0_rx_reqx <= '1' ;
fx3_ctl (8) <= '1' ;
-- dma1_rx_reqx <= '1' ;
fx3_ctl (12) <= '1' ;
-- dma_rx_enable <= '0' ;
fx3_ctl (4) <= '0' ;
-- wait until rising_edge(fx3_pclk) and system_reset = '0' ;
wait until rising_edge(fx3_pclk) and fx3_ctl (7) = '0' ;
for i in 1 to 10 loop
wait until rising_edge( fx3_pclk ) ;
end loop ;
if( fx3_rx_en = '0' ) then
wait;
end if;
wait for 30 us;
-- dma_rx_enable <= '1' ;
fx3_ctl (4) <= '1' ;
while true loop
for i in 0 to 2 loop
-- dma0_rx_reqx <= '0' ;
fx3_ctl (8) <= '0' ;
-- wait until rising_edge( fx3_pclk ) and dma0_rx_ack = '1' ;
wait until rising_edge( fx3_pclk ) and fx3_ctl (0) = '1' ;
wait until rising_edge( fx3_pclk ) ;
wait until rising_edge( fx3_pclk ) ;
-- dma0_rx_reqx <= '1' ;
fx3_ctl (8) <= '1' ;
for i in 1 to BLOCK_SIZE loop
wait until rising_edge( fx3_pclk ) ;
end loop ;
end loop ;
-- dma_rx_enable <= '0' ;
fx3_ctl (4) <= '0' ;
for i in 0 to 5000 loop
wait until rising_edge(fx3_pclk) ;
end loop ;
-- dma_rx_enable <= '1' ;
fx3_ctl (4) <= '1' ;
for i in 0 to 10 loop
wait until rising_edge(fx3_pclk);
end loop ;
end loop ;
report "Done with RX sample stream" ;
wait ;
end process ;
tx_sample_stream : process
constant BLOCK_SIZE : natural := 512 ;
variable count : natural := 0 ;
variable timestamp_cntr : natural := 80;
variable header_len : natural := 0;
begin
-- dma2_tx_reqx <= '1' ;
fx3_ctl (10) <= '1' ;
-- dma3_tx_reqx <= '1' ;
fx3_ctl (11) <= '1' ;
-- dma_tx_enable <= '0' ;
fx3_ctl (5) <= '0' ;
fx3_gpif <= (others =>'Z') ;
-- wait until system_reset = '0' ;
wait until fx3_ctl (7) = '0' ;
for i in 0 to 1000 loop
wait until rising_edge( fx3_pclk ) ;
end loop ;
if( fx3_tx_en = '0' ) then
wait;
end if;
wait for 120 us;
-- dma_tx_enable <= '1' ;
fx3_ctl (5) <= '1' ;
for i in 0 to 3 loop
-- dma3_tx_reqx <= '0' ;
fx3_ctl (11) <= '0' ;
-- wait until rising_edge( fx3_pclk ) and dma3_tx_ack = '1' ;
wait until rising_edge( fx3_pclk ) and fx3_ctl (3) = '1' ;
wait until rising_edge( fx3_pclk ) ;
wait until rising_edge( fx3_pclk ) ;
-- dma3_tx_reqx <= '1' ;
fx3_ctl (11) <= '1' ;
if( fx3_tx_meta_en = '1') then
for i in 1 to 4 loop
if (i = 1 ) then
fx3_gpif <= x"12341234";
elsif (i = 3 ) then
fx3_gpif <= (others => '0');
elsif(i = 4) then
fx3_gpif <= (others => '1');
elsif (i = 2) then
fx3_gpif(31 downto 0) <= std_logic_vector(to_signed(timestamp_cntr, 32));
timestamp_cntr := timestamp_cntr + 508 * 2;
end if;
wait until rising_edge( fx3_pclk );
end loop;
header_len := 4;
else
header_len := 0;
end if;
for i in 1 to BLOCK_SIZE - header_len loop
fx3_gpif(31 downto 16) <= std_logic_vector(to_signed(count, 16)) ;
fx3_gpif(15 downto 0) <= std_logic_vector(to_signed(-count, 16)) ;
count := (count + 1) mod 2048 ;
wait until rising_edge( fx3_pclk );
end loop ;
fx3_gpif <= (others =>'Z');
for i in 1 to 10 loop
wait until rising_edge( fx3_pclk );
end loop ;
end loop ;
report "Done with TX sample stream" ;
wait ;
end process ;
reset_system : process
begin
-- system_reset <= '1' ;
fx3_ctl (7) <= '1' ;
-- dma_idle <= '0' ;
fx3_ctl (6) <= '0' ;
nop( fx3_pclk, 100 ) ;
-- system_reset <= '0' ;
fx3_ctl (7) <= '0' ;
nop( fx3_pclk, 10 ) ;
-- dma_idle <= '1' ;
fx3_ctl (6) <= '1' ;
wait ;
end process ;
-- TODO: UART Interface
fx3_uart_txd <= '1' ;
fx3_uart_cts <= '1' ;
end architecture ; -- dma
architecture inband_scheduler of fx3_model is
begin
end architecture ; -- inband_scheduler
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Multiplexer_3x16 is
Port ( Selector : in STD_LOGIC_VECTOR (2 downto 0);
input_A, input_B, input_C, input_D, input_E, input_F, input_G, input_H: in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end Multiplexer_3x16;
architecture skeleton of Multiplexer_3x16 is
begin
with Selector select
output <= input_A when "000",
input_B when "001",
input_C when "010",
input_D when "011",
input_E when "100",
input_F when "101",
input_G when "110",
input_H when others;
end skeleton; |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_145 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end mul_145;
architecture augh of mul_145 is
signal tmp_res : signed(95 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
output <= std_logic_vector(tmp_res(63 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_145 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end mul_145;
architecture augh of mul_145 is
signal tmp_res : signed(95 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
output <= std_logic_vector(tmp_res(63 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_145 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end mul_145;
architecture augh of mul_145 is
signal tmp_res : signed(95 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
output <= std_logic_vector(tmp_res(63 downto 0));
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2482.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s03b03x00p01n01i02482pkg is
function uno return natural;
constant a_bit : bit_vector (uno to uno) := ( uno => '1' );
end c07s03b03x00p01n01i02482pkg;
package body c07s03b03x00p01n01i02482pkg is
function uno return natural is
begin
return 1;
end uno;
end c07s03b03x00p01n01i02482pkg;
ENTITY c07s03b03x00p01n01i02482ent IS
END c07s03b03x00p01n01i02482ent;
ARCHITECTURE c07s03b03x00p01n01i02482arch OF c07s03b03x00p01n01i02482ent IS
BEGIN
TESTING: PROCESS
BEGIN
uno;
assert FALSE
report "***FAILED TEST: c07s03b03x00p01n01i02482 - Function body is not defined."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p01n01i02482arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2482.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s03b03x00p01n01i02482pkg is
function uno return natural;
constant a_bit : bit_vector (uno to uno) := ( uno => '1' );
end c07s03b03x00p01n01i02482pkg;
package body c07s03b03x00p01n01i02482pkg is
function uno return natural is
begin
return 1;
end uno;
end c07s03b03x00p01n01i02482pkg;
ENTITY c07s03b03x00p01n01i02482ent IS
END c07s03b03x00p01n01i02482ent;
ARCHITECTURE c07s03b03x00p01n01i02482arch OF c07s03b03x00p01n01i02482ent IS
BEGIN
TESTING: PROCESS
BEGIN
uno;
assert FALSE
report "***FAILED TEST: c07s03b03x00p01n01i02482 - Function body is not defined."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p01n01i02482arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2482.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s03b03x00p01n01i02482pkg is
function uno return natural;
constant a_bit : bit_vector (uno to uno) := ( uno => '1' );
end c07s03b03x00p01n01i02482pkg;
package body c07s03b03x00p01n01i02482pkg is
function uno return natural is
begin
return 1;
end uno;
end c07s03b03x00p01n01i02482pkg;
ENTITY c07s03b03x00p01n01i02482ent IS
END c07s03b03x00p01n01i02482ent;
ARCHITECTURE c07s03b03x00p01n01i02482arch OF c07s03b03x00p01n01i02482ent IS
BEGIN
TESTING: PROCESS
BEGIN
uno;
assert FALSE
report "***FAILED TEST: c07s03b03x00p01n01i02482 - Function body is not defined."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p01n01i02482arch;
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library ieee;
use ieee.std_logic_1164.all;
entity mul32 is
port ( a : in std_logic_vector (31 downto 0);
b : in std_logic_vector (31 downto 0);
p : out std_logic_vector (31 downto 0));
end mul32;
architecture Behavioral of mul32 is
component badd32
port ( a : in std_logic_vector(2 downto 0);
b : in std_logic_vector(31 downto 0);
sum_in : in std_logic_vector(31 downto 0);
sum_out : out std_logic_vector(31 downto 0);
prod : out std_logic_vector(1 downto 0));
end component badd32;
signal zer : std_logic_vector(31 downto 0) := x"00000000"; -- zeros
signal mul0: std_logic_vector(2 downto 0);
type ary is array(0 to 15) of std_logic_vector(31 downto 0);
signal s : ary; -- temp sums
begin
mul0 <= a(1 downto 0) & '0';
a0: badd32 port map(mul0, b, zer, s(0 ), p(1 downto 0));
a1: badd32 port map(a(3 downto 1 ), b, s(0 ), s(1 ), p(3 downto 2));
a2: badd32 port map(a(5 downto 3 ), b, s(1 ), s(2 ), p(5 downto 4));
a3: badd32 port map(a(7 downto 5 ), b, s(2 ), s(3 ), p(7 downto 6));
a4: badd32 port map(a(9 downto 7 ), b, s(3 ), s(4 ), p(9 downto 8));
a5: badd32 port map(a(11 downto 9 ), b, s(4 ), s(5 ), p(11 downto 10));
a6: badd32 port map(a(13 downto 11), b, s(5 ), s(6 ), p(13 downto 12));
a7: badd32 port map(a(15 downto 13), b, s(6 ), s(7 ), p(15 downto 14));
a8: badd32 port map(a(17 downto 15), b, s(7 ), s(8 ), p(17 downto 16));
a9: badd32 port map(a(19 downto 17), b, s(8 ), s(9 ), p(19 downto 18));
a10:badd32 port map(a(21 downto 19), b, s(9 ), s(10), p(21 downto 20));
a11:badd32 port map(a(23 downto 21), b, s(10), s(11), p(23 downto 22));
a12:badd32 port map(a(25 downto 23), b, s(11), s(12), p(25 downto 24));
a13:badd32 port map(a(27 downto 25), b, s(12), s(13), p(27 downto 26));
a14:badd32 port map(a(29 downto 27), b, s(13), s(14), p(29 downto 28));
a15:badd32 port map(a(31 downto 29), b, s(14), open , p(31 downto 30));
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity audio_dac_8bit is
Port ( clk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (8 downto 0);
pulseStream : out STD_LOGIC);
end audio_dac_8bit;
architecture Behavioral of audio_dac_8bit is
signal sum : STD_LOGIC_VECTOR (9 downto 0) := (others =>'0');
begin
pulseStream <= sum(9);
process (clk) begin
if rising_edge(clk) then
sum <= ("0" & sum(8 downto 0)) + ("0" &data);
end if;
end process;
end Behavioral;
|
library IEEE;
use ieee.std_logic_1164.all;
entity two_to_one_mux is
port(
a, b : in std_logic_vector(31 downto 0);
sel : in std_logic;
output : out std_logic_vector(31 downto 0)
);
end entity two_to_one_mux;
architecture behav of two_to_one_mux is
begin
--output <= (a and (not sel)) or (b and sel);
output <= a when (sel = '0') else b;
end behav; |
entity tc7 is
end;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tc7 is
signal clk : std_logic;
signal tg : std_logic;
begin
process (clk) is
begin
if ?? falling_edge(clk) and (tg) then
null;
end if;
end process;
end behav;
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